TEWS TPMC813 LON Interface User Manual
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The Embedded I/O Company
TPMC813
LON Interface
Version 1.0
User Manual
Issue 1.2
September 2006
D76813800
TEWS TECHNOLOGIES GmbH
Am Bahnhof 7
25469 Halstenbek, Germany www.tews.com
Phone: +49-(0)4101-4058-0
Fax: +49-(0)4101-4058-19 e-mail: [email protected]
TEWS TECHNOLOGIES LLC
9190 Double Diamond Parkway,
Suite 127, Reno, NV 89521, USA www.tews.com
Phone: +1 (775) 850 5830
Fax: +1 (775) 201 0347 e-mail: [email protected]
TPMC813-10
LON interface RS485
TPMC813-30
LON interface FTT-10A
This document contains information, which is proprietary to TEWS TECHNOLOGIES GmbH. Any reproduction without written permission is forbidden.
TEWS TECHNOLOGIES GmbH has made any effort to ensure that this manual is accurate and complete. However TEWS TECHNOLOGIES GmbH reserves the right to change the product described in this document at any time without notice.
TEWS TECHNOLOGIES GmbH is not liable for any damage arising out of the application or use of the device described herein.
Style Conventions
Hexadecimal characters are specified with prefix 0x, i.e. 0x029E (that means hexadecimal value 029E).
For signals on hardware products, an ‚Active Low’ is represented by the signal name with # following, i.e.
IP_RESET#.
Access terms are described as:
R/W Read/Write
R/C Read/Clear
R/S Read/Set
2000-2006 by TEWS TECHNOLOGIES GmbH
TPMC813User Manual Issue 1.2 Page 2 of 20
Issue Description
1.0 First Issue
1.1
1.2
General Revision
New address TEWS LLC
Date
January 2000
May 2003
September 2006
TPMC813User Manual Issue 1.2 Page 3 of 20
Table of Contents
1 PRODUCT DESCRIPTION ......................................................................................... 6
2 TECHNICAL SPECIFICATION................................................................................... 7
3 LOCAL SPACE ADDRESSING.................................................................................. 8
3.1
PCI9050 Local Space Configuration .............................................................................................8
3.2
Local Address Space 0...................................................................................................................8
3.2.1
Dual Port RAM......................................................................................................................8
3.3
Local Address Space 1...................................................................................................................9
3.3.1
Semaphore Flag Registers...................................................................................................9
3.3.2
Local Interrupt Control Register (LICREG).........................................................................10
3.3.3
Local Interrupt Status Register (LISREG) ..........................................................................10
3.3.4
Local Reset Register (LRESREG)......................................................................................11
4 PCI9050 TARGET CHIP ........................................................................................... 12
4.1
PCI Configuration Registers (CFG) .............................................................................................12
4.1.1
PCI9050 Header .................................................................................................................12
4.1.2
PCI Base Address Initialization ..........................................................................................13
4.2
Local Configuration Register (LCR)............................................................................................14
4.3
Configuration EEPROM ................................................................................................................15
4.4
Local Software Reset....................................................................................................................16
4.5
Big / Little Endian..........................................................................................................................16
4.5.1
PCI Interrupt Control/Status Register .................................................................................17
5 INSTALLATION........................................................................................................ 18
5.1
Jumper Configuration...................................................................................................................18
5.2
Service LED / Service Request Button .......................................................................................19
6 PIN ASSIGNMENT – I/O CONNECTOR .................................................................. 20
6.1
Front panel DB9 female Connector.............................................................................................20
TPMC813User Manual Issue 1.2 Page 4 of 20
Table of Figures
FIGURE 1-1 : BLOCK DIAGRAM......................................................................................................................6
FIGURE 2-1 : TECHNICAL SPECIFICATION...................................................................................................7
FIGURE 3-1 : PCI9050 LOCAL SPACE CONFIGURATION ............................................................................8
FIGURE 3-2 : LOCAL MEMORY SPACE 1 ......................................................................................................8
FIGURE 3-3 : LOCAL ADDRESS SPACE 1 .....................................................................................................9
FIGURE 3-4 : INTERRUPT CONTROL REGISTER (LICREG) ......................................................................10
FIGURE 3-5 : INTERRUPT STATUS REGISTER (LISREG)..........................................................................10
FIGURE 3-6 : LOCAL RESET REGISTER (LRESREG).................................................................................11
FIGURE 4-1 : PCI9050 HEADER TPMC813-10 .............................................................................................12
FIGURE 4-2 : PCI9050 LOCAL CONFIGURATION REGISTER ....................................................................14
FIGURE 4-3 : CONFIGURATION EEPROM TPMC813-XX ...........................................................................15
FIGURE 4-4 : LOCAL BUS LITTLE/BIG ENDIAN...........................................................................................16
FIGURE 4-5 : INTERRUPT CONTROL/STATUS REGISTER (INTCSR; 0X4C)............................................17
FIGURE 5-1 : JUMPER CONFIGURATION....................................................................................................18
FIGURE 5-2 : SERVICE LED ..........................................................................................................................19
FIGURE 6-1 : DB9 FEMALE CONNECTOR ...................................................................................................20
TPMC813User Manual Issue 1.2 Page 5 of 20
1 Product Description
The TPMC813 is a standard single-width 32 bit PMC module providing a complete LON interface using the Neuron chip 3150. The communication is executed via a 4 Kbytes Dual Port RAM. A 32
Kbytes EPROM is used to store the protocol firmware of the Neuron chip 3150 and the application program.
Two kinds of on board physical interface are available: the TPMC813-10 supports standard RS485 and the TPMC813-30 provides the free topology twisted pair interface based on the ECHELON FTT-
10A transceiver.
Figure 1-1 : Block Diagram
TPMC813User Manual Issue 1.2 Page 6 of 20
2 Technical Specification
PMC Interface
Mechanical Interface
Electrical Interface
PCI Mezzanine Card (PMC) Interface
Single Size
PCI Rev. 2.1 compliant
33MHz / 32bit PCI
5V PCI Signaling Voltage
On Board Devices
PCI Target Chip
Firmware
I/O Interface
Interface Type
PCI9050-1 (PLX Technology)
MIP/DPR from ECHELON in EPROM, Run Time License included
TPMC813-10: 1LON port, RS485
TPMC813-30: 1LON port, FTT-10A Transceiver
DB9 connector I/O Connector
Physical Data
Power Requirements
Temperature Range
MTBF
Humidity
Weight
285mA typical @ +5V DC
Operating
Storage
-40 °C to +85 °C
-55°C to +125°C
TPMC813-10: 363274 h
TPMC813-30: 389994 h
5 – 95 % non-condensing
75 g
Figure 2-1 : Technical Specification
TPMC813User Manual Issue 1.2 Page 7 of 20
3 Local Space Addressing
3.1 PCI9050 Local Space Configuration
The local on board addressable regions are accessed from the PCI side by using the PCI9050 local spaces.
Endian Mode Description PCI9050
Local
Space
PCI9050
PCI Base Address
(Offset in PCI
Configuration
Space)
PCI Space
Mapping
Size
(Byte)
Port
Width
(Bit)
2
3
4
5
Registers
Registers
2 (0x18)
3 (0x1C)
4 (0x20)
MEM
MEM
-
4096
16
-
8
8
-
BIG (lower lane)
BIG (lower lane)
-
Local Address Space 0
Local Address Space 1
Local Address Space 2
5 (0x24) - - - - Local Address Space 3
(0x30) - - - Local Expansion ROM
Space
Figure 3-1 : PCI9050 Local Space Configuration
3.2 Local Address Space 0
PCI Base Address: PCI9050 PCI Base Address 2 (Offset 0x18 in PCI Configuration Space).
The Dual Port RAM memory is accessible through the Local Address Space 0 of the PMC module.
Offset / Register Offset Register Name
0x0000-0x0FFF 4k Dual Port RAM
Access Type
R/W
Register Width
8 bit
Figure 3-2 : Local Memory Space 1
TPMC813 is designed for a byte read/write access. A word or long word access will fail.
3.2.1 Dual Port RAM
The TPMC813 has a 4k x 8 Dual Ported RAM. This RAM is used to exchange messages and commands between the host software and the MIP/DPR firmware, which is running on the TPMC813.
The data structures are initialized by the MIP/DPR firmware as defined in the Microprocessor Interface
Program (MIP) User’s Guide of ECHELON.
TPMC813User Manual Issue 1.2 Page 8 of 20
3.3 Local Address Space 1
PCI Base Address: PCI9050 PCI Base Address 2 (Offset 0x1C in PCI Configuration Space).
Offset to PCI
Base Address 2
0x0000
0x0001
0x0002
0x0003
0x0004
0x0005
0x0006
0x0007
0x0008
0x0009
0x000A
Register Name
SEMMAPHORE FLAG 0
SEMMAPHORE FLAG 1
SEMMAPHORE FLAG 2
SEMMAPHORE FLAG 3
SEMMAPHORE FLAG 4
SEMMAPHORE FLAG 5
SEMMAPHORE FLAG 6
SEMMAPHORE FLAG 7
Local Interrupt Control Register (LICREG)
Local Interrupt Status Register (LISREG)
Local Reset Register (LRESREG)
Figure 3-3 : Local Address Space 1
Access
Type
Size
(Bit)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
R/W
W
8
8
8
8
8
8
8
8
8
8
8
TPMC813 is designed for a byte (8bit) read/write access. A word or long word access will fail.
3.3.1 Semaphore Flag Registers
The Semaphore Flag Registers are implemented in the Dual Ported RAM device of the TPMC813.
The MIP/DPR firmware of the TPMC813 uses these semaphores to synchronize the access to the data structures in the Dual Ported RAM between the host software and the MIP/DPR firmware. For more information please refer to Microprocessor Interface Program (MIP) User’s Guide of ECHELON.
The value of the semaphore flag is stored in bit 0 of the read data byte.
TPMC813User Manual Issue 1.2 Page 9 of 20
3.3.2 Local Interrupt Control Register (LICREG)
The Interrupt Control Register is used to control the interrupt generation.
Bit Symbol Description
7:1
0
Not used and undefined during reads
1 = interrupt enabled
0 = interrupt disabled
MIP/DPR firmware can generate an interrupt to indicate the transfer of messages. The interrupt will occur at pin INTA# of the PCI bus.
Access Reset
Value
W 0
Figure 3-4 : Interrupt Control Register (LICREG)
The LICREG is cleared to ‘0’ after power-on or reset.
3.3.3 Local Interrupt Status Register (LISREG)
The Interrupt Status Register is used to decode the interrupt type.
Bit Symbol Description
7:2
1
0
Not used and undefined during reads
If Neuron chip causes a reset
1 = reset
0 = run
Bit is cleared by writing ‘0x02’ to the LISREG address 0x1009.
If Neuron chip causes an interrupt
1 = interrupt
0 = run
Bit is cleared by writing ‘0x01’ to the LISREG address 0x1009.
Figure 3-5 : Interrupt Status Register (LISREG)
The LISREG is cleared to ‘0’ after power-on or reset.
Access Reset
Value
R/W 0
R/W 0
TPMC813User Manual Issue 1.2 Page 10 of 20
3.3.4 Local Reset Register (LRESREG)
The Local Reset Register LRESREG can be used to initiate a reset of the local side of the TPMC813 under control of the host software.
Bit Symbol Description
7:1
0
Access Reset
Value
W
Not used and undefined during reads
1 = active local reset
0 = run
The local reset remains active until this bit is cleared by the host software.
Figure 3-6 : Local Reset Register (LRESREG)
The LRESREG is cleared to ‘0’ after power-on or reset.
A local reset will restart the MIP/DPR firmware of the TPMC813.
TPMC813User Manual Issue 1.2 Page 11 of 20
4 PCI9050 Target Chip
4.1 PCI Configuration Registers (CFG)
0x10
0x14
0x18
0x1C
0x20
0x24
0x28
0x2C
0x30
0x34
PCI CFG
Register
Address
Write ‘0’ to all unused (Reserved) bits
0x00
0x04
0x08
31 24 23 16 15 8 7 0
Device ID
Status
Class Code
Vendor ID
Command
Revision ID
Timer
Cache Line
Size
PCI Base Address 0 for MEM Mapped Config. Registers
PCI Base Address 1 for I/O Mapped Config. Registers
PCI Base Address 2 for Local Address Space 0
PCI Base Address 3 for Local Address Space 1
PCI Base Address 4 for Local Address Space 2
PCI Base Address 5 for Local Address Space 3
PCI Cardbus Information Structure Pointer
Subsystem ID Subsystem Vendor ID
PCI Base Address for Local Expansion ROM
Reserved New Cap. Ptr.
PCI writeable
Initial Values
(Hex Values)
N
Y
N
Y[7:0]
Y
N
N
Y
N
Y
Y
Y
Y
Y
032D 1498
0280 0000
028000 XX
00 00 00 00
FFFFFF80
FFFFFF81
FFFFF000
FFFFFFF0
00000000
00000000
00000000
000A 1498
00000000
000000 00
Y[7:0] 00 00 01 00
Figure 4-1 : PCI9050 Header TPMC813-10
TPMC813User Manual Issue 1.2 Page 12 of 20
4.1.2 PCI Base Address Initialization
PCI Base Address Initialization is scope of the PCI host software.
PCI9050 PCI Base Address Initialization:
1. Write 0xFFFF_FFFF to the PCI9050 PCI Base Address Register.
2. Read back the PCI9050 PCI Base Address Register.
3. For PCI Base Address Registers 0:5, check bit 0 for PCI Address Space.
Bit 0 = '0' requires PCI Memory Space mapping
Bit 0 = '1' requires PCI I/O Space mapping
For the PCI Expansion ROM Base Address Register, check bit 0 for usage.
Bit 0 = ‘0’: Expansion ROM not used
Bit 0 = ‘1’: Expansion ROM used
4. For PCI I/O Space mapping, starting at bit location 2, the first bit set determines the size of the required PCI I/O Space size.
For PCI Memory Space mapping, starting at bit location 4, the first bit set to '1' determines the size of the required PCI Memory Space size.
For PCI Expansion ROM mapping, starting at bit location 11, the first bit set to '1' determines the required PCI Expansion ROM size.
For example, if bit 5 of a PCI Base Address Register is detected as the first bit set to ‘1’, the
PCI9050 is requesting a 32 byte space (address bits 4:0 are not part of base address decoding).
5. Determine the base address and write the base address to the PCI9050 PCI Base Address
Register. For PCI Memory Space mapping the mapped address region must comply with the definition of bits 3:1 of the PCI9050 PCI Base Address Register.
After programming the PCI9050 PCI Base Address Registers, the software must enable the
PCI9050 for PCI I/O and/or PCI Memory Space access in the PCI9050 PCI Command Register
(Offset 0x04). To enable PCI I/O Space access to the PCI9050, set bit 0 to '1'. To enable PCI
Memory Space access to the PCI9050, set bit 1 to '1'.
For more information please refer to the PCI9050-1 data sheet which is part of the TMPC813-ED
Engineering Documentation.
TPMC813User Manual Issue 1.2 Page 13 of 20
4.2 Local Configuration Register (LCR)
After reset, the PCI9050 Local Configuration Registers are loaded from the on board serial configuration EEPROM.
The PCI base address for the PCI9050 Local Configuration Registers is:
PCI9050 PCI Base Address 0 (PCI Memory Space) (Offset 0x10 in the PCI9050 PCI
Configuration Register Space) or
PCI9050 PCI Base Address 1 (PCI I/O Space) (Offset 0x14 in the PCI9050 PCI Configuration
Register Space).
Do not change hardware dependent bit settings in the PCI9050 Local Configuration Registers.
Offset from
PCI Base
Address
0x00
0x04
0x08
0x0C
0x10
0x14
0x18
0x1C
0x20
0x24
0x28
0x2C
0x30
0x34
0x38
0x3C
0x40
0x44
0x48
Register
Local Address Space 0 Range
Local Address Space 1 Range
Local Address Space 2 Range
Local Address Space 3 Range
Local Exp. ROM Range
Local Re-map Register Space 0
Local Re-map Register Space 1
Local Re-map Register Space 2
Local Re-map Register Space 3
Local Re-map Register ROM
Local Address Space 0 Descriptor
Local Address Space 1 Descriptor
Local Address Space 2 Descriptor
Local Address Space 3 Descriptor
Local Exp. ROM Descriptor
Chip Select 0 Base Address
Chip Select 1 Base Address
Chip Select 2 Base Address
Chip Select 3 Base Address
Value
0x0FFF_F000
0x0FFF_FFF0
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0001
0x0000_1001
0x0000_0000
0x0000_0000
0x0000_0000
0x2921_50C2
0x2921_50C2
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0801
0x0000_1009
0x0000_0000
0x0000_0000
0x50 Miscellaneous 0x0078_0000
Figure 4-2 : PCI9050 Local Configuration Register
TPMC813User Manual Issue 1.2 Page 14 of 20
4.3 Configuration EEPROM
After power-on or PCI reset, the PCI9050 loads initial configuration register data from the on board configuration EEPROM.
The configuration EEPROM contains the following configuration data:
•
Address 0x00 to 0x0F : PCI9050 PCI Configuration Register Values
•
Address 0x10 to 0x64 : PCI9050 Local Configuration Register Values
•
Address 0x65 to 0x7C : Not used
•
Address 0x7E + 0x7F : TPMC variant
See the PCI9050 Manual for more information.
Address Offset
0x00 0x02 0x04 0x06 0x08 0x0A 0x0C 0x0E
0x00 0x032D 0x1498 0x0280 0x0000 s.b. 0x1498 0x0000 0x0100
0x10 0x0FFF 0xF000 0x0FFF 0xFFF0 0x0000 0x0000 0x0000 0x0000
0x20 0x0000 0x0000 0x0000 0x0001 0x0000 0x1001 0x0000 0x0000
0x30 0x0000 0x0000 0x0000 0x0000 0x2921 0x50C2 0x2921 0x50C2
0x40 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0801
0x50 0x0000 0x1009 0x0000 0x0000 0x0000 0x0000 0x0000 0x0043
0x60 0x0078 0x0000 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF
0x70 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF s.b.
Figure 4-3 : Configuration EEPROM TPMC813-xx
Subsystem-ID Value (Offset 0x08): TPMC813-10 0x000A
TPMC813-30 0x001E
Subsystem-ID Value (Offset 0x7E): TPMC813-10 0x000A
TPMC813-30 0x001E
For more information please refer to the PCI9050-1 data sheet which is part of the TPMC813-ED
Engineering Documentation.
TPMC813User Manual Issue 1.2 Page 15 of 20
4.4 Local Software Reset
The PCI9050 Local Reset Output LRESETo# is used to reset the on board local logic.
The PCI9050 local reset is active during PCI reset or if the PCI Adapter Software Reset bit is set in the
PCI9050 local configuration register CNTRL (offset 0x50).
CNTRL[30] PCI Adapter Software Reset:
Value of ‘1’ resets the PCI9050 and issues a reset to the Local Bus (LRESETo# asserted). The
PCI9050 remains in this reset condition until the PCI Host clears this bit. The contents of the PCI9050
PCI and Local Configuration Registers are not reset. The PCI9050 PCI Interface is not reset.
4.5 Big / Little Endian
•
PCI – Bus (Little Endian)
Byte 0
Byte 1
Byte 2
Byte 3
AD[7..0]
AD[15..8]
AD[23..16]
AD[31..24]
•
Every Local Address Space (0...3) and the Expansion ROM Space can be programmed to operate in Big or Little Endian Mode.
Big Endian
32 Bit
Byte 0 D[31..24]
Byte 1 D[23..16]
Byte 2 D[15..8]
Byte 3 D[7..0]
16 Bit upper lane
Byte 0 D[31..24]
Byte 1 D[23..16]
16 Bit lower lane
Byte 0 D[15..8]
Byte 1 D[7..0]
8 Bit upper lane
Byte 0 D[31..24]
8 Bit lower lane
Byte 0 D[7..0]
Little Endian
32 Bit
Byte 0
Byte 1
Byte 2
Byte 3
16 Bit
Byte 0
Byte 1
8 Bit
Byte 0
D[7..0]
D[15..8]
D[23..16]
D[31..24]
D[7..0]
D[15..8]
D[7..0]
Figure 4-4 : Local Bus Little/Big Endian
TPMC813User Manual Issue 1.2 Page 16 of 20
Standard use of the TPMC813:
Local Address Space 0
Local Address Space 1
8 bit bus in Big Endian Mode
8 bit bus in Big Endian Mode
Local Address Space 2
Local Address Space 3 not used not used
Expansion ROM Space not used
To change the Endian Mode use the Local Configuration Registers for the corresponding Space. Bit
24 of the according register sets the mode. A value of 1 indicates Big Endian and a value of 0 indicates Little Endian.
For further information please refer to the PCI9050 manual which is also part of the TPMC813-ED
Engineering Documentation.
Use the PCI Base Address 0 + Offset or PCI Base Address 1 + Offset:
Short cut Offset Name
LAS0BRD
LAS1BRD
0x28 Local Address Space 0 Bus Region Description Register
0x2C Local Address Space 0 Bus Region Description Register
LAS2BRD
LAS3BRD
0x30 Local Address Space 0 Bus Region Description Register
0x34 Local Address Space 0 Bus Region Description Register
EROMBRD 0x38 Expansion ROM Bus Region Description Register
You could also use the PCI - Base Address 1 I/O Mapped Configuration Registers.
4.5.1 PCI Interrupt Control/Status Register
The Neuron chip can generate an interrupt at pin INTA# of the PCI bus. The interrupt status can be read at the Interrupt Status Register INTCSR of the PCI Controller PCI9050-1.
Bit
31:8 unused
6
5
4
3
1
0
Description
PCI Interrupt Enable
Local Interrupt 2 Status
Local Interrupt 2 Polarity
Local Interrupt 2 Enable
Local Interrupt 1 Polarity
Local Interrupt 1 Enable
Access Reset
Value
R 0
R/W 0
R/W 1
R
R/W
0
0
R/W
R
R/W
R/W
0
0
1
1
Figure 4-5 : Interrupt Control/Status Register (INTCSR; 0x4C)
TPMC813User Manual Issue 1.2 Page 17 of 20
5 Installation
5.1 Jumper Configuration
The jumper block J1 configures the termination of the TPMC813-30.
Termination
Termination with 52.5 ohms for
Singly Terminated Bus Topology
Termination with 105 ohms for
Singly Terminated Bus Topology
Termination with 105 ohms for
Doubly Terminated Bus Topology
No termination on board (factory setting)
1-3 2-4 close close open close close open open open
The jumper block J2 configures the termination of the TPMC813-10.
Termination
Termination with a R / C network
No termination on board (factory setting)
1-2 3-4 close close open open
TPMC813User Manual Issue 1.2
Figure 5-1 : Jumper Configuration
Page 18 of 20
5.2 Service LED / Service Request Button
The firmware flashes the Service LED at a ½ Hz rate if the TPMC813 has not been configured with network address information. Pressing the Service Request Button causes the TPMC813 to transmit a network management message containing its 48 bit unique ID on the network.
Node State
Without application and without configuration
Without configuration (but with an application)
Service LED
On
Flashing
Configured, Hard Off-Line Off
Configured Off
Figure 5-2 : Service LED
TPMC813User Manual Issue 1.2 Page 19 of 20
6 Pin Assignment – I/O Connector
6.1 Front panel DB9 female Connector
Pin
1
Signal
TPMC813-10 / RS485
LON DATA +
2 LON DATA -
3 NC
4 NC
5 NC
6 Case Ground
Level
TPMC813-30 / FTT-10A
LON NET A
LON NET B
NC
NC
NC
Case Ground
7 SERVICE#
8 Ground
SERVICE#
Ground
9 +5V, 1.1A maximum (fused) +5V, 1.1A maximum (fused)
Figure 6-1 : DB9 female connector
TPMC813User Manual Issue 1.2 Page 20 of 20
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