Intel 8291, 8292, 8293 Controller Application Note

intel APPLICATION AP-66
NOTE
| FABRIKSPARKEN 31-2600 GLOSTRUP -02- 45 66 45
DAMAGERVEJ 23 8260 VIBY J-06 11 00 11
January 1980
© e
се ° № E
KS © y
C INTEL CORPORATION, 1980
RELATED INTEL® PUBLICATIONS
8291 GPIB Talker/ Listener Data Sheet
8292 GPIB Controller Data Sheet
8293 GPIB Transceiver Data Sheet
AP-41 Introduction the UPI™41A
UPI™41 User’s Manual
RELATED ZIATECH PUBLICATIONS
ZT488 GPIB Logic Analyzer Operating Manual
ZT80/18 GPIB Controller Operating Manual
Z17488/ 18 GPIB Controller Operating Manual
RELATED IEEE PUBLICATIONS
IEEE Std 488-1978 Digital Interface for Programmable Instrumentation
The material in the Application Note is for informational purposes only and is subject to change without
notice. Intel Corporation has made an effort to verify that the material in this document is correct. How-
ever, Intel Corporation does not assume any responsibility for errors that may appear in this document.
The following are trademarks of Intel Corporation and may be used only to describe Intel products: Intel,
Insite, Intellec, Library Manager, Megachassis, Micromap, Multibus, PROMPT, RMX/80, UPI, Intelevi-
sion, uScope, Promware, MCS, ICE, 1SBC, BXP, 1CS, and the combination of MCS, ICE, iSBC or iCS
With a numerical suffix.
Intel Corporation Assumes No Responsibility for the Use of Any Circuitry Other Than Circuitry Embodied in an Intel Product. No Other Circuit Patent Licenses are Implied.
THE AUTHOR
Bert Forbes, Ziatech President, holds an SB from MIT (1966) and an
MSEE from Stanford (1967). During the ten years prior to forming Ziatech,
he worked at Hewlett-Packard where he was one of the architects of the
HP3000 multi-lingual, multi-programming computer, as well as a member
of the 3000’s European marketing team based in Geneva, Switzerland. This
innovative computer system is one of the major contributors to HP’s out-
standing sales record. Bert is a co-inventor named on several 3000 related
patents held by Hewlett-Packard.
Also at Hewlett-Packard, Bert was the architect and Project Manager for
the high-speed 16 bit CMOS/SOS microprocessor that is being used in con-
junction with an HPIB controller chip in dozens of Hewlett-Packard instru-
ments and computer peripherals. He has authored articles on logic design,
IEEE 488 and computer architecture and has taught several university
courses on microprocessors.
Bert has been specializing in the GPIB at Ziatech and has designed
numerous GPIB controllers and interfaces. He 1s a nationally known con-
sultant in this field.
Using the 8292
GPIB Controller
Contents
INTRODUCTION ee 1
GPIB/IEEE 488 OVERVIEW ii 1
HARDWARE ASPECTS OF THE SYSTEM ............. iii... 6
8291 TALKER/LISTENER ......... i, 6
8292 CONTROLLER dds 6
8293 BUS TRANSCEIVERS iii, 7
ZT7488/18 GPIB CONTROLLER ................................ 10
8292 COMMAND DESCRIPTION ..... oti, 11
SOFTWARE DRIVER OUTLINE ......... ii. 15
INITIALIZATION sss 15
TALKER/LISTENER .... 00000reeonooneao, 16
Send Data .......20202444 400100 a a aa aa a aa aa 16
Receive Data ..........eee00e0000a00aiecoracoreoocacondacera 17
Transfer Data ................ a ee 19
CONTROLLER .. sss sss 19
Trigger oo Lea a eee a ea a ea a ea a aa aa ae 19
Device Clear ........110101002020400 01 LL a Lanta a a 20
Serial Poll 111110011111 LL LL LL a anna 20
РагаПе! Ро! ................................................. 21
Pass Control... Lea a aan ana aa 23
Receive Control................0e00000000racoceconcecorcaeroo 24
Service Request .............eeeerccorvrccareacecorencecererna. 25
SYSTEM CONTROLLER ee Le Lalanne 26
Remote ........e e eeececoeseeaereaoeandoarecneeoodeereaacococdeceroo 26
Local ................. PR PP 26
Interface Clear/ Abort .......... in... 27
INTERRUPT AND DMA CONSIDER A TIONS 27
APPLICATION EXAMPLE.......….….....1001020001 1 LL La La 28
CON CLUSION od ds a a aa aan La. 29
APPENDIX A LL LL LL LL LA La a aa 29
SOURCE LISTINGS ode, 29
APPENDIX Bo... LL Le at 47
TEST CASES FOR THE SOFTWARE DRIVERS .............. 47
APPENDIX C.......1111001 LL LL LL ALL LL a Lana LL 51
INTRODUCTION
The Intel® 8292 1s a preprogrammed UPI™-41A that
implements the Controller function of the IEEE Std
488-1978 (GPIB, HP-IB, IEC Bus, etc.). In order to
function the 8292 must be used with the 8291
Talker/Listener and suitable interface and trans-
ceiver logic such as a pair of Intel 8293s. In this
configuration the system has the potential to be a
complete GPIB Controller when driven by the
appropriate software. It has the following capa-
bilities: System Controller, send IFC and Take
Charge, send REN, Respond to SRQ, send Interface
messages, Receive Control, Pass Control, Parallel
Poll and Take Control Synchronously.
This application note will explain the 8292 only in
the system context of an 8292, 8291, two 8293s and
the driver software. If the reader wishes to learn
more about the UPI-41 A aspects of the 8292, Intel's
Application Note AP-41 describes the hardware
features and programming characteristics of the
device. Additional information on the 8291 may be
obtained in the data sheet. The 8293 1s detailed in its
data sheet. Both chips will be covered here in the
details that relate to the GPIB controller.
The next section of this application note presents an
overview of the GPIB in a tutorial, but compre-
hensive nature. The knowledgable reader may wish
to skip this section; however, certain basic semantic
concepts introduced there will be used throughout
this note.
Additional sections cover the view of the 8292 from
the CPU’s data bus, the interaction of the 3 chip
types (8291, 8292, 8293), the 8292s software
protocol and the system level hardware/software
protocol. A brief description of interrupts and
DMA will be followed by an application example.
Appendix A contains the source code for the system
driver software.
GPIB/IEEE 488 OVERVIEW
DESIGN OBJECTIVES
What is the IEEE 488 (GPIB)?
The experience of designing systems for a variety of
applications in the early 1970’s caused Hewlett-
Packard to define a standard intercommunication
mechanism which would allow them to easily assemble
instrumentation systems of varying degrees of com-
plexity. In a typical situation each instrument de-
signer designed his/her own interface from scratch.
Each one was inconsistent in terms of electrical
levels, pin-outs on a connector, and types of con-
nectors. Every time they built a system they had to
invent new cables and new documentation just to
specify the cabling and interconnection procedures.
Based on this experience, Hewlett-Packard began to
define a new interconnection scheme. They went
further than that, however, for they wanted to
specify the typical communication protocol for
systems of instruments. So in 1972, Hewlett-
Packard came out with the first version of the bus
which since has been modified and standardized by a
committee of several manufacturers, coordinated
through the IEEE, to perfect what 1s now known as
the IEEE 488 Interface Bus (also known as the HP-
IB, the GPIB and the IEC bus). While this bus
specification may not be perfect, it is a good
compromise of the various desires and goals of
instrumentation and computer peripheral manu-
facturers to produce a common interconnection
mechanism. It fits most instrumentation systems in
use today and also fits very well the microcomputer
1/0 bus requirements. The basic design objectives
for the GPIB were to:
1. Specify a system that is easy to use, but has all of
the terminology and the definitions related to
that system precisely spelled out so that every-
one uses the same language when discussing the
GPIB.
2. Define all of the mechanical, electrical, and func-
tional interface requirements of a system, yet not
define any of the device aspects (they are left up
to the instrument designer).
3. Permit a wide range of capabilities of instruments
and computer peripherals to use a system simul-
taneously and not degrade each other’s per-
formance.
4. Allow different manufacturers’ equipment to be
connected together and work together on the
same bus.
5. Define a system that is good for limited dis-
tance interconnections.
6. Define a system with minimum restrictions on
performance of the devices.
7. Define a bus that allows asynchronous communi-
cation with a wide range of data rates.
8. Define a low cost system that does not require
extensive and elaborate interface logic for the
low cost instruments, yet provides higher capa-
bility for the higher cost instruments if desired.
9. Allow systems to exist that do not need a central
controller; that is, communication directly from
one instrument to another is possible.
Although the GPIB was originally designed for
instrumentation systems, it became obvious that
most of these systems would be controlled by a
calculator or computer. With this in mind several
modifications were made to the original proposal
before its final adoption as an international stan-
dard. Figure 1 lists the salient characteristics of the
GPIB as both an instrumentation bus and as a
computer 1/0 bus.
Data Rate
1M bytes/s, max
250k bytes/s, typ
Multiple Devices
15 devices, max (electrical limit)
8 devices, typ (interrupt flexibility)
Bus Length
20 m, max
2 m/device, typ
Byte Oriented
8-bit commands
8-bit data
Block Multiplexed
Optimum strategy on GPIB due to
setup overhead for commands
Interrupt Driven
Serial poll (slower devices)
Parallel poll (faster devices)
Direct Memory Access
One DMA facility at controller
serves all devices on bus
Asynchronous
One talker
Multiple listeners
|/О to I/O Transfers
Talker and listeners need not
include microcomputer/controller
3-wire handshake
Figure 1. Major Characteristics of
GPIB as Microcomputer I/O Bus
The bus can be best understood by examining each
of these characteristics from the viewpoint of a
general microcomputer 1/0 bus.
Data Rate — Most microcomputer systems utilize
peripherals of differing operational rates, such as
floppy discs at 31k or 62k bytes/s (single or double
density), tape cassettes at 5k to 10k bytes/s, and
cartridge tapes at 40k to 80k bytes/s. In general, the
only devices that need high speed 1/0 are 0.5” (1.3-
cm) magnetic tapes and hard discs, operational at
30k to 781k bytes/s, respectively. Certainly, the
250k-bytes/s data rate that can be easily achieved by
the IEEE 488 bus is sufficient for microcomputers
and their peripherals, and 1s more than needed for
typical analog instruments that take only a few read-
ings per second. The 1M-byte/s maximum data rate
Is not easily achieved on the GPIB and requires
special attention to considerations beyond the scope
of this note. Although not required, data buffering
in each device will improve the overall bus per-
formance and allow utilization of more of the bus
bandwidth.
Multiple Devices — Many microcomputer systems
used as computers (not as components) service from
three to seven peripherals. With the GPIB, up to 8
devices can be handled easily by 1 controller; with
some slowdown in interrupt handling, up to 15
devices can work together. The limit of 8 1s imposed
by the number of unique parallel poll responses
available; the limit of 15 1s set by the electrical drive
characteristics of the bus. Logically, the IEEE 488
Standard is capable of accommodating more device
addresses (31 primary, each potentially with 31
secondaries).
Bus Length — Physically, the majority of micro-
computer systems fit easily on a desk top or in a
standard 19” (48-cm) rack, eliminating the need for
extra long cables. The GPIB is designed typically to
have 2 m of length per device, which accommodates
most systems. A line printer might require greater
cable lengths, but this can be handled at the lower
speeds involved by using extra dummy termina-
tions.
Byte Oriented — The 8-bit byte 1s almost universal
in 1/0 applications; even 16-bit and 32-bit com-
puters use byte transfers for most peripherals. The 8-
bit byte matches the ASCII code for characters and
is an integral submultiple of most computer word
sizes. The GPIB has an 8-bit wide data path that may
be used to transfer ASCII or binary data, as well as
the necessary status and control bytes.
Block Multiplexed — Many peripherals are block
oriented or are used in a block mode. Bytes are
transferred in a fixed or variable length group; then
there is a wait before another group is sent to that
device, e.g., one sector of a floppy disc, one line on a
printer or tape punch, etc. The GPIB is, by nature, a
block multiplexed bus due to the overhead involved
in addressing various devices to talk and listen. This
overhead is less bothersome if it only occurs once for
a large number of data bytes (once per block). This
mode of operation matches the needs of micro-
computers and most of their peripherals. Because of
block multiplexing, the bus works best with buffered
memory devices.
Interrupt Driven — Many types of interrupt systems
exist, ranging from complex, fast, vectored / priority
networks to simple polling schemes. The main
tradeoff is usually cost versus speed of response. The
GPIB has two interrupt protocols to help span the
range of applications. The first is a single service
request (SRQ) line that may be asserted by all
interrupting devices. The controller then polls all
devices to find out which wants service. The polling
mechanism 1s well defined and can be easily
automated. For higher performance, the parallel
poll capability in the IEEE 488 allows up to eight
devices to be polled at once — each device is
assigned to one bit of the data bus. This mechanism
provides fast recognition of an interrupting device.
A drawback is the frequent need for the controller to
explicitly conduct a parallel poll, since there is no
equivalent of the SRQ line for this mode.
Direct Memory Access (DMA) — In many applica-
tions, no imediate processing of I/O data on a byte-
by-byte basis 1s needed or wanted. In fact,
programmed transfers slow down the data transfer
rate unnecessarily in these cases, and higher speed
can be obtained using DMA. With the GPIB, one
DMA facility at the controller serves all devices.
There 1s no need to incorporate complex logic in
each device.
Asynchronous Transfers — An asynchronous bus is
desirable so that each device can transfer at its own
rate. However, there is still a strong motivation to
buffer the data at each device when used in large
systems in order to speed up the aggregate data rate
on the bus by allowing each device to transfer at top
speed. The GPIB is asynchronous and uses a special
| a | 4 A 44 И
DEVICE A C
ABLE TO
TALK, LISTEN,
AND DATA BUS
р
CONTROL <
(e.g. computer)
DEVICE B 4
ABLE TO
TALK AND
LISTEN
(e.g. digital
; DATA BYTE
multimeter) TRANSFER
L—— CONTROL
DEVICE C <
ONLY ABLE
TO LISTEN
(e.g. signal
generator) GENERAL
INTERFACE
Г — MANAGEMENT
DEVICE D к
ONLY ABLE
TO TALK
YY
7
(e.g. counter)
| DIO 1...(DATA
INPUT/OUTPUT)
DAV (DATA VALID)
NRFD (NOT READY FOR DATA)
NDAC (NOT DATA ACCEPTED)
IFC (INTERFACE CLEAR)
ATN (ATTENTION)
SRQ (SERVICE REQUEST)
REN (REMOTE ENABLE)
EOI (END-OR-IDENTIFY)
Figure 2. Interface Capabilities and Bus Structure
3-wire handshake that allows data transfers from
one talker to many listeners.
ГО То 1/0 Transfers — In practice, 1/0 to I/O
transfers are seldom done due to the need for
processing data and changing formats or due to
mismatched data rates. However, the GPIB can
support this mode of operation where the micro-
computer is neither the talker nor one of the
listeners.
GPIB SIGNAL LINES
Data Bus
The lines DIOI through DIOS are used to transfer
addresses, control information and data. The
formats for addresses and control bytes are defined
by the IEEE 488 standard (see Appendix C). Data
formats are undefined and may be ASCII (with or
without parity) or binary. DIOI 1s the Least Sig-
nificant Bit (note that this will correspond to bit 0
on most computers).
Management Bus
ATN — Attention This signal 1s asserted by the
Controller to indicate that it is placing an address or
control byte on the Data Bus. ATN is de-asserted to
allow the assigned Talker to place status or data on
the Data Bus. The Controller regains control by re-
asserting ATN; this is normally done synchronously
with the handshake to avoid confusion between
control and data bytes.
FOI — End or Identify This signal has two uses as
its name implies. À talker may assert FOI simul-
taneously with the last byte of data to indicate end of
data. The Controller may assert EOI along with
ATN to initiate a Parallel Poll. Although many
devices do not use Parallel Poll, all devices should
use EOI to end transfers (many currently available
ones do not).
SRO — Service Request This line is like an
interrupt: it may be asserted by any device to request
the Controller to take some action. The Controller
must determine which device is asserting SRQ by
conducting a Serial Poll at its earliest convenience.
The device deasserts SRQ when polled.
IFC — Interface Clear This signal is asserted only
by the System Controller in order to initialize all
device interfaces to a known state. After deasserting
IFC, the System Controller is the active controller of
the system.
REN — Remote Enable This signal 1s asserted
only by the System Controller. Its assertion does not
place devices into Remote Control mode; REN only
enables a device to go remote when addressed to
listen. When in Remote, a device should ignore its
front panel controls.
Transfer Bus
NRFD — Not Ready For Data This handshake
line 1s asserted by a listener to indicate it is not yet
ready for the next data or control byte. Note that the
Controller will not see NRFD deasserted (1.e., ready
for data) until all devices have deasserted NRFD.
NDAC — Not Data Accepted This handshake
line 1s asserted by a Listener to indicate it has not yet
accepted the data or control byte on the DIO lines.
Note that the Controller will not see NDAC
deasserted (1.e., data accepted) until all devices have
deasserted NDAC.
DAV — Data Valid This handshake line is
asserted by the Talker to indicate that a data or
control byte has been placed on the DIO lines and
has had the minimum specified settling time.
Figure 3. GPIB Handshake Sequence
GPIB INTERFACE FUNCTIONS
There are ten (10) interface functions specified by
the IEEE 488 standard. Not all devices will have all
functions and some may only have partial subsets.
The ten functions are summarized below with the
relevant section number from the IEEE document
given at the beginning of each paragraph. For
further information please see the IEEE standard.
1. SH — Source Handshake (section 2.3) This
function provides a device with the ability to
properly transfer data from a Talker to one or
more Listeners using the three handshake lines.
2. AH — Acceptor Handshake (section 2.4) This
function provides a device with the ability to
properly receive data from the Talker using the
three handshake lines. The AH function may
also delay the beginning (NRFD) or end
(NDAC) of any transfer.
3. T — Talker (section 2.5) This function allows a
device to send status and data bytes when ad-
dressed to talk. An address consists of one
(Primary) or two (Primary and Secondary)
bytes. The latter 1s called an extended Talker.
4. L — Listener (section 2.6) This function allows
a device to receive data when addressed to listen.
There can be extended Listeners (analogous to
extended Talkers above).
5. SR — Service Request (section 2.7) This func-
tion allows a device to request service (inter-
rupt) the Controller. The SRQ line may be
asserted asynchronously.
6. RL — Remote Local (section 2.8) This function
allows a device to be operated in two modes:
Remote via the GPIB or Local via the manual
front panel controls.
7. PP — Parallel Poll (section 2.9) This function
allows a device to present one bit of status to the
Controller-in-charge. The device need not be
addressed to talk and no handshake is required.
8. DC — Device Clear (section 2.10) This function
allows a device to be cleared (initialized) by the
Controller. Note that there is a difference
between DC (device clear) and the IFC line
(interface clear).
9. DT — Device Trigger (section 2.11) This func-
tion allows a device to have its basic operation
started either individually or as part of a group.
This capability is often used to synchronize
several instruments.
10. С — Controller (section 2.12) This function
allows a device to send addresses, as well as
universal and addressed commands to other
devices. There may be more than one controller
on a system, but only one may be the controller-
in-charge at any one time.
At power-on time the controller that is handwired to
be the System Controller becomes the active
controller-in-charge. The System Controller has
several unique capabilities including the ability to
send Interface Clear (IFC — clears all device
interfaces and returns control to the System
Controller) and to send Remote Enable (REN —
allows devices to respond to bus data once they are
addressed to listen). The System Controller may
optionally Pass Control to another controller, if the
system software has the capability to do so.
GPIB CONNECTOR
The GPIB connector is a standard 24-pin industrial
connector such as Cinch or Amphenol series 57
Micro-Ribbon. The IEEE standard specifies this
connector, as well as the signal connections and the
mounting hardware.
The cable has 16 signal lines and 8 ground lines. The
maximum length is 20 meters with no more than two
meters per device.
SHIELD
ATN
SRQ
IFC
NDAC
NRFD
DAV
EOI
D104
DIO3
DI02
DIO1
Figure 4. GPIB Connector
GPIB SIGNAL LEVELS
The GPIB signals are all TTL compatible, low true
signals. A signal is asserted (true) when its electrical
voltage is less than 0.5 volts and 1s deasserted (false)
when it is greater than 2.4 volts. Be careful not to
become confused with the two handshake signals,
NRFD and NDAC which are also low true (1e.
> 0.5 volts implies the device is Not Ready For
Data).
The Intel 8293 GPIB transceiver chips ensure that all
relevant bus driver/receiver specifications are met.
Detailed bus electrical specifications may be found
in Section 3 of the IEEE Std 488-1978. The Standard
is the ultimate reference for all GPIB questions.
GPIB MESSAGE PROTOCOLS
The GPIB is a very flexible communications
medium and as such has many possible variations of
protocols. To bring some order to the situation, this
section will discuss a protocol similar to the one used
by Ziatech’s ZT80 GPIB controller for Intel’s
MULTIBUS™ computers. The ZT80 1s a complete
high-level interface processor that executes a set of
high level instructions that map directly into GPIB
actions. The sequences of commands, addresses and
data for these instructions provide a good example
of how to use the GPIB (additional information is
available in the ZT80 Instruction Manual). The
‘null’ at the end of each instruction is for cosmetic
use to remove previous information from the DIO
lines.
DA TA — Transfer a block of data from device A to
devices B, C...
|. Device A Primary (Talk) Address
Device A Secondary Address (1f any)
2. Universal Unlisten
3. Device B Primary (Listen) Address
Device B Secondary Address (1f any)
Device C Primary (Listen) Address
etc.
4. First Data Byte
Second Data Byte
Last Data Byte (EOI)
5. Null
TRIGR — Trigger devices A, B,...to take action
|. Universal Unlisten
2. Device A Primary (Listen) Address
Device A Secondary Address (if any)
Device B Primary (Listen) Address
Device B Secondary Address (if any)
etc.
3. Group Execute Trigger
4. Null
PSCTL — Pass control to device A
|. Device À Primary (Talk) Address
Device A Secondary Address (if any)
2. Take Control
3. Null
CLEAR — Clear all devices
|. Device Clear
2. Null
REMAL — Remote Enable
|. Assert REN continuously
GOREM — Put devices A, B,...into Remote
|. Assert REN continuously
2. Device A Primary (Listen) Address
Device A Secondary Address (if any)
Device B Primary (Listen) Address
Device B Secondary Address (if any)
etc.
3. Null
GOLOC — Put devices A, B,...into Local
|. Device A Primary (Listen) Address
Device A Secondary Address (if any)
Device B Primary (Listen) Address
Device B Secondary Address (if any)
etc.
2. Go To Local
3. Null
LOCAL — Reset all devices to Local
|. Stop asserting REN
LILKAL — Prevent all devices from returning to
Local
|. Local Lock Out
2. Null
SPOLL — Conduct a serial poll of devices A, B,...
|. Serial Poll Enable
2. Universal Unlisten
3. ZT 80 Primary (Listen) Address
ZT 80 Secondary Address
4. Device Primary (Talk) Address
Device Secondary Address (if any)
Status byte from device
Go to Step 4 until all devices on list have been polled
Serial Poll Disable
. Null
PPUAL — Unconfigure and disable Parallel Poll
response from all devices
|. Parallel Poll Unconfigure
2. Null
ENA PP — Enable Parallel Poll response in devices
A, B,...
|. Universal Unlisten
2. Device Primary (Listen) Address
Device Secondary Address (1f any)
3. Parallel Poll Configure
4. Parallel Poll Enable
5. Go to Step 2 until all devices on list have been
configured.
6. Null
DISPP — Disable Parallel Poll response from de-
vices A, B,...
|. Universal Unlisten
2. Device A Primary (Listen) Address
Device A Secondary Address (1f any)
Device B Primary (Listen) Address
Device B Secondary Address (if any)
etc.
3. Disable Parallel Poll
4. Null
This Ap Note will detail how to implement a useful
subset of these controller instructions.
ONU OU
HARDWARE ASPECTS OF THE SYSTEM
8291 GPIB TALKER/LISTENER
The 8291 ts a custom designed chip that implements
many of the non-controller GPIB functions. It pro-
vides hooks so the user’s software can implement
additional features to complete the set. This chip is
discussed in detail in its data sheet. The major fea-
tures are summarized here:
— Designed to interface microprocessors to the GPIB
— Complete Source and Acceptor Handshake
— Complete Talker and Listener Functions with ex-
tended addressing
— Service Request, Parallel Poll, Device Clear, De-
vice Trigger, Remote/ Local functions
— Programmable data transfer rate
—Maskable interrupts
— On-chip primary and secondary address recogni-
tion
— 1-8 MHz clock range
— 16 registers (8 read, 8 write) for CPU interface
— DMA handshake provision
— Trigger output pin
—On-chip EOS (End of Sequence) recognition
The pinouts and block diagram are shown in Fig. 5.
One of eight read registers is for data transfer to the
CPU; the other seven allow the microprocessor to
monitor the GPIB states and various bus and device
conditions. One of the eight write registers is for data
transfer from the CPU; the other seven control
various features of the 8291.
The 8291 interface functions will be software
configured in this application example to the
following subsets for use with the 8292 as a
controller that does not pass control. The 8291 1s
used only to provide the handshake logic and to send
and receive data bytes. It is not acting as a normal
device in this mode, as 1t never sees ATN asserted.
SHI Source Handshake
AHI Acceptor Handshake
T3 Basic Talk-only
Li — Basic Listen-only
SRO No Service Requests
RLO No Remote/ Local
PPO No Parallel Poll response
DCO No Device Clear
DTO No Device Trigger
If control 1s passed to another controller, the 8291
must be reconfigured to act as a talker/listener with
the following subsets:
SHI Source Handshake
AHI Acceptor Handshake
TS Basic Talker and Serial Poll
L3 Basic Listener
SRI Service Requests
RLI Remote / Local with Lockout
PP2 Preconfigured Parallel Poll
DCI Device Clear
DTI Device Trigger
CO Not a Controller
Most applications do not pass control and the con-
troller ıs always the system controller (see 8292
commands below).
8292 GPIB CONTROLLER
The 8292 ıs a preprogrammed Intel® 8041A that
provides the additional functions necessary to
PIN CONFIGURATION
8 READ
REGISTERS
BLOCK DIAGRAM
> |
вона
INTERFACE |
FUNCTIONS
SH GPIB CONTROL } | TO NON-INVERTING
AH | BUS TRANSCEIVERS
TE
LE |
md: NS оБусс
— - vec Qu | 8291
T/R2[]2 39JEOI
cLock [3 38 []NDAC |
RESET [4 37 NRFD |
TRIGOS 36 [1DAV
pREO de 35 [] DIOS |
DACK DIO7 3 KZ
DACK [47 34 [] DIO7 2
css 33] DIO6 «
ro0e 32 [] DIO5 g
WRO 10 8291 331f1]DIO4 5 >
— %
INT }11 30 [0 0103 8
vo 12 29 [] DIO2 3
010413 28 []DIO1 a
[e
02 14 27 [JSRQ 5 >
03 15 26 LJATN = |
Da 416 25 mil | |
05 17 24 Г) ЕС
о6 (18 23) RS? |
07419 220Rs1 |
NS
vss [420 21 LJ RSO
REGISTERS
T/RCONTROL
PP
vo
я ©
8291 INTERNAL BUS (DATA)
X
rm
MESSAGE
DECODER
а
Figure 5. 8291 Pin Configuration and Block Diagram
implement a GPIB controller when used with an
8291 Talker/ Listener. The 8041A is documented in
both a user’s manual and in AP-41. The following
description will serve only as an outline to guide the
later discussion.
The 8292 acts as an intelligent slave processor to the
main system CPU. It contains a processor, memory,
1/ О and is programmed to perform a variety of tasks
associated with GPIB controller operation. The on-
chip RAM is used to store information about the
state of the Controller function, as well as a variety
of local variables, the stack and certain user status
information. The timer/ counter may be optionally
used for several time-out functions or for counting
data bytes transferred. The I/O ports provide the
GPIB control signals, as well as the ancillary lines
necessary to make the 8291, 2, 3 work together.
The 8292 is closely coupled to the main CPU
through three on-chip registers that may be
independently accessed by both the master and the
8292 (UPI-41A). Figure 6 shows this Register
Interface. Also refer to Figure 12.
The status register 1s used to pass Interrupt Status
information to the master CPU (AO = | on a read).
The DBBOUT register is used to pass one of five
other status words to the master based on the last
command written into DBBIN. DBBOUT 1s accessed
when A0 = 0 on a Read. The five status words are
Error Flag, Controller Status, GPIB Status, Event
Counter Status or Time Out Status.
DBBIN receives either commands (AO = 1 on a
Write) or command related data (AO =0 on a write)
from the master. These command related data are
Interrupt Mask, Error Mask, Event Counter or
Time Out.
mm
)
\
(© Cr
od
< x ©
CPU к o E AO | DBBIN | UPI-41A
. o < zZ — >
[| Bt cs -
— RD _
WR || DBBOUT
cs AO RD WR REGISTER
0 0 0 1 READ DBBOUT
0 1 0 1 READ STATUS
0 0 1 0 WRITE DBBIN (DATA)
0 1 1 0 WRITE DBBIN (COMMAND)
1 X X X NO ACTION
Figure 6. UPI-41A Registers
8293 GPIB TRANSCEIVERS
The 8293 1s a multi-use HMOS chip that implements
the IEEE 488 bus transceivers and contains the
additional logic required to make the 8291 and 8292
work together. The two option strapping pins are
used to internally configure the chip to perform the
specialized gating required for use with 8291 as a
device or with 8291/92 as a controller.
In this application example the two configurations
used are shown in Fig. 7a and 7b. The drivers are set
to open collector or three state mode as required and
the special logic 1s enabled as required in the two
modes.
MODE 2
OPTA
+5
OPTB
NDAC NDAC*
NRFD NRFD *
T/R1
IFC IFC*
SYC
REN REN *
SRQ sra*
ATNI
— ATN*
ATN
E02 ЕО! *
ATNO
Ei
T/R2
ЕСС
CLTH
IC
Figure 7a. 8293 Mode 2
MODE 3 +5
— PT
ATNO OPTA
ЕСГ
ОРТВ
DAV s/R T/C Dav*
T/R1
DIO, mn та D101*
« р
DIO, Г J DIO2*
€ р
DIO; S/R T/C DIOS *
« y
DIO S/R T/C D1o4*
4 1
DIO; len vd 0105 *
>
DIO; S/R T/C D106 *
€ р
DIG, S/R T/C Dio7 *
L р
Diô | | *
8 S/R T/C Dios
Eol
ATN
Figure 7b. 8293 Mode 3
8291/2/3 CHIP SET
Figure 8 shows the four chips interconnected with
the special logic explicitly shown.
The 8291 acts only as the mechanism to put
commands and addresses on the bus while the 8292
is asserting ATN. The 8291 is tricked into believing
that the ATN line is not asserted by the ATN2
output of the ATN transceiver and 1s placed in Talk-
only mode by the CPU. The 8291 then acts as though
it 1$ sending data, when in reality it is sending
addresses and/or commands. When the 8292
deasserts ATN, the CPU software must place the
8291 in Talk-only, Listen-only or Idle based on the
implicit knowledge of how the controller 1s going to
participate in the data transfer. In other words, the
8291 does not respond directly to addresses or
commands that it sends on the bus on behalf of the
Controller. The user software, through the use of
Listen-only or Talk-only, makes the 8291 behave as
though 1t were addressed.
Although it is not a common occurrence, the GPIB
specification allows the Controller to set up a data
transfer between two devices and not directly
participate in the exchange. The controller must
know when to go active again and regain control.
The chip set accomplishes this through use of the
“Continuous Acceptor Handshake cycling mode”
and the ability to detect EOI or EOS at the end of the
transfer. See XFER in the Software Driver Outline
below.
If the 8292 1s not the System Controller as
determined by the signal on its SYC pin, then it must
be able to respond to an IFC within 100 usec. This 1s
accomplished by the cross-coupled NORs in Fig. 7a
which deassert the 8293s internal version of CIC
(Not Controller-in-Charge). This condition is latched
until the 8292’s firmware has received the IFCL
(interface clear received latch) signal by testing the
IFCL input. The firmware then sets its signals to re-
flect the inactive condition and clears the 8293’s latch.
In order for the 8292 to conduct a Parallel Poll the
8291 must be able to capture the PP response on the
DIO lines. The only way to do this is to fool the 8291
by putting it into Listen-only mode and generating a
DAV condition. However, the bus spec does not
allow a DAV during Parallel Poll, so the back-to-
back 3-state buffers (see Fig. 7b) in the 8293 isolate
the bus and allow the 8292 to generate a local DAV
for this purpose. Note that the 8291 cannot assert a
Parallel Poll response. When the 8292 1s not the
controller-in-charge the 8291 may respond to PPs
and the 8293 guarantees that the DIO drivers are in
“open collector” mode through the OR gate (Fig.
7b).
MODE 3 +5
OPTA
OPTB
DAV *
DIO1*
DIO2*
DIO3*
DIO4*
0105 *
DIOS *
DIO7 *
р108 *
ОРТА
ОРТВ
Figure 8. Talker/Listener/Controller
ZT7488/18 GPIB CONTROLLER
Ziatech’s GPIB Controller, the ZT7488/18 will be
used as the controller hardware in this Application
Note. The controller consists of an 8291, 8292, an 8
bit input port and TTL logic equivalent to that
shown in Figure 8. Figure 9 shows the card’s block
diagram. The ZT7488/18 plugs into the STD bus, a
56 pin 8 bit microprocessor oriented bus. An 8085
CPU card is also available on the STD bus and will
be used to execute the driver software.
The 8291 uses 1/0 Ports 60H to 67H and the 8292
uses 1/0 Ports 68 H and 69H. The five interrupt lines
are connected to a three-state buffer at I/O Port
6FH to facilitate polling operation. This is required
for the TCI, as it cannot be read internally in the
8292. The other three 8292 lines (SPI, IBF, OBF)
and the 8291's INT line are also connected to
minimize the number of 1/0 reads necessary to poll
the devices.
NDAC 1s connected to COUNT on the 8292 to allow
byte counting on data transfers. The example driver
software will not use this feature, as the software 1s
simpler and faster if an internal 8085 register is used
for counting in software.
3-STATE
DATA BUS
D0-D7 BUFFERS
ADDRESS
AO-A2
CLOCK*
RD*
wT
3-STATE
BUFFERS
SYS RESET"
10 EXP"
IORQ*
CARD
SELECT
PORT
SELECT
DECODER
ADDRESS co
A5-A7
ADDRESS
A3-A4
“INDICATES ACTIVE LOW LOGIC
DMA
CONNECTOR
INTERFACE
LOGIC
GPIB
CONNECTOR
TRANS-
CEIVERS
Figure 9. ZT7488/18 GPIB Controller
READ REGISTERS
“on Toe Tos [ow [on [on on [on
DATA IN
cer | APT | GET| END | DEC| ERR | Bo |B |
INTERRUPT STATUS 1
NT spas | LLO | REM | sPASC|LLOC | REMC ADSC
INTERRUPT STATUS 2
ENECENCNENCNENEN
SERIAL POLL STATUS
or | cor [coms [ ons [ia | va | man
ton
ADDRESS STATUS
| cPT7| сете | cers | сета | СРТЗ | ст? | сет! | сето |
COMMAND PASS THROUGH
|х | oro | DLO | ADS 0 AD4-0| AD3-0| К AD10
ADDRESS 0
| X | DT1 | Dt1 | as 1 AD4-1| AD3-1 AD2-1] ADI-1
ADDRESS 1
Figure 10.
PORT #
66H
61H
63H
65H
67H
WRITE REGISTERS
—
| DO7 | DO6 | DOS | DO4 | DO3 | DO2 | DO1 | DOO |
DATA OUT
“err [arr | сет | емо | оес | свя | во [ar |
INTERRUPT MASK 1
| DMAO| DMAI| SPASC| LLOC REMO] ADSC |
Le |
INTERRUPT MASK 2
[se [rw [se [es | 5 | |= |= |
SERIAL POLL MODE
| TO | LO | 0 o | 0 o | ADMI ADMO|
ADDRESS MODE
|
| смт?| смт! | CNTO| coma comal coma) сом1| сомо|
AUX MODE
Tans [or | ос | aos | ave | доз | ave | лот |
ADDRESS 0/1
| EC7 | eco | EC5 | eca | ЕСЗ | EC? | ЕСТ | eco |
EOS
8291 Registers
10
RST RD WR
-DO
ZOLA-ZOLA
A
RST RD WR
IBFI
OBFI
SPI
TCI
SRQ
REN
IFC
8292
COUNT
cic
EOI2
DAV
ATNI
ATNO
IFCL
CLTH A0
syc cs
8293 MODE 2
Figure 11. DMA/Interrupt GPIB Controller Block Diagram
The application example will not use DMA or
interrupts; however, the Figure 11 block diagram
includes these features for completeness.
The 8257-5 DMA chip can be used to transfer data
between the RAM and the 8291 Talker/ Listener.
This mode allows a faster data rate on the GPIB
and typically will depend on the 8291’s EOS or EOI
detection to terminate the transfer. The 8259-5
interrupt controller 1s used to vector the five possible
interrupts for rapid software handling of the various
conditions.
8292 COMMAND DESCRIPTION
This section discusses each command in detail and
relates them to a particular GPIB activity. Recall
that although the 8041 A has only two read registers
and one write register, through the magic of on-chip
firmware the 8292 appears to have six read registers
and five write registers. These are listed in Figure 12.
Please see the 8292 data sheet for detailed definitions
11
of each register. Note the two letter mnemonics to be
used in later discussions. The CPU must not write
into the 8292 while IBF (Input Buffer Full) is a one,
as information will be lost.
DIRECT COMMANDS
Both the Interrupt Mask (IM) and the Error Mask
(EM) register may be directly written with the LSB
of the address bus (A0) a “0”. The firmware uses the
MSB of the data written to differentiate between IM
and EM.
Load Interrupt Mask
This command loads the Interrupt Mask with
D7-D0. Note that D7 must be a “1” and that
interrupts are enabled by a corresponding “1” bit in
this register. IFC interrupt cannot be masked off;
however, when the 8292 is the System Controller,
sending an ABORT command will not cause an IFC
interrupt.
READ FROM 8292
INTERRUPT STATUS
SYC ERR | SRQ EV X IFCR IBF OBF
D7 Do
ERROR FLAG”
X X USER X X TOUT3| TOUT2| TOUT:
CONTROLLER STATUS”
CSBS | CA X X SYCS | IFC REN | SRQ
GPIB (BUS) STATUS”
REN | DAV EOI X SYC IFC | ANTI | SRQ
EVENT COUNTER STATUS”
D D D D D D D D
TIME OUT STATUS”
D D D D D D D D
PORT #
69H
68H
68H
68H
68H
68H
WRITE TO 8292
COMMAND FIELD
1 1 1 OP C C C C
INTERRUPT MASK
1 SPI TCI SYC OBFI IBFI 0 SRQ
D7 Do
ERROR MASK
0 0 USER 0 0 TOUTA| TOUT3| TOUT:
EVENT COUNTER*
D D D | D / D | D D D |
TIME OUT*
D D | D D | D D D D
*Note: These registers are accessed by a special utility command.
Figure 12. 8292 Registers
Load Error Mask
This command loads the Error Mask with D7-DO.
Note that D7 must be a zero and that interrupts are
enabled by a corresponding “1” bit in this register.
UTILITY COMMANDS
These commands are used to read or write the 8292
registers that are not directly accessible. All utility
commands are written with AO=1, D7=D6=D5=1,
D4 = 0. D3- DO specify the particular command. For
writing into registers the general sequence is:
|. wait for IBF = 0 in Interrupt Status Register
2. write the appropriate command to the 8292,
3. write the desired register value to the 8292 with
A0 = 1 with no other writes intervening,
4. wait for indication of completion from 8292
(IBF = 0).
For reading a register the general sequence is:
I. wait for IBF = 0 in Interrupt Status Register
2. write the appropriate command to the 8292
3. wait for a TCI (Task Complete Interrupt)
4. Read the value of the accessed register from the
8292 with AO = 0.
WEVC — Write to Event Counter
(Command = OE2H)
The byte written following this command will be
loaded into the event counter register and event
counter status for byte counting. The internal
12
counter 1s incremented on a high to low transition of
the COUNT (T1) input. In this application example
NDAC 1s connected to count. The counter 1s an 8 bit
register and therefore can count up to 256 bytes
(writing 0 to the EC implies a count of 256). Iflonger
blocks are desired, the main CPU must handle the
interrupts every 256 counts and carefully observe the
timing constraints.
Because the counter has a frequency range from 0 to
133 kHz when using a 6 MHz crystal, this feature
may not be usable with all devices on the GPIB. The
8291 can easily transfer data at rates up to 250 kHz
and even faster with some tuning of the system.
There is also a 500 ns minimum high time
requirement for COUNT which can potentially be
violated by the 8291 in continuous acceptor
handshake mode (1.e., TNDDV1 + TDVND2-C =
350 + 350 = 700 max). When cable delays are taken
into consideration, this problem will probably never.
occur.
When the 8292 has completed the command, IBF
will become a “0” and will cause an interrupt if
masked on.
WTOUT — Write to Time Out Register
(Command = OE1H)
The byte written following this command will be
used to determine the number of increments used for
the time out functions. Because the register is 8 bits,
the maximum time out 1s 256 time increments. This
is probably enough for most instruments on the
GPIB but is not enough for a manually stepped
operation using a GPIB logic analyzer like Ziatech’s
Z 1488. Also, the 488 Standard does not set a lower
limit on how long a device may take to do each
action. Therefore, any use of a time out must be able
to be overridden (this is a good general design rule
for service and debugging considerations).
The time out function is implemented in the 8292’s
firmware and will not be an accurate time. The
counter counts backwards to zero from its initial
value. The function may be enabled/disabled by a
bit in the Error mask register. When the command is
complete IBF will be set to a “0” and will cause an
interrupt if masked on.
REVC — Read Event Counter Status
(Command = OE3H)
This command transfers the content of the Event
Counter to the DBBOUT register. The firmware
then sets TCI = 1 and will cause an interrupt if
masked on. The CPU may then read the value from
the 8292 with AO = 0.
RINM — Read Interrupt Mask Register
(Command = OESH)
This command transfers the content of the Interrupt
Mask register to the DBBOUT register. The
firmware sets TCI = 1 and will cause an interrupt if
masked on. Ihe CPU may then read the value.
RERM — Read Error Mask Register
(Command = OEAH)
This command transfers the content of the Error
Mask register to the DBBOUT register. The
firmware sets TCI = 1 and will cause an interrupt if
masked on. The CPU may then read the value.
RCST — Read Controller Status Register
(Command = OE6H)
This command transfers the content of the Con-
troller Status register to the DBBOUT register. The
firmware sets TCI = I and will cause an interrupt if
masked on. The CPU may then read the value.
RTOUT — Read Time Out Status Register
(Command = OE9H)
This command transfers the content of the Time Out
Status register to the DBBOUT register. The
firmware sets TCI = 1 and will cause an interrupt if
masked on. The CPU may then read the value.
If this register is read while a time-out function is in
process, the value will be the time remaining before
time-out occurs. If it 1s read after a time-out, it will
be zero. If it is read when no time-out is in process, it
will be the last value reached when the previous
timing occurred.
13
RBST — Read Bus Status Register
(Command = OE7H)
This command causes the firmware to read the
GPIB management lines, DAV and the SYC pin and
place a copy in DBBOUT. TCI is set to “1” and will
cause an interrupt if masked on. The CPU may read
the value.
RERF — Read Error Flag Register
(Command = OE4H)
This command transfers the content of the Error
Flag register to the DBBOUT register. The firmware
sets TCI = | and will cause an interrupt if masked on.
The CPU may then read the value.
This register is also placed in DBBOUT byan IACK
command if ERR remains set. TCI 1s set to “1” in
this case also. |
[ACK — Interrupt Acknowledge
(Command = Al A2 A3 A4 1 AS | 1)
This command is used to acknowledge any combina-
tions of the five SPI interrupts (Al-AS5): SYC,
ERR, SRQ, EV, and IFCR. Each bit AI-AS5 1$ ап
individual acnowledgement to the corresponding bit
in the Interrupt Status Register. The command
clears SPI but it will be set again if all of the pending
interrupts were not acknowledged.
If A2 (ERR) is “1”, the Error Flag register is placed
in DBBOUT and TCI is set. The CPU may then read
the Error Flag without issuing an RERF command.
OPERATION COMMANDS
The following diagram (Fig. 13) is an attempt to
show the interrelationships among the various 8292
Operation Commands. It is not meant to replace the
complete controller state diagram in the IEEE
Standard.
RST — Reset (Command = OF2H)
This command has the same effect as an external
reset applied to the chip’s pin #4. The 8292°s actions
are:
|. All outputs go to their electrical high state. This
means that SPI, TCI, OBFI, IBFI, CLTH will be
TRUE and all other GPIB signals will be FALSE.
2. The 829?'s firmware will cause the above men-
tioned five signals to go FALSE after approxi-
mately 17.5 usec. (at 6 MHz).
3. These registers will be cleared: Interrupt Status,
Interrupt Mask, Error Mask, Time Out, Event
Counter, Error Flag.
4. If the 8292 1s the System Controller (SYC 1$
TRUE), then IFC will be sent TRUE forapproxi-
mately 100 usec and the Controller function will
end up in charge of the bus. If the 8292 is not the
TT TT TT q
(RST + ABORT) ® SYC | SPCNI
STCNI
|1 I GTSB _ |
TCNTR | > GSEC |
RST. SYC — IDLE GIDL | ACTIVE — TesY STANDBY
| — TCAS |
bs EXPP |
| PARALLEL |
POLL |
| — —CONTROLLER-IN.CHARGE _
rr TT —]
| SREM _ |
RST + ло
| ABOIT. EYE ————»| LOCAL sLoc | REMOTE |
| — — — -— -_SYSTEMCONTROLER — _ |
Figure 13. 8292 Command Flowchart
System Controller then 1t will end up in an Idle
state.
5. TCI will not be set.
RSTI — Reset Interrupts (Command = OF3)
This command clears all pending interrupts and
error flags. The 8292 will stop waiting for actions to
occur (e.g., waiting for ATN to go FALSE in a
TCNTR command or waiting for the proper
handshake state ina TCSY command). TCI will not
be set.
ABORT — Abort all operations and Clear Interface
(Command = OF9H)
If the 8292 1s not the System Controller this
command acts like a NOP and flags a USER
ERROR in the Error Flag Register. No TCI will
occur.
If the 8292 1s the System Controller then IFC is set
TRUE for approximately 100 usec and the 8292
becomes the Controller-in-Charge and asserts ATN.
TCI will be set, only if the 8292 was NOT the CIC.
STCNI — Start Counter Interrupts
(Command = OFEH)
Enables the EV Counter Interrupt. TCI will not be
set. Note that the counter must be enabled by a GSEC
command.
SPCNI — Stop Counter Interrupts
(Command = OFOH)
The 8292 will not generate an EV interrupt when the
counter reaches 0. Note that the counter will
continue counting. TCI will not be set.
SREM — Set Interface to Remote Control
(Command = OF8H)
If the 8292 1s the System Controller, it will set REN
14
and TCI TRUE. Otherwise it only sets the User
Error Flag.
SLOC — Set Interface to Local Mode
(Command = OF7H)
If the 8292 is the System Controller, it will set REN
FALSE and TCI TRUE. Otherwise, it only sets the
User Error Flag.
EX PP — Execute Parallel Poll
(Command = OF5H)
If not Controller-in-Charge, the 8292 will treat this
as a NOP and does not set TCI. If it is the Control-
ler-in-Charge then it sets IDY (FOI & ATN) TRUE
and generates a local DAV pulse (that never reaches
the GPIB because of gates in the 8293). If the 8291 is
configured as a listener, 1t will capture the Parallel
Poll Response byte in its data register. TCI is not
generated, the CPU must detect the BI (Byte In)
from the 8291. The 8292 will be ready to accept
another command before the BI occurs; therefore
the 8291's BI serves as a task complete indication.
GTSB — Go To Standby (Command = OF6H)
If the 8292 is not the Controller-in-Charge, it will
treat this command as a NOP and does not set TCI
TRUE. Otherwise, it goes to Controller Standby
State (CSBS), sets ATN FALSE and TCI TRUE.
This command is used as part of the Send, Receive,
Transfer and Serial Poll System commands (see
next section) to allow the addressed talker to send
data/ status.
If the data transfer does not start within the specified
Time-Out, the 8292 sets TOUT2 TRUE in the Error
Flag Register and sets SPI (if enabled). The
controller continues waiting for a new command.
The CPU must decide to wait longer or to regain
control and take corrective action.
GSEC — Go to Standby and Enable Counting
(Command = OF4H)
This command does the same things as GTSB but
also initializes the event counter to the value pre-
viously stored in the Event Counter Register (default
value is 256) and enables the counter. One may wire
the count input to NDAC to count bytes. When the
counter reaches zero, it sets EV (and SPI if enabled)
in Interrupt Status and will set EV every 256 bytes
thereafter. Note that there is a potential loss of
count information if the CPU does not respond to
the EV/SPI before another 256 bytes have been
transferred. TCI will be set at the end of the
command.
TCS Y — Take Control Synchronously
(Command = OFDH)
If the 8292 1s not in Standby, it treats this command
as a NOP and does not set TCI. Otherwise, it waits
for the proper handshake state and sets ATN
TRUE. The 8292 will set TOUT3 1f the handshake
never assumes the correct state and will remain in
this command until the handshake is proper or a
RSTI command is issued. If the 8292 successfully
takes control, 1t sets TCI TRUE.
This 1s the normal way to regain controlat the end of
a Send, Receive, Transfer or Serial Poll System
Command. If TCSY 1s not successful, then the
controller must try TCAS (see warning below).
TCAS — Take Control Asynchronously
(Command = OFCH)
If the 8292 is not in Standby, it treats this command
as a NOP and does not set TCI. Otherwise, it
arbitrarily sets ATN TRUE and TCI TRUE. Note
that this action may cause devices on the bus to lose
a data byte or cause them to interpret a data byteasa
command byte. Both Actions can result in anoma-
lous behavior. TCAS should be used only in
emergencies. If TCAS fails, then the System
Controller will have to issue an ABORT to clean
things up.
GIDL — Go to Idle (Command = OF1H)
If the 8292 1s not the Controller in Charge and
Active, then 1t treats this command as a NOP and
does not set TCI. Otherwise, 1t sets ATN FALSE,
becomes Not Controller in Charge, and sets TCI
TRUE. This command 1s used as part of the Pass
Control System Command.
TCNTR — Take (Receive) Control
(Command = OFAH)
If the 8292 1s not Idle, then 1t treats this command as
a NOP and does not set TCI. Otherwise, 1t waits for
the current Controller-in-Charge to set ATN
FALSE. If this does not occur within the specified
Time Out, the 8292 sets TOUT in the Error Flag
Register and sets SPI (if enabled). it will not proceed
until ATN goes false or it receives an RSTI
command. Note that the Controller in Charge must
previously have sent this controller (via the 8291's
command pass through register) a Pass Control
message. When ATN goes FALSE, the 8292 sets
CIC, ATN and TCI TRUE and becomes Active.
SOFTWARE DRIVER OUTLINE
The set of system commands discussed below is
shown in Figure 14. These commands are imple-
mented in software routines executed by the main
CPU.
The following section assumes that the Controller is
the System Controller and will not Pass Control.
This 1s a valid assumption for 99+% of all
controllers. It also assumes that no DMA or
Interrupts will be used. SYC (System Control Input)
15
should not be changed after Power-on in any system
— 1t adds unnecessary complexity to the CPU’s
software.
In order to use polling with the 8292 one must enable
TCI but not connect the pin to the CPU’s interrupt
pin. TCI must be readable by some means. In this
application example it is connected to bit | port 6FH
on the ZT7488/ 18. In addition, the other three 8292
interrupt lines and the 8291 interrupt are also on that
port (SPI-Bit 2, IBFI-Bit 4, OBFI-Bit 3, 8291 INT-
Bit 0).
These drivers assume that only primary addresses
will be used on the GPIB. To use secondary
addresses, one must modify the test for valid
talk/listen addresses (range macro) to include
secondaries.
INIT INITIALIZATION
Talker/Listener
SEND SEND DATA
RECV RECEIVE DATA
XFER TRANSFER DATA
Controller
TRIG GROUP EXECUTE TRIGGER
DCLR DEVICE CLEAR
SPOL SERIAL POLL
PPEN PARALLEL POLL ENABLE
PPDS PARALLEL POLL DISABLE
PPUN PARALLEL POLL UNCONFIGURE
PPOL PARALLEL POLL
PCTL PASS CONTROL
RCTL RECEIVE CONTROL
SRQD SERVICE REQUESTED
System Controller
REME REMOTE ENABLE
LOCL LOCAL
IFCL ABORT/INTERFACE CLEAR
Figure 14. Software Driver Routines
INITIALIZATION
8292 — Comes up in Controller Active State when
SYC is TRUE. The only initialization needed is to
enable the TCI interrupt mask. This is done by
writing OAOH to Port 68H.
829] — Disable both the major and minor addresses
because the 8291 will never see the 8292’s com-
mands /addresses (refer to earlier hardware discus-
sion). This is done by writing 60H and OEOH to
Port 66H.
Set Address Mode to Talk-only by writing 80H to
Port 64H.
Set internal counter to 3 MHz to match the clock
input coming from the 8085 by writing 23H to Port
65H. High speed mode for the handshakes will not
be used here even though the hardware uses three-
state drivers.
No interrupts will be enabled now. Each routine will
enable the ones it needs for ease of polling operation.
The INT bit may be read through Port 6FH. Clear
both interrupt mask registers.
Release the chip’s initialization state by writing 0 to
Port 65H.
INIT:
Enable-8292
Enable TCI
Enable-8291
Disable major address
Disable minor address
ton
Clock frequency
All interrupts off
Immediate execute pon
¡Set up Int. pins for Port 6FH
;Task complete must be on
¡In controller usage, the 8291
¡Is set to talk only and/or listen only
; Talk only is our rest state
;3 MHz in this ap note example
¡Releases 8291 from init. state
TALKER/LISTENER ROUTINES
Send Data
SEND < listener list pointer > <count> <EOS > <data buffer pointer >
This system command sends data from the CPU to
one or more devices. The data is usually a string of
ASCII characters, but may be binary or other forms
as well. The data 1s device-specific.
My Talk Address (MTA) must be output to satisfy
the GPIB requirement of only one talker at a time
(any other talker will stop when MTA goes out). The
MTA is not needed as faras the 8291 is concerned —
it will be put into talk-only mode (ton).
This routine assumes a non-null listener list in that it
always sends Universal Unlisten. If it 1s desired to
send data to the listeners previously addressed, one
could add a check for a null list and not send UNL.
Count must be 255 or less due to an 8 bit register.
This routine also always uses an EOS character to
terminate the string output; this could easily be
eliminated and rely on the count. Items in brackets
() are optional and will not be included in the actual
code in Appendix A.
SEND:
Output-to-8291 MTA, UNL
Put EOS into 8291
While 20H < listener < 3EH
output-to-8291 listener
Increment listen list pointer
Output-to-8292 GTSB
Enable-8291
Output EOI on EOS sent
If count < > 0 then
While not (end or count = 0)
(could check tout 2 here)
Output-to-8291 data
Increment data buffer pointer
Decrement count
Output-to-8292 TCSY
(If tout3 then take control async)
Enable 8291
No output FOI on EOS sent
Return
¡We will talk, nobody listen
¡End of string compare character
:GPIB listen addresses are
“space” thru “>” ASCII
¡Address all listeners
¡8292 stops asserting ATN, go to standby
¡Send EOI along with EOS character
¡Wait for EOS or end of count
¡Optionally check for stuck bus-tout 2
;Output all data, one byte at a time
:8085 CREG will count for us
8292 asserts ATN, take control sync.
¡If unable to take control sync.
¡Restore 8291 to standard condition
| ВЕСУ 1
IN INTI
SAVE IN B
MOV AB
IN INT1
IN DIN
IN DIN
STAX D STAX D
DCR С DCR 9 €
B = 40H — >
У ВЕСУ 5
TCSY
Figure 15. Flowchart For Receive Ending Conditions
Receive Data
CONTROLLER
8291,8292
DEVICE
DEVICE
DEVICE
Figure 16. SEND to “1”, 72”, ”>"; “ABCD”; EOS = “D”
RECV <talker> <count> <EOS> <data buffer pointer>
This system command is used to input data from a
device. The data 1s typically a string of ASCII
characters.
This routine is the dual of SEND. It assumes a new
talker will be specified, a count of less than 257, and
an EOS character to terminate the input. EOI
received will also terminate the input. Figure 15
shows the flow chart for the RECV ending
conditions. My Listen Address (MLA) is sent to
keep the GPIB transactions totally regular to
17
facilitate analysis by a GPIB logic analyzer like the
Ziatech ZT488. Otherwise, the bus would appear to
have no listener even though the 8291 will be
listening.
Note that although the count may go to zero before
the transmission ends, the talker will probably be
left in a strange state and may have to be cleared by
the controller. The count ending of КЕСУ 1$
therefore used as an error condition in most
situations.
RECYV:
Put EOS into 8291 ;End of string compare character
If 40H < talker < SEH then ¡GPIB talk addresses are
Output-to-8291 talker “@” thru “A” ASCII
Increment talker pointer ;Do this for consistency’s sake
Output-to-8291 UNL, MLA ¡Everyone except us stop listening
Enable-8291
Holdoff on end ¡Stop when EOS character 15
End on EOS received ¡Detected by 8291
lon, reset ton ¡Listen only (no talk)
Immediate execute pon
Output-to-8292 GTSB :8292 stops asserting ATN, go to standby
While not (end or count = 0 (or tout2)) ¡walt for EOS or EOI or end of count
soptionally check for stuck bus-tout2
Input-from-8291 data ¡input data, one byte at a time
Increment data buffer pointer
Decrement count ¡Use 8085 C register as counter
(If count = 0 then error) :Count should not occur before end
Output-to-8292 TCSY :8292 asserts ATN take control
(If Tout3 then take control async.) ¡If unable to take control sync.
Enable-8291 ¡Put 8291 back as needed for
No holdoff on end ¡Controller activity and
No end on EOS received ¡Clear holdoff due to end
ton, reset lon
Finish handshake ¡Complete holdoff due to end, 1f any
Immediate execute pon ¡Needed to reset lon
Return error-indicator
CONTROLLER CONTROLLER
8291,8292 8291,8292
TALK LSTN TALK
CTLR “A” “ps CTLA “a”
DEVICE DEVICE
LSTN TALK
“1 ” “ »”
DEVICE DEVICE
TALK
RP
DEVICE DEVICE
LSTN TALK TALK
DEVICE DEVICE
LSTN TALK
des An
Figure 17. RECV from “R”; EOS = ODH Figure 18. XFER from “A” to “1”, “2”, “+”; EOS = ODH
18
Transfer Data
XFER < Talker > < Listener list> < EOS >
This system command 1s used to transfer data froma
talker to one or more listeners where the controller
does not participate in the transfer of the ASCII
data. This 1s accomplished through the use of the
8291's continuous acceptor handshake mode while
in listen-only.
This routine assumes a device list that has the ASCII
talker address as the first byte and the string (one or
more) of ASCII listener addresses following. The
EOS character or an EOI will cause the controller to
take control synchronously and thereby terminate
the transfer.
XFER:
Output-to-8291: Talker, UNL
While 20H < listen < 3EH
Output-to-8291: Listener
Increment listen list pointer
Enable-8291
lon, no ton
Continuous AH mode
End on EOS received
Immediate execute PON
Put EOS into 8291
Output-to-8292: GTSB
Upon end (or tout2) then
Take control synchronously
Enable-8291
Finish handshake
Not continuous AH mode
Not END on EOS received
ton
Immediate execute pon
Return
:Send talk address and unlisten
:Send listen address
¡Controller 1s pseudo listener
;Handshake but don’t capture data
;Capture EOS as well as EOI
Initialize the 8291
¡Set up EOS character
¡Go to standby
8292 waits for EOS or EOI and then
¡Regains control
¡Go to Ready for Data
CONTROLLER
Group Execute Trigger
TRIG < Listener list >
This system command causes a group execute
trigger (GET) to be sent to all devices on the listener
list. The intended use is to synchronize a number of
instruments.
TRIG:
Output-to-8291 UNL
While 20H < listener < 3EH
Output-to-8291 Listener
Increment listen list pointer
Output-to-8291 GET
Return
;Everybody stop listening
¡Check for valid listen address
:Address each listener
; Terminate on any non-valid character
¡Issue group execute trigger
CONTROLLER
8291,8292
DEVICE
DEVICE
DEVICE
DEVICE
Figure 19. TRIG “17, “+”
CONTROLLER
8291,8292
TALK
LSTN
“ep
DEVICE
LS TALK
Enea “a”
DEVICE
TALK
“AR”
DEVICE
LSTN TALK
hy “К”
DEVICE
LSTN TALK
> “A”
Figure 20. DCLR “1”, “2”
Device Clear
DCLR < Listener list >
This system command causes a device clear (SDC)
to be sent to all devices on the listener list. Note
that this 1s not intended to clear the GPIB interface
of the device, but should clear the device-specific
logic.
DCLR:
Output-to-8291 UNL
While 20H < Listener < 3EH
Output-to-8291 listener
Increment listen list pointer
Output-to-8291 SDC
Return
;Everybody stop listening
¡Check for valid listen address
¡Address each listener
; Terminate on any non-valid character
Selective device clear
Serial Poll
SPOL <Talker list> < status buffer pointer >
This system command sequentially addresses the
designated devices and receives one byte of status
from each. The bytes are stored in the buffer in the
same order as the devices appear on the talker list.
MLA is output for completeness.
20
SPOL: |
Output-to-8291 UNL, MLA, SPE ;Unlisten, we listen, serial poll enable
¡Only one byte of serial poll
;Status wanted from each talker
While 40H < talker < SEH :Check for valid transfer
Output-to-8291 talker ¡Address each device to talk
Increment talker list pointer ¡One at a time
Enable-8291
lon, reset ton ¡Listen only to get status
Immediate execute pon ; This resets ton
Output-to-8292 GTSB ¡Go to standby
Wait for data in (BI) ¡Serial poll status byte into 8291
Output-to-8292 TCS Y ; Take control synchronously
Input-from-8291 data ¡Actually get data from 8291
Increment buffer pointer
Enable 8291
ton, reset lon
Immediate execute pon ;Resets lon
Output-to-8291 SPD Send serial poll disable after all devices polled
Return
CONTROLLER CONTROLLER
8291,8292 8291,8292
TALK TT т
CTLR “A” : ©
DEVICE DEVICE
noni rare reee > LSTN TALK
i or
DEVICE
PE ESAS TALK
Te no “В”
DEVICE
É LSTN TALK
| мнений * “K”
DEVICE
FRERE >
É ans à LSTN TALK
: E “om SA»
Figure 21. SPOL “Q”, “R”, “K”, “ A” Figure 22. PPEN “2”; iP;P,P, = 0111B
Parallel Poll Enable
PPEN < Listener list> < Configuration Buffer pointer >
This system command configures one or more list. The configuration byte has the format
devices to respond to Parallel Poll, assuming they XXXXIP3P2P1 as defined by the IEEE Std. P3P2P1
implement subset PP1. The configuration informa- indicates the bit # to be used for a response and |
tion 1s stored in a buffer with one byte per device indicates the assertion value. See Sec. 2.9.3.3 of the
in the same order as devices appear on the listener Std. for more details.
21
PPEN:
Output-to-8291 UNL
While 20H < Listener < 3EH
Output-to-8291 listener
Output-to-8291 PPC, (PPE or data)
Increment listener list pointer
Increment buffer pointer
Return
:Universal unlisten
:Check for valid listener
:Stop old listener, address new
:Send parallel poll info
‘Point to next listener
;One configuration byte per listener
Parallel Poll Disable
PPDS < listener list >
This system command disables one or more devices
from responding to a Parallel Poll by issuing a
Parallel Poll Disable (PPD). It does not decon-
figure the devices.
PPDS:
Output-to-8291 UNL
While 20H < Listener < 3EH
Output-to-8291 listener
Increment listener list pointer
Output-to-8291 PPC, PPD
:Universal Unlisten
:Check for valid listener
:Address listener
‘Disable PP on all listeners
Return
CONTROLLER CONTROLLER
8291,8292
8291,8292
DEVICE
DEVICE
DEVICE
DEVICE
Figure 23. PPDS “1”, “+”, “>”
22
DEVICE
LSTN TALK
“q” “Q”
DEVICE
DEVICE
DEVICE
Figure 24. PPUN
Parallel Poll Unconfigure
PPUN
This system command deconfigures the Parallel Poll
response of all devices by issuing a Parallel Poll
Unconfigure message.
PPUN:
Output-to-8291 PPU
Return
;Unconfigure all parallel poll
Conduct a Parallel Poll
PPOL
This system command causes the controller to con-
duct a Parallel Poll on the GPIB for approximately
12.5 usec (at 6 MHz). Note that a parallel poll does
not use the handshake; therefore, to ensure that the
device knows whether or not its positive response
was observed by the controller, the CPU should
explicitly acknowledge each device by a device-
dependent data string. Otherwise, the response bit
will still be set when the next Parallel Poll occurs.
This command returns one byte of status.
PPOL:
Enable-8291
lon
Immediate execute pon
Output-to-8292 EXPP
Upon BI
Input-from-8291 data
Enable-8291
ton
Immediate execute pon
Return Data (status byte)
;Listen only
: This resets ton
;Execute parallel poll
¡When byte is input
¡Read 1t
; Talk only
This resets lon
Pass Control
PCTL <talker >
This system command allows the controller to
relinquish active control of the GPIB to another
controller. Normally some software protocol should
already have informed the controller to expect this,
and under what conditions to return control. The
8291 must be set up to become a normal device
and the CPU must handle all commands passed
through, otherwise control cannot be returned (see
Receive Control below). The controller will go idle.
PCTL:
It 40H < talker < SEH then
if talker < > MTA then
output-to-8291 talker, TCT
Enable-8291
not ton, not lon
Immediate execute pon
My device address, mode |
Undefined command pass through
(Parallel Poll Configuration)
Output-to-8292 GIDL
Return
;Cannot pass control to myself
; Take control message to talker
¡Set up 8291 as normal device
¡Reset ton and lon
;Put device number in Register 6
;Required to receive control
;Optional use of PP
¡Put controller in idle
CONTROLLER
8291,8292
TALK
“A”
=| 2
ЗЕ
В DIO 1 DEVICE
—»] LSTN TALK
“q” “Q”
DIO 2 DEVICE
»| LSTN TALK
“2” “R”
- DIO 3 DEVICE
>| LSTN TALK
s“ “К”
DEVICE
a LSTN TALK
“>” “A”
Figure 25. PPOL
Receive Control
RCTL
This system command 1s used to get control back
from the current controller-in-charge if it has passed
control to this inactive controller. Most GPIB
systems do not use more than one controller and
therefore would not need this routine.
To make passing and receiving control a man-
ageable event, the system designer should specify a
CONTROLLER
8291,8292
DEVICE
LSTN TALK
1 Q
DEVICE
> LSTN TALK
2 R
DEVICE
> LSTN TALK
yn “К”
DEVICE
> LSTN TALK
> “A”
LSTN CTLR
“a”
CONTROLLER
Figure 26. PCTL “C”
protocol whereby the controller-in-charge sends a
data message to the soon-to-be-active controller.
This message should give the current state of the
system, why control 1s being passed, what to do,
and when to pass control back. Most of these issues
are beyond the scope of this Ap Note.
RCTL:
Upon CPT
If (command=TCT) then
If TA then
Enable-8291
Disable major device number
ton
Mask off interrupts
Immediate execute pon
;Wait for command pass through bit in 8291
:If command 1s take control and
:We are talker addressed
¡Controller will use ton and lon
; Talk only mode
Output-to-8292 TCNTR ;Take (receive) control
Enable-829 1
Valid command ¡Release handshake
Return valid
Else
Enable-8291
Invalid command ¡Not talker addr. so TCT not for us
Else
Enable-8291
Invalid command :Not TCT, so we don’t care
Return invalid
SYSTEM
CONTROLLER CONTROLLER
8291,8292 8291,8292
WEN стя | TALK
«<
Wu
aC
DEVICE
> N DEVICE
LSTN TALK LSTN TALK
“т” “а” 4 “а”
DEVICE
> _ DEVICE
LSTN TALK LSTN TALK
“2” “В” “2” “В”
DEVICE
> > DEVICE
LSTN TALK LSTN TALK
yn “К” 6,99 “К”
DEVICE
> DEVICE
LSTN TALK LSTN TALK
se» “A E “д”
CONTROLLER
Figure 27. RCTL Figure 28. REME
Service Request
SROD
This system command is used to detect the occur- the CPU would normally conduct a Serial Poll
rence of a Service Request on the GPIB. One or after calling this routine to determine which devices
more devices may assert SRQ simultaneously, and are SRQing.
25
SROD:
If SRQ then
Output-to-8292 IACK.SRQ
Return SRQ
Else return no SRQ
:Test 92 status bit
;Acknowledge 1t
SYSTEM CONTROLLER
Remote Enable
REME
This system command asserts the Remote Enable
line (REN) on the GPIB. The devices will not go
remote until they are later addressed to listen by
some other system command.
REME:
Output-to-8292 SREM
Return
:8292 asserts remote enable line
Local
LOCL
This system command deasserts the REN line on the
GPIB. The devices will go local immediately.
LOCL:
Output-to-8292 SLOC ¡8292 stops asserting remote enable
Return
SYSTEM |
SYSTEM
CONTROLLER CONTROLLER
8291,8292
DEVICE
LSTN TALK
“q” “Q”
DEVICE
LSTN TALK
но” “R”
DEVICE
LSTN TALK
4” YK”
DEVICE
LSTN TALK
ня) “A
Figure 29. LOCL
IFC
DEVICE
LSTN TALK
“qr “Q”
DEVICE
LSTN TALK
“2” “R”
DEVICE
LSTN
649
DEVICE
LSTN TALK
“>” “A”
Figure 30. IFCL
26
Interface Clear/ Abort
IFCL
This system command asserts the GPIB’s Interface
Clear (IFC) line for at least 100 microseconds.
This causes all interface logic in all devices to go to
a known state. Note that the device itself may or
may not be reset, too. Most instruments do totally
reset upon IFC. Some devices may require a DCLR
as well as an IFCL to be completely reset. The
(system) controller becomes Controller-in-Charge.
IFCL:
Output-to-8292 ABORT
Return
:8292 asserts Interface Clear
:For 100 microseconds
INTERRUPTS AND
DMA CONSIDERATIONS
The previous sections have discussed in detail how
to use the 8291, 8292, 8293 chip set as a GPIB
controller with the software operating in a polling
mode and using programmed transfer of the data.
This is the simplest mode of use, but it ties up the
microprocessor for the duration of a GPIB transac-
tion. If system design constraints do not allow this,
then either Interrupts and/or DMA may be used to
free up processor cycles.
The 8291 and 8292 provide sufficient interrupts that
one may return to do other work while waiting for
such things as 8292 Task Completion, 8291 Next
Byte In, 8291 Last Byte Out, 8292 Service Request
In, etc. The only difficulty lies in integrating these
various interrupt sources and their matching
routines into the overall system’s interrupt structure.
This 1s highly situation-specific and is beyond the
scope of this Ap Note.
The strategy to follow is to replace each of the WAIT
routines (see Appendix A) with a return to the main
code and provide for the corresponding interrupt to
bring the control back to the next section of GPIB
code. For example WAITO (Wait for Byte Out of
8291) would be replaced by having the BO interrupt
enabled and storing the (return) address of the next
Instruction in a known place. This co-routine
structure will then be activated by a BO interrupt.
Fig. 31 shows an example of the flow of control.
MAIN CODE INTERRUPT CODE GPIB SUBROUTINE
USER: SEND:
mare Un —
SEND (WAIT O)
z
o A
U
IH
W
€
>
=
©
z
-
©
9
о
о
|
O
9
<
>
=
©
INT:
m
À
O
"GPIB BO
GPIB TCI?
—
AA
li
|
=
ЩЕ
+4
3
m
+
O
Figure 31. GPIB Interrupt & Co-Routine Flow of Control
DMA is also useful in relieving the processor if the
average length of a data buffer is long enough to
overcome the extra time used to set upa DMA chip.
This decision will also be a function of the data rate
of the instrument. The best strategy is to use the
DMA to handle only the data buffer transfers on
SEND and RECV and to do all the addressing and
control just as shown in the driver descriptions.
Another major reason for using a DMA chip is to
increase the data rate and therefore increase the
overall transaction rate. In this case the limiting
factor becomes the time used to do the addressing
and control of the GPIB using software like that in
Appendix A. The data transmission time becomes
insignificant at DMA speeds unless extremely long
buffers are used.
Refer to Figure 11 for a typical DMA and interrupt
based design using the 8291, 8292, 8293. A system
like this can achieve a 250K byte transfer rate while
under DMA control.
APPLICATION EXAMPLE
This section will present the code required to operate
a typical GPIB instrument set up as shown in Fig.
32. The HP5328A universal counter and the
HP3325 function generator are typical of many
GPIB devices; however, there are a wide variety of
software protocols to be found on the GPIB. The
Ziatech ZT488 GPIB analyzer 1s used to single step
the bus to facilitate debugging the system. It also
serves as a training/familiarization aid for new-
comers to the bus.
This example will set up the function generator to
output a specific waveform, frequency and ampli-
tude. It will then tell the counter to measure the
frequency and Request Service (SRQ) when com-
plete. The program will then read in the data. The
assembled source code will be found at the end of
Appendix A.
ZT7488/18
CONTROLLER
LSTN TALK
“p CTLR “A”
HP 5328A
COUNTER
LSTN TALK
“q” “Q”
HP 3325A
FUNCTION
GENERATOR
LSTN TALK
“2” “R”
ZT488
GPIB ANALYZER
Figure 32. GPIB Example Configuration
SEND
LSTN: “2”, COUNT: 15, EOS: ODH, DATA: “FUIFR37KHAM2V0 (CR)”
SETS UP FUNCTION GEN. TO 37 KHZ SINE, 2 VOLTS PP
; COUNT EQUAL TO # CHAR IN BUFFER
"EOS CHARACTER IS (CR) = 0DH = CARRIAGE RETURN
SEND
LSTN: “1”, COUNT: 6, EOS: “T” DATA: “PR4G71”
SETS UP COUNTER FOR P:INITIALIZE, F4: FREQ CHAN À
G7:0.1 HZ RESOLUTION, T: TRIGGER AND SRQ
¡COUNT IS EQUAL TO # CHAR
WAIT FOR SRQ
SPOL TALK: “Q”, DATA: STATUS |
:CLEARS THE SRO —IN THIS EXAMPLE ONLY FREQ CTR ASSERTS SRQ
RECV TALK: “Q”, COUNT: 17, EOS: OAH,
DATA: “+ 37000.0E+0” (CR) (LF)
¡GETS 17 BYTES OF DATA FROM COUNTER
¡COUNT IS EXACT BUFFER LENGTH
; DATA SHOWN IS TYPICAL HP5328A READING THAT WOULD BE RECEIVED
CONCLUSION
This Application Note has shown a structured way
to view the IEEE 488 bus and has given typical code
sequences to make the Intel 8291, 8292, and 8293’s
behave as a controller of the GPIB. There are other
ways to use the chip set, but whatever solution is
chosen, it must be integrated into the overall system
software.
The ultimate reference for GPIB questions is the
IEEE Std 488, -1978 which is available from IEEE,
345 East 47th St., New York, NY, 10017. The ulti-
mate reference for the 8292 is the source listing for it
(remember it’s a pre-programmed UPI-41A) which
is available from INSITE, Intel Corp., 3065 Bowers
Ave., Santa Clara, CA 95051.
APPENDIX A
ISIS-II 8080/8085 MACRO ASSEMBLER,
GPIR CONTROLLER SUBROUTINES
V3.0
LOC OBJ LINE SOURCE STATEMENT
1 STITLE ('GPIB CONTROLLER SUBROUTINES')
2 ; |
3 ; GPIB CONTROLLER SUBROUTINES
4
5 ;
6 ; for Intel 8291, 8292 on ZT 7488/18
7; Bert Forbes, Ziatech Corporation
8 ; 2410 Broad Street
9 San Luis Obispo, CA, USA 93401
19 ;
11 ;
12 ; General Definitions & Equates
13 ; 8291 Control Values
14 ;
1009 15 ORG 19998 ; For 2T7483/18 w/8985
16 ;
09050 17 PRT91 EQU 6UH ;8291 Base Port |
18 ;
19 ; Reg #9 Data in & Data out
0069 20 DIN EQU PRT91+% ;91 Data in reg
0060 21 DOUT EQU PRT91+3 ;91 Data out reg
22 ;
23 ; Reg # 1 Interrupt 1 Constants
9051 24 INTI EQU PRT91+1 ; INT Reg 1
0861 25 INTM1 EQU PRT91+1 ;INT Mask Reg. 1
0002 26 BOM EQU 02 ;91 BO INTRP Mask
9081 27 BIM EQU gl :91 BI INTRP Mask
9010 28 ENDMK EQU 10H 91 END INTRP Mask
0089 29 CPT EQU 83H ¿91 command pass thru int hit
30 ;
31 ; Reg #2 Interrupt 2
0062 32 INT2 EQU PRT91+2
33 ;
34 ; Reg #4 Address Mode Constants
9964 35 ADRMD EQU PRT91+4 ;91 address mode register #
0988 36 TON E QU 80H ;91 talk only mode & not listen only
#040 37 LON EQU 40H ;91 listen only & not ton
IC 38 TLON EQU GCOH ;91 talk & listen only
7081 39 MODEL EQU 21 ¿mode 1 addressing for device
40
41 ; Reg #4 (Read) Address Status Register
06264 42 ADRST EQU PRT91+4 ;req #4
4720 43 EOIST EQU 20H
9092 44 TA EQU 2
9371 45 LA EQU 1 ; listener active
46 ;
47 ; Reg #5 (Write) Auxillary Mode Register
0065 48 AUXMD EQU PRT91+5 ;91 auxillary mode register #
8023 49 CLKRT EQU 23H ;91 3 Mhz clock input
29
0003
0076
0980
2091
0002
7073
9074
9908
oor
9007
UA
99971
9765
0065
9969
QAED
7067
7068
9768
ЙЙАЙ
0068
gl
7982
0004
9968
2068
0069
9969
7019
0982
0020
9068
7768
1068
1768
PAGS
UFO
BAF 1
UF?
g0F3
ВОР 4
FS
AOF6
VOF7
g0F8
03FI
OOFA
ОВЁС
AFD
ВОВЕ
197
198
109
110
111
112
113
114
115
116
117
118
119
128
121
122
ms. -
O
N
pu
“us wo Ve We Ve Ne
TU
pu
3
o
N
’
INTMR
INTM
ERRM
TOUT1
TOUT 2
TOUT3
EVREG
TOREG
CMD92
INTST
EVBIT
IBFBT
SROBT
ERF LG
CLRST
BUSST
EVCST
TOST
e
e
,
e
7
SPCNI
GIDL
RSET
RSTI
GSEC
EXPP
GTSB
SLOC
SREM
ABORT
TCNTR
TCASY
TCSY
STCNI
’
e
’
EQU
E QU
EQU
E QU
EQU
E QU
EQU
EQU
E QU
E QU
EQU
EQU
Reg
EQU
Reg
EQU
E QU
EQU
Reg
EQU
8292
EQU
EQU
EQU
EQU
E QU
EQU
E QU
EQU
E QU
EQU
E QU
E QU
EQU
E QU
E QU
E QU
E QU
EQU
E QU
8292
EQU
EQU
E QU
EQU
EQU
E QU
EQU
EQU
EQU
EQU
EQU
E QU
E QU
E QU
#5
#7
03
ga
83H
1
2
3
4
8
AFH
07H
gAOH
glnH
(Read)
PRT91+5
Address
PRT9] +6
69H
AE AH
EOS
PRT91+7
CONTROL
PRT91+8
PRT92+9
АОН
PRT92 +9
PRT92+8
РВТ92 +0
PRT92+1
PRT92+1
18H
02
20H
PRT92 +7
РВТ92 +0
PRTI2 +0
PRT92+0
PRT92+0
;91 fininsh handshake command
;91 send EOI with next byte
;91 aux. reg A pattern
;91 hold off handshake on all bytes
;91 hold off handshake on end
;91 continuous AH cycling
391 end on EOS received
; 91 output EOI on EOS sent
;91 valid command pass through
;91 invalid command pass through
sAux. reg. B pattern
;command pass thru enable
ÿ/1 reg. constants
;Disable major talker & listener
;Disable minor talker & listener
Character Register
VALUES
;8292 Base Port # (CS7)
; 92 INTRP Mask Reg
; TCI
; 92 Error Mask Reg
;92 Time Out for Pass Control
;92 Time Out for Standby
792 Time Out for Take Control Sync
;92 Event Counter Pseudo Reg
;92 Time Out Pseudo Reg
;92 Command Register
;92 Interrupt Status Reg
;Event Counter Bit
; Input Buffer Full Bit
¿Seg bit
;92 Error Flag Pseudo Reg
;92 Controller Status Pseudo Reg
;92 GPIB (Bus) Status Pseudo Reg
;92 Event Counter Status Pseudo Reg
;92 Time Out Status Pseudo Reg
OPERATION COMMANDS
OFOH
QF 1H
AF 2H
OF 3H
AF 44
@F5H
AF 6H
AF 7H
gF8H
gr 9H
gF AH
ÖFCH
dF DH
AF EH
¿Stop Counter Interrupts
¿Go to idle
; Reset
;Reset Interrupts
:Goto standby, enable counting
;Execute parallel poll
;Goto standby
‚Set local mode
‚Set interface to remote
;Abort all operation, clear interface
; Take control (Receive control)
; Take control asyncronously
; Take control syncronously
;Start counter interrupts
30
OBEl
BUE?
O0EJ
QOE4
AES
VBE6
0957
APES
PAEA
900B
VBEF
9092
0004
7008
9818
gal
0001
2341
9021
903F
9998
00094
9018
9919
0095
9070
7063
7915
9909
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
149
141
142
143
144
145
146
147
148
149
159
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
189
181
182
183
184
185
186
187
188
189
198
191
192
193
194
195
® wg “o
’
WOUT
WEVC
REVC
RERF
RINM
RCST
RBST
RTOUT
RERM
IACK
e “e % “Cs U.S Ve
PRTF
TCIF
SPIF
OBFF
IBFF
BOF
ve we “e
MDA
MTA
MLA
UNL
GET
SDC
SPE
SPD
PPC
PPD
PPE
PPU
TCT
wn wo “e “e o
ETF
WAITO
WAITL:
o
,
WAITI
WAITL:
’
WAITX
WAITL:
8292
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
PORT F BIT ASSIGNMENTS
EQU
EQU
EQU
EQU
EQU
EQU
UTILITY
QE 1H
QE 2H
OE 3H
VE4H
AESH
QOE6H
QE7H
VE9H
PEAH
ABH
COMMANDS
¡Write to timeout reg
¡Write to event counter
sRead
; Read
; Read
; Read
; Read
; Read
: Read
event counter status
error flag reg
interrupt mask reg
controller status reg
GPIB Bus status reg
timeout status reg
error mask reg
; Interrupt Acknowledge
PRTI91 +9 FH
02H
04H
98H
10H
A1H
; Task
;Z2T7488 port 6F for interrupts
complete interrupt
; Special interrupt
;92 Output (to CPU) Buffer full
; 92 Input (from CPU) Buffer empty
;91 Int line (BO in this case)
GPIB MESSAGES (COMMANDS)
EQU
EQU
EQU
EQU
EQU
EQU
E QU
E QU
EQU
EQU
EQU
E QU
E QU
1
MDA +4 2H
MDA +2 0H
3FH
78
34H
18H
19H
AS
70H
69H
15H
29
;My device address is 1
;My talk address is 1 ("A")
¡My listen address is 1 ("!")
Universal unlisten
¿Group Execute Trigger
;Device Clear
¿Serial poll enable
¿Serial poll disable
¿Parallel poll configure
¿Parallel poll disable
¿Parallel poll disable
¿Parallel poll unconfigured
; Take control (pass control)
MACRO DEFINITIONS
MACRO
ORA
ENDM
MACRO
LOCAL
IN
ANI
JZ
ENDM
MACRO
LOCAL
IN
MOV
ANI
JZ
ENDM
MACRO
LOCAL
IN
ANI
JNZ
ENDM
WAITL
INT1
BOM
WAITL
WAITL
INT]
B,A
BIM
WAITL
WAITL
PRTF
TCIF
WAITL
;Sets flags on A register
;Wait for last 91 byte to be done
;Get Intl status
¿Check for byte out
; If not, try again
suntil it is
;Wait for 91 byte to be input
:Get INT] status
;Save status in B
;Check for byte in
¿If not, just try again
‚until it is
;Wait for 92's TCI to go false
1009
1002
1004
1096
1008
102A
192C
190E
1910
1912
1014
1815
1017
1919
1918
ЗЕАЙ
D368
3E69
D366
3EEQ
D366
3E89
D364
3E23
D365
AF
D361
D362
D355
C9
196 WAITT
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259+
260
261
262
263
264
265
266
267
268
269
WAITL:
RANGE
CLRA
. we we we ve no “ее “о ve “o we “чо we ve ve ve ve “e ve ve ve ve we ve
; INPUTS :
MACRO
LOCAL
IN
ANI
JZ
ENDM
MACRO
MOV
CPI
JM
CPI
JP
ENDM
MACRO
XRA
ENDM
WAITL
PRTF ¿Get task complete int,etc.
TCIF ¿Mask it
WAITL ‚wait for task to be complete
LOWER, UPPER, LABEL
;Checks for value in range
;branches to label if not
;in range. Falls through if
¿lower <= ( (H)(L) ) <= upper.
¿Get next byte.
A,M
LOWER
LABEL
UPPER+1
LABEL
A ;A XOR A =
All of the following routines have these common
assumptions about the state of the 8291 & 8292 upon entry
to the routine and will exit the routine in an identical state.
8291:
8292:
8985:
BO is or has been set,
All interrupts are masked off
TON mode, not LA
No holdoffs in effect or enabled
No holdoffs waiting for finish command
ATN asserted (active controller)
note: RCTL is an exception--- it expects
to not be active controller
Any previous task is complete & 92 is
ready to receive next command.
Pointer registers (DE,HL) end one
beyond last legal entry
* % de e de de de e de 4 de de de de e e de Le de e Le de e e de de de de de à de x à à à x à à x à à à à à à k à à k X k % k * X
INITIALIZATION ROUTINE
; OUTPUTS:
s CALLS:
;: DESTROYS
INIT:
ve My e e We e
MVI
our
MVI
OU'T
MVI
OUT
MVI
OUT
MVI
our
CLRA
XRA
OUT
OUT
OUT
RET
None
None —
None
A,F
A, INTM ¿Enable TCI
INTMR ;Output to 92's intr. mask reg
A,DTDL1I ;Disable major talker/listener
ADR®1
A,DTDL2 ;Disable minor talker/listener
ADR®?1
A, TON ¿Talk only mode
ADRMD
A,CLKRT ;3 MHZ for delay timer
AUXMD
A ‚A XOR A =0
INT]
INT2 ¿Disable all 91 mask bits
AUXMD ;Immediate execute PON
* x à % à % k * % k à à à à à k k k k k à à * à À k à k à k * k à à à k k * k à k à à k à à * k k à à à à
SEND ROUTINE
32
191C
101E
1020
1022
1024
1027
1929
1928
192C
102Е
102F
1031
1934
1936
1939
193B
193D
1340
1041
1043
1044
1847
1949
104B
104E
1959
1952
1954
1956
1958
105A
1950
185F
1861
1964
1965
1966
1069
105A
186C
3E41
D350
DB61
£622
CA20818
3E3F
D369
78
D357
7E
FE20
FA4710
FE3F
F24710
DB61
E632
CA3919
C32E1@
DB61
E692
CA4710
3EF6
D369
3E88
D365
DB6F
E692
C25610
DB6F
E692
CASD19
79
B7
CA8819
lA
D359
B8
270
271
272
273
274
275
276
277
278
279
289
281
282
283
284
285+228991:
286+
287+
288
289
290
291
292
293
294+
295+
295+
297+
298+
299+
300+
301+
302+
343+
304
395+? 20702:
306+
307+
308
309
319
311
312
313
3144220023:
315+
316+
317
318
319
320
321
322
323
324+770A34:
325+
326+
327
3284220005:
329+
330+
331
332
333
334
335
336+
337
338
339
340
341
342
U so ve WE DO “€ DI V6 Ve We “че “о we
END:
SEND]:
SEND2:
.
,
.
,
SEND3:
20H, 3EH, SEND2
A, AXRA+EOIS
INPUTS:
OUTPUTS:
CALLS:
DESTROYS:
MVI A,MTA
OUT DOUT
WAITO
IN INT1
ANI BOM
JZ 220971
MVI A,UNL
OUT DOUT
MOV A,B
ouT EOSR
RANGE
MOV A,M
CPI 20H
JM SEND2
CPI ЗЕН+1
JP SEND2
WAITO
IN INT1
ANI BOM
JZ 220002
MOV A, M
OUT DOUT
INX H
JMP SEND1
WAITO
IN INT1
ANI BOM
JZ 220093
MVI A,GTSB
OUT CMD92
MVI
OUT AUXMD
WAITX
IN PRTF
ANI TCIF
INZ 229904
WAITT
IN PRTF
ANI TCIF
JZ 220995
HL listener list pointer
DE data buffer pointer
C count-- 9 will cause no data to be sent
b EOS character-- software detected
none
none
A, C,
DE, HL, EF
¿Send MTA to turn off any
¿previous talker
;Get Intl status
¿Check for byte out
¿If not, try again
sSend universal unlisten
;to stop previous listeners
;Get EOS character
sOutput it to 8291
¡while listener.....
¿Check next listen address
;Checks for value in range
;branches tn label if not
;in range. Falls through if
; lower <= ( (H) (L) ) <= upper.
¿Get next byte.
swait for previous listener sent
sGet Intl status
¿Check for byte out
‚If not, try again
;Get this listener
;Output to GPIB
: 3;Increment listener list pointer
¿Loop till non-valid listener
;Enable 91 ending conditions
¿Wait for lstn addr accepted
sGet Intl status
¿Check for byte out
; If not, try again
;WAITO required for early versions
sof 8292 to avoid GTSB before DAC
;Goto standby
,
:Send EOI with EOS character
¿Wait for TCI to go false
¿Wait for TCI on GTSB
¿Get task complete int,etc.
‚Mask it
sWait for task to be complete
delete next 3 instructions to make count of @#=256
MOV
SETF
ORA
JZ
LDAX
OUT
CMP
A,C
A
SENDA
р
DOUT
8
¿Get count
; Set flags
«If count=9, send no data
;Get data byte
; Output to GPIB
; Test EOS ...this is faster
;and uses less code than using
;91's END or EOI bits
33
106D
1970
1972
1074
1077
1078
1079
107C
197F
1989
1081
1883
1985
1988
108A
198C
108E
1990
1092
1094
1097
1099
1998
109E
109F
10А0
10А2
10A3
18A5
10A8
18AA
10AD
10AF
10B8
19B2
1984
1987
1989
1088
19BD
10BF
CA7F1%
DB61
E692
CA7810
DB61
E692
CA8118
3EFD
D369
3E89
D365
DBSF
£602
C29310
DB6F
ERA?
CA9719
C9
78
D367
7E
FE40
FA3911
FESF
F23911
D360
23
DBAL
ED?
САВЙ1Й
3E3F
D367
DBA 1
E602
CABB1Q
SENDS
INT]
BOM
220006
D
C
SEND3
SEND6
D
C
INT]
BOM
270907
A, TCSY
CMD92
A, AXRA
AUXMD
PRTF
TCIF
220998
PRTF
TCIF
220079
;I1f char = EOS , go finish
;Get Intl status
;Check for byte out
¿If not, try again
; Increment buffer pointer
; Decrement count
; If count < > 4,
¡Else go finish
¿for consistency
go send
’
;This ensures that the standard entry
:Get Intl status
;Check for byte out
¡If not, try again
sassumptions for the next subroutine are met
;Take control syncronously
;Reset send EOI on EOS
;Wait for TCI false
sWait for TCI |
¿Get task complete int,etc.
sMask it
¡Wait for task to be complete
* de E de de de e Le A de de e de de de de de de de e à de de à e de e de e à à à à à à à de de de e de de de 4 à k x & à à k k k à à à à k k k à à à à à X à k À
RECEIVE ROUTINE
343 JZ
344 SENDA: WAITO
3454220096: IN
346+ ANI
347+ JZ
348 INX
349 DCR
350 JNZ
351 JMP
352 SENDS5: INX
353 DCR
354 WAITO
3554220007: IN
356+ ANI
357+ JZ
358
359 SENDA: MVI
369 OUT
361 MVI
362 OUT
363 WAITX
354+220008: IN
355+ ANI
365+ INZ
367 WAITT
368+220009: IN
369+ ANI
370+ JZ
371 RET
372 ;
373 ;
374 ;
375 ;
376 ;
377 ; INPUT:
378 ;
379 y
380 ;
381 ;OUTPUT:
382 ;CALLS:
383 +DESTROYS:
384 ;
385 ; RETURNS:
386 :
387 ;
388 ;
389 y;
398 RECV: MOV
391 our
392 RANGE
393+
394+
395+
395+
397+
398+ MOV
399+ CPI
400+ JM
401+ CPI
402+ JP
403
404 our
405 INX
406 WAITO
407+220018: IN
408+ ANT
409+ JZ
410 MVI
411 OUT
412 NAITO
413+?73311: IN
414+ ANI
415+ JZ
HL talker pointer
DE data buffer pointer
C count (max buffer size)
9 implies 254
B EOS character
Fills buffer pointed at by DE
None .
A, BC, DE, HL, F
A=0 normal termination--EOS detected
A=40 Error--- count overrun
A<44 or A>5EH Error--- bad talk address
A,B ;Get EOS character
E OSR
¿Output it to 91
40H, 5EH, RECV6
A,M
40H
RECV6
S5EH+1
RECV6
DOUT
INT]
BOM
2230810
A,UNL
DOUT
INTI
BOM
227211
;Checks for value in range
sbranches to label if not
sin range. Falls through if
; lower <= ( (Н) (1) ) <= upper.
¿Get next byte.
svalid if 40H<= talk <=5EH
;Output talker to GPIB
; Incr pointer for consistency
;Get Intl status
;Check for byte out
¿If not, try again
;Stop other listeners
¿Get Intl status
¿Check for byte out
;If not, try again
34
19C2
19C4
19C6
10C8
10СА
19CC
10СЕ
19D1
1903
1905
1906
18608
19DA
13DC
10DE
10E8
10E3
18E5
10EA
10EC
18ED
LOEF
19F2
10F3
10F5
19F8
10FA
10FB
10FC
19FD
1198
1102
1185
1106
1198
11088
119D
1110
1112
1113
1114
1115
1117
1119
1118
111D
111F
1122
1124
1126
1129
1128
112D
112F
1131
1133
1135
1136
1138
1139
3821
D360
3E86
D355
DB6l
E602
САСА1Й
3E48
D354
AF
D365
3EF6
D359
DB6F
E692
C2DC19
DB6F
E602
DB51
47
E610
C20511
78
E601
CAEAlQ
DB69
DB6F
E602
c21B11
DB6F
£602
CA2211
3E89
D355
3E80
D364
3E93
D345
AF
D365
78
C9
4156
417
418
419
420
4214220012:
422+
423+
424
425
426
427+
428
429
430
431
432+220013:
433+
434+
435
436+220014:
437+
439
440
441
442
443
444
445
446
447
448
449
4 50
451
452
453
454
455
456
457
458
459
460
451
462
453
464
465
466
467
468+? 20015:
469+
479 +
471
472+229916:
473+
474 +
475
476
477
478
479
489
481
482
483
484
485
486
487+
488
489
499
RECVI1:
RECV2:
RECV3:
RECVA4:
RECVS:
,
MVI
OUT
MVI
OUT
WAITO
IN
ANI
JZ
MVI
OUT
CLRA
XRA
ouT
MVI
OU'T
WAITX
IN
ANI
JNZ
WAITT
IN
ANI
IN
MOV
ANI
INZ
MOV
ANI
JZ
IN
STAX
INX
DCR
JNZ
MVI
JMP
MOV
ANI
JNZ
IN
JMP
IN
STAX
INX
DCR
MVI
MVI
OUT
WAITX
IN
ANI
JNZ
WAITT
IN
ANI
JZ
A,MLA
DOUT
A, AXRA+HOEND+EDEOS
AUXMD
INT1
BOM
220912
A,LON
ADRMD
A
AUXMD
A,GTSB
CMD92
PRTF
TCIF
2720413
PRTF
TCIF
INT]
B,A
ENDMK
RECV2
A,B
BIM
RECV1
DIN
D
D
C
RECV1
B, 40H
RECV5
A,B
BIM
RECV4
INT]
RECV3
DIN
ооо
, 0
A, TCSY
CMD92
PRTE
TCIF
220915
PRTF
TCIF
220016
;For completeness
; End when
sEOS or EOI & Holdoff
;Get Intl status
;Check for byte out
sIf not, try again
;Listen only
;Immediate XEQ PON
¡A XOR A =9
¿Goto standby
¿Wait for TCI=9
¿Wait for TCI=1
¿Get task complete int,etc.
¿Mask it
;Get 91 Int status (END &/or BI)
;Save it in B for BI check later
;Check for EOS or EOI
;Yes end--- go wait for BI
;NO, retrieve status €
¿Check for BI
;NO, go wait for either END or BI
; YES, BI--- get data
;Store it in buffer
;Increment buffer pointer
;Decrement counter
¿If count < > 4 go back 8 wait
;Else set error indicator
;And go take control
;Retreive status
;Check for BI
;If BI then go input data
;Else wait for last BI
;In loop
;Get data hyte
;Store it in buffer
;Incr data pointer
;Decrement count, but ignore it
;Set normal completion indicators
;Take control synchronously
sWait for TCI=9 (7 tcy)
swait for TCI=]
;Get task complete int,etc.
¡Mask it
¿Wait for task to be complete
;1f timeout 3 is to be checked, the above WAITT should
; be omitted & the appropriate code to look for TCI or
; TOUT3 inserted here.
,
RECVO:
MVI
OUT
MVI
OUT
MVI
OUT
CLRA
XRA
OU'T
MOV
RET
A, AXRA
AUXMD
A, TON
ADRMD
A, FNHSK
AUXMD
A
AUXMD
A,B
sPattern to clear 91 END conditions
¿This bit pattern already in "A"
;Output TON
;Finish handshake
;A XOR A =9
; Immediate execute PON-Reset LON
¿Get completion character
35
113A
113B
113D
1140
1142
1145
1147
1148
114А
114C
114F
1151
1153
1154
1156
1159
1158
115E
1169
1162
1165
1166
1168
1169
116C
116E
1170
1173
1175
1177
1179
1178
117C
117E
117F
1181
1183
7E
FE40
FABB11
FESF
F2BB11
D350
23
DB61
E632
CA4811
3E3F
D359
7E
FE20
FA6C11
FE3F
F26C11
DB61
E602
CASE11
7E
D369
23
C35311
DB61
E692
CA6C11
3E87
D365
3E40
D364
AF
D365
78
D367
3EF6
D369
491
we
«à k k k k À à à k à k à k à À à à À À à à de de de de de de de de de de de de de de de de de de de de de de de de de de de e de de A A A À A AA A A
XFER ROUTINE
492 ;
493 ;
494 ;
495 ;
495 ;INPUTS:
497 ;
498 ;OU'TPUTS :
499 ;CALLS:
5990 ;DESTROYS:
591 ;RETURNS:
592 ;
593 ;
504 ;NOTE:
595 ;
596 ;
597 ;
588 ;
599 >
518 ;
511 XFER: RANGE
512+
513+
514+
515+
516+
517+ MOV
518+ CPI
519+ JM
520+ CPI
521+ JP
522 OUT
523 INX
524 WATTO
525+220017: IN
526+ ANI
527+ JZ
528 MVI
529 OUT
530 XFER1: RANGE
531+
532+
533+
534+
535+
536+ MOV
537+ CPI
538+ JM
539+ CPI
540+ JP
541 WAITO
542+2?0018: IN
543+ ANI
544+ JZ
545 MOV
546 OUT
547 INX
548 JMP
549 XFER2: WAITO
550+??20019: IN
551+ ANI
552+ JZ
553 MVI
554 OUT
555 MVI
556 OU'T
557 CLRA
558+ XRA
559 OUT
569 MOV
561 our
562 MVI
563 OUT
HL device list pointer
B EOS character
None
None
A, HL, F
A=9 normal, A <> @ bad talker
XFER will not work if the talker
uses EOI to terminate the transfer.
Intel will be making hardware
modifications to the 8291 that will
correct this problem. Until that time,
only EOS may be used without possible
loss of the last data byte transfered.
40H, 5EH, XFERA4 ;Check for valid talker
;Checks for value in range
; branches to label if not
sin range. Falls through if
slower <= ( (H)(L) ) <= upper.
¿Get next byte.
A,M
40H
XFER4
SEH+1
XF ER 4
DOUT ;Send it to GPIB
H ;Incr pointer
INT1 ¿Get Intl status
BOM ¿Check for byte out
2720917 If not, try again
A,UNL ;Universal unlisten
DOUT
20H, 3EH,XFER2 ;Check for valid listener
;Checks for ‘value in range
; branches to label if not
;in range. Falls through if
; lower <= ( (H)(L) ) <= upper.
¿Get next byte.
A,M
20H
XFER2
3EH+1
XFER?
INTl ¿Get Intl status
BOM ¿Check for byte out
2720018 ¡If not, try again
A,M ;Get listener
DOUT
H ;Incr pointer
XFER1 ¿Loop until non-valid listener
INTl ;Get Intl status
BOM ¿Check for byte out
2720919 ¡If not, try again
A, AXRA+CAHCY+EDEOS ¿Invisible handshake
AUXMD Continuous AH mode
A, LON ¡Listen only
ADRMD
A ¿RH XOR A =
AUXMD ; Immed. XEQ PON
A,B ; Get EOS
EOSR ;Output it to 91
A,GTSB ;Go to standby
CMD92
36
1185
1187
1189
118C
118E
1190
1193
1195
1197
119A
119C
119E
11Ag
11А2
11А5
11А7
11А9
11AC
11AE
118%
11B2
11B4
11B6
1188
1189
11BB
11BC
11BE
11C#
11C1
11C3
11C6
11C8
11C8
11CD
11CF
11D2
11D3
11D5
1105
1109
11DB
11DD
11E0
11E2
11E4
11E6
DB6F
E602
C28511
DB6F
E692
CA8C11
DB61
E610
CA9311
3EFD
D369
DBSF
£692
C29E11
DB6F
E602
CAAS11
3E80
D365
ЗЕЙЗ
D365
3E89
D354
AF
D365
C9
3E3F
D359
7E
FE20
FAD911
FE3F
F2D911
DB61
E692
САСВ11
TE
D369
23
c3call
DB61
5502
CAD911
3E08
D359
DB61
E602
564
565+7?720920:
566+
567+
568
569+7279221:
578+
571+
572 XFER3:
573
574
575
576
577
578+773422:
579+
580+
581
582+?7?7023:
583+
584+
535
586
587
588
589
598
591
592+
593
594 XFER4:
595 ;
WAITX
IN
ANT
JNZ
WAITT
IN
ANI
JZ
IN
ANI
JZ
MVI
OUT
WAITX
IN
ANI
JNZ
WAITT
IN
ANI
JZ
MVI
OU'T
MVI
OUT
MVI
OUT
CLRA
XRA
OUT
RET
PRTF
TCIF
220020
PRTF
TCIF
220021
INT]
ENDMK
XFER3
A, TCSY
CMD92
PRTF
TCIF
220222
PRTF
TCIF
27207123
A, AXRA
AUXMD
A,FNHSK
AUXMD
A, TON
ADRMD
A
AUXMD
;Wait for TCS
;Get task complete int,etc.
;Mask it
;Wait for task to be complete
;Get END status hit
;Mask it
; Take control syncronously
;Wait for TCI
;Get task complete int,etc.
‚Mask it
;Wait for task to be complete
¿Not cont AH or END on EOS
;Finish handshake
;Talk only
;Normal return A=1
sA XOR A =0
;Immediate XEQ PON
596» 2 de % de de e de AAkAAAKAA RRA AAA AAA A AAR AAA AA IAA AAA AAAI AA AAA kkk
597
598
599
609
601 ;
632 ;INPUTS:
- wo ve ve %e ©
TRIGGER ROUTINE
643 ;OUTPUTS:
604 ;CALLS:
585 ;DESTROYS :
696 ;
697 z;
698 TRIG: MVI
699 OU'T
619 TRIG1: RANGE
511+
512+
A13+
614+
615+
616+ MOV
617+ CPI
618+ JM
619+ CPI
620+ JP
621 WAITO
622+??0924: IN
623+ ANI
624+ JZ
625 MOV
626 our
627 INX
628 JMP
529 TRIG2: WAITO
630+?209025: IN
631+ ANT
632+ JZ
633 MVI
634 OUT
635 WAITO
63642290026: IN
637+ ANI
HL listener list pointer
None
None
A, HL,
A,UNL
DOUT
20H,3EH, TRIG2
A,M
20H
TRIG2
3EH+1
TRIG2
INTI]
BOM
220924
A,M
DOUT
H
TRIGI1
INTI
BOM
229025
A,GET
DO UT
INT]
BOM
Send universal unlisten
¿Check for valid listen
; Checks for value in range
; branches to label if not
;in range. Falls through if
¿lower <= ( (H) (L) ) <= upper.
;Get next byte.
sWait for UNL to finish
Get Intl status
¿Check for byte out
¿If not, try again
;Get listener
; Send Listener to GPIB
;Incr. pointer
; Loop until non-valid char
¿Wait for last listen to finish
¿Get Intl status
¿Check for byte out
;If not, try again
;Send group execute trigger
sto all addressed listeners
:Get Intl status
¿Check for bvte out
37
11E8
11EB
11EC
11EE
1189
11F1
11F3
11F6
11F8
11FB
11FD
11FF
1202
1203
1205
1206
1209
1208
120D
1218
1212
1214
1216
1218
121B
121C
121E
1220
1222
1224
1227
1229
1228
122D
122F
1232
1234
1236
CAE411
C9
3E3F
D369
TE
FE20
FAQ912
FE3F
F20912
DB61
E602
CAFB11
C3FQ11
DB61
E692
CA9912
3EQ4
D369
DB61
E6032
CAl412
C9
3E3F
D360
DB61
E602
CA2012
3E21
D369
DB61
E602
CA2B12
3E18
D360
DB61
270826 ;If not, try again
* * * à * À # k à k * * k à ARE RE ERE
HL listener pointer
None
None
A, HL, F
A,UNL
DOUT
29H, 3EH,DCLR2
;Checks for value in range
;branches to label if not
sin range. Falls through if
; lower <= ( (H) (L) ) <= upper.
;Get next byte.
A,M
20H
DCLR 2
3EH+1
DCLR2
Тит] ;Get Intl status
BOM ¿Check for byte out
220027 ¡If not, try again
A,M
DOUT ;Send listener to GPIB
H
DCLR1
INTI1 ;Get Intl status
BOM ;Check for byte out
220028 ¡If not, try again
A, SDC ;Send device clear
DOUT ;To all addressed listeners
INTI1 ;Get Intl status
BOM ;Check for byte out
220029 If not, try again
2 * à e de XA * de à x de de de x de de * à à à * à à à à % k* à X k k k à k À à * à à à à * % à k à à à k À
SERIAL POLL ROUTINE
HL talker list pointer
DE status buffer pointer
Fills buffer pointed to by DE
None
A, BC, DE, HL, F
638+ JZ
639 RET
640 ;
641 ;
642 ; |
643 ;DEVICE CLEAR ROUTINE
644 ;
645 ;
646 ;
647 ; INPUTS:
648 ;QUTPUT:
649 ;CALLS:
650 ;DESTROYS:
651 ;
652 DCLR: MVI
653 OUT
654 DCLR1: RANGE
655+
656+
657+
658+
659+
660+ MOV
661+ CPI
662+ JM
663+ CPI
664+ JP
665 WAITO
656+220027: IN
667+ ANI
668+ JZ
669 MOV
670 OUT
671 INX
672 JMP
673 DCLR2: WAITO
674+220028: IN
675+ ANI
676+ JZ
677 MVI
678 OUT
679 WAITO
689+220029: IN
681+ ANI
682+ JZ
683 RET
684 ;
685 ;
686 ;
687 ;
688 ;
689 INPUTS:
690 ;
691 ;0UTPUTS:
692 ;CALLS:
693 ;DESTROYS:
694 ;
695 SPOL: MVI
696 OUT
697 WAITO
698+220030: IN
699+ ANI
703+ JZ
781 MVI
782 OUT
783 WAITO
7084+220031: IN
70 5+ ANI
706+ JZ
707 MVI
798 OUT
799 WAITO
710+220032: IN
A,UNL ¿Universal unlisten
DOUT
INT1 ;Get Intl status
BOM ¿Check for byte out
220030 ;If not, try again
A,MLA ¡My listen address
DOUT
INTl ¿Get Intl status
BOM ¿Check for byte out
2720831 ¡If not, try again
A, SPE :Serial poll enable
DOUT ¿To be formal about it
INT1 ¿Get Intl status
38
1238
123A
123D
123E
1240
1243
1245
1248
1249
124B
124C
124E
1250
1252
1254
1257
1258
125A
125C
125E
1269
1262
1265
1267
1269
126C
126E
126F
1271
1274
1276
1278
127A
127C
127F
1281
1283
1286
1288
1289
128A
128C
128E
128F
1291
1294
1296
1298
129A
129C
129F
12A0
12A2
E602
CA3512
7E
FE40
FA9412
FESF
F29412
7E
D369
23
3E40
D364
DB61
E502
CA5@12
AF
D365
3EF6
D369
DB6F
E592
C25E12
DB6F
E692
CA5512
DB61
47
E691
CA6C12
3EFD
D359
DBAF
E6A2
C27812
DB6F
E692
CA7F12
D360
C33D12
3E19
D360
DB61
E602
CA9812
AF
D365
C9
711+
712+
713 SPOL1:
714+
715+
716+
717+
718+
719+
720+
721+
722+
723+
724
725
726
727
728
729
730+?7?0733:
731+
732+
733
734+
735
736
737
738
739+7?70734:
740+
741+
742
743+223035:
744+
745+
746
7474220036:
748+
749+
752+
751
752
753
754+7729737:
755+
756+
757
758+? ?0 238:
759+
769+
761
762
763
764
765
766
767+
768
769
770
771 y
772 SPOL2:
773
774
775+??8 039:
776+
777+
778
779+
789
781
782
783
784
ve %e we
ANT
JZ
RANGE
MOV
CPI
JM
CPI
JP
MOV
OUT
INX
MVI
OUT
WAITO
IN
ANI
JZ
CLRA
XRA
OU'T
MVI
OUT
WAITX
IN
ANI
JNZ
WAITT
IN
ANI
JZ
WAITI
IN
MOV
ANI
JZ
MVI
OUT
NAITX
IN
ANI
JNZ
WAITT
IN
ANI
JZ
IN
STAX
INX
MVI
OUT
CLRA
XRA
OUT
JMP
MVI
OUT
WAITO
IN
ANI
JZ
CLRA
XRA
OUT
RET
BOM
220932
404, 5EH,
A,M
40H
SPOL2
SEH+1
SPOL2
A,M
DOU'T
H
A, LON
ADRMD
INT]
BOM
220033
A
AUXMD
A,GTSB
CMD92
PRTF
TCIF
220034
PRTE
TCIF
220935
INT1
B,A
BIM
228936
A,TCSY
CMD92
PRTF
TCIF
229037
PRTF
TCIF
220038
DIN
D
D
A, TON
ADRMD
A
AUXMD
SPOL1
A,SPD
DOUT
INT]
BOM
2207939
A
AUXMD
;Check for byte out
; If not, try again
SPOL2 ;Check for valid talker
;Checks for value in range
; branches to label if not
sin range. Falls through if
; lower <= ( (H) (L) ) <= upper.
¿Get next byte.
‚Get talker
;5end to GPIB
;Incr talker list pointer
;Listen only
;Wait for talk address to complete
;Get Intl status
¿Check for byte out
¿If not, try again
¡Pattern for immediate XEQ PON
:A XOR A =0
¿Goto standby
;Wait for TCI false
;Wait for TCI
¿Get task complete int,etc.
¡Mask it
¿Wait for task to be complete
¿Walt for status byte input
¿Get INT1 status
; Save status in B
¿Check for byte in
¿If not, just try again
;Take control sync
:Wait for TCI false
¡Wait for TCI
¡Get task complete int,etc.
;Mask it
;Wait for task to be complete
¿Get serial poll status byte
¿Store it in buffer
;Incr pointer
¿Talk only for controller
,
sA XOR A =H
sImmeditate XEQ PON
; CLR LA
;Go on to next device on list
¿Serial poll disable
¿We know BO was set (WAITO above)
; Get Intl status
¿Check for byte out
; If not, try again
:A XOR A =
;Immediate XEQ PON to clear LA
* x à à à x k k k à k à k à k à k à à à à à à à à k à à à à k à à à à à à à à à k à à à à à À à à % à À à
39
12A3
12A5
12A7
12A8
12AA
12AD
12AF
12B2
12B4
1286
1289
128A
12BC
12BE
12C9
12C3
12C5
12C7
12C9
12CB
12CE
12CF
12D1
12D3
12D4
12D5
12D8
12DA
12DC
12DF
12E0
12E2
12E4
12E5
12E7
12EA
12EC
12EF
12F1
12F3
3E3F
D369
7E
FE20
FAD812
FE3F
F2D812
DB61
E602
CAB212
7E
D359
DB61
E692
CABC12
3E05
03590
DB61
E632
CAC712
1A
F669
D369
23
13
C3A712
DB61
E642
CAD812
C9
3E3F
D359
7E
FE2@
FAFD12
FE3F
F2FD12
DB61
E602
CAEF12
785
786
787
788
e se “€ “e “oe
INPUTS:
PARALLEL POLL ENABLE ROUTINE
789 ;QUTPUTS:
790 ;CALLS:
791 ; DESTROYS:
792 ;
793 ;
794 PPEN:
795
796 PPEN]l:
797+
798+
799+
800+
821 +
892 +
833+
804+
805+
836+
807
808+7?77040:
809+
810+
811
812
813
814+?70/41:
815+
816+
817
818
819
820+2?270042:
821+
822+
823
824
825
826
827
828
829 PPEN2:
830+220943:
831+
832+
833
834
MVI
ouT
RANGE
MOV
CPI
JM
CPI
JP
NAITO
IN
ANI
JZ
MOV
OUT
NAITO
IN
ANI
JZ
MVI
OUT
WAITO
IN
ANI
JZ
LDAX
ORI
OUT
INX
INX
JMP
WAITO
IN
ANI
JZ
RET
HL listener list pointer
DE configuration byte pointer
None
None
A, DE,
A,UNL
DOUT
20H, 3EH, PPEN2
A,M
20H
РРЕМ2
ЗЕН+1
РРЕМ 2
INT1
BOM
220040
A,M
DOUT
INT1
BOM
220041
A, PPC
DOUT
INTI
BOM
22909042
D
PPE
DO UT
H
D
PPEN1
INT]
BOM
2230243
HL, F
;Universal unlisten
¿Check for valid listener
;Checks for value in range
; branches to label if not
;in range. Falls through if
; lower <= ( (Н) (1) ) <= upper.
;Get next byte.
;Valid wait 91 data out reg
:Get Intl status —
;Check for byte out
; If not, try again
;Get listener
sGet Intl status
;Check for byte out
¿If not, try again
¿Parallel poll configure
;Get Intl status
;Check for byte out
sIf not, try again
;Get matching configuration byte
;Merge with parallel poll enable
;Incr pointers
; Loop until invalid listener char
;Get Intl status
;Check for byte out
¿If not, try again
;
835 ;PARALLEL POLL DISABLE ROUTINE
836
837 ; INPUTS:
838 ;QUTPUTS:
839 ;CALLS:
847 ;DESTROYS:
841 ;
842 PPDS:
843
844 PPDS1:
845+
845+
847+
848+
849+
850+
851+
852+
853+
854+
855
856+2?20044:
857+
858+
MV I
OUT
RANGE
MOV
CPI
CPI
JP
NAITO
IN
ANI
JZ
HL listener list pointer
None
None
A,UNL
DOUT
20H,3£EH, PPDS2
A,M
20H
PPDS2
3EH+1
PPDS2
INT]
BOM
229044
sUniversal unlisten
; Check for valid listener
; Checks for value in range
;branches to label if not
sin range. Falls through if
; lower <= ( (H)(L) ) <= upper.
¿Get next byte.
Get Intl status
¡Check for byte out
; If not, try again
40
12F6
12F7
12F9
12FA
12FD
12FF
1391
1384
1305
1398
130A
130C
130F
1311
1313
1315
1317
131A
1318
131D
131F
1321
1323
1326
1327
1329
1328
132C
132E
1330
1332
1334
1335
1337
133A
133C
133E
133F
1341
1343
7E
D369
23
C3E412
DB61
E692
CAFD12
3EA5
D357
DB61
E602
CA9813
3E7ÿ
D360
DB61
£602
CA1313
C9
3E15
D360
DB61
E602
CA1F13
C9
3E40
D364
AF
D365
3EFS
D359
DB61
47
E691
CA3213
3E8A
D364
AF
D355
DB59
C9
859
850
861
852
863 PPDS2:
854+7720345:
865+
856+
857
858
859
879+220846:
871+
872+
873
874
875
876+229047:
877+
878+
879
889
881
Co
o
N
-» ve Ne “
884 ; INPUTS:
MOV
OUT
INX
JMP
WAITO
IN
ANI
JZ
MVI
OUT
WAITO
IN
ANI
JZ
MVI
OUT
WAITO
IN
ANI
JZ
RET
A,M
DOUT
d
PPDS1
INT]
BOM
270945
A, PPC
DO UT
INT]
BOM
72209456
A, PPD
DO UT
INT]
BOM
220047
;Get listener
;Incr pointer
;Loop until invalid listener
;Get Intl status
;Check for byte out
;I£ not, try again
;Parallel poll confiqure
¿Get Intl status
¿Check for byte out
;If not, try again
¿Parallel poll disable
¿Get Intl status
¿Check for byte out
; If not, try again
PARALLEL POLL UNCONFIGURE ALL ROUTINE
885 ; OUTPUTS :
886 ;CALLS:
887 ; DESTROYS:
889 PPUN:
891
892+229N 48:
893+
894+
895
895
se
MVI
OUT
NAITO
IN
ANI
JZ
RET
None
None
None
A, F
A,PPU
DOU'T
INTI]
BOM
220048
;Parallel poll unconfiqure
;Get Intl status
;Check for byte out
If not, try again
897 » 2 26 A de de de de de de à k k de de de e de de de de de de de de de de de de de de à k à Xx Xx XXIX * à à k à à À k à à à À
898
899
900
991
- ve =
ve “че
902 ; INPUTS:
993 ;0UTPUTS:
994 ;CALLS:
905 ; DESTROYS:
936 ; RETURNS:
987 ;
998 PPOL:
999
910
911+
912
913
914
915
916+220049:
917+
918+
919+
920
921
922
923+
924
925
926
927 :
MVI
OU'I
CLRA
XRA
OUT
MVI
OU'T
WAITI
IN
MOV
ANT
JZ
MV I
OUT
CLRA
XRA
OUT
IN
RET
None
None
None
A, B,
A= par
A, LON
ADRMD
A
AUXMD
A,EXPP
CMD92
INT]
B,A
BIM
220849
A, TON
ADRMD
A
AUXMD
DIN
; CONDUCT A PARALLEL POLL
F
allel poll status byte
;Listen only
;Immediate XEQ PON
¿ARA XOR A =
¿Reset TON
;Execute parallel poll
sWait for completion= BI on 91
sGet INT] status
; Save status in B
;Check for byte in
;If not, just try again
¿Talk only
; Immediate XEQ PON
¡A XOR A =9
; Reset LON
;Get PP byte
28 ;hhkhkhk kkk Ahhh kkk hh kh AAA kh kkk kA ARR kk kkk Ahhh kK
929 ; PASS CONTROL ROUTINE
938
931 ;INPUTS:
932 ;0UTPUTS:
HL poi
None
nter to talker
41
933 ;CALLS: None
934 ; DESTROYS: A, HL, F
935 PCTL: RANGE 40H, 5EH, PCTL1 ;Is it a valid talker ?
936+ ;Checks for value in range
937+ ; branches to label if not
938+ ;in range. Falls through if
939+ ¿lower <= ( (H)(L) ) <= upper.
94 9+ ¿Get next byte.
1344 7E 941+ MOV A,M
1345 FE40 942+ CPI 49H
1347 FABA13 943+ JM PCTL1
134A FESF 944+ CPI SEH+1
134C F28A13 945+ JP PCTLI
134F FE41 946 CPI MTA ;Is it my talker address
1351 CA8A13 947 JZ PCTL1 ; Yes, just return
1354 0350 94 8 OUT DO UT ; Send on GPIB
949 WAITO
13556 DB61 950+220A59 IN INT1 ;Get Intl status
1358 E6C2 951+ ANT BOM ;Check for byte out
135A CA5613 952+ 72 220059 If not, try again
135D 3E@9 953 MVI A,TCT ¿Take control messade
135F D350 954 OUT DO UT
955 WAITO
1361 DB6l 956+7?70051: IN INT] ;Get Intl status —
1363 Еб02 957+ ANI BOM ¿Check for byte out
1365 CA6113 958+ JZ 224251 ;If not, try again
1368 3E01 959 MVI A,MODEl ;Not talk only or listen only
136A D364 969 OUT ADRMD ¿Enable 91 address mode 1
951 CLRA
136C AF 952 + XRA A :A XOR A =
136D D365 963 OUT AUXMD sImmediate XEQ PON
136F 3EQ1 954 MVI A, MDA ;My device address
1371 D346 965 OUT ADRA1 ¿enabled to talk and listen
1373 3EAl 964 MVI A, AXRB+CPTEN ¿Command pass thru enable
1375 0355 967 OUT AUXMD
9568 ; *******optional PP configuration goes here* * *** 4%
1377 3EF1 959 MVI A,GIDL ;92 go idle command _
1379 D359 970 OU'T CMD92
971 WAITX
1378 DBAF 972+220952: IN PRTF
137D E692 973+ ANI TCIF
137F C27813 974+ INZ 220952
975 WAITT ;Wait for TCI
1382 DB6F 97642237453: IN PRTF ¿Get task complete int,etc.
1384 E6%2 977+ ANI TCIF Mask it
1385 CA8213 978+ JZ 270453 ;Wait for task to be complete
1389 23 979 INX H
138A C9 934 PCTLl: RET
981 ; _
982 ;
933 ek AKA AA
984 ;
985 ;RECEIVE CONTROL ROUTINE
986 ;
987 ; INPUTS: None
988 ; OUTPUTS: None
989 ;CALLS: None
998 ; DESTROYS: A, F
991 ;RETURNS: p= invalid (not take control to us or CPT bit not on)
992 ; < > A valid take control-- 92 will now be in control
993 ;NOTE: THIS CODE MUST BE TIGHTLY INTEGRATED INTO ANY USER
994 ; SOFTWARE THAT FUNCTIONS WITH THE 8291 AS A DEVICE.
995 ; NORMALLY SOME ADVANCE WARNING OF IMPENDING PASS
996 ; CONTROL SHOULD BE GIVEN TO US BY THE CONTROLLER
997 ; WITH OTHER USEFUL INFO. THIS PROTOCOL IS SITUATION
998 ; SPECIFIC AND WILL NOT BE COVERED HERE,
999 ;
1990 ;
138B DB51 1991 RCTL: IN INT] ¿Get INT] req (i.e. CPT etc.) N
138D E684 1992 ANI CPT ¿IS command pass thru on ?
138F CACF13 1003 JZ RCTL2 ;No, invalid-- go return
1392 DB65 10834 IN CPTRG sGet Command
1394 РЕЙ9 1805 CPI TCT Is it take control ?
42
1396
1399
139B
139D
13А9
13А2
13A4
13A6
13A8
13A9
13AB
13AD
13AF
13B1
1383
1385
1387
1389
138B
138E
13C0
13C2
13C5
13C7
13CA
13CC
13CE
13CF
13D9
13D2
13D4
13D7
13D9
13DB
13DD
13DF
13E2
13E3
13E5
1387
13E9
13EB
13EE
13F0
13F2
C2CA13
DBA 4
E692
CACA13
3E64
D356
3E8A
D354
AF
D361
D362
D365
3EFA
D369
3EQF
D355
DBAF
E692
C28B713
DB6F
E692
CABE13
3EA9
C3CF13
3EQF
D365
AF
C9
DRB69
E620
CAE213
F69B
D359
DB69
E682
CADB13
C9
3EF8
D359
DBAF
ERA?
C2E713
DB6F
ERA?
CAEE13
RCTL1
ADRST
TA
RCTL1
A,DTDL1
АРКИ]
А, ТОМ
ADRMD
A
INT]
INT2
AUXMD
A, TCNTR
CMD92
A,V5CMD
AUXMD
PRTF
TCIF
229954
PRTF
TCIF
220755
А, ТСТ
RCTL2
A, VSCMD
AUXMD
A
SRO ROUTINE
1095 JNZ
1007 IN
1008 ANT
1909 JZ
1810 MVI
1911 OUT
1812 MVI
1813 OU'T
1914 CLRA
1015+ XRA
1916 OUT
1017 OU'T
1918 OUT
1019 MVI
1020 OU'T
1921 MVI
1022 OU'T
1923
1024 WAITX
1025+228054: IN
1926+ ANT
1927+ JNZ
1928 WAITT
1029+220055: IN
1330+ ANI
1031+ JZ
1032 MVI
1033 J MP
1334 RCTL1: MVI
1035 OUT
1436 CLRA
1037+ XRA
1038 RCTL2: RET
1039 ;
1940 ;
1941 :
1042 ;
1943 ;
1344 ; INPUTS:
1045 ;OUTPUTS:
1946 ;CALLS:
1847 ;RETURNS :
1048 ;
1949 ;
19858 ;
1951 SROD: IN
1052 ANT
1953 JZ
1954 ORI
1955 our
1956 SRODI: IN
1057 АМТ
1958 JZ
1959 SRQD2: RET
1999 y
1861 ;
19562 ;
1963 ;
1064 ;
1055 ;INPUTS:
1956 ;OUTPUTS:
1967 ;CALLS:
1068 ;DESTROYS:
1059 ;
1074 REME: MVI
1871 OUT
1972 WAITX
197342200156: IN
1374+ ANI
1375+ JNZ
1976 WAITT
1977+2208057: IN
1978+ ANI
1379+ JZ
None
None
None
A= Y no
A <> 4
INTST
SROBT
SROD2
IACK
CMD92
INTST
IBFBT
SRODI1
REMOTE ENABLE ROUTINE
None
None
NONE
A, E
A, SREM
CMD92
PRTF
TCIF
220055
PRTF
TCIF
220957
;No, go return invalid
:Get address status
¡IS TA on ?
¡No -- go return invalid
;Disable talker listener
¿Talk only
¿A XOR À =0
;Mask off INT bits
; Take (receive) control 92 command
;Valid command pattern for 91
; ****;#*;* optional TOUT1 check could be put here ********
;Wait for TCI
¿Get task complete int,etc.
¿Mask it
sWait for task to be complete
;Valid return pattern
;Only one return per routine
;Acknowledge CPT
¡Error return pattern
¿A XOR A =3
ЕЕ,
SRO
SRO occured
;Get 92's INTRO status
sMask off SRO
¿Not set--- go return
sSet--- must clear it with IACK
‚Get IBF
¡Mask it
¡Wait if not set
e He XA A A AAA AAN à % X à x * * à à À * x x à k * % à À
; 92 asserts remote enable
;Wait for TCI = 9
;Wait for TCI
;Get task complete
;Mask it
;Wait for task to be complete
int,etc.
43
13F5
13F6
13F8
13FA
13FC
13FE
1481
1403
1405
1408
1409
1408
140D
140F
1411
1414
1416
1418
1418
C9
3EF7
D369
DB6F
E622
C2FA13
DB6F
E692
CAQ114
C9
3EF9
D369
DBA F
E602
C20D14
DB6F
E602
CA1414
cy
1089
1981
1082
1983
1984
1085
1986
1087
1988
1089
14992
1991
1092
1993
1994
1795+77?9758:
1095 +
1997 +
1098
1099+2290759:
1100+
1101+
1102
1193
1104
1195
11956
1197
1198
1169
1110
1111
1112
1113
1114
1115
1116
1117
1118+?20760:
1119+
1120+
1121
112242203061:
1123+
1124+
1125
1126
1127
1128
1129
1139
1132
se
RET
% * à Ae de de À à % x à à % à à k * à à à k à k
. ve =
ve Wo
s INPUTS :
; LOCAL ROUTINE
; OUTPUTS:
; CALLS:
; DESTROYS:
LOCL:
“we
MVI
OUT
WAITX
IN
ANT
JNZ
WAITT
IN
ANI
JZ
RET
None
None
None
A, F
A, SLOC
CMD92 ;92 stops asserting remote enable
;Wait for TCI =9
PRTE
TCIF
220058
;Wait for TCI
PRTF ;Get task complete int,etc.
TCIF ¿Mask it
2240459 ¿Wait for task to be complete
ok A
ve +»
; INTERFACE CLEAR / ABORT ROUTINE
’
,
; INPUTS:
; OUTPUTS:
; CALLS:
; DESTROYS:
o
I
IFCL:
MVI
OUT
WAITX
IN
ANI
JNZ
WAITT
IN
ANI
JZ
None
None
None
A, F
A,ABORT
CMD92 ;Send IFC
:sWait for TCI =9
PRTF
TCIF
220763
¿Wait for TCI
PRTF ;Get task complete int,etc.
TCIF ;Mask it
220761 ¡Wait for task to be complete
¡Delete both NAITX & WAITT if this routine
sis to be called while the 3292 is
sController-in-Charge.
; TCI is set,
‚and the WAIT'S will hang forever
RET
else nothing
If not C.I.C. then
is set (IFC is sent)
44
1133 ; APPLICATION EXAMPLE CODE FOR 8985
1134 ;
0932 1135 FGDNL EQU "2" ; Func gen device num "2" ASCII,lstn
2731 1136 FCDNL EQU "17" ;Freq ctr device num "1" ASCII,lstn
2951 1137 ECDNT E QU ‘О’ ;Freq ctr talk address
000D 1138 CR — EQU ADA ;ASCII carriage return
I393A 1139 LF EQU ЙАН ;ASCII line feed
GOFF 1149 LEND E QU OFFH sList end for Talk/Listen lists
2740 1141 SROM EQU 40H ;Bit indicating device sent SRO
1142 ;
141C 46553146 1143 FGDATA: DB ' FULIFR37KHAM2VO' ,CR ;Data to set up func. gen
1429 5233374B
1424 48414032
1428 564F
142A (D
A0UE 1144 LIM] E QU 15 ;Buffer length
1428 50463447 1145 FCDATA: DB ‘PF4G7T' ;Data to set up freq ctr
142F 3754
9076 1146 LIM2 E QU 6 ;Buffer length
1431 31 1147 LL1: DB FCDNL, LEND ¿Listen list for freq ctr
1432 FF
1433 32 1148 LL2: DB FGDNL, LEND ;Listen list for func. gen
1434 FF
1435 51 1149 TL1: DB FCDNT, LEND ;Talk list for freq ctr
1434 FF
1159 ;
1151 ;SETUP FUNCTION GENERATOR
1437 36UD 1152 MVI B,CR ; EOS
1439 QEQF 1153 MVI C,LIM1 ¿Count
1438 111C14 1154 LXI D, FGDATA ;Data pointer
143E 213314 1155 LXI H,LL2 ¿Listen list pointer
1441 CD1C10 1156 CALL SEND
1157 ;
1158 ;SETUP FRED COUNTER
1159 ;
1444 9554 1169 MVI B, 'T' ; EOS
1446 JED6 1161 MVI C,LIM2 ¿Count
1448 112814 1162 LXI D, FCDATA ;Data pointer
144B 213114 1163 LXI H,LL] sListen list pointer
144E CDICI18 1164 CALL SEND
1185 y
1166 ; WAIT FOR SRO FROM FREO CTR
1167 ;
1451 CDD213 1168 LOOP: CALL SROD ¡Has SRO occurred ?
1454 CA5114 1169 JZ LOOP :No, wait for it
1179 ;
1171 ;SERIAL POLL TO CLEAR SRQ
1172 ;
1457 11893C 1173 LXI D,SPBYTE ;Buffer pointer
145A 213514 1174 LXI H, TL] ; Talk list pointer
145D CDIC12 1175 CALL SPOL
1408 18 1176 DCX D ¿Backup buffer pointer to ctr byte
1461 1A 1177 LDAX D ¿Get status byte
1462 E640 1178 ANT SROM ¿Did ctr assert SRO ?
1464 CA7714 1179 JZ ERROR +Ctr should have said yes
1189 ;
1181 ;RECEIVE READING FROM COUNTER
1182 ;
1467 060A 1183 MVI B, LF ; EOS
1469 9Е11 1184 MV I C,LIM3 ¿Count
146B 213514 1185 LXI H,TL1 ;Talk list pointer
146E 11013C 1185 LXI D, FCDATI ;Data in buffer pointer
1471 CD9FIG 1187 CALL RECV
1474 C27714 1188 JNZ ERROR
1189 ;
1199 ; ******* rest of user processing goes here *****
1191 ;
1192 ;
1477 80 1193 ERROR: NOP ;User dependant error handling
1194 ; ETC.
3C0% 1195 ORG 3CABH
3C00 1195 SPBYTE: DS 1 sLocation for serial poll byte
4211 1197 LIM3 EQU 17 ;Max freq counter input
45
3CO1 1198 FCDATI:
1199
PUBLIC SYMBOLS
EXTERNAL SYMBOLS
USER SYMBOLS
DS
END
ABORT A OQVF9 ADROI1 A 9056 ADRMD
BIM А 0091 BOF A 0791 BOM
CLRST A 92068 CMD92 A 0069 CPT
DCLR А 11ЕС DCLR1 A 11F9 DCLR2
EDEOS A 8084 ENDMK A 8018 EOIS
ERROR A 1477 EVBIT A 4710 EVCST
FCDNL A 9831 FCONT A 9451 FGDATA
GSEC A (0F4 GTS8 A QNF6 HOEND
IFCL A 1409 INIT А 1007 INT]
INTST A 9969 LA A 0071 LEND
LL] A 1431 LL2 A 1433 LOCL
MODE] A 9801 MTA A 0741 NVCMD
PPD A 0978 PPDS A 12E3 PPDS1
PPEN2 A 12D8 PPOL A 1327 PPU
RANGE + 03995 RBST A 00E7 RCST
RECV1 A 10EA RECV2 A 1195 RECV3
RERF A POE4 RERM A OIJEA REVC
SDEOI A 0906 SEND A 101C SENDI
SENDS A 1988 SETF + 0007 SLOC
SPIF A 08404 SPOL A 121C SPOL1
SROD1 A 13DB SROD2 A 13E2 SROM
TCNTR A MOFA TCSY A OVUFD TCT
TOST A 7068 TOUT] A 7081 TOUT2
UNL A AQ3F VSCMD A 090F WAITI
WOUT A ABEL XFER A 113A XFER1
ASSEMBLY COMPLETE, NO ERRORS
> + > > >» в р > Роб о > в» > > > > рэ в м» > в >
9064
90902
GARY
1299
9098
9068
141C
0002
9051
AFF
13F6
10937
12E4
0915
90E6
1106
90E3
102E
gOnF7
123D
7349
9779
9002
6072
1153
LIM3
ADRST
BUSST
CPTEN
DIN
EOIST
EVREG
FGNNL
HOHSK
INT2
LF
LON
OBFF
PPDS2
PPUN
RCTL
RECVA4
RINM
SEND2
SPBYTE
SPOL?
STCNI
TL]
TOUT 3
WAITO
XFER2
> + нэ м мены ро» > > р > > >
;Freq ctr input buffer
9954
9058
anal
A360
3020
0068
0032
anal
0052
BARA
3040
1078
12FD
131B
138B
1119
AgES
1047
3C90
1294
BGFE
1435
BABA
anol
115C
AUXMD
CAHCY
CPTRG
DOUT
E OSR
EXPP
FNHSK
IACK
INTM
LIM]
LOOP
PCTL
PPE
PRT91
RCTL1
RECVS
RSET
SEND3
SPCNI
SREM
TA
TLON
TRIG
WAITT
XFER3
> + ны озеро РРР»
A055
77123
0065
759
0057
ES
AAA
ganB
A3A0
ONF
1451
1344
dasa
27454
13CA
1117
IF?
1959
dara
PpFB
9072
20CA
11BC
#004
1193
> + > > № РБ Бо № о» > РБ PP
1089
09023
Anan
00958
12058
1428
0028
ana
9051
0095
0991
138A
12A3
0058
13CF
1139
BAF 3
1970
1719
70237
AFC
9720
110
9903
1188
AXRB
CLRA
DCL
DTDL2
ERRM
FCDATI
GIDL
IBFF
INTMR
LIM3
MLA
PPC
PPEN]
PRTE
RECV
REME
RTOUT
SENDS
SPE
SROD
TCIF
TOREG
TRIG2
NEVC
DPPDPDDPDPDDVPDDPDDDDDDDD+D
AAD
29727
9014
ONE?
0068
3C91
PAF1
9218
#258
7011
74021
9705
12А7
ARSE
199F
13E3
AES
107F
0718
1309
anna
0058
11D9
AE?
46
APPENDIX B
TEST CASESFORTHE SOFTWARE DRIVERS
The following test cases were used to exercise the
software routines and to check their action. To
provide another device/controller on the GPIB a
71488 СР1В Analyzer was used. This analyzer
SEND TEST
B =
С =
CASES
44
30
DE = 3E80
HL = 3E70
3E70:
3E80:
GPIB output:
Ending B
Ending C
Ending DE
Ending HL
RECEIVE TEST CASES
B
C
DE
HL
3E70:
GPIB output:
7,1488 Data
In
Ending A
Ending B
Ending C
Ending DE
Ending HL
20 30 3E 3F
11 44
41 ATN
3F ATN
20 ATN
30 ATN
3E ATN
11
44 EOI
= 44
=2E
= 3E82
= 3E73
= 44
= 30
= 3E80
= 3E70
40
40 ATN
ЗЕ АТМ
21 АТМ
= 3E85
= 3E71
2B
3E85
3E71
SERIAL POLL TEST CASES
C
DE
HL
3E70:
= 30
= 3E80
= 3E70
40
50
SE
SF
hexadecimal.
44
2
3E80
3E70
41 ATN
3F ATN
20 ATN
30 ATN
3E ATN
11
44 EOI
44
0
3E82
3E73
44 44 44
30 30 4
3E80 3E80 3E80
3E70 3E70 3E70
SE SF 40
SE AIN 40 ATN
3F ATN 3F ATN
21 ATN 21 ATN
1 1
2 2
3 3
44 EOI 4
0 SF 40
0 44 40)
2C 30 0
3E84 3E80 3E84
3E71 3E70 3E71
C = 30
DE = 3E80
HL = 3E70
3E70: SF
GPIB output: 3F ATN
21 ATN
18 ATN
47
acted as a talker, listener or another controller as
needed to execute the tests. The sequence of out-
puts are shown with each test. All numbers are
44
0
3E80
3E70
41 ATN
ЗЕ АТМ
20 ATN
30 ATN
ЗЕ АТМ
44
0
3E80
3E73
44 44
4 0=256
3E80 3E80
3E70 3E70
40 40
40 ATN 40 ATN
ЗЕ АТМ ЗЕ АТМ
21 АТМ 21 ATN
11 1
22 2
33 3
44 44
0 0
0 0
0 FC
3E84 3E84
3E71 3E71
19 ATN
Ending C = 30
Ending DE = 3E80
Ending HL = 3E70
GPIB output: 3F ATN
output: 21 ATN
output: 18 ATN
output: 40 ATN
input*: 00
output: 50 ATN
Input*: 41
output: 5E AIN
input*: 7F
output: 19 AIN
*NOTE: leave ZT488 in single step mode even on input
Ending C = 30
Ending DE = 3E83
Ending HL = 3E73
Ending 3E80: 00 41 7F
PASS CONTROL TEST CASES
HL = 3E70 3E70 3E70
3E70: 40 41(MTA) SF
GPIB output: 40 AIN
09 ATN
— ATN
Ending HL = 3E71 3E70 3E70
Ending A =02 41(MTA) SF
RECEIVE CONTROL TEST CASES
GPIB input 10 ATN 40 ATN 41 ATN
ATN 09 ATN 09 ATN
Run Receive Control
GPIB Input ATN AIN
Ending À = 0 09
PARALLEL POLL ENABLE TEST CASES
DE = 3E80 3E80
HL = 3E70 3E70
3E70: 20 30 3E 3F 3F
3E80: 01 02 03
GPIB output: 3F ATN 3F ATN
20 ATN
05 ATN
61 ATN
30 ATN
05 ATN
62 ATN
3E ATN
05 ATN
63 ATN
Ending DE = 3E83 3E80
Ending HL = 3E73 3E70
PARALLEL POLL DISABLE TEST CASES
HL = 3E70
3E70:
20 30 3E 3F
3E70
3F
48
GPIB output: 3F AIN ЗЕ АТМ
20 ATN 05 ATN
30 ATN 70 ATN
ЗЕ АТМ |
05 ATN
70 ATN
Ending HL = 3E73 3E70
PARALLEL POLL UNCONFIGURE TEST CASE
GPIB output: 15 ATN
PARALLEL POLL TEST CASES
Set DIO# 1 2 3 4 5 6 7 8 None
Ending A 1 2 4 8 10 20 40 80 O
SRQ TEST
Set SRQ momentarily Reset SRQ
Ending À =02 00
TRIGGER TEST
HL = 3E70
DE = 3E80
BC = 4430
3E70: 20 30 3E 3F
GPIB output: 3F ATN
20 ATN
30 ATN
3E ATN
08 AIN
Ending HL = 3E73
DE = 3E80
BC = 4430
DEVICE CLEAR TEST
HL = 3E70
DE = 3E80
BC = 4430
3E70: 20 30 3E 3F
GPIB output: 3F ATN
20 ATN
30 ATN
ЗЕ АТМ
14 ATN
Ending HL = 3E73
DE = 3E80
RC = 4430
49
XFER TEST
B = 44
HL = 3E70
3E70: 40 20 30 3E 3F
GPIB output: 40 ATN
3F ATN
20 ATN
30 ATN
3E ATN
GPIB input: 0
1
2
3
44
Ending À = 0
B = 44
HL = 3E74
APPLICATION EXAMPLE
GPIB OUTPUT/INPUT
GPIB output: 41 ATN
3F ATN
32 ATN
46
55
31
46
52
33
37
4B
48
41
4D
32
56
4F
0D EOI
41 ATN
3F ATN
31 ATN
50
46
34
47
37
54 EOI
GPIB input: SRQ
GPIB output: 3F AIN
21 ATN
18 ATN
51 ATN
GPIB input: 40 SRQ
GPIB output: 19 ATN
51 ATN
3F ATN
21 ATN
GPIB input: 20
2B
20
20
20
33
37
30
30
30
2E
30
45
2B
30
0D
0A
GPIB output: XX ATN
APPENDIX C
REMOTE MESSAGE CODING
Bus Signal Line(s) and
Coding That Asserts the
( True Value of the Message
T |; D D NN
y al 1 DRDAESI R
p s o O AFATORFE
Mnemonic Message Name e s 8 7 6 5 4 3 2 1 VDCNI QC N
ACG addressed command group M AC Y Y Y 9 x X X X XXX 1 X X X X
ATN attention U ue X X X X X X X X XXX 1 X X X X
DAB data byte (Notes 1, 9) M DD PDDDDDDDXXXO X XXX
8 76654 321
DAC data accepted U us X X X X X X X X XX0 X X X X X
DAV data valid U HS X X X X X X X X 1XX X XXX X
DCL =— device clear M uc Yo 01 91 0 0 XXX1 X X X X
END end U ST x X X X X X X X XXX Q 1 X X X
EOS end of string (Notes 2, 9) M DD EE E E E E E E XXX 0 X X x X
8 7 6 5 4 3 2 1
GET group execute trigger M AC Y 9 001 0 0 0 XXX1 X X XX
GTL go to local M AC YO 0 0 0 0 01 XXX 1X XXX
IDY identify U UC X XX XX XX X XXXX1 X XX
IFC interface clear U UC XXX X X X X Хх XXX X X X 1 X
LAG listen address group M AD Y Y 1 XXX X X XXX 1 X X X X
LLO local lock out M UC YO 01 0 06 01 XXX 1 XX XX
MLA my listen address (Note 3) M AD Y 9 1 LLL LULXXX1X XXX
5 4 3 2 1
MTA my talk address “Note 4) M AD Y 1 ¢ TT TTT XXX 1 X X X X
5 4 3 2 1
MSA my secondary address (Note 5) M SE Y 1 1 5 5 $ 5 SS XXX1 XX X
5 4 3 2 1
51
Bus Signal Line(s) and
Coding That Asserts the
C True Value of the Message
T 1 D D NN
y a | I DRDA ES 1 R
p s O O AFAT ORF E
Mnemonic Message Name e s 8 76 54 3 21 VDCNI QCN
NUL null byte M DD 0 0 0 0 0 0 0 9 XXXX X X XX
OSA other secondary address M SE (OSA = SCG A MSA)
OTA — other talk address M AD (OTA =TAGA MTA)
PCG primary command group M — (PCG = ACG V UCG V LAG V TAG)
PPC parallel poll configure M ACY 0 9001091 XXX1XXXX
PPE parallel poll enable (Note 6) М SE Y1 19g SPPP xxx 1 x x x x
3 2 1
PPD parallel poll disable (Note 7) M SE Y 1 11 D 5 5 р XXX IT X X X X
PPR1 parallel poll response 1 U ST XX X X X X X 1 XXX1 1 XXX
PPR2 parallel poll response 2 U ST X X X X X X 1 X XXX 1 1 XXX
PPR3 parallel poll response 3 (Note 10) U ST XX X X X 1 X X XXX 11 X X X
PPR4 parallel poll response 4 U ST XX X X 1 XXX XXX1 1 X XX
PPR5 parallel poll response 5 U ST XXX1XXXX XXX11XXX
PPR6 parallel poll response 6 U ST X X 1 X X X X X XXX 11 X XX
PPR7 parallel poll response 7 (Note 10) U ST X 1 X X X X X X XXX 1 1 X X X
PPR& parallel poll response 8 U ST 1 XX X X X X X XXX 1 1 X X X
PPU parallel poll unconfigure M UCYO A101 01 XXX 1 X X X X
REN remote enable U UCX X X X X X X X XXX XXX XI
RFD ready for data U HS X X X X X X X X XOX X X X X X
RQS request service (Note 9) U ST X1 XXX XXX XXX ¢g XX XX
SCG secondary command group M SE Y 11 X X X X X XXX 1X XXX
SDC selected device clear M AC YD 00 01 0 0 XXX 1 X X X X
SPD serial poll disable M UC Yd 911901 XXX 1 X XXX
SPE serial poll enable M UCYOQ®OQO 11000 XXX1XXXX
SRQ service request U ST X X X X X X X X XXX X X 1 X X
STB status byte (Notes 8, 9) M ST S XS SS SSS XXX ¢ XX XX
8 6 5 4 3 2 1
TCT take control M AC YQ 001001 XXX 1 X X X X
TAG talk address group М AD Y 1 9 X X X X X XXX I X X X X
UCG universal command group M UC Y9? 91 XXXX XXX 1X XXX
UNL unlisten M AD YO 1 1 1 1 1 1 XXX 1 X XXX
UNT untalk (Note 11) М AD Y1 91 1 1 1 1 XXX 1 X X XX
The 1/9 coding on ATN when sent concurrent with multiline messages has been added to this revision for interpre-
tive convenience.
NOTES:
(1) D1-D8 specify the device dependent data bits.
(2) El-E8 specify the device dependent code used to
indicate the EOS message.
(3) L1-L5 specify the device dependent bits of the
device's listen address.
(4) T1-T5 specify the device dependent bits of the
device's talk address.
(5) S1-S5 specify the device dependent bits of the de-
vice's secondary address.
(6) S specifies the sense of the PPR,
S Response
Ô 0
1 1
P1-P3 specify the PPR message to be sent when a paral-
lel poll is executed.
P3 Р2 Р1 PPR Message
0 0 0 PPRI
1 1 1 PPRS
(7) D1-D4 specify don’t-care bits that shall not be
decoded by the receiving device. It is recommended
that all zeroes be sent.
(8) S1-S6, S8 specify the device dependent status.
(DIO7 is used for the RQS message. )
(9) The source of the message on the ATN line is
always the C function, whereas the messages on the
DIO and EOI lines are enabled by the T function.
(10) The source of the messages on the ATN and EOI
lines is always the C function, whereas the source of
the messages on the DIO lines is always the PP func-
tion.
(11) This code is provided for system use, see 6.3.
52
intel
INTEL CORPORATION, 3065 Bowers Avenue, Santa Clara, CA 95051 e (408) 987-8080
Printed in U.S.A. T197/180/15K TL
">