Ni NAT7210 Reference User Manual

NAT7210 TM

Reference Manual

June 1995 Edition

Part Number 370875A-01

© Copyright 1994, 1995 National Instruments Corporation.

All Rights Reserved.

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Limited Warranty

The NAT7210

™

integrated circuit (“equipment”) is warranted against defects in material and workmanship under normal use and service for a period of one (1) year from the date of shipment from the National Instruments factory. During this period of one year,

National Instruments shall at its sole option either repair, replace, or credit the Buyer for defective equipment if: (i) Buyer returns the equipment to National Instruments, FOB the

National Instruments factory in Austin, Texas; (ii) Buyer notifies National Instruments promptly upon discovery of any defect in writing, including a detailed description of the defect; and (iii) upon examination of the returned equipment, National Instruments is satisfied that the circuit is defective and that the cause of such defect is not alteration or repair by someone other than National Instruments, neglect, accident, misuse, improper installation, or use contrary to any instructions issued by National Instruments.

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This warranty expires one year from date of original shipment regardless of any warranty performance during that warranty period. The warranty provided herein is Buyer’s sole and exclusive remedy for nonconformity of the equipment or for breach of any warranty.

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Under the copyright laws, this publication may not be reproduced or transmitted in any form, electronic or mechanical, including photocopying, recording, storing in an information retrieval system, or translating, in whole or in part, without the prior written consent of National Instruments Corporation.

Trademarks

NAT7210

™

is a trademark of National Instruments Corporation.

Product and company names listed are trademarks or trade names of their respective companies.

WARNING REGARDING MEDICAL AND CLINICAL

USE OF NATIONAL INSTRUMENTS PRODUCTS

National Instruments products are not designed with components and testing intended to ensure a level of reliability suitable for use in treatment and diagnosis of humans.

Applications of National Instruments products involving medical or clinical treatment can create a potential for accidental injury caused by product failure, or by errors on the part of the user or application designer. Any use or application of National Instruments products for or involving medical or clinical treatment must be performed by properly trained and qualified medical personnel, and all traditional medical safeguards, equipment, and procedures that are appropriate in the particular situation to prevent serious injury or death should always continue to be used when National Instruments products are being used. National Instruments products are NOT intended to be a substitute for any form of established process, procedure, or equipment used to monitor or safeguard human health and safety in medical or clinical treatment.

Contents

About This Manual

.............................................................................................

Chapter 1

Introduction and General Description

........................................................

Chapter 2

NAT7210 Architecture

.......................................................................................

Chapter 3

7210-Mode Interface Registers

.......................................................................

© National Instruments Corp.

v NAT7210 Reference Manual

Contents

Chapter 4

9914-Mode Interface Registers

.......................................................................

NAT7210 Reference Manual vi © National Instruments Corp.

Contents

Chapter 5

Software Considerations

...................................................................................

A.

Set the GPIB Address(es) ..........................................

B.

Write the Initial Serial Poll Response ........................

C.

Configure Initial Parallel Response ...........................

D.

Set GPIB Handshake Parameters ...............................

Implementing One Logical Device: Normal

Implementing One Logical Device: Extended

Implementing Two Logical Devices: Normal

Implementing Two Logical Devices: Extended

Implementing Three or More Logical Devices:

Implementing Three or More Logical Devices:

© National Instruments Corp.

vii NAT7210 Reference Manual

Contents

Chapter 6

Controller Software Considerations

.............................................................

Other System Controller Capabilities: Setting and

NAT7210 Reference Manual viii © National Instruments Corp.

Contents

Chapter 7

Hardware Considerations

.................................................................................

Appendix A

Common Questions

.............................................................................................

Appendix B

Introduction to the GPIB

..................................................................................

© National Instruments Corp.

ix NAT7210 Reference Manual

Contents

Appendix C

Standard Commands for Programmable Instruments (SCPI)

.........

Constructing SCPI Commands by Using the Hierarchical

Appendix D

Multiline Interface Command Messages

....................................................

Appendix E

Mnemonics Key

.....................................................................................................

Appendix F

Customer Communication

...............................................................................

Glossary

....................................................................................................................

NAT7210 Reference Manual x © National Instruments Corp.

Contents

Index

..........................................................................................................................

Figures

Figure 1-1.

NAT7210 Implementation Block Diagram .........................................

Figure 2-1.

NAT7210 Block Diagram ...................................................................

Figure 2-2.

Changing the NAT7210 Mode ............................................................

Figure 3-1.

GPIB I/O Hardware Configuration .....................................................

Figure 4-1.

GPIB I/O Hardware Configuration .....................................................

Figure 6-1.

Basic Controller States ........................................................................

Figure 7-1.

CLK Signal Timing Diagram ..............................................................

Figure 7-2.

Interfacing the NAT7210 to the 75160 and 75162 Transceivers ........

Figure B-1.

Structure of the GPIB Standards .........................................................

Figure B-2.

Linear Configuration ...........................................................................

Figure B-3.

Star Configuration ...............................................................................

Figure B-4.

GPIB Connector and Pin Assignments ...............................................

Figure B-5.

Three-Wire Handshake Process ..........................................................

Figure B-6.

System Setup Example .......................................................................

Figure B-7.

Events During a Serial Poll .................................................................

Figure B-8.

IEEE 488.2 Standard Status Structures ...............................................

Figure B-9.

Example Exchange of Messages During a Parallel Poll .....................

Figure C-1.

Partial Command Categories ..............................................................

Figure C-2.

Simple Command Tree for the SENSe Command Subsystem ...........

Figure C-3.

Partial Command Tree for the SENSe Command Subsystem ............

Figure C-4.

Partial Command Tree for the SOURce Command Subsystem .........

Figure C-5.

Partial Command Tree for the TRIGger Command Subsystem .........

© National Instruments Corp.

xi NAT7210 Reference Manual

Contents

Tables

Table 1-1.

NAT7210 IEEE 488 Interface Capabilities .........................................

Table 3-1.

7210-Mode Register Map ...................................................................

Table 3-2.

Hidden Registers at Offset 6 (ADR) ...................................................

Table 3-3.

Hidden Registers at Offset 5 (AUXMR) .............................................

Table 3-4.

Valid ADMR Patterns .........................................................................

Table 3-5.

Auxiliary Command Summary ...........................................................

Table 3-6.

Auxiliary Command Description ........................................................

Table 3-7.

Clear Conditions for SISB Bit ............................................................

Table 4-1.

9914-Mode Interface Registers ...........................................................

Table 4-2.

Hidden Registers at the ACCR Offset ................................................

Table 4-3.

Auxiliary Command Summary ...........................................................

Table 4-4.

Auxiliary Command Description ........................................................

Table 5-1.

IEEE 488.1 Minimum T1 Delay Requirements ..................................

Table 5-2.

T1 5-10

Table 5-3.

5-10

Table 5-4.

Parallel Poll Register Example ...........................................................

Table 6-1.

Basic Controller State .........................................................................

Table B-1.

IEEE 488.1 Standard Status Data Structure ........................................

Table B-2.

PPR Message Value ............................................................................

Table B-3.

Determining the PPE Message ............................................................

Table C-1.

IEEE 488.2 Common Commands Required by SCPI .........................

Table C-2.

SCPI Required Commands .................................................................

NAT7210 Reference Manual xii © National Instruments Corp.

About This Manual

This manual describes the programmable features of the NAT7210 and contains information that is suitable for programmers and engineers who wish to write software for the NAT7210.

This manual assumes that you are already familiar with general IEEE 488 concepts.

Organization of This Manual

This manual is organized as follows:

• Chapter 1, Introduction and General Description, explains the features and capabilities of the NAT7210.

• Chapter 2, NAT7210 Architecture, discusses the internal hardware architecture of the

NAT7210.

• Chapter 3, 7210-Mode Interface Registers, contains NAT7210 address maps and detailed descriptions of the NAT7210 interface registers in 7210 mode.

• Chapter 4, 9914-Mode Interface Registers, contains NAT7210 address maps and detailed descriptions of the NAT7210 interface registers in 9914 mode.

• Chapter 5, Software Considerations, explains important NAT7210 programming considerations, including chip initialization, Talkers and Listeners, message reception, and holdoffs.

• Chapter 6, Controller Software Considerations, explains important system and GPIB

Controller considerations.

• Chapter 7, Hardware Considerations , explains important NAT7210 hardwareinterfacing considerations, including a description of the pins.

• Appendix A, Common Questions , lists common questions and answers.

• Appendix B, Introduction to the GPIB, discusses the history of the GPIB, GPIB hardware configurations, and serial polling.

• Appendix C, Standard Commands for Programmable Instruments (SCPI), discusses the SCPI document, the required SCPI commands, and SCPI programming.

• Appendix D, Multiline Interface Command Messages, lists the multiline interface messages and describes the mnemonics and messages that correspond to the interface functions.

© National Instruments Corp.

xiii NAT7210 Reference Manual

About This Manual

• Appendix E, Mnemonics Key, defines the mnemonics (abbreviations) that this manual uses for functions, remote messages, local messages, states, bits, registers, integrated circuits, and system functions.

• Appendix F, Customer Communication, contains forms you can use to request help from National Instruments or to comment on our products and manuals.

• The Glossary contains an alphabetical list and a description of the terms, including abbreviations, acronyms, metric prefixes, mnemonics, and symbols, that this manual uses.

• The Index contains an alphabetical list of the key terms and topics that this manual uses, and it includes the page number where you can locate each term and topic.

Conventions Used in This Manual

This manual uses the following conventions.

italic bold italic monospace

IEEE 488 and

IEEE 488.2

Italic text denotes emphasis, a cross reference, or an introduction to a key concept.

Bold italic text denotes a note, caution, or warning.

Text in this font denotes programming examples.

IEEE 488 and IEEE 488.2 refer to the ANSI/IEEE

Standard 488.1-1987 and ANSI/IEEE Standard 488.2-1992, respectively, which define the GPIB.

The Glossary lists abbreviations, acronyms, metric prefixes, mnemonics, symbols, and terms.

Related Documentation

The following documents contain information that you may find helpful as you read this manual.

• 40-Pin IEEE 488.2 Controller Chip: Drop-In Replacement for NEC

µ

PD7210

NAT7210APD

• ANSI/IEEE Standard 488.1-1987, IEEE Standard Digital Interface for

Programmable Instrumentation

• ANSI/IEEE Standard 488.2-1992, IEEE Standard Codes, Formats,

Protocols, and Common Commands

NAT7210 Reference Manual xiv © National Instruments Corp.

About This Manual

You may obtain the two ANSI/IEEE documents through the Institute of Electrical and

Electronics Engineers, 345 East 47th Street, New York, New York 10017.

You may obtain more information about Standard Commands for Programmable

Instruments from the SCPI Consortium, 8380 Hercules Drive, Suite P3, La Mesa,

CA 91942.

Customer Communication

National Instruments wants to receive your comments on our products and manuals. We are interested in the applications you develop with our products, and we want to help if you have problems with them. To make it easy for you to contact us, this manual contains comment and configuration forms for you to complete. These forms are in

Appendix F, Customer Communication, at the end of this manual.

© National Instruments Corp. xv NAT7210 Reference Manual

Chapter 1

Introduction and General Description

This chapter explains the features and capabilities of the NAT7210.

The NAT7210 is an IEEE 488.2 Controller chip designed to perform all the interface functions defined in the ANSI/IEEE Standard 488.1-1987 and the additional requirements and recommendations of the ANSI/IEEE Standard

488.2-1987. The NAT7210 manages the IEEE 488 interface functions with a set of control and status registers that increase the throughput of driver software and simplify hardware and software design. The NAT7210 performs complete

IEEE 488 Talker, Listener, and Controller functions and is software compatible with the NEC

µ

PD7210 and TI TMS9914A chips.

The NAT7210 can be characterized as a bus translator: it converts messages and signals from the CPU into appropriate GPIB messages and signals. In GPIB terminology, the NAT7210 implements GPIB board and device functions to communicate with the central processor and memory. For the computer, the

NAT7210 is an interface to the outside world.

IEEE 488 Capabilities

The National Instruments NAT7210 has the features necessary to provide a high-performance IEEE 488 interface. Table 1-1 lists the capabilities of the NAT7210 in terms of the IEEE 488 standard codes.

Table 1-1. NAT7210 IEEE 488 Interface Capabilities

Capability Code

SH1

Description

Complete Source Handshake Capability

AH1

T5

Complete Acceptor Handshake Capability;

DAC and RFD Holdoff on Certain Events

Complete Talker Capability:

• Basic Talker

• Serial Poll

• Talk-Only Mode

• Unaddressed on MLA

• Send END or EOS

© National Instruments Corp.

1-1

(continues)

NAT7210 Reference Manual

Introduction and General Description Chapter 1

Table 1-1. NAT7210 IEEE 488 Interface Capabilities (Continued)

Capability Code

TE5

Description

Complete Extended Talker Capability:

• Basic Extended Talker

• Serial Poll

• Talk-Only Mode

• Unaddressed on MSA & LPAS

• Send END or EOS

L3

LE3

Complete Listener Capability:

• Basic Listener

• Listen-Only Mode

• Unaddressed on MTA

• Detect END or EOS

Complete Extended Listener Capability:

• Basic Extended Listener

• Listen-Only Mode

• Unaddressed on MSA & TPAS

• Detect END or EOS

SR1

RL1

PP1

PP2

Complete Service Request Capability

Complete Remote/Local Capability

Remote Parallel Poll Configuration

Local Parallel Poll Configuration

DC1

DT1

Complete Device Clear Capability

Complete Device Trigger Capability

C1 through C5 Complete Controller Capability:

• System Controller

• Send IFC and Take Charge

• Send REN

• Respond to SRQ

• Send Interface Messages

• Received Control

• Parallel Poll

• Take Control Synchronously or Asynchronously

E2 Three-State Drivers (Open-Collector Drivers During Parallel

Polls)

NAT7210 Reference Manual 1-2 © National Instruments Corp.

Chapter 1 Introduction and General Description

The NAT7210 has complete Source and Acceptor Handshake capability. It can operate as a basic Talker or an extended Talker and can respond to a Serial Poll. If you place it in talk-only mode, it is unaddressed to talk when it receives its listen address. The

NAT7210 GPIB interface can also operate as a basic Listener or an extended Listener.

If you place it in listen-only mode, it is unaddressed to listen when it receives its talk address. The NAT7210 can request service from a Controller.

Device Clear and Trigger capability is included in the interface; the interpretation is software dependent.

Other GPIB features include the following:

• Messages not sent when there are no Listeners

• Automatic detection of EOS and/or NL messages

• Automatic bus synchronization detection

• Programmable data transfer rates (T1 delays as short as 350 ns)

• Programmable GPIB transceiver support

• Automatic processing of IEEE 488 commands and read-undefined commands

• Ability to use six addressing modes:

– Automatic single or dual primary addressing detection

– Automatic single primary with single secondary address detection

– Single or dual primary with multiple secondary addressing

– Multiple primary addressing

CPU Interface Capabilities

• Software compatible with NEC

µ

PD7210 and TI TMS9914A Controller chips

• DMA interface to the host system

• Flexible interrupt capabilities

• Uses only eight bytes of address space

© National Instruments Corp.

1-3 NAT7210 Reference Manual

Introduction and General Description Chapter 1

Typical System Interface

Figure 1-1 shows a block diagram of a typical application that uses the NAT7210 to implement an IEEE 488.2 interface.

CPU Bus

Control

Address

Decode

Data

Interrupt

NAT7210

GPIB

XCVR

GPIB

XCVR

Figure 1-1. NAT7210 Implementation Block Diagram

In all applications, the NAT7210 must be connected to the GPIB via IEEE 488 compliant transceivers such as the 75160 and 75162, which are available from National

Semiconductor and other vendors. The NAT7210 has control signals that let it easily interface to several different types of transceivers.

NAT7210 Reference Manual 1-4 © National Instruments Corp.

Chapter 2

NAT7210 Architecture

This chapter discusses the internal hardware architecture of the NAT7210.

The NAT7210 includes the following major components:

• Read/Write Control converts the CPU interface signals to read and write signals for each internal NAT7210 register.

• Internal NAT7210 Registers configure and control the operation of the NAT7210.

They transfer data between the NAT7210 and the GPIB, report status information, and set the operating modes. Chapter 3, 7210-Mode Interface Registers , and

Chapter 4, 9914-Mode Interface Registers, describe each register in detail.

• Interface Functions implement the interface functions described in the IEEE 488.1

standard. Some internal registers control the interface functions, and you can use other internal registers to monitor the status of interface functions. The interface functions drive and receive the GPIB control signals and generate the signals to control the GPIB transceivers.

• Message Decoders receive the GPIB data lines and decode the GPIB commands that affect the operation of the interface functions.

© National Instruments Corp.

2-1 NAT7210 Reference Manual

NAT7210 Architecture

Figure 2-1 contains a block diagram of the NAT7210.

D(7-0)

CS*

RS(2-0)

RD*

WR*

DRQ

DACK*

Read/

Write

Control

INT

CLK

RESET

Data-In

Command Pass Through

Command/Data Out

Address Status

Address Mode

Address

End-Of-String

Interrupt Mask 0, 1, 2

Interrupt Status 0, 1, 2

Internal Count

Internal Count 2

Serial Poll

Parallel Poll

Aux A, B, E, F, G, I

SASR

Auxiliary

Command Decoder

Version

Figure 2-1. NAT7210 Block Diagram

Chapter 2

DIO(8-1)*

Message

Decoder

Interface

Functions

SH1

AH1

T5/TE5

L3/LE3

SR1

RL1

PP1/PP2

DC1

DT1

C1-C5

RSV Gen

EOI Gen

STB Out

SYNC

T/R3

T/R2

T/R1

Bus Status and Control

GPIB

Control

NAT7210 Reference Manual 2-2 © National Instruments Corp.

Chapter 2 NAT7210 Architecture

NAT7210 Modes

The NAT7210 has two basic modes of operation: 7210 mode and 9914 mode.

In 7210 mode, the NAT7210 is software compatible with the

µ

PD7210 IEEE 488

Controller. The NAT7210 has many registers and features that are not present in the

µ

PD7210. In 9914 mode, the NAT7210 is software compatible with the TMS9914A

IEEE 488 Controller. The NAT7210 has many registers and features that are not present in the TMS9914A.

Note: Throughout this manual, 7210 mode refers to the NEC

µ

PD7210 software compatibility mode, and 9914 mode refers to the TI TMS9914A software compatibility mode.

Changing the NAT7210 Mode

Figure 2-2 illustrates how you change the mode of the NAT7210.

7210 Mode sw9914 Auxiliary

Command sw7210 Auxiliary

Command

Hardware Reset

9914 Mode

Figure 2-2. Changing the NAT7210 Mode

Notice that the NAT7210 is in 7210 mode after a hardware reset. To change from 7210 mode to 9914 mode, write the sw9914 auxiliary command to the (7210 mode) Auxiliary

Mode Register (AUXMR). To change from 9914 mode to 7210 mode, write the sw7210 auxiliary command to the (9914 mode) Auxiliary Command Register (AUXCR).

© National Instruments Corp.

2-3 NAT7210 Reference Manual

Chapter 3

7210-Mode Interface Registers

This chapter contains NAT7210 address maps and detailed descriptions of the NAT7210 interface registers in 7210 mode. For 9914-mode register descriptions, see Chapter 4,

9914-Mode Interface Registers.

7210 Register Map

Table 3-1 is the register bit map for the NAT7210 in 7210 mode.

Notice that bold-ruled cells distinguish seven registers that are accessible only when the

Page-In state is true. Refer to The Page-In State section that immediately follows the register map for more information.

© National Instruments Corp.

3-1 NAT7210 Reference Manual

7210-Mode Interface Registers

Table 3-1. 7210-Mode Register Map

Chapter 3

Key

R

W

= 7210-Mode Paged Registers

= Read Register

= Write Register

DIR

CDOR

+0

+0

7

DIO8

DIO8

6

DIO7

DIO7

5

DIO6

DIO6

4

DIO5

DIO5

3

DIO4

DIO4

2

DIO3

DIO3

1

DIO2

DIO2

0

DIO1

DIO1

R

W

ISR1

IMR1

+1

+1

CPT

CPT IE

APT

APT IE

DET

DET IE

END RX

END IE

DEC

DEC IE

ERR

ERR IE

DO

DO IE

ISR2

IMR2

+2

+2

INT

0

SRQI

SRQI IE

LOK

DMAO

REM

DMAI

CO

CO IE

DI

DI IE

R

W

LOKC

LOKC IE

REMC

REMC IE

ADSC

ADSC IE

R

2

SPSR

VSR

ICR2

SPMR

+3

+3

+3

+3

S8

V3

1

S8

PEND

V2

0 rsv/RQS

S6

V1

SLOW

S6

S5

V0

0

S5

S4

X

0

S4

S3

X

0

S3

S2

X

0

S2

S1

X

MICR

S1

W

W

R

R

ADSR +4

ADMR +4

CIC ton

ATN* lon

SPMS

TRM1

LPAS

TRM0

TPAS

0

LA

0

TA

ADM1

MJMN

ADM0

R

W

CPTR +5

SASR +5

AUXMR +5

CPT7 nba

AUX7

CPT6

AEHS

AUX6

CPT5

ANHS1

AUX5

CPT4

ANHS2

AUX4

CPT3

ADHS

AUX3

CPT2

ACRDY

AUX2

CPT1

SH1A

AUX1

CPT0

SH1B

AUX0

R

R

W

ADR0

ISR0

IMR0

ADR

+6

+6

+6

+6

X nba

GLINT

ARS

DT0

STBO

STBO 1E

DT

DL0

NL

NLEN

DL

AD5-0

EOS

BTO

AD5

AD4-0

IFCI

IFCI IE

AD4

AD3-0

ATNI

ATNI IE

AD3

AD2-0

X

0

AD2

AD1-0

SYNC

SYNC IE

AD1

R

R

W

W

ADR1

BSR

BCR

EOSR

+7

+7

+7

+7

EOI

ATN

ATN

EOS7

DT1

DAV

DAV

EOS6

DL1

NDAC

NDAC

EOS5

AD5-1

NRFD

NRFD

EOS4

AD4-1

EOI

EOI

EOS3

AD3-1

SRQ

SRQ

EOS2

AD2-1

IFC

IFC

EOS1

AD1-1

REN

REN

EOS0

R

R

W

W

NAT7210 Reference Manual 3-2 © National Instruments Corp.

Chapter 3 7210-Mode Interface Registers

The Page-In State

At some offsets, Table 3-1 shows two readable or two writable registers. The shaded registers in Table 3-1 are accessible only when the Page-In state is true. For each shaded register, the corresponding unshaded register is accessible only when the Page-In state is false.

How to Page-In

The NAT7210 enters the Page-In state when the host interface writes the Page-In auxiliary command to the Auxiliary Mode Register (AUXMR). The NAT7210 registers appear at their Page-In state offset for the first register access after the Page-In command.

The NAT7210 leaves the Page-In state at the end of the first register access after the

Page-In command.

Hidden Registers

In addition to the registers shown in Table 3-1, the NAT7210 contains hidden registers.

All hidden registers are write-only registers. Two or more hidden registers can appear at the same offset. When you write an 8-bit pattern to these offsets, some of the bits determine which hidden register will be written. The other bits represent the value written to the register.

Address Register Map

The NAT7210 has two address registers: ADR1 and ADR0. Table 3-1 shows the offsets for the readable portion of ADR1 and ADR0. The writable portion of ADR0 and ADR1 appears at the offset of the Address Register (ADR) shown in Table 3-1. Table 3-2 shows the bit map for the two writable address registers.

Register Bit 7

ADR0 0

ADR1 1

Table 3-2. Hidden Registers at Offset 6 (ADR)

Bit 6

DT0

DT1

Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

DL0 AD5–0 AD4–0 AD3–0 AD2–0 AD1–0

DL1 AD5–1 AD4–1 AD3–1 AD2–1 AD1–1

© National Instruments Corp.

3-3 NAT7210 Reference Manual

7210-Mode Interface Registers Chapter 3

Auxiliary Mode Register Map

Several hidden registers appear at the AUXMR offset. Table 3-3 shows these hidden registers.

Table 3-3. Hidden Registers at Offset 5 (AUXMR)

Register Bit 7 Bit 6 Bit 5 Bit 4

PPR 0 1 1 U

AUXRA

AUXRB

1

1

0

0

0

1

BIN

ISS

AUXRE

AUXRF

AUXRG

AUXRI

ICR

1

1

0

1

0

1

1

1

1

0

0

0

0

1

1

0

1

0

0

0

Bit 3

S

XEOS

INV

Bit 2

P 3

REOS

TRI

Bit 1

P 2

HLDE

SPEOI

Bit 0

P 1

HLDA

CPT

ENABLE

DHADT DHADC DHDT DHDC

DHATA DHALA DHUNTL DHALL

NTNL

USTD

F 3

RPP2

PP2

F 2

DISTCT

0

F 1

CHES

SISB

F 0

Register Bit Descriptions

Some 7210-mode registers and 9914-mode registers share identical names. The

9914-mode registers are described in Chapter 4, 9914-Mode Interface Registers. If you are using the NAT7210 in 7210 mode, be sure to read the proper description for the

7210-mode registers.

All registers are listed in alphabetical order. The registers are alphabetized according to their mnemonics.

NAT7210 Reference Manual 3-4 © National Instruments Corp.

Chapter 3 7210-Mode Interface Registers

Address Mode Register (ADMR)

Attributes: Write only

7 ton

6 lon

5 4

TRM1 TRM0

3

0

2

0

1

ADM1

0

ADM0

The host interface can put the NAT7210 into one of six GPIB addressing modes by writing to the Address Mode Register (ADMR). The values of ADMR (7–6; 3–0) are undefined after a hardware reset. Before the host interface can clear pon, it must write a valid pattern to the ADMR.

Table 3-4. Valid ADMR Patterns

Hex Value of

ADMR*

30 No Addressing

31

GPIB Addressing Mode

The Controller cannot address the NAT7210 to become a Talker or

Listener in no-addressing mode.

Normal Dual Addressing

32

The NAT7210 can implement one or two logical devices by using normal dual addressing.

See the GPIB Addressing section in Chapter 5, Software Considerations .

Extended Single Addressing

Extended single addressing mode implements the Extended Listener and

Extended Talker functions, as defined in the IEEE 488 standard, without intervention from the host interface.

33

See the GPIB Addressing section in Chapter 5, Software Considerations .

Extended Dual Addressing

Extended dual addressing mode implements the Extended Listener and

Extended Talker functions, as defined in the IEEE 488 standard. This mode requires intervention from the host interface.

See the GPIB Addressing section in Chapter 5, Software Considerations .

(continues)

© National Instruments Corp.

3-5 NAT7210 Reference Manual

7210-Mode Interface Registers Chapter 3

ADMR (continued)

Table 3-4. Valid ADMR Patterns (Continued)

Hex Value of

ADMR*

70 Listen Only (lon)

B0

GPIB Addressing Mode

The NAT7210 becomes a GPIB Listener and enters the Listener Active

State (LACS). Do not use lon if a GPIB Controller is present in the

GPIB system.

The host interface should write a hex 30 (No Addressing) to the ADMR immediately after writing lon to the ADMR. To force the NAT7210 to exit LACS, issue the unlisten (lul) auxiliary command.

Talk Only (ton)

The NAT7210 becomes a GPIB Talker. Do not use ton if a GPIB

Controller is present in the GPIB system.

The host interface should write a hex 30 (No Addressing) to the ADMR immediately after writing ton to the ADMR. To force the NAT7210 to exit TACS, issue the local untalk (lut) auxiliary command.

* The hex values in Table 3-4 assume that TRM1 = 1 and TRM0 = 1.

NAT7210 Reference Manual 3-6 © National Instruments Corp.

Chapter 3

ADMR (continued)

Bit

5–4w

Mnemonic

TRM[1–0]

7210-Mode Interface Registers

Description

Transmit/Receive Mode bit

TRM1 and TRM0 control the function of the NAT7210

T/R2 and T/R3 output pins in the following manner:

TRM1 TRM0 T/R2

0 0 EOIOE

T/R3

TRIG

0

1

1

1

0

1

CIC

CIC

CIC

TRIG

EOIOE

PE

Key:

EOIOE = GPIB EOI signal output enable

TACS + SPAS + CIC & ~(CSBS +

CIC

TRIG

CSHS)

= Controller-in-Charge (CIDS + CADS)

= Trigger (pulses when DTAS = 1 or a trigger auxiliary command is issued)

PE = Pull-up enable (CIC + -(PPAS))

A hardware reset clears TRM1 and TRM0.

Note: In many applications, the NAT7210 is interfaced to a 75160 and a 75162 GPIB transceiver. In these applications, TRM1 and

TRM0 should always be set.

© National Instruments Corp.

3-7 NAT7210 Reference Manual

7210-Mode Interface Registers Chapter 3

Address Register (ADR)

Attributes: Write only

7

ARS

6

DT

5

DL

4

AD5

3

AD4

2

AD3

1

AD2

0

AD1

Writing to the Address Register (ADR) loads the internal registers ADR0 and ADR1.

You must load both ADR0 and ADR1 for all addressing modes. See the GPIB

Addressing section in Chapter 5, Software Considerations.

Bit

7w

Mnemonic

ARS

Description

Address Register Select bit

If ARS = 1, writing to the ADR loads the seven low-order bits of ADR into internal register ADR1. If ARS = 0, writing to the ADR loads the seven low-order bits into

ADR0.

6w DT Disable Talker bit

DT = 1 disables recognition of the GPIB talk address formed from AD[5–1]. ADR0 and ADR1 have independent DT bits.

5w DL Disable Listener bit

DL = 1 disables recognition of the GPIB listen address formed from AD[5–1]. ADR0 and ADR1 have independent DL bits.

4–0w AD[5–1] NAT7210 GPIB Address bits 5 through 1

These bits specify the GPIB address of the NAT7210.

The corresponding GPIB talk address is formed by adding hex 40 to AD[5–1], while the corresponding GPIB listen address is formed by adding hex 20 to AD[5–1]. The value written to AD[5–1] should not be 11111 (binary), because the corresponding talk and listen addresses would conflict with the GPIB Untalk (UNT) and GPIB Unlisten

(UNL) commands.

NAT7210 Reference Manual

ADR0 and ADR1 have independent AD[5–1] bits.

3-8 © National Instruments Corp.

Chapter 3 7210-Mode Interface Registers

Address Register 0 (ADR0)

Attributes: Read only

7

X

6

DT0

5

DL0

4 3 2 1 0

AD5–0 AD4–0 AD3–0 AD2–0 AD1–0

Address Register 0 (ADR0) reflects the internal GPIB address status of the NAT7210. In extended single addressing mode, ADR0 indicates the address and enable bits for the primary GPIB address of the NAT7210. In the dual primary addressing modes, ADR0 indicates the NAT7210 major primary GPIB address. See the GPIB Addressing section in Chapter 5, Software Considerations.

Bit

7r

Mnemonic

X

Description

Reads back a 1 or 0.

6r DT0 Disable Talker 0 bit

If DT0 = 1, the primary (or major) Talker function is not enabled, and ADR0 is not compared with GPIB Talker addresses.

If DT0 = 0, the NAT7210 responds to a GPIB talk address matching bits AD[5–0 through 1–0].

5r

4–0r

DL0 Disable Listener 0 bit

If DL0 = 1, the primary (or major) Listener function is not enabled, and ADR0 is not compared with GPIB Listener addresses.

If DL0 = 0, the NAT7210 responds to a GPIB listen address matching bits AD[5–0 through 1–0].

AD[5–0 – 1–0] NAT7210 GPIB Address bits 5–0 through 1–0

These are the lower 5 bits of the NAT7210 GPIB primary

(or major) address. The primary talk address is formed by adding hex 40 to AD[5–0 through 1–0], while the primary listen address is formed by adding hex 20.

© National Instruments Corp.

3-9 NAT7210 Reference Manual

7210-Mode Interface Registers Chapter 3

Address Register 1 (ADR1)

Attributes: Read only

7

EOI

6

DT1

5

DL1

4 3 2 1 0

AD5–1 AD4–1 AD3–1 AD2–1 AD1–1

Address Register 1 (ADR1) indicates the status of the GPIB address and enable bits for the secondary address of the NAT7210 if extended single addressing is used. ADR1 indicates the minor primary address of the NAT7210 if dual primary addressing is used.

See the GPIB Addressing section in Chapter 5, Software Considerations.

Bit

7r

Mnemonic

EOI

Description

End-or-Identify bit

EOI indicates the value of the GPIB EOI line that is latched when a data byte is received by the NAT7210

GPIB Acceptor Handshake (AH) function. If EOI = 1, the

EOI line was asserted with the received byte. EOI is cleared by issuing the Chip Reset auxiliary command.

EOI is updated after each byte is received.

6r

5r

DT1

DL1

Disable Talker 1 bit

If DT1 = 1, the secondary (or minor) Talker function is not enabled—that is, the GPIB secondary address (or minor primary talk address) is not compared with this register.

Disable Listener 1 bit

If DL1 = 1, the secondary (or minor) Listener function is not enabled—that is, the GPIB secondary address (or minor primary listen address) is not compared with this register.

4–0r AD[5–1 – 1–1]

NAT7210 Reference Manual

NAT7210 GPIB Address bits 5–1 through 1–1

These bits indicate the NAT7210 secondary or minor address. Form the secondary address by adding hex 60 to bits AD[5–1 through 1–1]. Form the minor talk address by adding hex 40 to AD[5–1 through 1–1]. Form the listen address by adding a hex 20.

3-10 © National Instruments Corp.

Chapter 3 7210-Mode Interface Registers

Address Status Register (ADSR)

Attributes: Read only

7

CIC

6 5 4

ATN* SPMS LPAS

3

TPAS

2

LA

1

TA

0

MJMN

The Address Status Register (ADSR) contains information that you can use to monitor the NAT7210 GPIB address status.

Bit

7r

Mnemonic

CIC

Description

Controller-In-Charge bit

CIC = ~(CIDS + CADS)

CIC indicates that the NAT7210 GPIB Controller function is either in an active state with ATN* asserted or a standby state with ATN* unasserted. The Controller function is in an idle state (CIDS or CADS) if CIC = 0.

6r

5r

ATN*

SPMS

Attention* bit

ATN* is a status bit that indicates the current level of the

GPIB ATN* signal. If ATN* = 0, the GPIB ATN* signal is asserted.

Serial Poll Mode State bit

If SPMS = 1, the NAT7210 GPIB Talker (T) or Talker

Extended (TE) function is enabled to participate in a serial poll.

SPMS is set by

SPE & ACDS

SPMS is cleared by

(SPD & ACDS) + pon + IFC

© National Instruments Corp.

3-11 NAT7210 Reference Manual

7210-Mode Interface Registers

ADSR (continued)

Bit

4r

Mnemonic

LPAS

Chapter 3

Description

Listener Primary Addressed State bit

LPAS indicates that the NAT7210 has received its primary listen address. See the Address Mode Register

(ADMR) section in this chapter.

LPAS is cleared by

(PCG & ~MLA & ACDS) + pon

3r TPAS

2r

1r

LA

TA

Talker Primary Addressed State bit

TPAS indicates that the NAT7210 has received its primary GPIB talk address. See the Address Mode

Register (ADMR) section in this chapter.

TPAS is cleared by

(PCG & ~MTA & ACDS) + pon

Listener Active bit

LA = 1 when the NAT7210 has been addressed or programmed as a GPIB Listener—that is, the NAT7210 is in the Listener Active State (LACS) or the Listener

Addressed State (LADS). The NAT7210 is addressed to listen when it receives its listen address from the CIC.

The NAT7210 can also be programmed to listen by using the Listen-Only (lon) bit in the ADMR.

If the NAT7210 is addressed to talk, it is automatically unaddressed to listen.

LA is also cleared by

(UNL & ACDS) + IFC + pon + (lun & CACS)

+ lul

Talker Active bit

TA = 1 when the NAT7210 has been addressed or programmed as the GPIB Talker—that is, the NAT7210 is in the Talker Active State (TACS), the Talker Addressed

NAT7210 Reference Manual 3-12 © National Instruments Corp.

Chapter 3

ADSR (continued)

Bit Mnemonic

0r MJMN

7210-Mode Interface Registers

Description

State (TADS), or the Serial Poll Active State (SPAS).

The NAT7210 can be addressed to talk when it receives its talk address from the CIC. It can also be programmed to talk by using the Talk-Only (ton) bit in the ADMR.

If the NAT7210 is addressed to listen, it is automatically unaddressed to talk.

TA is also cleared by

(OTA & ACDS) + IFC + pon + lut

Major-Minor bit

MJMN indicates whether the information in the other

ADSR bits applies to the NAT7210 major or minor Talker and Listener functions. MJMN = 1 when the NAT7210 receives its GPIB minor talk address or minor listen address. MJMN clears when the NAT7210 receives its major talk or major listen address. The pon message also clears MJMN.

Note: Only one Talker or Listener can be active at a time. The MJMN bit indicates which, if either, of the NAT7210 Talker and Listener functions is

addressed or active.

MJMN is always 0 unless the normal or extended dual primary addressing mode is enabled. See the Address

Mode Register (ADMR) section in this chapter.

© National Instruments Corp.

3-13 NAT7210 Reference Manual

7210-Mode Interface Registers Chapter 3

Auxiliary Mode Register (AUXMR)

Attributes: Write only

Permits access to hidden registers

7 6 5 4 3 2 1 0

AUX7 AUX6 AUX5 AUX4 AUX3 AUX2 AUX1 AUX0

Use the AUXMR to issue auxiliary commands and to write the following eight hidden registers:

• Parallel Poll Register (PPR)

• Auxiliary Register A (AUXRA)

• Auxiliary Register B (AUXRB)

• Auxiliary Register E (AUXRE)

• Auxiliary Register F (AUXRF)

• Auxiliary Register G (AUXRG)

• Auxiliary Register I (AUXRI)

• Internal Counter Register (ICR)

Note: You should issue commands at intervals of at least 4 clock periods.

For more information, see the Hidden Registers section, which is located earlier in this chapter.

NAT7210 Reference Manual 3-14 © National Instruments Corp.

Chapter 3 7210-Mode Interface Registers

AUXMR (continued)

Table 3-5 summarizes the AUXMR auxiliary commands and Table 3-6 describes the

AUXMR auxiliary commands.

Table 3-5. Auxiliary Command Summary

Hex

Code*

Auxiliary Command

00 Immediate Execute Power-On (pon)

01 Clear Parallel Poll Flag (~ist)

02 Chip Reset (chip_reset)

03 Finish Handshake (rhdf)

04 Trigger (trig)

05 Clear Or Pulse Return To Local (rtl)

06 Send EOI (seoi)

07 Nonvalid Secondary Command Or

Address (nonvalid)

08† Request Control Command (rqc)

09 Set Parallel Poll Flag (ist)

0A† Release Control Command (rlc)

0B† Untalk Command (lut)

0C† Unlisten Command (lul)

0D Set Return To Local

0E† New Byte Available False (nbaf)

0F Valid Secondary Command or Address

(valid)

10 Go To Standby (gts)

(continues)

© National Instruments Corp.

3-15 NAT7210 Reference Manual

7210-Mode Interface Registers

AUXMR (continued)

Table 3-5. Auxiliary Command Summary (Continued)

Hex

Code*

11

12

1A

Auxiliary Command

13

1B

1C

Take Control Asynchronously (tca)

Take Control Synchronously (tcs)

Take Control Synchronously On End (tcse)

Listen (ltn)

Listen In Continuous Mode (ltn and cont)

Local Unlisten (lun)

14 Disable System Control (~rsc)

15† Switch To 9914 Mode Command (sw9914)

16

1E

17

1F

18†

19†

Clear IFC (~sic & rsc)

Set IFC (sic & rsc)

Clear REN (~sre & rsc)

Set REN (sre & rsc)

Request rsv True (reqt)

Request rsv False (reqf)

1D Execute Parallel Poll (rppl)

50† Page-In Additional Registers (page-in)

51† Holdoff Handshake Immediately (hldi)

54† Clear DET (ISR1[5]r) Command

55† Clear END (ISR1[4]r) Command

56† Clear DEC (ISR1[3]r) Command

57† Clear ERR (ISR1[2]r) Command

58† Clear SRQI (ISR2[6]r) Command

59† Clear LOKC (ISR2[2]r) Command

5A† Clear REMC (ISR2[1]r) Command

(continues)

Chapter 3

NAT7210 Reference Manual 3-16 © National Instruments Corp.

Chapter 3 7210-Mode Interface Registers

AUXMR (continued)

Table 3-5. Auxiliary Command Summary (Continued)

Hex

Code*

Auxiliary Command

5B† Clear ADSC (ISR2[0]r) Command

5C† Clear IFCI (ISR0[3]r) Command

5D† Clear ATNI (ISR0[2]r) Command

5E†

5F†

Clear SYNC (ISR0[0]r) Command

Set SYNC (ISR0[0]r) Command

* Represents all eight bits of the AUXMR.

† Denotes an auxiliary command not available in the NEC

µ

PD7210.

© National Instruments Corp.

3-17 NAT7210 Reference Manual

7210-Mode Interface Registers Chapter 3

AUXMR (continued)

Table 3-6. Auxiliary Command Description

Data

Pattern

(Hex)

00

Description

Immediate Execute Power-On (pon)

The Immediate Execute Power-On auxiliary command sets the local pon message true, then clears it. If the local pon message is already asserted, the pon auxiliary command simply clears the local pon message. The following figure illustrates the behavior of the local pon message: start of pon aux.

command pulse local pon message true end of pon aux.

command pulse

01

09

HW reset + chip_reset aux. command

When the local pon message is true, the NAT7210 holds all GPIB interface functions in their idle states.

Clear Parallel Poll Flag (~ist)

Set Parallel Poll Flag (ist)

These commands set and clear the Parallel Poll Flag. The value of the Parallel Poll Flag is used as the local message ist when

AUXRB[4]w = 0. The value of SRQS is used as ist when ISS = 1.

A hardware reset or the Chip Reset auxiliary command clears ist.

(continues)

NAT7210 Reference Manual 3-18 © National Instruments Corp.

Chapter 3 7210-Mode Interface Registers

AUXMR (continued)

Table 3-6. Auxiliary Command Description (Continued)

Data

Pattern

(Hex)

02

03

Description

Chip Reset

The Chip Reset auxiliary command resets the NAT7210 to the following conditions:

• The local pon message is set and the interface functions are placed in their idle states.

• The SPMR bits are cleared.

• The TRM[1–0] bits are cleared.

• The EOI bit is cleared.

• The AUXRA, AUXRB, AUXRE, AUXRF, AUXRG, and

AUXRI registers are cleared.

• The Parallel Poll Flag is cleared.

• The BCR is cleared.

The interface functions remain in their idle states until they are released by an Immediate Execute pon command. While the interface functions are in their idle states, the host interface can program the NAT7210 writable bits to their desired states.

Finish Handshake (rhdf)

The Finish Handshake command finishes a GPIB handshake that was stopped because of a Holdoff On RFD condition.

See The GPIB rdy Message and RFD Holdoffs section in Chapter 5,

Software Considerations.

(continues)

© National Instruments Corp.

3-19 NAT7210 Reference Manual

7210-Mode Interface Registers Chapter 3

AUXMR (continued)

Table 3-6. Auxiliary Command Description (Continued)

Data

Pattern

(Hex)

04

05

0D

06

07

08*

0A*

Description

Trigger (trig)

The Trigger command generates a high pulse on the T/R 3 pin when

TRM1 = 0. The DET bit is not set by issuing the Trigger command.

Clear Or Pulse Return To Local (rtl)

Set Return To Local (rtl)

The two Return To Local commands implement the rtl message as defined by the IEEE 488 standard. If the host interface writes 05 hex, the rtl message is generated in the form of a pulse. If rtl is already set, the rtl command clears it. If the host interface writes 0D hex, the rtl command is set and remains set until either the 05 hex rtl command is issued or a Chip Reset auxiliary command is issued.

Send EOI (seoi)

The seoi command causes the GPIB End-or-Identify (EOI) line to go true with the next data byte transmitted. The EOI line is cleared upon completion of the handshake for that byte. When NTNL = 0, the

NAT7210 recognizes the seoi command only if TACS = 1—that is, the NAT7210 is in the Talker Active State.

Nonvalid Secondary Command Or Address (nonvalid)

The nonvalid command releases a DAC (Data Accepted) holdoff.

If APT = 1, the NAT7210 operates as if an Other Secondary Address

(OSA) message had been received.

Request Control Command (rqc)

If the NAT7210 is in the Idle Controller State, the rqc command forces the NAT7210 to become the Active Controller when it detects that the ATN signal is unasserted.

Release Control Command (rlc)

The rlc command forces the NAT7210 to become an Idle Controller and to unassert ATN.

(continues)

NAT7210 Reference Manual 3-20 © National Instruments Corp.

Chapter 3 7210-Mode Interface Registers

AUXMR (continued)

Table 3-6. Auxiliary Command Description (Continued)

Data

Pattern

(Hex)

0B*

0C*

0E*

0F

10

11

Description

Untalk (lut)

The lut command issues the local unt message, forcing the Talker function to enter TIDS.

Unlisten (lul)

The lul command issues the local unl message, forcing the Listener function to enter LIDS.

New Byte Available False (nbaf) nbaf forces the local message, nba, to become false. This action prohibits the NAT7210 from sending the last byte written to the

Command/Data Our Register (CDOR). See the Using nbaf section in Chapter 5, Software Considerations .

Valid Secondary Command Or Address (valid)

The valid command releases a DAC holdoff. If APT = 1, the

NAT7210 operates as if a My Secondary Address (MSA) message had been received.

Go To Standby (gts)

The gts command pulses the local gts message. If the NAT7210 is the Active Controller, gts causes the NAT7210 to become the

Standby Controller and to unassert the GPIB ATN signal. See the

Three Basic Controller States section in Chapter 6, Controller

Software Considerations.

Take Control Asynchronously (tca)

The tca command pulses the local tca message. If the NAT7210 is the Standby Controller, tca causes the NAT7210 to become the

Active Controller and to assert the GPIB ATN signal. See the

Standby State to Active State section in Chapter 6, Controller

Software Considerations.

(continues)

© National Instruments Corp.

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7210-Mode Interface Registers Chapter 3

AUXMR (continued)

Table 3-6. Auxiliary Command Description (Continued)

Data

Pattern

(Hex)

12

13

14

15*

16

Description

Take Control Synchronously (tcs)

The tcs command sets the local tcs message. If the NAT7210 is the

Standby Controller and an Active Listener, the tcs message causes the

NAT7210 to become the Active Controller when the NAT7210 performs an RFD holdoff—that is, the AH function enters ANRS.

The local tcs message clears when the NAT7210 becomes the Active

Controller by this method or if the NAT7210 becomes an Idle

Controller. See the Standby State to Active State section in Chapter 6,

Controller Software Considerations .

Listen (ltn)

The ltn command pulses the local ltn message. If the NAT7210 is the

Active Controller, the local ltn message causes the NAT7210 to become an Addressed Listener. The ltn command can also take the

NAT7210 out of the continuous data-receiving mode (see ltn & cont command).

Disable System Control (~rsc)

The ~rsc command, a hardware reset, or the Chip Reset auxiliary command clears the local rsc message. See the System Controller

Considerations section in Chapter 6, Controller Software

Considerations.

Switch To 9914A Mode (sw9914)

This command places the NAT7210 in 9914 compatibility mode.

Clear IFC (~sic & rsc)

The ~sic & rsc command clears the local sic message and sets the local rsc messages. This action causes the NAT7210 to become the

System Controller and to unassert the GPIB IFC signal. See the

System Controller Considerations section in Chapter 6, Controller

Software Considerations.

(continues)

NAT7210 Reference Manual 3-22 © National Instruments Corp.

Chapter 3 7210-Mode Interface Registers

AUXMR (continued)

Table 3-6. Auxiliary Command Description (Continued)

Data

Pattern

(Hex)

17

18*

19*

1A

Description

Clear REN (~sre & rsc)

The ~sre & rsc command clears the local sre message and sets the local rsc messages. This action causes the NAT7210 to become the

System Controller and to unassert the GPIB REN signal. See the

System Controller Considerations section in Chapter 6, Controller

Software Considerations.

Request rsv True (reqt)

Request rsv False (reqf)

The reqt and reqf commands are inputs to the IEEE 488.2 Service

Request Synchronization Circuitry. These commands set and clear the local rsv message.

If STBO IE = 1, the reqt and reqf commands are issued immediately.

If STBO IE = 0, the reqt and reqf commands are not issued immediately: they are issued on the write of the SPMR that follows the issuing of the reqt or reqf auxiliary command.

Take Control Synchronously On END (tcse)

The tcse command causes the local tcs message to set when the

NAT7210 accepts a byte satisfying the END condition (see the END

RX bit ISR1[4]). If the NAT7210 is the Standby Controller and an

Active Listener, the tcs message causes the NAT7210 to become the

Active Controller when the NAT7210 performs an RFD holdoff — that is, when the AH function enters ANRS. The local tcs message

(and the END detection circuitry) clears when the NAT7210 becomes the Active Controller by this method or if the NAT7210 becomes an

Idle Controller.

(continues)

© National Instruments Corp.

3-23 NAT7210 Reference Manual

7210-Mode Interface Registers Chapter 3

AUXMR (continued)

Table 3-6. Auxiliary Command Description (Continued)

Data

Pattern

(Hex)

1B

1C

1D

1E

Description

Listen In Continuous Mode (ltn & cont)

The ltn & cont command pulses the local ltn message. If the

NAT7210 is the Active Controller, the local ltn message causes the

NAT7210 to become an Addressed Listener.

The ltn & cont command also places the NAT7210 in continuous mode regardless of the settings of the AUXRA[1–0] bits (see The

GPIB rdy Message and RFD Holdoffs section in Chapter 5). If the NAT7210 enters continuous mode because of the ltn & cont command, it remains in continuous mode until the NAT7210 becomes unaddressed to Listen—that is, the L or LE function enters

LIDS—or until the control program issues the ltn command.

Local Unlisten (lun)

The lun command pulses the local lun message. If the NAT7210 is the Active Controller, the local lun message causes the NAT7210 to become an Unaddressed Listener—that is, the L or LE function enters

LIDS.

Execute Parallel Poll (rpp1)

The rpp1 command sets the local rpp message. If the NAT7210 is the Active Controller, the rpp message causes the NAT7210 to send the IDY message to all GPIB devices in the system and to conduct a parallel poll. (See the Conducting Parallel Polls section in

Chapter 6.) The rpp message clears when the NAT7210 completes a parallel poll or becomes an Idle Controller.

Set IFC (sic & rsc)

The sic & rsc command sets the local sic and rsc messages. The local message pon or the ~rsc auxiliary command also clears sic. This action causes the NAT7210 to become the System Controller and to assert the GPIB IFC signal. See the System Controller

Considerations section in Chapter 6, Controller Software

Considerations.

(continues)

NAT7210 Reference Manual 3-24 © National Instruments Corp.

Chapter 3 7210-Mode Interface Registers

AUXMR (continued)

Table 3-6. Auxiliary Command Description (Continued)

Data

Pattern

(Hex)

1F

50*

51*

54*

55*

56*

57*

Description

Set REN (sre & rsc)

The sre & rsc command sets the local sre and rsc messages. The local message pon or the ~rsc auxiliary command also clears sre.

This action causes the NAT7210 to become the System Controller and to assert the GPIB REN signal. See the System Controller

Considerations section in Chapter 6, Controller Software

Considerations.

Page-In Additional Registers (page-in)

The Page-In command causes the NAT7210 to enter the Page-In state. The Page-In state makes several registers accessible. See The

Page-In State section located at the beginning of this chapter.

Holdoff Handshake Immediately (hldi)

This command forces the Acceptor Handshake function to immediately perform an RFD holdoff. Issuing this command forces a transition into ANRS, where the handshake is held off until a finish handshake auxiliary command is issued.

Clear DET

This command clears the DET bit (ISR1[5]r). Use this command to clear the DET bit when SISB = 1.

Clear END

This command clears the END bit (ISR1[4]r). Use this command to clear the END bit when SISB = 1.

Clear DEC

This command clears the DEC bit (ISR1[3]r). Use this command to clear the DEC bit when SISB = 1.

Clear ERR

This command clears the ERR bit (ISR1[2]r). Use this command to clear the ERR bit when SISB = 1.

© National Instruments Corp.

3-25

(continues)

NAT7210 Reference Manual

7210-Mode Interface Registers Chapter 3

AUXMR (continued)

Table 3-6. Auxiliary Command Description (Continued)

Data

Pattern

(Hex)

58*

Description

59*

5A*

Clear SRQI Command

This command clears the SRQI bit if SISB = 1. See the SRQI bit description that is in the Interrupt Status Register 2 (ISR2) section in this chapter.

Clear LOKC

This command clears the LOKC bit (ISR2[2]r). Use this command to clear the LOKC bit when SISB = 1.

Clear REMC

This command clears the REMC bit (ISR2[1]r). Use this command to clear the REMC bit when SISB = 1.

5B*

5C*

Clear ADSC

This command clears the ADSC bit (ISR2[0]r). Use this command to clear the ADCS bit when SISB = 1.

Clear IFCI

This command clears the IFCI bit (ISR0[3]r). Use this command to clear the IFCI bit when SISB = 1.

5D* Clear ATNI

This command clears the ATNI bit (ISR0[2]r). Use this command to clear the ATNI bit when SISB = 1.

5E*

5F*

Clear SYNC

Set SYNC

These commands start or reset the SYNC function.

* Denotes an auxiliary command not available in the

µ

PD7210.

NAT7210 Reference Manual 3-26 © National Instruments Corp.

Chapter 3 7210-Mode Interface Registers

Auxiliary Register A (AUXRA)

Attributes: Write only

Accessed at the same offset as AUXMR

7

1

6

0

5

0

4

BIN

3 2 1 0

XEOS REOS HLDE HLDA

AUXRA controls the End-of-String (EOS) and END messages and specifies the RFD holdoff mode. The Chip Reset auxiliary command or a hardware reset clears AUXRA.

You write to AUXRA at the same offset as the AUXMR.

Bit

4w

Mnemonic

BIN

Description

Binary bit

The BIN bit selects the length of the EOS message. If

BIN = 1, the End-of-String Register (EOSR) is treated as an 8-bit byte. When BIN = 0, the EOSR is treated as a

7-bit register (for ASCII characters), and only a 7-bit comparison is done with the data on the GPIB.

3w XEOS Transmit END With EOS bit

XEOS permits or prohibits automatic transmission of the

GPIB END message at the same time as the EOS message when the NAT7210 is in TACS. If XEOS = 1 and the byte in the CDOR matches the contents of the EOSR, the

EOI line is sent true along with the data.

2w REOS END On EOS Received bit

The REOS bit permits or prohibits setting the END bit

(ISR1[4]r) when the NAT7210 receives the EOS message as a Listener. If REOS = 1 and the byte in the DIR matches the byte in the EOSR, the END RX bit

(ISR1[4]r) is set and the acceptor function treats the EOS character just as if it were received with EOI asserted.

© National Instruments Corp.

3-27 NAT7210 Reference Manual

7210-Mode Interface Registers Chapter 3

AUXRA (continued)

Bit Mnemonic

1w, 0w HLDE

HLDA

Description

Holdoff On End bit

Holdoff On All Data bit

HLDE and HLDA together determine the GPIB data-receiving mode.

HLDE HLDA

0 0

0

1

1

1

0

1

Data-Receiving Mode

Normal Handshake Mode

RFD Holdoff on All Data Mode

RFD Holdoff on END Mode

Continuous Mode

For more information, see The GPIB rdy Message and

RFD Holdoffs section in Chapter 5, Software

Considerations.

Issuing the ltn & cont auxiliary command can also place the NAT7210 in the continuous data-receiving mode.

The NAT7210 enters continuous mode regardless of the value of HLDE and HLDA. In this situation, the

NAT7210 remains in continuous mode until you issue the ltn auxiliary command or the NAT7210 becomes unaddressed to listen (by entering the LIDS).

NAT7210 Reference Manual 3-28 © National Instruments Corp.

Chapter 3 7210-Mode Interface Registers

Auxiliary Register B (AUXRB)

Attributes: Write only

Accessed at the same offset as AUXMR

7

1

6

0

5

1

4

ISS

3

INV

2

TRI

1 0

SPEOI CPT

ENABLE

AUXRB affects several interface functions. The Chip Reset auxiliary command or a hardware reset clears AUXRB. You write to AUXRB at the same offset as the AUXMR.

Bit

4w

Mnemonic

ISS

Description

Individual Status Select bit

ISS determines the value of the NAT7210 ist message.

When ISS = 1, ist takes on the value of the NAT7210

Service Request State (SRQS). (The NAT7210 asserts the GPIB SRQ message when it is in SRQS.) If ISS = 0, ist takes on the value of the NAT7210 Parallel Poll Flag.

You set and clear the Parallel Poll Flag by using the Set

Parallel Poll Flag and Clear Parallel Poll Flag auxiliary commands. See the Parallel Polling section in

Appendix B, Introduction to the GPIB.

3w INV Invert bit

INV determines the polarity of the INT pin.

INV Bit

0

1

INT Pin Polarity

Active High

Active Low

2w TRI

© National Instruments Corp.

Three-State Timing bit

TRI determines the NAT7210 GPIB Source Handshake

Timing (T1). Clearing TRI sets the low-speed timing

(T1

≥

2

µ s). Setting TRI enables the NAT7210 to use a shorter T1 delay. See the T1 Delay Generation section in

Chapter 5, Software Considerations.

3-29 NAT7210 Reference Manual

7210-Mode Interface Registers Chapter 3

AUXRB (continued)

Bit

1w

Mnemonic

SPEOI

Description

Send Serial Poll EOI bit

SPEOI determines whether the NAT7210 sends EOI when a Controller serial polls the NAT7210.

SPEOI EOI During Serial Polls

0 Sent False

1 Sent True

0w CPT ENABLE Command Pass Through Enable bit

The CPT ENABLE bit permits or prohibits detecting undefined GPIB commands and permits or prohibits setting the CPT bit (ISR1[7]r).

NAT7210 Reference Manual 3-30 © National Instruments Corp.

1w

0w

Chapter 3 7210-Mode Interface Registers

Auxiliary Register E (AUXRE)

Attributes: Write only

Accessed at the same offset as AUXMR

7

1

6

1

5

0

4

0

3 2 1 0

DHADT DHADC DHDT DHDC

AUXRE determines when the NAT7210 performs a DAC holdoff. The Chip Reset auxiliary command or a hardware reset clears AUXRE.

Each bit of AUXRE enables DAC holdoffs on a GPIB command or group of commands.

When a GPIB Controller sends the specified command to the NAT7210, the CPT bit sets and the NAT7210 performs a DAC holdoff. See the DAC Holdoffs section in Chapter 5,

Software Considerations.

Bit

3w

Mnemonic

DHADT

Description

DAC Holdoff On GET Command bit

2w DHADC DAC Holdoff On DCL Or SDC Command bit

DHDT

DHDC

DAC Holdoff On DTAS Command bit

DAC Holdoff On DCAS Command bit

© National Instruments Corp.

3-31 NAT7210 Reference Manual

1w

0w

7210-Mode Interface Registers Chapter 3

Auxiliary Register F (AUXRF)

Attributes: Write only

Accessed at the same offset as AUXMR

7

1

6

1

5

0

4

1

3 2 1 0

DHATA DHALA DHUNTL DHALL

AUXRF determines how the NAT7210 uses a DAC holdoff. The Chip Reset auxiliary command or a hardware reset clears AUXRF.

Each bit of AUXRF enables DAC holdoffs on a GPIB command or group of commands.

When a GPIB Controller sends the specified command to the NAT7210, the CPT bit sets and the NAT7210 performs a DAC holdoff. See the DAC Holdoffs section in Chapter 5,

Software Considerations.

Bit

3w

Mnemonic

DHATA

Description

DAC Holdoff On All Talker Addresses Command bit

2w DHALA DAC Holdoff On All Listener Addresses Command bit

DHUNTL

DHALL

DAC Holdoff On The UNT Or UNL Command bit

DAC Holdoff On All UCG, ACG, And SCG Commands bit

NAT7210 Reference Manual 3-32 © National Instruments Corp.

Chapter 3 7210-Mode Interface Registers

Auxiliary Register G (AUXRG)

Attributes: Write only

Accessed at the same offset as AUXMR

7

0

6

1

5

0

4

0

3 2 1 0

NTNL RPP2 DISTCT CHES

Bit

3w

Mnemonic

NTNL

Description

No Talking When No Listener bit

Set NTNL to prevent the NAT7210 from sourcing data

(talking) when there is no external Listener, to modify the setting of the ERR bit, to modify the way the nba local message is cleared, and to change the EOI generation function. If the NAT7210 is used in an IEEE 488.2

device, you should set NTNL.

If NTNL = 0, the following actions occur:

• The NAT7210 handshake function enters STRS after the T1 delay has elapsed and NRFD is unasserted.

• The ERR bit is set on TACS & SDYS & DAC &

RFD or SIDS & (write CDOR) or the transition from

SDYS to SIDS.

• The local nba message is cleared upon entering SIDS or STRS.

• The Send EOI auxiliary command is ignored or forgotten upon exiting TACS.

If NTNL = 1, the following actions occur:

• The NAT7210 handshake function does not make the transition from SDYS to STRS unless an external

Listener exists—that is, a device on the GPIB is asserting NDAC.

• The ERR bit is set when the T1 delay has elapsed and

TACS & SDYS & EXTDAC & RFD (where

EXTDAC refers to some device on the GPIB asserting NDAC).

© National Instruments Corp.

3-33 NAT7210 Reference Manual

7210-Mode Interface Registers Chapter 3

AUXRG (continued)

Bit Mnemonic Description

• The local nba message is cleared upon entering STRS and ~SPAS.

• The Send EOI auxiliary command is cleared upon entering SDYS or STRS.

2w RPP2 Request Parallel Poll 2 bit

If RPP2 = 1, the local rpp message is true. Clearing RPP2 clears rpp. If the NAT7210 is the Active Controller, setting rpp causes the NAT7210 to conduct a parallel poll.

See the Conducting Parallel Polls section in Chapter 6,

Controller Software Considerations.

1w

0w

DISTCT

CHES

Disable Automatic Take Control bit

If DISTCT = 1, the NAT7210 considers the GPIB TCT message undefined. If the GPIB Controller tries to pass control to the NAT7210, the NAT7210 will not become a

Controller. You usually set DISTCT if the NAT7210 is a talk-only or listen-only device.

If DISTCT = 0, the NAT7210 recognizes TCT. Another

Controller may pass control to the NAT7210 without software intervention.

Clear Holdoff On End Select bit

CHES determines how long the NAT7210 remembers that it detected an END condition.

If CHES = 0, the NAT7210 remembers the detection of the END condition until the host interface issues the

Release Handshake Holdoff auxiliary command.

If CHES = 1, the NAT7210 remembers the detection of the END condition until the Release Handshake Holdoff auxiliary command is issued or the DIR is read when the

NAT7210 is in the normal handshake holdoff mode—that is, HLDE and HLDA = 0.

NAT7210 Reference Manual 3-34 © National Instruments Corp.

Chapter 3 7210-Mode Interface Registers

Auxiliary Register I (AUXRI)

Attributes: Write only

Accessed at the same offset as AUXMR

Bit

3w

7

1

6

1

Mnemonic

USTD

5

1

4

0

3

USTD

2

PP2

1

0

0

SISB

Description

Ultra Short T1 Delay bit

USTD sets the value of the T1 delay (used by the Source

Handshake function for data setup) to 350 ns for the second and subsequent data bytes sent after ATN unasserts. If USTD = 0, the TRI bit (AUXRB[2]w) determines the value of T1. See the T1 Delay Generation section in Chapter 5, Software Considerations.

2w PP2

0w SISB

Parallel Poll bit 2

If PP2 = 0, the NAT7210 responds to parallel polls in the same manner as the

µ

PD7210—that is, it supports Parallel

Poll functions PP1 and PP2 simultaneously. However, a contradiction arises because PP1 requires the interface to be configured by remote GPIB commands, and PP2 requires the interface to be configured locally and ignore remote GPIB commands.

When PP2 = 1, the chip ignores remote GPIB commands—that is, PPC and PPU are treated as undefined commands, allowing a true implementation of

PP2. In addition, setting PP2 and U (PPR[4]w) lets the

NAT7210 support PP0 (no Parallel Poll response). See the Parallel Polling section in Appendix B.

Static Interrupt Status Bits bit

If SISB = 0, reading ISR0, ISR1, or ISR2 clears the bits of the register that is read (ISR0, ISR1, or ISR2).

© National Instruments Corp.

3-35 NAT7210 Reference Manual

7210-Mode Interface Registers Chapter 3

AUXRI (continued)

If SISB = 1, the bits remain set until a certain condition is met. Table 3-7 lists the condition that clears each interrupt status bit when SISB = 1.

Table 3-7. Clear Conditions for SISB Bit

CO

CPT

DEC

DET

Bit

ADSC

APT

ATNI

Clear Condition when SISB = 1 pon + clearADSC + ton + lon pon + valid + nonvalid pon + clearATNI pon + ~CACS + ~SGNS + nba pon + read CPTR pon + clearDEC pon + clearDET

DI

DO

END

ERR pon + (finish handshake) * (Holdoff mode) + read DIR pon + ~TACS + ~SGNS + nba pon + clearEND pon + clearERR

IFCI pon + clearIFCI

LOKC pon + clearLOKC

REMC pon + clearREMC

SRQI pon + clearSRQI

Note: Interrupt Status bits STBO and SYNC are not affected by the SISB bit.

NAT7210 Reference Manual 3-36 © National Instruments Corp.

Chapter 3 7210-Mode Interface Registers

Bit

7r

7w

Bus Control Register (BCR)/Bus Status Register (BSR)

Attributes: Write only (BCR)

Read only (BSR)

7

ATN

ATN

6 5 4

DAV NDAC NRFD

DAV NDAC NRFD

3

EOI

EOI

2

SRQ

SRQ

1

IFC

IFC

Mnemonic

ATN

ATN

Description

GPIB Attention Status bit

GPIB Attention Control bit

0

REN

REN

4r

4w

3r

3w

6r

6w

5r

5w

DAV

DAV

NDAC

NDAC

NRFD

NRFD

EOI

EOI

GPIB Data Valid Status bit

GPIB Data Valid Control bit

GPIB Not Data Accepted Status bit

GPIB Not Data Accepted Control bit

GPIB Not Ready For Data Status bit

GPIB Not Ready For Data Control bit

GPIB End-or-Identify Status bit

GPIB End-or-Identify Control bit

2r

2w

1r

1w

SRQ

SRQ

IFC

IFC

GPIB Service Request Status bit

GPIB Service Request Control bit

GPIB Interface Clear Status bit

GPIB Interface Clear Control bit

0r

0w

REN

REN

GPIB Remote Enable Status bit

GPIB Remote Enable Control bit

Reads of the Bus Status Register (BSR) return the status of the GPIB control lines at the time of the read. Write ones to bits in the Bus Control Register (BCR) to assert the corresponding GPIB control lines.

© National Instruments Corp.

3-37 NAT7210 Reference Manual

7210-Mode Interface Registers Chapter 3

BCR/BSR (continued)

Because the NAT7210 is either transmitting or receiving a GPIB control line at any particular time and is not performing both actions simultaneously, setting a bit in the

BCR may not automatically assert the corresponding line on the GPIB. If the NAT7210 is transmitting a GPIB line when the corresponding bit in the BCR is set, the NAT7210 asserts the GPIB line. If the NAT7210 is receiving a GPIB line when the corresponding bit in the BCR is set, the GPIB line is not asserted. However, in both these cases, the

GPIB signal internal to the NAT7210 is logically ORed with the value of the BCR bit.

Figure 3-1 illustrates the GPIB input/output hardware configuration.

Transmit Enable

GPIB Line Out

BCR Bit

PIN

NDAC

NRFD

SRQ

GPIB Line In eliminates glitches in

REN & IFC

Figure 3-1. GPIB I/O Hardware Configuration

In Figure 3-1, Transmit Enable represents the internal signal that is true when the chip is driving a particular GPIB control line. GPIB Line Out represents the internal signal that is true when an interface function within the chip is attempting to assert a GPIB control signal. BCR Bit corresponds to the bit in the BCR. GPIB Line In represents the internal

GPIB lines that are inputs to the GPIB interface functions and the BSR. The internal signals SRQ , NDAC, and NRFD are monitored by the interface functions even when they are not driven onto the pin. For this reason, the internal value of these signals is ORed with the external value.

Because the BSR samples the GPIB control lines from the GPIB transceiver—not the actual GPIB bus—the direction of each line determines the validity of each bit.

Generally, when a signal is an input, the BSR reflects its true bus status, while an output signal reflects only the NAT7210 value of that particular line. Under normal GPIB operation, this restriction on the validity of the BSR should not be too limiting, because the lines that are typically monitored are valid when they are monitored. For example, the SRQ line is valid in the BSR when the NAT7210 is CIC, which is also when the SRQ line will be monitored.

NAT7210 Reference Manual 3-38 © National Instruments Corp.

Chapter 3 7210-Mode Interface Registers

Command/Data Out Register (CDOR)

Attributes: Write only

Bit

7–0w

7

DIO8

6

DIO7

Mnemonic

DIO[8–1]

5

DIO6

4

DIO5

3

DIO4

2

DIO3

1

DIO2

0

DIO1

Description

GPIB data lines DIO[8–1]

The CDOR moves data from the CPU to the GPIB when the interface is the GPIB Talker or Controller. Writing to the CDOR sets the local message, nba. When nba is true, the Source Handshake (SH) function can transfer the data or command in the CDOR to other GPIB devices.

Writing to the CDOR also

• Clears the Data Out (DO) bit.

• Clears the DRQ signal (unless DMAO = 0).

The host interface can write to the CDOR at offset 0 or by performing a DMA write operation.

The CDOR and the DIR use separate latches. A read of the DIR does not change data in the CDOR. The CDOR is a transparent latch; thus, the GPIB data bus (DIO(8–1)) reflects changes on the CPU data bus during write cycles to the CDOR.

© National Instruments Corp.

3-39 NAT7210 Reference Manual

7210-Mode Interface Registers Chapter 3

Command Pass Through Register (CPTR)

Attributes: Read only

7 6

CPT7 CPT6

5 4

CPT5 CPT4

3

CPT3

2 1

CPT2 CPT1

0

CPT0

The host interface can examine the GPIB DIO lines by reading the Command Pass

Through Register (CPTR). The CPTR has no storage; the host interface should read the

CPTR only during a DAC holdoff. See the DAC Holdoffs section in Chapter 5, Software

Considerations.

Bit

7–0r

Mnemonic

CPT[7–0]

Description

Command Pass Through bits 7 through 0

NAT7210 Reference Manual 3-40 © National Instruments Corp.

Chapter 3 7210-Mode Interface Registers

Data In Register (DIR)

Attributes: Read only

7

DIO8

6

DIO7

5

DIO6

Bit

7–0r

Mnemonic

DIO[8–1]

4

DIO5

3

DI04

2

DIO3

1

DIO2

0

DIO1

Description

GPIB data lines DIO[8–1]

The Data In Register (DIR) holds data that the NAT7210 receives when the NAT7210 is a Listener. The NAT7210 latches GPIB data into the DIR when LACS & ACDS is true.

Latching data into the DIR causes the DI bit (ISR1[0]) to set, unless the NAT7210 is in continuous mode (see

AUXMR[1:0]). Usually, latching data into the DIR causes an RFD holdoff (see The GPIB rdy Message and

RFD Holdoffs section in Chapter 5, Software

Considerations).

The host interface can read the DIR at offset 0 or by asserting the DACK* and RD* pins. Reading the DIR also

• Clears DI (ISR1[0]).

• Clears the DRQ signal if DMAI (IMR2[4]) is set.

• Clears an RFD holdoff (depending on several other conditions).

The DIR and the CDOR use separate latches. When the host interface writes to the CDOR, data in the DIR is not changed.

© National Instruments Corp.

3-41 NAT7210 Reference Manual

7210-Mode Interface Registers Chapter 3

End-of-String Register (EOSR)

Attributes: Write only

7

EOS7

6

EOS6

5

EOS5

4

EOS4

3

EOS3

2

EOS2

1

EOS1

0

EOS0

EOSR holds the byte that the NAT7210 uses to detect the end of a GPIB data block transfer. The NAT7210 compares data it receives to a 7- or 8-bit byte (ASCII or binary—depending on the BIN bit) in the EOSR in order to detect the end of a block of data.

If the NAT7210 is a Listener and REOS = 1, the END bit is set in ISR1 whenever the received data byte matches the EOSR. If the NAT7210 is a Talker and XEOS = 1, the

END message (GPIB EOI* line asserted low) is sent along with a data byte whenever the data byte matches the EOSR.

Bit

7–0w

Mnemonic

EOS[7–0]

Description

End-of-String bits 7 through 0

NAT7210 Reference Manual 3-42 © National Instruments Corp.

Chapter 3 7210-Mode Interface Registers

Internal Count Register (ICR)

Attributes: Write only

7

0

6

0

5

1

4

0

3

F3

2

F2

1

F1

0

F0

ICR determines the internal clock frequency of the NAT7210. You write to the ICR at the same offset as the AUXMR.

Note: The ICR resets to 00101000 (8 MHz).

Bit Mnemonic Description

3–0 F(3–0) Clock Frequency

These bits, in addition to MICR (ICR2[0]), determine the length of certain delays that are required by the

IEEE 488 standard. You should set these bits according to the frequency of the signal driving the CLK pin. For proper operation, set F(3–0) and MICR as follows:

Clock

Frequency

1

2

5

6

3

4

10

16

7

8

20

MICR

0

0

0

0

0

0

0

0

1

1

1

F(3–0)

0101

0110

0111

1000

0001

0010

0011

0100

0101

1000

1010

© National Instruments Corp.

3-43 NAT7210 Reference Manual

7210-Mode Interface Registers Chapter 3

Internal Count Register 2 (ICR2)

Attributes: Write only

Bit

5w

7

1

6

0

Mnemonic

SLOW

5

SLOW

4

0

3

0

2

0

1

0

0

MICR

Description

Slow Handshake bit

Setting this bit enables circuitry that increases the time

NRFD* or NDAC* must be unasserted before the

NAT7210 responds to the unassertion.

If SLOW = 1, NRFD* and NDAC* must be unasserted for at least 400 ns before the NAT7210 responds to the unassertion.

0w MICR Modify Internal Count Register

Setting this bit modifies the meaning of the bits in the

Internal Count Register. For more details, see the Internal

Count Register (ICR) section in this chapter.

NAT7210 Reference Manual 3-44 © National Instruments Corp.

Chapter 3 7210-Mode Interface Registers

Interrupt Mask Register 0 (IMR0)

Attributes: Write only

7 6

GLINT STBO

IE

5

NLEN

4

0

3 2

IFCI IE ATNI

IE

1

0

0

SYNC

IE

Interrupt Status Register 0 (ISR0)

Attributes: Read only

7 nba

6

STBO

5

NL

4

EOS

3

IFCI

2

ATNI

1

X

0

SYNC

Interrupt Status Register 0 (ISR0) contains Interrupt Status bits and Internal Status bits.

Interrupt Mask Register 0 (IMR0) contains Interrupt Enable bits and Internal Control bits.

If an Interrupt Enable is true when the corresponding status condition or event occurs, the

NAT7210 can generate a hardware interrupt request. See the Generating Hardware

Interrupts section in Chapter 5, Software Considerations .

Bits in ISR0 are set and cleared regardless of the status of bits in IMR0. If an interrupt condition occurs at the same time the host interface is reading ISR0, the NAT7210 does not set the corresponding Interrupt Status bit until the read is finished. A hardware reset clears all bits in IMR0 except GLINT, which is set.

Bit

7r

Mnemonic nba

Description

New Byte Available local message bit nba reflects the status of the local New Byte Available message.

nba is set on writes to the CDOR. nba is cleared by pon + nbaf + (NTNL & SIDS) + STRS

7w GLINT

© National Instruments Corp.

Global Interrupt Enable bit

GLINT enables the NAT7210 to assert the INT pin. If

GLINT = 0, the INT pin does not assert. See the

Generating Hardware Interrupts section in Chapter 5,

Software Considerations.

3-45 NAT7210 Reference Manual

7210-Mode Interface Registers Chapter 3

IMR0/ISR0 (continued)

Bit

6r

6w

Mnemonic

STBO

STBO IE

Description

Status Byte Out bit

Status Byte Out Interrupt Enable bit

STBO IE determines how the NAT7210 requests service and responds to serial polls. See the Serial Polling section in Appendix B, Introduction to the GPIB.

If STBO IE = 0, the rsv bit in SPMR can be used to request service. When the GPIB Controller serial polls the NAT7210, the NAT7210 transmits the current value of SPMR.

If STBO IE = 1, the rsv bit in the SPMR has no effect on the Service Request (SR1) function and rsv must be generated through the reqt auxiliary command. STBO sets when the GPIB Controller serial polls the NAT7210.

In response to STBO, the host interface writes a byte to

SPMR, then the NAT7210 transmits this byte as the Serial

Poll response.

STBO is set by

STBO IE & SPAS

STBO is cleared by pon + (write SPMR) + ~SPAS

5r NL New Line Receive bit

NL is set when the NAT7210 accepts the ASCII new line character from the GPIB data bus.

NL is set by

LACS & NL & ACDS

NL is cleared by pon + (LACS & ~NL & ACDS)

NAT7210 Reference Manual 3-46 © National Instruments Corp.

Chapter 3 7210-Mode Interface Registers

IMR0/ISR0 (continued)

Bit

5w

Mnemonic

NLEN

Description

New Line End Enable bit

If NLEN = 1, the NAT7210 treats the 7-bit ASCII new line character (0A hex) as an EOS character. The

Acceptor Handshake function responds to the acceptance of a new line character in the same manner as if EOI were sent.

4r EOS

3r

3w

IFCI

IFCI IE

End-of-String bit

The EOS bit indicates that the END bit in ISR1 was set by the acceptance of the End-of-String character.

EOS is set by

LACS & EOS & REOS & ACDS

EOS is cleared by pon + (LACS & ~EOS & ACDS) + ~REOS

IFC Interrupt bit

IFC Interrupt Enable bit

IFCI is set on the assertion of the GPIB IFC* line.

IFCI is cleared by pon + (read ISR0) & ~SISB + clearIFCI

2r

2w

1r

ATNI

ATNI IE

X

ATN Interrupt bit

ATN Interrupt Enable bit

ATNI is set on the assertion of the ATN* line.

ATNI is cleared by pon + (read ISR0) & ~SISB + clearATNI

Don’t care bit

© National Instruments Corp.

3-47 NAT7210 Reference Manual

7210-Mode Interface Registers Chapter 3

IMR0/ISR0 (continued)

Bit

0r

0w

Mnemonic

SYNC

SYNC IE

Description

GPIB Synchronization bit

GPIB Synchronization Interrupt Enable bit

SYNC reflects the status of GPIB handshake lines after a transfer. SYNC is set at the completion of a transfer when the GPIB handshake is complete. An interrupt is generated when SYNC IE and SYNC are set.

NAT7210 Reference Manual 3-48 © National Instruments Corp.

Chapter 3 7210-Mode Interface Registers

Interrupt Mask Register 1 (IMR1)

Attributes: Write only

7 6 5 4 3 2 1 0

CPT IE APT IE DET IE END IE DEC IE ERR IE DO IE DI IE

Interrupt Status Register 1 (ISR1)

Attributes: Read only

Bits are cleared when read if SISB = 0

7

CPT

6

APT

5 4 3

DET END RX DEC

2

ERR

1

DO

0

DI

Bit

7r

7w

Interrupt Status Register 1 (ISR1) contains eight Interrupt Status bits. Interrupt Mask

Register 1 (IMR1) contains eight Interrupt Enable bits that directly correspond to the

Interrupt Status bits in ISR1. As a result, ISR1 and IMR1 service eight possible interrupt conditions; each condition has an associated Interrupt Status bit and an Interrupt Enable bit. If an Interrupt Enable bit is true when the corresponding status condition or event occurs, the NAT7210 can generate a hardware interrupt request. See the Generating

Hardware Interrupts section in Chapter 5, Software Considerations .

Bits in ISR1 are set and cleared regardless of the status of the Interrupt bits in IMR1.

If an interrupt condition occurs at the same time the host interface is reading ISR1, the

NAT7210 does not set the corresponding Interrupt Status bit until the read is finished.

A hardware reset clears all bits in IMR1.

Mnemonic

CPT

CPT IE

Description

Command Pass Through bit

Command Pass Through Interrupt Enable bit

© National Instruments Corp.

The CPT bit can flag the occurrence of two types of GPIB commands: undefined commands and user-specified commands.

When CPT ENAB = 1, the CPT bit flags the occurrence of undefined commands and all following secondary commands. The CPT bit flags undefined Address

Command Group (ACG) commands only when the

NAT7210 is an addressed Talker or Listener. The host interface can read the CPTR to determine the command the NAT7210 received.

3-49 NAT7210 Reference Manual

7210-Mode Interface Registers Chapter 3

IMR1/ISR1 (continued)

Bit Mnemonic Description

The CPT bit also flags the occurrence of commands that you specify when you set the AUXRE[3–0] or

AUXRF[3–0] bits.

When the CPT bit flags a command, the NAT7210 remains in a DAC Holdoff state until the host interface writes the valid or invalid auxiliary command to the

AUXMR.

CPT is set by

[UCG + ACG & (TADS + LADS)] & undefined

& ACDS & CPT ENABLE

+ UDPCF & SCG & ACDS & CPT ENABLE

+ DHADT & GET & ACDS

+ DHADC & (SDC + DCL) & ACDS

+ DHATA & TAG & ~UNT & ACDS

+ DHALA & LAG & ~UNL & ACDS

+ DHUNTL & (UNT + UNL) & ACDS

+ DHALL & ATN & ACDS

CPT is cleared by pon + (read ISR1) & ~SISB + (read CPTR) &

SISB

UDPCF is set by

[UCG + ACG & (TADS + LADS)] & undefined

& ACDS & CPT ENAB

UDPCF is cleared by

[(UCG + ACG) & defined + TAG + LAG] &

ACDS + ~(CPT ENAB) + pon

6r

6w

APT

APT IE

Address Pass Through bit

Address Pass Through Interrupt Enable bit

APT indicates that the NAT7210 has received a secondary

GPIB address. The host interface can read the secondary

GPIB address in the CPTR.

Note: If the application program uses extended dual addressing, it must check this bit.

NAT7210 Reference Manual 3-50 © National Instruments Corp.

Chapter 3 7210-Mode Interface Registers

IMR1/ISR1 (continued)

Bit Mnemonic Description

When APT sets, the NAT7210 enters the DAC Holdoff state. When the host interface writes the valid or invalid auxiliary command to the AUXMR, the NAT7210 exits the DAC Holdoff state.

APT is set by

ADM1 & ADM0 & (TPAS + LPAS) & SCG &

ACDS

APT is cleared by pon + (read ISR1) & ~SISB

+ (valid + nonvalid) & SISB

5r

5w

DET

DET IE

Device Execute Trigger bit

Device Execute Trigger Interrupt Enable bit

DET indicates that the NAT7210 received the GPIB

Group Execute Trigger (GET) command while the

NAT7210 was a GPIB Listener.

DET is set by

DTAS = GET & LADS & ACDS

DET is cleared by pon + (read ISR1) & ~SISB + clearDET

4r

4w

END RX

END IE

© National Instruments Corp.

End Received bit

End Received Interrupt Enable bit

END RX sets when the NAT7210, as a Listener, receives a data byte satisfying the END condition. A data byte satisfies the END condition if one of the following conditions is true:

• REOS = 1 and the data byte matches the contents of the EOSR.

• NLEN = 1 and the data byte matches the ASCII new line character (hex 0A).

• The GPIB EOI signal is asserted when the byte is received.

3-51 NAT7210 Reference Manual

7210-Mode Interface Registers Chapter 3

IMR1/ISR1 (continued)

Bit Mnemonic Description

END RX is set by

(EOI + EOS & REOS + NL & NLEN) & ACDS

& LACS

END RX is cleared by pon + (read ISR1) & ~SISB + clearEND

3r

3w

2r

2w

DEC

DEC IE

ERR

ERR IE

Device Clear bit

Device Clear Interrupt Enable bit

DEC indicates that either the NAT7210 received the

GPIB Device Clear (DCL) command or that the

NAT7210 was a GPIB Listener and received the GPIB

Selected Device Clear (SDC) command.

DEC is set by

DCAS = (SDC & LADS + DCL) & ACDS

DEC is cleared by pon + (read ISR1) & ~SISB + clearDEC

Error bit

Error Interrupt Enable bit

The definition of ERR depends on NTNL. When

NTNL = 0, ERR indicates that the contents of the CDOR have been lost. ERR sets when the NAT7210 sends data over the GPIB while no Listener exists on the GPIB.

ERR also sets when a byte is written to the CDOR during

SIDS or when a transition from SDYS to SIDS occurs.

When NTNL = 1, ERR indicates that the source handshake has attempted to send data or commands across the bus but has found no Listeners (that is, NDAC and

NRFD were unasserted). Data is not lost. The SH function does not source the data or command until a

Listener appears (that is, NDAC asserts).

NAT7210 Reference Manual 3-52 © National Instruments Corp.

Chapter 3 7210-Mode Interface Registers

IMR1/ISR1 (continued)

Bit Mnemonic Description

ERR is set by

~NTNL & TACS & SDYS & DAC & RFD

+ ~NTNL & SIDS & (write CDOR)

+ ~NTNL & (SDYS to SIDS)

+ NTNL & SDYS & EXTDAC & RFD

ERR is cleared by pon + (read ISR1) & ~SISB + clearERR

1r

1w

DO

DO IE

0r

0w

DI

DI IE

Data Out bit

Data Out Interrupt Enable bit

DO indicates that the NAT7210, as GPIB Talker, is ready to accept another data byte into the CDOR. This data byte will be transmitted to the GPIB. DO clears when a byte is written to the CDOR or when the NAT7210 ceases to be the Active Talker.

DO is set by

TACS & SGNS & ~nba

DO is cleared by

~TACS + ~SGNS + nba + (read ISR1) & ~SISB

Data In bit

Data In Interrupt Enable Bit

DI indicates that the NAT7210, as a GPIB Listener, has accepted a data byte from the GPIB Talker.

DI is set by

LACS & ACDS & ~(continuous mode)

DI is cleared by pon + (read ISR1 & ~SISB) + (Finish Handshake

& Holdoff mode) + (read DIR)

© National Instruments Corp.

3-53 NAT7210 Reference Manual

7210-Mode Interface Registers Chapter 3

Interrupt Mask Register 2 (IMR2)

Attributes: Write only

7

0

6 5 4 3 2

SRQI DMAO DMAI CO IE LOKC

IE

1

REMC

IE

0

ADSC

IE

Interrupt Status Register 2 (ISR2)

Type:

Attributes:

7210 mode

Read only

Bits clear when read if SISB = 0

7

INT

6

SRQI

5

LOK

4

REM

3

CO

2 1 0

LOKC REMC ADSC

Interrupt Status Register 2 (ISR2) contains Interrupt Status bits and Internal Status bits.

Interrupt Mask Register 2 (IMR2) contains Interrupt Enable bits and Internal Control bits.

If an Interrupt Enable is true when the corresponding status condition or event occurs, the

NAT7210 can generate a hardware interrupt request. See the Generating Hardware

Interrupts section in Chapter 5, Software Considerations .

Bits in ISR2 are set and cleared regardless of the status of the bits in IMR2. If an interrupt condition occurs at the same time the host interface is reading ISR2, the

NAT7210 does not set the corresponding Interrupt Status bit until the read is finished.

A hardware reset clears all bits in IMR2.

Bit

7r

Mnemonic

INT

Description

Interrupt bit

This bit is the logical OR of the Enabled Interrupt Status bits in ISR0, ISR1, and ISR2.

NAT7210 Reference Manual 3-54 © National Instruments Corp.

Chapter 3 7210-Mode Interface Registers

IMR2/ISR2 (continued)

Bit Mnemonic Description

INT is set by

GLINT & [(CPT & CPT IE) + (APT & APT IE)

+ (DET & DET IE) + (ERR & ERR IE)

+ (END RX & END IE) + (DEC & DEC IE)

+ (DO & DO IE) + (DI & DI IE)

+ (REMC & REMC IE) + (SRQI IE & SRQI)

+ (LOKC & LOKC IE) + (CO IE & CO)

+ (ADSC & ADSC IE) + (STBO IE & STBO)

+ (IFCI IE & IFCI) + (ATNI IE & ATNI)

+ (SYNC IE & SYNC)]

6r

6w

SRQI

SRQI IE

© National Instruments Corp.

Service Request bit

Service Request Interrupt Enable bit

SRQI indicates that the NAT7210, as CIC, received a

GPIB Service Request (SRQ) message. SRQI is normally edge sensitive; however, consider the following sequence of events:

1. SRQ asserts, which asserts SRQI.

2. The control program clears SRQI, but SRQ remains asserted.

3. The NAT7210 serial polls a device.

4. The device sends the RQS message to the NAT7210 in response to the serial poll.

5. SRQ remains asserted because another device (not the one being serial polled) is asserting SRQ.

In the situation outlined above, SRQI sets at the end of the serial poll, even if SRQ never unasserts. In addition, if the control program issues the clear SRQI auxiliary command while SRQ is asserted, the NAT7210 clears

SRQI for one clock pulse and then sets SRQI again.

SRQI is set by

(CIC & SRQ & -(RQS & DAV)) becoming true where RQS = DIO7 & ~ATN & SPMS

SRQI is cleared by pon + (read ISR2) & ~SISB + clearSRQI

3-55 NAT7210 Reference Manual

7210-Mode Interface Registers Chapter 3

IMR2/ISR2 (continued)

Bit

5r

4r

Mnemonic

LOK

REM

Description

Lockout bit

Remote bit

LOK and REM indicate the status of the GPIB

Remote/Local (RL1) function of the NAT7210.

LOK

0

0

1

1

REM RL1 State

0

1

0

1

LOCS

REMS

LWLS

RWLS

See the Remote/Local State Considerations section in

Chapter 5, Software Considerations.

5w DMAO

4w

3r

3w

DMAI

CO

CO IE

DMA Output Enable bit

If DMAO = 1, the DRQ pin asserts when the NAT7210, as a GPIB Talker, is ready to accept another data byte into the CDOR.

DMA Input Enable bit

If DMAI = 1, the DRQ pin asserts to indicate that the

NAT7210, as a GPIB Listener, has accepted a data byte from the GPIB Talker.

Command Out bit

Command Out Interrupt Enable bit

CO = 1 indicates that the CDOR is empty and that another command can be written to it for transmission over the

GPIB without overwriting a previous command.

CO is set by

CACS & SGNS & ~nba

NAT7210 Reference Manual 3-56 © National Instruments Corp.

Chapter 3 7210-Mode Interface Registers

IMR2/ISR2 (continued)

Bit Mnemonic Description

CO is cleared by

(read ISR2) & ~SISB + ~CACS + ~SGNS + cdba

2r

2w

LOKC

LOKC IE

Lockout Change bit

Lockout Change Interrupt Enable bit

LOKC sets when no change occurs in the LOK bit,

ISR2[5]r.

LOKC is set by any change in LOK

LOKC is cleared by pon + (read ISR2) & ~SISB + clearLOKC

1r

1w

REMC

REMC IE

Remote Change bit

Remote Change Interrupt Enable bit

REMC sets when no change occurs in the REM bit,

ISR2[4]r.

REMC is set by any change in REM

REMC is cleared by pon + (read ISR2) & ~SISB + clearREMC

0r

0w

ADSC

ADSC IE

Addressed Status Change bit

Addressed Status Change Interrupt Enable bit

ADSC sets when one of the following ADSR bits changes: TA, LA, CIC, or MJMN.

© National Instruments Corp.

ADSC is set by

[(any change in TA) + (any change in LA)

+ (any change in CIC) + (any change in MJMN)]

& ~(lon + ton)

ADSC is cleared by pon + (read ISR2) & ~SISB + clearADSC + lon

+ ton

3-57 NAT7210 Reference Manual

7210-Mode Interface Registers Chapter 3

Parallel Poll Register (PPR)

Attributes: Write only

Accessed at the same offset as AUXMR

7

0

6

1

5

1

4

U

3

S

2

P3

1

P2

0

P1

You use the Parallel Poll Register (PPR) to locally configure the manner in which the

NAT7210 responds to a parallel poll. You write to the PPR at the same offset as the

AUXMR. See the Parallel Polling section in Appendix B, Introduction to the GPIB .

When you use remote Parallel Poll Configuration (IEEE 488 capability code PP1), do not write to the PPR: writing to the PPR after it is remotely configured corrupts the configuration. The NAT7210 implements remote configuration fully and automatically without software assistance. However, you must still set or clear the individual status

(ist) message (by using Set/Clear Parallel Poll Flag auxiliary commands) according to pre-established system protocol convention.

When you use the local Parallel Poll Configuration (capability code PP2), write to the

PPR in advance of a poll. If PP2 (AUXRI[2]w) = 0, the contents written to the PPR are overwritten if the Controller sends a Parallel Poll command (such as PPE or PPD while in

PACS or PPU) that causes the remote configuration to override the local configuration.

If PP2 = 1, the reception of parallel poll commands does not affect the contents of the

PPR and the local configuration determines the response during parallel polls.

Bit

4w

Mnemonic

U

Description

Unconfigure bit

The U bit determines whether the NAT7210 is locally configured to participate in parallel polls. If U = 1, the

NAT7210 does not participate in parallel polls unless it is remotely configured to do so. If the host interface sets U, it should clear S and P[3–1] simultaneously.

If U = 0, the NAT7210 participates in parallel polls and responds in the manner defined by PPR[3] through

PPR[0] and by ist. S and P[3–1] are the same as the bits of the same name in the PPE message, and the I/O write operation to the PPR is the same as the receipt of the PPE message from the GPIB Controller.

NAT7210 Reference Manual 3-58 © National Instruments Corp.

Chapter 3

PPR (continued)

Bit

3w

2–0w

Mnemonic

S

P[3–1]

7210-Mode Interface Registers

Description

Status Bit Polarity (Sense) bit

S indicates the polarity, or sense, of the NAT7210 local ist message. The following table describes the function of S.

S

1

1

0

0 ist

0

1

0

1

State of DIO Line

(Selected by P[3–1]

During a Parallel Poll)

Low Voltage—Logic 1

Unasserted—Logic 0

Unasserted—Logic 0

Low Voltage—Logic 1

Note: The DIO lines must be driven with open-

collector drivers during parallel polls.

Parallel Poll Response bits 3 through 1

P[3–1] indicate which of the eight DIO lines is asserted during a parallel poll. The following table shows the signal on which the NAT7210 responds to parallel polls.

P[3–1]

000

001

010

011

100

101

110

111

Signals on which NAT7210

Responds to Parallel Polls

DIO1

DIO2

DIO3

DIO4

DIO5

DIO6

DIO7

DIO8

For examples of PPR configuration, see Chapter 6, Controller Software Considerations.

© National Instruments Corp.

3-59 NAT7210 Reference Manual

3r

2r

5r

4r

7210-Mode Interface Registers Chapter 3

Source/Acceptor Status Register (SASR)

Attributes: Read only

7 nba

6 5 4 3 2 1 0

AEHS ANHS1 ANHS2 ADHS ACRDY SH1A SH1B

The Source/Acceptor Status Register (SASR) contains status bits that you can use to determine the state of the Source and Acceptor functions.

Bit

7r

Mnemonic nba

Description

New Byte Available local message

6r AEHS Acceptor End Holdoff State bit

ANHS1

ANHS2

ADHS

ACRDY

Acceptor Not Ready Holdoff bit

Acceptor Not Ready Holdoff Immediately bit

Acceptor Data Holdoff State bit

Acceptor Ready State bit

Use this bit to determine the state of the Acceptor

Handshake. By monitoring the LA and ATN bits in the

ADSR, the DAV bit in the BSR, and the ADHS and

ACRDY bits, you can determine the state of the Acceptor

Handshake function as described below:

ANRS = ~AIDS & ~ACRDY & ~DAV

ACRS = ~AIDS & ACRDY & ~DAV

ACDS = ~AIDS & ACRDY & DAV

+ ~AIDS & ~ACRDY & DAV & ATN &

ADHS

AWNS = ~AIDS & ~ACRDY & DAV & ~(ATN &

ADHS)

NAT7210 Reference Manual 3-60 © National Instruments Corp.

Chapter 3

SASR (continued)

Bit

1–0r

Mnemonic

SH1A, SH1B

7210-Mode Interface Registers

Description

Source Handshake State bits

Use these bits to determine the state of the Source

Handshake interface function. By monitoring the TA,

Serial Poll Mode State (SPMS), ATN bits in the ADSR, and the SH1A and SH1B bits, you can determine the state of the Source Handshake function as described below:

SIDS = ~(TACS & ~ATN + CIC & ATN)

SGNS = ~SIDS & ~SH1A & ~SH1B

SDYS = ~SIDS & SH1A

STRS = ~SIDS & ~SH1A & SH1B

© National Instruments Corp.

3-61 NAT7210 Reference Manual

7210-Mode Interface Registers

Serial Poll Mode Register (SPMR)

Attributes: Write only

7

S8

6 rsv/RQS

5

S6

4

S5

3

S4

2

S3

1

S2

Chapter 3

0

S1

Bit

7r,

7w

Serial Poll Status Register (SPSR)

Attributes: Read only

7

S8

6

PEND

Mnemonic

S8

5

S6

4

S5

3

S4

Description

Serial Poll Status bit 8

2

S3

5–0r,

5–0w

S[6–1]

1

S2

0

S1

Serial Poll Status bits 6 through 1

These bits send device- or system-dependent status information over the GPIB when the Controller serial polls the NAT7210.

When STBO IE = 0, the NAT7210 transmits a byte of status information, SPMR[7–0], to the CIC if the CIC serial polls the NAT7210. The SPMR bits S[8, 6–1] are double buffered. If the host interface writes to the SPMR during a serial poll when SPAS is active, the NAT7210 saves the value. The NAT7210 updates the SPMR when the NAT7210 exits SPAS.

When STBO IE = 1 and the Controller serial polls the

NAT7210, the STBO interrupt condition sets. The host interface should write the STB and the RQS bit to the

SPMR in response to an STBO interrupt.

Issuing the Chip Reset auxiliary command clears these bits.

NAT7210 Reference Manual 3-62 © National Instruments Corp.

Chapter 3 7210-Mode Interface Registers

SPMR/SPSR (continued)

Bit

6r

Mnemonic

PEND

Description

Pending bit

PEND sets when rsv = 1. PEND clears when the

NAT7210 is in the Negative Poll Response State (NPRS) and the local Request Service (rsv) message is false. By reading the PEND status bit, you can confirm that a request was accepted and that the Status Byte (STB) was transmitted (PEND = 0).

6w rsv/RQS Request Service/ RQS bit

When STBO IE = 0, bit 6 is the rsv bit. The rsv bit generates the GPIB local rsv message. When rsv = 1 and the GPIB Controller is not serial polling the NAT7210, the NAT7210 enters the Service Request State (SRQS) and asserts the GPIB SRQ signal. When the Controller reads the STB during the poll, the NAT7210 clears rsv.

The rsv bit is also cleared by a hardware reset or by writing 0 to it. Issuing the Chip Reset auxiliary command also clears rsv.

When STBO IE = 1, bit 6 is the RQS bit. When the

Controller serial polls the NAT7210, the STBO interrupt condition sets. The host interface should write the STB and the RQS bit to the SPMR in response to an STBO interrupt. The NAT7210 transfers the STB and RQS to the Controller during that particular serial poll. A hardware reset clears RQS. Issuing the Chip Reset auxiliary command also clears RQS.

© National Instruments Corp.

3-63 NAT7210 Reference Manual

7210-Mode Interface Registers Chapter 3

Version Status Register (VSR)

Attributes: Read only

7

V3

6

V2

5

V1

4

V0

3

X

2

X

1

X

0

X

The Version Status Register (VSR) contains a value that is unique to each NAT7210 revision. You can use the VSR to distinguish a NAT7210 from a

µ

PD7210. Future versions of the NAT7210 may read 10XX.

Bit

7–4r

Mnemonic

V[3–0]

Description

The version number of the NAT7210APD is 1000.

3–0r X Don’t care bits

NAT7210 Reference Manual 3-64 © National Instruments Corp.

Chapter 4

9914-Mode Interface Registers

This chapter contains NAT7210 address maps and detailed descriptions of the NAT7210 interface registers in 9914 mode. For 7210-mode register descriptions, see Chapter 3,

7210-Mode Interface Registers.

9914 Register Map

Table 4-1 is the register bit map for the NAT7210 in 9914 mode.

Notice that bold-ruled cells distinguish six registers that are accessible only when the

Page-In state is true. Refer to The Page-In Condition section that immediately follows the register map for more information.

© National Instruments Corp.

4-1 NAT7210 Reference Manual

9914-Mode Interface Registers

9914 Mode Only

Table 4-1. 9914-Mode Interface Registers

Chapter 4

Key

R

W

= 9914-Mode Paged Registers

= Read Register

= Write Register

ISR0

IMR0

+0

+0

7

INT0

DMAO

6

INT1

DMAI

5

BI

BI IE

4

BO

BO IE

3

END

END IE

2

SPAS

SPAS IE

1

RLC

RLC IE

0

MAC

MAC IE

R

W

ISR1

IMR1

+1

+1

GET

GET IE

ERR

ERR IE

UNC

UNC IE

APT

APT IE

DCAS

DCAS IE

MA

MA IE

SRQ

SRQ IE

IFC

IFC IE

R

W

ADSR

IMR2

EOSR

BCR

ACCR

+2

+2

+2

+2

+2

REM

GLINT

EOS7

ATN

ACC7

LLO

STBO IE

EOS6

DAV

ACC6

ATN

NLEN

EOS5

NDAC

ACC5

LPAS

0

EOS4

NRFD

ACC4

TPAS

LLOC IE

EOS3

EOI

ACC3

LA

ATNI IE

EOS2

SRQ

ACC2

TA

0

EOS1

IFC

ACC1 ulpa

CIC IE

EOS0

REN

ACC0

R

W

W

W

W

BSR +3

AUXCR +3

ISR2

ADR

+4

+4

ATN

C/S nba edpa

DAV

0

STBO dal

NDAC

0

NRFD

F4

NL dat

EOS

A5

EOI

F3

SRQ

F2

LLOC

A4

ATNI

A3

IFC

F1

X

A2

REN

F0

CIC

A1

R

W

R

W

SPSR

SPMR

+5

+5

S8

S8

PEND rsv/RQS

S6

S6

S5

S5

S4

S4

S3

S3

S2

S2

S1

S1

R

W

CPTR

PPR

+6

+6

CPT7

PP8

DIR

CDOR

+7

+7

DIO8

DIO8

CPT6

PP7

DIO7

DIO7

CPT5

PP6

DIO6

DIO6

CPT4

PP5

DIO5

DIO5

CPT3

PP4

DIO4

DIO4

CPT2

PP3

DIO3

DIO3

CPT1

PP2

DIO2

DIO2

CPT0

PP1

R

W

DIO1

DIO1

R

W

NAT7210 Reference Manual 4-2 © National Instruments Corp.

Chapter 4

The Page-In Condition

9914 Mode Only

9914-Mode Interface Registers

Four writable registers can appear at the same offset as the Address Status Register

(ADSR) (offset 4). After a hardware or software reset, no writable register appears at the

ADSR offset: the NAT7210 ignores writes to that offset.

One Page-In auxiliary command exists for each of the four registers. The host interface can make one of the four registers accessible by issuing the appropriate Page-In command to the Auxiliary Command Register (AUXCR). The paged-in register remains accessible at the ADSR offset until the host interface pages-in another register or issues the Clear Page-In Register auxiliary command.

When any one of the four writable registers is accessible at the ADSR offset, Interrupt

Status Register 2 (ISR2) is accessible at the same offset as ADR, and the Serial Poll

Status Register (SPSR) is accessible at the same offset as the Serial Poll Mode Register

(SPMR).

Hidden Registers

In addition to the registers shown in Table 4-1, the NAT7210 contains hidden registers.

All hidden registers are write-only registers. Two or more hidden registers can appear at the same offset. When you write an 8-bit pattern to these offsets, some of the bits determine which hidden register will be written. The other bits represent the value written to the register.

Accessory Read Register Map

Several hidden registers appear at the ACCR offset. Table 4-2 shows these hidden registers.

Table 4-2. Hidden Registers at the ACCR Offset

Register Bit 7 Bit 6 Bit 5 Bit 4

ICR

ACCA

0

1

0

0

1

0

0

BIN

ACCB

ACCE

ACCF

ACCI

1

1

1

1

0

1

1

1

1

0

0

1

ISS

0

1

0

Bit 3

F 3

XEOS

Bit 2

F 2

REOS

Bit 1

F 1

0

Bit 0

F 0

0

INV LWC

DHADT DHADC

DHATA

USTD

DHALA

PP1

SPEOI

0

DHUNTL

0

ATCT

0

DHALL

DMAE

© National Instruments Corp.

4-3 NAT7210 Reference Manual

9914-Mode Interface Registers

9914 Mode Only

Register Bit Descriptions

Chapter 4

Some 7210-mode registers and 9914-mode registers share identical names. The

7210-mode registers are described in Chapter 3, 7210-Mode Interface Registers. If you are using the NAT7210 in 9914 mode, be sure to read the proper description for the

9914-mode registers.

All registers are listed in alphabetical order. The registers are alphabetized according to their mnemonics.

NAT7210 Reference Manual 4-4 © National Instruments Corp.

Chapter 4

9914 Mode Only

Accessory Register A (ACCRA)

9914-Mode Interface Registers

Attributes: Write only

Accessed at the same offset as ACCR

7

1

6

0

5

0

4

BIN

3 2

XEOS REOS

1

0

0

0

Accessory Register A (ACCRA) controls the EOS and END messages. A hardware reset or the ch_rst auxiliary command clears ACCRA.

Bit

4w

Mnemonic

BIN

Description

Binary bit

The BIN bit selects the length of the EOS message. If

BIN = 1, the EOSR is treated as an 8-bit byte. When

BIN = 0, the EOSR is treated as a 7-bit register (for

ASCII characters), and only a 7-bit comparison is done with the data on the GPIB.

3w XEOS

2w REOS

Transmit END With EOS bit

The XEOS bit permits or prohibits automatic transmission of the GPIB END message at the same time as the EOS message when the NAT7210 is in Talker Active State

(TACS). If XEOS = 1 and the byte in the CDOR matches the contents of the EOSR, the EOI line is sent true along with the data.

END On EOS Received bit

The REOS bit permits or prohibits setting the END bit

(ISR0[3]r) when the NAT7210 receives the EOS message as a Listener. If REOS = 1 and the byte in the DIR matches the byte in the EOSR, the END bit (ISR1[4]r) is set and the acceptor function treats the EOS character just as if it were received with EOI asserted.

© National Instruments Corp.

4-5 NAT7210 Reference Manual

9914-Mode Interface Registers

9914 Mode Only

Accessory Register B (ACCRB)

Attributes: Write only

Accessed at the same offset as ACCR

7

1

6

0

5

1

4

ISS

3

INV

Chapter 4

2 1 0

LWC SPEOI ATCT

Bit

4w

Mnemonic

ISS

Description

Individual Status Select bit

ISS determines the value of the NAT7210 ist message.

When ISS = 1, ist takes on the value of the NAT7210

SRQS. (The NAT7210 is asserting the GPIB SRQ message when it is in SRQS.) If ISS = 0, ist takes on the value of the NAT7210 Parallel Poll Flag. You set and clear the Parallel Poll Flag by using the Set Parallel Poll

Flag and Clear Parallel Poll Flag auxiliary commands.

3w

2w

INV

LWC

Invert bit

INV determines the polarity of the INT pin.

INV Bit

0

1

INT Pin Polarity

Active High

Active Low

See the Generating Hardware Interrupts section in

Chapter 5, Software Considerations.

Listen When Controller bit

LWC enables the NAT7210 to accept command bytes that the NAT7210 sources when it is CIC. If LWC = 0, the

NAT7210 does not accept command bytes sent by the

NAT7210.

NAT7210 Reference Manual 4-6 © National Instruments Corp.

Chapter 4

9914 Mode Only

9914-Mode Interface Registers

ACCRB (continued)

Bit

1w

Mnemonic

SPEOI

Description

Send Serial Poll EOI bit

SPEOI determines whether the NAT7210 sends EOI when a Controller serial polls the NAT7210.

SPEOI

0

1

EOI During Serial Polls

Sent False

Sent True

0w ATCT Automatic Take Control bit

If ATCT = 1, the NAT7210 can—without software intervention—take control when another CIC passes control to the NAT7210. Use the CIC bit (ISR2[0] to determine when the NAT7210 receives control. See the

GPIB Controller Considerations section in Chapter 6,

Controller Software Considerations.

© National Instruments Corp.

4-7 NAT7210 Reference Manual

9914-Mode Interface Registers

9914 Mode Only

Accessory Register E (ACCRE)

Attributes: Write only

Accessed at the same offset as ACCR

7

1

6

1

5

0

4

0

3 2

DHADT DHADC

Chapter 4

1

0

0

0

Accessory Register E (ACCRE) determines how the NAT7210 uses a Data Accepted

(DAC) holdoff. A hardware reset or the ch_rst auxiliary command clears ACCRE.

Each bit of ACCRE enables DAC holdoffs on a GPIB command or group of commands. When a GPIB Controller sends the specified command to the NAT7210, the Unrecognized Command (UNC) bit sets and the NAT7210 performs a DAC holdoff.

See the DAC Holdoffs section in Chapter 5, Software Considerations.

Bit

3w

Mnemonic

DHADT

Description

DAC Holdoff On GET bit

2w DHADC DAC Holdoff On DCL Or SDC bit

NAT7210 Reference Manual 4-8 © National Instruments Corp.

1w

0w

Chapter 4

9914 Mode Only

Accessory Register F (ACCRF)

9914-Mode Interface Registers

Attributes: Write only

Accessed at the same offset as ACCR

7

1

6

1

5

0

4

1

3 2 1 0

DHATA DHALA DHUNTL DHALL

Accessory Register F (ACCRF) determines how the NAT7210 uses a DAC holdoff.

A hardware reset or the ch_rst auxiliary command clears ACCRF.

Each bit of ACCRF enables DAC holdoffs on a GPIB command or group of commands.

When a GPIB Controller sends the specified command to the NAT7210, the UNC bit sets and the NAT7210 performs a DAC holdoff. See the DAC Holdoffs section in Chapter 5,

Software Considerations.

Bit

3w

Mnemonic

DHATA

Description

DAC Holdoff On All Talker Addresses bit

2w DHALA DAC Holdoff On All Listener Addresses bit

DHUNTL

DHALL

DAC Holdoff On The UNT Or UNL Command bit

DAC Holdoff On All UCG, ACG, And SCG Commands bit

© National Instruments Corp.

4-9 NAT7210 Reference Manual

9914-Mode Interface Registers

9914 Mode Only

Accessory Register I (ACCRI)

Attributes: Write only

Accessed at the same offset as ACCR

7

1

6

1

5

1

4

0

3

USTD

2

PP1

Bit

3w

Mnemonic

USTD

Chapter 4

1

0

0

DMAE

Description

Ultra Short T1 Delay bit

If USTD = 1, the T1 delay can be as short as 350 ns. See the T1 Delay Generation section in Chapter 5, Software

Considerations.

2w PP1 Parallel Poll bit 1

The PP1 bit permits or prohibits the NAT7210’s ability to automatically respond to remote parallel poll configuration. If PP1 = 1, the NAT7210 can be configured remotely for parallel polls without software intervention.

The Acceptor Handshake does not perform a DAC holdoff or set the UNC bit when it receives a Parallel Poll

Command (PPC or PPU).

If PP1 = 0, parallel polls must be configured through the

PPR, and Parallel Poll commands must be monitored by

UNC.

0w DMAE DMA Enable bit

DMAE lets you use DMAO (IMR0[7]) and DMAI

(IMR0[6]) to enable the DRQ signal.

If DMAE = 0, DRQ always asserts when the NAT7210 receives a data byte as a Listener or when the NAT7210 is a Talker and the CDOR is empty.

DRQ is cleared by pon + (read DIR) + (write CDOR)

NAT7210 Reference Manual 4-10 © National Instruments Corp.

Chapter 4

9914 Mode Only

9914-Mode Interface Registers

Address Register (ADR)

Attributes: Write only

7 edpa

6 dal

5 dat

4

A5

3

A4

2

A3

1

A2

0

A1

ADR is used to load the primary GPIB address of the interface.

Bit Mnemonic Description

7w edpa Enable Dual Primary Addressing Mode bit

Setting edpa enables the dual primary addressing mode of the NAT7210. If edpa = 1, the NAT7210 ignores the least significant bit (A1) of its GPIB address. The NAT7210 then has two consecutive primary addresses. The ulpa bit in the Address Status Register indicates which address is active.

6w

5w dal dat

Disable Listener bit

Setting dal returns the NAT7210 Listener function to

LIDS and forces the NAT7210 Listener function to remain in LIDS even if the chip receives its GPIB listen address or a lon auxiliary command.

Disable Talker bit

Setting dat returns the NAT7210 Talker function to TIDS and forces the Talker function to remain in TIDS even if the chip receives its GPIB talk address or a ton auxiliary command.

4–0w A[5–1]

© National Instruments Corp.

NAT7210 GPIB Address bits 5 through 1

A[5–1] specify the primary GPIB address of the

NAT7210. The corresponding GPIB talk address is formed by adding hex 40 to A[5–1], while the corresponding GPIB listen address is formed by adding hex 20. A[5–1] should not be 11111 (binary) to prevent the corresponding talk and listen addresses from conflicting with the GPIB UNT and GPIB UNL commands.

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9914-Mode Interface Registers

9914 Mode Only

Address Status Register (ADSR)

Attributes: Read only

7

REM

6

LLO

5

ATN

4

LPAS

3

TPAS

2

LA

Chapter 4

1

TA

0 ulpa

The Address Status Register (ADSR) contains information that you can use to monitor the NAT7210 GPIB address status.

Bit

7r

6r

Mnemonic

REM

LLO

Description

Remote bit

Local Lockout bit

REM and LLO indicate the status of the GPIB

Remote/Local (RL1) function of the NAT7210.

LLO

0

0

1

1

REM

0

1

0

1

RL1 State

LOCS

REMS

LWLS

RWLS

5r ATN

4r LPAS

Attention bit

ATN indicates the current level of the NAT7210 ATN pin. If ATN = 1, the ATN pin is asserted (active low).

Listener Primary Addressed State bit

LPAS indicates that the NAT7210 has accepted its primary listen address.

LPAS is cleared by

(PCG & ~MLA & ACDS) + pon

NAT7210 Reference Manual 4-12 © National Instruments Corp.

Chapter 4

ADSR (continued)

Bit

3r

Mnemonic

TPAS

2r

1r

LA

TA

9914 Mode Only

9914-Mode Interface Registers

Description

Talker Primary Addressed State bit

TPAS indicates that the NAT7210 has accepted its primary talk address.

TPAS is cleared by

(PCG & ~MTA & ACDS) + pon

Listener Active bit

LA = 1 when the NAT7210 has been addressed or programmed as a GPIB Listener—that is, the NAT7210 is in LACS or LADS. The NAT7210 is addressed to listen when it receives its listen address from the CIC. You can also program the NAT7210 to listen by using the

Listen-Only auxiliary command.

If the NAT7210 is addressed to listen, it is automatically unaddressed to talk.

LA is cleared by pon + IFC + (UNL & ACDS)

Talker Active bit

TA = 1 when the NAT7210 has been addressed or programmed as the GPIB Talker—that is, the NAT7210 is in TACS, TADS, or SPAS. The NAT7210 can be addressed to talk when it receives its talk address from the

CIC. You can also program the NAT7210 to talk by using the Talk-Only auxiliary command.

If the NAT7210 is addressed to talk, it is automatically unaddressed to listen.

TA is cleared by pon + IFC + (OTA & ACDS)

© National Instruments Corp.

4-13 NAT7210 Reference Manual

9914-Mode Interface Registers

9914 Mode Only

ADSR (continued)

Bit

0r

Mnemonic ulpa

Chapter 4

Description

Upper/Lower Primary Address bit ulpa indicates the least significant bit of the last primary address that the NAT7210 received.

Note: Only one Talker or Listener is active at a time.

ulpa indicates which, if either, NAT7210 Talker or Listener function is addressed or active.

The ch_rst auxiliary command clears the ulpa bit in the

ADSR.

NAT7210 Reference Manual 4-14 © National Instruments Corp.

03

83

04

84

05

06

86

07

87

Hex

Code

00

80

01

81

02

Chapter 4

9914 Mode Only

Auxiliary Command Register (AUXCR)

9914-Mode Interface Registers

Attributes: Write only

7

C/S

6

0

5

0

4

F4

3

F3

2

F2

1

F1

0

F0

Use the AUXCR to issue auxiliary commands. Two basic types of commands are implemented in the AUXCR: pulsed and static. Use static commands to enable (set) or disable (clear) various features of the NAT7210. The pulsed commands stay active for one clock pulse after the AUXCR has been written.

Note: Writes to the AUXCR should be separated by at least 4 clock cycles.

Table 4-3 summarizes the AUXCR auxiliary commands and Table 4-4 describes the

AUXCR auxiliary commands.

Type

Table 4-3. Auxiliary Command Summary

Mnemonic Auxiliary Command static static pulsed pulsed pulsed static static static static pulsed static static static static

~swrst swrst nonvalid valid rhdf

~hdfa hdfa

~hdfe hdfe nbaf

~fget fget

~rtl rtl

Clear Software Reset

Set Software Reset

Nonvalid Release DAC Holdoff

Valid Release DAC Holdoff

Release RFD Holdoff

Clear Holdoff On All Data

Set Holdoff On All Data

Clear Holdoff On END Only

Set Holdoff On END Only

New Byte Available False

Clear Force Group Execute Trigger

Set Force Group Execute Trigger

Clear Return To Local

Set Return To Local

(continues)

© National Instruments Corp.

4-15 NAT7210 Reference Manual

9914-Mode Interface Registers

9914 Mode Only

AUXCR (continued)

Table 4-3. Auxiliary Command Summary (Continued) feoi

~lon lon

~ton ton gts tca tcs

~rpp rpp

~sic sic

~sre sre rqc rlc

~dai dai pulsed static static static static pulsed pulsed pulsed static static static static static static pulsed pulsed static static

Hex

Code

08

0B

0C

0D

0E

8E

09

89

0A

8A

11

12

13

0F

8F

10

90

93

Type Mnemonic Auxiliary Command

14

15

95

16

96 pulsed static static static static pts

~stdl stdl

~shdw shdw

Chapter 4

Send EOI With The Next Byte

Clear Listen Only

Set Listen Only

Clear Talk Only

Set Talk Only

Go To Standby

Take Control Asynchronously

Take Control Synchronously

Clear Request Parallel Poll

Set Request Parallel Poll

Clear Send Interface Clear

Set Send Interface Clear

Clear Send Remote Enable

Set Send Remote Enable

Request Control

Release Control

Clear Disable IMR2, IMR1, And

IMR0 Interrupts

Set Disable IMR2, IMR1, And IMR0

Interrupts

Pass Through Next Secondary

Clear Short T1 Delay

Set Short T1 Delay

Clear Shadow Handshaking

Set Shadow Handshaking

(continues)

NAT7210 Reference Manual 4-16 © National Instruments Corp.

Chapter 4

9914 Mode Only

9914-Mode Interface Registers

AUXCR (continued)

Table 4-3. Auxiliary Command Summary (Continued)

Hex

Code

17

97

18

98

99

1A

9A

1C

9C

9E

9F

1D

9D

1E

1F

Type static static pulsed pulsed pulsed pulsed pulsed static static static static pulsed pulsed pulsed pulsed

Mnemonic

~ist ist piimr2 pibcr clrpi pieosr piaccr

~vstdl vstdl

~rsv2 rsv2 sw7210 reqf reqt ch_rst

Auxiliary Command

Clear Very Short T1 Delay

Set Very Short T1 Delay

Clear Request Service bit 2

Set Request Service bit 2

Switch To 7210 Mode

Request rsv False (reqf)

Request rsv True (reqt)

Chip Reset

Clear Parallel Poll Flag

Set Parallel Poll Flag

Page-In Interrupt Mask Register 2

Page-In Bus Control Register

Clear Page-In Registers

Page-In End-of-String Register

Page-In Accessory Register

Values not specified are reserved.

© National Instruments Corp.

4-17 NAT7210 Reference Manual

9914-Mode Interface Registers

9914 Mode Only

AUXCR (continued)

Table 4-4. Auxiliary Command Description

Chapter 4

Data

Pattern

(Hex)

00

80

01

81

02

03

83

Description

Clear Software Reset (~swrst)

Set Software Reset (swrst)

The local swrst message places all GPIB interface functions into their idle states. swrst is equivalent to the GPIB local Power On (pon) message.

swrst is set by a hardware reset, the ch_rst auxiliary command, or the swrst auxiliary command. You should configure the NAT7210 while swrst is set. Configuration includes writing the address of the device into the Address Register, writing mask values into the Interrupt Mask

Registers, and selecting the desired features in the Auxiliary Command,

Accessory, and Address Registers. When swrst is cleared, the device becomes logically existent on the GPIB.

Release DAC Holdoff (nonvalid)

Release DAC Holdoff (valid)

These commands clear a DAC holdoff condition. When APT = 1,

nonvalid indicates that the last GPIB command byte received from the

Controller was an invalid secondary address. Valid indicates a valid secondary address.

A DAC holdoff caused by any other GPIB command byte should be released with the nonvalid command. See the DAC Holdoffs section in

Chapter 5, Software Considerations.

Release RFD Holdoff (rhdf)

This command releases any RFD holdoffs that hdfa or hlde have caused.

Clear Holdoff On All Data (~hdfa)

Set Holdoff On All Data (hdfa)

If hdfa is true, the NAT7210 performs an RFD holdoff after it receives a data byte. To complete the handshake, you must issue the rhdf command after the NAT7210 receives each byte. A hardware reset or the ch_rst auxiliary command clears hdfa. See The GPIB rdy Message and RFD

Holdoffs section in Chapter 5, Software Considerations.

(continues)

NAT7210 Reference Manual 4-18 © National Instruments Corp.

Chapter 4

9914 Mode Only

9914-Mode Interface Registers

AUXCR (continued)

Table 4-4. Auxiliary Command Description (Continued)

Data

Pattern

(Hex)

04

84

05

06

86

Description

Clear Holdoff On END Only (~hdfe)

Set Holdoff On END Only (hdfe)

If hdfe is true, the NAT7210 performs an RFD holdoff after it receives a data byte that satisfies the END condition. A hardware reset or the ch_rst auxiliary command clears hdfe. The GPIB rdy Message and RFD

Holdoffs section in Chapter 5, Software Considerations.

New Byte Available False (nbaf) nbaf forces the local message, nba, to become false. This action prohibits the NAT7210 from sending the last byte written to the CDOR. See the

Using nbaf section in Chapter 5, Software Considerations .

Clear Force Group Execute Trigger (~fget)

Set Force Group Execute Trigger (fget)

These commands generate a trigger condition.

If the host interface issues ~fget, the TRIG pin pulses asserted for one clock cycle.

If the host interface issues fget, the TRIG pin asserts and remains asserted until the host interface issues ~fget.

These commands do not set or clear the GET bit.

Note: TRIG pin refers to the T/R3 pin when TRM1 = 0. If TRM1 does not equal 1, the TRIG signal is not visible at a pin. See

the Address Mode Register (ADMR) section in Chapter 3,

7210-Mode Interface Registers.

(continues)

© National Instruments Corp.

4-19 NAT7210 Reference Manual

9914-Mode Interface Registers

9914 Mode Only

AUXCR (continued)

Table 4-4. Auxiliary Command Description (Continued)

Chapter 4

Data

Pattern

(Hex)

07

87

08

09

89

0A

8A

0B

Description

Clear Return To Local (~rtl)

Set Return To Local (rtl)

These commands set and clear the IEEE 488 rtl local message. A hardware reset or the ch_rst auxiliary command also clears rtl.

If the host interface issues the ~rtl command, the IEEE 488 rtl message pulses true.

If the host interface issues the rtl command, the IEEE 488 rtl message becomes true and remains true until the host interface issues ~rtl.

Send EOI With The Next Byte (feoi)

The Send EOI command causes the GPIB EOI line to go true with the next data byte transmitted.

Clear Listen Only (~lon)

Set Listen Only (lon) lon forces the Listener function into the Listener Active state. ~lon forces the Listener function to leave the Listener Active state. The local message pon clears lon.

Clear Talk Only (~ton)

Set Talk Only (ton) ton forces the Talker function into the Talker Active state. ~ton forces the

Talker function to leave the Talker Active state. The local message pon clears ton.

Go To Standby (gts)

The gts command pulses the local gts message. If the NAT7210 is the

Active Controller, gts causes the NAT7210 to become the Standby

Controller and to unassert the GPIB ATN signal. See the Three Basic

Controller States section in Chapter 6, Controller Software

Considerations.

(continues)

NAT7210 Reference Manual 4-20 © National Instruments Corp.

Chapter 4 9914-Mode Interface Registers

9914 Mode Only

AUXCR (continued)

Table 4-4. Auxiliary Command Description (Continued)

Data

Pattern

(Hex)

0C

0D

0E

8E

0F

8F

Description

Take Control Asynchronously (tca)

The tca command pulses the local tca message. If the NAT7210 is the

Standby Controller, tca causes the NAT7210 to become the Active

Controller and to assert the GPIB ATN signal.

Take Control Synchronously (tcs)

The tcs command pulses the local tcs message. If the NAT7210 is the

Standby Controller and an Active Listener, the tcs message causes the

NAT7210 to become the Active Controller when the NAT7210 performs an RFD holdoff (that is, the AH function enters ANRS).

Clear Request Parallel Poll (~rpp)

Set Request Parallel Poll (rpp)

The ~rpp and rpp commands set and clear the local rpp message. A hardware reset or the ch_rst auxiliary command also clears rpp. If the

NAT7210 is the Active Controller, the rpp message causes the NAT7210 to send the IDY message to all GPIB devices in the system and to conduct a parallel poll. After the NAT9914 has been conducting a parallel poll for at least 2

µ s, the control program can read the Command Pass Through

Register (CPTR) to obtain the parallel poll result, then the control program can end the parallel poll by issuing the ~rpp command.

Clear Send Interface Clear (~sic)

Set Send Interface Clear (sic)

The ~sic and sic commands clear and set the sic and rsc local messages.

A hardware reset or the ch_rst auxiliary command also clears sic. Setting sic and rsc causes the NAT7210 to become the System Controller and to assert the GPIB Interface Clear (IFC) signal. The control program must not issue the ~sic command until after IFC has been asserted at least 100

µ s. See the System Controller Considerations section in Chapter 6,

Controller Software Considerations.

Note: Before it issues the sic command, the control program must ensure—by some means external to the NAT7210—that the

GPIB transceivers are enabled to drive the GPIB IFC* signal.

© National Instruments Corp.

4-21

(continues)

NAT7210 Reference Manual

9914-Mode Interface Registers

9914 Mode Only

AUXCR (continued)

Table 4-4. Auxiliary Command Description (Continued)

Chapter 4

Data

Pattern

(Hex)

10

90

11

12

13

93

Description

Clear Send Remote Enable (~sre)

Set Send Remote Enable (sre)

The ~sre and sre commands clear and set the sre and rsc local messages.

A hardware reset or the ch_rst auxiliary command also clears sre. Setting sre and rsc causes the NAT7210 to become the System Controller and to assert the GPIB REN signal. The control program must not issue the sre command until after REN has been unasserted at least 100

µ s. Remote

Enable (REN) signal. The control program must not issue the sre command until after REN has been unasserted at least 100

µ s. See the

System Controller Considerations section in Chapter 6, Controller

Software Considerations.

Note: Before it issues the sre command, the control program must ensure—by some means external to the NAT7210—that the

GPIB transceivers are enabled to drive the GPIB REN* signal.

Request Control (rqc)

If the NAT7210 is in the Idle Controller State, the rqc command forces the NAT7210 to become the Active Controller when it detects that the

ATN signal is unasserted.

Release Control (rlc)

The rlc command forces the NAT7210 to become an Idle Controller and to unassert ATN.

Clear Disable IMR2, IMR1, And IMR0 Interrupts (~dai)

Set Disable IMR2, IMR1, And IMR0 Interrupts (dai)

Issuing dai disables the interrupt pin. The Interrupt Status Registers and any holdoffs selected in the Interrupt Mask Register are not affected by the dai command. A hardware reset or the ch_rst auxiliary command clears dai. See the Generating Hardware Interrupts section in Chapter 5,

Software Considerations.

(continues)

NAT7210 Reference Manual 4-22 © National Instruments Corp.

Chapter 4

9914 Mode Only

9914-Mode Interface Registers

AUXCR (continued)

Table 4-4. Auxiliary Command Description (Continued)

Data

Pattern

(Hex)

14

15

95

16

96

17

97

Description

Pass Through Next Secondary (pts)

After you issue the pts command, UNC (ISR1[5]) sets when the

NAT7210 receives a secondary command from the Controller.

If PP1 = 0, you can use the pts command to implement remote parallel poll configuration.

Note: It is simpler to set the PP1 bit to implement remote parallel poll configuration. When PP1 = 1, the NAT7210 interprets remote parallel poll configuration commands without software intervention.

If the NAT7210 receives the PPC command, UNC sets. When the control program detects UNC, the control program issues pts. UNC sets again when the Controller sends the PPE command. The control program reads the CPTR to obtain the PPE command, then the control program writes the appropriate value to the PPR.

Clear Short T1 Delay (~stdl)

Set Short T1 Delay (stdl)

Issuing stdl makes the T1 delay time 1.1

µ s. A hardware reset or the ch_rst auxiliary command clears stdl. See the T1 Delay Generation section in Chapter 5, Software Considerations.

Clear Shadow Handshaking (~shdw)

Set Shadow Handshaking (shdw)

The shdw command places the NAT7210 in continuous mode. A hardware reset or the ch_rst auxiliary command clears shdw. See The

GPIB rdy Message and RFD Holdoffs section in Chapter 5, Software

Considerations.

Clear Very Short T1 Delay (~vstdl)

Set Very Short T1 Delay (vstdl)

Issuing vstdl reduces the T1 delay time to 500 ns. A hardware reset or the ch_rst auxiliary command clears vstdl. See the T1 Delay Generation section in Chapter 5, Software Considerations.

© National Instruments Corp.

4-23

(continues)

NAT7210 Reference Manual

9914-Mode Interface Registers

9914 Mode Only

AUXCR (continued)

Table 4-4. Auxiliary Command Description (Continued)

Chapter 4

Data

Pattern

(Hex)

18

98

99

1A

9A

Description

Clear Request Service bit 2 (~rsv2)

Set Request Service bit 2 (rsv2)

The rsv2 bit performs the same function as the rsv bit in the SPMR, but it provides a means of requesting service that is independent of the SPMR.

With rsv2, you can make minor updates to the SPMR without affecting the state of service request. rsv2 is cleared when the serial poll status byte is sent to the Controller during a serial poll (SPAS & APRS & STRS). A hardware reset or the ch_rst auxiliary command also clears rsv2.

Switch To 7210 Mode (sw7210)

Issuing sw7210 places the NAT7210 into 7210 compatibility mode.

Request rsv False (reqf)

Request rsv True (reqt)

The reqt and reqf commands are inputs to the IEEE 488.2 Service Request

Synchronization Circuit. Use these commands to set and clear the local rsv message. The local message pon clears reqf and reqt.

If STBO IE = 0, reqt and reqf are not issued immediately; they are issued on the write of the SPMR that follows the issuing of the reqt or reqf auxiliary command.

If STBO IE = 1, reqt and reqf are issued immediately. The local message pon clears reqf and reqt. See the IEEE 488.2 Service Requesting section in Chapter 5, Software Considerations .

(continues)

NAT7210 Reference Manual 4-24 © National Instruments Corp.

Chapter 4

9914 Mode Only

9914-Mode Interface Registers

AUXCR (continued)

Table 4-4. Auxiliary Command Description (Continued)

Data

Pattern

(Hex)

1C

1D

9D

1E

Description

Chip Reset (ch_rst)

The Chip Reset command resets the NAT7210 to the following conditions:

• The local swrst message is set and the interface functions are placed in their idle states.

• SPMR bits are cleared.

• EOS and NL bits are cleared.

• ACCRA, ACCRB, ACCRE, ACCRF, and ACCRI registers are cleared.

• The Parallel Poll Flag local message is cleared.

• The ulpa bit is cleared.

Clear Parallel Poll Flag (~ist)

Set Parallel Poll Flag (ist)

The ~ist and ist commands set and clear the Parallel Poll Flag. The value of the Parallel Poll Flag is used as the local ist message when bit four of

Accessory Register B (ISS) = 0. The value of SRQS is used as the local ist message when ISS = 1. A hardware reset or the ch_rst auxiliary command clears ist.

Page-In Interrupt Mask Register 2 (piimr2)

Issuing piimr2 maps Interrupt Mask Register 2 (IMR2) to the ADSR offset. After this command is issued, you can access IMR2 at the ADSR offset until one of the following events occurs:

• A hardware reset occurs.

• The ch_rst auxiliary command is issued.

• Another register is paged into the ADSR offset.

• The Clear Page-In auxiliary command is issued.

© National Instruments Corp.

4-25

(continues)

NAT7210 Reference Manual

9914-Mode Interface Registers

9914 Mode Only

AUXCR (continued)

Table 4-4. Auxiliary Command Description (Continued)

Chapter 4

Data

Pattern

(Hex)

1F

9C

9E

Description

Page-In Bus Control Register (pibcr)

Issuing pibcr maps the Bus Control Register (BCR) to the ADSR offset.

After this command is issued, you can access BCR at the ADSR offset until one of the following events occurs:

• A hardware reset occurs.

• The ch_rst auxiliary command is issued.

• Another register is paged into the ADSR offset.

• The Clear Page-In auxiliary command is issued.

Clear Page-In Registers (clrpi)

Issuing clrpi removes the previously paged-in Accessory Register from the ADSR offset. After this command is issued, writes to offset 2 have no effect until a Page-In auxiliary command is issued.

Page-In End-of-String Register (pieosr)

Issuing pieosr maps the EOSR to the ADSR offset. After this command is issued, you can access the EOSR at the ADSR offset until one of the following events occurs:

• A hardware reset occurs.

• The ch_rst auxiliary command is issued.

• Another register is paged into the ADSR offset.

• The Clear Page-In auxiliary command is issued.

(continues)

NAT7210 Reference Manual 4-26 © National Instruments Corp.

Chapter 4

9914 Mode Only

9914-Mode Interface Registers

AUXCR (continued)

Table 4-4. Auxiliary Command Description (Continued)

9F Page-In Accessory Register (piaccr)

Issuing piaccr maps the ACCR to the ADSR offset. After this command is issued, you can access the ACCR at the ADSR offset until one of the following events occurs:

• A hardware reset occurs.

• The ch_rst auxiliary command is issued.

• Another register is paged into the ADSR offset.

• The Clear Page-In auxiliary command is issued.

© National Instruments Corp.

4-27 NAT7210 Reference Manual

Bit

7r

7w

9914-Mode Interface Registers

9914 Mode Only

Bus Control Register (BCR)/Bus Status Register (BSR)

Attributes: Write only (BCR)

Read only (BSR)

7

ATN

ATN

6 5 4

DAV NDAC NRFD

DAV NDAC NRFD

3

EOI

EOI

2

SRQ

SRQ

1

IFC

IFC

Mnemonic

ATN

ATN

Description

GPIB Attention Status bit

GPIB Attention Control bit

Chapter 4

0

REN

REN

4r

4w

3r

3w

6r

6w

5r

5w

DAV

DAV

NDAC

NDAC

NRFD

NRFD

EOI

EOI

GPIB Data Valid Status bit

GPIB Data Valid Control bit

GPIB Not Data Accepted Status bit

GPIB Not Data Accepted Control bit

GPIB Not Ready For Data Status bit

GPIB Not Ready For Data Control bit

GPIB End-or-Identify Status bit

GPIB End-or-Identify Control bit

2r

2w

1r

1w

SRQ

SRQ

IFC

IFC

GPIB Service Request Status bit

GPIB Service Request Control bit

GPIB Interface Clear Status bit

GPIB Interface Clear Control bit

0r

0w

REN

REN

GPIB Remote Enable Status bit

GPIB Remote Enable Control bit

Reads of the Bus Status Register (BSR) return the status of the GPIB control lines at the time of the read. Write ones to bits in the Bus Control Register (BCR) to assert the corresponding GPIB control lines.

NAT7210 Reference Manual 4-28 © National Instruments Corp.

Chapter 4 9914-Mode Interface Registers

9914 Mode Only

BCR/BSR (continued)

Because the NAT7210 is either transmitting or receiving a GPIB control line at any particular time and is not performing both actions simultaneously, setting a bit in the

BCR may not automatically assert the corresponding line on the GPIB. If the NAT7210 is transmitting a GPIB line when the corresponding bit in the BCR is set, the NAT7210 asserts the GPIB line. If the NAT7210 is receiving a GPIB line when the corresponding bit in the BCR is set, the GPIB line is not asserted. However, in both these cases, the

GPIB signal internal to the NAT7210 is logically ORed with the value of the BCR bit.

Figure 4-1 illustrates the GPIB input/output hardware configuration.

Transmit Enable

GPIB Line Out

BCR Bit

PIN

NDAC

NRFD

SRQ

GPIB Line In eliminates glitches in

REN & IFC

Figure 4-1. GPIB I/O Hardware Configuration

In Figure 4-1, Transmit Enable represents the internal signal that is true when the chip is driving a particular GPIB control line. GPIB Line Out represents the internal signal that is true when an interface function within the chip is attempting to assert a GPIB control signal. BCR Bit corresponds to the bit in the BCR. GPIB Line In represents the internal

GPIB lines that are inputs to the GPIB interface functions and the BSR. The internal signals SRQ , NDAC, and NRFD are monitored by the interface functions even when they are not driven onto the pin. For this reason, the internal value of these signals is ORed with the external value.

Because the BSR samples the GPIB control lines from the GPIB transceiver—not the actual GPIB bus—the direction of each line determines the validity of each bit.

Generally, when a signal is an input, the BSR reflects its true bus status, while an output signal reflects only the NAT7210 value of that particular line. Under normal GPIB operation, this restriction on the validity of the BSR should not be too limiting, because the lines that are typically monitored are valid when they are monitored. For example, the SRQ line is valid in the BSR when the NAT7210 is CIC, which is also when the SRQ line will be monitored.

© National Instruments Corp.

4-29 NAT7210 Reference Manual

9914-Mode Interface Registers

9914 Mode Only

Command/Data Out Register (CDOR)

Attributes: Write only

7

DIO8

6

DIO7

5

DIO6

4

DIO5

3

DIO4

2

DIO3

Bit

7–0w

Mnemonic

DIO[8–1]

Chapter 4

1

DIO2

0

DIO1

Description

GPIB data lines DIO[8–1]

The CDOR moves data from the CPU to the GPIB when the interface is the GPIB Talker or Controller. Writing to the CDOR sets the local message, nba. When nba is true, the Source Handshake (SH) function can transfer the data or command in the CDOR to other GPIB devices.

Writing to the CDOR also

• Clears the Byte Out (BO) bit.

• Clears the DRQ signal (unless DMAE = 1 and

DMAO = 0).

The host interface can write to the CDOR at offset 7 or by performing a DMA write operation.

The CDOR and the DIR use separate latches. A read of the DIR does not change data in the CDOR. The CDOR is a transparent latch; thus, the GPIB data bus (DIO(8–1)) reflects changes on the CPU data bus during write cycles to the CDOR.

NAT7210 Reference Manual 4-30 © National Instruments Corp.

Chapter 4

9914 Mode Only

Command Pass Through Register (CPTR)

9914-Mode Interface Registers

Attributes: Read only

7 6

CPT7 CPT6

5 4

CPT5 CPT4

3

CPT3

2 1

CPT2 CPT1

0

CPT0

The host interface can examine the GPIB DIO lines by reading the Command Pass

Through Register (CPTR). The CPTR has no storage; the host interface should read the

CPTR only during a DAC holdoff. See the DAC Holdoffs section in Chapter 5, Software

Considerations.

Bit

7–0r

Mnemonic

CPT[7–0]

Description

Command Pass Through bits 7 through 0

© National Instruments Corp.

4-31 NAT7210 Reference Manual

9914-Mode Interface Registers

9914 Mode Only

Data In Register (DIR)

Attributes: Read only

7

DIO8

6

DIO7

5

DIO6

4

DIO5

3

DIO4

2

DIO3

Bit

7–0r

Mnemonic

DIO[8–1]

Chapter 4

1

DIO2

0

DIO1

Description

GPIB data lines DIO[8–1]

The DIR holds data that the NAT7210 receives when the

NAT7210 is a Listener. The NAT7210 latches GPIB data into the DIR when LACS & ACDS is true.

Latching data into the DIR causes the DI bit to set.

Usually, latching data into the DIR causes an RFD (Ready

For Data) holdoff. (See The GPIB rdy Message and RFD

Holdoffs section in Chapter 5, Software Considerations.)

The host interface can read the DIR at offset 7 or by performing a DMA read operation. Reading the DIR also

• Clears the BI bit.

• Can clear an RFD holdoff (depending on several other conditions).

• Clears the DRQ signal (unless DMAE = 1 and

DMAI = 0).

The DIR and the CDOR use separate latches. When the host interface writes to the CDOR, data in the DIR is not changed.

NAT7210 Reference Manual 4-32 © National Instruments Corp.

Chapter 4

9914 Mode Only

End-of-String Register (EOSR)

9914-Mode Interface Registers

Attributes: Write only

7

EOS7

6

EOS6

5

EOS5

4

EOS4

3

EOS3

2

EOS2

1

EOS1

0

EOS0

The End-of-String Register (EOSR) holds the byte that the NAT7210 uses to detect the end of a GPIB data block transfer. The NAT7210 compares data it receives to a 7- or

8-bit byte (ASCII or binary—depending on the BIN bit) in the EOSR in order to detect the end of a block of data.

If the NAT7210 is a Listener and REOS = 1, the END bit is set in ISR0 whenever the received data byte matches the EOSR. If the NAT7210 is a Talker and XEOS = 1, the

END message (GPIB EOI* line asserted low) is sent along with a data byte whenever the data byte matches the EOSR.

Bit

7–0w

Mnemonic

EOS[7–0]

Description

End-of-String bits 7 through 0

© National Instruments Corp.

4-33 NAT7210 Reference Manual

9914-Mode Interface Registers

9914 Mode Only

Internal Count Register (ICR)

Attributes: Write only

7

0

6

0

5

1

4

0

3

F3

2

F2

Chapter 4

1

F1

0

F0

The Internal Count Register (ICR) determines the internal clock frequency of the

NAT7210. You write to the ICR at the same offset as the ACCR.

Note: The ICR resets to 00101000 (8 MHz).

Bit Mnemonic Description

3–0 F(3–0) Clock Frequency

These bits, in addition to MICR (ICR2[0]), determine the length of certain delays that are required by the

IEEE 488 standard. You should set these bits according to the frequency of the signal driving the CLK pin. For proper operation, set F(3–0) and MICR as follows:

Clock

Frequency

1

2

5

6

3

4

10

16

7

8

20

MICR

0

0

0

0

0

0

0

0

1

1

1

F(3–0)

0101

0110

0111

1000

0001

0010

0011

0100

0101

1000

1010

NAT7210 Reference Manual 4-34 © National Instruments Corp.

Chapter 4

9914 Mode Only

Interrupt Mask Register 0 (IMR0)

9914-Mode Interface Registers

Attributes: Write only

7 6

DMAO DMAI

5

BI IE

4 3 2 1 0

BO IE END IE SPAS IE RLC IE MAC IE

Interrupt Status Register 0 (ISR0)

Attributes: Read only

Bits are cleared when read

7

INT0

6

INT1

5

BI

4

BO

3

END

2

SPAS

1

RLC

0

MAC

Interrupt Status Register 0 (ISR0) contains Interrupt Status bits. Interrupt Mask

Register 0 (IMR0) contains Interrupt Enable bits that directly correspond to the Interrupt

Status bits in ISR0. As a result, ISR0 and IMR0 service six possible interrupt conditions; each condition has an associated Interrupt Status bit and an Interrupt Enable bit. If an

Interrupt Enable bit is true when the corresponding status condition or event occurs, the

NAT7210 can generate a hardware interrupt request. See the Generating Hardware

Interrupts section in Chapter 5, Software Considerations .

Bits in ISR0 are set and cleared regardless of the status of the Interrupt bits in IMR0.

If an interrupt condition occurs at the same time the host interface is reading ISR0, the

NAT7210 does not set the corresponding Interrupt Status bit until the read is finished.

A hardware reset clears all bits in IMR0.

Bit

7r

Mnemonic

INT0

Description

Interrupt Register 0 Interrupt bit

INT0 is set when an unmasked status bit in ISR0 is set.

7w DMAO DMA Output Enable bit

If DMAE = 1 (ACCRI[0]), DMAO enables the NAT7210 to assert the DRQ pin as a GPIB Talker. The NAT7210 asserts DRQ when it is ready to accept another byte in the

CDOR. DRQ does not assert if the NAT7210 is not a

Talker.

© National Instruments Corp.

If DMAE = 0, write 0 to DMAO.

4-35 NAT7210 Reference Manual

9914-Mode Interface Registers

9914 Mode Only

IMR0/ISR0

(

continued)

Bit

6r

Mnemonic

INT1

Chapter 4

Description

Interrupt Register 1 Interrupt bit

INT1 is set when an unmasked status bit in Interrupt

Status Register 1 (ISR1) is set.

6w

5r

5w

DMAI

BI

BI IE

DMA Input Enable bit

If DMAE = 1 (ACCRI[0]), DMAI enables the NAT7210 to assert the DRQ pin as a GPIB Listener. The NAT7210 asserts DRQ when the DIR contains a byte for the host interface to read.

If DMAE = 0, write 0 to DMAI.

Byte In bit

Byte In Interrupt Enable bit

BI indicates that a data byte has been received in the Data

In Register. An RFD holdoff must be cleared before the

NAT7210 accepts the next data byte.

BI is set by

LACS & ACDS & ~(continuous mode)

BI is cleared by swrst + (read ISR0) + (read DIR)

4r

4w

BO

BO IE

NAT7210 Reference Manual

Byte Out bit

Byte Out Interrupt Enable bit

BO indicates that the NAT7210 is the Active Controller or Talker and that the CDOR does not contain a byte to send over the GPIB. BO sets again after each byte has been sent and the source handshake has returned to

SGNS.

BO is set by

(CACS + TACS) & SGNS & ~nba

BO is cleared by swrst + (read ISR0) + (write CDOR)

4-36 © National Instruments Corp.

Chapter 4

9914 Mode Only

9914-Mode Interface Registers

IMR0/ISR0

(

continued)

Bit

3r

3w

Mnemonic

END

END IE

Description

End Received bit

End Received Interrupt Enable bit

END sets when the NAT7210, as a Listener, receives a data byte satisfying the END condition. A data byte satisfies the END condition if one of the following conditions is true:

• REOS = 1 and the data byte matches the contents of the EOSR.

• NLEN = 1 and the data byte matches the ASCII new line character (hex 0A).

• The GPIB EOI signal is asserted when the byte is received.

That is, END is set by

(EOI + EOS & REOS + NL & NLEN) & LACS

& ACDS

END is cleared by swrst + (read ISR0)

2r

2w

SPAS

SPAS IE

Serial Poll Active State bit

Serial Poll Active State Interrupt Enable bit

SPAS indicates that the Controller has serial polled the

NAT7210 in response to the NAT7210 requesting service.

SPAS is set by

[STRS & SPAS & APRS] becoming false

SPAS is cleared by swrst + (read ISR0)

1r

1w

RLC

RLC IE

Remote/Local Change bit

Remote/Local Change Interrupt Enable bit

RLC is set when a change occurs in the REM bit,

ADSR[7]r.

© National Instruments Corp.

4-37 NAT7210 Reference Manual

9914-Mode Interface Registers

9914 Mode Only

IMR0/ISR0

(

continued)

Bit Mnemonic Description

RLC is cleared by swrst + (read ISR0)

0r

0w

MAC

MAC IE

Chapter 4

My Address Change bit

My Address Change Interrupt Enable bit

MAC indicates that the NAT7210 has received a command from the Controller and that this command has changed the addressed state of the NAT7210.

If the NAT7210 is using secondary addressing, MAC sets only when the NAT7210 becomes unaddressed. If edpa = 1, MAC does not set when the Controller readdresses the NAT7210 at the NAT7210’s other primary address.

MAC is set by

ACDS & (MTA & ~TADS & ~APT IE

+ OTA & TADS

+ MLA & ~LADS & ~APT IE

+ UNL & LADS)

MAC is cleared by swrst + (read ISR0)

NAT7210 Reference Manual 4-38 © National Instruments Corp.

Chapter 4

9914 Mode Only

Interrupt Mask Register 1 (IMR1)

9914-Mode Interface Registers

Attributes: Write only

7 6 5 4 3 2 1 0

GET IE ERR IE UNC IE APT IE DCAS IE MA IE SRQ IE IFC IE

Interrupt Status Register 1 (ISR1)

Attributes: Read only

Bits are cleared when read

7

GET

6

ERR

5

UNC

4

APT

3

DCAS

2

MA

1

SRQ

0

IFC

Bit

7r

7w

Interrupt Status Register 1 (ISR1) contains Interrupt Status bits. Interrupt Mask

Register 1 (IMR1) contains Interrupt Enable bits that directly correspond to the Interrupt

Status bits in ISR1. As a result, ISR1 and IMR1 service interrupt conditions; each condition has an associated Interrupt Status bit and an Interrupt Enable bit. If an Interrupt

Enable bit is true when the corresponding status condition or event occurs, the NAT7210 can generate a hardware interrupt request. See the Generating Hardware Interrupts section in Chapter 5, Software Considerations.

Bits in ISR1 are set and cleared regardless of the status of the Interrupt bits in IMR1.

If an interrupt condition occurs at the same time the host interface is reading ISR1, the

NAT7210 does not set the corresponding Interrupt Status bit until the read is finished.

A hardware reset clears all bits in IMR1.

The interrupts GET, UNC, APT, DCAS, and MA are set in response to commands received over the bus. If the corresponding Interrupt Enable bit is set, a DAC holdoff occurs when the interrupt sets.

Mnemonic

GET

GET IE

Description

Group Execute Trigger bit

Group Execute Trigger Interrupt Enable bit

GET indicates that the NAT7210 received the GPIB GET command while the NAT7210 was a GPIB Listener.

© National Instruments Corp.

4-39 NAT7210 Reference Manual

9914-Mode Interface Registers

9914 Mode Only

IMR1/ISR1 (continued)

Bit Mnemonic

Chapter 4

Description

If GET IE = 1, a DAC holdoff occurs when the interrupt condition occurs. The TRIG pin goes high when the interrupt condition occurs and remains high until the DAC holdoff is released.

If GET IE = 0, the TRIG pin pulses high.

GET is set by

GET & LADS & ACDS

GET is cleared by swrst + (read ISR1)

Note: TRIG pin refers to the T/R3 pin when

TRM1 = 0. If TRM1 does not equal 1, the

TRIG signal is not visible at a pin. See the

Address Mode Register (ADMR) section in

Chapter 3, 7210-Mode Interface Registers.

6r

6w

ERR

ERR IE

5r

5w

UNC

UNC IE

Error bit

Error Interrupt Enable bit

ERR sets when the Source Handshake becomes active

(enters SDYS) and finds that the NDAC and NRFD lines are both unasserted on the GPIB. This condition indicates that there are no acceptors on the GPIB.

ERR is set by

SDYS & EXTDAC & RFD

ERR is cleared by swrst + (read ISR1)

Unrecognized Command bit

Unrecognized Command Interrupt Enable bit

UNC flags the occurrence of several types of GPIB commands. UNC sets when the NAT7210 accepts any unrecognized Universal Command Group (UCG) command.

NAT7210 Reference Manual 4-40 © National Instruments Corp.

Chapter 4

9914 Mode Only

9914-Mode Interface Registers

IMR1/ISR1 (continued)

Bit Mnemonic Description

If the NAT7210 is an addressed Listener, UNC sets when the NAT7210 accepts any unrecognized Addressed

Command Group (ACG) command.

UNC flags the first secondary command that the

NAT7210 accepts after the host interface issues the Pass

Through Next secondary auxiliary command. UNC can also flag the occurrence of commands that you specify when you set the AUXRE[3–2]w or AUXRF[3–0]w bits.

If UNC IE = 1, the NAT7210 performs a DAC holdoff when UNC sets. The host interface releases the DAC holdoff by issuing the Release DAC Holdoff auxiliary command. Read undefined commands by using the

Command Pass Through Register (CPTR).

UNC is set by

ACDS & UCG & ~(LLO + SPE + SPD + DCL +

PPU & PP1)

+ ACDS & ACG & ~(GET + GTL

+ SDC + TCT + PPC & PP1) & LADS

+ SCG & PTS & ACDS

+ DHADT & GET & ACDS

+ DHADC & (SDC + DCL) & ACDS

+ DHATA & TAG & ~UNT & ACDS

+ DHALA & LAG & ~UNL & ACDS

+ DHUNTL & (UNT + UNL) & ACDS

+ DHALL & ATN & ACDS

UNC is cleared by swrst + (read ISR1)

4r

4w

APT

APT IE

© National Instruments Corp.

Address Pass Through bit

Address Pass Through Interrupt Enable bit

Setting APT IE enables secondary addressing. If the last primary command accepted was a primary talk or listen address of the NAT7210, APT sets when the NAT7210 accepts a secondary command. The secondary command is a secondary GPIB address that can be read in the

CPTR.

Note: When the host interface uses secondary addressing, it must check APT.

4-41 NAT7210 Reference Manual

9914-Mode Interface Registers

9914 Mode Only

IMR1/ISR1 (continued)

Bit Mnemonic

Chapter 4

Description

If APT IE = 1, the NAT7210 performs a DAC holdoff when APT sets. The host interface releases the DAC holdoff by issuing the Release DAC Holdoff auxiliary command.

APT is set by

(TPAS + LPAS) & SCG & ACDS

APT is cleared by swrst + (read ISR1)

3r

3w

DCAS

DCAS IE

2r

2w

MA

MA IE

Device Clear Active State bit

Device Clear Active State Interrupt Enable bit

DCAS indicates that either the NAT7210 received the

GPIB Device Clear (DCL) command or that the

NAT7210 was a Listener and received the GPIB Selected

Device Clear (SDC) command.

If DCAS IE = 1, the NAT7210 performs a DAC holdoff when DCAS sets. The host interface releases the DAC holdoff by issuing the Release DAC Holdoff auxiliary command.

DCAS is set by

ACDS & (DCL + SDC & LADS)

DCAS is cleared by swrst + (read ISR1)

My Address bit

My Address Interrupt Enable bit

MA sets when the NAT7210 accepts its primary talk or listen address.

If MA IE = 1, the NAT7210 performs a DAC holdoff when MA sets. The host interface releases the DAC holdoff by issuing the Release DAC Holdoff auxiliary command.

NAT7210 Reference Manual 4-42 © National Instruments Corp.

Chapter 4

9914 Mode Only

9914-Mode Interface Registers

IMR1/ISR1 (continued)

Bit Mnemonic Description

MA is set by

(MLA + MTA) & ACDS & ~SPMS & ~APT IE

MA is cleared by swrst + (read ISR1)

1r

1w

SRQ

SRQ IE

0r

0w

IFC

IFC IE

Service Request bit

Service Request Interrupt Enable bit

The SRQ bit indicates that the NAT7210 received a GPIB

SRQ message while the NAT7210 was the CIC.

The SRQ bit is cleared by swrst + (read ISR1)

Interface Clear bit

Interface Clear Interrupt Enable bit

IFC sets on the assertion of the GPIB IFC signal.

IFC is cleared by swrst + (read ISR1)

© National Instruments Corp.

4-43 NAT7210 Reference Manual

9914-Mode Interface Registers

9914 Mode Only

Interrupt Mask Register 2 (IMR2)

Attributes: Write only

7 6

GLINT STBO

IE

5

NLEN

4

0

3

LLOC

IE

2

ATNI

IE

Interrupt Status Register 2 (ISR2)

Chapter 4

1

0

0

CIC IE

7 nba

6

STBO

5

NL

4

EOS

3 2

LLOC ATNI

1

X

0

CIC

Interrupt Status Register 2 (ISR2) contains Interrupt Status bits and Internal Status bits.

Interrupt Mask Register 2 (IMR2) contains Interrupt Enable bits and Internal Control bits.

As a result, ISR2 and IMR2 service several possible interrupt conditions; each condition has an associated Interrupt Status bit and an Interrupt Enable bit. If an Interrupt Enable bit is true when the corresponding status condition or event occurs, the NAT7210 can generate a hardware interrupt request. See the Generating Hardware Interrupts section in Chapter 5, Software Considerations .

Bits in ISR2 are set and cleared regardless of the status of the Interrupt bits in IMR2.

If an interrupt condition occurs at the same time the host interface is reading ISR2, the

NAT7210 does not set the corresponding Interrupt Status bit until the read is finished.

A hardware reset clears all bits in IMR2 except GLINT.

Bit

7r

Mnemonic nba

Description

New Byte Available local message bit nba is true when the local variable nba is true. nba is set on writes to the CDOR and cleared on entrance to STRS, pon, or nbaf.

7w GLINT

NAT7210 Reference Manual

Global Interrupt Enable bit

GLINT enables the NAT7210 to assert the INT pin.

If GLINT = 0, INT does not assert. See the Generating

Hardware Interrupts section in Chapter 5, Software

Considerations.

4-44 © National Instruments Corp.

Chapter 4

9914 Mode Only

9914-Mode Interface Registers

IMR2/ISR2 (continued)

Bit

6r

6w

Mnemonic

STBO

STBO IE

Description

Status Byte Out bit

Status Byte Out Interrupt Enable bit

STBO is set when the NAT7210 enters SPAS when

STBO IE = 1. After STBO sets, the control program should write the current STB to the SPMR. The current

STB is then transmitted to the GPIB as the STB. Writing the SPMR clears STBO.

STBO IE determines how the NAT7210 requests service and responds to serial polls.

If STBO IE = 0, the rsv bit in the SPMR can be used to request service. When the GPIB Controller serial polls the NAT7210, the NAT7210 transmits the current value of the SPMR.

If STBO IE = 1, the rsv bit in the SPMR has no effect on the SR1 function and rsv must be generated through the reqt auxiliary command. When the GPIB Controller serial polls the NAT7210, STBO sets. In response to

STBO, the host interface writes a byte to the SPMR, then the NAT7210 transmits this byte as the Serial Poll response.

STBO is set by

STBO IE & SPAS

STBO is cleared by swrst + (write SPMR) + ~SPAS

5r NL New Line Receive bit

NL indicates that the last data byte that the NAT7210 received was an ASCII new line character.

NL is set by

LACS & NL & ACDS

NL is cleared by swrst + (LACS & ~NL & ACDS)

© National Instruments Corp.

4-45 NAT7210 Reference Manual

9914-Mode Interface Registers

9914 Mode Only

IMR2/ISR2 (continued)

Bit

5w

Mnemonic

NLEN

Chapter 4

Description

New Line End Enable bit

If NLEN = 1, the NAT7210 treats the 7-bit ASCII new line character (0A hex) as an EOS character. The

Acceptor Handshake function responds to the acceptance of a new line character in the same manner as if EOI were sent.

4r EOS End-of-String bit

EOS indicates that REOS = 1 and that the last data byte the NAT7210 received matched the contents of the

EOSR.

EOS is set by

LACS & EOS & REOS & ACDS

EOS is cleared by swrst + (LACS & ~EOS & ACDS) + ~REOS

3r

3w

LLOC

LLOC IE

2r

2w

1r

ATNI

ATNI IE

X

Local Lockout Change bit

Local Lockout Change Interrupt Enable bit

LLOC is set by any change in the LLO bit

LLOC is cleared by ch_rst + (read ISR0)

ATN Interrupt bit

ATN Interrupt Enable bit

ATN is set by

(ATN) becoming true

ATN is cleared by ch_rst + read ISR0

Don’t care bit

NAT7210 Reference Manual 4-46 © National Instruments Corp.

Chapter 4

9914 Mode Only

9914-Mode Interface Registers

IMR2/ISR2 (continued)

Bit

0r

0w

Mnemonic

CIC

CIC IE

Description

Controller-In-Charge bit

Controller-In-Charge Interrupt Enable bit

CIC indicates whether the NAT7210 is the Controller-in -

Charge.

CIC = ~(CIDS + CADS)

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4-47 NAT7210 Reference Manual

9914-Mode Interface Registers

9914 Mode Only

Parallel Poll Register (PPR)

Attributes: Write only

7

PP8

6

PP7

5

PP6

4

PP5

3

PP4

2

PP3

Bit

7–0w

Mnemonic

PP8–PP1

Chapter 4

1

PP2

0

PP1

Description

When a Controller initiates a parallel poll, the NAT7210 drives the contents of the PPR on the GPIB DIO lines using open-collector drivers. If PP8–PP1 = 00 (hex), none of the lines (DIO(8–1)) are asserted during a parallel poll.

The PPR is double buffered. If the PPR is written during a parallel poll, the new value is held until the parallel poll ends. When the parallel poll ends, the register is updated, so the control program can update the parallel poll response asynchronously to the GPIB.

A hardware reset or the ch_rst auxiliary command clears

PPR. The host interface can load PPR while swrst = 1.

NAT7210 Reference Manual 4-48 © National Instruments Corp.

Chapter 4

9914 Mode Only

Serial Poll Mode Register (SPMR)

9914-Mode Interface Registers

Attributes: Write only

7

S8

6 rsv/RQS

5

S6

4

S5

3

S4

2

S3

1

S2

0

S1

Bit

7r,

7w

Serial Poll Status Register (SPSR)

Attributes: Read only

7

S8

6

PEND

Mnemonic

S8

5

S6

4

S5

3

S4

Description

Serial Poll Status bit 8

2

S3

5–0r,

5–0w

S[6–1]

1

S2

0

S1

Serial Poll Status bits 6 through 1

These bits send device- or system-dependent status information over the GPIB when the Controller serial polls the NAT7210.

When STBO IE = 0, the NAT7210 transmits a byte of status information, SPMR[7–0], to the CIC if the CIC serial polls the NAT7210. The SPMR bits S[8, 6–1] are double buffered. If the host interface writes to the SPMR during a serial poll when SPAS is active, the NAT7210 saves the value. The NAT7210 updates the SPMR when the NAT7210 exits SPAS.

When STBO IE = 1 and the Controller serial polls the

NAT7210, the STBO interrupt condition sets. The host interface should write the STB and the RQS bit to the

SPMR in response to an STBO interrupt.

Issuing the ch_rst auxiliary command clears these bits.

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4-49 NAT7210 Reference Manual

9914-Mode Interface Registers

9914 Mode Only

SPMR/SPSR (continued)

Bit

6r

Mnemonic

PEND

Chapter 4

Description

Pending bit

PEND sets when rsv = 1. PEND clears when the

NAT7210 is in the Negative Poll Response State (NPRS) and the local Request Service (rsv) message is false. By reading the PEND status bit, you can confirm that a request was accepted and that the Status Byte (STB) was transmitted (PEND = 0).

6w rsv/RQS Request Service/ RQS bit

When STBO IE = 0, bit 6 is the rsv bit. The rsv bit generates the GPIB local rsv message. When rsv = 1 and the GPIB Controller is not serial polling the NAT7210, the NAT7210 enters the Service Request State (SRQS) and asserts the GPIB SRQ signal. When the Controller reads the STB during the poll, the NAT7210 clears rsv.

The rsv bit is also cleared by a hardware reset or by writing 0 to it. Issuing the ch_rst auxiliary command also clears rsv.

When STBO IE = 1, bit 6 is the RQS bit. When the

Controller serial polls the NAT7210, the STBO interrupt condition sets. The host interface should write the STB and the RQS bit to the SPMR in response to an STBO interrupt. The NAT7210 transfers the STB and RQS to the Controller during that particular serial poll. A hardware reset clears RQS. Issuing the ch_rst auxiliary command also clears RQS.

NAT7210 Reference Manual 4-50 © National Instruments Corp.

Chapter 5

Software Considerations

The chapter explains important NAT7210 programming considerations, including chip initialization, Talkers and Listeners, message reception, and holdoffs. You should also refer to Chapter 6, Controller Software Considerations , for applications that use the

NAT7210 GPIB Controller functions.

This chapter, except where explicitly noted, assumes that the NAT7210 uses 7210-mode architecture and that the reader is familiar with the GPIB. For more information about

GPIB, refer to Appendix B, Introduction to the GPIB, and the IEEE 488.1 and

IEEE 488.2 standard.

Chip Initialization Sequence

1. Place the NAT7210 in 7210 Mode

Place the NAT7210 in 7210 mode by performing one of the following actions:

• Assert the RESET* pin.

• Write the sw7210 command to the AUXCR if the NAT7210 is in 9914 mode.

• Write 99 (hex) to offset 3 if you do not know whether the NAT7210 is in 7210 mode or 9914 mode. If the chip is in 9914 mode, this write places it in 7120 mode. If the chip is already in 7210 mode, this write access writes to the 7210-mode SPMR.

2. Make Sure the Local pon Message Is Asserted

Write the Chip Reset auxiliary command (2 hex) to the AUXMR to assert the local pon message. When pon is asserted, the chip is logically disconnected from the GPIB and the

GPIB interface functions of the NAT7210 are idle (and ignore GPIB signals).

3. Set the Clock Frequency

Set the clock frequency of the NAT7210 by writing to the ICR and the ICR2.

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Software Considerations Chapter 5

4. Configure the Chip for GPIB Operation

A. Set the GPIB Address(es)

Write to the ADMR to configure the GPIB addressing mode of the NAT7210. In most applications, you write 31 (hex) to the ADMR to set the dual primary addressing mode.

Load the primary GPIB address of the NAT7210 into internal Address Register 0

(ADR0) by writing to the Address register. If the device has only one GPIB address, disable ADR1 by writing E0 (hex) to the Address Register.

Note: If the device has only one GPIB address, disable ADR1 by writing E0 (hex) to the Address Register.

B. Write the Initial Serial Poll Response

If another device in your system has Controller capabilities, write the initial serial poll response of the NAT7210 to the SPMR. See the Serial Polling section in Appendix B,

Introduction to the GPIB.

C. Configure Initial Parallel Response

If another device in your system has Controller capabilities, configure the initial parallel poll response of the NAT7210 by writing to AUXRI and PPR. (See the Parallel Polling section in Appendix B, Introduction to the GPIB.)

D. Set GPIB Handshake Parameters

1.

Set the Source Handshake T1 delay by setting or clearing the TRI and USTD bits.

(See the T1 Delay Generation section, which is located later in this chapter.)

2.

Set CHES to enable the clearing of the END detection circuitry on the reception of a data byte without END.

3.

Set NTNL to prevent the NAT7210 from sourcing data or commands when no

Listeners are on the GPIB.

4.

Issue the hldi auxiliary command to make the NAT7210 perform an RFD holdoff if it is addressed to listen.

5. Enable Interrupts

Set or clear the appropriate Interrupt Enable bits in IMR0, IMR1, and IMR2. Set the

SISB bit, if desired.

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Chapter 5 Software Considerations

6. Clear the Local pon Message

Issue the pon auxiliary command to clear the local pon message and to begin GPIB operation.

GPIB Talker or Listener Considerations

GPIB Addressing

Logical and Physical Devices

When you connect the NAT7210 to the GPIB by using standard GPIB transceivers, the

NAT7210 is one physical GPIB device. The IEEE 488.1 transceiver places a single physical device load on the GPIB. The IEEE 488.1 standard specifies that a GPIB system contain no more than 15 physical devices.

In most applications, the NAT7210 is also one logical device. However, a single physical

GPIB device can implement more than one logical GPIB device. Each logical device must have a unique GPIB address. The NAT7210 can implement up to 961 logical GPIB devices.

Normal and Extended Addressing

Logical GPIB devices use either normal or extended addressing. With normal addressing, a GPIB device has a single address; valid addresses are 0 through 30

(decimal), inclusive. To address a device to become a Talker or Listener, a Controller sends the talk or listen address of the device. If a device’s address is 6, for example, a

Controller sends the My Talk Address 6 (MTA6) message to address that device to become a Talker.

With extended addressing, a GPIB device has two addresses: a primary address and a secondary address. Valid primary addresses are 0 through 30 (decimal), inclusive; valid secondary addresses are also 0 through 30 (decimal), inclusive. With extended addressing, 961 (decimal) unique GPIB addresses exist. To address a device to become a

Talker or Listener, a Controller sends the primary talk or listen address of the device, then sends the secondary address of the device.

Implementing One Logical Device: Normal Addressing

The NAT7210 can implement one logical device that uses normal addressing. The

NAT7210 can become an Addressed Listener or Talker without the intervention of the host interface. The TA bit in ADSR sets when the NAT7210 is an Addressed Talker, and the Listener Active (LA) bit in ADSR sets when the NAT7210 is an Addressed Listener.

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Software Considerations Chapter 5

Complete the following steps to implement one logical device that uses normal addressing:

1.

Choose the normal dual addressing mode by writing a 31 (hex) to the ADMR.

2.

Write the logical address to ADR0.

3.

Disable ADR1 by setting the Disable Talker (DT) and Disable Listener (DL) bits in

ADR1—that is, write a hex E0 to offset hex 6. Notice that ADR1 and ADR0 both appear at offset 6.

Implementing One Logical Device: Extended Addressing

The NAT7210 can implement one logical device that uses extended addressing. The

NAT7210 can become an Addressed Listener or Talker without the intervention of the host interface. When the Controller sends the primary talk or listen address of the

NAT7210, the Talker Primary Addressed State (TPAS) bit or the Listener Primary

Addressed State (LPAS) bit in the ADSR sets. When the Controller sends the secondary address of the NAT7210, the TA bit and the LA bit in the ADSR set.

Complete the following steps to implement one logical device that uses extended addressing:

1.

Choose the extended single addressing mode by writing a 32 (hex) to the ADMR.

2. Write the primary and secondary addresses to ADR0 and ADR1, respectively.

Notice that ADR1 and ADR0 both appear at offset 6.

Implementing Two Logical Devices: Normal Addressing

The NAT7210 can implement two logical devices that use normal addressing. The

NAT7210 can become an Addressed Listener or Talker for either of these devices without the intervention of the host interface. The TA bit in ADSR sets when the

NAT7210 is an Addressed Talker, and the LA bit in ADSR sets when the NAT7210 is an

Addressed Listener. The Major-Minor (MJMN) bit in ADSR indicates which of the two devices is addressed.

This mode requires one logical address for each device: the major device address and the minor device address. Major and minor distinguish between the two devices and do not denote the priority of one device over the other.

Complete the following steps to implement two logical devices that use normal addressing:

1.

Choose the normal dual addressing mode by writing a 31 (hex) to the ADMR.

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Chapter 5 Software Considerations

2.

Write the major address to ADR0 and write the minor address to ADR1. Notice that

ADR1 and ADR0 both appear at offset 6.

Implementing Two Logical Devices: Extended Addressing

The NAT7210 can implement two logical devices that use extended addressing. The

NAT7210 can become an Addressed Talker or Listener only after the Controller sends the primary and secondary addresses of one of the two logical devices. The two logical devices are the major logical device and the minor logical device.

This mode requires intervention from the host interface. Complete the following steps to implement two logical devices that use extended addressing:

1.

Choose the extended dual addressing mode by writing a 33 (hex) to the ADMR.

2.

Write the primary address of the major device to the ADR0 and write the primary address of the minor device to the ADR1. The host interface stores the secondary addresses of the NAT7210 external to the NAT7210, then the following sequence of events occurs:

• The Controller sends the primary talk or listen address of the NAT7210 to the

GPIB.

• The NAT7210 enters the TPAS or LPAS state. The MJMN bit sets or clears to indicate the reception of the minor or major primary address.

• The Controller sends a secondary address to the GPIB.

• The Address Pass Through (APT) bit sets (see ISR1).

• The NAT7210 performs a Data Accepted (DAC) holdoff.

• The host interface reads the Command Pass Through Register (CPTR) to determine whether the Controller sent the secondary address of the NAT7210.

• If the host interface determines that the Controller sent the secondary address of the NAT7210, it issues the valid auxiliary command, and the NAT7210 becomes addressed.

• If the host interface determines that the Controller sent the secondary address of another device, it issues the nonvalid auxiliary command.

Implementing Three or More Logical Devices: Normal Addressing

The NAT7210 can implement three or more logical devices that use normal addressing.

This mode requires intervention from the host interface. Refer to the Talker function in the IEEE 488.1 standard.

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Software Considerations Chapter 5

Complete the following steps to implement three logical devices that use normal addressing:

1.

Choose the no-addressing mode by writing a 30 (hex) to the ADMR. The host interface stores the addresses of the NAT7210 external to the NAT7210.

2.

Set the following bits in Auxiliary Register F (AUXRF): DAC Holdoff On All

Talker Addresses (DHATA) bit and DAC Holdoff On All Listener Addresses

(DHALA) bit. The following sequence of events then occurs:

• The Controller sends a talk or listen address to the GPIB.

• The Command Pass Through (CPT) bit sets (see ISR1).

• The NAT7210 performs a DAC holdoff.

3.

Wait for the CPT bit to set. CPT sets when the Controller sends any talk or listen address over the GPIB.

4.

Read the CPTR to determine whether the Controller sent one of the talk or listen addresses of the NAT7210.

5.

If the CPTR matches one of the talk addresses of the NAT7210, the following sequence programs the NAT7210 to be the Addressed Talker:

• Write B0 to the ADMR.

• Write 30 to the ADMR.

If the CPTR matches one of the listen addresses of the NAT7210, the following sequence programs the NAT7210 to be the Addressed Listener:

• Write 70 to the ADMR.

• Write 30 to the ADMR.

6.

Write the valid auxiliary command to the AUXMR. The NAT7210 performs a DAC holdoff on the command byte the Controller sends. The valid auxiliary command releases the DAC holdoff.

Implementing Three or More Logical Devices: Extended Addressing

The NAT7210 can implement three or more logical devices that use extended addressing.

The required steps are similar to the steps for implementing three or more logical devices that use normal addressing. By using CPT and CPTR, the host interface monitors all commands. The host interface addresses and unaddresses the NAT7210 as needed. See the Extended Talker function in the IEEE 488.1 standard.

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Chapter 5 Software Considerations

Complete the following steps to implement three logical devices that use extended addressing:

1.

Choose the no-addressing mode by writing a 30 (hex) to the ADMR. The host interface stores the addresses of the NAT7210 external to the NAT7210.

2.

Set the DAC Holdoff On All UCG, ACG, and SCG Commands (DHALL) bit in

AUXRF.

Programmed Implementation of a Talker and Listener

When no Controller is in the GPIB system, you can use the ton and lon address modes to activate the NAT7210 GPIB Talker and Listener functions (refer to the Address Mode

Register section in Chapter 3, 7210-Mode Interface Registers). Set the ton or lon mode during NAT7210 initialization.

Detecting a GPIB Listener

When the NAT7210 is the Active Talker (and not an Active Listener), it can determine whether a Listener is in the GPIB system. Simply read the BCR. If either NDAC or

NRFD is asserted in the BCR, an Active Listener is in the system.

Sending GPIB Data Messages

Basic Flow

Complete the following steps to send GPIB (device-dependent) data to another device in your system:

1. Be certain that NTNL = 1 (AUXRG[3]). NTNL prevents the NAT7210 from sourcing commands if there are no listening devices in the system.

2. Be certain that the you have enabled the desired T1 delay. (See the T1 Delay

Generation section, which is located later in this chapter.)

3. Wait until the NAT7210 has been programmed or addressed to be the Active Talker.

Poll or interrupt on the ADSC (ISR2[0]) condition, then read the ADSR to determine whether the NAT7210 is a Talker.

4. Wait for the DO bit to set.

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Software Considerations Chapter 5

5. Perform the following steps for each data byte that is sent:

• Write the data byte to the CDOR.

• Wait for either the DO bit or the ERR (ISR1[2]) bit to set. DO indicates that all devices in the system have accepted the command. ERR indicates that no properly operating GPIB devices are in the system.

The host interface can either poll the DO and ERR bits or configure the NAT7210 to interrupt on DO and ERR by setting the DO IE and ERR IE bits.

If the ERR bit sets, issue the nbaf auxiliary command to clear any byte that may be in the CDOR, then issue the ClearERR auxiliary command to clear the ERR bit.

Sending EOI or EOS

To send the GPIB END message and a data byte, issue the SendEOI auxiliary command just before you write the byte to the CDOR. To send the EOS message, simply make the last byte that you write to the CDOR the End-of-String (EOS) code. You can also use the

XEOS bit (AUXRA[3]) to send the END message whenever the byte in the CDOR matches the End-of-String Register (EOSR).

Using DMA

To use DMA to send data bytes, set the DMAO bit after the NAT7210 has been addressed to talk. The DRQ pin of the NAT7210 asserts whenever the CDOR is empty.

The DMA Controller should respond to DRQ by asserting the DACK* and WR* pins to place a data byte into the CDOR.

T1 Delay Generation

The T1 Delay

When the NAT7210, as a GPIB Talker, transfers data bytes to GPIB Listeners, it drives the data byte on the GPIB DIO[8–1] signals. After waiting for a certain delay (known as the T1 delay), the NAT7210 asserts DAV to indicate to the Listeners that the data byte has settled on the DIO[8–1] signals.

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Chapter 5 Software Considerations

HSTS Definition

The length of the T1 delay depends on several factors. One factor is the internal HSTS signal of the NAT7210. HSTS clears when the GPIB Controller asserts the GPIB ATN signal. HSTS sets after the NAT7210, as a GPIB Talker, transfers a byte. Usually, the

T1 delay is longer for the first data byte of a transfer (HSTS = 0). The T1 delay is shorter for the second byte of a transfer (and for subsequent bytes).

IEEE 488.1 Standard Requirements

The IEEE 488.1 standard describes minimum T1 delay requirements for three cases:

• Case 1: The Talking device uses three-state drivers on the DIO, DAV, and EOI signals. Usually, the NAT7210 is connected to the GPIB with 75160 and 75162 transceivers. In the typical configuration, the 75160 and 75162 transceivers use three-state drivers on the DIO, DAV, and EOI signals.

• Case 2: The Talking device satisfies the requirements of case 1 and uses 48-mA three-state drivers (again, the 75160 and 75162 satisfy this requirement). In addition, the following requirements are placed on the GPIB system (and not just on the

Talking device):

– All devices in the system must be powered on.

– The maximum cable length for the system is either 15 m or 1 m times the number of equivalent device loads in the system—whichever is less.

– The device capacitance on each signal should be less that 50 pF per device

(again, the 75160 and 75162 satisfy this requirement).

• Case 3: All other configurations.

Table 5-1 shows the IEEE 488.1 minimum T1 delay requirements for the three cases.

Table 5-1. IEEE 488.1 Minimum T1 Delay Requirements

Case

Number

Case 1

Case 2

Case 3

First Byte (HSTS = 0, or ATN asserted)

1100 ns

1100 ns

2000 ns

Other Bytes

(HSTS = 1)

500 ns

350 ns

2000 ns

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T1 Delay: 7210 Mode

In 7210 mode, the USTD bit (AUXRI[3]), the B2 bit (AUXRB[2]), and the HSTS signal determine the NAT7210 T1 delay. Table 5-2 shows the T1 delay for various settings.

Table 5-2. T1 Delay Settings in 7210 Mode

HSTS USTD

0 0

0

1

1

0

1

1

1

1

0

1

TRI

X

X

0

0

1

1

T1 Delay (ns)

2000

1100

2000

1100

500

350

T1 Delay: 9914 Mode

In 9914 mode, the USTD bit (ACCRI[3]), the vstdl bit (AUXCR), the stdl bit (AUXCR), and the HSTS signal determine the NAT7210 T1 delay (see the HSTS Definition section in this chapter). Table 5-3 shows the T1 delay for various settings.

Table 5-3. T1 Delay Settings in 9914 Mode

HSTS USTD

X 0

0

0

X

X

1

1

1

0

0

1 vstdl

0

X

X

0

1

X stdl

0

0

1

1

X

X

T1 Delay (ns)

2000

2000

1100

1100

500

350

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Chapter 5 Software Considerations

Using nbaf

You can use the nbaf auxiliary command in the following situation: Suppose the

NAT7210 is a Talker and a byte is written to the CDOR. Also suppose that the

Controller asserts ATN before the NAT7210 transfers the byte in the CDOR. The

Controller unasserts ATN and the NAT7210 is still a Talker. If NTNL is set, the Talker transmits the byte stored in the CDOR. The nbaf command suppresses the transmission of this byte.

Receiving GPIB Data Messages

Basic Flow

Complete the following steps to receive GPIB (device-dependent) data from another device in your system:

1. Wait until the NAT7210 has been programmed or addressed to be an Active

Listener.

2. Issue the rhdf auxiliary command to release holdoffs caused by the hldi auxiliary command.

3. Perform the following steps for each data byte that is received:

• Wait for the DI bit to set.

• Read the DIR to obtain the received byte.

The host interface can either poll the DI bit or configure the NAT7210 to interrupt on the DI condition by setting DI IE.

Receiving END or EOS

The END RX bit (ISR1[4]) informs the control program that the NAT7210 has received an END or EOS message. The EOS message can be the new line character, 0A hex (if the NLEN bit is set in IMR0), the value written to the EOSR (if the REOS bit in AUXRA is set), or both.

When the END bit is set, read the EOI bit in ADR1 and the NL and EOS bits in ISR0 to determine which terminating event caused END to set.

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Performing an RFD Holdoff on the Last Data Byte

You usually want to perform an RFD holdoff on the last byte of a string of data that was read in from the GPIB during a GPIB read operation. If the last byte of the data read in was sent with EOI asserted or was the EOS character, an RFD holdoff is performed automatically if the NAT7210 has been programmed for the RFD Holdoff On END Mode

(AUXRA(1–0) = 10 (bin)).

If you do not know whether the last byte that the Talker sent will be transmitted with EOI or whether it will match the EOS character, program the NAT7210 to RFD Holdoff On

All Data Mode (AUXRA(1–0) = 01 (bin)). By programming the NAT7210 to RFD

Holdoff On All Data Mode, you force the NAT7210 to perform an RFD holdoff on the next byte of data that is received in the DIR until a Release Handshake Holdoff auxiliary command is issued.

Also see the Acceptor Handshake Holdoffs section, which is located later in this chapter.

Using DMA

To use DMA to receive data bytes, set the DMAI bit after the NAT7210 has been addressed to listen. The DRQ pin of the NAT7210 asserts whenever the DIR contains a byte to read. The DMA Controller should respond to DRQ by asserting the DACK* and

RD* pins in order to read a data byte from the DIR.

Acceptor Handshake Holdoffs

The GPIB rdy Message and RFD Holdoffs

When it is a Listener, the NAT7210 must let the Talker know whether the NAT7210 is ready to receive another data byte. The NAT7210 unasserts the GPIB Not Ready For

Data (NRFD) signal to indicate that it is ready to receive another byte. The NAT7210 generates the Ready For Next (rdy) message internally. When rdy = 1, the NAT7210 is ready to receive a data byte. When rdy = 0, the NAT7210 is not ready to receive a data byte and it asserts the GPIB NRFD signal. When the NAT7210 asserts the GPIB NRFD signal to prevent the transmission of a data byte, the NAT7210 is performing a Ready For

Data (RFD) holdoff. (For more information, refer to Figure B-5, Three-Wire Handshake

Process , in Appendix B, Introduction to the GPIB.)

The NAT7210 performs RFD holdoffs only on data bytes—that is, bytes sent with ATN unasserted. The NAT7210 can holdoff command bytes by using DAC holdoffs.

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Chapter 5 Software Considerations

Generating the rdy Message

The local rdy message becomes true if ATN is asserted or if the following conditions are both true:

• The NAT7210 is not performing an immediate RFD holdoff.

• The NAT7210 is not performing a data byte RFD holdoff.

Immediate RFD Holdoff

Write the Holdoff Handshake Immediately (hldi) auxiliary command to the AUXMR in order to start an immediate RFD holdoff. You can clear the immediate RFD holdoff by writing the Release RFD Holdoff (rhdf) or Chip Reset auxiliary command to the

AUXMR. The pon message does not clear an immediate RFD holdoff condition, so the host interface can issue hldi while pon is set and the NAT7210 is being configured.

Read the Acceptor Not Ready Holdoff Immediately (ANHS2) bit (SASR[4]) to determine the state of the Immediate Holdoff function.

Data-Receiving Modes

The data byte RFD holdoff condition is set and cleared depending on the data-receiving mode. When the NAT7210 is a Listener, it receives data in one of four modes. One (and only one) data-receiving mode is active at any time.

1. Normal

In normal mode, the NAT7210 performs a data byte RFD holdoff after every byte it accepts. After receiving a data byte, the NAT7210 is not ready to receive another byte until the data byte RFD holdoff condition is cleared. The NAT7210 releases the holdoff when the DIR is read.

2. RFD Holdoff On All Data (hlda)

In hlda mode, the NAT7210 performs a data byte RFD holdoff after every data byte it receives. Writing the rhdf auxiliary command to the AUXMR clears the RFD holdoff condition in hlda mode.

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3. RFD Holdoff On END (hlde)

In hlde mode, the NAT7210 performs a data byte RFD holdoff after every data byte it receives. If the last data byte the NAT7210 received satisfies the END condition, writing the rhdf auxiliary command to the AUXMR clears the RFD holdoff. The END condition is defined by

END = EOI + (REOS & EOS) + (NLEE & newline)

If the last data byte the NAT7210 received does not satisfy the END condition, the

NAT7210 releases the holdoff when the DIR is read.

4. Continuous (cont)

You generally use continuous mode when the NAT7210, as a Controller, wants to monitor a data transfer between two devices but does not need to store the data.

The NAT7210 performs an RFD holdoff in continuous mode if it receives a byte that satisfies the END condition. If the NAT7210 receives a byte that does not satisfy the

END condition, it does not perform an RFD holdoff. Writing the rhdf auxiliary command to the AUXMR clears the RFD holdoff in continuous mode. Bytes are not stored in the

DIR and the DI bit does not set in continuous mode.

Choosing a Data-Receiving Mode

The value of the AUXRA[1–0] bits usually determines the data-receiving mode.

However, if the host interface writes the (ltn&cont) command to the AUXMR, the

NAT7210 uses continuous mode until the host interface either writes the ltn command to the AUXMR or the NAT7210 becomes unaddressed as a Listener.

DAC Holdoffs

When a DAC holdoff condition is true, the NAT7210 is interpreting but has not yet accepted a command byte sent by the Controller. A DAC holdoff forces the Controller to keep the command byte on the GPIB valid and the GPIB Data Valid (DAV) signal asserted. (For more information, refer to Figure B-5, Three-Wire Handshake Process , in

Appendix B, Introduction to the GPIB.) By using DAC holdoffs, a control program prevents another command from being sent until the current command has been completely processed. Once the host interface responds to the command byte, it releases the DAC holdoff by writing the valid or nonvalid auxiliary command to the AUXMR.

In most applications, you do not need to use DAC holdoffs: the NAT7210 automatically interprets command bytes and sets various interrupt bits when it receives certain command bytes.

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Chapter 5 Software Considerations

DAC holdoffs can occur only on GPIB command bytes (ATN asserted). Data bytes

(ATN unasserted) can be held off with RFD holdoffs, which are described earlier in this chapter.

Determining When DAC Holdoffs Occur

The NAT7210 can be configured to perform DAC holdoffs on many different types of command bytes. The SDHS signal determines which command bytes will cause a DAC holdoff. SDHS is defined by the following:

SDHS = [UCG + ACG & (TADS + LADS)] & undefined & CPT ENAB

+ UDPCF & SCG & CPT ENAB

+ DHADT & GET

+ DHADC & (SDC + DCL)

+ DHATA & TAG & ~UNT

+ DHALA & LAG & ~UNL

+ DHUNTL & (UNT + UNL)

+ DHALL & (UCG + ACG + SCG)

+ DHDC & (DCL + SDC & LADS)

+ DHDT & GET

+ SCG & (TPAS + LPAS) & (dual extended address mode)

By issuing the valid or nonvalid auxiliary command, you clear the Acceptor Data Holdoff

State (ADHS). By clearing ADHS, you clear the DAC holdoff.

Read the ADHS bit (SASR[3]) to determine the state of the DAC holdoff condition.

Device Status Reporting (Polling)

Requesting Service

Asserting the SRQ Signal

The NAT7210 requests service from the GPIB CIC by asserting the GPIB SRQ signal.

However, the host interface cannot directly control the SRQ signal: the rsv signal determines when the NAT7210 asserts SRQ.

After rsv asserts, the NAT7210 asserts the SRQ signal. When the CIC serial polls the

NAT7210, the NAT7210 unasserts SRQ. The NAT7210 does not assert SRQ again until rsv unasserts, then reasserts. Refer to the SR1 function in the IEEE 488.1 standard for more information.

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Software Considerations Chapter 5

IEEE 488.2 Service Requesting

To request service, issue the reqt auxiliary command, then write the status byte (STB) to the SPMR.

Note: If STBO IE = 1 after issuing reqt, do not write to the SPMR until the STBO interrupt condition becomes true.

When you write to the SPMR, write 0 to bit 6 (the rsv bit). The NAT7210 asserts and unasserts the rsv signal according to the Set rsv State Machine that is described in the

IEEE 488.2 standard.

After the CIC serial polls the NAT7210, you must issue the reqt auxiliary command and write to the SPMR again to request service. If you want to stop requesting service before a serial poll occurs, issue the reqf auxiliary command.

7210-Style Service Requesting

Most applications should use the IEEE 488.2 service-requesting method that is described in the section above. However, the NAT7210 also supports the 7210 style of requesting service. To request service, check the PEND bit of the SPSR to make sure that the

NAT7210 is not currently responding to a serial poll. If PEND = 0, write the desired

STB to the SPMR. When you write to the SPMR, set bit 6, which is the rsv bit. This write causes the PEND bit to set and the NAT7210 to assert the GPIB SRQ line. The

PEND bit remains set until the serial poll completes.

Responding to Serial Polls

If STBO IE = 0 when the CIC serial polls the NAT7210, the NAT7210 sends the STB to the CIC without the host interface intervening.

If the contents of the STB are likely to change between the time you issue reqt and the time the CIC serial polls the NAT7210, you can use the STBO IE bit. When

STBO IE = 1, the NAT7210 does not respond to a serial poll immediately. Instead, when the CIC serial polls the NAT7210, the NAT7210 generates an interrupt. In response to this interrupt, the host interface writes the STB to the SPMR (write 0 to bit 6). The

NAT7210 responds to the serial poll by sending the STB to the CIC.

When the NAT7210 sends the STB to the CIC, it also sends the RQS message to the CIC by asserting the GPIB DIO7 signal if the NAT7210 is requesting service. The CIC normally reads the STB once, but if the CIC asserts ATN between each 1-byte read, the

CIC can read the STB any number of times. The NAT7210 asserts the GPIB DIO7 signal, however, only during the first read. After the first read, rsv clears. PEND clears when the CIC asserts ATN in order to terminate the serial poll.

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Chapter 5 Software Considerations

The NAT7210 asserts the GPIB EOI line during a serial poll if the SPEOI bit of AUXRB is set.

Responding to Parallel Polls

For more information, see the Parallel Polling section in Appendix B, Introduction to

the GPIB.

The ist Message

When it responds to a Parallel Poll, the NAT7210 can transmit only one bit of information to the CIC. This one bit contains the status of the ist message. If ISS = 1

(AUXRB[4]), ist is true if the NAT7210 is asserting the SRQ signal—that is, the

IEEE 488.1 Service Request function of the NAT7210 is in the SRQS state.

If ISS = 0, you set and clear the ist message by using the ist and ~ist auxiliary commands.

If ISS = 0, the meaning of the ist message is device dependent.

Remote Configuration

Before the CIC can parallel poll the NAT7210, the NAT7210 must first be configured to respond to parallel polls. The control program can locally configure the NAT7210

(IEEE 488.1 capability code PP1) or the NAT7210 can let the CIC remotely configure the

NAT7210 (IEEE 488.1 capability code PP2).

To let the CIC remotely configure the NAT7210, clear the PP2 bit in AUXRI. Do not write to the PPR. The CIC configures the NAT7210 without software intervention, and it enables or disables the NAT7210 to respond to parallel polls. The CIC configures the polarity of the NAT7210’s response, and it also selects the PPR message that the

NAT7210 uses to respond to parallel polls.

Local Configuration

To implement local configuration, disable remote configuration by setting the PP2 in

AUXRI, then write to the PPR to configure the parallel poll response. The bits in the

PPR determine which GPIB data line the NAT7210 uses to respond to parallel polls.

The PPR also determines the polarity of the parallel poll response. See Table 5-4.

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Software Considerations

Table 5-4. Parallel Poll Register Example

Binary Value Written to the AUXMR

0 1 1 1 0 0 0 0

0 1 1 0 0 0 0 0

0 1 1 0 1 0 0 1

Result

Unconfigures PPR. U = 1.

0 0 0 0 0 is written to the PPR. The NAT7210 participates in parallel polls, asserting the

DIO1 line if ist is 0.

0 1 0 0 1 is written to the PPR. The NAT7210 participates in parallel polls, asserting the

DIO2 line if ist is 1.

Chapter 5

Disabling the Parallel Poll Response

To completely disable the NAT7210 from responding to parallel polls (IEEE 488.1

capability code PP0), set the PP2 bit in AUXRI and set the U bit in the PPR.

Generating Hardware Interrupts

The Interrupt pin asserts when the INT bit (ISR2[7]) is true. If INV = 1 (AUXRB[3]), the

INTR pin is active low. If INV = 0, the INTR pin is active high.

Remote/Local State Considerations

The NAT7210 implements the GPIB Remote/Local (RL1) function as described by the

IEEE 488.1 standard. The host interface determines the state of the RL1 function by reading the Lockout (LOK) bit and the Remote (REM) bit in ISR2. The Lockout Change

(LOKC) bit and the Remote Change (REMC) bit can be used to interrupt the host interface when the state of the RL1 function changes.

If the NAT7210 is not in a Lockout state (that is, LOK = 0), the host interface can force the NAT7210 to enter a Local state (REM = 0) by writing one of the Return To Local

(rtl) auxiliary commands to the AUXMR.

See the IEEE 488.1 standard and the IEEE 488.2 standard for device requirements that depend on the RL1 function.

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Chapter 5 Software Considerations

Device Triggering

The NAT7210 enters the Device Trigger Active State (DTAS) when the GPIB Controller sends the Group Execute Trigger (GET) command to the NAT7210. As the IEEE 488.1

standard requires, the NAT7210 enters DTAS only if the NAT7210 is an Addressed

Listener. The DET bit in ISR1 sets when the NAT7210 enters DTAS. If the Data

Accepted Holdoff On Device Trigger Active State (DHDT) bit (AUXRE[1]) is set, the

NAT7210 performs a DAC holdoff when the DET bit sets.

If the DAC Holdoff On Get (DHADT) bit (AUXRE[3]) is set, the NAT7210 performs a

DAC holdoff when the NAT7210 receives the GET command (whether or not the

NAT7210 is a GPIB Listener).

The DET bit can cause an interrupt if the Enable Interrupt On Device Execute Trigger

(DET IE) bit in IMR1 is set. DHADT and DHDT can cause an interrupt if the Enable

Interrupt On Command Pass Through (CPT IE) bit (IMR1) is set.

Device Clearing

As the IEEE 488.1 standard requires, the NAT7210 enters the Device Clear Active State

(DCAS) when the GPIB Controller sends the Device Clear (DCL) command or when the

NAT7210 is a GPIB Listener and the Controller sent the Selected Device Clear (SDC) command. The Device Clear (DEC) bit in ISR1 detects when the NAT7210 enters

DCAS. If the Data Accepted Holdoff On Device Clear Active State (DHDC) bit

(AUXRE[0]) is set, the NAT7210 performs a DAC holdoff when the DEC bit sets.

If the DAC Holdoff On DCL Or SDC (DHADC) bit (AUXRE[2]) is set, the NAT7210 performs a DAC holdoff when the NAT7210 receives the DCL or SDC command

(whether or not the NAT7210 is a GPIB Listener).

DEC can cause an interrupt if the Device Clear Interrupt Enable (DEC IE) bit in IMR1 is set. DHADC and DHDC can cause an interrupt if the CPT IE bit (IMR1) is set.

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Chapter 6

Controller Software Considerations

This chapter explains important system and GPIB Controller considerations. The information in this chapter applies only to applications in which the NAT7210 has GPIB

Controller capabilities. Because a GPIB Controller has Talker, Listener, and Controller capabilities, you should also refer to Chapter 5, Software Considerations.

This chapter, except where explicitly noted, assumes that the NAT7210 uses 7210-mode architecture and that the reader is familiar with the GPIB. For more information about

GPIB, refer to Appendix B, Introduction to the GPIB, and the IEEE 488.1 and

IEEE 488.2 standard.

System Controller Considerations

In a GPIB system, only one device may be the System Controller. The System Controller drives the GPIB REN and IFC signals true or false. The System Controller becomes the

Active Controller by asserting IFC.

Becoming System Controller

Complete the following steps to make a device become the System Controller:

1. Enable the external GPIB transceivers to drive the GPIB IFC and REN signals. In a typical system, a 75162-type transceiver drives these signals. In such a system, you assert the SC pin of the 75162 to enable the GPIB transceiver to drive the GPIB IFC and REN signals.

The NAT7210 does not directly drive the 75162 SC pin. The SC pin should be driven with circuitry that is external to the NAT7210. See the Interfacing to

Common GPIB Transceivers section in Chapter 7, Hardware Considerations .

2. Write the sic auxiliary command to the AUXMR to assert the GPIB IFC signal. The

IFC message initializes the GPIB interface functions of all devices on the bus. The sic command also causes the NAT7210 to become CIC and to assert the GPIB ATN signal.

3. Wait at least 100

µ s. The IEEE 488.1 standard requires that IFC be asserted for at least 100

µ s.

4. Write the ~sic auxiliary command to the AUXMR in order to unassert the GPIB IFC signal.

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Other System Controller Capabilities: Setting and Clearing REN

The System Controller can assert and unassert the GPIB REN signal. The control program issues the sre and ~sre auxiliary commands to set and clear REN. The control program must guarantee that the NAT7210 never unasserts the REN signal for less than

100

µ s.

Disabling System Controller Capabilities

Complete the following steps to disable the System Controller capabilities of the

NAT7210:

1. Write the ~rsc auxiliary command to the AUXMR.

2. Disable the external GPIB transceivers from driving the GPIB IFC and REN signals.

In a system that uses a 75162-type transceiver, you unassert the SC pin of the 75162 to enable the GPIB transceiver to receive the GPIB IFC and REN signals.

GPIB Controller Considerations

Three Basic Controller States

The IEEE 488.1 Controller function has many states, but for clarity, this manual groups them into three basic Controller function states: Idle Controller State, Active Controller

State, and Standby Controller State. See Figure 6-1.

pon +

IFC & ~rsc

Idle sic+

"Receive Control"

"Pass Control"

Active

CIC

ATN gts tca + tcs

Standby

CIC

Figure 6-1. Basic Controller States

Idle Controller State

In the Idle Controller State, the NAT7210 is not CIC and does not drive the ATN signal.

The NAT7210 can, however, send and receive data bytes in the Idle Controller State if the device that is CIC addresses the NAT7210 to talk or listen.

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Chapter 6 Controller Software Considerations

Only one device may be CIC at a time. Therefore, every GPIB device except the CIC must be in the Idle Controller State. In Talk-Only and Listen-Only applications, no device is CIC.

The NAT7210 enters the Idle Controller State if the pon message is true or if another device asserts the GPIB IFC message.

Active Controller State

In the Active Controller State, the NAT7210 is CIC and drives the ATN signal asserted.

As an Active Controller, the NAT7210 can send remote multiline messages (commands such as Untalk) and conduct serial and parallel polls. No devices can send or receive data bytes when the NAT7210 is the Active Controller.

Standby Controller State

In the Standby Controller State, the NAT7210 is CIC and drives the ATN signal unasserted. As a Standby Controller, the NAT7210 can send and receive data bytes if it addresses itself to talk or listen.

Determining the Basic Controller State

Read the ADSR and examine the CIC and ATN* bits (ADSR[7] and ADSR[6]). Read

Table 6-1 to determine the Basic Controller State.

Table 6-1. Basic Controller State

CIC (ADSR[7]) ATN* (ADSR[6])

0 X

1

1

0

1

Basic Controller State

Idle Controller

Active Controller

Standby Controller

Changing Controller States

Idle State to Active State: Becoming CIC

When the NAT7210 becomes System Controller (by issuing the sic command), the

NAT7210 exits the Idle Controller State and enters the Active Controller State. The

NAT7210 also enters the Active Controller State if another CIC passes control to it.

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The NAT7210 receives control from another CIC when the following events occur:

1. The current CIC sends the GPIB talk address (MTA) of the NAT7210. The

NAT7210 enters the GPIB Talker Addressed State (TADS) and sets the TA bit in the

ADSR.

2. The current CIC sends the GPIB Take Control (TCT) message to the NAT7210.

3. The current CIC sees that the GPIB handshake completes. The device that sent the

TCT message becomes an Idle Controller and stops driving ATN.

4. When ATN unasserts, the NAT7210 becomes the Active Controller and asserts

ATN. The NAT7210 sets the CIC bit in the ADSR and the CO bit in the ISR2.

Active State to Standby State

Complete the following steps to make the NAT7210 exit the Active Controller State and enter the Standby Controller State:

1. Complete any necessary addressing. In most cases, you address the NAT7210 to be a Talker or a Listener before the NAT7210 becomes the Standby Controller.

2. Wait until the CO bit in ISR2 is set in order to guarantee that the NAT7210 is the

Active Controller and that no parallel poll or command transfer is in progress.

3. Write the Go To Standby (gts) auxiliary command to the AUXMR.

Standby State to Active State

Complete the following steps to make the NAT7210 exit the Standby Controller State and enter the Active Controller State:

1. Wait for the chip to finish transferring bytes as a Talker or a Listener. Use the

SYNC bit to determine when the GPIB is synchronized.

2. Write the Take Control Asynchronously (tca) or Take Control Synchronously (tcs) auxiliary command to the AUXMR.

3. Wait for the CO bit to set. The CO bit sets when the NAT7210 becomes the Active

Controller.

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Chapter 6 Controller Software Considerations

Active State to Idle State: Passing Control

The NAT7210 exits the Active Controller State and enters the Idle Controller State by passing control to another device. Complete the following steps to pass control to another device:

1. Send the device’s talk address (its MTA) across the GPIB.

2. Send the TCT command.

The NAT7210 enters the Idle Controller State and unasserts ATN when the device accepts the TCT command.

Sending Remote Multiline Messages (Commands)

Complete the following steps to send commands (GPIB interface messages) to devices in your system:

1. Be sure that NTNL = 1 (AUXRG[3]). NTNL prevents the NAT7210 from sourcing commands if there are no listening devices in the system.

2. Make the NAT7210 become the Active Controller.

3. Wait for the CO bit to set.

4. Perform the following actions for each command that is sent:

• Write the command byte to the CDOR.

• Wait for either the CO bit (ISR2[3]) or the ERR (ISR1[2]) bit to set. CO indicates that all devices in the system have accepted the command. ERR indicates that no properly operating GPIB devices are in the system.

The host interface can either poll the CO and ERR bits or configure the NAT7210 to interrupt on these conditions by setting CO IE and ERR IE.

If the ERR bit sets, clear any byte that might be in the CDOR by issuing the nbaf auxiliary command, then clear the ERR bit by issuing the ClearERR auxiliary command.

Normally, command strings are short and DMA is not used.

Polling: Obtaining Status from Devices

According to the IEEE 488.1 standard, the CIC obtains status from devices by using two methods: Parallel Polls and Serial Polls. A CIC can serial poll only one device at a time.

The device responds by sending back a status byte to the CIC. All system devices can respond to a parallel poll simultaneously. However, each device can send only one bit of status to the CIC.

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Any device can assert the GPIB SRQ signal to indicate that its status has changed. The

CIC can poll devices at any time; however, the CIC does not generally poll devices unless

SRQ is asserted.

Conducting Serial Polls

The NAT7210, as a CIC, can serial poll other devices as described in the IEEE 488.1

standard. Complete the following steps to conduct a serial poll:

1. Make the NAT7210 become the Active Controller.

2. Send the UNT and UNL commands to unaddress all devices.

3. Make the device that will be serial polled an Addressed Talker. To make the device a Talker, send the MTA command and—if the device uses secondary addressing— the MSA command of the device.

4. Configure the NAT7210 to be a Listener.

5. Send the SPE command.

6. Make the NAT7210 become a Standby Controller. (See the Changing Controller

States section, which is located earlier in this chapter.)

The device then sources its status byte. The NAT7210 should read this byte from the

DIR like it would read any other data transfer from the device. After it has read the status byte, make the NAT7210 become the Active Controller again, then send the SPD command.

Configuring Devices for Parallel Polls

If the NAT7210 is the Controller, complete the following steps to use the NAT7210 to remotely configure other devices to respond to parallel polls:

1. Place the NAT7210 in the Active Controller State.

2. Send the GPIB UNL (Unlisten) message to unaddress all GPIB Listeners.

3. Address a device to Listen by sending the MLA command and—if the device uses secondary addressing—the MSA command of the device.

4. Send the GPIB Parallel Poll Configure command (PPC).

5. Send the PPE message for that device. (See the Determining the PPE Message section in Appendix B, Introduction to the GPIB.)

6.

Repeat steps 2 through 5 for each device that you will configure.

To disable a device from responding to parallel polls, repeat steps 1 through 3, then send the GPIB Parallel Poll Disable (PPD) command.

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Chapter 6 Controller Software Considerations

Conducting Parallel Polls

The NAT7210, as a CIC, can parallel poll other devices by using the rpp auxiliary command or the RPP2 bit.

The rpp Auxiliary Command

In most applications, this method is easier to implement than the RPP2 method.

Complete the following steps to conduct a parallel poll that uses the rpp auxiliary command:

1. Make the NAT7210 become the Active Controller.

2. Issue the rpp auxiliary command.

3. Wait until the CO bit (ISR2[3]) sets.

4. Read the CPTR to obtain the parallel poll response.

The NAT7210 stops conducting the parallel poll 2

µ s (or longer) after you issue the rpp command. The CO bit sets when the NAT7210 stops conducting the parallel poll after you issue the rpp command.

The RPP2 Bit

By using the RPP2 bit, you can control the duration of a parallel poll in software.

Complete the following steps to conduct a parallel poll that uses the RPP2 bit:

1. Make the NAT7210 become the Active Controller.

2. Set the RPP2 bit.

3. Wait for at least 2

µ s.

4. Read the CPTR to obtain the parallel poll response.

5. Clear the RPP2 bit.

Note: For more information on parallel polls, see the Parallel Polling section in

Appendix B, Introduction to the GPIB.

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Chapter 7

Hardware Considerations

This chapter explains important NAT7210 hardware-interfacing considerations, including a description of the pins.

Pin Descriptions

GPIB Transceiver Controls

T/R1

T/R1 asserts when the NAT7210 drives the GPIB DIO signals. The NAT7210 drives the

DIO signals when it is responding to a parallel poll or when it is sourcing data bytes, command bytes, or status bytes. T/R1 can be connected directly to the TE inputs of

75160 and 75162 GPIB transceivers.

T/R1 = (PPAS & ~CIC) + ~SIDS

T/R2 and T/R3

Four internal NAT7210 signals—EOIOE, TRIG, CIC, and PE—can drive the T/R2 and

T/R3 signals. (EOIOE, TRIG, CIC, and PE are described in the following sections.) The

TRM[1–0] bits in the ADMR determine which internal signals drive T/R2 and T/R3. In applications that use 75160 and 75162 transceivers, the TRM[1–0] bits should both be set so that the CIC signal drives T/R2 and the PE signal drives T/R3.

CIC Internal Signal

CIC asserts when the NAT7210 is an Active or Standby Controller. CIC unasserts when the NAT7210 is an Idle Controller.

The NAT7210 is Controller-in-Change when it is the

Active or Standby Controller.

When the NAT7210 is the Active Controller, it asserts the IEEE 488 ATN* signal. As an

Active Controller, the NAT7210 can send remote multiline messages (commands) and conduct serial and parallel polls.

When the NAT7210 is the Standby Controller, it does not assert the IEEE 488 ATN* signal. When the NAT7210 is the Standby Controller, the IEEE 488 Addressed Talker can send data to the IEEE 488 Addressed Listener.

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The CIC signal can be read as bit 7 of the Address Status Register (ADSR[7]) in 7210 mode.

Referring to the IEEE 488.1 Controller function:

CIC = ~(CIDS + CADS)

PE Internal Signal

PE asserts when the NAT7210 is not responding to a parallel poll. When the NAT7210 is responding to parallel polls, the GPIB transceivers should drive the GPIB DIO signals with open-collector drivers.

PE = ~(PPAS & ~CIC)

EOIOE Internal Signal

EOIOE asserts when the NAT7210 drives the GPIB EOI signal. The NAT7210 drives

EOI when it is sourcing data bytes, command bytes, or status bytes. The NAT7210 also drives EOI when it conducts a parallel poll.

EOIOE = TACS + SPAS + (CIC & ~CSBS)

TRIG Internal Signal

TRIG asserts when the NAT7210 is in the IEEE 488 Device Trigger Active State

(DTAS). The NAT7210 enters the DTAS when it is an Addressed Listener and is receiving the Group Execute Trigger (GET) command from the Active Controller.

The TRIG internal signal also pulses when the trig auxiliary command is written to the

Auxiliary Mode Register (AUXMR) in 7210 mode or when the fget auxiliary command is written to the Auxiliary Command Register (AUXCR) in 9914 mode.

GPIB Signal Pins

You can directly connect the NAT7210 GPIB signal pins (IFC, REN, SRQ, ATN, EOI,

DAV, NDAC, and NRFD) to a GPIB transceiver. One popular transceiver is the 75162

IC. If you use a 75162, you must connect the GPIB bus pins that are on the 75162

(usually pins 3 through 10 in a DIP package) to the GPIB connector and connect the

terminal pins (pins 13 through 20 in a DIP package) to the NAT7210. (See Figure 7-2.)

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Chapter 7 Hardware Considerations

GPIB Data Bus Pins

You can directly connect the NAT7210 GPIB data bus pins (DIO[8–1]) to a GPIB transceiver. One popular transceiver is the 75160 IC. If you use a 75160, you must connect the GPIB bus pins that are on the 75160 (usually pins 2 through 9 in a DIP package) to the GPIB connector and connect the terminal pins (pins 12 through 19 in a

DIP package) to the NAT7210.

CPU Register Control Pins

CS* and the CPU Address Bus

The address bus, RS(2–0), selects one NAT7210 internal register for reading and writing.

The Page-in condition also affects which register RS(2–0) selects. See The Page-In State section in Chapter 3, 7210-Mode Interface Registers.

The NAT7210 ignores RS(2–0) if the host interface asserts the DACK* pin or if the host interface does not assert CS*.

RD*/WR*

Asserting the RD* pin enables the CPU or DMA Controller to read a NAT7210 register.

Some read accesses also have other effects on the NAT7210. For example, if the

SISB = 0, reading ISR1 clears the bits in ISR1.

Asserting the WR* pin enables the CPU or DMA Controller to write to a NAT7210 register. Some writable registers are not storage registers. For example, writing certain values to the AUXMR forces internal signals to pulse true.

CPU Data Bus

The bidirectional CPU Data bus D(7–0) transfers data, commands, and status between the

CPU and the NAT7210. D7 is the most significant bit of the NAT7210 8-bit CPU data bus. D0 is the least significant bit.

DMA Pins

DRQ

When the DMAI bit is set, DRQ asserts when the NAT7210, as a Listener, accepts a byte from the GPIB. DRQ does not assert if the NAT7210 is in continuous mode (see the

Acceptor Handshake Holdoffs section in Chapter 5, Software Considerations.) DRQ unasserts when the host interface reads the GPIB data byte from the DIR.

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When the DMAO bit is set, DRQ asserts when the NAT7210 is a Talker and the CDOR is empty. DRQ unasserts when the host interface writes a byte to the CDOR.

DRQ unasserts when the host interface asserts the DACK* pin. However, if the host interface does not read DIR (if DMAI = 1) or write to the CDOR (if DMAO=1), DRQ reasserts when DACK* unasserts.

DRQ is an output-only pin. If the application does not require DMA, you can leave DRQ unconnected.

DACK*

Asserting DACK* enables accesses to the CDOR (for DMA writes) and the DIR (for

DMA reads). Asserting DACK* also causes the DRQ pin to unassert. The NAT7210 ignores the CS* and RS(2–0) pins when DACK* is asserted.

The DACK* pin is an active low input-only pin with an internal pull-up resistor. If the application does not require DMA, you can connect DACK* to Vcc or leave DACK* unconnected.

Other Pins

INT

The Interrupt pin asserts when the INT bit in ISR2 is true. If INV = 1 (AUXRB[3]), the

INTR pin is active low. If INV = 0, the INTR pin is active high.

Several of the interrupting conditions depend on the CLK signal. For these interrupts, the delay between an event occurring and the related interrupt asserting depends on the CLK frequency.

RESET

Asserting RESET places the NAT7210 in 7210 mode. (See Figure 2-2, Changing the

NAT7210 Mode , in Chapter 2, NAT7210 Architecture.) Asserting RESET initializes all

GPIB interface functions. The NAT7210 asserts the local pon message until the control software issues the immediate execute pon auxiliary command. See the Auxiliary Mode

Register (AUXMR) section in Chapter 3, 7210-Mode Interface Registers.

The RESET signal is asynchronous to the CLK signal.

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Chapter 7 Hardware Considerations

CLK

The following list summarizes the CLK signal requirements for the NAT7210:

• The CLK pin is a TTL input.

• The minimum CLK frequency is 1 MHz.

• The NAT7210 does not function properly without a CLK signal.

• The rising and falling edges of the CLK signal must be monotonic.

• The minimum pulse width of the CLK signal high or low (Tpw in Figure 7-1) is

15 ns.

• National Instruments does not specify the maximum rise or fall time of the CLK signal ( Trf in Figure 7-1). Using a signal with unusually slow rise and fall times can adversely affect power consumption.

2.0V

0.8V

T pw

T rf

T rf

T r f

= rise or fall time

T pw

= pulse width (high or low)

T pw

Figure 7-1. CLK Signal Timing Diagram

© National Instruments Corp.

7-5 NAT7210 Reference Manual

Hardware Considerations Chapter 7

Interfacing to Common GPIB Transceivers

Figure 7-2 shows how to interface the NAT7210 to the 75160 and 75162 transceivers.

The SC signal can be driven by a register external to the NAT7210.

Figure 7-2. Interfacing the NAT7210 to the 75160 and 75162 Transceivers

NAT7210 Reference Manual 7-6 © National Instruments Corp.

Appendix A

Common Questions

This appendix lists common questions and answers.

If there are two devices, one using a NAT7210 with a 16 MHz clock frequency, and another using the NAT7210 with a 5 MHz clock frequency, will the one with the higher clock frequency communicate faster?

Yes, but not much faster. Depending on the application, the 16 MHz chip might increase throughput by up to 15%. It will not make your throughput 3 times faster.

When the NAT7210 sends a data byte, it delays for a time “T1.” The longer the T1 delay is, the longer it takes to transfer a byte.

For example, suppose you program the NAT7210 to use a T1 delay of 500 ns. For a 5

MHz clock, T1 would have to be at least 600 ns, because it must be some multiple of the clock period. On average, the actual delay would be about 700 ns, because you must add about 0.5 of a clock period for synchronizing delays. For a 16 MHz clock, 500 ns is an exact multiple of the clock period, so the average T1 delay would be close to 500 ns + 0.5

clock periods—about 531 ns.

Therefore, the T1 delay for a 16 MHz clock might be 169 ns shorter (on average) than that of a 5 MHz clock. The faster clock saves 169 ns of time on every bite. If your throughput is 10 kBytes/s, this will not be a noticeable time difference. However, if your throughput is 800 kBytes/s, the difference will be noticeable.

Although the faster clock frequencies don’t improve throughput very much, the

NAT7210 is designed have high throughput at any clock frequency.

What should I do if I am using a clock that uses fractional output frequencies?

Simply round up to the next highest integer. Examples follow:

Fractional Output Frequency

1.2

3.35

3.6864

ICR Value

2

4

4

You can write any integer higher than the actual input frequency to the ICR. Even if you do not write any value to the ICR, the NAT7210 will still work with actual frequencies of

1.2, 3.35, 3.6864 MHz, because it defaults to 8 MHz.

© National Instruments Corp.

A-1 NAT7210 Reference Manual

Common Questions Appendix A

The NAT7210 uses the input clock to generate certain delays, such as the T1 delay (see previous question). For example, suppose you program the NAT7210 to use a 2

µ s nominal T1 delay. The NAT7210 examines the ICR register to determine how many clock periods to wait. If the ICR contains 2, the NAT7210 assumes that the input frequency is 2 MHz and the clock period is 500 ns. For a delay of 2

µ s, the NAT7210 calculates that it will need to wait:

2

µ s

÷

500 ns = 4 clock periods

If the ICR contains 2, the NAT7210 waits for 4 clock periods regardless of the actual clock frequency. If the actual frequency is 1.2 MHz (with a clock period of 833 ns), the actual delay will be:

4 clock periods x 833 ns = 3.33

µ s

3.33

µ s is longer than the nominal 2

µ s, but this is acceptable. The T1 delay can be longer than 2

µ s.

NAT7210 Reference Manual A-2 © National Instruments Corp.

Appendix B

Introduction to the GPIB

This appendix discusses the history of the GPIB, GPIB hardware configurations, and serial polling.

History of the GPIB

Hewlett-Packard developed the original GPIB (and called it the HP-IB) in the late 1960s.

Hewlett-Packard developed its HB-IB to connect and control programmable instruments that Hewlett-Packard had manufactured. The introduction of digital controllers and programmable test equipment created the need for a standard, high-speed interface that would permit communication between instruments and controllers from various vendors.

In 1975, the IEEE published ANSI/IEEE Standard 488-1975, IEEE Standard Digital

Interface for Programmable Instrumentation, which contained the electrical, mechanical, and functional specifications of an interfacing system. The original IEEE 488-1975 was revised in 1978 primarily for editorial clarification and addendum. This bus is now used worldwide and is known by three names:

• General Purpose Interface Bus (GPIB)

• Hewlett-Packard Interface Bus (HP-IB)

• IEEE 488 Bus

Because the original IEEE 488 document contained no guidelines for preferred syntax and format conventions, work continued on the specification to enhance system compatibility and configurability among test systems. This work resulted in a supplement standard—IEEE 488.2, Codes, Formats, Protocols, and Common

Commands —that you use with IEEE 488 (which was renamed IEEE 488.1).

IEEE 488.2 does not replace IEEE 488.1. Many devices still conform only to

IEEE 488.1. IEEE 488.2 builds on IEEE 488.1 by defining a minimum set of device interface capabilities, a common set of data codes and formats, a device message protocol, a generic set of commonly needed device commands, and a new status reporting model.

In 1990, a consortium of test and measurement companies developed the Standard

Commands for Programmable Instrumentation (SCPI) document. SCPI defines specific commands that each instrument class (which usually includes instruments from various vendors) must obey. Thus, SCPI guarantees complete system compatibility and configurability among these instruments. You no longer need to learn a different command set for each instrument, and you can easily replace an instrument from one vendor with an instrument from another.

© National Instruments Corp.

B-1 NAT7210 Reference Manual

Introduction to the GPIB Appendix B

The IEEE 488.1 Specification

The GPIB is a digital, 8-bit, parallel communications interface with maximum data transfer rates over 1 MB/s. The bus supports one system controller—usually a computer—and up to 14 additional instruments. Because the GPIB is an 8-bit parallel interface with fast data transfer rates, it has gained popularity in other applications such as intercomputer communication and peripheral control.

IEEE 488.2 and SCPI Specifications

Although IEEE 488.1 eliminated the need to find the right type of connector and determine which signal line was connected to which pin, it did not solve other problems.

More than 10 years after the release of IEEE 488.1, IEEE 488.2 and SCPI solved these problems.

Problems with IEEE 488.1 Compatible Devices

Users of IEEE 488.1 compatible devices encountered the following problems:

• No common method for performing operations existed: In a system with two different meters, one meter could require a command to take a reading while the other could take a reading without a command.

• No common data format existed among communicating devices: Two communicating devices used two different formats to represent the same number.

• No common command set existed: Two devices performed identical functions, but used completely different device-dependent data messages.

• Status reporting was unique to each device: Each device reported its status information in a different format.

The IEEE 488.2 Solution

The IEEE 488.2 standard eliminates the IEEE 488.1 problems through the following solutions:

• IEEE 488.2 contains a minimum set of required device interface capabilities.

• IEEE 488.2 specifies a way of presenting data through data formats and codes.

• IEEE 488.2 defines a specific protocol for sending device messages and the syntax for multiple commands in a single string.

NAT7210 Reference Manual B-2 © National Instruments Corp.

Appendix B Introduction to the GPIB

• IEEE 488.2 contains a common command set.

• IEEE 488.2 contains a standard status reporting model.

SCPI Specification

The SCPI specification expands the IEEE 488.2 common command set by defining a single, comprehensive command set that is suitable for all instruments. For example, all

SCPI-compatible voltmeters, regardless of manufacturer or model, respond to the same command for reading AC voltage. Their response format is also the same.

SCPI embraces many of the commands and protocols that the hardware-independent portion of the IEEE 488.2 standard defines. Figure B-1 illustrates the structure of the

GPIB standards.

Command

Hierarchy

SCPI

Standard Response

Format

Standard Program

Command Set

Software/

Firmware

IEEE 488.2

Common Commands

Syntax/Data Structures

Hardware

IEEE 488.1

Handshaking/Control

Mechanical/Electrical Standards

Figure B-1. Structure of the GPIB Standards

© National Instruments Corp.

B-3 NAT7210 Reference Manual

Introduction to the GPIB Appendix B

The combination of IEEE 488.2 and SCPI leads to greater productivity by featuring software command standards and instant interchangeability. Rather than learning a different command set for each instrument, you can focus on solving measurement problems.

Although you can mix SCPI and non-SCPI instruments in a system, your complete system must adhere to IEEE 488.2 for you to fully benefit from these standards.

See Appendix C, Standard Commands for Programmable Instruments (SCPI), for more information.

GPIB Hardware Configuration

A GPIB hardware setup consists of two or more GPIB devices (instruments and/or interface boards) that are connected by a GPIB cable. The cable assembly consists of a shielded 24-conductor cable with a plug and a receptacle (male/female) connector at each end. With this design, you can link devices in a linear configuration, a star configuration, or a combination of these two configurations (see Figures B-2 and B-3).

NAT7210 Reference Manual B-4 © National Instruments Corp.

Appendix B Introduction to the GPIB

Device A

Device B

Device C

Figure B-2. Linear Configuration

© National Instruments Corp.

B-5 NAT7210 Reference Manual

Introduction to the GPIB

Device A

Device B Device C

Figure B-3. Star Configuration

Device D

Appendix B

NAT7210 Reference Manual B-6 © National Instruments Corp.

Appendix B Introduction to the GPIB

GPIB Signals and Lines

The GPIB has 16 signal lines and 8 ground return or shield drain lines (see Figure B-4).

All GPIB devices share the same 24 bus lines. The 16 signal lines fall into three groups:

• Eight data lines.

• Five interface management lines.

• Three handshake lines.

DIO1

DIO2

DIO3

DIO4

EOI

DAV

NRFD

NDAC

IFC

SRQ

ATN

SHIELD

17

18

19

20

21

22

23

24

13

14

15

16

8

9

10

11

12

5

6

7

3

4

1

2

DIO5

DIO6

DIO7

DIO8

REN

GND (TW PAIR W/DAV)

GND (TW PAIR W/NRFD)

GND (TW PAIR W/NDAC)

GND (TW PAIR W/IFC)

GND (TW PAIR W/SRQ)

GND (TW PAIR W/ATN)

SIGNAL GROUND

Figure B-4. GPIB Connector and Pin Assignments

Data Lines

The eight data lines, DIO1 through DIO8, carry the command and data messages on the

GPIB. All commands and most data use the 7-bit ASCII or ISO code set; thus, the eighth bit, DIO8, is not used or is used for parity.

© National Instruments Corp.

B-7 NAT7210 Reference Manual

Introduction to the GPIB

Interface Management Lines

The following lines manage the flow of information across the GPIB:

• Interface Clear (IFC)

• Attention (ATN)

• Remote Enable (REN)

• End-or-Identify (EOI)

• Service Request (SRQ)

Appendix B

Interface Clear (IFC)

Only the System Controller can control the IFC line. The System Controller uses IFC to take control of the bus asynchronously. This action must initially be done to establish

Controller status.

The IFC line is the master reset of the GPIB. When it is asserted, all devices return to a known quiescent state.

Interface Clear

(IFC)

• Places all devices into quiescent state.

• Is asserted by System Controller.

– 300.0005 V

NAT7210 Reference Manual B-8 © National Instruments Corp.

Appendix B Introduction to the GPIB

Attention (ATN)

When the ATN line is asserted, all devices become Listeners and participate in the communication. ATN signifies that a GPIB command message or data message is present on the data lines. When ATN is unasserted, information on the bus is interpreted as a data message. When ATN is asserted, information on the bus is interpreted as a

command message.

Attention

(ATN)

• Notifies devices of current data type.

• Is asserted by Controller-In-Charge.

Controller

ATN asserted

Command messages

Talker

ATN unasserted

Data messages

– 300.0005 V

All

Devices

Listener(s)

© National Instruments Corp.

B-9 NAT7210 Reference Manual

Introduction to the GPIB Appendix B

Remote Enable (REN)

The System Controller uses the REN line to put devices into a remote state. Each device has its own remote/local state capabilities. The IEEE 488 standard requires a device to go into a remote programming state whenever the REN line is asserted and addressed to listen.

Remote Enable

(REN)

• Enables devices for remote programming.

• Is asserted by System Controller.

– 300.0005 V

End-or-Identify (EOI)

Some devices terminate their output data by using the EOI line. A Talker asserts EOI along with the last byte of data. A Listener stops reading data when the EOI is asserted.

More details of transfer termination are presented later. This line is also used in parallel polling, which will be discussed later.

End Or Identify

(EOI)

• Signals end of data.

• Signals the execution of a Parallel Poll.

• Is asserted by current Talker.

– 300.0005 V

NAT7210 Reference Manual B-10 © National Instruments Corp.

Appendix B Introduction to the GPIB

Service Request (SRQ)

A device asserts the SRQ line at any time in order to notify the CIC that it needs service.

The SRQ line remains asserted until the device is serial polled. The Controller must monitor SRQ, poll the device, and determine the type of service the device needs.

Service Request

(SRQ)

• Alerts Controller that service is needed.

• Is asserted by Non-Controller.

– 300.0005 V

Handshake Lines

Three lines asynchronously control the transfer of message bytes among devices:

• Not Ready For Data (NRFD)

• Not Data Accepted (NDAC)

• Data Valid (DAV)

The GPIB uses a three-wire interlocking handshake scheme. This handshake scheme guarantees that message bytes on the data lines are sent and received without transmission error.

Not Ready For Data (NRFD)

The NRFD line indicates whether a device is ready to receive a data byte. When a

Controller is sending commands, all devices drive NRFD. When a Talker is sending data messages, only Listeners drive NRFD.

© National Instruments Corp.

B-11 NAT7210 Reference Manual

Introduction to the GPIB Appendix B

Not Data Accepted (NDAC)

The NDAC line indicates whether a device has accepted a data byte. When a Controller is sending commands, all devices drive NRFD. When a Talker is sending data messages, only Listeners drive NRFD.

Note: This handshake scheme limits the transfer rate on the GPIB to that of the slowest active Listener. The transfer rate is limited because a Talker waits until all Listeners are ready (that is, NRFD is false) before sending data and waits for all Listeners to accept data (that is, NDAC is false) before transferring more data. Therefore, the slowest device dictates the maximum

GPIB transfer rate.

Data Valid (DAV)

The DAV line indicates whether signals on the data lines are stable (valid) and whether devices can safely accept the signals. When the Controller sends commands, it controls

DAV, and when the Talker sends data messages, it controls DAV.

Figure B-5 illustrates the three-wire handshake process.

The GPIB uses negative logic with standard TTL voltage levels:

Logic Level Voltage Level

0 – false (unasserted)

1 – true (asserted)

> +2.0 V (high)

< +0.8 V (low)

{

DAV

Data

NRFD {

NDAC

1

Ready

2

Data

1

New Data is Valid

3

Don't Send More Yet

4

Data Not Valid Anymore

6

2

Transfer

Begins

5

Byte

Accepted

7

Data

Transfer

Ends

Ready

Again

Figure B-5. Three-Wire Handshake Process

NAT7210 Reference Manual B-12 © National Instruments Corp.

Appendix B Introduction to the GPIB

Three-Wire Handshake Process

GPIB devices use the three-wire handshake process to transfer information. The threewire handshake process is identical for command and data transfers. During command transfers, the Controller drives the DIO and DAV lines; all devices drive the NRFD and

NDAC lines. During data transfers, the Talker drives the DIO and DAV lines; all

Listeners drive the NRFD and NDAC lines.

Devices drive the NDAC and NRFD lines with open-collector drivers, so if any device drives NDAC (or NRFD) to a low voltage level, the signal is logically asserted (true).

If no device drives NDAC (or NRFD) to a low voltage level, the signal floats to a high voltage level; thus, the signal is logically unasserted (false).

The following actions occur during the three-wire handshake process (refer to

Figure B-5):

1.

The Talker (or Controller) places data on the DIO lines and waits at least T1 seconds.

2.

After the T1 delay, the Talker waits until the Listener unasserts NRFD. NRFD unasserted (not Not-Ready-For Data) indicates that the Listener can receive the data byte.

3.

The Talker asserts DAV to indicate that new data is valid on the DIO lines.

4.

The Listener asserts NRFD to signal a Not Ready Status (Don’t Send More Yet).

5.

When the Listener accepts the current byte (by placing it in some internal buffer or by otherwise processing it), the Listener unasserts NDAC.

6.

The Talker unasserts DAV.

7.

The Listener asserts NDAC, then the Talker executes step 1 to begin transferring the next byte.

Physical and Electrical Specifications

To achieve the GPIB’s high data transfer rate, you must limit the physical distance between devices and the number of devices on the bus. This limitation is necessary because the GPIB is a transmission line system. Any distance beyond the maximum allowable cable length, as well as any excess GPIB device loads, can surpass interface circuit drive capability.

The IEEE 488 standard dictates the following limits:

• The total length of all cables is less than or equal to 2 m times the number of connected devices—up to a total of 20 m.

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B-13 NAT7210 Reference Manual

Introduction to the GPIB Appendix B

• No more than 15 devices are connected to each bus, with at least two-thirds of the devices powered on.

If you must exceed these limits, you can purchase bus extenders and expanders.

Controllers, Talkers, and Listeners

All buses operate under rules that ensure that data passes reliably and that instruments do not use the bus simultaneously. To determine which device has active control of the bus, devices are categorized as Controllers, Talkers , or Listeners. Whenever two devices communicate, one device will be a Talker and the other will be a Listener. In addition, one device will always be a Controller.

Controllers

Most GPIB systems consist of one computer and a variety of instruments. In this type of system, the computer is typically the System Controller. If multiple computers are connected, several devices can have Controller capability, but only one Controller is active, or Controller-In-Charge (CIC), at a time. Active control can pass from the current CIC to an idle Controller.

For each GPIB system, you must define a System Controller. You usually define the

System Controller through jumper settings on the GPIB interface board, a software configuration file, or both. Only one device on the bus, the System Controller, can make itself the CIC.

The four primary responsibilities of a Controller are the following:

• Defining the communication links.

• Responding to devices requesting service.

• Sending GPIB commands.

• Passing/receiving control.

NAT7210 Reference Manual B-14 © National Instruments Corp.

Appendix B Introduction to the GPIB

Talkers and Listeners

You can set most GPIB devices to be either Talkers or Listeners. However, some devices only talk or only listen. Each device accepts its own command set and has its own method of terminating data strings. Talkers and Listeners have the following properties:

• Talkers

– Are instructed by the Controller to talk.

– Place data on the GPIB.

– Permit only one device to talk at a time.

• Listeners

– Are instructed by the Controller to listen.

– Read data that the Talker places on the GPIB.

– Permit several devices to be Listeners simultaneously.

You can compare GPIB operation to a classroom. The instructor (Controller) controls the communication of data between the students (devices). The instructor decides who talks and who listens. On the GPIB, a device cannot talk or listen unless the Controller explicitly tells it to do so.

Figure B-6 shows a system setup example.

© National Instruments Corp.

B-15 NAT7210 Reference Manual

Introduction to the GPIB

Controller

System Controller

GPIB

Multimeter

– 300.0005 V

Oscilloscope

Plotter

Figure B-6. System Setup Example

Appendix B

NAT7210 Reference Manual B-16 © National Instruments Corp.

Appendix B Introduction to the GPIB

Data and Command Messages

In a classroom, when the instructor tells the students who is the Talker and who are the

Listeners, his or her information is a command—not the actual data information that the instructor will send. On the GPIB, this distinction is not so intuitive. The bus management line, ATN, determines what type of message you are sending on the bus. If this line is unasserted, the information on the bus is a data message; if this line is asserted, the information is a command message from the Controller to all devices. The devices on the GPIB monitor the ATN line, determine the data type, and treat the data appropriately.

GPIB Addressing Protocol

In a classroom, an instructor either speaks to the entire class or to a particular student. To speak to a student, the instructor first addresses that student by name.

Addressing on the GPIB follows the same idea. Before any communication can take place on the bus, you must address the Talker and Listener. Before any data passes between devices, the Controller determines who talks and who listens.

In the classroom, we address people by their names. However, on the GPIB, each device

(including the Controller) has a unique primary GPIB address in the range of 0 to 30

(decimal). The Controller places a command message specifying the addresses of the

Talker and Listener devices on the bus.

The Controller sends a single byte (8 bits) of information for a Talker or Listener address command message. Address command messages have the following format:

Bit

Data

7 6 5 4

TA LA X

3 2 1 0

X X X X

Bits 0 through 4 contain the binary GPIB primary address of the device in communication, and either bit 5—Listener Address (LA)—or bit 6—Talker Address

(TA)—will be set if the device is a Talker or a Listener. Bit 7 is never used and is considered a don’t care bit. For simplicity, assume bit 7 is zero.

© National Instruments Corp.

B-17 NAT7210 Reference Manual

Introduction to the GPIB Appendix B

Consider an example in which a Controller at primary GPIB address 0 talks to a device at primary GPIB address 1. To establish the communication link, the Controller must send its GPIB talk address and the device’s listen address over the GPIB. In this example, these addresses are as follows:

Bit Patterns Sent to Set Up Talker

Bit pattern: 01000000

010 00000

Hexadecimal value:

TA ADR Talker's GPIB Address is 0

0100 0000

4 0 Hex 40 = ASCII "@"

Refer to the Multiline Interface Command Messages table (in Appendix C) and find the hex 40 location. On the same row under the Msg column, you see the message MTA0, which means My Talk Address 0. Hex 40 is the command message for setting device 0 to be a Talker.

Bit Patterns Sent to Set Up Listener

Bit pattern: 00100001

001 00001

LA ADR Listener's GPIB Address is 1

0010 0001 Hexadecimal value:

2 1 Hex 21 = ASCII "!"

Refer to the Multiline Interface Command Messages table and find the hex 21 location.

On the same row under the Msg column, you see the message MLA1, which means My

Listen Address 1 . Hex 21 is the command message for setting device 1 to be a Listener.

NAT7210 Reference Manual B-18 © National Instruments Corp.

Appendix B Introduction to the GPIB

Reading the Multiline Interface Command Messages Table

By using the Multiline Interface Command Messages table, you can understand how the

GPIB circuitry interprets the bit patterns to produce the proper message commands. The

Multiline Interface Command Messages table is organized into four groups of columns.

The left or first group of columns (hex 00–1F) represents the primary GPIB addresses.

Moving to the right to the next group of columns (hex 20–3F), you will find the corresponding listen addresses (MLA). The listen address of a device is formed by adding hex 20 to the GPIB primary address. Again, move right to the next group of columns (hex 40–5F) for the corresponding talk addresses (MTA). You form the talk address of a device by adding hex 40 to the GPIB primary address.

Secondary Addressing

A device can have a secondary address. A secondary address is in the range of 0 to 30 decimal (IE hex). To form a secondary address command (bit pattern), add 96 decimal

(60 hex) to the secondary address. You address a device with a secondary address by sending the primary GPIB address, then the corresponding secondary address. With secondary addressing, you can assign up to 961 talk and listen addresses. Most instruments do not use secondary addressing. In the Multiline Interface Command

Messages table, the group of columns on the right (hex 60–7F) represents the secondary

GPIB address commands.

Unaddressing Command Messages

The CIC uses two special command messages to clear the bus of Talkers and Listeners before assigning new Talkers and Listeners. These command messages are Untalk and

Unlisten. The Untalk (UNT) command (hex 5F (ASCII “_”)) unaddresses the current

Talker. The Untalk command is merely a command for convenience, because addressing one Talker automatically unaddresses all others. The Unlisten (UNL) command (hex 3F

(ASCII “?”)) unaddresses all current Listeners on the bus. You cannot unaddress only a single Listener if you have previously addressed several Listeners. You must use the

UNL command to guarantee that you address only desired Listeners.

Termination Methods

When devices send data over the GPIB, they use up to three different methods to signify the end of a data transfer. These methods are EOS, EOI, and the count method.

Termination methods in GPIB are necessary only for data messages, not for command messages.

© National Instruments Corp.

B-19 NAT7210 Reference Manual

Introduction to the GPIB Appendix B

EOS Method

The EOS method uses an EOS character, which signifies the termination of data that devices send on the GPIB. This EOS character can be any character. However, it is commonly a carriage return (hex 0D) or a line feed (hex 0A) that the Talker places as the last character in a data string. The Listener reads individual data bytes from the Talker until the Listener reads the EOS character. When the Listener reads the EOS character, it knows that there is no more data, so it completes the read operation.

You must configure the Talker and Listener to use the EOS method before the communication takes place. Many devices send specific EOS characters and look for specific characters from other devices, so it is important for you to read the documentation for all devices to see which termination method the devices use.

To use the EOS method in a classroom setting, the instructor and students would use a certain word to finish all communication within the classroom. As with the GPIB, the instructor and students would define this method and the word used before any communication took place. In the GPIB and in the classroom, the termination signal is sent by using the normal data path (data lines in GPIB, or speech in the classroom).

EOI Method

The EOI method uses the GPIB EOI line, which is separate from the eight data lines on the GPIB. In the EOI method, when the Talker sends the last byte of data in the transmission, it sets the EOI line high to specify that the byte is the last byte to be sent.

The Listener monitors the EOI line and recognizes when there is no more data. You must establish ahead of time whether the Talker will use the EOI method, so you can correctly configure the Listener to watch the EOI line.

Students could use the EOI method in the classroom: they would wave device cards in the air to signal when they have finished speaking. This form of communication is separate from the method of sending data (speech), but the other Listeners can monitor this communication while they receive data (hear the speech).

Count Method

The count method uses neither the EOI line nor the EOS character. In the count method, the device that receives information specifies the number of bytes to read. Through this method, a listening device reads a specified amount of data and prevents the talking device from sending more data. If you do not clear the remaining data from the bus, you can recover it later.

Students can use the count method in the classroom. Students count the words of someone who is talking. The Listener announces that he or she will listen to only a

NAT7210 Reference Manual B-20 © National Instruments Corp.

Appendix B Introduction to the GPIB specified number of words. Beyond this number of words, the Listener will not hear any further information from the Talker. If the Listener wants more information, he or she requests more words from the Talker.

Combinations of Termination Methods

You can use any combination of the three termination methods to terminate communication on the GPIB. For example, you can specify an EOS character and also use the EOI line method. In this case, when the end of the string is reached, the device sending the data will send an EOS character and assert the EOI line. When you use more than one method, the first termination method recognized causes the termination. In this example, the EOS character or EOI line causes termination, depending on which method the device recognizes first.

In general, when you use more than one termination method at a time, all methods are logically ORed together for a result. Therefore, if you use all three methods, the communication termination will take place if the device sees the EOS character, the system asserts the EOI line, or the count value has been reached.

Serial Polling

Servicing SRQs

In the classroom, an instructor is in charge of the class and controls activity. The GPIB works in a similar fashion: the Controller bus controls when tasks are performed. In the classroom, a student must have permission to speak, and on the GPIB, no device can communicate unless it is addressed to talk on the bus. A device may, however, need to communicate with the Controller before the Controller tells it to talk. In a classroom, students who have something to say usually raise their hands. On the GPIB, any device can assert the SRQ line, which is separate from the data lines. SRQ informs the

Controller that a device needs attention. The next section discusses how the SRQ line is asserted and how the device that asserts it is identified.

Serial Polling Devices

This section investigates how the GPIB handles the SRQ line. Remember the SRQ line purpose: signaling to the Controller that a device needs attention. When SRQ is asserted, it is the responsibility of the Controller to determine who requested service by checking all devices individually. Checking the devices individually is known as polling the devices. The Controller can poll devices in two ways: in serial or in parallel. This appendix discusses serial polling and parallel polling.

Serial polling obtains specific information from a device. When you serial poll, the

Controller sends a special command message—Serial Poll Enable (SPE)—to the device,

© National Instruments Corp.

B-21 NAT7210 Reference Manual

Introduction to the GPIB Appendix B directing it to return its serial poll status byte. The SPE message sets the IEEE 488.1

serial poll mode in the device, so when the device is addressed to talk, it returns a single

8-bit status byte. This serial poll status byte is different for each type of instrument; except for one bit, you must refer to the instrument user manual for information on the other bits. Bit 6 (hex 40) of any serial poll status byte indicates whether a device requested service by asserting the SRQ line. The device uses the other seven bits of the status byte to specify why it needs attention.

After the Controller reads the status byte, it sends another command message, Serial Poll

Disable (SPD), to the device. The SPD message terminates the serial poll mode, thus returning the device to its normal Talker/Listener state. Once a device requesting service is serial polled, it usually unasserts the SRQ line.

When a serial poll is conducted, the following sequence of events occurs:

System Controller GPIB Device

UNListen (UNL)

Device Listen Address

Serial Poll Enable (SPE)

Device Talk Address

Device as Listener

Generates Serial Poll Byte

Device Set as Talker

Read (IBRD) Serial Poll

Byte from Device

Serial Poll Disable (SPD)

UNTalk (UNT) All Devices

Serial Poll Byte Returned

Turns off Serial Poll Mode

Figure B-7. Events During a Serial Poll

NAT7210 Reference Manual B-22 © National Instruments Corp.

Appendix B Introduction to the GPIB

Status Byte Model for IEEE 488.1

IEEE 488.1 defines only bit 6, the RQS bit, of the serial poll status byte (see Table B-1).

If a device is requesting service, it sets RQS. The meaning of the remaining bits is device dependent.

Table B-1. IEEE 488.1 Standard Status Data Structure

7 RQS 5 4 3 2 1 0 Status Byte Register

ESR and SRE Registers

The IEEE 488.2 standard defines a set of commands for controlling the GPIB. The standard also defines a new method of working with the SRQ line on the GPIB. This section applies only to those GPIB devices that are IEEE 488.2 compatible. If a device is only IEEE 488.1 compatible, the previous section applies.

Status Byte Model for IEEE 488.2

IEEE 488.2 describes a scheme for status reporting. This scheme is required for all IEEE 488.2 instruments. With this scheme, the Controller can obtain status information for every instrument in the system. This scheme builds on and extends the

IEEE 488.1 status byte shown in Table B-1. Three bits of this status byte are defined.

The IEEE 488.2 standard defines the RQS bit like the IEEE 488.1 standard. IEEE 488.2

adds the Event Status Bit (ESB) and the Message Available (MAV) bit. The manufacturer defines other bits. The RQS bit indicates the device has requested service by asserting the SRQ line. The ESB indicates that one of the standard events defined in the Standard Event Status Register has occurred. By setting the corresponding bits in the

Standard Event Status Enable Register, you define which standard events will set the

ESB. The MAV bit indicates whether a message is available in the instrument output queue. By setting the corresponding bits in the Service Request Enable Register, you can configure an instrument to assert the SRQ line based on the bits of its status register.

IEEE 488.2 defines a dual role for the RQS bit. This bit is also known as the Master

Summary Status (MSS) bit. The MSS bit indicates whether there is at least one reason for the instrument to request service. The status of this bit is returned only in response to the status byte (STB) query; its status is not sent in response to a serial poll because this bit is not part of the IEEE 488.1 status byte (see Figure B-8).

© National Instruments Corp.

B-23 NAT7210 Reference Manual

Introduction to the GPIB Appendix B

Service

Request

Generation

7 6 5 4 3 2 1 0

&

&

&

&

&

&

&

&

7 6 5 4 3 2 1 0

Standard

Event Status Register

*ESR?

Queue

Not-Empty

Standard

Event Status Enable

Register

*ESE <NR f >

*ESE?

Output Queue

RQS

7 6

MSS

ESB MAV

3 2 1 0 read by Serial Poll

Status Byte Register read by *STB?

&

&

&

&

&

&

&

7 5 4 3 2 1 0

Service Request

Enable Register

*SRE <NR f >

*SRE?

Figure B-8. IEEE 488.2 Standard Status Structures

NAT7210 Reference Manual B-24 © National Instruments Corp.

Appendix B Introduction to the GPIB

Parallel Polling

Parallel polling is another way to get information from a device that requests service.

Parallel polling differs from serial polling in two ways: all configured devices are polled simultaneously (that is, in parallel) and a Controller initiates a parallel poll sequence (any device requests the initiation of a serial poll sequence).

Overview of Parallel Polls

A parallel poll is an exchange of messages between the Controller and other system devices. The Controller sends the IDY message true to the other devices; each device responds to the IDY message by sending one PPR message (PPR1, PPR2, PPR3, PPR4,

PPR5, PPR6, PPR7, or PPR8) to the Controller. Each device usually sends a different

PPR message. (See the Physical Representation of the PPR Message section in this chapter.) Each device can send its PPR message either true or false. See Figure B-9.

Controller

PPR1 = true

IDY

PPR4 = False

Device

Device

PPR6 = true

Device

Figure B-9. Example Exchange of Messages During a Parallel Poll

© National Instruments Corp.

B-25 NAT7210 Reference Manual

Introduction to the GPIB Appendix B

Determining the Value of the PPR Message

Each device examines its local ist message and its Sense bit (S) to determine whether it will send its PPR message true or false. Table B-2 illustrates how the ist message and the

Sense bit affect the value of the PPR message.

Table B-2. PPR Message Value ist Message Sense Bit (S) PPR Message Sent

0 (False) 0 True

0 (False)

1 (True)

1 (True)

1

0

1

False

False

True

The ist message usually reflects a bit of status information about the device. For example, when the device has taken a measurement, it can assert its local ist message.

The Sense bit is part of the configuration of a device. Each device has an independent

Sense bit.

The meaning of the PPR message and the local ist message is device dependent.

Configuring a Device for Parallel Polls

To configure a device to respond to parallel polls, you must supply the device with two pieces of data:

• The PPR message that the device should send to the Controller (PPR1, PPR2, . . , or

PPR8)

• The value of the Sense bit of the device.

You can configure devices locally or remotely. You locally configure (Parallel Poll function subset PP2) a device by setting knobs or switches on the front panel of the device (or by physically manipulating the device in some other way). You remotely configure (Parallel Poll function subset PP1) a device by sending messages across the

GPIB from the Controller to the device. If a device has not been configured to respond to parallel polls, it does not respond to parallel polls.

Some devices support only local configuration and some support only remote configuration. Some devices do not support any parallel polls (Parallel Poll function subset PP0).

NAT7210 Reference Manual B-26 © National Instruments Corp.

Appendix B Introduction to the GPIB

Determining the PPE Message

The PPE message contains the parallel poll configuration data for a device. Table B-3 shows how you determine the value of DIO[7:1] for the PPE message. As with all commands, the DIO[8] is a don’t care bit.

Table B-3. Determining the PPE Message

Sense Bit (S) PPR Message to Send

0

0

0

0

PPR1

PPR2

PPR3

PPR4

1

1

1

1

0

0

0

0

1

1

1

1

PPR5

PPR6

PPR7

PPR8

PPR1

PPR2

PPR3

PPR4

PPR5

PPR6

PPR7

PPR8

PPE Message

(hex)

60

61

62

63

68

69

6A

6B

64

65

66

67

6C

6D

6E

6F

Physical Representation of the PPR Message

To send a PPR message true, a device drives the corresponding GPIB DIO signal low with an open-collector driver. For example, to send the PPR4 message true, a device drives the GPIB DIO4 signal low.

Because devices drive the DIO signals with open-collector drivers during parallel polls, more than one device can share a PPR message. If a Controller detects a PPR message being sent true, the Controller knows that one or more of the devices sharing the PPR message is sending the PPR message true.

© National Instruments Corp.

B-27 NAT7210 Reference Manual

Introduction to the GPIB Appendix B

Clearing and Triggering Devices

A Controller can clear devices in several ways. It can assert the IFC line to clear all devices, or it can send the Device Clear (DCL) command message to clear all devices on the bus. To clear a single device, a Controller can address the device to listen, then send the Selected Device Clear (SDC) command message.

After a device receives DCL or SDC, its clear state is device dependent. Generally, sending DCL or SDC is a less extreme method of clearing a device than asserting IFC.

Most devices support the DCL and SDC method; all devices support the IFC method.

All devices in multidevice measurement systems must often be sampled as closely together as possible. You can trigger devices simultaneously by using the Group Execute

Trigger (GET) command message. This command message causes all devices that have triggering capability and that are currently addressed to initiate a preprogrammed action.

The action could be, for example, to take a measurement or begin a sweep.

NAT7210 Reference Manual B-28 © National Instruments Corp.

Appendix C

Standard Commands for Programmable

Instruments (SCPI)

This appendix discusses the Standard Commands for Programmable Instruments (SCPI) document, the required SCPI commands, and SCPI programming.

GPIB instrumentation standards have progressed from the IEEE 488.1 standard to the

IEEE 488.2 standard to SCPI. The IEEE 488.1 standard simplified and standardized the interconnection of programmable instrumentation by defining the electrical, mechanical, and protocol specifications of the GPIB. Before IEEE 488.1, each manufacturer had its own proprietary interface.

The IEEE 488.2 standard kept the IEEE 488.1 standard intact, but it made systems more compatible and program development easier by defining standard data codes and formats, a status-reporting model, a message exchange protocol, a set of common commands for all instruments, and Controller requirements. Because the IEEE 488.1 standard did not address these issues, manufacturers implemented each item differently, thus creating complex programming and unpredictable development costs.

SCPI uses the IEEE 488.2 standard as a basis for defining a single, comprehensive command set that is suitable for all instruments. SCPI users no longer need to learn a different command set for each instrument in their systems.

You can use IEEE 488.1, IEEE 488.2, and SCPI instruments and Controllers together, but you achieve the maximum benefits with a system consisting of an IEEE 488.2 Controller and SCPI instruments.

© National Instruments Corp.

C- 1 NAT7210 Reference Manual

SCPI Appendix C

IEEE 488.2 Common Commands Required by SCPI

All SCPI devices require the mandatory common commands that the IEEE 488.2

standard defines (see Table C-1). This command set consists of program commands and status queries that are common to all devices. These commands and queries do not handle device-specific operations; they handle more general operations such as device identification, operation synchronization, standard event status enabling and reporting, device reset and self-test, and service request enable reporting.

Table C-1. IEEE 488.2 Common Commands Required by SCPI

Command

*CLS

*ESE

*ESE?

*ESR?

*IDN?

*OPC

*OPC?

*RST

*SRE

*SRE?

*STB?

*TST?

*WAI?

Description

Clear Status Command

Standard Event Status Enable Command

Standard Event Status Enable Query

Standard Event Status Register Query

Identification Query

Operation Complete Command

Operation Complete Query

Reset Command

Service Request Enable Command

Service Request Enable Query

Read Status Byte Query

Self-Test Query

Wait-to-Continue Command

NAT7210 Reference Manual C- 2 © National Instruments Corp.

Appendix C SCPI

SCPI Required Commands

In addition to the IEEE 488.2 common commands and queries, SCPI defines its own set of required common commands (see Table C-2). In general, these commands build on the IEEE 488.2 common command set, but SCPI expands the standard status-reporting model defined in IEEE 488.2 with OPERation and QUEStionable status registers. For both of these registers, commands read the contents of the EVENt and CONDition registers, set the ENABle mask, and read the ENABle mask.

The SYSTem command set defines functions that are not related to instrument performance, such as commands for performing general housekeeping like setting

TIME or SECurity. The subcommand query ERRor? requests the next entry from the error/event queue of the device. The PRESet command configures the SCPI and device-dependent status registers to be reported through the SCPI status-reporting model.

Table C-2. SCPI Required Commands

Command

:SYSTem

:ERRor?

:STATus

:OPERation

[:EVENt]?

:CONDition?

:ENABle

:QUEStionable

[:EVENt]?

:CONDition

:ENABle

:ENABle?

:PRESet

Description

Collects functions not related to instrument performance

Requests the next entry from the instrument’s error queue

Controls the SCPI-defined status-reporting structures

Selects the Operation structure

Returns the contents of the Event register

Returns the contents of the Condition register

Reads the Enable mask

Selects the Questionable structure

Returns the contents of the Event register

Returns the contents of the Condition register

Sets the Enable mask, which allows event reporting

Reads Enable mask

Enables all required event reporting

SCPI Optional Commands

The SCPI command set that an instrument uses can include a subset of the commands covered in the SCPI specification. An instrument designed to measure voltage does not implement commands to measure frequency. An instrument can also support special commands not presently covered in the SCPI standard.

© National Instruments Corp.

C- 3 NAT7210 Reference Manual

SCPI Appendix C

SCPI commands are not case sensitive. Moreover, a command such as TRIGger can be issued as TRIGGER or as its short-form mnemonic, TRIG. However, SCPI does not recognize any other version of this command. For example, TRIGG is not a valid command.

Programming with SCPI

The functional blocks of the SCPI Instrument model define the command categories.

These categories, along with some other general categories, have a hierarchical structure of subcommands and parameters for more specific functions (see Figure C-1).

. . .

. . .

SENSe

VOLTage

. . .

CURRent

. . .

TRIGger

. . .

. . .

SOURce

. . .

. . .

Figure C-1. Partial Command Categories

Most instruments require commands to execute a specific function. For example, a digital voltmeter can require the MEASure, VOLTage, and AUTO commands to take a voltage reading. To properly interpret these commands, SCPI defines a hierarchical command structure called a command tree. Figure C-2 illustrates a simple command tree for the SENSe command subsystem.

SENSe

. . .

UPPer

. . .

RANge

. . .

VOLTage

. . .

AUTO

. . .

RESolution

AUTO

. . .

UPPer

. . .

RANge

CURRent

. . .

. . .

POWer

RESolution

. . .

AUTO AUTO

Figure C-2. Simple Command Tree for the SENSe Command Subsystem

NAT7210 Reference Manual C- 4 © National Instruments Corp.

Appendix C SCPI

The SENSe commands control the characteristics of the conversion process for the input sensors of the instrument. Examples include the following:

• Signal amplitude for VOLTage, CURRent, and POWer

• Filter BANDwidth

• FREQuency characteristics

The SENSe commands do not mathematically manipulate the data after it has been converted.

Constructing SCPI Commands by Using the Hierarchical Command

Structure

The SENSe commands program an instrument to control the conversion of the signal into internal data that can be manipulated. SENSe commands control such parameters as range, resolution, gate time, and normal mode rejection. By using the partial command tree shown in Figure C-3, you can construct the short form command to configure an instrument for a voltage measurement that uses dynamic autoranging. This command is as follows:

SENS:VOLT:RANG:AUTO:DIR:EITH

. . .

UPPer

. . .

SENSe

. . .

VOLTage

. . .

POWer

.

.

RANGe

LOWer

. . .

AUTO

DIRection

. . .

UP DOWN

CURRent

.

.

EITHer

. . .

. . .

Figure C-3. Partial Command Tree for the SENSe Command Subsystem

© National Instruments Corp.

C- 5 NAT7210 Reference Manual

SCPI Appendix C

The SOURce commands program the instrument to generate a signal based on specified characteristics and internal data. SOURce block functions specify such signal parameters as amplitude modulation, power, current, voltage, and frequency. By using the partial command tree shown in Figure C-4, you can construct the short form command to set the upper limit of the current output to 500 mA. This command is as follows:

SOUR:CURR:LIM:HIGH 0.5

AMPLitude

SOURce

. . .

. . .

CURRent

LIMit

. . .

POWer

.

.

OFFSet HIGH

VOLTage

.

.

. . .

LOW STATe

Figure C-4. Partial Command Tree for the SOURce Command Subsystem

The TRIGger commands program the instrument to synchronize its operation based on some event. Trigger sources include an internal event or condition involving the instrument functionality, an external condition such as an analog or digital signal, or a software command. By using the partial command tree shown in Figure C-5, you can construct the short form command to trigger an instrument from an external source. This command is as follows:

TRIG:SOUR:EXT

BUS ECLTrg EXTernal

. . .

TRIGger

SOURce

. . .

HOLD IMMediate INTernal LINE

Figure C-5. Partial Command Tree for the TRIGger Command Subsystem

LINK

NAT7210 Reference Manual C- 6 © National Instruments Corp.

Appendix C SCPI

Parsing SCPI Commands

Colons separate each command and instruct the instrument parser to move down a level in the command tree hierarchy. In situations where two commands are issued without changing levels, a semicolon separates the commands. Commas separate parameters such as numeric, extended numeric, discrete, and Boolean. Commas are generally ignored with two exceptions:

• Spaces should not break command words.

• Spaces must not separate commands and parameters.

The colon preceding the first command in a SCPI message instructs the parser in the

SCPI instrument to reset itself to the root level in the hierarchy.

Unless specifically noted, all commands have a query form as defined in the IEEE 488.2

standard. When a query command is received, the current instrument settings associated with that command are placed in the instrument output buffer. For more commands, consult the SCPI standard or the user manuals for the SCPI instruments of interest in a particular application.

© National Instruments Corp.

C- 7 NAT7210 Reference Manual

Appendix D

Multiline Interface Command Messages

This appendix lists the multiline interface messages and describes the mnemonics and messages that correspond to the interface functions. The multiline interface messages are

IEEE 488 defined commands that are sent and received with ATN TRUE. The interface functions include initializing the bus, addressing and unaddressing devices, and setting device modes for local or remote programming.

© National Instruments Corp.

D- 1 NAT7210 Reference Manual

Multiline Interface Command Messages

Multiline Interface Messages

Appendix D

Hex Oct Dec ASCII Msg

1C

1D

1E

1F

18

19

1A

1B

14

15

16

17

10

11

12

13

0C

0D

0E

0F

08

09

0A

0B

04

05

06

07

00

01

02

03

030

031

032

033

034

035

036

037

020

021

022

023

024

025

026

027

010

011

012

013

014

015

016

017

000

001

002

003

004

005

006

007

28

29

30

31

24

25

26

27

20

21

22

23

16

17

18

19

12

13

14

15

10

11

8

9

6

7

4

5

2

3

0

1

FS

GS

RS

US

CAN

EM

SUB

ESC

DLE

DC1

DC2

DC3

DC4

NAK

SYN

ETB

BS

HT

LF

VT

FF

CR

SO

SI

NUL

SOH

STX

ETX

EOT

ENQ

ACK

BEL

Hex Oct Dec ASCII Msg

GTL

SDC

PPC

GET

TCT

LLO

DCL 34

PPU 35

36

37

30

31

32

33

SPE

SPD

3C

3D

3E

3F

38

39

3A

3B

2C

2D

2E

2F

28

29

2A

2B

24

25

26

27

20

21

22

23

060

061

062

063

064

066

067

070

071

072

073

074

075

076

077

050

051

052

053

054

055

056

057

040

041

042

043

044

045

046

047

>

?

<

=

;

:

8

9

6

7

4

5

2

3

0

1

$

%

'

&

"

#

!

SP MLA0

MLA1

MLA2

MLA3

MLA4

MLA5

MLA6

MLA7

*

+

)

( MLA8

MLA9

MLA10

MLA11

/

.

, MLA12

- MLA13

MLA14

MLA15

MLA16

MLA17

MLA18

MLA19

MLA20

MLA21

MLA22

MLA23

MLA24

MLA25

MLA26

MLA27

MLA28

MLA29

MLA30

UNL

48

49

50

51

52

54

55

60

61

62

63

56

57

58

59

44

45

46

47

40

41

42

43

36

37

38

39

32

33

34

35

Message Definitions

DCL

GET

GTL

LLO

MLA

Device Clear

Group Execute Trigger

Go To Local

Local Lockout

My Listen Address

MSA

MTA

PPC

PPD

My Secondary Address

My Talk Address

Parallel Poll Configure

Parallel Poll Disable

NAT7210 Reference Manual D- 2 © National Instruments Corp.

Appendix D

Multiline Interface Messages

130

131

132

133

134

135

136

137

120

121

122

123

124

125

126

127

110

111

112

113

114

115

116

117

100

101

102

103

104

105

106

107

Hex Oct Dec ASCII Msg

5C

5D

5E

5F

58

59

5A

5B

54

55

56

57

50

51

52

53

4C

4D

4E

4F

48

49

4A

4B

44

45

46

47

40

41

42

43

92

93

94

95

88

89

90

91

84

85

86

87

80

81

82

83

76

77

78

79

72

73

74

75

68

69

70

71

64

65

66

67

^

_

]

\

[

Z

X

Y

T

U

V

W

P

Q

R

S

L

M

N

O

I

H

J

K

D

E

F

G

@

A

B

C

MTA16

MTA17

MTA18

MTA19

MTA20

MTA21

MTA22

MTA23

MTA24

MTA25

MTA26

MTA27

MTA28

MTA29

MTA30

UNT

MTA0

MTA1

MTA2

MTA3

MTA4

MTA5

MTA6

MTA7

MTA8

MTA9

MTA10

MTA11

MTA12

MTA13

MTA14

MTA15

Message Definitions

PPE

PPU

SDC

SPD

Parallel Poll Enable

Parallel Poll Unconfigure

Selected Device Clear

Serial Poll Disable

Multiline Interface Command Messages

7C

7D

7E

7F

78

79

7A

7B

74

75

76

77

70

71

72

73

6C

6D

6E

6F

68

69

6A

6B

64

65

66

67

60

61

62

63

170

171

172

173

174

175

176

177

160

161

162

163

164

165

166

167

150

151

152

153

154

155

156

157

140

141

142

143

144

145

146

147

120

121

122

123

124

125

126

127

112

113

114

115

116

117

118

119

104

105

106

107

108

109

110

111

96

97

98

99

100

101

102

103

Hex Oct Dec ASCII Msg

MSA16,PPD

MSA17,PPD

MSA18,PPD

MSA19,PPD

MSA20,PPD

MSA21,PPD

MSA22,PPD

MSA23,PPD

MSA24,PPD

MSA25,PPD

MSA26,PPD

MSA27,PPD

MSA28,PPD

MSA29,PPD

MSA30,PPD

MSA0,PPE

MSA1,PPE

MSA2,PPE

MSA3,PPE

MSA4,PPE

MSA5,PPE

MSA6,PPE

MSA7,PPE

MSA8,PPE

MSA9,PPE

MSA10,PPE

MSA11,PPE

MSA12,PPE

MSA13,PPE

MSA14,PPE

MSA15,PPE z

{ x y

|

}

~

DEL t u v w r s p q n o l m j k i h f g d e b c

` a

SPE Serial Poll Enable

TCT Take Control

UNL Unlisten

UNT Untalk

© National Instruments Corp.

D- 3 NAT7210 Reference Manual

Appendix E

Mnemonics Key

This appendix defines the mnemonics (abbreviations) that this manual uses for functions, remote messages, local messages, states, bits, registers, integrated circuits, and system functions.

The mnemonic types in this key are abbreviated to mean the following:

A

B

F

IC

LM

P

R

RM

SF

ST

Auxiliary or Accessory Commands

Bit

Function

Integrated Circuit

Local Message

Physical Device Pin

Register

Remote Message

System Function

State

© National Instruments Corp.

E-1 NAT7210 Reference Manual

Mnemonics Key

Mnemonic

A

ADR

ADR0

ADR1

ADSC

ADSC IE

ADSR

AEFN

AEHS

AH

AH1

ANHS1

ANHS2

ANRS

APT

APT IE

ARS

ACCRA

ACCRB

ACCRE

ACCRF

ACCRI

ACCRJ

ACCR

ACCWR

ACDS

ACG

ACRDY

ACRS

AD[5–1]

ADHS

ADMR

ATCT

ATN

ATN*

ATN IE

ATNI

ATNI IE

AUXCR

Type

ST

B

B

B

F

F

B

B

B

R

B

B

R

R

R

B

B

B

R

B

RM

B

B

ST

B

B

R

R

ST

RM

B

R

R

R

R

R

R

R

Appendix E

Definition

Accessory Register A

Accessory Register B

Accessory Register E

Accessory Register F

Accessory Register I

Accessory Register J

Accessory Register

Accessory Write Register

Acceptor Data State (AH function)

Addressed Command Group

Acceptor Ready State bit

Acceptor Ready State

NAT7210 GPIB Address bits 5 through 1

Acceptor Data Holdoff State bit

Address Mode Register

Address Register

Address Register 0

Address Register 1

Address Status Change bit

Address Status Change Interrupt Enable bit

Address Status Register

FIFO A Empty Flag bit

Acceptor End Holdoff State bit

Acceptor Handshake function

Acceptor Handshake

Acceptor Not Ready Holdoff bit

Acceptor Not Ready Holdoff Immediately bit

Acceptor Not Ready State

Address Pass Through bit

Address Pass Through Interrupt Enable bit

Address Register Select bit

Automatic Take Control bit

Attention

Attention bit

Attention Interrupt Enable bit

ATN Interrupt bit

ATN Interrupt Enable bit

Auxiliary Command Register

NAT7210 Reference Manual E-2 © National Instruments Corp.

Appendix E

Mnemonic

AUXMR

AUXRA

AUXRB

AUXRE

AUXRF

AUXRG

AUXRI

B

BCR

BI

BI IE

BIN

BO

BO IE

BSR

C

CDOR

CHES ch_rst

CIC

CIC IE

Clear ERR clrpi

CMDR

CO

CO IE cont

CPT B

CPT ENABLE B

CPT IE

CPTR

B

R

R

B

B

B

B

A

A

R

B

A

B

B

R

R

B

B

B

Type

R

R

R

R

R

R

R

Mnemonics Key

Definition

Auxiliary Mode Register

Auxiliary Register A

Auxiliary Register B

Auxiliary Register E

Auxiliary Register F

Auxiliary Register G

Auxiliary Register I

Bus Control Register

Byte In bit

Byte In Interrupt Enable bit

Binary bit

Byte Out bit

Byte Out Interrupt Enable bit

Bus Status Register

Command/Data Out Register

Clear Holdoff On End Select bit

Chip Reset auxiliary command

Controller-In-Charge bit

Controller-In-Charge Interrupt Enable bit

Clear ERR Interrupt auxiliary command

Clear Page-In Registers auxiliary command

Command Register

Command Out bit

Command Out Interrupt Enable bit

Continuous mode

Command Pass Through bit

Command Pass Through Enable bit

Command Pass Through Interrupt Enable bit

Command Pass Through Register

© National Instruments Corp.

E-3 NAT7210 Reference Manual

Mnemonics Key

Mnemonic

D

DAC dacr dai dai dal dat

DAV

DAV

DCAS

DCAS IE

DCL

DEC

DEC IE

DET

DET IE

DHADC

DHADT

DHALA

DHALL

DHATA

DHDC

DHDT

DHUNTL

DI

DI IE

DIO

DIR

DISTCT

DL

DL0

DL1

DMAE

DMAEN

DMAI

DMAO

DO

DO IE

DRQ

DT

DT

DT0

Type

RM

A

A

B

B

B

B

B

RM

B

B

B

B

B

B

RM

B

B

B

B

B

B

B

B

B

B

B

B

B

P

R

B

B

B

B

B

B

B

B

F

B

Appendix E

Definition

NAT7210 Reference Manual

Data Accepted

Release DAC Holdoff auxiliary command

Disable IMR2, IMR1, And IMR0 Interrupts auxiliary command

Disable IMR2, IMR1, And IMR0 Interrupts bit

Disable Listener bit

Disable Talker bit

Data Valid

GPIB Data Valid Signal bit

Device Clear Active State bit

Device Clear Active State Interrupt Enable bit

Device Clear

Device Clear bit

Device Clear Interrupt Enable bit

Device Execute Trigger bit

Device Execute Trigger Interrupt Enable bit

DAC Holdoff On DCL Or SDC Command bit

DAC Holdoff On GET Command bit

DAC Holdoff On All Listener Addresses Command bit

DAC Holdoff On All UCG, ACG, And SCG Commands bit

DAC Holdoff On All Talker Addresses Command bit

DAC Holdoff On DCAS Command bit

DAC Holdoff On DTAS Command bit

DAC Holdoff On The UNL Or UNT Command bit

Data In bit

Data In Interrupt Enable bit

GPIB Data Input/Output pins

Data In Register

Disable Automatic Take Control bit

Disable Listener bit

Disable Listener 0 bit

Disable Listener 1 bit

DMA Enable bit

DMA Enable bit

DMA Input Enable bit

DMA Output Enable bit

Data Out bit

Data Out Interrupt Enable bit

DMA Request Pin Status bit

Disable Talker bit

Device Trigger function

Disable Talker 0 bit

E-4 © National Instruments Corp.

Appendix E

Mnemonic

DT1

DTAS

E

edpa

END

END IE

END RX

EOI

EOI

EOIOE

EOS

EOS0

EOS1

EOS2

EOS3

EOS4

EOS5

EOS6

EOS7

EOSR

ERR

ERR IE

ESB

EXTDAC

F

F[3–0] feoi fget

G

GET

GET IE

GLINT gts

Type

B

ST

A

A

B

B

B

A

B

B

B

B

RM

B

B

B

B

R

B

B

B

B

B

B

B

RM

B

B

Mnemonics Key

Definition

Disable Talker 1 bit

Device Trigger Active State

Enable Dual Primary Addressing Mode bit

End Received bit

End Received Interrupt Enable bit

End Received bit

End or Identify

End-or-Identify bit

GPIB EOI Signal Output Enable bit

End of String

End-of-String bit 0

End-of-String bit 1

End-of-String bit 2

End-of-String bit 3

End-of-String bit 4

End-of-String bit 5

End-of-String bit 6

End-of-String bit 7

End-of-String Register

Error bit

Error Interrupt Enable bit

Event Status Bit

External DAC

Clock Frequency

Send EOI With The Next Byte

Force Group Execute Trigger auxiliary command

Group Execute Trigger bit

Group Execute Trigger Interrupt Enable bit

Global Interrupt Enable bit

Go To Standby auxiliary command

© National Instruments Corp.

E-5 NAT7210 Reference Manual

Mnemonics Key Appendix E

Mnemonic

H

hdfa hdfe hlda

HLDA hlde hlde

HLDE hldi

HSTS

I

ICR

ICR2

IDY

IFC

IFC IE

IFCI

IFCI IE

IMR0

IMR1

IMR2

INT

INT0

INV

INT1

ISR0

ISR1

ISR2

ISS ist

Type

A

A

B

A

B

A

ST

Definition

Holdoff On All Data auxiliary command

Holdoff On End Only auxiliary command

RFD Holdoff On All Data mode

Holdoff On All Data bit

Holdoff On All END mode

Holdoff On All END Mode auxiliary command

Holdoff On End bit

Holdoff Handshake Immediately auxiliary command

High-Speed T1 State

B

B

B

R

R

R

R

B

R

R

B

A

R

R

RM

RM

B

B

B

Internal Count Register

Internal Count Register 2

Identify

Interface Clear

Interface Clear Interrupt Enable bit

IFC Interrupt bit

IFC Interrupt Enable bit

Interrupt Mask Register 0

Interrupt Mask Register 1

Interrupt Mask Register 2

Interrupt Request Pin bit

Interrupt Register 0 Interrupt bit

Invert bit

Interrupt Register 1 Interrupt bit

Interrupt Status Register 0

Interrupt Status Register 1

Interrupt Status Register 2

Individual Status Select bit

Parallel Poll Flag auxiliary command

L

L

LA

LACS

LADCS

LADS

LIDS

LLO

LLOC

ST

ST

B

B

F

B

ST

ST

NAT7210 Reference Manual

Listen

Listener Active bit

Listener Active State

Listener Addressed Or Active State

Listener Addressed State (L function)

Listener Idle State

Local Lockout bit

Local Lockout Change bit

E-6 © National Instruments Corp.

Appendix E Mnemonics Key

Mnemonic

LLOC IE

LOCS

LOK

LOKC

LOKC IE lon lon

LPAS

LPAS

LPIS ltn lul lun lut

LWC

Type

B

ST

ST

A

A

LM

A

B

B

ST

B

B

B

B

LM

Definition

Local Lockout Change Interrupt Enable bit

Local State

Lockout bit

Lockout Change bit

Lockout Change Interrupt Enable bit

Listen-Only bit

Listen Only

Listener Primary Addressed State bit

Listener Primary Addressed State

Listener Primary Idle State

Listen auxiliary command

Unlisten auxiliary command

Local Unlisten

Local Untalk auxiliary command

Listen When Controller bit

M

MA

MA IE

MAC

MAC IE

MAV

MICR

MICR

MJMN

MLA

MSA

MSS

MTA

MAT6

B

R

B

B

B

B

B

B

RM

RM

B

RM

RM

My Address bit

My Address Interrupt Enable bit

My Address Change bit

My Address Change Interrupt Enable bit

Message Available bit

Modify Internal Count Register

Modify Internal Count Register bit

Major-Minor bit

My Listen Address

My Secondary Address

Master Summary Status bit

My Talk Address

My Talk Address 6

N

nba nba nbaf nbaf

NDAC

NL

NL IE

NLEN nonvalid

NPRS

B

B

B

B

B

LM

A

B

A

ST

© National Instruments Corp.

New Byte Available local message bit

New Byte Available

New Byte Available False auxiliary command

New Byte Available False bit

Not Data Accepted bit

New Line Receive bit

New Line Receive Interrupt Enable bit

New Line End Enable bit

Nonvalid auxiliary command issued

Negative Poll Response State

E-7 NAT7210 Reference Manual

Mnemonics Key Appendix E

Mnemonic

NRFD

NTNL

O

OSA

Type

RM

B

RM

Definition

Not Ready For Data Message

No Talking When No Listener bit

Other Secondary Address

P

P1

P2

P3

PACS

PCG

PE

PEND piaccr pibcr pieosr piimr2 pon

PP1

PP2

PPC

PPD

PPE

PPR

PPR

PPU pts

RM

RM

RM

R

RM

RM

A

B

A

A

A

A

LM

B

B

B

B

B

ST

RM

Parallel Poll Response bit 1

Parallel Poll Response bit 2

Parallel Poll Response bit 3

Parallel Poll Addressed To Configure state

Primary Command Group

Pull-Up Enable

Pending bit

Page-In Accessory Register auxiliary command

Page-In Bus Control Register auxiliary command

Page-In End-of-String Register auxiliary command

Page-In Interrupt Mask Register 2 auxiliary command

Power On

Parallel Poll bit 1

Parallel Poll bit 2

Parallel Poll Configure

Parallel Poll Disable

Parallel Poll Enable

Parallel Poll Register

Parallel Poll Response

Parallel Poll Unconfigure

Pass Through Next Secondary auxiliary command

R

rdy

REM

REMC

REMC IE

REN

REOS reqf reqt

RFD

LM

B

B

B

RM

B

A

A

RM

NAT7210 Reference Manual

Ready For Next Message

Remote bit

Remote Change bit

Remote Change Interrupt Enable bit

Remote Enable

End On EOS Received bit

Request rsv False auxiliary command

Request rsv True auxiliary command

Ready For Data

E-8 © National Instruments Corp.

Appendix E Mnemonics Key

Mnemonic Type rhdf rhdf

RL1 rlc

RLC

RLC IE rpp rpp1

RPP2 rqc

B

B

RQS RM rsv LM rsv rsv2 rtl

B

A

A

B

B

A

A

B

A

F

B

Definition

Release RFD Holdoff

Release RFD Holdoff auxiliary command

Remote/Local

Release Control command

Remote/Local Change bit

Remote/Local Change Interrupt Enable bit

Clear/Set Request Parallel Poll

Execute Parallel Poll auxiliary command

Request Parallel Poll 2 bit

Request Control command

Request Service

Request Service

Request Service bit

Request Service Bit 2 auxiliary command

Return To Local auxiliary command

S

SISB

SLOW

SPAS

SPAS IE

SPD

SPE

SPEOI

SPIS

SPMR

SPMS

SPMS

SPSR seoi

SH

SH1A

SH1B

SHAS shdw sic

SIDS

S

S[6–1]

SASR

SC

SCG

SDC

SDHS

SDYS

A

ST

B

B

ST

B

RM

RM

ST

A

F

B

B

ST

A

B

ST

R

ST

B

R

B

B

R

P

RM

RM

© National Instruments Corp.

Status Bit Polarity (Sense) bit

Serial Poll Status bits 6 through 1

Source Acceptor Status Register

75162 System Controller pin

Secondary Command Group

Selected Device Clear

Selected DAC Holdoffs Internal Signal

Source Delay State

Send EOI auxiliary command

Source Handshake function

Source Handshake State bit A

Source Handshake State bit B

Source High-Speed Active State

Clear/Set Shadow Handshake auxiliary command

Clear/Set Send Interface Clear auxiliary command

Source Idle State

Static Interrupt Status bit

Slow Handshake Lines

Serial Poll Active State

Serial Poll Active State Interrupt Enable bit

Serial Poll Disable

Serial Poll Enable

Send Serial Poll EOI bit

Serial Poll Idle State

Serial Poll Mode Register

Serial Poll Mode State

Serial Poll Mode State bit

Serial Poll Status Register

E-9 NAT7210 Reference Manual

Mnemonics Key

Mnemonic

SR1 sre

SRQ

SRQ IE

SRQI

SRQI IE

SRQS

STB

STBO

STBO IE stdl

STRS sw7210 swrst

SYNC

SYNC IE

T

T

TA

TACS

F

B

ST

TADS ST tca A tcs tcse

A

A

TCT

TE

TIDS ton ton

TPAS

TPAS

TPIS

TRI

TRIG trig

TRM0

TRM1

A

B

B

B

ST

B

ST

B

RM

F

ST

LM

Type

ST

A

A

B

B

RM

B

B

A

F

A

RM

B

B

B

ST

Appendix E

Definition

Service Request function

Clear/Set Send Remote Enable auxiliary command

Service Request

Service Request Interrupt Enable bit

Service Request bit

Service Request Interrupt Enable bit

Service Request State

Status Byte

Status Byte Out bit

Status Byte Out Interrupt Enable bit

Set Short T1 Delay auxiliary command

Source Transfer State

Switch To Turbo+7210 Mode auxiliary command

Software Reset auxiliary command issued

GPIB Synchronization bit

GPIB Synchronization Interrupt Enable bit

Talker

Talker Active bit

Talker Active State (T function)

Talker Addressed State

Take Control Asynchronously auxiliary command

Take Control Synchronously auxiliary command

Take Control Synchronously On End auxiliary command

Take Control

Extended Talker

Talker Idle State

Talk Only

Talk-Only bit

Talker Primary Addressed State

Talker Primary Addressed State bit

Talker Primary Idle State

Three-State Timing bit

Trigger

Trigger auxiliary command

Transmit/Receive Mode bit 0

Transmit/Receive Mode bit 1

NAT7210 Reference Manual E-10 © National Instruments Corp.

Appendix E

Mnemonic

U

Type

U

UCG ulpa

UNC

UNC IE unl

UNL unt A

UNT RM

USTD B

B

RM

B

B

B

A

RM

V

valid

VSR vstdl

A

R

A

X

X

XEOS

B

B

Mnemonics Key

Definition

Unconfigure bit

Universal Command Group

Upper/Lower Primary Address bit

Unrecognized Command bit

Unrecognized Command Interrupt Enable bit

Unlisten auxiliary command

Unlisten command

Untalk auxiliary command

Ultra Short T1 Delay bit

Valid auxiliary command

Version Status Register

Very Short T1 Delay auxiliary command

Don’t care bit

Transmit END With EOS bit

© National Instruments Corp.

E-11 NAT7210 Reference Manual

Appendix F

Customer Communication

For your convenience, this appendix contains forms to help you gather the information necessary to help us solve technical problems you might have as well as a form you can use to comment on the product documentation. Filling out a copy of the Technical

Support Form before contacting National Instruments helps us help you better and faster.

National Instruments provides comprehensive technical assistance around the world. In the U.S. and Canada, applications engineers are available Monday through Friday from

8:00 a.m. to 6:00 p.m. (central time). In other countries, contact the nearest branch office.

You may fax questions to us at any time.

Corporate Headquarters

(512) 795-8248

Technical support fax: (800) 328-2203

(512) 794-5678

Branch Offices

Australia

Austria

Belgium

Denmark

Finland

France

Germany

Hong Kong

Phone Number

03 9 879 9179

0662 45 79 90 19

02 757 03 11

45 76 71 11

90 502 2930

1 48 14 24 14

089 714 60 35

2686 8505

Japan

Korea

Mexico

Netherlands

Norway

Singapore

Spain

Sweden

Switzerland

Taiwan

U.K.

03 5472 2977

02 596 7455

5 202 2544

03480 30673

32 84 86 00

2265887

91 640 0533

08 730 43 70

056 20 51 55

02 737 4644

01635 523154

Fax Number

03 9 879 9422

0662 45 79 90 0

02 757 00 20

45 76 26 00

90 527 2321

1 48 14 24 24

089 741 31 30

2645 3186

02 48301892

03 5472 2970

02 596 7456

5 520 3282

03480 33466

32 84 84 00

2265886

91 640 0085

08 730 49 70

056 20 51 51

02 377 1200

01635 523545

© National Instruments Corp.

F-1 NAT7210 Reference Manual

Technical Support Form

Technical support is available at any time by fax. Include the information from your configuration form. Use additional pages if necessary.

Name

Company

Address

Fax ( )

Computer brand

Model

Operating system

RAM MB

Display adapter

Mouse no

Other adapters installed

Brand

Instruments used

National Instruments hardware product(s)

Revision

Configuration

(continues)

The problem is

List any error messages

The following steps will reproduce the problem

Documentation Comment Form

National Instruments encourages you to comment on the documentation supplied with our products. This information helps us provide quality products to meet your needs.

Title: NAT7210 TM Reference Manual

Edition Date: June 1995

Part Number: 370875A-01

Please comment on the completeness, clarity, and organization of the manual.

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If you find errors in the manual, please record the page numbers and describe the errors.

Thank you for your help.

Name

Title

Company

Address

Phone ( )

Mail to:

Fax to:

Technical Publications

National Instruments Corporation

6504 Bridge Point Parkway, MS 53-02

Austin, TX 78730-5039

Technical Publications

National Instruments Corporation

MS 53-02

(512) 794-5678

EOS

F

GPIB hex

Hz

IC

I/O

ISO

AC

ANSI

CIC

CPU

DIP

DMA

EOI m

MB

MHz s

Glossary

Prefix pn-

µ

m-

M-

Meaning piconanomicromillimega-

Value

10

-12

10

-9

10

-6

10

-3

10

6 alternating current

American National Standards Institute

Controller-In-Charge central processing unit dual inline package direct memory access

End-or-Identify

End-of-String

Farads

General Purpose Interface Bus hexadecimal hertz integrated circuit input/output

International Standards Organization meters megabytes of memory megahertz seconds

© National Instruments Corp.

G-1 NAT7210 Reference Manual

Index

Numbers

7210-mode interface registers, 3-1 to 3-64

Address Mode Register (ADMR),

3-5 to 3-7

Address Register (ADR), 3-8

Address Register 0 (ADR0), 3-9

Address Register 1 (ADR1), 3-10

Address Status Register (ADSR),

3-11 to 3-13

Auxiliary Mode Register (AUXMR),

3-14 to 3-26

Auxiliary Register A (AUXRA),

3-27 to 3-28

Auxiliary Register B (AUXRB), 3-29 to 3-30

Auxiliary Register E (AUXRE), 3-31

Auxiliary Register F (AUXRF), 3-32

Auxiliary Register G (AUXRG),

3-33 to 3-34

Auxiliary Register I (AUXRI), 3-35 to 3-36

Bus Control Register (BCR)/Bus

Status Register (BSR), 3-37 to 3-38

Command/Data Out Register

(CDOR), 3-39

Command Pass Through Register

(CPTR), 3-40

Data In Register (DIR), 3-41

End-of-String Register (EOSR), 3-42 hidden registers address register map, 3-3 auxiliary mode register map, 3-4

Internal Count Register (ICR), 3-43

Internal Count Register 2

(ICR2), 3-44

Interrupt Mask Register 0 (IMR0),

3-45 to 3-48

Interrupt Mask Register 1 (IMR1),

3-49 to 3-53

Interrupt Mask Register 2 (IMR2),

3-54 to 3-57

Interrupt Status Register 0 (ISR0),

3-45 to 3-48

Interrupt Status Register 1 (ISR1),

3-49 to 3-53

Interrupt Status Register 2 (ISR2),

3-54 to 3-57

Page-In state, 3-3

Parallel Poll Register (PPR), 3-58 to 3-59 register map, 3-2

Serial Poll Mode Register (SPMR),

3-62 to 3-63

Serial Poll Status Register (SPSR),

3-62 to 3-63

Source/Acceptor Status Register

(SASR), 3-60 to 3-61

Version Status Register (VSR), 3-64

9914-mode interface registers, 4-1 to 4-50

Accessory Register A (ACCRA), 4-5

Accessory Register B (ACCRB), 4-6 to 4-7

Accessory Register E (ACCRE), 4-8

Accessory Register F (ACCRF), 4-9

Accessory Register I (ACCRI), 4-10

Address Register (ADR), 4-11

Address Status Register (ADSR),

4-12 to 4-14

Auxiliary Command Register

(AUXCR), 4-15 to 4-27

Bus Control Register (BCR)/Bus

Status Register (BSR), 4-28 to 4-29

Command/Data Out Register

(CDOR), 4-30



National Instruments Corp.

I-1 NAT7210 Reference Manual

Index

Command Pass Through Register

(CPTR), 4-31

Data In Register (DIR), 4-32

End-of-String Register (EOSR), 4-33 hidden registers, 4-3

Internal Count Register (ICR), 4-34

Interrupt Mask Register 0 (IMR0),

4-35 to 4-38

Interrupt Mask Register 1 (IMR1),

4-39 to 4-43

Interrupt Mask Register 2 (IMR2),

4-44 to 4-47

Interrupt Status Register 0 (ISR0),

4-35 to 4-38

Interrupt Status Register 1 (ISR1),

4-39 to 4-43

Interrupt Status Register 2 (ISR2),

4-44 to 4-47 page-in condition, 4-3

Parallel Poll Register (PPR), 4-48 register map, 4-2

Serial Poll Mode Register (SPMR),

4-49 to 4-50

Serial Poll Status Register (SPSR),

4-49 to 4-50

A

A[5-1] bit, Address Register (ADR), 4-11 acceptor handshake holdoffs

GPIB rdy message and RFD holdoffs choosing data-receiving mode, 5-14 data-receiving modes, 5-13 to 5-14 generating rdy message, 5-13 immediate RFD holdoff, 5-13

Accessory Register (ACCR) offset

(table), 4-3

Accessory Register A (ACCRA), 4-5

Accessory Register B (ACCRB), 4-6 to 4-7

Accessory Register E (ACCRE), 4-8

Accessory Register F (ACCRF), 4-9

Accessory Register I (ACCRI), 4-10

ACRDY bit, Source/Acceptor Status

Register (SASR), 3-60

Active Controller State changing states, 6-3 to 6-4 definition, 6-3

AD[5-0 -- 1-0] bits, Address Register 0

(ADR0), 3-9

AD[5-1 -- 1-1] bits, Address Register 1

(ADR1), 3-10

AD[5-1] bits, Address Register

(ADR), 3-8

Address Mode Register (ADMR), 3-5 to 3-7

Extended Dual Addressing mode, 3-6

Extended Single Addressing mode, 3-5

Listen Only (lon) mode, 3-6

No Addressing mode, 3-5

Normal Dual Addressing mode, 3-5

Talk Only (ton) mode, 3-6

TRM[1-0] bits, 3-7

Address Register (ADR)

7210 mode, 3-8

9914 mode, 4-11

Address Register 0 (ADR0), 3-9

Address Register 1 (ADR1), 3-10

Address Status Register (ADSR)

7210 mode, 3-11 to 3-13

9914 mode, 4-12 to 4-14

NAT7210 Reference Manual I-2



National Instruments Corp.

Index addressing, GPIB . See GPIB addressing.

ADHS bit, Source/Acceptor Status

Register (SASR), 3-60, 5-15

ADMR (Address Mode Register) . See

Address Mode Register (ADMR).

ADR (Address Register)

7210 mode, 3-8

9914 mode, 4-11

ADR0 (Address Register 0), 3-3, 3-9

ADR1 (Address Register 1), 3-3, 3-10

ADSC bit, Interrupt Status Register 2

(ISR2), 3-57

ADSC IE bit, Interrupt Mask Register 2

(IMR2), 3-57

ADSR (Address Status Register)

7210 mode, 3-11 to 3-13

9914 mode, 4-12 to 4-14

AEHS bit, Source/Acceptor Status

Register (SASR), 3-60

ANHS1 bit, Source/Acceptor Status

Register (SASR), 3-60

ANHS2 bit, Source/Acceptor Status

Register (SASR), 3-60, 5-13

ANSI/IEEE standard .

See IEEE 488.1 standard.

APT bit, Interrupt Status

Register 1 (ISR1)

7210 mode, 3-50 to 3-51

9914 mode, 4-41 to 4-42 implementing logical devices, 5-5

APT IE bit, Interrupt Mask

Register 1 (IMR1)

7210 mode, 3-50 to 3-51

9914 mode, 4-41 to 4-42

ARS bit, Address Register (ADR), 3-8

ATCT bit, Accessory Register B

(ACCRB), 4-7

ATN bit

Address Status Register

(ADSR), 4-12

Bus Control Register (BCR)/Bus

Status Register (BSR), 3-37, 4-28

ATN* bit, Address Status Register

(ADSR), 3-11

ATN (Attention) line, GPIB, B-9

ATNI bit

Interrupt Status Register 0

(ISR0), 3-47

Interrupt Status Register 2

(ISR2), 4-46

ATNI IE bit

Interrupt Mask Register 0

(IMR0), 3-47

Interrupt Mask Register 2

(IMR2), 4-46

Attention (ATN) line, GPIB, B-9

Auxiliary Command Register (AUXCR),

4-15 to 4-27

Chip Reset (ch_rst), 4-25

Clear Disable IMR2, IMR1, and

IMR0 Interrupts (~dai), 4-22

Clear Force Group Execute Trigger

(~fget), 4-19

Clear Holdoff On All Data

(~hdfa), 4-18

Clear Holdoff On END Only

(~hdfe), 4-19

Clear Listen Only (~lon), 4-20

Clear Page-In Registers (clrpi), 4-26

Clear Parallel Poll Flag (~ist), 4-25

Clear Request Parallel Poll

(~rpp), 4-21

Clear Request Service bit 2

(~rsv2), 4-24

Clear Return to Local (~rtl), 4-20

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National Instruments Corp.

I-3 NAT7210 Reference Manual

Index

Clear Send Interface Clear (~sic),

4-21, 6-1

Clear Send Remote Enable (~sre),

4-22, 6-2

Clear Shadow Handshaking

(~shdw), 4-23

Clear Short T1 Delay (~stdl), 4-23

Clear Software Reset (~swrst), 4-18

Clear Talk Only (~ton), 4-20

Clear Very Short T1 Delay

(~vstdl), 4-23

Go To Standby (gts), 4-20, 6-4

New Byte Available False

(nbaf), 4-19

Page-In Accessory Register

(piaccr), 4-27

Page-In Bus Register (pibcr), 4-26

Page-In End-of-String Registers

(pieosr), 4-26

Page-In Interrupt Mask Register 2

(piimr2), 4-25

Pass Through Next Secondary

(pts), 4-23

Release Control (rlc), 4-22

Release DAC Holdoff

(nonvalid), 4-18

Release DAC Holdoff (valid), 4-18

Release RFD Holdoff (rhdf),

4-18, 5-11

Request Control (rqc), 4-22

Request rsv False (reqf), 4-24

Request rsv True (reqt), 4-24, 5-16

Send EOI With The Next Byte

(feoi), 4-20

Set Disable IMR2, IMR1, and IMR0

Interrupts (dai), 4-22

Set Force Group Execute Trigger

(fget), 4-19

Set Holdoff On All Data (hdfa), 4-18

Set Holdoff On END Only

(hdfe), 4-19

Set Listen Only (lon), 4-20

Set Parallel Poll Flag (ist), 4-25

Set Request Parallel Poll (rpp),

4-21, 6-7

Set Request Service bit 2 (rsv2), 4-24

Set Return to Local (rtl), 4-20

Set Send Interface Clear (sic),

4-21, 6-1

Set Send Remote Enable (sre),

4-21, 6-2

Set Shadow Handshaking

(shdw), 4-23

Set Short T1 Delay (stdl), 4-23

Set Software Reset (swrst), 4-18

Set Talk Only (ton), 4-20

Set Very Short T1 Delay (vstdl), 4-23 summary of commands (table), 4-15 to 4-17

Switch To 7210 Mode (sw7210),

4-24, 5-1

Take Control Asynchronously (tca),

4-21, 6-4

Take Control Synchronously

(tcs), 4-21

Auxiliary Mode Register (AUXMR),

3-14 to 3-26

Chip Reset, 3-19

Clear ADSC, 3-26

Clear ATNI, 3-26

Clear DEC, 3-25

Clear DET, 3-25

Clear END, 3-25

Clear ERR, 3-25, 6-5

Clear IFC (~sic & rsc), 3-22

Clear IFCI, 3-26

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National Instruments Corp.

Clear LOKC, 3-26

Clear Or Pulse Return To Local

(rtl), 3-20

Clear Parallel Poll Flag (~ist), 3-18

Clear REMC, 3-26

Clear REN (~sre & rsc), 3-23

Clear SRQI Command, 3-26

Clear SYNC, 3-26

Disable System Control (~rsc),

3-22, 6-2

Execute Parallel Poll (rpp1), 3-24

Finish Handshake (rhdf), 3-19

Go To Standby (gts), 3-21

Holdoff Handshake Immediately

(hldi), 3-25, 5-2, 5-13

Immediate Execute Power-On

(pon), 3-18

Listen (ltn), 3-22

Listen In Continuous Mode

(ltn & cont), 3-24

Local Unlisten (lun), 3-24

New Byte Available False

(nbaf), 3-21

Nonvalid Secondary Command Or

Address (nonvalid), 3-20

Page-In Additional Registers

(page-in), 3-25 register map, 3-4

Release Control Command

(rlc), 3-20

Request Control Command

(rqc), 3-20

Request rsv False (reqf), 3-23

Request rsv True (reqt), 3-23

Send EOI (seoi), 3-20

Set IFC (sic & rsc), 3-24

Set Parallel Poll Flag (ist), 3-18

Set REN (sre & rsc), 3-25

Index

Set Return To Local (rtl), 3-20

Set SYNC, 3-26 summary of auxiliary commands

(table), 3-15 to 3-17

Switch To 9914A Mode

(sw9914), 3-22

Take Control Asynchronously

(tca), 3-21

Take Control Synchronously

(tcs), 3-22

Take Control Synchronously On

END (tcse), 3-23

Trigger (trig), 3-19

Unlisten (lul), 3-21

Untalk (lut), 3-21

Valid Secondary Command Or

Address (valid), 3-21 writing to hidden registers, 3-14

Auxiliary Register A (AUXRA), 3-27 to 3-28

Auxiliary Register B (AUXRB), 3-29 to 3-30

Auxiliary Register E (AUXRE), 3-31

Auxiliary Register F (AUXRF), 3-32

Auxiliary Register G (AUXRG), 3-33 to 3-34

Auxiliary Register I (AUXRI), 3-35 to 3-36

B

B2 bit, 5-10

BCR (Bus Control Register)/BSR

(Bus Status Register)

7210 mode, 3-37 to 3-38

9914 mode, 4-28 to 4-29

BI bit, Interrupt Status Register 0

(ISR0), 4-36

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National Instruments Corp.

I-5 NAT7210 Reference Manual

Index

BI IE bit, Interrupt Mask Register 0

(IMR0), 4-36

BIN bit

Accessory Register A (ACCRA), 4-5

Auxiliary Register A

(AUXRA), 3-27 bits

A[5-1], 4-11

ACRDY, 3-60

AD[5-0 -- 1-0], 3-9

AD[5-1], 3-8

AD[5-1 -- 1-1], 3-10

ADHS, 3-60, 5-15

ADSC, 3-57

ADSC IE, 3-57

AEHS, 3-60

ANHS1, 3-60

ANHS2, 3-60, 5-13

APT, 3-50 to 3-51, 4-41 to 4-42, 5-5

APT IE, 3-50 to 3-51, 4-41 to 4-42

ARS, 3-8

ATCT, 4-7

ATN, 3-37, 4-12, 4-28

ATN*, 3-11

ATNI, 3-47, 4-46

ATNI IE, 3-47, 4-46

B2, 5-10

BI, 4-36

BI IE, 4-36

BIN, 3-27, 4-5

BO, 4-36

BO IE, 4-36

CHES, 3-34

CIC, 3-11, 4-47

CIC IE, 4-47

CO, 3-56, 6-4, 6-5

CO IE, 3-56, 6-5

CPT, 3-49 to 3-50, 5-6

NAT7210 Reference Manual I-6

CPT ENABLE, 3-30

CPT IE, 3-49 to 3-50, 5-19

CPT[7-0], 3-40, 4-31 dal, 4-11 dat, 4-11

DAV, 3-37, 4-28

DCAS, 4-42

DCAS IE, 4-42

DEC, 3-52, 5-19

DEC IE, 3-52, 5-19

DET, 3-51, 5-19

DET IE, 3-51, 5-19

DHADC, 3-31, 4-8, 5-19

DHADT, 3-31, 4-8, 5-19

DHALA, 3-32, 4-9, 5-6

DHALL, 3-32, 4-9, 5-7

DHATA, 3-32, 4-9, 5-6

DHDC, 3-31, 5-19

DHDT, 3-31, 5-19

DHUNTL, 3-32, 4-9

DI, 3-53, 5-11

DI IE, 3-53, 5-11

DIO[8-1], 3-39, 3-41, 4-30, 4-32

DISTCT, 3-34

DL, 3-8, 5-4

DL0, 3-9

DL1, 3-10

DMAE, 4-10

DMAI, 3-56, 4-36

DMAO, 3-56, 4-35

DO, 3-53, 5-8

DO IE, 3-53, 5-8

DT, 3-8, 5-4

DT0, 3-9

DT1, 3-10 edpa, 4-11

END, 4-37

END IE, 3-51 to 3-52, 4-37

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National Instruments Corp.

END RX, 3-51 to 3-52, 5-11

EOI, 3-10, 3-37, 4-27, 5-11

EOS, 3-47, 4-45, 5-11

EOS[7-0], 3-42, 4-33

ERR, 3-52 to 3-53, 4-40, 5-8, 6-5

ERR IE, 3-52 to 3-53, 4-40, 5-8, 6-5

F(3-0), 3-43, 4-34

GET, 4-39 to 4-40

GET IE, 4-39 to 4-40

GLINT, 3-45, 4-44

HLDA, 3-28

HLDE, 3-28

IFC, 3-37, 4-27, 4-43

IFC IE, 4-43

IFCI, 3-47

IFCI IE, 3-47

INT, 3-54 to 3-55

INT0, 4-35

INT1, 4-36

INV, 3-29, 4-6

ISS, 3-29, 4-6

LA, 3-12, 4-13, 5-4

LLO, 4-12

LLOC, 4-46

LLOC IE, 4-46

LOK, 3-56, 5-18

LOKC, 3-57, 5-18

LOKC IE, 3-57

LPAS, 3-12, 4-12, 5-4

LWC, 4-6

MA, 4-42 to 4-43

MA IE, 4-42 to 4-43

MAC, 4-38

MAC IE, 4-38

MICR, 3-44

MJMN, 3-13, 5-4, 5-5 nba, 3-45, 3-60, 4-44

NDAC, 3-37, 4-28

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National Instruments Corp.

I-7

NL, 3-46, 4-45

NLEN, 3-47, 4-46

NRFD, 3-37, 4-28

NTNL, 3-33 to 3-34, 5-7, 6-5

P[3-1], 3-59

PEND, 3-63, 4-49, 5-16

PP1, 4-10

PP2, 3-35, 5-17

PP8-PP1, 4-48

REM, 3-56, 4-12, 5-18

REMC, 3-57, 5-18

REMC IE, 3-57

REN, 3-37, 4-27

REOS, 3-27, 4-5

RLC, 4-37 to 4-38

RLC IE, 4-37 to 4-38

RPP2, 3-34, 6-7 rsv/RQS, 3-63, 4-50

S, 3-59

S[6-1], 3-62, 4-49

S8, 3-62, 4-49

SH1A, SH1B, 3-61

SISB, 3-35 to 3-36

SLOW, 3-44

SPAS, 4-37

SPAS IE, 4-37

SPEOI, 3-30, 4-7

SPMS, 3-11

SRQ, 3-37, 4-28, 4-43

SRQ IE, 4-43

SRQI, 3-55

SRQI IE, 3-55

STBO, 3-46, 4-45

STBO IE, 3-46, 4-45, 5-16

SYNC, 3-48, 6-4

SYNC IE, 3-48

TA, 3-12 to 3-13, 4-13, 5-4

TPAS, 3-12, 4-13, 5-4

Index

NAT7210 Reference Manual

Index

TRI, 3-29

TRM[1-0], 3-7

U, 3-58, 5-18 ulpa, 4-14

UNC, 4-40 to 4-41

UNC IE, 4-40 to 4-41

USTD, 3-35, 4-10, 5-2, 5-10

V[3-0], 3-64

X, 3-9, 3-64

XEOS, 3-27, 4-5

BO bit, Interrupt Status Register 0

(ISR0), 4-36

BO IE bit, Interrupt Mask Register 0

(IMR0), 4-36

Bus Control Register (BCR)/Bus Status

Register (BSR)

7210 mode, 3-37 to 3-38

9914 mode, 4-28 to 4-29

C

capabilities codes (table), 1-1 to 1-2

CDOR (Command/Data Out Register)

7210 mode, 3-39

9914 mode, 4-30

CHES bit, Auxiliary Register G

(AUXRG), 3-34 chip initialization sequence asserting local pon message, 5-1 clearing local pon message, 5-3 configuring chip for GPIB operation, 5-2 enabling interrupts, 5-2 placing NAT7210 in 7210 mode, 5-1 setting clock frequency, 5-1

Chip Reset (chip_reset) command,

Auxiliary Mode Register

(AUXMR), 3-19 asserting local pon message, 5-1 clearing RFD holdoff condition, 5-13

Chip Reset (ch_rst) command, Auxiliary

Command Register

(AUXCR), 4-26

CIC bit

Address Status Register

(ADSR), 3-11

Interrupt Status Register 2

(ISR2), 4-47

CIC IE bit, Interrupt Mask Register 2

(IMR2), 4-47

CIC internal signal, 7-1 to 7-2

Clear ADSC command, 3-26

Clear ATNI command, 3-26

Clear DEC command, 3-25

Clear DET command, 3-25

Clear Disable IMR2, IMR1, and IMR0

Interrupts (~dai) command, 4-22

Clear END command, 3-25

Clear ERR command, 3-25, 6-5

Clear Force Group Execute Trigger

(~fget) command, 4-19

Clear Holdoff On All Data (~hdfa) command, 4-18

Clear Holdoff On END Only (~hdfe) command, 4-19

Clear IFC (~sic & rsc) command, 3-22

Clear IFCI command, 3-26

Clear Listen Only (~lon) command, 4-20

Clear LOKC command, 3-26

Clear Or Pulse Return To Local (rtl) command, 3-20

Clear Page-In Registers (clrpi) command, 4-26

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National Instruments Corp.

Index

Clear Parallel Poll Flag (~ist) command

Auxiliary Command Register

(AUXCR), 4-25

Auxiliary Mode Register

(AUXMR), 3-18

Clear REMC command, 3-26

Clear REN (~sre & rsc) command, 3-23

Clear Request Parallel Poll (~rpp) command, 4-21

Clear Request Service bit 2 (~rsv2) command, 4-24

Clear Return to Local (~rtl) command, 4-20

Clear Send Interface Clear (~sic) command, 4-21, 6-1

Clear Send Remote Enable (~sre) command, 4-22, 6-2

Clear Shadow Handshaking (~shdw) command, 4-23

Clear Short T1 Delay (~stdl) command, 4-23

Clear Software Reset (~swrst) command, 4-18

Clear SRQI Command, 3-26

Clear SYNC command, 3-26

Clear Talk Only (~ton) command, 4-20

Clear Very Short T1 Delay (~vstdl) command, 4-23 clearing devices, 5-19, B-28

CLK signal requirements, 7-5 timing diagram, 7-5 clock frequency. See also Internal Count

Register (ICR).

setting, 5-1 difference between rates, A-1 clock frequency bits F(3-0), Internal

Count Register (ICR), 3-43, 4-34 clrpi (Clear Page-In Registers) command, 4-26

CO bit, Interrupt Status Register 2 (ISR2),

3-56 to 3-57, 6-4, 6-5

CO IE bit, Interrupt Mask Register 2

(IMR2), 3-56 to 3-57, 6-5

Command/Data Out Register (CDOR)

7210 mode, 3-39

9914 mode, 4-30 command messages, GPIB, B-17, B-19 .

See also GPIB messages.

Command Pass Through Register

(CPTR)

7210 mode, 3-40

9914 mode, 4-31 commands . See Auxiliary Command

Register (AUXCR); Auxiliary Mode

Register (AUXMR); Standard

Commands for Programmable

Instrumentation (SCPI).

continuous mode, 5-14 controller software considerations . See

GPIB Controller; System Controller.

count termination method, GPIB, B-20 to B-21

CPT bit implementing logical devices, 5-6

Interrupt Status Register 1 (ISR1),

3-49 to 3-50

CPT ENABLE bit, Auxiliary Register B

(AUXRB), 3-30

CPT IE bit, Interrupt Mask Register 1

(IMR1), 3-49 to 3-50, 5-19

CPT[7-0] bits, Command Pass Through

Register (CPTR), 3-40, 4-31

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National Instruments Corp.

I-9 NAT7210 Reference Manual

Index

CPTR (Command Pass Through Register)

7210 mode, 3-40

9914 mode, 4-31

CPU address bus, 7-3

CPU data bus, 7-3

CPU interface capabilities, 1-3

CPU register control pins

CPU data bus, 7-3

CS* and CPU address bus, 7-3

RD*/WR* pins, 7-3 customer communication, xv , F-1

D

DAC holdoff determining occurrence of, 5-15 purpose and use, 5-14 to 5-15

DACK* signal, 5-8, 5-12, 7-4

~dai (Clear Disable IMR2, IMR1, and

IMR0 Interrupts) command, 4-22 dai (Set Disable IMR2, IMR1, and IMR0

Interrupts) command, 4-22 dal bit, Address Register (ADR), 4-11 dat bit, Address Register (ADR), 4-11 data bus pins, GPIB, 7-3

Data In Register (DIR)

7210 mode, 3-41

9914 mode, 4-32 data lines, GPIB, B-7 data messages, GPIB . See GPIB data messages.

data-receiving modes . See GPIB rdy message and RFD holdoffs.

Data Valid (DAV) line, GPIB, B-12

DAV bit, Bus Control Register (BCR)/

Bus Status Register (BSR), 3-37, 4-28

DCAS (Device Clear Active State), 5-19

DCAS bit, Interrupt Status Register 1

(ISR1), 4-42

DCAS IE bit, Interrupt Mask Register 1

(IMR1), 4-42

DCL (Device Clear) command, 5-19

DEC bit, Interrupt Status Register 1

(ISR1), 3-52, 5-19

DEC IE bit, Interrupt Mask Register 1

(IMR1), 3-52, 5-19

DET bit, Interrupt Status Register 1

(ISR1), 3-51, 5-19

DET IE bit, Interrupt Mask Register 1

(IMR1), 3-51, 5-19

Device Clear Active State (DCAS), 5-19

Device Clear (DCL) command, 5-19 device status reporting (polling) . See parallel polling; serial polling.

Device Trigger Active State

(DTAS), 5-19 devices clearing, 5-19, B-28 triggering, 5-19, B-28

DHADC bit

Accessory Register E (ACCRE), 4-8

Auxiliary Register E (AUXRE), 3-31 device clearing, 5-19

DHADT bit

Accessory Register E (ACCRE), 4-8

Auxiliary Register E (AUXRE), 3-31 device triggering, 5-19

DHALA bit

Accessory Register F (ACCRF), 4-9

Auxiliary Register F (AUXRF), 3-32 implementing logical devices, 5-6

DHALL bit

Accessory Register F (ACCRF), 4-9

Auxiliary Register F (AUXRF), 3-32 implementing logical devices, 5-7

NAT7210 Reference Manual I-10

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National Instruments Corp.

Index

DHATA bit

Accessory Register F (ACCRF), 4-9

Auxiliary Register F (AUXRF), 3-32 implementing logical devices, 5-6

DHDC bit, Auxiliary Register E

(AUXRE), 3-31, 5-19

DHDT bit, Auxiliary Register E

(AUXRE), 3-31, 5-19

DHUNTL bit

Accessory Register F (ACCRF), 4-9

Auxiliary Register F (AUXRF), 3-32

DI bit, Interrupt Status Register 1 (ISR1) description, 3-53 receiving GPIB data messages, 5-11

DI IE bit, Interrupt Mask

Register 1 (IMR1) description, 3-53 receiving GPIB data message, 5-11

DIO[8-1] bits

Command/Data Out Register

(CDOR), 3-39, 4-30

Data In Register (DIR), 3-41, 4-32

DIR (Data In Register)

7210 mode, 3-41

9914 mode, 4-32

Disable System Control (~rsc) command,

3-22, 6-2

DISTCT bit, Auxiliary Register G

(AUXRG), 3-34

DL bit

Address Register (ADR), 3-8 implementing logical devices, 5-4

DL0 bit, Address Register 0 (ADR0), 3-9

DL1 bit, Address Register 1

(ADR1), 3-10

DMA receiving GPIB data messages, 5-11 sending GPIB data messages, 5-7

DMA pins

DACK*, 7-4

DRQ, 7-3 to 7-4

DMAE bit, Accessory Register I

(ACCRI), 4-10

DMAI bit

Interrupt Mask Register 0

(IMR0), 4-36

Interrupt Mask Register 2

(IMR2), 3-56

DMAO bit

Interrupt Mask Register 0

(IMR0), 4-35

Interrupt Mask Register 2

(IMR2), 3-56

DO bit, Interrupt Status Register 1 (ISR1) description, 3-53 sending GPIB data messages, 5-8

DO IE bit, Interrupt Mask

Register 1 (IMR1) description, 3-53 sending GPIB data messages, 5-8 documentation conventions used in manual, xiv mnemonics key, E-1 to E-11 organization of manual, xiii xiv related documentation, xiv-xv

DRQ signal, 7-3 to 7-4

DT bit

Address Register (ADR), 3-8 implementing logical devices, 5-4

DT0 bit, Address Register 0 (ADR0), 3-9

DT1 bit, Address Register 1

(ADR1), 3-10

DTAS (Device Trigger Active

State), 5-19

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National Instruments Corp.

I-11 NAT7210 Reference Manual

Index

E

edpa bit, Address Register (ADR), 4-11 electrical specifications, GPIB, B-13 to B-14

END bit, Interrupt Status Register 0

(ISR0), 4-37

END IE bit

Interrupt Mask Register 0

(IMR0), 4-37

Interrupt Mask Register 1 (IMR1),

3-51 to 3-52

END message, receiving, 5-11

End-of-String Register (EOSR)

7210 mode, 3-42

9914 mode, 4-32

End-or-Identify (EOI) line, GPIB,

5-17, B-10

END RX bit, Interrupt Status

Register 1 (ISR1) description, 3-51 to 3-52 receiving GPIB data messages, 5-11

EOI, sending . See Send EOI

(seoi) command.

EOI bit

Address Register 1 (ADR1), 3-10

Bus Control Register (BCR)/Bus

Status Register (BSR), 3-37, 4-28 receiving GPIB data message, 5-11

EOI (End-or-Identify) line, GPIB,

5-17, B-10

EOI termination method, GPIB, B-20

EOIOE internal signal, 7-2

EOS bit

Interrupt Status Register 0

(ISR0), 3-47

Interrupt Status Register 2

(ISR2), 4-46 receiving GPIB data message, 5-11

EOS message receiving, 5-11 sending, 5-8

EOS termination method, GPIB, B-20

EOS[7-0] bits, End-of-String Register

(EOSR), 3-42, 4-33

EOSR (End-of-String Register)

7210 mode, 3-42

9914 mode, 4-33

ERR bit, Interrupt Status

Register 1 (ISR1) description, 3-52 to 3-53, 4-40 sending GPIB data messages, 5-8 sending remote multiline messages, 6-5

ERR IE bit, Interrupt Mask

Register 1 (IMR1) description, 3-52 to 3-53, 4-40 sending GPIB data messages, 5-8 sending remote multiline messages, 6-5

ESB (Event Status Bit), B-23

Event Status Register (ESR), B-23, B-24

Execute Parallel Poll (rpp1) command, 3-24 extended addressing .

See GPIB addressing.

F

F(3-0) bits, Internal Count Register

(ICR), 3-43, 4-34 feoi (Send EOI With The Next Byte) command, 4-20

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National Instruments Corp.

~fget (Clear Force Group Execute

Trigger) command, 4-19 fget (Set Force Group Execute Trigger) command, 4-19

Finish Handshake (rhdf) command, 3-19

G

General Purpose Interface Bus . See GPIB.

generating hardware interrupts, 5-18

GET bit, Interrupt Status Register 1

(ISR1), 4-38 to 4-40

GET (Group Execute Trigger) command, 5-19

GET IE bit, Interrupt Mask Register 1

(IMR1), 4-39 to 4-40

GLINT bit

Interrupt Mask Register 0

(IMR0), 3-45

Interrupt Mask Register 2

(IMR2), 4-44

Go To Standby (gts) command

Auxiliary Command Register

(AUXCR), 4-20

Auxiliary Mode Register

(AUXMR), 3-21 changing controller states, 6-4

GPIB addressing protocol, B-17 to B-19.

See also GPIB addressing.

examples, B-18 reading multiline interface command messages table, B-19 secondary addressing, B-19 unaddressing command messages, B-19 clearing devices, B-28



National Instruments Corp.

I-13

Index

Controller . See GPIB Controller.

data and command messages, B-17 data lines, B-7 handshake lines, B-11 to B-13

Data Valid (DAV), B-12

Not Data Accepted

(NDAC), B-12

Not Ready For Data (NRFD),

5-12, B-11 three-wire handshake process, B-13 hardware configuration, B-4 to B-6 history, B-1

IEEE 488.1 specification, B-2

IEEE 488.2 specification, B-2 to B-3 interface management lines, B-8 to B-11

Attention (ATN), B-9

End-or-Identify (EOI),

5-17, B-10

Interface Clear (IFC), B-8

Remote Enable (REN), B-10

Service Request (SRQ), B-11

Listeners, 5-7, B-15 to B-16 parallel polling, B-25 to B-27. See also parallel polling.

configuring devices, B-26 determining PPE message, B-27 determining value of PPR message, B-26 example exchange of messages

(illustration), B-25 overview, B-25 physical representation of PPR message, B-27 physical and electrical specifications,

B-13 to B-14

SCPI specification, B-3 to B-4

NAT7210 Reference Manual

Index serial polling. See also serial polling.

ESR and SRE registers, B-23 serial polling devices, B-21 to B-22 servicing SRQs, B-21 status byte model for

IEEE 488.1, B-23 status byte model for

IEEE 488.2, B-23 to B-24 signals and lines, B-7

Talkers, 5-7, B-15 to B-16 termination methods, B-19 to B-21 combinations of methods, B-21 count method, B-20

EOI method, B-20

EOS method, B-20 triggering devices, B-28

GPIB addressing addressing protocol, B-17 to B-19 examples, B-18 format of address command messages, B-17 primary address, B-17 reading multiline interface command messages table, B-19 secondary addressing, B-19 unaddressing command messages, B-19 unique addresses, B-17 implementing one logical device extended addressing, 5-4 normal addressing, 5-4 implementing three or more logical devices extended addressing, 5-6 to 5-7 normal addressing, 5-5 to 5-6 implementing two logical devices extended addressing, 5-5 normal addressing, 5-4 logical and physical devices, 5-3 normal and extended addressing, 5-3 setting addresses, 5-2

GPIB Controller. See also GPIB addressing; System Controller.

Active Controller State, 6-3 basic states, 6-2 to 6-3 determining, 6-3 changing states

Active State to Idle State, 6-5

Active State to Standby

State, 6-4 becoming CIC, 6-3 to 6-4

Idle State to Active State, 6-3 to 6-4

Standby State to Active

State, 6-4

Controller-In-Charge (CIC), B-14 defining System Controller, B-14

Idle Controller State, 6-2 to 6-3 polling, 6-5 to 6-7 configuring devices for parallel polls, 6-6 parallel polls, 6-7 serial polls, 6-6 responsibilities, B-14 sending remote multiline messages

(commands), 6-5

Standby Controller State, 6-3

GPIB data bus pins, 7-3

NAT7210 Reference Manual I-14

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National Instruments Corp.

Index

GPIB data messages.

See also GPIB messages.

compared with commands, B-17 receiving basic flow, 5-11 performing RFD holdoff on last data byte, 5-12 receiving END or EOS, 5-11 using DMA, 5-12 sending, 5-7 to 5-11 basic flow, 5-7 to 5-8 sending EOI or EOS, 5-8

T1 delay generation

7210 mode, 5-10

9114 mode, 5-10

HSTS definition, 5-9

IEEE 488.1 standard requirements, 5-9 using DMA, 5-8 using nbaf, 5-11

GPIB features of NAT7210 chip, 1-3

GPIB handshake parameters, setting . See

T1 delay generation.

GPIB messages.

See also GPIB data messages.

data messages compared with command messages, B-17 format of address command messages, B-17 mnemonics key, E-1 to E-11 multiline interface command messages, D-1 to D-3 sending remote multiline messages, 6-5 unaddressing command messages, B-19

GPIB rdy message and RFD holdoffs,

5-12 to 5-14 choosing data-receiving mode, 5-14 data-receiving modes, 5-13 to 5-14 continuous (cont), 5-14 normal, 5-13

RFD Holdoff on All Data

(hlda), 5-13

RFD Holdoff on END

(hlde), 5-14 generating rdy message, 5-13

GPIB signal pins, 7-2

GPIB transceiver controls

CIC internal signal, 7-1 to 7-2

EOIOE internal signal, 7-2

PE internal signal, 7-2

T/R1, 7-1

T/R2 and T/R3, 7-1 to 7-2

TRIG internal signal, 7-2

GPIB transceivers, interfacing, 7-6

Group Execute Trigger (GET) command, 5-19 gts (Go To Standby) command

Auxiliary Command Register

(AUXCR), 4-20

Auxiliary Mode Register

(AUXMR), 3-21 changing controller states, 6-4

H

handshake lines, GPIB, B-11 to B-13

Data Valid (DAV), B-12

Not Data Accepted (NDAC), B-12

Not Ready For Data (NRFD),

5-12, B-11 three-wire handshake process, B-13

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National Instruments Corp.

I-15 NAT7210 Reference Manual

Index handshake parameters, setting . See T1 delay generation.

hardware configuration, GPIB, B-4 to B-6 hardware considerations interfacing to common GPIB transceivers, 7-6 pin descriptions

CPU register control pins, 7-3

DMA pins, 7-3 to 7-4

GPIB data bus pins, 7-3

GPIB signal pins, 7-2

GPIB transceiver controls, 7-1 to 7-2 other pins, 7-4 to 7-5 hardware interrupts, generating, 5-18

~hdfa (Clear Holdoff On All Data) command, 4-18 hdfa (Set Holdoff On All Data) command, 4-18

~hdfe (Clear Holdoff On END Only) command, 4-19 hdfe (Set Holdoff On END Only) command, 4-19

Hewlett-Packard Interface Bus

(HP-IB), B-1 hidden registers

7210-mode interface registers address register map, 3-3 auxiliary mode register map, 3-4 writing to hidden registers, 3-14

Accessory Register (ACCR) offset

(table), 4-3

HLDA bit, Auxiliary Register A

(AUXRA), 3-28 hlda mode, 5-13

HLDE bit, Auxiliary Register A

(AUXRA), 3-28 hlde mode, 5-14 hldi (Holdoff Handshake Immediately) command definition, 3-25 performing RFD holdoff, 5-2,

5-11, 5-13

HSTS signals, T1 delay generation,

5-9, 5-10

I

ICR (Internal Count Register)

7210 mode, 3-43

9914 mode, 4-34

ICR2 (Internal Count Register 2), 3-44

Idle Controller State changing states, 6-3 to 6-4 definition, 6-2 to 6-3

IEEE 488 Bus . See GPIB.

IEEE 488 interface capabilities (table),

1-1 to 1-2

IEEE 488.1 standard history, B-1

NAT7210 compatibility, 1-1 problems with IEEE 488.1 compatible devices, B-2 requirements for T1 delay generation, 5-9 specification, B-2 status byte model for serial polling, B-23

IEEE 488.2 service requesting, 5-15 to 5-16

IEEE 488.2 standard history, B-1 specification, B-2 to B-3 status byte model for serial polling,

B-23 to B-24

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National Instruments Corp.

Index

IEEE Standard 488.1-1987, 1-1

IFC bit

Bus Control Register (BCR)/Bus

Status Register (BSR), 3-37, 4-28

Interrupt Status Register 1

(ISR1), 4-43

IFC IE bit, Interrupt Mask Register 1

(IMR1), 4-43

IFC (Interface Clear) signal, 6-1, 6-2, B-8

IFCI bit, Interrupt Status Register 0

(ISR0), 3-47

IFCI IE bit, Interrupt Mask Register 0

(IMR0), 3-47

Immediate Execute Power-On (pon) command, 3-18

IMR0 (Interrupt Mask Register 0)

7210 mode, 3-45 to 3-48

9914 mode, 4-35 to 4-38

IMR1 (Interrupt Mask Register 1)

7210 mode, 3-49 to 3-53

9914 mode, 4-39 to 4-43

IMR2 (Interrupt Mask Register 2)

7210 mode, 3-54 to 3-57

9914 mode, 4-44 to 4-47 initialization sequence . See chip initialization sequence.

INT bit, Interrupt Status Register 2

(ISR2), 3-54 to 3-55

INT pin, 7-4

INT0 bit, Interrupt Status Register 0

(ISR0), 4-35

INT1 bit, Interrupt Status Register 0

(ISR0), 4-36

Interface Clear (IFC) line, GPIB, 6-1,

6-2, B-8 interface management lines, GPIB, B-8 to B-11

Attention (ATN), B-9

End-or-Identify (EOI), B-10

Interface Clear (IFC), B-8

Remote Enable (REN), B-10

Service Request (SRQ), B-11

Internal Count Register (ICR)

7210 mode, 3-43

9914 mode, 4-34 and fractional output frequencies, A-2

Internal Count Register 2 (ICR2), 3-44

Interrupt Mask Register 0 (IMR0)

7210 mode, 3-45 to 3-48

9914 mode, 4-34 to 4-38

Interrupt Mask Register 1 (IMR1)

7210 mode, 3-49 to 3-53

9914 mode, 4-39 to 4-43

Interrupt Mask Register 2 (IMR2)

7210 mode, 3-54 to 3-57

9914 mode, 4-44 to 4-47

Interrupt Status Register 0 (ISR0)

7210 mode, 3-45 to 3-48

9914 mode, 4-35 to 4-38

Interrupt Status Register 1 (ISR1)

7210 mode, 3-49 to 3-53

9914 mode, 4-39 to 4-43

Interrupt Status Register 2 (ISR2)

7210 mode, 3-54 to 3-57

9914 mode, 4-44 to 4-47 interrupts, enabling, 5-2

INV bit

Accessory Register B (ACCRB), 4-6

Auxiliary Register B

(AUXRB), 3-29

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National Instruments Corp.

I-17 NAT7210 Reference Manual

Index

ISR0 (Interrupt Status Register 0)

7210 mode, 3-45 to 3-48

9914 mode, 4-35 to 4-38

ISR1 (Interrupt Status Register 1)

7210 mode, 3-49 to 3-53

9914 mode, 4-37 to 4-43

ISR2 (Interrupt Status Register 2)

7210 mode, 3-54 to 3-57

9914 mode, 4-44 to 4-47

ISS bit

Accessory Register B (ACCRB), 4-6

Auxiliary Register B

(AUXRB), 3-29

~ist (Clear Parallel Poll Flag) command

Auxiliary Command Register

(AUXCR), 4-25

Auxiliary Mode Register

(AUXMR), 3-18 ist (Set Parallel Poll Flag) command

Auxiliary Command Register

(AUXCR), 4-25

Auxiliary Mode Register

(AUXMR), 3-18 ist message, 5-17

L

LA bit

Address Status Register (ADSR),

3-12, 4-13 implementing logical devices, 5-3

Listen (ltn) command, 3-22

Listen In Continuous Mode (ltn & cont) command, 3-24

Listeners. See also GPIB addressing;

GPIB Controller; Talkers.

activating, 5-7 detecting GPIB Listeners, 5-7 programmed implementation, 5-7 properties, B-15 system setup example

(illustration), B-16

LLO bit, Address Status Register

(ADSR), 4-12

LLOC bit, Interrupt Status Register 2

(ISR2), 4-46

LLOC IE bit, Interrupt Mask Register 2

(IMR2), 4-46

Local Unlisten (lun) command, 3-24 logical devices, addressing . See GPIB addressing.

LOK bit, Interrupt Status Register 2

(ISR2), 3-56, 5-18

LOKC bit, Interrupt Status Register 2

(ISR2), 3-57, 5-18

LOKC IE bit, Interrupt Mask Register 2

(IMR2), 3-57

~lon (Clear Listen Only) command, 4-20 lon (Set Listen Only) command, 4-20

LPAS bit

Address Status Register (ADSR),

3-12, 4-12 implementing logical devices, 5-4 ltn & cont (Listen In Continuous Mode) command, 3-24 ltn (Listen) command, 3-22 lul (Unlisten) command, 3-21 lun (Local Unlisten) command, 3-24 lut (Untalk) command, 3-21

LWC bit, Accessory Register B

(ACCRB), 4-6

M

MA bit, Interrupt Status Register 1

(ISR1), 4-42 to 4-43

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National Instruments Corp.

Index

MA IE bit, Interrupt Mask Register 1

(IMR1), 4-42 to 4-43

MAC bit, Interrupt Status Register 0

(ISR0), 4-38

MAC IE bit, Interrupt Mask Register 0

(IMR0), 4-38 manual . See documentation.

MAV (Message Available) bit, B-23 messages, GPIB . See GPIB messages.

MICR bit, Internal Count Register 2

(ICR2), 3-45

MJMN bit

Address Status Register

(ADSR), 3-13 implementing logical devices,

5-4, 5-5

MLA command, 6-6 mnemonics key, E-1 to E-11 modes of operation

7210 and 9914 modes, 2-3 changing between modes, 2-3

MSA command, 6-6

MSS (Master Summary Status) bit, B-23

MTA command, 6-6 multiline messages mnemonics and definitions, D-1 to D-3 reading, B-19 sending, 6-5

N

NAT7210 Controller chip. See also 7210mode interface registers; 9914-mode interface registers.

architecture, 2-1 to 2-3 block diagram, 2-2 changing mode of operation, 2-3 chip initialization sequence, 5-1 to 5-3 compatibility with NEC

µ

PD7210 and TI TMS9914A chips, 1-1 components, 2-1

CPU interface capabilities, 1-3 definition, 1-1

GPIB features, 1-3

IEEE 488 interface capabilities

(table), 1-1 to 1-2 implementation block diagram, 1-4 modes of operation, 2-3 placing in 7210 mode, 5-1 purpose, 1-1 transceiver requirements, 1-4 nba bit

Interrupt Status Register 0

(ISR0), 3-45

Interrupt Status Register 2

(ISR2), 4-44

Source/Acceptor Status Register

(SASR), 3-60 nbaf (New Byte Available False) command

Auxiliary Command Register

(AUXCR), 4-19

Auxiliary Mode Register

(AUXMR), 3-21

NDAC bit, Bus Control Register (BCR)/

Bus Status Register (BSR), 3-37, 4-28

New Byte Available False (nbaf) command

Auxiliary Command Register

(AUXCR), 4-19

Auxiliary Mode Register

(AUXMR), 3-21

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National Instruments Corp.

I-19 NAT7210 Reference Manual

Index

NL bit

Interrupt Status Register 0

(ISR0), 3-46

Interrupt Status Register 2

(ISR2), 4-45

NLEN bit

Interrupt Mask Register 0

(IMR0), 3-47

Interrupt Mask Register 2

(IMR2), 4-46

Nonvalid Secondary Command Or

Address (nonvalid) command,

AUXMR, 3-20 normal addressing . See GPIB addressing.

Not Data Accepted (NDAC) line

GPIB, B-12

Not Ready For Data (NRFD) line, GPIB,

5-12, B-11

NRFD bit, Bus Control Register (BCR)/

Bus Status Register (BSR), 3-37, 4-28

NTNL bit, Auxiliary Register G

(AUXRG) description, 3-33 to 3-34 sending GPIB data messages, 5-7 sending remote multiline messages, 6-5

P

P[3-1] bit, Parallel Poll Register

(PPR), 3-59

Page-In Accessory Register (piaccr) command, 4-27

Page-In Additional Registers (page-in) command, 3-25

Page-In Bus Register (pibcr) command, 4-26

Page-In End-of-String Registers (pieosr) command, 4-26

Page-In Interrupt Mask Register 2

(piimr2) command, 4-25

Page-In state

7210 mode interface registers, 3-3

9914 mode, 4-3 how to page-in, 3-3

Parallel Poll Register (PPR)

7210 mode, 3-58 to 3-59

9914 mode, 4-48 parallel polling configuring initial parallel poll response, 5-2 determining value of PPR message, B-26 example exchange of messages

(illustration), B-25

GPIB controller, 6-5 to 6-7 conducting parallel polls, 6-7 configuring devices for parallel polls, 6-6, B-26 overview, B-25

PPE message, determining, B-27

PPR message determining value of, B-27 physical representation of, B-27 requesting service asserting SRQ signal, 5-15

IEEE 488.2 service requesting,

5-15 to 5-16

7210-style service requesting, 5-16 responding to parallel polls, 5-17 disabling response, 5-18 local configuration, 5-17 remote configuration, 5-17

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National Instruments Corp.

Index

Pass Through Next Secondary (pts) command, 4-23

PE internal signal, 7-2

PEND bit requesting polling service, 5-16

Serial Poll Mode Register

(SPMR), 3-63

Serial Poll Status Register

(SPSR), 4-50 physical devices, addressing . See GPIB addressing.

physical specifications, GPIB, B-13 to B-14 piaccr (Page-In Accessory Register) command, 4-27 pibcr (Page-In Bus Register) command, 4-26 pieosr (Page-In End-of-String Registers) command, 4-26 piimr2 (Page-In Interrupt Mask

Register 2) command, 4-25 pin descriptions

CPU register control pins, 7-3

CPU data bus, 7-3

CS* and CPU address bus, 7-3

RD*/WR*, 7-3

DMA pins

DACK*, 7-4

DRQ, 7-3 to 7-4

GPIB data bus pins, 7-3

GPIB signal pins, 7-2

GPIB transceiver controls

CIC internal signal, 7-1 to 7-2

EOIOE internal signal, 7-2

PE internal signal, 7-2

T/R1, 7-1

T/R2 and T/R3, 7-1 to 7-2

TRIG internal signal, 7-2 other pins

CLK, 7-5

INT, 7-4

RESET*, 7-4 polling . See parallel polling; serial polling.

pon (Immediate Execute Power-On) command, 3-18 pon message asserting, 5-1 clearing, 5-3

PP1 bit

Accessory Register I (ACCRI), 4-10 enabling automatic configuration, 5-17

PP2 bit

Auxiliary Register I (AUXRI), 3-35 disabling response to parallel polling, 5-18 remote or local configuration, 5-17

PP8-PP1 bits, Parallel Poll Register

(PPR), 4-48

PPC command, 6-6

PPD command, 6-6

PPE message determining, B-27 sending, 6-6

PPR (Parallel Poll Register)

7210 mode, 3-58 to 3-59

9914 mode, 4-48

PPR message determining, B-26 physical representation, B-27 primary address, GPIB, 5-3, B-17.

See also GPIB addressing.

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National Instruments Corp.

I-21 NAT7210 Reference Manual

Index programming considerations. See software considerations.

pts (Pass Through Next Secondary) command, 4-23

R

RD* pin, 5-12

RD*/WR* pins, 7-3 rdy message, generating. See GPIB rdy message and RFD holdoffs.

receiving GPIB data messages basic flow, 5-11 performing RFD holdoff on last data byte, 5-12 receiving END or EOS, 5-11 using DMA, 5-12 register bit descriptions. See bits.

registers. See 7210-mode interface registers; 9914-mode interface registers.

Release Control Command (rlc)

Auxiliary Command Register

(AUXCR), 4-22

Auxiliary Mode Register

(AUXMR), 3-20

Release DAC Holdoff (nonvalid) command, 4-18

Release DAC Holdoff (valid) command, 4-18

Release RFD Holdoff (rhdf) command,

4-18, 5-11

REM bit

Address Status Register

(ADSR), 4-12

Interrupt Status Register 2

(ISR2), 3-56 remote/local state considerations, 5-18

REMC bit, Interrupt Status Register 2

(ISR2), 3-57, 5-18

REMC IE bit, Interrupt Mask Register 2

(IMR2), 3-57 remote configuration, enabling, 5-17

Remote Enable (REN) line, GPIB, B-10 remote/local state considerations, 5-18 remote multiline messages.

See multiline messages.

REN bit, Bus Control Register (BCR)/

Bus Status Register (BSR), 3-37, 4-28

REN (Remote Enable) line, GPIB, B-10

REN signal, setting and clearing, 6-2

REOS bit

Accessory Register A (ACCRA), 4-5

Auxiliary Register A

(AUXRA), 3-27 reqf (Request rsv False) command

Auxiliary Command Register

(AUXCR), 4-24

Auxiliary Mode Register

(AUXMR), 3-23 reqt (Request rsv True) command

Auxiliary Command Register

(AUXCR), 4-24

Auxiliary Mode Register

(AUXMR), 3-23 requesting polling service, 5-16

Request Control Command (rqc)

Auxiliary Command Register

(AUXCR), 4-22

Auxiliary Mode Register

(AUXMR), 3-20

Request rsv False (reqf) command

Auxiliary Command Register

(AUXCR), 4-24

Auxiliary Mode Register

(AUXMR), 3-23

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National Instruments Corp.

Index

Request rsv True (reqt) command

Auxiliary Command Register

(AUXCR), 4-24

Auxiliary Mode Register

(AUXMR), 3-23 requesting polling service, 5-16

RESET* signal, 7-4

RFD holdoff

GPIB rdy message and RFD holdoffs, 5-12 to 5-14 choosing data-receiving mode, 5-14 data-receiving modes, 5-13 to 5-14 generating rdy message, 5-13

RFD Holdoff On All Data

(hlda), 5-13

RFD Holdoff on END

(hlde), 5-14 performing on last data byte, 5-12 rhdf (Finish Handshake) command, 3-19 rhdf (Release RFD Holdoff) command,

4-18, 5-11 rlc (Release Control Command), 3-20

RLC bit, Interrupt Status Register 0

(ISR0), 4-37 to 4-38 rlc (Release Control) command, 4-22

RLC IE bit, Interrupt Mask Register 0

(IMR0), 4-37 to 4-38

~rpp (Clear Request Parallel Poll) command, 4-21 rpp (Set Request Parallel Poll) command,

4-21, 6-7 rpp1 (Execute Parallel Poll) command, 3-24

RPP2 bit, Auxiliary Register G

(AUXRG), 3-34, 6-7 rqc (Request Control Command)

Auxiliary Command Register

(AUXCR), 4-22

Auxiliary Mode Register

(AUXMR), 3-20

RQS bit, B-23

~rsc (Disable System Control) command,

3-22, 6-2 rsv/RQS bit, Serial Poll Mode Register

(SPMR), 3-63, 4-50

~rsv2 (Clear Request Service bit 2) command, 4-24 rsv2 (Set Request Service bit 2) command, 4-24 rtl (Clear Or Pulse Return To Local) command, 3-20

~rtl (Clear Return to Local) command, 4-20 rtl (Set Return To Local) command

Auxiliary Command Register

(AUXCR), 4-20

Auxiliary Mode Register

(AUXMR), 3-20

S

S bit, Parallel Poll Register (PPR), 3-59

S[6-1] bits, Serial Poll Mode Register

(SPMR)/Serial Poll Status Register

(SPSR), 3-62, 4-49

S8 bit, Serial Poll Mode Register

(SPMR)/Serial Poll Status Register

(SPSR), 3-62, 4-49

SASR (Source/Acceptor Status Register),

3-60 to 3-61

SC pin, 6-1, 6-2

SCPI. See Standard Commands for

Programmable Instrumentation (SCPI).

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National Instruments Corp.

I-23 NAT7210 Reference Manual

Index

SDC (Selected Device Clear) command, 5-19

SDHS signal, 5-15 secondary address, GPIB, 5-3, B-19. See

also GPIB addressing.

Selected Device Clear (SDC) command, 5-19

Send EOI (seoi) command, 3-20

Send EOI With The Next Byte (feoi) command, AUXCR, 4-20 sending GPIB data messages basic flow, 5-7 to 5-8 sending EOI or EOS, 5-8

T1 delay generation

7210 mode, 5-10

9114 mode, 5-10

HSTS definition, 5-9

IEEE 488.1 standard requirements, 5-9 using DMA, 5-8

Serial Poll Mode Register (SPMR)

7210 mode, 3-62 to 3-63

9914 mode, 4-49 to 4-50 serial polling conducting for Controller in

Charge, 6-6 events during serial poll

(illustration), B-22

GPIB controller, 6-6 configuring devices for parallel polls, 6-6 serial polls, 6-6 requesting service asserting SRQ signal, 5-15

IEEE 488.2 service requesting, 5-16

7210-style service requesting, 5-16 responding to serial polls, 5-16 to 5-17 serial polling devices, B-21 to B-22 servicing SRQs, B-21 status byte model

IEEE 488.1, B-23

IEEE 488.2, B-23 to B-24 writing initial serial poll response, 5-2

Service Request Enable Register (SRE),

B-23, B-24

Service Request (SRQ) line, GPIB, B-11

Set Disable IMR2, IMR1, and IMR0

Interrupts (dai) command, 4-22

Set Force Group Execute Trigger (fget) command, 4-19

Set Holdoff On All Data (hdfa) command, 4-18

Set Holdoff On END Only (hdfe) command, 4-19

Set IFC (sic & rsc) command, 3-24

Set Listen Only (lon) command, 4-20

Set Parallel Poll Flag (ist) command

Auxiliary Command Register

(AUXCR), 4-25

Auxiliary Mode Register

(AUXMR), 3-18

Set REN (sre & rsc) command, 3-25

Set Request Parallel Poll (rpp) command conducting parallel polls, 6-7 description, 4-21

Set Request Service bit 2 (rsv2) command, 4-24

Set Return To Local (rtl) command

Auxiliary Command Register

(AUXCR), 4-20

Auxiliary Mode Register

(AUXMR), 3-20

NAT7210 Reference Manual I-24

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National Instruments Corp.

Set Send Interface Clear (sic) command,

4-21, 6-1

Set Send Remote Enable (sre) command,

4-22, 6-2

Set Shadow Handshaking (shdw) command, 4-23

Set Short T1 Delay (stdl) command, 4-23

Set Software Reset (swrst) command, 4-18

Set SYNC command, Auxiliary Mode

Register (AUXMR), 3-26

Set Talk Only (ton) command, 4-20

Set Very Short T1 Delay (vstdl) command, 4-23

SH1A, SH1B bits, Source/Acceptor

Status Register (SASR), 3-61

~shdw (Clear Shadow Handshaking) command, 4-23 shdw (Set Shadow Handshaking) command, 4-23

~sic & rsc (Clear IFC) command, 3-22 sic & rsc (Set IFC) command, 3-24

~sic (Clear Send Interface Clear) command, 4-21, 6-1 sic (Set Send Interface Clear) command,

4-21, 6-1 signal pins, GPIB, 7-2 signals and lines, GPIB, B-7

SISB bit, Auxiliary Register I (AUXRI) clear conditions (table), 3-36 description, 3-35 to 3-36

SLOW bit, Internal Count Register 2

(ICR2), 3-44 software considerations. See also GPIB

Controller; System Controller.

acceptor handshake holdoffs

DAC holdoffs, 5-14 to 5-15

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National Instruments Corp.

I-25

Index

GPIB rdy message and RFD holdoffs, 5-12 to 5-13 choosing data-receiving mode, 5-14 data-receiving modes, 5-13 to 5-14 generating rdy message, 5-13 immediate RFD holdoff, 5-13 chip initialization sequence asserting local pon message, 5-1 clearing local pon message, 5-3 configuring chip for GPIB operation, 5-2 enabling interrupts, 5-2 placing NAT7210 in 7210 mode, 5-1 setting clock frequency, 5-1 device clearing, 5-19 device status reporting (polling) requesting service, 5-15 to 5-16 responding to parallel polls, 5-17 to 5-18 responding to serial polls, 5-16 to 5-17 device triggering, 5-18 generating hardware interrupts, 5-18

GPIB addressing implementing one logical device extended addressing, 5-4 normal addressing, 5-4 implementing three or more logical devices extended addressing, 5-6 to 5-7 normal addressing, 5-5 to 5-6

NAT7210 Reference Manual

Index implementing two logical devices extended addressing, 5-5 normal addressing, 5-4 logical and physical devices, 5-3 normal and extended addressing, 5-3 programmed implementation of

Talker and Listener, 5-7 receiving GPIB data messages basic flow, 5-11 performing RFD holdoff on last data byte, 5-12 receiving END or EOS, 5-11 using DMA, 5-12 remote/local state considerations, 5-18 sending GPIB data messages basic flow, 5-7 to 5-8 sending EOI or EOS, 5-8

T1 delay generation

7210 mode, 5-10

9114 mode, 5-10

HSTS definition, 5-9

IEEE 488.1 standard requirements, 5-9

T1 delay, 5-8 using DMA, 5-8

Source/Acceptor Status Register (SASR),

3-60 to 3-61

Source Handshake T1 delay.

See T1 delay generation.

SPAS bit, Interrupt Status Register 0

(ISR0), 4-37

SPAS IE bit, Interrupt Mask Register 0

(IMR0), 4-37

SPD command, 6-6

SPE command, 6-6

SPEOI bit

Accessory Register B (ACCRB), 4-7

Auxiliary Register B

(AUXRB), 3-30

SPMR (Serial Poll Mode Register)

7210 mode, 3-62 to 3-63

9914 mode, 4-49 to 4-50

SPMS bit, Address Status Register

(ADSR), 3-11

SPSR (Serial Poll Status Register), 4-49 to 4-50

SRE (Service Request Enable Register),

B-23, B-24

~sre & rsc (Clear REN) command, 3-23 sre & rsc (Set REN) command, 3-25

~sre (Clear Send Remote Enable) command, 4-22, 6-2 sre (Set Send Remote Enable) command,

4-22, 6-2

SRQ bit

Bus Control Register (BCR)/Bus

Status Register (BSR), 3-37, 4-28

Interrupt Status Register 1

(ISR1), 4-43

SRQ IE bit, Interrupt Mask Register 1

(IMR1), 4-43

SRQ (Service Request) line asserting, 5-15 purpose and use, B-11

SRQI bit, Interrupt Status Register 2

(ISR2), 3-55

SRQI IE bit, Interrupt Mask Register 2

(IMR2), 3-55

Standard Commands for Programmable

Instrumentation (SCPI) history, B-1, C-1

IEEE 488.2 command commands required by SCPI, C-2

NAT7210 Reference Manual I-26

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National Instruments Corp.

Index optional commands, C-4 programming with SCPI, C-4 to C-7 constructing commands using hierarchical command structure, C-5 to C-6 parsing commands, C-7 partial command categories

(illustration), C-4 partial command tree

SENSe command subsystem

(illustration), C-5

SOURce command subsystem

(illustration), C-6

TRIGger command subsystem

(illustration), C-6 simple command tree for SENSe command subsystem

(illustration), C-4 required commands, C-3 specification, B-3 to B-4 standards. See IEEE 488.1 standard;

IEEE 488.2 standard.

Standby Controller State changing states, 6-4 definition, 6-3

STBO bit

Interrupt Status Register 0

(ISR0), 3-46

Interrupt Status Register 2

(ISR2), 4-45

STBO IE bit

Interrupt Mask Register 0

(IMR0), 3-46

Interrupt Mask Register 2

(IMR2), 4-45 responding to serial polls, 5-16

~stdl (Clear Short T1 Delay) command, 4-23 stdl (Set Short T1 Delay) command,

4-23, 5-10 sw7210 (Switch To 7210 Mode) command definition, 4-24 placing NAT7210 in 7210 mode, 5-1 sw9914 (Switch To 9914A Mode) command, 3-22

~swrst (Clear Software Reset) command, 4-18 swrst (Set Software Reset) command, 4-18

SYNC bit, Interrupt Status Register 0

(ISR0), 3-48, 6-4

SYNC IE bit, Interrupt Mask Register 0

(IMR0), 3-48

System Controller.

See also GPIB Controller.

becoming System Controller, 6-1 defining, B-14 disabling, 6-2 setting and clearing REN, 6-2

T

T/R1 signal, 7-1

T/R2 and T/R3 signals, 7-1 to 7-2

CIC internal signal, 7-1 to 7-2

EOIOE internal signal, 7-2

PE internal signal, 7-2

TRIG internal signal, 7-2

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National Instruments Corp.

I-27 NAT7210 Reference Manual

Index

T1 delay generation, 5-8 to 5-10

7210 mode, 5-10

9114 mode, 5-10 effect on transfer rate, A-1

HSTS definition, 5-9

IEEE 488.1 standard requirements, 5-9 setting GPIB handshake parameters, 5-2

T1 delay, 5-8

TA bit

Address Status Register (ADSR),

3-12 to 3-13, 4-13 implementing logical devices, 5-4

Take Control Asynchronously

(tca) command

Auxiliary Command Register

(AUXCR), 4-21

Auxiliary Mode Register

(AUXMR), 3-21 changing controller states, 6-4

Take Control Synchronously

(tcs) command

Auxiliary Command Register

(AUXCR), 4-21

Auxiliary Mode Register

(AUXMR), 3-22

Take Control Synchronously On END

(tcse) command, 3-23

Talkers. See also GPIB addressing; GPIB

Controller; Listeners.

activating, 5-7 programmed implementation, 5-7 properties, B-15 system setup example

(illustration), B-16 tca (Take Control

Asynchronously) command

Auxiliary Command Register

(AUXCR), 4-21

Auxiliary Mode Register

(AUXMR), 3-21 changing controller states, 6-4 tcs (Take Control

Synchronously) command

Auxiliary Command Register

(AUXCR), 4-21

Auxiliary Mode Register

(AUXMR), 3-22 tcse (Take Control Synchronously on

END) command, 3-23

TCT command, 6-4 technical support, F-1 termination methods, GPIB, B-19 to B-21 combination of methods, B-21 count method, B-20 to B-21

EOI method, B-20

EOS method, B-20 three-wire handshake process description, B-13 illustration, B-12

~ton (Clear Talk Only) command, 4-20 ton (Set Talk Only) command, 4-20

TPAS bit

Address Status Register (ADSR),

3-12, 4-13 implementing logical devices, 5-4 transceivers. See GPIB transceiver controls.

TRI bit, Auxiliary Register B

(AUXRB), 3-29

TRIG internal signal, 7-2

Trigger (trig) command, 3-20

NAT7210 Reference Manual I-28

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National Instruments Corp.

Index triggering devices, 5-19, B-28

TRM[1-0] bits, Address Mode Register

(ADMR), 7210 mode, 3-7

U

U bit, Parallel Poll Register (PPR),

3-58, 5-18 ulpa bit, Address Status Register

(ADSR), 4-14

UNC bit, Interrupt Status Register 1

(ISR1), 4-39 to 4-41

UNC IE bit, Interrupt Mask Register 1

(IMR1), 4-39 to 4-41

UNL command, 6-6

Unlisten (lul) command, 3-21

UNT command, 6-6

Untalk (lut) command, 3-21

USTD bit

Accessory Register I (ACCRI), 4-10

Auxiliary Register I (AUXRI), 3-35 determining T1 delay, 5-10 setting Source Handshake T1 delay, 5-2

V

V[3-0] bits, Version Status Register

(VSR), 3-64

Valid Secondary Command Or Address

(valid) command, 3-21

Version Status Register (VSR), 3-64

~vstdl (Clear Very Short T1 Delay) command, 4-23 vstdl (Set Very Short T1 Delay) command, 4-23, 5-10

W

WR* signal, 5-8, 7-3

X

X bit, Address Register 0 (ADR0), 3-9

XEOS bit

Accessory Register A (ACCRA), 4-5

Auxiliary Register A

(AUXRA), 3-27 sending GPIB data messages, 5-8

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National Instruments Corp.

I-29 NAT7210 Reference Manual