Freescale Semiconductor
User’s Manual Addendum
MCF5272UMAD
Rev. 6, 02/2006
MCF5272 Integrated
Microprocessor User’s Manual
Errata
by: Microcontroller Division
This errata document describes corrections to the
MCF5272 ColdFire Integrated Microprocessor User’s
Manual, order number MCF5272UM. For convenience, the addenda items are grouped by revision. Please check our website at http://www.freescale.com/coldfire for the latest updates.
The current version available of the MCF5272 User’s
Manual is Revision 2.1.
Table of Contents
1 Errata for Revision 2 & 2.1 .................................. 2
2 Revision History .................................................. 5
© Freescale Semiconductor, Inc., 2006. All rights reserved.
Errata for Revision 2 & 2.1
1 Errata for Revision 2 & 2.1
Table 1. MCF5272UM Rev 2 & 2.1 Errata
Location
Table 9-3/Page 9-4
Description
Change “Total page size” row as shown below:
Table 9-3. Configurations for 16-Bit Data Bus
8-Bit 16-Bit
Parameter
Number of devices
Total size
Total page size
Number of banks
Refresh count in 64 mS
16 Mbits 64 Mbits 16 Mbits 64 Mbits 128 Mbits 256 Mbits
2 1
4 Mbytes 16 Mbytes 2 Mbytes 8 Mbytes 16 Mbytes 32 Mbytes
2 Kbytes
2
4K
4 Kbytes
4
4K
2 Kbytes
2
4K
4 Kbytes
4
4K
4 Kbytes
4
4K
8 Kbytes
4
8K
Table 9-4/Page 9-4
Table 11-9/11-14
Table 13-17/13-33
14.4.3/14-8
Change “Total page size” row as shown below:
Table 9-4. Configurations for 32-Bit Data Bus
8-Bit 16-Bit 32-Bit
Parameter
16
Mbits
64
Mbits
16
Mbits
64
Mbits
128
Mbits
256
Mbits
64
Mbits
128
Mbits
Number of devices
Total size
Total page size
Number of banks
Refresh count in 64 mS
4
8
Mbytes
32
Mbytes
2
Kbytes
2
4K
4
Kbytes
4
4K
4
Mbytes
16
Mbytes
2
32
Mbytes
64
Mbytes
1
8
Mbytes
16
Mbytes
2
Kbytes
2
4K
4
Kbytes
4
4K
4
Kbytes
4
4K
8
Kbytes
4
8K
2
Kbytes
4
4K
4
Kbytes
4
8K
Change encodings for bits 31–9 to:
0 The corresponding interrupt source is masked.
1 The corresponding interrupt source is not masked.
The description of CMULT reads “100 x 32” instead of “100 x 23” as printed in the user’s manual.
Replaced “Adequate delay between transfers must be specified for long data streams because the
QSPI module requires time to load a transmit RAM entry for transfer. Receiving devices need at least the standard delay between successive transfers.” with “Receiving devices need at least the standard delay (DT=0) between successive transfers for long data streams because the
QSPI module requires time to load a transmit RAM entry for transfer.”
2
MCF5272 Integrated Microprocessor User’s Manual Errata, Rev. 6
Freescale Semiconductor
Location
14.5.1/14-11
Table 1. MCF5272UM Rev 2 & 2.1 Errata (continued)
Description
Added Figure 14-5 “SPI Modes Timing” shown below.
Errata for Revision 2 & 2.1
SCK
(CPOL = 0, CPHA = 0)
14.5.6/14-14
Table 14-7/14-15
14.5.8/14-16
15.2/15-3
Figure 15-4/15-5
Figure 16-24/16-23
Table 17-5/17-6
20.12/20-23
20.12.1/20-24
SCK
(CPOL = 0, CPHA = 1)
SCK
(CPOL = 1, CPHA = 0)
SCK
(CPOL = 1, CPHA = 1)
Added this text: “A read or a write to QDR causes the value in QAR to increment.”
In this table, the CONT bit description has been reworded to read: “Chip selects remain asserted between transfers for a transfer of up to 16 words of data.”
In example 4, replaced “0x D00F” with “0x D00D.”
Changed “Timers 0 and 2” to “Timers 0 and 1” because these drive TOUT0 and TOUT1.
Corrected address field to read “MBAR + 0x208 (TCAP0); 0x228 (TCAP1); 0x248 (TCAP2); 0x268
(TCAP3).”
Changed upper “UART Transmit FIFO (URB) (24 Bytes)” to “UART Transmit FIFO (UTB) (24
Bytes)” and lower “UART Transmit FIFO (URB) (24 Bytes)” to “UART Receive FIFO (URB) (24
Bytes).”
The description of PBCNT11 reads “10 Reserved” instead of “10 QSPI_CS” as printed in the user’s manual.
Add to note. “SDCLK can be affected if master reset is not used for power-on.”
Changed RSTI to RSTO in “The levels of the mode select inputs, QSPI_Dout/WSEL,
QSPI_CLK/BUSW1, and QSPI_CS0/BUSW0, are sampled when RSTO negates and they select the port size of CS0 and the physical data bus width after a master reset occurs.”
Freescale Semiconductor
MCF5272 Integrated Microprocessor User’s Manual Errata, Rev. 6
3
Errata for Revision 2 & 2.1
Location
Figure 20-5/20-10
Table 1. MCF5272UM Rev 2 & 2.1 Errata (continued)
Description
Replaced Figure 20-5 with the figure below. This figure differs from the user’s manual in that it reflects the assertion of OE, BS[3:0] one clock earlier.
SDCLK
A[22:0]
D[31:0]
C1 C2 C3
OE, BS[3:0]
R/W (H)
CSn
TA (H)
Figure 20-5. Longword Read with Address Setup; EBI = 00; 32-Bit Port; Internal
Termination
4
MCF5272 Integrated Microprocessor User’s Manual Errata, Rev. 6
Freescale Semiconductor
Location
Figure 20-6/20-11
Revision History
Table 1. MCF5272UM Rev 2 & 2.1 Errata (continued)
Description
Replaced Figure 20-6 with the figure below. This figure differs from the user’s manual in that it reflects the assertion of R/W, BS[3:0] one clock earlier.
SDCLK C1 C2 C3
A[22:0]
D[31:0]
OE (H)
R/W
CSn
BS[3:0]
TA (H)
Figure 20-6. Longword Write with Address Setup; EBI = 00; 32-Bit Port; Internal
Termination
Input high voltage (VIH) maximum entry should be 5.5V instead of 5.0V.
Table 23-4/23-3
2 Revision History
Table 2 provides a revision history for this document.
Table 2. Revision History Table
Rev. Number
5
6
Substantive Changes
• Added Table 11-9 errata.
• Added Figure 16-24 errata.
• Added SDCLK errata for Section 20.12.
• Added VIH max errata.
• Added SDRAM configuration tables errata.
Date of Release
07/2005
02/2006
Freescale Semiconductor
MCF5272 Integrated Microprocessor User’s Manual Errata, Rev. 6
5
How to Reach Us:
Home Page: www.freescale.com
E-mail: [email protected]
USA/Europe or Locations Not Listed:
Freescale Semiconductor
Technical Information Center, CH370
1300 N. Alma School Road
Chandler, Arizona 85224
+1-800-521-6274 or +1-480-768-2130 [email protected]
Europe, Middle East, and Africa:
Freescale Halbleiter Deutschland GmbH
Technical Information Center
Schatzbogen 7
81829 Muenchen, Germany
+44 1296 380 456 (English)
+46 8 52200080 (English)
+49 89 92103 559 (German)
+33 1 69 35 48 48 (French) [email protected]
Japan:
Freescale Semiconductor Japan Ltd.
Headquarters
ARCO Tower 15F
1-8-1, Shimo-Meguro, Meguro-ku,
Tokyo 153-0064, Japan
0120 191014 or +81 3 5437 9125 [email protected]
Asia/Pacific:
Freescale Semiconductor Hong Kong Ltd.
Technical Information Center
2 Dai King Street
Tai Po Industrial Estate
Tai Po, N.T., Hong Kong
+800 2666 8080 [email protected]
For Literature Requests Only:
Freescale Semiconductor Literature Distribution Center
P.O. Box 5405
Denver, Colorado 80217
1-800-441-2447 or 303-675-2140
Fax: 303-675-2150
[email protected]
Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document.
Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale
Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”, must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others.
Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale
Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part.
Freescale™ and the Freescale logo are trademarks of Freescale
Semiconductor, Inc. All other product or service names are the property of their respective owners.© Freescale Semiconductor, Inc. 2006. All rights reserved.
MCF5272UMAD
Rev. 6
02/2006
