NXP MCX N Series High Performance Microcontrollers User Guide
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UG10111 MCX Nx4x TSI User Guide Rev. 1 — 7 May 2024 User guide Document information Information Content Keywords MCX, MCX Nx4x, TSI, touch. Abstract The Touch Sensing Interface (TSI) of the MCX Nx4x series is the upgraded IP with new features to implement the baseline/threshold autotuning. UG10111 NXP Semiconductors MCX Nx4x TSI User Guide 1 Introduction The MCX N series of the Industrial and IoT (IIoT) MCU feature dual Arm Cortex-M33 cores operates up to 150 MHz. The MCX N series are high-performance, low-power microcontrollers with intelligent peripherals and accelerators providing multitasking capabilities and performance efficiency. The Touch Sensing Interface (TSI) of the MCX Nx4x series is the upgraded IP with new features to implement the baseline/threshold autotuning. 2 MCX Nx4x TSI overview TSI provides touch-sensing detection on capacitive touch sensors. The external capacitive touch sensor is typically formed on PCB and the sensor electrodes are connected to the TSI input channels through the I/O pins in the device. 2.1 MCX Nx4x TSI block diagram MCX Nx4x has one TSI module and supports 2 kinds of touch sensing methods, the self-capacitance (also called self-cap) mode and the mutual-capacitance (also called mutual-cap) mode. The block diagram of MCX Nx4x TSI I shown in Figure 1: Enable TSI Read TSI result TSI_GENCS[TSIIEN] MUX TSI channel [0] Tx channel TSI channel [...] TSI channel [7] TSI_GENCS[ESOR] Analog front end mutual-cap sensing Rx channel TSI_GENCS[OUTRG_EN] Transmitter Receiver TSI_GENCS[DMAEN_OUTRG] TSI_GENCS[DMAEN_EOS] Analog front end self-cap sensing TSI channel [8] Self-cap channel TSI channel [...] TSI channel [24] Charge transfer circuit TSI_DATA[TSICH] TSI end-of-scan interrupt TSI out-of-range interrupt NVIC 117 TSI end-of-scan 118 TSI out-of-range TSI end-of-scan DMA DMA TSI out-of-range DMA Scanning clock generation TSI clock generation SSC FRO_12M [OSC_CLK_SEL] SINC filter TSICNT Auto trigger TSI clock generation 32 K TSI IP MCX N MCU aaa-055213 Figure 1. MCX Nx4x TSI block diagram The TSI module of MCX Nx4x has 25 touch channels. 4 of these channels can be used as shield channels to enhance the drive strength of touch channels. The 4 shield channels are used to enhance the liquid tolerance and improve the driving ability. The enhanced driving ability also enables users to design a larger touchpad on the hardware board. The TSI module of MCX Nx4x has up to 25 touch channels for self-cap mode and up to 8 x 17 touch channels for mutual-cap mode. Both mentioned methods can be combined on a single PCB, but the TSI channel is more flexible for Mutual-cap mode. The TSI[0:7] are TSI Tx pins and TSI[8:25] are TSI Rx pins in Mutual-cap mode. In self-capacitive mode, developers can use 25 self-cap channels to design 25 touch electrodes. UG10111 User guide All information provided in this document is subject to legal disclaimers. Rev. 1 — 7 May 2024 © 2024 NXP B.V. All rights reserved. 2 / 20 UG10111 NXP Semiconductors MCX Nx4x TSI User Guide In mutual-capacitive mode, design options expand to up to 136 (8 x 17) touch electrodes. Several use cases such as a multiburner induction cooker with touch controls, touch keyboards, touchscreen, require a lot of touch key design. The MCX Nx4x TSI can support up to 136 touch electrodes when mutual-cap channels are used. The MCX Nx4x TSI can expand more touch electrodes to meet the requirements of multiple touch electrodes. Some new features have been added to make the IP easier to be used in low-power mode. TSI has advanced EMC robustness, which makes it suitable for use in industrial, home appliance, and consumer electronics applications. 2.2 MCX Nx4x parts supported TSI Table 1 shows the number of TSI channels corresponding to different parts of the MCX Nx4x series. All these parts support one TSI module that has 25 channels. Table 1. MCX Nx4x parts supporting TSI module Parts Frequency [Max] (MHz) Flash (MB) SRAM (kB) TSI [Number, channels] GPIOs Package type MCXN546VDFT 150 1 352 1 x 25 124 VFBGA184 MCXN546VNLT 150 1 352 1 x 25 74 HLQFP100 MCXN547VDFT 150 2 512 1 x 25 124 VFBGA184 MCXN547VNLT 150 2 512 1 x 25 74 HLQFP100 MCXN946VDFT 150 1 352 1 x 25 124 VFBGA184 MCXN946VNLT 150 1 352 1 x 25 78 HLQFP100 MCXN947VDFT 150 2 512 1 x 25 124 VFBGA184 MCXN947VNLT 150 2 512 1 x 25 78 HLQFP100 2.3 MCX Nx4x TSI channel assignment on different packages Table 2. TSI channel assignment for MCX Nx4x VFBGA and LQFP packages 184BGA ALL 184BGA ALL 100HLQFP pin name N94X 100HLQFP N94X pin name 100HLQFP N54X 100HLQFP N54X pin name TSI channel A1 P1_8 1 P1_8 1 P1_8 TSI0_CH17/ADC1_A8 B1 P1_9 2 P1_9 2 P1_9 TSI0_CH18/ADC1_A9 C3 P1_10 3 P1_10 3 P1_10 TSI0_CH19/ADC1_A10 D3 P1_11 4 P1_11 4 P1_11 TSI0_CH20/ADC1_A11 D2 P1_12 5 P1_12 5 P1_12 TSI0_CH21/ADC1_A12 D1 P1_13 6 P1_13 6 P1_13 TSI0_CH22/ADC1_A13 D4 P1_14 7 P1_14 7 P1_14 TSI0_CH23/ADC1_A14 E4 P1_15 8 P1_15 8 P1_15 TSI0_CH24/ADC1_A15 B14 P0_4 80 P0_4 80 P0_4 TSI0_CH8 A14 P0_5 81 P0_5 81 P0_5 TSI0_CH9 C14 P0_6 82 P0_6 82 P0_6 TSI0_CH10 B10 P0_16 84 P0_16 84 P0_16 TSI0_CH11/ADC0_A8 UG10111 User guide All information provided in this document is subject to legal disclaimers. Rev. 1 — 7 May 2024 © 2024 NXP B.V. All rights reserved. 3 / 20 UG10111 NXP Semiconductors MCX Nx4x TSI User Guide Table 2. TSI channel assignment for MCX Nx4x VFBGA and LQFP packages...continued 184BGA ALL 184BGA ALL 100HLQFP pin name N94X 100HLQFP N94X pin name 100HLQFP N54X 100HLQFP N54X pin name TSI channel A10 P0_17 85 P0_17 85 P0_17 TSI0_CH12/ADC0_A9 C10 P0_18 86 P0_18 86 P0_18 TSI0_CH13/ADC0_A10 C9 P0_19 87 P0_19 87 P0_19 TSI0_CH14/ADC0_A11 C8 P0_20 88 P0_20 88 P0_20 TSI0_CH15/ADC0_A12 A8 P0_21 89 P0_21 89 P0_21 TSI0_CH16/ADC0_A13 C6 P1_0 92 P1_0 92 P1_0 TSI0_CH0/ADC0_A16/CMP0_IN0 C5 P1_1 93 P1_1 93 P1_1 TSI0_CH1/ADC0_A17/CMP1_IN0 C4 P1_2 94 P1_2 94 P1_2 TSI0_CH2/ADC0_A18/CMP2_IN0 B4 P1_3 95 P1_3 95 P1_3 TSI0_CH3/ADC0_A19/CMP0_IN1 A4 P1_4 97 P1_4 97 P1_4 TSI0_CH4/ADC0_A20/CMP0_IN2 B3 P1_5 98 P1_5 98 P1_5 TSI0_CH5/ADC0_A21/CMP0_IN3 B2 P1_6 99 P1_6 99 P1_6 TSI0_CH6/ADC0_A22 A2 P1_7 100 P1_7 100 P1_7 TSI0_CH7/ADC0_A23 TSI0_CH17 PIO0_0/TMS/... PIO0_1/TCLK/... PIO0_2/TDO/... PIO0_3/TDI/... TSI0_CH8 TSI0_CH9 TSI0_CH10 VSS83 TSI0_CH11 TSI0_CH12 TSI0_CH13 TSI0_CH14 TSI0_CH15 TSI0_CH16 PIO0_22/... PIO0_23/... TSI0_CH0 TSI0_CH1 TSI0_CH2 TSI0_CH3 VDD96 TSI0_CH4 TSI0_CH5 TSI0_CH6 TSI0_CH7 Figure 2 and Figure 3 show the assignment of dual TSI channels on the two packages of MCX Nx4x. In the two packages, the pins marked in green are the location of the TSI channel distribution. To make reasonable pin assignment for hardware touch board design, refer to pin location. PIO3_0/... ADC0 ADC1 CAN0 CAN1 CMP0 CMP1 CMP2 CTIMER0 CTIMER1 CTIMER2 CTIMER3 CTIMER4 DAC0 DAC1 DAC2 EMVSIM0 TSI0_CH22 EMVSIM1 ENC0 ENC1 ENET0 PIO3_8/... TSI0_CH23 EVTG0 EWM0 FLEXIO0 FLEXSPI0 PIO3_9/FC6_P5/... FREQME0 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 I3C0 I3C1 INPUTMUX0 JTAG LPTMR0 LPTMR1 LP_FLEXCOM LP_FLEXCOM LP_FLEXCOM PIO3_13/...... LP_FLEXCOM LP_FLEXCOM LP_FLEXCOM LP_FLEXCOM PIO3_14/...... LP_FLEXCOM LP_FLEXCOM LP_FLEXCOM OPAMP0 OPAMP1 OPAMP2 PDM PINT0 PLU0 PMW0 PWM1 RTC0 PIO2_4/... SAI0 SAI1 SCG0 SCT0 VDD_CORE PIO2_5/... SINC0 SMARTDMA0 SPC0 SUPPLY PIO3_20/... SWD SYSCON0 TDET0 TPIU PIO3_21/... TSI0 USBDCD0 USBFS0 USBPHY USDHC0 UTICK0 VBAT0 WUU0 TSI0_CH18 TSI0_CH19 TSI0_CH20 TSI0_CH21 TSI0_CH24 RESET_B PIO1_30/... PIO1_31/... VDD_CORE/... VDD13 PIO2_0/... PIO2_1/... PIO2_2/... PIO3_1/... VDD_P373 PIO3_6/... PIO3_7/FC6_P6/... PIO3_10/... PIO3_11/... VDD_P366 PIO3_12/...... PIO3_15/...... PIO3_16/...... PIO3_17/...... PIO2_3/FC9_P1... PIO2_6/... PIO2_7/... VDD_P359... VDD_SYS PIO4_0/... VDD_DCDC PIO4_1/... DCDC_LX PIO4_2/... VSS_DCDC PIO4_3/... PIO5_3/... PIO5_2/ PIO5_1/ PIO5_0/ VDD_BAT USB0_DP/... USB0_DM/... VDD_USB PIO4_21/... PIO4_23/... PIO4_20/... PIO4_19/... PIO4_17/... PIO4_16/... PIO4_15/... PIO4_13/... PIO4_12/... VDD_P434 VSS_P433 VREFL VREFH VDD_ANA PIO4_7/... PIO4_6/... PIO4_5/... PIO4_4/... MCXN947VNL - HLQFP 100 package aaa-055214 Figure 2. TSI channel assignment of MCX Nx4x 100LQFP and 164VFBGA UG10111 User guide All information provided in this document is subject to legal disclaimers. Rev. 1 — 7 May 2024 © 2024 NXP B.V. All rights reserved. 4 / 20 UG10111 NXP Semiconductors MCX Nx4x TSI User Guide 17 A B C D E F G H J K L M N P R T U 16 15 A17 A16 14 13 A14 12 11 A12 B17 B16 B15 B14 G16 B12 B11 B10 B8 C10 C9 D12 D11 F8 H10 H9 H8 J10 J8 G11 L16 K13 K12 L14 L13 M17 M16 M15 M14 P17 P16 P15 P14 K9 M8 N11 N10 N8 P12 P11 R15 R14 R13 R12 P9 R10 R9 T12 T11 T10 T8 U17 U16 U12 U8 17 16 U14 15 14 13 U10 1 A2 A1 B2 B1 B3 C4 C3 D4 D3 D2 D1 F3 F2 F1 C5 D6 E5 E4 F4 G5 H6 G4 H5 K6 K5 L5 M6 G2 H3 J4 H1 K2 K1 J3 K3 L4 M4 H2 L2 M3 M2 M1 P4 P3 P2 P1 R4 R3 T6 T4 T3 T2 T1 U6 U4 U2 U1 N7 N5 P6 R6 T7 2 B4 F6 R8 3 B6 E7 P7 T17 T16 T15 T14 4 A4 L7 M10 5 A6 C6 K8 L11 N14 N13 6 G7 K10 M12 B7 D7 F10 J15 J14 K17 K16 K15 D9 E8 H13 H12 7 C8 E11 E10 F12 G14 G13 H17 H16 H15 8 A8 E14 E13 F17 F16 F15 F14 9 A10 C15 C14 C13 C12 D17 D16 D15 D14 10 R5 12 11 10 9 8 7 6 5 MCXN947VDF - VFBGA 184 package N4 4 3 2 A B C D E F G H J K L M N P R T U 1 aaa-055215 Figure 3. TSI channel assignment of MCX Nx4x 100LQFP and 164VFBGA 3 MCX Nx4x TSI features This section gives the detals of MCX Nx4x TSI features. 3.1 TSI comparison between MCX Nx4x TSI and Kinetis TSI MCX Nx4x of TSI and TSI on the NXP Kinetis E series TSI are designed on different technology platforms. Therefore, from the basic features of TSI to the registers of TSI, there are differences between MCX Nx4x TSI and TSI of the Kinetis E series. Only the differences are listed in this document. To check the TSI registers, use the reference manual. This chapter describes the features of MCX Nx4x TSI by comparing it to the TSI of the Kinetis E series. As shown in Table 3, MCX Nx4x TSI is not affected by the VDD noise. It has more function clock choices. If the function clock is configured from the chip system clock, the TSI power consumption can be decreased. Even though the MCX Nx4x TSI has only one TSI module, it supports designing more hardware touch keys on a hardware board when using mutual-cap mode. Table 3. The difference between MCX Nx4x TSI and Kinetis E TSI (KE17Z256) MCX Nx4x series Kinetis E series Operating voltage 1.71 V – 3.6 V 2.7 V – 5.5 V VDD noise impact No Yes Function clock source • TSI IP internal generated • Chip system clock TSI IP internal generated Function clock range 30 KHz - 10 MHz 37 KHz - 10 MHz TSI channels Up to 25 channels (TSI0) Up to 50 channels (TSI0, TSI1) Shield channels 4 shield channels: CH0, CH6, CH12, CH18 3 shield channels for each TSI: CH4, CH12, CH21 Touch mode Self-cap mode: TSI[0:24] Self-cap mode: TSI[0:24] UG10111 User guide All information provided in this document is subject to legal disclaimers. Rev. 1 — 7 May 2024 © 2024 NXP B.V. All rights reserved. 5 / 20 UG10111 NXP Semiconductors MCX Nx4x TSI User Guide Table 3. The difference between MCX Nx4x TSI and Kinetis E TSI (KE17Z256)...continued MCX Nx4x series Kinetis E series Mutual-cap mode: Tx[0:7], Rx[8:24] Mutual-cap mode: Tx[0:5], Rx[6:12] Touch electrodes self-cap electrodes: up to 25 mutual-cap electrodes: up to 136 (8x17) self-cap electrodes: up to 50 (25+25) mutual-cap electrodes: up to 72 (6x6 +6x6) Products MCX N9x and MCX N5x KE17Z256 The features supported both by MCX Nx4x TSI and Kinetis TSI are shown in Table 4. Table 4. The features supported both by MCX Nx4x TSI and Kinetis TSI MCX Nx4x series Two kinds of Sensing mode Kinetis E series Self-cap mode: Basic self-cap mode Sensitivity boost mode Noise cancellation mode Mutual-cap mode: Basic mutual-cap mode Sensitivity boost enable Interrupt support End of scan interrupt Out of range interrupt Trigger source support 1. Software trigger by writing the GENCS[SWTS] bit 2. Hardware trigger through INPUTMUX 3. Automatic trigger by AUTO_TRIG[TRIG_ EN] Low-power support Deep Sleep: fully function when GENCS[STPE] STOP mode, VLPS mode: fully is set to 1 functioning when GENCS[STPE] is set Power Down: If the WAKE domain is active, TSI to 1. can operate as in "Deep Sleep" mode. Deep Power Down, VBAT: not available Low-power wake-up Each TSI channel can wake up the MCU from low-power mode. DMA support 1. Software trigger by writing the GENCS[SWTS] bit 2. Hardware trigger through INP UTMUX The out of range event or end of scan event can trigger the DMA transfer. Hardware noise filter SSC reduces the frequency noise and promotes the signalto-noise ratio (PRBS mode, up-down counter mode). 3.2 MCX Nx4x TSI new features Some new features are added to MCX Nx4x TSI. The most significant are listed in the table below. MCX Nx4x TSI provides a richer range of features for users. Like the functions of Baseline auto trace, Threshold auto trace, Debounce, these features can realize some hardware calculations. It saves software development resources. Table 5. MCX Nx4x TSI new features MCX Nx4x series 1 Proximity channels merge function 2 Baseline auto trace function 3 Threshold auto trace function UG10111 User guide All information provided in this document is subject to legal disclaimers. Rev. 1 — 7 May 2024 © 2024 NXP B.V. All rights reserved. 6 / 20 UG10111 NXP Semiconductors MCX Nx4x TSI User Guide Table 5. MCX Nx4x TSI new features...continued 4 Debounce function 5 Automatic trigger function 6 Clock from chip system clock 7 Test finger function 3.3 MCX Nx4x TSI function description Here is the description of these newly added features: 1. The proximity channels merge function The proximity function is used to merge multiple TSI channels for scanning. Configure TSI0_GENCS[S_PROX_EN] to 1 to enable the proximity mode, the value in TSI0_CONFIG[TSICH] is invalid, it is not used to select channel in proximity mode. The 25-bit register TSI0_CHMERGE[CHANNEL_ENABLE] is configured to select multiple channels, the 25-bit controls the selection of 25 TSI channels. It can select up to 25 channels, by configuring the 25 bits to 1 (1_1111_1111_1111_1111_1111_1111b). When a trigger occurs, the multiple channels selected by TSI0_CHMERGE[CHANNEL_ENABLE] are scanned together, and generate one set of the TSI scan value. The scan value can be read from register TSI0_DATA[TSICNT]. The proximity merge function theoretically integrates the capacitance of the multiple channels and then starts scanning, which is only valid in self-cap mode. The more touch channels merged can get a shorter scanning time, the smaller is the scanning value, and the poorer is the sensitivity. Therefore, when touch detect, more touch capacitance is needed to get the higher sensitivity. This function is suitable for the large area touch detect and large area proximity detect. 2. Baseline auto trace function The TSI of MCX Nx4x provides the register to set the baseline of TSI and the baseline trace function. After the TSI channel software calibration is complete, fill an initialize baseline value in the TSI0_BASELINE[BASELINE] register. The initial baseline of the touch channel in the TSI0_BASELINE[BASELINE] register is written in the software by the user. The setting of the baseline is valid only for one channel. The baseline trace function can adjust the baseline in the TSI0_BASELINE[BASELINE] register to make it close to the TSI current sample value. The baseline trace enable function is enabled by the TSI0_BASELINE[BASE_TRACE_EN] bit, and the autotrace ratio is set in the register TSI0_BASELINE[BASE_TRACE_DEBOUNCE]. The baseline value is increased or decreased automatically, the change value for each increase/decrease is BASELINE * BASE_TRACE_DEBOUNCE. The baseline trace function is only enabled in low-power mode and the setting is valid only for one channel. When the touch channel is changed, the baseline-related registers must be reconfigured. 3. Threshold auto trace function The threshold can be calculated by the IP internal hardware if the threshold trace is enabled by configuring the TSI0_BASELINE[THRESHOLD_TRACE_EN] bit to 1. The calculated threshold value is loaded to threshold register TSI0_TSHD. To get the desired threshold value, select the threshold ratio in TSI0_BASELINE[THRESHOLD_RATIO]. The threshold of the touch channel is calculated according to the below formula in the IP internal. Threshold_H: TSI0_TSHD[THRESH] = [BASELINE + BASELINE >>(THRESHOLD_RATIO+1)] Threshold_L: TSI0_TSHD[THRESL] = [BASELINE - BASELINE >>(THRESHOLD_RATIO+1)] BASELINE is the value in TSI0_BASELINE[BASELINE]. 4. Debounce function MCX Nx4x TSI provides the hardware debounce function, the TSI_GENCS[DEBOUNCE] can be used to configure the number of out-of-range events that can generate an interrupt. Only the out-of-range interrupt event mode supports the debounce function and the end-of-scan interrupt event does not support it. UG10111 User guide All information provided in this document is subject to legal disclaimers. Rev. 1 — 7 May 2024 © 2024 NXP B.V. All rights reserved. 7 / 20 UG10111 NXP Semiconductors MCX Nx4x TSI User Guide 5. Automatic trigger function. There are three trigger sources of TSI, including the software trigger by writing the TSI0_GENCS[SWTS] bit, the hardware trigger through INPUTMUX, and the automatic trigger by TSI0_AUTO_TRIG[TRIG_EN]. Figure 4 shows the automatically trigger-generated progress. TSI automatic trigger lp_osc clk_in 010 fro_12m 100 To TSI 32 KHz 00 Trigger clock divider TSI clock divider To TSI MAX: 25 MHz Trigger period counter Trigger generated 01 TSI_TRIG[TRIG_PERIOD_COUNTER] TSI_TRIG[TRIG_CLK_DIVIDER] SYSCON_TSICLKDIV[DIV] Trigger enable/disable TSI_TRIG[TRIG_EN] TSI_TRIG[TRIG_CLK_SEL] SYSCON_TSICLKSEL[SEL] aaa-055216 Figure 4. TSI automatic trigger generation block diagram The automatic trigger function is a new feature in MCX Nx4x TSI. This feature is enabled by setting TSI0_AUTO_TRIG[TRIG_EN] to 1. Once the automatic trigger is enabled, the software trigger and hardware trigger configuration in TSI0_GENCS[SWTS] is invalid. The time period between each trigger can be calculated by the below formula: Timer period between each trigger = trigger clock / trigger clock divider * trigger clock counter. Trigger clock: configure TSI0_AUTO_TRIG[TRIG_CLK_SEL] to select the automatic trigger clock source. Trigger clock divider: configure TSI0_AUTO_TRIG[TRIG_CLK_DIVIDER] to select the trigger clock divider. Trigger clock counter: configure TSI0_AUTO_TRIG[TRIG_PERIOD_COUNTER] to configure the trigger clock counter value. For the clock of the automatic trigger clock source, one is the lp_osc 32k clock, another is the FRO_12Mhz clock or the clk_in clock can be selected by TSICLKSEL[SEL], and divided by TSICLKDIV[DIV]. 6. Clock from chip system clock Usually, Kinetis E series TSI provides an internal reference clock to generate the TSI functional clock. For the TSI of MCX Nx4x, the operating clock cannot only be from the IP internal, but it can be from the chip system clock. MCX Nx4x TSI has two function clock source choices (by configuring TSICLKSEL[SEL]). As shown in Figure 5, one from the chip system clock can decrease the TSI operate power consumption, another is generated from the TSI internal oscillator. It can decrease the jitter of the TSI operate clock. TSI Main clock TSI internal oscillator 27.37 MHz 22.23 MHz 18.73 MHz 16.65 MHz 14.27 MHz 12.73 MHz 11.49 MHz 10.46 MHz GENCS[SETCLK] clk_in fro_12m 010 100 TSI clock To TSI divider MAX: 25 MHz No SSC 00 SSC_MODE = 10b Basic Main clock prescale + 1 SYSCON_TSICLKDIV[DIV] SSC SSC_MODE 01 TSI_MISC[OSC_CLK_SEL] SYSCON_TSICLKSEL[SEL] 1/2 Advanced SSC_MODE = 00b/10b Switching clock PRBS SSC Up-down counter SSC Touch key aaa-055217 Figure 5. Clock generation block diagram FRO_12 MHz clock or the clk_in clock is the TSI function clock source, it can be selected by TSICLKSEL[SEL] and divided by TSICLKDIV[DIV]. 7. Test finger function MCX Nx4x TSI provides the test finger function that can simulate a finger touch without a real finger touch on the hardware board by configuring the related register. This function is useful during the code debug and hardware board test. UG10111 User guide All information provided in this document is subject to legal disclaimers. Rev. 1 — 7 May 2024 © 2024 NXP B.V. All rights reserved. 8 / 20 UG10111 NXP Semiconductors MCX Nx4x TSI User Guide The strength of the TSI test finger can be configured by TSI0_MISC[TEST_FINGER], the user can change the touch strength through it. There are 8 options for the finger capacitance: 148pF, 296pF, 444pF, 592pF, 740pF, 888pF, 1036pF, 1184pF. The test finger function is enabled by configuring TSI0_MISC[TEST_FINGER_EN] to 1. The user can use this function to calculate the hardware touchpad capacitance, the TSI parameter debug and do the software safety /failure tests (FMEA). In the software code, configure the finger capacitance first and then enable the test finger function. 3.4 Example use case of MCX Nx4x TSI new function MCX Nx4x TSI has a feature for the low-power use case: • Use the chip system clock to save the IP power consumption. • Use automatic trigger function, proximity channels merge function, baseline auto trace function, threshold auto trace function, debounce function to do an easy low-power wake-up use case. 4 MCX Nx4x TSI hardware and software support NXP has four kinds of hardware boards to support the MCX Nx4x TSI evaluation. The X-MCX-N9XX-TSI board is the internal evaluation board, contract FAE/Marketing to request it. The other three boards are NXP official release boards and can be found on in the NXP web where the user can download the official supported software SDK and touch library. 4.1 MCX Nx4x series TSI evaluation board NXP provides evaluation boards to help users to evaluate the TSI function. The following is the detailed board information. 4.1.1 X-MCX-N9XX-TSI board The X-MCX-N9XX-TSI board is a touch sensing reference design including multiple touch patterns based on the NXP high-performance MCX Nx4x MCU that has one TSI module and supports up to 25 touch channels demonstrated on the board. The board can be used to evaluate the TSI function for the MCX N9x and N5x series MCU. This product has passed the IEC61000-4-6 3V certification. UG10111 User guide All information provided in this document is subject to legal disclaimers. Rev. 1 — 7 May 2024 © 2024 NXP B.V. All rights reserved. 9 / 20 UG10111 NXP Semiconductors MCX Nx4x TSI User Guide Figure 6. X-MCX-N9XX-TSI, MCX N5/N9 dedicated TSI evaluation board 4.1.2 MCX-N5XX-EVK MCX-N5XX-EVK provides the touch slider on the board, and it is compatible with the FRDM-TOUCH board. NXP provides a touch library to realize the functions of keys, slider, and rotary touches. Figure 7. MCX-N5XX-EVK with touch 4.1.3 MCX-N9XX-EVK MCX-N9XX-EVK provides the touch slider on the board, and it is compatible with the FRDM-TOUCH board. NXP provides a touch library to realize the functions of keys, slider, and rotary touches. UG10111 User guide All information provided in this document is subject to legal disclaimers. Rev. 1 — 7 May 2024 © 2024 NXP B.V. All rights reserved. 10 / 20 UG10111 NXP Semiconductors MCX Nx4x TSI User Guide Figure 8. MCX-N9XX-EVK with touch 4.1.4 FRDM-MCXN947 FRDM-MCXN947 provides a one-touch key on the board and it is compatible with the FRDM-TOUCH board. NXP provides a touch library to realize the functions of keys, slider, and rotary touches. Figure 9. FRDM-MCXN947 with touch UG10111 User guide All information provided in this document is subject to legal disclaimers. Rev. 1 — 7 May 2024 © 2024 NXP B.V. All rights reserved. 11 / 20 UG10111 NXP Semiconductors MCX Nx4x TSI User Guide 4.2 NXP touch library support for MCX Nx4x TSI NXP offers a touch software library free of charge. It provides all the software required to detect touches and to implement more advanced controllers like sliders or keypads. TSI background algorithms are available for touch keypad and analog decoders, sensitivity auto calibration, low-power, proximity, water tolerance. The SW is distributed in source code form in “object C language code structure”. And a touch tuner tool based on FreeMASTER is provided for TSI configuration and tune. 4.2.1 SDK build and touch library download The user can build SDK of MCX hardware boards from https://mcuxpresso.nxp.com/en/welcome, add the touch library to the SDK and download the package. The process is shown on Figure 10, Figure 11, and Figure 12. Figure 10. Build MCUXpresso SDK for selected board Figure 11. Add the touch library to SDK UG10111 User guide All information provided in this document is subject to legal disclaimers. Rev. 1 — 7 May 2024 © 2024 NXP B.V. All rights reserved. 12 / 20 UG10111 NXP Semiconductors MCX Nx4x TSI User Guide Figure 12. Download SDK 4.2.2 NXP touch library The touch sensing code in the downloaded SDK folder …\boards\frdmmcxn947\demo_apps\touch_ sensing is developed using the NXP touch library. The NXP Touch Library Reference Manual can be found in the folder …/middleware/touch/freemaster/ html/index.html, it describes the NXP Touch software library for implementing touch-sensing applications on NXP MCU platforms. The NXP Touch software library provides touch-sensing algorithms to detect finger touch, movement, or gestures. The FreeMASTER tool for TSI configure and tune is included into the NXP touch library. For more information, see the NXP Touch Library Reference Manual (document NT20RM) or NXP Touch Development Guide (document AN12709) . The basic building blocks of the NXP Touch library are shown in Figure 13: UG10111 User guide All information provided in this document is subject to legal disclaimers. Rev. 1 — 7 May 2024 © 2024 NXP B.V. All rights reserved. 13 / 20 UG10111 NXP Semiconductors MCX Nx4x TSI User Guide Application NT setup Callbacks Touch gui tool Debugging NXP touch library Controls Slider Analog slider Rotary Analog rotary Keypad Proxi Matrix System Electrodes Keydetectors Filters Electrode 1 AFID IIR Electrode 2 SAFA Electrode x Butterworth uSAFA DC tracker Modules TSI CS GPIO GPIOint Drivers TSI ver5 specific Common TSI ver4 specific CS MCUXpresso SDK drivers SDK TSI CS HW TSI CS GPIO INT aaa-055218 Figure 13. The basic building blocks of the NXP Touch library 5 MCX Nx4x TSI performance For MCX Nx4x TSI, the following parameters have been tested on the X-MCX-N9XX-TSI board. Here is the performance summary. Table 6. Performance summary MCX Nx4x series 1 SNR Up to 200:1 for self-cap mode and mutual-cap mode 2 Overlay thickness Up to 20 mm 3 Shield drive strength Up to 600pF at 1MHz, Up to 200pF at 2MHz 4 Sensor capacitance range 5pF – 200pF UG10111 User guide All information provided in this document is subject to legal disclaimers. Rev. 1 — 7 May 2024 © 2024 NXP B.V. All rights reserved. 14 / 20 UG10111 NXP Semiconductors MCX Nx4x TSI User Guide 1. SNR test The SNR is calculated according to the raw data of the TSI counter value. In the case when no algorithm is used to process the sampled values, SNR values of 200:1 can be achieved in self-cap mode and mutualcap mode. As shown in Figure 14, the SNR test has been performed on the TSI board on EVB. Noice Touch Signal No touch SNR = signal/noise Signal is difference value of averaging. Noise is 3 sigma distribution boundary. aaa-052119 Figure 14. SNR tested on board 2. Shield drive strength test The strong shield strength of TSI can improve the waterproof performance of the touchpad and can support a larger touchpad design on hardware board. When the 4 TSI shield channels are all enabled, the maximum driver capability of the shield channels is tested at 1 MHz and 2 MHz TSI working clocks in self-cap mode. The higher the TSI operating clock, the lower the drive strength of the shielded channel. If the TSI operating clock is lower than 1MHz, the maximum drive strength of the TSI is larger than 600 pF. To do the hardware design, refer to the test results shown in Table 7. Table 7. Shield driver strength test result Shield channel on Clock Max shield drive strength CH0, CH6, CH12, CH18 1 MHz 600 pF 2 MHz 200 pF 3. Overlay thickness test To protect the touch electrode from the interference of the external environment, the overlay material must be closely attached to the surface of the touch electrode. There should be no air gap between the touch electrode and the overlay. An overlay with a high dielectric constant or an overlay with a small thickness improves the sensitivity of the touch electrode. The maximum overlay thickness of the acrylic overlay material was tested on the X-MCX-N9XX-TSI board as shown in Figure 15 and Figure 16. The touch action can be detected on the 20 mm acrylic overlay. Here are the conditions to be fulfilled: • SNR>5:1 • Self-cap mode • 4 shield channels on • The sensitivity boost UG10111 User guide All information provided in this document is subject to legal disclaimers. Rev. 1 — 7 May 2024 © 2024 NXP B.V. All rights reserved. 15 / 20 UG10111 NXP Semiconductors MCX Nx4x TSI User Guide No air gap between touch electrode and overlay Overlay ∆Cs PCB Cs Electrode Cs Ground hatch via Ground hatch Ground hatch aaa-055220 Figure 15. Overlay thickness test base on the acrylic Figure 16. Overlay thickness test base on the acrylic 4. Sensor capacitance range test The recommended intrinsic capacitance of a touch sensor on a hardware board is in the range of 5 pF to 50 pF. The area of the touch sensor, the material of the PCB, and the routing trace on the board affect the size of the intrinsic capacitance. These must be considered during the hardware design of the board. After testing on the X-MCX-N9XX-TSI board, MCX Nx4x TSI can detect a touch action when the intrinsic capacitance is as high as 200 pF, the SNR is larger than 5:1. Therefore, the requirements for touch board design are more flexible. 6 Conclusion This document introduces the basic functions of TSI on MCX Nx4x chips. For details on the MCX Nx4x TSI principle, refer to the TSI chapter of the MCX Nx4x Reference Manual (document MCXNx4xRM). For suggestions of the hardware board design and touchpad design, refer to the KE17Z Dual TSI User Guide (document KE17ZDTSIUG). 7 References The following references are available on NXP website: 1. MCX Nx4x Reference Manual (document MCXNx4xRM) 2. KE17Z Dual TSI User Guide (document KE17ZDTSIUG) UG10111 User guide All information provided in this document is subject to legal disclaimers. Rev. 1 — 7 May 2024 © 2024 NXP B.V. All rights reserved. 16 / 20 UG10111 NXP Semiconductors MCX Nx4x TSI User Guide 3. NXP Touch development guide ( document AN12709) 4. NXP Touch Library Reference Manual (document NT20RM) 8 Revision history Table 8. Revision history Document ID Release date Description UG10111 v.1 7 May 2024 Initial version UG10111 User guide All information provided in this document is subject to legal disclaimers. Rev. 1 — 7 May 2024 © 2024 NXP B.V. All rights reserved. 17 / 20 UG10111 NXP Semiconductors MCX Nx4x TSI User Guide Legal information Definitions Draft — A draft status on a document indicates that the content is still under internal review and subject to formal approval, which may result in modifications or additions. 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Customer shall select products with security features that best meet rules, regulations, and standards of the intended application and make the ultimate design decisions regarding its products and is solely responsible for compliance with all legal, regulatory, and security related requirements concerning its products, regardless of any information or support that may be provided by NXP. NXP has a Product Security Incident Response Team (PSIRT) (reachable at [email protected]) that manages the investigation, reporting, and solution release to security vulnerabilities of NXP products. NXP B.V. — NXP B.V. is not an operating company and it does not distribute or sell products. Trademarks Notice: All referenced brands, product names, service names, and trademarks are the property of their respective owners. NXP — wordmark and logo are trademarks of NXP B.V. All information provided in this document is subject to legal disclaimers. Rev. 1 — 7 May 2024 © 2024 NXP B.V. All rights reserved. 18 / 20 UG10111 NXP Semiconductors MCX Nx4x TSI User Guide AMBA, Arm, Arm7, Arm7TDMI, Arm9, Arm11, Artisan, big.LITTLE, Cordio, CoreLink, CoreSight, Cortex, DesignStart, DynamIQ, Jazelle, Keil, Mali, Mbed, Mbed Enabled, NEON, POP, RealView, SecurCore, Socrates, Thumb, TrustZone, ULINK, ULINK2, ULINK-ME, ULINKPLUS, ULINKpro, μVision, Versatile — are trademarks and/or registered trademarks of Arm Limited (or its subsidiaries or affiliates) in the US and/or elsewhere. The related technology may be protected by any or all of patents, copyrights, designs and trade secrets. All rights reserved. UG10111 User guide Kinetis — is a trademark of NXP B.V. MCX — is a trademark of NXP B.V. Microsoft, Azure, and ThreadX — are trademarks of the Microsoft group of companies. All information provided in this document is subject to legal disclaimers. Rev. 1 — 7 May 2024 © 2024 NXP B.V. All rights reserved. 19 / 20 UG10111 NXP Semiconductors MCX Nx4x TSI User Guide Contents 1 2 2.1 2.2 2.3 3 3.1 3.2 3.3 3.4 4 4.1 4.1.1 4.1.2 4.1.3 4.1.4 4.2 4.2.1 4.2.2 5 6 7 8 Introduction ...................................................... 2 MCX Nx4x TSI overview ..................................2 MCX Nx4x TSI block diagram ........................... 2 MCX Nx4x parts supported TSI .........................3 MCX Nx4x TSI channel assignment on different packages ............................................. 3 MCX Nx4x TSI features ................................... 5 TSI comparison between MCX Nx4x TSI and Kinetis TSI .................................................. 5 MCX Nx4x TSI new features ............................. 6 MCX Nx4x TSI function description ................... 7 Example use case of MCX Nx4x TSI new function .............................................................. 9 MCX Nx4x TSI hardware and software support ..............................................................9 MCX Nx4x series TSI evaluation board .............9 X-MCX-N9XX-TSI board ....................................9 MCX-N5XX-EVK .............................................. 10 MCX-N9XX-EVK .............................................. 10 FRDM-MCXN947 .............................................11 NXP touch library support for MCX Nx4x TSI ................................................................... 12 SDK build and touch library download .............12 NXP touch library ............................................ 13 MCX Nx4x TSI performance ..........................14 Conclusion ..................................................... 16 References ......................................................16 Revision history .............................................17 Legal information ...........................................18 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © 2024 NXP B.V. All rights reserved. For more information, please visit: https://www.nxp.com Date of release: 7 May 2024 Document identifier: UG10111 ">
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