NXP TDA3681 Multiple voltage regulator Data Sheet

INTEGRATED CIRCUITS

DATA SHEET

TDA3681

Multiple voltage regulator with switch and ignition buffer

Product specification

Supersedes data of 2002 Apr 10

2004 Mar 31

Philips Semiconductors

Multiple voltage regulator with switch and ignition buffer

Product specification

TDA3681

FEATURES

General

•

Extremely low noise behaviour and good stability with very small output capacitors

•

Second supply pin for regulators 3 and 4 to reduce power dissipation (e.g. via a DC-to-DC converter)

•

Three V

P

-state controlled regulators (regulators 1, 3 and 4) and a power switch

•

Regulator 2, reset and ignition buffer operational during load dump and thermal shutdown

•

Combined control pin for switching regulators 1 and 3

•

Separate control pins for switching regulator 4 and the power switch

•

Supply voltage range from

−

18 to +50 V

•

Low quiescent current in standby mode (when regulators 1, 3 and 4 and power switch are switched off and ignition input is low)

•

Hold output (open-collector output stage) for low V

P

(regulators 1, 3 and 4 and power switch off)

•

Hold output when one of regulators 1 and 3 and/or 4 is out of regulation

•

Hold output for foldback mode of power switch and regulators 1, 3 and 4

•

Hold output for load dump and temperature protection

•

Reset (push-pull output stage) for regulator 2

•

Adjustable reset delay time

•

High supply voltage ripple rejection

•

Backup capacitor for regulator 2

•

One independent ignition buffer (active HIGH).

Protections

•

Reverse polarity safe (down to

−

18 V without high reverse current)

•

Able to withstand voltages up to 18 V at the outputs

(supply line may be short-circuited)

•

•

•

•

•

ESD protection on all pins

Thermal protections

Load dump protection

•

Foldback current limit protection for regulators 1, 2, 3 and 4

Delayed second current limit protection for the power switch (at short-circuit)

The regulator outputs and the power switch are

DC short-circuit safe to ground and supply (V

P

GENERAL DESCRIPTION

The TDA3681 is a multiple output voltage regulator with a power switch and an ignition buffer. It is intended for use in car radios with or without a microcontroller. The TDA3681 contains the following:

•

Four fixed voltage regulators with a foldback current protection (regulators 1, 2, 3 and 4). Regulator 2, which is intended to supply a microcontroller, also operates during load dump and thermal shutdown

•

Regulators 3 and 4 have a second supply pin that can be connected to a lower supply voltage (>6.5 V) to reduce the power dissipation

•

A power switch with protection, operated by a control input

•

Reset and hold outputs that can be used to interface with the microcontroller; the reset signal can be used to call up the microcontroller

•

Both supply pins can withstand load dump pulses and negative supply voltages

•

Regulator 2, which is in regulation at a backup voltage above 6.5 V

•

A provision for the use of a reserve supply capacitor that will hold enough energy for regulator 2 (5 V continuous) to allow a microcontroller to prepare for loss of voltage

•

An ignition input Schmitt trigger with push-pull output stage.

ORDERING INFORMATION

TYPE

NUMBER

TDA3681J

TDA3681JR

TDA3681TH

PACKAGE

NAME DESCRIPTION

DBS17P plastic DIL-bent-SIL power package; 17 leads (lead length 7.7 mm)

DBS17P plastic DIL-bent-SIL (special bent) power package; 17 leads

(lead length 12 mm)

HSOP20 plastic, heatsink small outline package; 20 leads; low stand-off height

).

VERSION

SOT243-3

SOT475-1

SOT418-3

2004 Mar 31 2

Philips Semiconductors



TDA3681

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN.

TYP.

MAX.

UNIT

Supplies

I

V

V

P1

P2 supply voltage 1 operating reverse polarity regulator 2 on jump start load dump protection non-operating t t

≤

10 minutes

≤

50 ms; t r

≥

2.5 ms supply voltage 2 operating reverse polarity non-operating regulator 2 on jump start load dump protection t

≤

10 minutes t

≤

50 ms; t r

≥

2.5 ms total quiescent supply current standby mode junction temperature

9.5

−

4

−

−

0

−

−

−

−

6.5

−

14.4

−

18

18

14.4

50

−

−

I q(tot)

T j

Voltage regulators

V

V

V

V o(REG1) o(REG2) o(REG3) o(REG4) output voltage of regulator 1 1 mA

≤

I

REG1 output voltage of regulator 2 1 mA

≤

I


≤

I


≤

I

REG4

≤

600 mA; V

P

≤

300 mA; V

P

= 14.4 V

= 14.4 V

8.0

4.75

8.5

5.0

≤

1400 mA; V

P

≤

1 A; V

P

= 14.4 V

= 14.4 V

4.75

3.14

5.0

3.3

Power switch

30

50

14.4

18

−

−

−

−

18

50

30

50

110

−

150

150

9.0

V

V

5.25

V

5.25

V

3.46

V

V

V

µ

A

°

C

V

V

V

V

V

V

V

V drop(SW)

M(SW) drop-out voltage peak current

I

I

SW

SW

= 1 A; V

P1

= 1.8 A; V

= 13.5 V

P1

= 13.5 V

−

−

3

0.45

1.0

−

0.65

1.8

−

V

V

A

2004 Mar 31 3



BLOCK DIAGRAMS


TDA3681

2004 Mar 31

V

P1

(14.4 V) 17

ENSW

V

P2

EN4

EN1/3

C

RES

IGN

IN

POWER SWITCH

16

(14 V/

3 A)

SW

11

&

BACKUP SWITCH

TEMPERATURE

LOAD DUMP

PROTECTION

14

(14 V/

100 mA)

BU

BACKUP CONTROL

REGULATOR 2

15

(5 V/

300 mA)

REG2

3

REGULATOR 4

4

(3.3 V/

1 A)

REG4

&

9

2

(5 V/

1400 mA)

REG3

&

REGULATOR 3

TDA3681J

TDA3681JR

REGULATOR 1

1

(8.5 V/

600 mA)

REG1

&

10

12

OR

+

&

7

8

5 6

IGNITION BUFFER

13

GND mgl902

Fig.1 Block diagram of TDA3681J and TDA3681JR.

HOLD

RES

IGN

OUT

4




TDA3681

2004 Mar 31

V

P1

(14.4 V) 14

8

ENSW

20

V

P2

EN4

HEATTAB n.c.

n.c.

6

11

15

18

EN1/3

7

C

RES

IGN

IN

5

2

POWER SWITCH

16

(14 V/

3 A)

SW

&

BACKUP SWITCH

TEMPERATURE

LOAD DUMP

PROTECTION

13

(14 V/

100 mA)

BU

BACKUP CONTROL

REGULATOR 2

REGULATOR 4

12

(5 V/

300 mA)

REG2

1

(3.3 V/

1 A)

REG4

&

19

(5 V/

1400 mA)

REG3

&

REGULATOR 3

TDA3681TH

REGULATOR 1

&

17

(8.5 V/

600 mA)

REG1

9

HOLD

+

OR

&

4

RES

3

IGNITION BUFFER

10

GND

Fig.2 Block diagram of TDA3681TH.

5 mgu353

IGN

OUT



PINNING

Pin description of TDA3681J and TDA3681JR

SYMBOL PIN

REG1

REG3

V

P2

REG4

IGN

IN

IGN

OUT

RES

C

RES

EN4

EN1/3

ENSW

HOLD

GND

BU

REG2

SW

V

P1

DESCRIPTION

1 regulator 1 output


3 second supply voltage


5 ignition input

6 ignition output (active HIGH)

7 reset output (active LOW)

8 reset delay capacitor

9 enable input for regulator 4

10 enable input for regulators 1 and 3

11 enable input for power switch

12 hold output (active LOW)

13

ground; note 1

14 backup switch output


16 power switch output

17 supply voltage

Note

1. The heat tab is internally connected to pin GND.

handbook, halfpage

REG1 1

REG3 2

VP2 3

REG4 4

IGNIN 5

IGNOUT 6

RES 7

CRES 8

EN4 9

TDA3681J

TDA3681JR

EN1/3 10

ENSW 11

HOLD 12

GND 13

BU 14

REG2 15

SW 16

VP1 17

MGL903


TDA3681

Fig.3

Pin configuration for TDA3681J and

TDA3681JR.

2004 Mar 31 6




TDA3681

Pin description of TDA3681TH

SYMBOL PIN DESCRIPTION

REG4

IGN

IN

IGN

OUT

RES

C

RES

EN4

EN1/3

ENSW


2 ignition input

3 ignition output (active HIGH)

4 reset output (active LOW)

5 reset delay capacitor

6 enable input for regulator 4

7 enable input for regulators 1 and 3

8 enable input for power switch

BU

V

P1 n.c.

SW

HOLD

GND

9 hold output (active LOW)

10 ground

HEATTAB 11

heat tab connection; note 1

REG2 12 regulator 2 output

13

14

15

16 backup switch output supply voltage not connected power switch output

REG1 n.c.

REG3

V

P2


18 not connected


20 second supply voltage

Note

1. The pin is used for final test purposes. In the application it should be connected directly to ground.

handbook, halfpage

VP2 20

REG3 19 n.c.

18

1 REG4

2 IGNIN

3 IGNOUT

4 RES REG1 17

SW 16

TDA3681TH n.c.

15

5 CRES

6 EN4

VP1 14

BU 13

REG2 12

HEATTAB 11

7 EN1/3

8 ENSW

9 HOLD

10 GND

MGU329

Fig.4 Pin configuration for TDA3681TH.

2004 Mar 31 7




TDA3681

FUNCTIONAL DESCRIPTION

The TDA3681 is a multiple output voltage regulator with a power switch, intended for use in car radios with or without a microcontroller. Because of the low voltage operation of the car radio, low voltage drop regulators are used.

Regulator 2 is in regulation when the backup voltage exceeds 6.5 V for the first time. When regulator 2 is switched on and its output voltage is within its voltage range, the reset output is disabled to release the microcontroller. The reset delay time before release can be extended by an external capacitor (C

RES

). This start-up feature is included to secure a smooth start-up of the microcontroller at first connection, without uncontrolled switching of regulator 2 during the start-up sequence.

The charge on the backup capacitor can be used to supply regulator 2 for a short period when the external supply voltage drops to 0 V (the time depends on the value of the backup capacitor).

The output stages of all switchable regulators have an extremely low noise behaviour and good stability, even for small values of the output capacitors.

When both regulator 2 and the supply voltages (V

P1 and

V

P2

> 4.5 V) are available, regulators 1 and 3 can be operated by means of one enable input.

Regulator 4 and the power switch have a separate enable input.

Pin HOLD is normally HIGH but is active LOW. Pin HOLD is connected to an open-collector NPN transistor and must have an external pull-up resistor to operate. The hold output is controlled by a low voltage detection circuit which, when activated, pulls the hold output LOW

(enabled). The hold outputs of the regulators are connected to an OR gate inside the IC so that the hold circuit is activated when one or more regulators (1, 3 or 4) are out of regulation for any reason. Each regulator enable input controls its own hold triggering circuit, so that if a regulator is disabled or switched off, the hold circuit for that regulator is disabled.

The hold circuit is also controlled by the temperature and load dump protection. Activating the temperature or load dump protection causes a hold (LOW) during the time that the protection is activated. When all regulators are switched off, the hold output is controlled by the battery line V

P1

, temperature protection and load dump protection.

The hold circuit is enabled at low battery voltages. This indicates that it is not possible to get regulator 1 into regulation when switching it on: regulator 1 has the highest output voltage (8.5 V) of all switchable regulators.

Therefore, regulator 1 is the most critical regulator with respect to an out of regulation condition caused by a low battery voltage.

The hold function includes hysteresis to avoid oscillations when the regulator voltage crosses the hold threshold level. The hold output also becomes active when the

power switch is in foldback protection mode; see Fig.8.

The block diagram of the hold function is illustrated in

Fig.5.

All output pins are fully protected. The regulators are protected against load dump (regulators 1, 3 and 4 switch off at supply voltages >18 V) and short-circuit (foldback current protection).

The power switch contains a current protection. However, this protection is delayed at short-circuit by the reset delay capacitor (it should be noted that this is the second function of the reset delay capacitor C

RES

). During this time, the output current is limited to a peak value of at least

3 A (after a delay, the power switch can deliver 1.8 A continuous if V

P

≤

18 V).

In a normal situation, the voltage on the reset delay capacitor is approximately 3.5 V (depending on the temperature). The power switch output is approximately

V

P

−

0.4 V. At operating temperature, the power switch can deliver at least 3 A. At high temperature, the switch can deliver approximately 2 A.

During an overload condition or a short circuit

(V

SW

< V

P

−

3.7 V), the voltage on the reset delay capacitor rises 0.6 V above the voltage of regulator 2. This rise time depends on the capacitor connected to pin C

RES

.

During this time, the power switch can deliver more than

3 A. When regulator 2 is out of regulation and generates a reset, the power switch can only deliver 2 A and will immediately go into foldback protection.

At supply voltages >17 V, the power switch is clamped at

16 V maximum (to avoid externally connected circuits being damaged by an overvoltage) and the power switch will switch off at load dump.

Interfacing with the microcontroller (simple full or semi on/off logic applications) can be realized with an independent ignition Schmitt trigger and ignition output buffer (push-pull output).

The timing diagrams are illustrated in Figs 6 and 7.

The second supply voltage V

P2 is used for the switchable regulators 3 and 4. This input can be connected to a lower supply voltage of

≥

6 V to reduce the power dissipation of the TDA3681. A DC-to-DC converter could be used for this purpose.

2004 Mar 31 8




TDA3681 handbook, full pagewidth

VP1 internal

voltage reference 1 low battery detector internal voltage reference 2 output stage

EN1/3 enable output of regulation detector

REGULATOR 1 output stage

EN4

TDA3681

REG1

REG3 enable output of regulation detector

REGULATOR 3 output stage

OR &

REG4

OR enable output of regulation detector

REGULATOR 4

TEMPERATURE

PROTECTION

LOAD DUMP

POWER SWITCH

FOLDBACK

MODE buffer

MGL904

HOLD

2004 Mar 31

Fig.5 Block diagram of the hold circuit.

9




TDA3681 load dump

V

P1

V

BU

6.5 V

5.4 V regulator 2 reset delay capacitor reset

5.0 V

0 V

5.0 V

3.0 V

0 V

5.0 V

Back-up Schmitt trigger and reset behaviour load dump

V

P1 = V P2 ignition input ignition output

50 V

0 V

−

100 V

5.0 V

0 V

>22 V

V

P1 = V P2 enable regulator 1/3

>1.8 V

<1.3 V enable regulator 4

>1.8 V

<1.3 V regulator 1 and 3 regulator 4 temperature protection

150

°

C active passive

HOLD

HIGH

LOW

2004 Mar 31

Enable Schmitt trigger ignition

Hold behaviour

Fig.6 Timing diagram of ignition Schmitt triggers and hold circuit.

10 mgl905




TDA3681 handbook, full pagewidth

VP1 = VP2

18 V

8.9 V

7.0 V

4.0 V enable regulator 1/3

≥ 1.8 V

1.3 V

8.5 V regulator 1 regulator 3

0 V

5.0 V

0 V enable regulator 4

> 1.8 V

<

1.3 V

3.3 V regulator 4

0 V

VP

16.9 V

7.0 V

4.0 V enable power switch

>

1.8 V

<

1.3 V

16 V power switch output

0 V load dump

VP and enable Schmitt trigger load dump

Power switch behaviour

MGL906

2004 Mar 31

Fig.7 Timing diagram of regulators and power switch.

11




TDA3681

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134).

SYMBOL

V

P1

V

P

P2

T stg

T amb

T j tot

PARAMETER supply voltage 1 operating reverse polarity jump start load dump protection supply voltage 2 operating reverse polarity jump start load dump protection total power dissipation storage temperature ambient temperature junction temperature t non-operating

≤

CONDITIONS

10 minutes

−

−

− t

≤

50 ms; t r

≥

2.5 ms

− non-operating

MIN.

t

≤

10 minutes non-operating

− t

≤

50 ms; t r

≥

2.5 ms

−

−

−

55 operating operating

−

−

−

40

−

40

18

18

30

50

MAX.

18

18

30

50

62

+150

+85

+150

V

V

V

V

W

°

C

°

C

°

C

V

V

V

V

UNIT

THERMAL CHARACTERISTICS

SYMBOL

R th(j-c)

R th(j-a)

PARAMETER thermal resistance from junction to case thermal resistance from junction to ambient

CONDITIONS in free air

QUALITY SPECIFICATION

In accordance with “General Quality Specification For Integrated Circuits (SNW-FQ-611D)”.

VALUE

1.3

50

UNIT

K/W

K/W

2004 Mar 31 12




TDA3681

CHARACTERISTICS

V

P

= V

P1

= V

P2

= 14.4 V; T amb

= 25

°

C; measured in test circuits of Figs 10 and 11; unless otherwise specified.


TYP.

MAX.

UNIT

Supplies

V

V

P1

P2 supply voltage 1 operating reverse polarity non-operating regulator 2 on

note 1

jump start t

≤

10 minutes load dump protection t

≤

50 ms; t r

≥

2.5 ms supply voltage 2 operating reverse polarity non-operating

I

V bat(loaddump) q(tot) regulator 2 on jump start t

≤

10 minutes load dump protection t

≤

50 ms; t r

≥

2.5 ms battery overvoltage shutdown

V

P1 and/or V

P2 total quiescent supply current

V

P

= 12.4 V; note 2

V

P

= 14.4 V; note 2

Schmitt trigger for power supply (regulators 1, 3 and 4)

9.5

−

4

−

−

6.5

−

0

−

−

18

−

−

14.4

−

14.4

−

−

14.4

−

−

−

−

20

105

110

18

18

50

30

50

18

18

50

30

50

22

145

150

V

V

V

V

V

µ

µ

A

A

V th(r)

V th(f)

V hys rising threshold voltage V falling threshold voltage V hysteresis voltage

P1

P1

rising

falling

Schmitt trigger for enable input (regulators 1, 3, 4 and power switch)

6.5

7.0

4.0

4.5

−

2.5

V th(r)

V th(f)

V hys

I

LI rising threshold voltage falling threshold voltage hysteresis voltage input leakage current

Reset trigger level of regulator 2

I

REG

V

EN

= I

SW

= 5 V

= 1 mA

1.4

1.8

0.9

1.3

−

0.5

1 5

V

V th(r) th(f) rising threshold voltage V

P1 rising; I

note 3

REG2

= 50 mA; falling threshold voltage V

P1 falling; I

note 3

REG2

= 50 mA;

7.5

5.0

−

2.4

1.9

−

20

4.43

V

REG2

−

0.15 V

REG2

−

0.1

4.4

V

REG2

−

0.25 V

REG2

−

0.13

V

V

V

V

V

V

V

V

µ

A

V

V

V

V

V

V

Schmitt triggers for hold circuit output

V th(r)(REG1)

V

V th(f)(REG1) hys(REG1) rising threshold voltage of regulator 1 falling threshold voltage of regulator 1 hysteresis voltage due to regulator 1

V

P1

rising; note 3

V

P1

falling; note 3

−

7.67

−

V

V

REG1

REG1

0.2

−

0.15 V

−

0.35

−

−

REG1

−

0.075 V

V

V

2004 Mar 31 13




TDA3681

V

V

V

V

V

V

V

V

V

SYMBOL th(r)(REG3) th(f)(REG3) hys(REG3) th(r)(REG4) th(f)(REG4) hys(REG4) th(r)(VP) th(f)(VP) hys(VP)

PARAMETER rising threshold voltage of regulator 3 falling threshold voltage of regulator 3 hysteresis voltage due to regulator 3 rising threshold voltage of regulator 4 falling threshold voltage of regulator 4 hysteresis voltage due to regulator 4 rising threshold voltage of supply voltage falling threshold voltage of supply voltage hysteresis voltage of supply voltage t r t f

Reset and hold buffer

I sink(L)

I

LO

I source(H)

LOW-level sink current output leakage current

HIGH-level source current rise time fall time

Reset delay

V

P2

V

V

V

V

V

V

V

V

V

P2

P2

P2

EN

EN

EN

P2

P2

CONDITIONS

rising; note 3 falling; note 3 rising; note 3 falling; note 3

RES

= 0 V

= 0 V

= 0 V

note 4 note 4

≤

0.8 V; V

= 14.4 V; V

HOLD

= 14.4 V; V

HOLD

RES

≤

0.8 V

= 5 V

≥

4.5 V t t

I

I ch dch

V

V th(r)(RES) th(f)(RES) d(RES) d(SW) reset delay capacitor charge current reset delay capacitor discharge current rising voltage threshold reset signal falling voltage threshold reset signal delay reset signal delay power switch foldback protection

V

V

V

C

C

CRES

CRES

P1

= V

RES

RES

= 0 V

= 3 V;

P2

= 4.3 V

= 47 nF; note 5

= 47 nF; note 6

Regulator 1 (I

REG1

= 5 mA; unless otherwise specified)

V o(off)

V o(REG1)

∆

V

∆

V line load output voltage off output voltage line regulation load regulation

1 mA

≤

I

9.5 V

≤

REG1

V

P1

9.5 V

≤

V

P1

≤

600 mA

≤

18 V

≤

1 mA

≤

I

REG1

18 V

≤

600 mA

MIN.

−

TYP.

MAX.

UNIT

V

REG3

−

0.15 V

REG3

−

0.075 V

4.3

V

REG3

−

0.35

−

−

0.2

−

V

V

−

V

REG4

−

0.15 V

REG4

−

0.075 V

2.7

V

REG4

−

0.3

−

−

0.15

−

V

V

9.1

9.7

10.3

V

9.0

−

2

−

240 400

−

−

2

1.0

2.5

1.0

20

8

9.4

0.3

−

0.1

7

1

4

1.6

3.0

1.2

35

17.6

−

1

8.0

8.5

8.0

8.5

−

2

−

20

9.8

−

−

5

900

50

50

8

−

3.5

1.4

70

40

400

9.0

9.0

75

85

V

V mA

µ

A

µ

A

µ s

µ s

µ mA

V

V

A ms ms mV

V

V mV mV

2004 Mar 31 14




TDA3681

I q

SYMBOL

SVRR

V drop(REG1)

I m(REG1)

I sc(REG1)

PARAMETER quiescent current supply voltage ripple rejection drop-out voltage current limit short-circuit current f

I i

REG1

CONDITIONS

= 600 mA

= 3 kHz; V i

= 2 V (p-p)

I

REG1

note 7

= 550 mA; V

P1

= 8.55 V;

V

REG1

R

L

> 7 V; note 8

≤

0.5

Ω

; note 9

I

I

Regulator 2 (I

REG2


V

∆

∆ o(REG2)

V

V line load output voltage line regulation load regulation

0.5 mA

≤

I

REG2

7 V

≤

V

P1

≤

≤

18 V

300 mA

I

18 V

≤

V

REG2

P1

≤

50 V;

≤

150 mA

6 V

≤

V

P1

6 V

≤

V

P1

≤

18 V

≤

50 V

1 mA

≤

I

REG2

1 mA

≤

I

REG2

≤

150 mA

≤

300 mA

SVRR supply voltage ripple rejection f i

= 3 kHz; V i

= 2 V (p-p)

V drop(REG2) drop-out voltage I

REG2

note 7

= 100 mA; V

P1

= 4.75 V;

I

REG2

note 7

= 200 mA; V

P1

= 5.75 V; m(REG2) sc(REG2) current limit short-circuit current

I

REG2

= 100 mA; V

note 10

BU

= 4.75 V;

I

REG2

= 200 mA; V

note 10

BU

= 5.75 V;

V

REG2

R

L

> 4.5 V; note 8

≤

0.5

Ω

; note 9

MIN.

−

60

−

0.65

250

4.75

4.75

5.0

4.75

5.0

−

−

−

−

50

−

−

−

−

0.32

95

25

70

0.4

1.2

800

5.0

I

Regulator 3 (I

REG3


V

V

∆ o(off) o(REG3)

∆

V q

V line load

SVRR output voltage off output voltage line regulation load regulation quiescent current supply voltage ripple rejection

−

1

I

1 mA

≤

I

REG3

7 V

≤

V

P1

≤

1400 mA and/or V

P2

≤

18 V

4.75

4.75

5.0

5.0

7 V

≤

V

P1

1 mA

≤

I and/or V

P2

REG3

≤

18 V

≤

1400 mA

−

−

2

20

REG3

= 1400 mA

−

19 f i

= 3 kHz; V i

= 2 V (p-p) 60 70

V drop(REG3) drop-out voltage I

REG3

note 7

= 1400 mA ; V

P2

= 6 V;

−

1

I m(REG3)

I sc(REG3) current limit short-circuit current

V

REG3

R

L

> 4.5 V; note 8

≤

0.5

Ω

; note 9

1.5

430

1.7

750

2

15

20

−

55

0.4

0.8

0.2

0.8

0.37

120

TYP.

1.5

−

−

400

5.25

5.25

50

150

45

−

5.25

5.25

5.25

50

75

50

100

−

0.6

1.2

0.5

1.0

−

−

60

−

MAX.

0.7

−

−

V

A mA mV

V

V mV mV mA dB

V

V

V mV mV mV mV dB

V

V

V

V

A mA

UNIT mA dB

V

A mA

2004 Mar 31 15




TDA3681


TYP.

I

I

I

I

I

I

Regulator 4 (I

REG4


V

V

∆ q o(off) o(REG4)

V

∆

V line load output voltage off output voltage line regulation load regulation quiescent current

−

1

I

1 mA

≤

I

REG4

6.5 V

≤

V

P1

≤

1 A and/or V

P2

6.5 V

≤

V

1 mA

≤

I

P1 and/or V

P2

REG4

≤

1 A

REG4

= 1 A

3.14

≤

18 V 3.14

3.3

≤

18 V

−

2

−

−

3.3

20

15

SVRR supply voltage ripple rejection f i

= 3 kHz; V i

= 2 V (p-p) 60 70

V drop(REG4) m(REG4) sc(REG4) drop-out voltage current limit short-circuit current

I

REG4

= 1 A; V

P2

= 5 V; note 7

−

V

REG4

R

L

> 3.0 V; note 8

≤

0.5

Ω

; note 9

1.1

1.5

470

1.7

750

Power switch

V drop(SW) drop-out voltage

−

0.45

DC(SW)

V

M(SW)

V clamp(SW) fb(SW) continuous current clamping voltage peak current

I

SW

= 1 A; V

note 11

P1

= 13.5 V;

I

SW

= 1.8 A; V

note 11

P1

= 13.5 V;

V

P1

V

P1

= 16 V; V

SW

≥

17 V;

1 mA < I

SW

= 13.5 V

< 1.8 A

V

P1

< 17 V;

notes 6, 12 and 13

I

SW

=

−

100 mA

−

1.8

13.5

3

−

1.0

2.0

15.0

−

V

P1

+ 3 sc(SW) flyback voltage behaviour short-circuit current V

P1

= 14.4 V; V

note 13

SW

< 1.2 V; 0.5

1.7

Backup switch

I

I

DC(BU)

V clamp(BU) r(BU) continuous current clamping voltage reverse current

V

BU

> 5 V

V

V

P1

P1

0.3

≥

16.7 V; I

= 0 V; V

BU

REG2

= 100 mA

−

= 12.4 V

−

Schmitt trigger for enable ignition input

V th(r)(IGNIN)

V

V

I

LI

V th(f)(IGNIN) hys(IGNIN)

I i(clamp)

V

IH(clamp)

IL(clamp) rising threshold voltage of ignition input falling threshold voltage of ignition input hysteresis voltage input leakage current input clamp current

HIGH-level input clamping voltage

LOW-level input clamping voltage

V

P1

> 3.5 V

V

V

V

P1

P

> 3.5 V

> 3.5 V

V

IGNIN

V

IGNIN

IGNIN

= 5 V

≤

50 V

≥ −

100 V

1.9

2.2

1.7

0.1

−

−

V

−

P1

0.6

0.35

−

−

2.0

0.2

−

−

−

−

2004 Mar 31 16

0.65

1.8

−

16.0

−

22

−

400

3.46

3.46

50

50

40

−

2.4

−

−

−

16

900

2.5

2.3

0.5

1.0

50

50

0

MAX.

UNIT

A

V

µ

A

V

V

V

µ

A mA

V

V

A

V

A

V

V

A

V mV

V

V mV mV mA dB

V

A mA




TDA3681


I

I t t

Ignition buffer

V

OL

V

OH

OL

OH

PLH

PHL

LOW-level output voltage I

IGNOUT

= 0 mA

HIGH-level output voltage

I

IGNOUT

= 0 mA

LOW-level sink current

HIGH-level source current

V

IGNOUT

V

IGNOUT

≤

0.8 V

≥

4.5 V

LOW-to-HIGH propagation time

0

4.5

0.45

0.45

V

IGNIN

rising from 1.7 to 2.5 V

−

0.2

5.0

0.8

2.0

−

HIGH-to-LOW propagation time

V

IGNIN

falling from 2.5 to 1.7 V

− −

Temperature protection

T j(sd)

T j(hold) junction temperature for shutdown junction temperature for hold trigger

150

150

160

160

TYP.

0.8

5.25

−

−

500

500

170

170

MAX.

UNIT

V

V mA mA

µ

µ

°

° s s

C

C

Notes

1. Minimum operating voltage, only if V

P1

has exceeded 6.5 V.

2. The total quiescent current is measured in the standby mode. Therefore, the enable inputs of regulators 1, 3, 4 and the power switch are grounded and R

L(REG2)

=

∞

; see Figs 10 and 11.

3. The voltage of the regulator drops as a result of a V

P1 drop for regulators 1 and 2. Regulators 3 and 4 drop as a result of V

P2

drop.

4. The rise and fall times are measured with a 10 k

Ω

pull-up resistor and a 50 pF load capacitor.

5. The delay time depends on the value of the reset delay capacitor: t d(RES)

=

C

------

×

V

I ch

C(th)

= C

× (

750

×

10

3 )

6. The delay time depends on the value of the reset delay capacitor: t d(SW)

=

I

C

-----ch

×

V

C(th)

= C

× (

375

×

10

3 )

7. The drop-out voltage of regulators 1 and 2 is measured between pins V

P1

and REGn. The drop-out voltage of regulators 3 and 4 is measured between pins V

P2

and REGn.

8. At current limit, I m(REGn)

is held constant (see Fig.8).

9. The foldback current protection limits the dissipated power at short-circuit (see Fig.8).

10. The drop-out voltage is measured between pins BU and REG2.

11. The drop-out voltage of the power switch is measured between pins V

P1 and SW.

12. The maximum output current of the power switch is limited to 1.8 A when the supply voltage exceeds 18 V.

13. At short-circuit, I sc(SW) of at least 10 ms.

of the power switch is held constant to a lower value than the continuous current after a delay

2004 Mar 31 17


Multiple voltage regulator with switch and ignition buffer handbook, halfpage

8.5 V

Vo(REG1)

MGL907 handbook, halfpage

Vo(REG2)

5.0 V


TDA3681


Vo(REG3)

5.0 V

Isc(REG2)

Isc(REG1) a. Regulator 1.

IREG1

Im(REG1)


Vo(REG4)

3.3 V b. Regulator 2.

IREG2

Im(REG2)

MGL910 handbook, full pagewidth

2004 Mar 31

Isc(REG3)

IREG3

Im(REG3) Isc(REG4) d. Regulator 4.

IREG4 c. Regulator 3.

Fig.8 Foldback current protection of the regulators.

Im(REG4)

MGR931

VSW

VP

−

3.3 V generates hold delayed not delayed

2VBE

1 A

>

1.8 A

ISW

>

3 A

Fig.9 Current protection of the power switch.

18



TEST AND APPLICATION INFORMATION

Test information


TDA3681

V

P1

V

ENSW

V

EN1/3

V

EN4

V

P2

V

BU

V

IGNIN

C1

220 nF

C7

220 nF

(1) supply voltage 1

C13

1000 µ F

17 enable input power switch enable input regulator 1/3 enable input regulator 4

(1)

11

10

9 supply voltage 2

C14

1000

µ

F

3

TDA3681J

TDA3681JR power switch output

16

15

1

C16

100 nF regulator 1 output

C17


2

C15


C18


4

C19

100 nF reset delay capacitor

C8

47 nF

8

7 reset output

R6

10 k

Ω

(2)

C10

100

µ

F backup

14 ignition input

5

C11

1 nF

12 hold output

13 ground

6 ignition output

C2

10

µ

F

5 V

C3

10 µ F

C4

10

µ

F

8.5 V

5 V

C5

10 µ F

C6

10

µ

F

3.3 V

R3

10 k Ω

(3)

C9

50 pF

(3)

C12

50 pF mgl911

R

L(SW)

12 k

Ω

R

L(REG2)

5 k

Ω

R

L(REG1)

10 k Ω

R

L(REG3)

5 k

Ω

R

L(REG4)

5 k

Ω

(1) A minimum capacitor of 220 nF on the supply lines V

P1

and V

P2

is required for stability.

(2) A minimum capacitor of 1

µ

F for backup supply is required for stability.

(3) Capacitor represents the typical input capacitance of CMOS logic connected to the reset and hold outputs.

Fig.10 Test circuit of TDA3681J and TDA3681JR.

2004 Mar 31 19




TDA3681

V

P1

V

ENSW

V

EN1/3

V

EN4

V

P2

V

BU

V

IGNIN

C1

220 nF

C7

220 nF


C13

1000

µ

F enable input power switch enable input regulator 1/3 enable input regulator 4


20

C14

1000

µ

F

14

8

7

6

TDA3681TH power switch output

16

C15


12

C16


17

C17


19

1

C18


C19

100 nF reset delay capacitor

5

C8

47 nF

4 reset output

R6

10 k

Ω

(2)

C10

100 µ F backup

13 ignition input

C11

1 nF

2

11 heat tab

9 hold output

3

10 ground ignition output

C2

10

µ

F

5 V

C3

10

µ

F

C4

10

µ

F

8.5 V

5 V

C5

10

µ

F

C6

10

µ

F

3.3 V

R3

10 k

Ω

(3)

C9

50 pF

(3)

C12

50 pF mgu355

R

L(SW)

12 k Ω

R

L(REG2)

5 k

Ω

R

L(REG1)

10 k

Ω

R

L(REG3)

5 k

Ω

R

L(REG4)

5 k

Ω

(1) A minimum capacitor of 220 nF on the supply lines V

P1

and V

P2

is required for stability.

(2) A minimum capacitor of 1

µ

F for backup supply is required for stability.

(3) Capacitor represents the typical input capacitance of CMOS logic connected to the reset and hold outputs.

Fig.11 Test circuit of TDA3681TH.

2004 Mar 31 20




TDA3681

Application information

N OISE

Table 1 Noise figures

REGULATOR

1

2

3

4

NOISE FIGURE (

µ

V) (1)

C o

= 10

µ

F C o

= 47

µ

F C o

= 100

µ

F

170

440

120

85

110

240

100

70

110

190

80

55

Note

1. Measured at a bandwidth of 30 kHz.

The noise on the supply line depends on the value of the supply capacitor and is caused by a current noise (the output noise of the regulators is translated to a current noise by the output capacitors). The noise is minimal when a high frequency capacitor of 220 nF in parallel with an electrolytic capacitor of 100

µ

F is connected directly to the supply pins V

P1

, V

P2

and GND.

S TABILITY

The regulators are stabilized by the externally connected output capacitors.

The output capacitors can be selected by using the graphs

given in Figs 12 and 13. When an electrolytic capacitor is

used, its temperature behaviour can cause oscillations at a low temperature. The two examples below show how an output capacitor value is selected.

Example 1

Regulators 1, 3 and 4 are stabilized with an electrolytic output capacitor of 220

µ

F (ESR = 0.15

Ω

).

At T amb

= −

30

°

C, the capacitor value is decreased to

73

µ

F and the ESR is increased to 1.1

Ω

. The regulator remains stable at T amb

=

−

30

°

C; see Fig.12.

Example 2

Regulator 2 is stabilized with a 10

µ

F electrolytic capacitor

(ESR = 3

Ω

). At T amb

=

−

30

°

C, the capacitor value is decreased to 3

µ

F and the ESR is increased to 23.1

Ω

.

As can be seen from Fig.13, the regulator will be unstable

at T amb

=

−

30

°

C.

Solution

To avoid problems with stability at low temperatures, the use of tantalum capacitors is recommended. Use a tantalum capacitor of 10

µ

F or a larger electrolytic capacitor.

handbook, halfpage

20

ESR

(

Ω

)

15

10

5

0

0.1

MGL912 maximum ESR stable region

1 10

C (

µ

F)

100 handbook, halfpage

14

ESR

( Ω )

12

10

8

6

4

2

0

−

2

0.22

maximum ESR stable region

MGL913

1 minimum ESR

10

C (

µ

F)

100

Fig.12 Curve for selecting the value of the output capacitor for regulators 1, 3 and 4.

2004 Mar 31 21

Fig.13 Curve for selecting the value of the output capacitor for regulator 2.



PACKAGE OUTLINES

DBS17P: plastic DIL-bent-SIL power package; 17 leads (lead length 7.7 mm) non-concave x

D

Eh

D h


TDA3681

SOT243-3 view B: mounting base side

A

2 d

B j E

A

1

Z e e

1 b p w M

17

L

L

3

Q m e c

2 v

M

0 5 scale

10 mm

DIMENSIONS (mm are the original dimensions)

UNIT A A

2 b p c D

(1) d D h mm

17.0

15.5

4.6

4.4

0.75

0.60

0.48

0.38

24.0

23.6

20.0

19.6

10

E

(1) e e

1 e

2

12.2

11.8

2.54

1.27

5.08

E h

6 j

3.4

3.1

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

L

8.4

7.0

L

3

2.4

1.6

m

4.3

Q

2.1

1.8

v

0.6

w x Z

(1)

0.25

0.03

2.00

1.45

OUTLINE

VERSION

SOT243-3

IEC

REFERENCES

JEDEC JEITA

EUROPEAN

PROJECTION

ISSUE DATE

99-12-17

03-03-12

2004 Mar 31 22




TDA3681

DBS17P: plastic DIL-bent-SIL (special bent) power package; 17 leads (lead length 12 mm) non-concave x

D

D h

Eh

SOT475-1 d view B: mounting base side

A

2

B j E

A

L

3

L

Q

1

Z w M

17 e

1 e

2 c v M e b p m

0 5 scale

10 mm


UNIT A A

2 b p c D

(1) d D h mm

17.0

15.5

4.6

4.4

0.75

0.60

0.48

0.38

24.0

23.6

20.0

19.6

10

E

(1) e e

1 e

2

12.2

11.8

2.54

1.27

5.08

E h

6 j L

3.4

3.1

12.4

11.0

L

3

2.4

1.6

m

4.3

Q

2.1

1.8

v

0.8

w

0.4

x Z

(1)

0.03

2.00

1.45

Note


OUTLINE

VERSION

SOT475-1

IEC

REFERENCES

JEDEC JEITA

EUROPEAN

PROJECTION

ISSUE DATE

99-12-17

03-03-12

2004 Mar 31 23




TDA3681

HSOP20: plastic, heatsink small outline package; 20 leads; low stand-off height SOT418-3

D x

E A

X c y E2

HE v M A

D1

10

D2

1 pin 1 index

E1

A2

A4

Q

Lp

(A3)

A

θ detail X

20

Z e bp

11 w M

0 5 scale

10 mm


UNIT

A max.

mm 3.5

A2

3.5

3.2

A3

0.35

A4

(1)

+

0.08

−

0.04

bp

0.53

0.40

c

0.32

0.23

D

(2)

16.0

15.8

D1

13.0

12.6

D2

1.1

0.9

E

(2)

11.1

10.9

E1

6.2

5.8

E2

2.9

2.5

e HE

1.27

14.5

13.9

Lp

1.1

0.8

Q

1.7

1.5

v w x y Z

0.25

0.25

0.03

0.07

2.5

2.0

Notes

1. Limits per individual lead.


OUTLINE

VERSION

SOT418-3

IEC

REFERENCES

JEDEC JEITA

EUROPEAN

PROJECTION

ISSUE DATE

02-02-12

03-07-23

θ

8

°

0

°

2004 Mar 31 24




TDA3681

SOLDERING

Introduction

This text gives a very brief insight to a complex technology.

A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).

There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mount components are mixed on one printed-circuit board. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing.

Through-hole mount packages

S OLDERING BY DIPPING OR BY SOLDER WAVE

Typical dwell time of the leads in the wave ranges from

3 to 4 seconds at 250

°

C or 265

°

C, depending on solder material applied, SnPb or Pb-free respectively.

The total contact time of successive solder waves must not exceed 5 seconds.

The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (T stg(max)

). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit.

M ANUAL SOLDERING

Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the seating plane or not more than

2 mm above it. If the temperature of the soldering iron bit is less than 300

°

C it may remain in contact for up to

10 seconds. If the bit temperature is between

300 and 400

°

C, contact may be up to 5 seconds.

Surface mount packages

R EFLOW SOLDERING

Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven.

Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method.

Typical reflow peak temperatures range from

215 to 270

°

C depending on solder paste material. The top-surface temperature of the packages should preferably be kept:

• below 225

°

C (SnPb process) or below 245

°

C (Pb-free process)

– for all the BGA, HTSSON..T and SSOP-T packages

– for packages with a thickness

≥

2.5 mm

– for packages with a thickness < 2.5 mm and a volume

≥

350 mm 3 so called thick/large packages.

• below 240

°

C (SnPb process) or below 260

°

C (Pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm 3 so called small/thin packages.

Moisture sensitivity precautions, as indicated on packing, must be respected at all times.

W AVE SOLDERING

Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems.

To overcome these problems the double-wave soldering method was specifically developed.

2004 Mar 31 25




TDA3681

If wave soldering is used the following conditions must be observed for optimal results:

•

Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave.

•

For packages with leads on two sides and a pitch (e):

– larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the printed-circuit board.

The footprint must incorporate solder thieves at the downstream end.

•

For packages with leads on four sides, the footprint must be placed at a 45

° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners.

During placement and before soldering, the package must be fixed with a droplet of adhesive.

The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured.

Typical dwell time of the leads in the wave ranges from

3 to 4 seconds at 250

°

C or 265

°

C, depending on solder material applied, SnPb or Pb-free respectively.

A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.

M ANUAL SOLDERING

Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead.

Contact time must be limited to 10 seconds at up to

300

°

C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320

°

C.

2004 Mar 31 26




TDA3681

Suitability of IC packages for wave, reflow and dipping soldering methods

MOUNTING PACKAGE

(1)

Through-hole mount CPGA, HCPGA

DBS, DIP, HDIP, RDBS, SDIP, SIL

PMFP (4)

Through-holesurface mount

Surface mount

BGA, HTSSON..T

(5) , LBGA, LFBGA, SQFP,

SSOP-T

(5)

, TFBGA, USON, VFBGA

DHVQFN, HBCC, HBGA, HLQFP, HSO,

HSOP, HSQFP, HSSON, HTQFP, HTSSOP,

HVQFN, HVSON, SMS

PLCC

(7) , SO, SOJ

LQFP, QFP, TQFP

SSOP, TSSOP, VSO, VSSOP

CWQCCN..L

(11) , PMFP (10) , WQCCN32L (11)

suitable

suitable (3)

not suitable not suitable not suitable

SOLDERING METHOD

WAVE

(6)

REFLOW (2)

−

−

DIPPING suitable

− not suitable

− suitable suitable

−

− suitable not recommended

(7)(8)

not recommended

(9)

not suitable suitable suitable suitable

− not suitable

−

−

−

Notes

1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy from your Philips Semiconductors sales office.

2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the

Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.

3. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board.

4. Hot bar soldering or manual soldering is suitable for PMFP packages.

5. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217

°

C

±

10

°

C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible.

6. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface.

7. If wave soldering is considered, then the package must be placed at a 45

°

angle to the solder wave direction.

The package footprint must incorporate solder thieves downstream and at the side corners.

8. Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

9. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than

0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

10. Hot bar or manual soldering is suitable for PMFP packages.

11. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate soldering profile can be provided on request.

2004 Mar 31 27




TDA3681

DATA SHEET STATUS

I

LEVEL

II

III

DATA SHEET

STATUS

(1)

PRODUCT

STATUS (2)(3)

DEFINITION

Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice.

Preliminary data Qualification This data sheet contains data from the preliminary specification.

Supplementary data will be published at a later date. Philips

Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product.

Product data Production This data sheet contains data from the product specification. Philips

Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification

(CPCN).

Notes

1. Please consult the most recently issued data sheet before initiating or completing a design.

2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.

3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

DEFINITIONS

Short-form specification



The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook.

Limiting values definition



Limiting values given are in accordance with the Absolute Maximum Rating System

(IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device.

These are stress ratings only and operation of the device at these or at any other conditions above those given in the

Characteristics sections of the specification is not implied.

Exposure to limiting values for extended periods may affect device reliability.

Application information



Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

DISCLAIMERS

Life support applications



These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips

Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes



Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production

(status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change

Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.

2004 Mar 31 28

Philips Semiconductors – a worldwide company

Contact information

For additional information please visit http://www.semiconductors.philips.com.

Fax: +31 40 27 24825

For sales offices addresses send e-mail to: [email protected].

© Koninklijke Philips Electronics N.V. 2004 SCA76

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.

Printed in The Netherlands

R32/06/pp 29 Date of release: 2004 Mar 31 Document order number: 9397 750 12427

NXP TDA3681 Multiple voltage regulator Data Sheet

INTEGRATED CIRCUITS

DATA SHEET

Multiple voltage regulator with switch and ignition buffer

Multiple voltage regulator with switch and ignition buffer

TDA3681

Philips Semiconductors – a worldwide company

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NXP TDA3681 Multiple voltage regulator Data Sheet

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DATA SHEET

Multiple voltage regulator with switch and ignition buffer

Multiple voltage regulator with switch and ignition buffer

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