NXP i.MX516 Applications Processors - Multimedia, High Performance, Low Power, Connectivity, Arm® Cortex®-A8 Core Data Sheet

Freescale Semiconductor

Data Sheet: Technical Data

Document Number: IMX51AEC

Rev. 6,

10/2012

IMX51A i.MX51A Automotive and

Infotainment Applications

Processors

Package Information

Plastic Package

Case 2017 19 x 19 mm, 0.8 mm pitch

Ordering Information

See Table 1 on page 2

for ordering information.

1 Introduction

The MCIMX51A (i.MX51A) Automotive Infotainment

Processor represents Freescale Semiconductor’s latest addition to a growing family of multimedia focused products offering high performance processing with a high degree of functional integration, aimed at the growing automotive infotainment market. This device includes two graphics processors, 720p video processing, dual display, and many I/Os.

The i.MX51A processor features Freescale’s advanced implementation of the ARM Cortex A8™ core, targeting speeds up to 600 MHz with 200 MHz I/O bus clock

DDR2 and mobile DDR. This device is well-suited for graphics rendering for HMI and navigation, high performance speech processing with large databases, video processing and display, audio playback and ripping, and many other applications.

1.

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1.

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 2

1.2.

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2.

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.1.

Special Signal Considerations . . . . . . . . . . . . . . . 11

3.

IOMUX Configuration for Boot Media . . . . . . . . . . . . . . . 13

3.1.

NAND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.2.

SD/MMC IOMUX Pin Configuration . . . . . . . . . . . 14

3.3.

I

2

C IOMUX Pin Configuration . . . . . . . . . . . . . . . . 14

3.4.

eCSPI/CSPI IOMUX Pin Configuration . . . . . . . . 15

3.5.

Wireless External Interface Module (WEIM) . . . . 15

3.6.

UART IOMUX Pin Configuration . . . . . . . . . . . . . 15

3.7.

USB-OTG IOMUX Pin Configuration . . . . . . . . . . 15

4.

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 16

4.1.

Chip-Level Conditions . . . . . . . . . . . . . . . . . . . . . 16

4.2.

Supply Power-Up/Power-Down Requirements and

Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.3.

I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 22

4.4.

Output Buffer Impedance Characteristics . . . . . . 29

4.5.

I/O AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 33

4.6.

Module Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

4.7.

External Peripheral Interfaces . . . . . . . . . . . . . . . 72

5.

Package Information and Contact Assignments . . . . . 151

5.1.

19 x 19 mm Package Information . . . . . . . . . . . . 151

5.2.

19 x 19 mm, 0.8 Pitch Ball Map . . . . . . . . . . . . . 169

6.

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

© 2012 Freescale Semiconductor, Inc. All rights reserved.

Introduction

Features of the i.MX51A processor include the following:

• Smart Speed Technology—The i.MX51A device has power management throughout the IC that enables the rich suite of multimedia feature and peripherals to achieve minimum power consumption in both active and various low power modes. Smart Speed Technology enables the designer to deliver a feature-rich product that requires levels of power that are far less than industry expectations.

• Multimedia—The multimedia performance of the ARM Cortex A8 is enhanced with a multi-level cache system, a Multi-standard Hardware Video CODECs, autonomous image processing unit, multi-standard audio CODECs, Neon (an advanced SIMD, 32 bit single-precision floating point support and vector floating point co-processor), and a programmable smart DMA controller.

• Powerful Graphics Acceleration—The i.MX51A processor has an integrated Graphics Processing

Unit which includes an OpenGl 2.0 GPU that provides 27Mtri/sec, 166Mpix/s, and 664Mpix/s z-plane performance. Silicon version 2.0 of the i.MX51A device includes an independent OpenVG

GPU operating at166Mpix/s.

• Interface Flexibility—The i.MX51A processor supports connections to all popular types of external memories: mobile DDR, DDR2, PSRAM, NOR Flash, NAND Flash (MLC and SLC), and

OneNAND (managed NAND). The i.MX51A processor also includes a rich multimedia suite of interfaces: LCD controller for two displays, CMOS sensor interface, High-Speed USB On-The-Go plus three High-Speed USB hosts, high-speed MMC/SDIO, Fast Ethernet controller, UART, I2C,

I2S (SSI), and others.

1.1

Ordering Information

Table 1

provides the ordering information.

Table 1. Ordering Information

Part Number

MCIMX514AJM6C

MCIMX516AJM6C

Mask Set Features

M77X No hardware video codecs

M77X Full specification

Junction

Temperature

Range (

°

C)

Package

1

–40 to 125 19 x 19 mm, 0.8 mm pitch BGA

Case 2017

–40 to 125 19 x 19 mm, 0.8 mm pitch BGA

Case 2017

1

Case 2017 and Case 2058 are RoHS compliant, lead-free, MSL = 3.

2 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

1.2

Block Diagram

Figure 1

shows the functional modules of the processor.

Digital

Audio

DDR

Memory

NOR/Nand

Flash

Battery Ctrl

Device

USB

Dev/Host

Camera 1

Camera 2

LCD Display 1

LCD Display 2

ATA HDD

External

Memory I/F

Smart DMA

(SDMA)

SPBA

SDMA Peripherals eSDHC (4)

UART

SPDIF Tx

FEC

SSI eCSPI (1 of 2)

SIM

P-ATA

Fuse Box

USB PHY

USB OTG +

3 HS Ports

Internal

RAM

(128 Kbytes)

Boot

ROM

Security

SAHARA

Lite

RTIC

SCC

SRTC

CSU

TZIC

Application Processor Domain (AP)

TV Encoder

Image Processing

Subsystem

ARM Cortex A8

Platform

ARM Cortex A8

Neon and VFP

L1 I/D cache

L2 cache

ETM, CTI0,1

Video

Proc. Unit

(VPU)

AP Peripherals eCSPI (2 )

CSPI

UART (3)

AUDMUX

I

2

C(2),HSI

2

C

1-WIRE

PWM (2)

IIM

IOMUXC

KPP

GPIOx32 (4)

SJC

SSI (3)

FIRI

3D Graphics

Proc Unit

(GPU)

Debug

DAP

TPIU

CTI (2)

Timers

WDOG (2)

GPT

EPIT (2)

Graphics

Memory

(128 Kbytes)

2D Graphics

Proc Unit

(GPU2D)

Clock and Reset

PLL (3)

CCM

GPC

SRC

XTALOSC

CAMP (2)

JTAG

IrDA

XVR

Bluetooth

WLAN

USB-OTG

XVR

MMC/SDIO Keypad

Access.

Conn.

Figure 1. Functional Block Diagram

Introduction

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

3

4

Features

2 Features

The i.MX51A processor contains a large number of digital and analog modules that are described in

Table 2 .

Table 2. i.MX51A Digital and Analog Modules

Block

Mnemonic

Block Name Subsystem Brief Description

1-WIRE

Audio

Subsystem

AUDMUX

CCM

GPC

SRC

CSPI-1, eCSPI-2 eCSPI-3

CSU

Debug

System

1-Wire

Interface

ARM

Cortex™-A8

ARM

Cortex™-A8

Platform

Audio

Subsystem

Digital Audio

Mux

Connectivity

Peripherals

ARM

Multimedia

Peripherals

Multimedia

Peripherals

1-Wire support provided for interfacing with an on-board EEPROM, and smart battery interfaces, for example: Dallas DS2502.

The ARM Cortex™-A8 Core Platform consists of the ARM Cortex™-A8 processor version r2p5 (with TrustZone) and its essential sub-blocks. It contains the Level 2 Cache Controller, 32 Kbyte L1 instruction cache, 32 Kbyte L1 data cache, and a 256 Kbyte L2 cache. The platform also contains an Event Monitor and Debug modules. It also has a NEON co-processor with SIMD media processing architecture, register file with 32

× 64-bit general-purpose registers, an Integer execute pipeline (ALU, Shift, MAC), dual, single-precision floating point execute pipeline (FADD, FMUL), load/store and permute pipeline and a

Non-Pipelined Vector Floating Point (VFP) co-processor (VFPv3).

The elements of the audio subsystem are three Synchronous Serial Interfaces

(SSI1-3), a Digital Audio Mux (AUDMUX), and Digital Audio Out (SPDIF TX).

See the specific interface listings in this table.

The AUDMUX is a programmable interconnect for voice, audio, and synchronous data routing between host serial interfaces (for example, SSI1,

SSI2, and SSI3) and peripheral serial interfaces (audio and voice codecs). The

AUDMUX has seven ports (three internal and four external) with identical functionality and programming models. A desired connectivity is achieved by configuring two or more AUDMUX ports.

Clock Control

Module

Global Power

Controller

System Reset

Controller

Clocks,

Resets, and

Power Control

These modules are responsible for clock and reset distribution in the system, and also for system power management. The modules include three PLLs and a Frequency Pre-Multiplier (FPM).

Configurable

SPI,

Enhanced

CSPI

Connectivity

Peripherals

Full-duplex enhanced Synchronous Serial Interface, with data rate up to

66.5 Mbit/s (for eCSPI, master mode). It is configurable to support Master/Slave modes, four chip selects to support multiple peripherals.

Central

Security Unit

Debug

System

Security

System

Control

The Central Security Unit (CSU) is responsible for setting comprehensive security policy within the i.MX51 platform, and for sharing security information between the various security modules. The Security Control Registers (SCR) of the CSU are set during boot time by the High Assurance Boot (HAB) code and are locked to prevent further writing.

The Debug System provides real-time trace debug capability of both instructions and data. It supports a trace protocol that is an integral part of the ARM Real

Time Debug solution (RealView). Real-time tracing is controlled by specifying a set of triggering and filtering resources, which include address and data comparators, cross-system triggers, counters, and sequencers. i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Features

Table 2. i.MX51A Digital and Analog Modules (continued)

Block

Mnemonic

EMI

EPIT-1

EPIT-2 eSDHC-1 eSDHC-2 eSDHC-3

Block Name Subsystem Brief Description

External

Memory

Interface

Enhanced

Periodic

Interrupt

Timer

Connectivity

Peripherals

Timer

Peripherals

Enhanced

Multi-Media

Card/

Secure Digital

Host

Controller

Connectivity

Peripherals

The EMI is an external and internal memory interface. It performs arbitration between multi-AXI masters to multi-memory controllers, divided into four major channels: fast memories (Mobile DDR, DDR2) channel, slow memories

(NOR-FLASH/PSRAM/NAND-FLASH and so on) channel, internal memory

(RAM, ROM) channel and graphical memory (GMEM) Channel.

In order to increase the bandwidth performance, the EMI separates the buffering and the arbitration between different channels so parallel accesses can occur.

By separating the channels, slow accesses do not interfere with fast accesses.

EMI features:

• 64-bit and 32-bit AXI ports

• Enhanced arbitration scheme for fast channel, including dynamic master priority, and taking into account which pages are open or closed and what type (Read or Write) was the last access

• Flexible bank interleaving

• Supports 16/32-bit Mobile DDR up to 200 MHz SDCLK (mDDR400)

• Supports 16/32-bit (Non-Mobile) DDR2 up to 200 MHz SDCLK (DDR2-400)

• Supports up to 2 Gbit Mobile DDR memories

• Supports 16-bit (in muxed mode only) PSRAM memories (sync and async operating modes), at slow frequency, for debugging purposes

• Supports 32-bit NOR-Flash memories (only in muxed mode), at slow frequencies for debugging purposes

• Supports 4/8-ECC, page sizes of 512 Bytes, 2 Kbytes and 4 Kbytes

• NAND-Flash (including MLC)

• Multiple chip selects

• Enhanced Mobile DDR memory controller, supporting access latency hiding

• Supports watermarking for security (Internal and external memories)

• Supports Samsung OneNAND ™ (only in muxed I/O mode)

Each EPIT is a 32-bit “set and forget” timer that starts counting after the EPIT is enabled by software. It is capable of providing precise interrupts at regular intervals with minimal processor intervention. It has a 12-bit prescaler for division of input clock frequency to get the required time setting for the interrupts to occur, and counter values can be programmed on the fly.

The features of the eSDHC module, when serving as host, include the following:

• Conforms to SD Host Controller Standard Specification version 2.0

• Compatible with the MMC System Specification version 4.2

• Compatible with the SD Memory Card Specification version 2.0

• Compatible with the SDIO Card Specification version 1.2

• Designed to work with SD Memory, miniSD Memory, SDIO, miniSDIO, SD

Combo, MMC and MMC RS cards

• Configurable to work in one of the following modes:

—SD/SDIO 1-bit, 4-bit

—MMC 1-bit, 4-bit, 8-bit

• Full-/high-speed mode

• Host clock frequency variable between 32 kHz to 52 MHz

• Up to 200 Mbps data transfer for SD/SDIO cards using four parallel data lines

• Up to 416 Mbps data transfer for MMC cards using eight parallel data lines

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

5

Features

Table 2. i.MX51A Digital and Analog Modules (continued)

Block

Mnemonic

Block Name Subsystem Brief Description eSDHC-4

(muxed with

P-ATA)

Enhanced

Multi-Media

Card/

Secure Digital

Host

Controller

Connectivity

Peripherals

FEC Fast Ethernet

Controller

Connectivity

Peripherals

FIRI

Can be configured as eSDHC (see above) and is muxed with the P-ATA interface.

Connectivity

Peripherals

The Ethernet Media Access Controller (MAC) is designed to support both

10 Mbps and 100 Mbps ethernet/IEEE Std 802.3™ networks. An external transceiver interface and transceiver function are required to complete the interface to the media.

Fast Infra-Red Interface

GPIO-1

GPIO-2

GPIO-3

GPIO-4

GPT

Fast

Infra-Red

Interface

General

Purpose I/O

Modules

General

Purpose

Timer

System

Control

Peripherals

Timer

Peripherals

These modules are used for general purpose input/output to external ICs. Each

GPIO module supports up to 32 bits of I/O.

GPU2D

I

I

GPU

2

2

C-1

C-2

HS-I

2

C

I

Graphics

Processing

Unit

Graphics

Processing

Unit-2D Ver. 1

2

C Interface

Multimedia

Peripherals

Multimedia

Peripherals

Connectivity

Peripherals

Each GPT is a 32-bit “free-running” or “set and forget” mode timer with a programmable prescaler and compare and capture register. A timer counter value can be captured using an external event, and can be configured to trigger a capture event on either the leading or trailing edges of an input pulse. When the timer is configured to operate in “set and forget” mode, it is capable of providing precise interrupts at regular intervals with minimal processor intervention. The counter has output compare logic to provide the status and interrupt at comparison. This timer can be configured to run either on an external clock or on an internal clock.

The GPU provides hardware acceleration for 2D and 3D graphics algorithms with sufficient processor power to run desk-top quality interactive graphics applications on displays up to HD720 resolution. It supports color representation up to 32 bits per pixel.

The GPU with its 128 KByte memory enables high performance mobile 3D and

2D vector graphics at rates up to 27 Mtriangles/sec, 166 Mpixels/sec,

664 Mpixels/sec (Z).

The GPU2D provides hardware acceleration for 2D graphic algorithms with sufficient processor power to run desk-top quality interactive graphics applications on displays up to HD720 resolution.

I

2

C provides serial interface for controlling peripheral devices. Data rates of up to 400 Kbps are supported by two of the I

(I

2

2

C ports. Data rates of up to 3.4 Mbps

C Specification v2.1) are supported by the HS-I

2

C.

Note: See the errata for the HS-I

2

C in the i.MX51 Chip Errata. The two standard

I

2

C modules have no errata.

6 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Features

Table 2. i.MX51A Digital and Analog Modules (continued)

Block

Mnemonic

IIM

Block Name Subsystem

IC

Identification

Module

Security

IOMUXC

IPU

IOMUX

Control

Image

Processing

Unit

System

Control

Peripherals

Multimedia

Peripherals

Brief Description

The IC Identification Module (IIM) provides an interface for reading, programming, and/or overriding identification and control information stored in on-chip fuse elements. The module supports electrically programmable poly fuses (e-Fuses). The IIM also provides a set of volatile software-accessible signals that can be used for software control of hardware elements not requiring non-volatility. The IIM provides the primary user-visible mechanism for interfacing with on-chip fuse elements. Among the uses for the fuses are unique chip identifiers, mask revision numbers, cryptographic keys, JTAG secure mode, boot characteristics, and various control signals requiring permanent non-volatility. The IIM also provides up to 28 volatile control signals. The IIM consists of a master controller, a software fuse value shadow cache, and a set of registers to hold the values of signals visible outside the module.

This module enables flexible I/O multiplexing. Each I/O pad has default as well as several alternate functions. The alternate functions are software configurable.

IPU enables connectivity to displays and image sensors, relevant processing and synchronization. It supports two display ports and two camera ports, through the following interfaces.

• Legacy Interfaces

• Analog TV interfaces (through a TV encoder bridge)

KPP

P-ATA (Muxed with eSDHC-4

Parallel ATA Connectivity

Peripherals

PWM-1

PWM-2

Keypad Port Connectivity

Peripherals

Pulse Width

Modulation

Connectivity

Peripherals

The processing includes:

• Support for camera control

• Image enhancement: color adjustment and gamut mapping, gamma correction and contrast enhancement, sharpening and noise reduction

• Video/graphics combining

• Support for display backlight reduction

• Image conversion—resizing, rotation, inversion and color space conversion

• Synchronization and control capabilities, allowing autonomous operation.

• Hardware de-interlacing support

The KPP supports an 8

× 8 external keypad matrix. The KPP features are as follows:

• Open drain design

• Glitch suppression circuit design

• Multiple keys detection

• Standby key press detection

The P-ATA block is an AT attachment host interface. Its main use is to interface with hard disc drives and optical disc drives. It interfaces with the ATA-5

(UDMA-4) compliant device over a number of ATA signals. It is possible to connect a bus buffer between the host side and the device side. This is muxed with eSDHC-4 interfaces.

The pulse-width modulator (PWM) has a 16-bit counter and is optimized to generate sound from stored sample audio images. It can also generate tones.

The PWM uses 16-bit resolution and a 4 x 16 data FIFO to generate sound.

Unified RAM, can be split between Secure RAM and Non-Secure RAM RAM

128 Kbytes

ROM

36 Kbytes

Internal RAM Internal

Memory

Boot ROM Internal

Memory

Supports secure and regular Boot Modes

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

7

Features

Table 2. i.MX51A Digital and Analog Modules (continued)

Block

Mnemonic

Block Name Subsystem Brief Description

RTIC

SAHARA Lite SAHARA

SCC

SDMA

SIM

Real Time

Integrity

Checker security accelerator

Lite

Security

Controller

Smart Direct

Memory

Access

Subscriber

Identity

Module

Interface

Security

Security

Security

System

Control

Peripherals

Connectivity

Peripherals

Protecting read-only data from modification is one of the basic elements in trusted platforms. The Run-Time Integrity Checker v3 (RTICv3) module, is a data monitoring device responsible for ensuring that memory content is not corrupted during program execution. The RTICv3 mechanism periodically checks the integrity of code or data sections during normal OS run-time execution without interfering with normal operation. The RTICv3’s purpose is to ensure the integrity of the peripheral memory contents, protect against unauthorized external memory elements replacement, and assist with boot authentication.

SAHARA (Symmetric/Asymmetric Hashing and Random Accelerator) is a security co-processor. It implements symmetric encryption algorithms, (AES,

DES, 3DES, and RC4), public key algorithms, hashing algorithms (MD5, SHA-1,

SHA-224, and SHA-256), and a hardware random number generator. It has a slave IP bus interface for the host to write configuration and command information, and to read status information. It also has a DMA controller, with an

AHB bus interface, to reduce the burden on the host to move the required data to and from memory.

The Security Controller is a security assurance hardware module designed to safely hold sensitive data such as encryption keys, digital right management

(DRM) keys, passwords, and biometrics reference data. The SCC monitors the system’s alert signal to determine if the data paths to and from it are secure—that is, cannot be accessed from outside of the defined security perimeter. If not, it erases all sensitive data on its internal RAM. The SCC also features a Key Encryption Module (KEM) that allows non-volatile (external memory) storage of any sensitive data that is temporarily not in use. The KEM utilizes a device-specific hidden secret key and a symmetric cryptographic algorithm to transform the sensitive data into encrypted data.

The SDMA is multi-channel flexible DMA engine. It helps in maximizing system performance by off loading various cores in dynamic data routing.

The SDMA features list is as follows:

• Powered by a 16-bit instruction-set micro-RISC engine

• Multi-channel DMA supports up to 32 time-division multiplexed DMA channels

• 48 events with total flexibility to trigger any combination of channels

• Memory accesses including linear, FIFO, and 2D addressing

• Shared peripherals between ARM Cortex™-A8 and SDMA

• Very fast context-switching with two-level priority-based preemptive multi-tasking

• DMA units with auto-flush and prefetch capability

• Flexible address management for DMA transfers (increment, decrement, and no address changes on source and destination address)

• DMA ports can handle unit-directional and bi-directional flows (copy mode)

• Up to 8-word buffer for configurable burst transfers for EMI

• Support of byte-swapping and CRC calculations

• A library of scripts and API are available

The SIM is an asynchronous interface with additional features for allowing communication with Smart Cards conforming to the ISO 7816 specification. The

SIM is designed to facilitate communication to SIM cards or pre-paid phone cards.

8 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Features

Table 2. i.MX51A Digital and Analog Modules (continued)

Block

Mnemonic

SJC

Block Name Subsystem

Secure JTAG

Interface

System

Control

Peripherals

Brief Description

JTAG manipulation is a known hacker’s method of executing unauthorized program code, getting control over secure applications, and running code in privileged modes. The JTAG port provides a debug access to several hardware blocks including the ARM processor and the system bus.

SPBA

SPDIF

SRTC

SSI-1

SSI-2

SSI-3

TVE

The JTAG port must be accessible during platform initial laboratory bring-up, manufacturing tests and troubleshooting, as well as for software debugging by authorized entities. However, in order to properly secure the system, unauthorized JTAG usage should be strictly forbidden.

In order to prevent JTAG manipulation while allowing access for manufacturing tests and software debugging, the i.MX51A processor incorporates a mechanism for regulating JTAG access. The i.MX51A Secure JTAG Controller provides four different JTAG security modes that can be selected via e-fuse configuration.

SPBA (Shared Peripheral Bus Arbiter) is a two-to-one IP bus interface (IP bus) arbiter.

Shared

Peripheral

Bus Arbiter

Sony Philips

Digital

Interface

System

Control

Peripherals

Multimedia

Peripherals

Secure Real

Time Clock

Security

A standard digital audio transmission protocol developed jointly by the Sony and

Philips corporations. Only the transmitter functionality is supported.

I2S/SSI/AC97

Interface

Connectivity

Peripherals

TV Encoder Multimedia

The SRTC incorporates a special System State Retention Register (SSRR) that stores system parameters during system shutdown modes. This register and all

SRTC counters are powered by dedicated supply rail NVCC_SRTC_POW. The

NVCC_SRTC_POW can be energized even if all other supply rails are shut down. The power for this block comes from NVCC_SRTC_POW supply. When this supply is driven by the MC13892 power management controller, this block can be power backed up via the coin-cell feature of the MC13892.This register is helpful for storing warm boot parameters. The SSRR also stores the system security state. In case of a security violation, the SSRR mark the event (security violation indication).

The SSI is a full-duplex synchronous interface used on the i.MX51A processor to provide connectivity with off-chip audio peripherals. The SSI interfaces connect internally to the AUDMUX which interfaces to the i.MX51 system memory. The SSI supports a wide variety of protocols (SSI normal, SSI network,

I2S, and AC-97), bit depths (up to 24 bits per word), and clock/frame sync options.

Each SSI has two pairs of 8x24 FIFOs and hardware support for an external

DMA controller in order to minimize its impact on system performance. The second pair of FIFOs provides hardware interleaving of a second audio stream, which reduces CPU overhead in use cases where two timeslots are being used simultaneously.

The TVE is implemented in conjunction with the Image Processing Unit (IPU) allowing handheld devices to display captured still images and video directly on a TV or LCD projector. It supports the following analog video outputs: composite, S-video, and component video up to HD720p/1080i.

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

9

Features

Table 2. i.MX51A Digital and Analog Modules (continued)

Block

Mnemonic

Block Name Subsystem Brief Description

TZIC

UART-1

UART-2

UART-3

USB

VPU

WDOG-1

TrustZone

Aware

Interrupt

Controller

UART

Interface

USB 2.0

High-Speed

OTG and 3x

Hosts

Video

Processing

Unit

ARM/Control The TrustZone Interrupt Controller (TZIC) collects interrupt requests from all i.MX51 sources and routes them to the ARM core. Each interrupt can be configured as a normal or a secure interrupt. Software Force Registers and software Priority Masking are also supported.

Connectivity

Peripherals

Each of the UART modules supports the following serial data transmit/receive protocols and configurations:

• 7 or 8 bit data words, 1 or 2 stop bits, programmable parity (even, odd, or none)

• Programmable baud rates up to 4 MHz. This is a higher max baud rate relative to the 1.875 MHz, which is stated by the TIA/EIA-232-F standard and previous Freescale UART modules.

• 32-byte FIFO on Tx and 32 half-word FIFO on Rx supporting auto-baud

• IrDA 1.0 support (up to SIR speed of 115200 bps)

• Option to operate as 8-pins full UART, DCE, or DTE

Connectivity

Peripherals

Multimedia

Peripherals

USB-OTG contains one high-speed OTG module, which is internally connected to the on-chip HS USB PHY. There are an additional three high-speed host modules that require external USB PHYs.

Watch Dog Timer

Peripherals

A high-performing video processing unit (VPU), which covers many SD-level video decoders and SD-level encoders as a multi-standard video codec engine as well as several important video processing such as rotation and mirroring.

VPU Features:

• MPEG-4 decode: 720p, 30 fps, simple profile and advanced simple profile

• MPEG-4 encode: D1, 25/30 fps, simple profile

• H.263 decode: 720p, 30 fps, profile 3

• H.263 encode: D1, 25/30 fps, profile 3

• H.264 decode: 720p, 30 fps, baseline, main, and high profile

• H.264 encode: D1, 25/30 fps, baseline profile

• MPEG-2 decode: 720p, 30 fps, MP-ML

• MPEG-2 encode: D1, 25/30 fps, MP-ML (in software with partial acceleration in hardware)

• VC-1 decode: 720p, 30 fps, simple, main, and advanced profile

• DivX decode: 720p, 30 fps versions 3, 4, and 5

• RV10 decode: 720p, 30 fps

• MJPEG decode: 32 Mpix/s

• MJPEG encode: 64 Mpix/s

The Watch Dog Timer supports two comparison points during each counting period. Each of the comparison points is configurable to evoke an interrupt to the

ARM core, and a second point evokes an external event on the WDOG line.

10 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Features

Table 2. i.MX51A Digital and Analog Modules (continued)

Block

Mnemonic

WDOG-2

(TZ)

Block Name

Watch Dog

(TrustZone)

Subsystem

Timer

Peripherals

XTALOSC Crystal

Oscillator I/F

Clocking

Brief Description

The TrustZone Watchdog (TZ WDOG) timer module protects against TrustZone starvation by providing a method of escaping normal mode and forcing a switch to the TZ mode. TZ starvation is a situation where the normal OS prevents switching to the TZ mode. This situation should be avoided, as it can compromise the system’s security. Once the TZ WDOG module is activated, it must be serviced by TZ software on a periodic basis. If servicing does not take place, the timer times out. Upon a time-out, the TZ WDOG asserts a TZ mapped interrupt that forces switching to the TZ mode. If it is still not served, the TZ

WDOG asserts a security violation signal to the CSU. The TZ WDOG module cannot be programmed or deactivated by a normal mode SW.

The XTALOSC module allows connectivity to an external crystal.

2.1

Special Signal Considerations

Table 3 lists special signal considerations for the i.MX51. The signal names are listed in alphabetical order.

The package contact assignments are found in

Section 5, “Package Information and Contact

Assignments.”

Signal descriptions are defined in the i.MX51 Multimedia Applications Processor

Reference Manual (MCIMX51RM).

Table 3. Special Signal Considerations

Signal Name

CKIH1, CKIH2

CLK_SS

COMP

FASTR_ANA and

FASTR_DIG

GPANAIO

Remarks

Inputs feeding CAMPs (Clock Amplifiers) that have on-chip ac coupling precluding the need for external coupling capacitors. The CAMPs are enabled by default, but the main clocks feeding the on-chip clock tree are sourced from XTAL/EXTAL by default. Optionally, the use of a low jitter external oscillators to feed CKIH1 or CKIH2 (while not required) can be an advantage if low jitter or special frequency clock sources are required by modules driven by CKIH1 or CKIH2. See CCM chapter in the i.MX51 Multimedia Applications Processor Reference Manual (MCIMX51RM) for details on the respective clock trees.

After initialization, the CAMPs could be disabled (if not used) by CCM registers (CCR CAMPx_EN field). If disabled, the on-chip CAMP output is low; the input is irrelevant. If unused, the user should tie CKIH1/CKIH2 to GND for best practice.

Clock Source Select is the input that selects the default reference clock source providing input to the DPLLs. To use a reference in the megahertz range per Table 8, tie CLK_SS to GND to select

EXTAL/XTAL. To use a reference in the kilohertz range per Table 59, tie CLK_SS to NVCC_PER3 to select CKIL. After initialization, the reference clock source can be changed (initial setting is overwritten).

Note: Because this input has a keeper circuit, Freescale recommends tying this input to directly to GND or NVCC_PER3. If a series resistor is used its value must be

≤

4.7 k

Ω.

The user should bypass this reference with an external 0.1 µ F capacitor tied to GND. If TV OUT is not used, float the COMP contact and ensure the DACs are powered down.

Note: Previous engineering samples required this reference to be bypassed to a positive supply.

These signals are reserved for Freescale manufacturing use only. User must tie both connections to GND.

This signal is reserved for Freescale manufacturing use only. Users should float this output.

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

11

Features

Table 3. Special Signal Considerations (continued)

Signal Name

GPIO_NAND

IOB, IOG, IOR,

IOB_BACK, IOG_BACK, and IOR_BACK

JTAG_ nnnn

NC

PMIC_INT_REQ

POR_B

RESET_IN_B

RREFEXT

SGND, SVCC, and

SVDDGP

STR

TEST_MODE

Remarks

This is a general-purpose input/output (GPIO3_12) on the NVCC_NANDF_A power rail.

These signals are analog TV outputs that should be tied to GND when not being used.

The JTAG interface is summarized in

Table 4 . Use of external resistors is unnecessary. However,

if external resistors are used, the user must ensure that the on-chip pull-up/down configuration is followed. For example, do not use an external pull down on an input that has on-chip pull-up.

JTAG_TDO is configured with a keeper circuit such that the floating condition is eliminated if an external pull resistor is not present. An external pull resistor on JTAG_TDO is detrimental and should be avoided.

JTAG_MOD is referenced as SJC_MOD in the i.MX51 Multimedia Applications Processor

Reference Manual (MCIMX51RM). Both names refer to the same signal. JTAG_MOD must be externally connected to GND for normal operation. Termination to GND through an external pull-down resistor (such as 1 k

Ω) is allowed.

These signals are No Connect (NC) and should be floated by the user.

When using the MC13892 power management IC, the PMIC_INT_REQ high-priority interrupt input on i.MX51 should be either floated or tied to NVCC_SRTC_POW with a 4.7 k

Ω to 68 kΩ resistor.

This avoids a continuous current drain on the real-time clock backup battery due to a 100 k

Ω on-chip pull-up resistor.

PMIC_INT_REQ is not used by the Freescale BSP (board support package) software. The BSP requires that the general-purpose INT output from the MC13892 be connected to the i.MX51 GPIO input GPIO1_8 configured to cause an interrupt that is not high-priority.

The original intent was for PMIC_INT_REQ to be connected to a circuit that detects when the battery is almost depleted. In this case, the I/O must be configured as alternate mode 0 (ALT0 = power fail).

This cold reset negative logic input resets all modules and logic in the IC.

Note: The POR_B input must be immediately asserted at power-up and remain asserted until after the last power rail is at its working voltage.

This warm reset negative logic input resets all modules and logic except for the following:

• Test logic (JTAG, IOMUXC, DAP)

• SRTC

• Memory repair – Configuration of memory repair per fuse settings

• Cold reset logic of WDOG – Some WDOG logic is only reset by POR_B. See WDOG chapter in i.MX51 Multimedia Applications Processor Reference Manual (MCIMX51RM) for details.

Determines the reference current for the USB PHY bandgap reference. An external 6.04 k

Ω 1% resistor to GND is required.

These sense lines provide the ability to sense actual on-chip voltage levels on their respective supplies. SGND monitors differentials of the on-chip ground versus an external power source.

SVCC monitors on-chip VCC, and SVDDGP monitors VDDGP. Freescale recommends connection of the SVCC and SVDDGP signals to the feedback inputs of switching power-supplies or to test points.

This signal is reserved for Freescale manufacturing use. The user should float this signal.

TEST_MODE is for Freescale factory use only. This signal is internally connected to an on-chip pull-down device. Users must either float this signal or tie it to GND.

12 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

VREF

Signal Name

VREFOUT

VREG

XTAL/EXTAL

JTAG

JTAG_TCK

JTAG_TMS

JTAG_TDI

JTAG_TDO

JTAG_TRSTB

JTAG_DE_B

JTAG_MOD

IOMUX Configuration for Boot Media

Table 3. Special Signal Considerations (continued)

Remarks

When using VREF with DDR-2 I/O, the nominal 0.9 V reference voltage must be half of the

NVCC_EMI_DRAM supply. The user must tie VREF to a precision external resistor divider. Use a

1 k

Ω 0.5% resistor to GND and a 1 kΩ 0.5% resistor to NVCC_EMI_DRAM. Shunt each resistor with a closely-mounted 0.1 µF capacitor.

To reduce supply current, a pair of 1.5 k

Ω 0.1% resistors can be used. Using resistors with recommended tolerances ensures the ± 2% VREF tolerance (per the DDR-2 specification) is maintained when four DDR-2 ICs plus the i.MX51 are drawing current on the resistor divider.

Note: When VREF is used with mDDR this signal must be tied to GND.

This signal determines the Triple Video DAC (TVDAC) reference voltage. The user must tie

VREFOUT to an external 1.05 k

Ω 1% resistor to GND.

This regulator is no longer used and should be floated by the user.

The user should tie a fundamental-mode crystal across XTAL and EXTAL. The crystal must be rated for a maximum drive level of 100

μ

W or higher. An ESR (equivalent series resistance) of

80

Ω or less is recommended. Freescale BSP (Board Support Package) software requires 24 MHz on EXTAL.

The crystal can be eliminated if an external 24 MHz oscillator is available. In this case, EXTAL must be directly driven by the external oscillator and XTAL is floated. The EXTAL signal level must swing from NVCC_OSC to GND. If the clock is used for USB, then there are strict jitter requirements: < 50 ps peak-to-peak below 1.2 MHz and < 100 ps peak-to-peak above 1.2 MHz for the USB PHY. The

COSC_EN bit in the CCM (Clock Control Module) must be cleared to put the on-chip oscillator circuit in bypass mode which allows EXTAL to be externally driven. COSC_EN is bit 12 in the CCR register of the CCM.

Table 4. JTAG Controller Interface Summary

I/O Type

Input

Input

Input

3-state output

Input

Input/open-drain output

Input

On-Chip Termination

100 k

Ω pull-down

47 k

Ω pull-up

47 k

Ω pull-up

Keeper

47 k

Ω pull-up

47 k

Ω pull-up

100 k

Ω pull-up

3 IOMUX Configuration for Boot Media

The information provided in this section describes the contacts assigned for each type of bootable media.

It also includes data about the clocks used during boot flow and their frequencies. Signals that can be multiplexed appear in tables throughout this section. See the IOMUXC chapter in the i.MX51 Multimedia

Applications Processor Reference Manual (MCIMX51RM) for details about how to program the IOMUX controller.

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

13

IOMUX Configuration for Boot Media

3.1

NAND

The NAND Flash Controller (NFC) signals are not configured in the IOMUX. The NFC interface uses dedicated contacts on the IC.

3.2

SD/MMC IOMUX Pin Configuration

Table 5

shows the SD/MMC IOMUX pin configuration.

Table 5. SD/MMC IOMUX Pin Configuration

Signal eSDHC1

SD1_CLK.alt0

eSDHC2

SD2_CLK.alt0

CLK

CMD

SD1_CMD.alt0

SD2_CMD.alt0

DAT0

SD1_DATA0.alt0

N/A

1

SD2_DATA0.alt0

DAT1

N/A

DAT2

N/A N/A

CD/DAT3

SD1_DATA3.alt0

SD2_DATA3.alt0

DAT4

N/A N/A

DAT5

N/A N/A

DAT6

N/A N/A

DAT7

N/A

1

N/A in the ROM code indicates the pins are not available.

N/A eSDHC3 eSDHC4

NANDF_RDY_INT.alt5

NANDF_CS2.alt5

NANDF_CS7.alt5

NANDF_WE_B.alt2

N/A

N/A

NANDF_RB0.alt5

N/A

N/A

N/A

N/A

NANDF_RB1.alt5

NANDF_CS3.alt5

N/A

N/A

NANDF_CS6.alt5

N/A

N/A

N/A

N/A

Only DAT0 is available when the SD/MMC is used for boot. The remaining lines (DAT1–DAT7) are not available.

3.3

I

2

C IOMUX Pin Configuration

The contacts assigned to the signals used by the three I

2

C modules is shown in

Table 6 .

Table 6. I

2

C IOMUX Pin Configuration

Signal

SDA

SCL

HSI

2

C

I2C1_DAT.alt0

I2C1_CLK.alt0

I

2

C1

I2C1_DAT.alt0

I2C1_CLK.alt0

I

2

C2

GPIO1_3.alt2

GPIO1_2.alt2

14 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

IOMUX Configuration for Boot Media

3.4

eCSPI/CSPI IOMUX Pin Configuration

The contacts assigned to the signals used by the three SPI modules is shown in

Table 7 .

Table 7. SPI IOMUX Pin Configuration

Signal eCSPI1 eCSPI2

MISO

MOSI

CSPI1_MISO.alt0

CSPI1_MOSI.alt0

RDY

SCLK

SS0

SS1

SS2

CSPI1_RDY.alt0

CSPI1_SCLK.alt0

N/A

N/A

N/A

1

SS3 N/A

1

N/A in the ROM code indicates the pins are not available.

NANDF_RB3.alt2

NANDF_D15.alt2

NANDF_RB1.alt2

NANDF_RB2.alt2

N/A

N/A

N/A

N/A

CSPI

USBH1_NXT.alt1

USBH1_DIR.alt1

USBH1_STP.alt1

USBH1_CLK.alt1

N/A

USBH1_DATA5.alt1

N/A

N/A

3.5

Wireless External Interface Module (WEIM)

The WEIM interface signals are not configured in the IOMUX. The WEIM interface uses dedicated contacts on the IC.

3.6

UART IOMUX Pin Configuration

The contacts assigned to the signals used by the three UART modules are shown in

Table 8

.

Table 8. UART IOMUX Pin Configuration

Signal

TXD

RXD

CTS

RTS

UART1

UART1_TXD.alt0

UART1_RXD.alt0

UART1_CTS.alt0

UART1_RTS.alt0

UART2

UART2_TXD.alt0

UART2_RXD.alt0

USBH1_DATA0.alt1

USBH1_DATA3.alt1

UART3

UART3_TXD.alt1

UART3_RXD.alt1

KEY_COL5.alt2

KEY_COL4.alt2

3.7

USB-OTG IOMUX Pin Configuration

The interface signals of the UTMI PHY are not configured in the IOMUX. The UTMI PHY interface uses dedicated contacts on the IC.

Table 9. ULPI PHY IOMUX Pin Configuration

Signal

USB_PWR

USB_OC

ULPI PHY

GPIO1_8.alt1

GPIO1_9.alt1

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

15

Electrical Characteristics

Table 9. ULPI PHY IOMUX Pin Configuration (continued)

Signal

USBOTG_CLK

USBOTG_NXT

USBOTG_STP

USBOTG_DAT0

USBOTG_DAT1

USBOTG_DAT2

USBOTG_DAT3

USBOTG_DAT4

USBOTG_DAT5

USBOTG_DAT6

USBOTG_DAT7

ULPI PHY

EIM_CS4.alt2

EIM_CS3.alt2

EIM_CS2.alt2

EIM_D24.alt2

EIM_D25.alt2

EIM_D26.alt2

EIM_D27.alt2

EIM_D28.alt2

EIM_D29.alt2

EIM_D30.alt2

EIM_D31.alt2

NOTE

USB OTG ULPI port is not supported and it is not functional. On-chip PHY is always used for the OTG port.

4 Electrical Characteristics

This section provides the device and module-level electrical characteristics for the i.MX51A processor.

4.1

Chip-Level Conditions

This section provides the device-level electrical characteristics for the IC. See Table 10 for a quick

reference to the individual tables and sections.

Table 10. i.MX51A Chip-Level Conditions

For these characteristics, …

Table 11, “Absolute Maximum Ratings”

Table 12

, “

Thermal Resistance Data ”

Table 13

, “

i.MX51A Operating Ranges

”

Table 14

, “

Interface Frequency

”

Topic appears …

on page 17 on page 17

on page 18

on page 19

CAUTION

Stresses beyond those listed under

Table 11

may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under

Table 13

is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

16 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Electrical Characteristics

Table 11. Absolute Maximum Ratings

Parameter Description Symbol Min Max Unit

Peripheral Core Supply Voltage

ARM Core Supply Voltage

Supply Voltage (UHVIO, I

2

C)

Supply Voltage (except UHVIO, I

2

C)

VCC

VDDGP

Supplies denoted as I/O Supply

Supplies denoted as I/O Supply

–0.3

–0.3

–0.5

–0.5

1.35

1.15

3.6

3.3

V

V

V

V

USB VBUS

Input/Output Voltage Range

ESD Damage Immunity:

VBUS

V in

/V out

V esd

—

–0.5

5.25

OVDD + 0.3

1

V

V

V

Human Body Model (HBM)

Charge Device Model (CDM)

—

—

2000

500

Storage Temperature Range T

STORAGE

–40 125 o

C

Junction Temperature T

J

— 125

2

1

2

The term OVDD in this section refers to the associated supply rail of an input or output. The association is described in

Table 128

. The maximum range can be superseded by the DC tables.

During the life of the device, T

J must be limited to a cumulative of 2% of the time over 105 o

C.

o

C

Table 12 provides the thermal resistance data.

Table 12. Thermal Resistance Data

Rating Board Symbol Value Unit

1

Junction to Case

1

, 19 x 19 mm package — R

θJC

6 °C/W

Rjc-x per JEDEC 51-12: The junction-to-case thermal resistance. The “x” indicates the case surface where T case

is measured and through which 100% of the junction power is forced to flow due to the cold plate heat sink fixture placed either at the top (T) or bottom (B) of the package, with no board attached to the package.

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

17

Electrical Characteristics

Table 13

shows the i.MX51 operating ranges.

Table 13. i.MX51A Operating Ranges

Symbol Parameter Minimum

1

Nominal

2

Maximum

1

VDDGP

MCIMX51xA products

VCC

MCIMX51xA products

VDDA

ARM core supply voltage

0

< f

ARM

≤

600 MHz

ARM core supply voltage

Stop mode

Peripheral supply voltage High Performance

Mode (HPM) The clock frequencies are derived from AXI and AHB buses using 133 or 166 MHz

(as needed). The DDR clock rate is 200 MHz.

Note: For detailed information about the use of

133 or 166 MHz clocks, see i.MX51 Multimedia

Applications Processor Reference Manual

(MCIMX51RM).

Peripheral supply voltage—Stop mode

Memory arrays voltage—Run Mode

Memory arrays voltage—Stop Mode

PLL Digital supplies

0.95

0.9

1.0

0.95

1.175 1.225

0.9

1.15

0.9

1.15

0.95

1.20

0.95

1.2

1.1

1.05

1.275

1.275

1.275

1.275

1.35

VDD_DIG_PLL_A

VDD_DIG_PLL_B

VDD_ANA_PLL_A

VDD_ANA_PLL_B

NVCC_EMI

NVCC_PER5

NVCC_PER10

NVCC_PER11

NVCC_PER12

NVCC_PER13

NVCC_PER14

NVCC_IPUx

3

NVCC_PER3

NVCC_PER8

NVCC_PER9

NVCC_EMI_DRAM

VDD_FUSE

4

NVCC_NANDF_x

5

NVCC_PER15

NVCC_PER17

NVCC_USBPHY

NVCC_OSC

TVDAC_DHVDD,

NVCC_TV_BACK,

AHVDDRGB

PLL Analog supplies

GPIO EMI Supply and additional digital power supplies.

GPIO IPU Supply and additional digital power supplies.

DDR and Fuse Read Supply

Fusebox Program Supply (Write Only)

Ultra High voltage I/O (UHVIO) supplies

UHVIO_L

UHVIO_H

UHVIO_UH

USB_PHY analog supply, oscillator analog supply

6

TVE-to-DAC level shifter supply, cable detector supply, analog power supply to RGB channel

1.75

1.65

1.65

1.65

3.0

1.65

2.5

3.0

2.25

2.69

1.8

1.875 or

2.775

1.875 or

2.775

1.8

—

—

1.875

2.775

3.3

2.5

2.75

1.95

3.1

3.1

1.95

3.3

1.95

3.1

3.6

2.75

2.91

Unit

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

18 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Electrical Characteristics

Table 13. i.MX51A Operating Ranges (continued)

Parameter Minimum

1

Nominal

2

Maximum

1

Symbol Unit

NVCC_HS4_1

NVCC_HS4_2

NVCC_HS6

NVCC_HS10

NVCC_I2C

HS-GPIO additional digital power supplies 1.65

— 3.1

V

I

2

C and HS-I

2

C I/O Supply

7

1.65

2.7

1.875

3.0

1.95

3.3

V

NVCC_SRTC_

POW

VDDA33

SRTC Core and I/O Supply (LVIO) 1.1

1.2

1.3

V

USB PHY I/O analog supply 3.0

3.3

3.6

V

VBUS

See Table 11 and

Table 126 for details. This is

not a power supply.

— — — —

1

2

3

4

5

6

7

Voltage at the package power supply contact must be maintained between the minimum and maximum voltages. The design must allow for supply tolerances and system voltage drops.

The nominal values for the supplies indicate the target setpoint for a tolerance no tighter than ± 50 mV. Use of supplies with a tighter tolerance allows reduction of the setpoint with commensurate power savings.

The NVCC_IPUx rails are isolated from one another. This allows the connection of different supply voltages for each one. For example, NVCC_IPU2 can operate at 1.8 V while NVCC_IPU4 operates at 3.0 V.

In Read mode, Freescale recommends VDD_FUSE be floated or grounded. Tying VDD_FUSE to a positive supply

(3.0 V–3.3 V) increases the possibility of inadvertently blowing fuses and is not recommended.

The NAND Flash supplies are composed of three groups: A, B, and C. Each group can be powered with a different supply voltage. For example, NVCC_NANDF_A = 1.8 V, NVCC_NANDF_B = 3.0 V, NVCC_NANDF_C = 2.7 V.

The analog supplies should be isolated in the application design. Use of series inductors is recommended.

Operation of the HS-I

2

C and I

2

C is not guaranteed when operated between the supply voltages of 1.95 to 2.7 V.

Parameter Description

JTAG: TCK Operating Frequency

CKIL: Operating Frequency

CKIH: Operating Frequency

XTAL Oscillator

Table 14. Interface Frequency

Symbol f tck f ckil f ckih f xtal

Min Max

See Table 99, "JTAG Timing," on page 130

See Table 74, "FPM Specifications," on page 80

See Table 47, "CAMP Electrical Parameters (CKIH1,

CKIH2)," on page 46

22 27

Unit

MHz kHz

MHz

MHz

4.1.1

Supply Current

Table 15 shows the fuse supply current.

Table 15. Fuse Supply Current

1

Description eFuse Program Current.

2

Current required to program one eFuse bit: The associated

VDD_FUSE supply per Table 13

.

Symbol

I program

Min

—

Typ

60

Max

120

Unit mA

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

19

Electrical Characteristics

1

2

The read current of approximately 5 mA is derived from the DDR supply (NVCC_EMI_DRAM).

The current I program

is only required during program time.

Table 16 shows the current core consumption (not including I/O) of the i.MX51.

Table 16. i.MX51 Stop Mode Current and Power Consumption

Mode

Stop Mode

• External reference clocks gated

• Power gating for ARM and processing units

• Stop mode voltage

Stop Mode

• External reference clocks gated

• Power gating for ARM and processing units

• HPM voltage

Stop Mode

• External reference clocks enabled

• Power gating for ARM and processing units

• HPM voltage

Condition

VDDGP = 0.95 V, VCC = 0.95 V, VDDA = 0.95 V

ARM CORE in SRPG mode

L1 and L2 caches power gated

IPU in S&RPG mode

VPU and GPU in PG mode

All PLLs off, all CCM-generated clocks off

CKIL input on with 32 kHz signal present

All modules disabled

USBPHY PLL off

External (MHz) crystal and on-chip oscillator powered down (SBYOS bit asserted)

No external resistive loads that cause current flow

Standby voltage allowed (VSTBY bit is asserted)

T A = 25

°C

VDDGP = 1.0 V, VCC = 1.225 V, VDDA = 1.2 V

ARM CORE in SRPG mode

L1 and L2 caches power gated

IPU in S&RPG mode

VPU and GPU in PG mode

All PLLs off, all CCM-generated clocks off

CKIL input on with 32 kHz signal present

All modules disabled.

USBPHY PLL off

External (MHz) crystal and on-chip oscillator powered down (SBYOS bit asserted)

No external resistive loads that cause current flow

T A = 25

°C

VDDGP = 1.0 V, VCC = 1.225 V, VDDA = 1.20 V

ARM CORE in SRPG mode

L1 and L2 caches power gated

IPU in S&RPG mode

VPU and GPU in PG mode

All PLLs off, all CCM-generated clocks off

CKIL input on with 32 kHz signal present

All modules disabled

USBPHY PLL off

External (MHz) crystal and on-chip oscillator powered and generating reference clock

No external resistive loads that cause current flow

T A = 25

°C

Supply

VDDGP

VCC

VDDA

NVCC_OSC

Total

VDDGP

VCC

VDDA

NVCC_OSC

Total

VDDGP

VCC

VDDA

NVCC_OSC

Total

Nominal Unit mA 0.18

0.35

0.15

0.012

0.66

mW

0.24

0.45

0.2

1.5

4.8

0.24

0.45

0.2

0.012

1.09

mA mW mA mW

20 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Electrical Characteristics

Table 16. i.MX51 Stop Mode Current and Power Consumption (continued)

Mode Condition

Stop Mode

• External reference clocks enabled

• No power gating for ARM and processing units

• HPM voltage

VDDGP = 1.0 V, VCC = 1.225 V, VDDA = 1.2 V

All PLLs off, all CCM-generated clocks off

CKIL input on with 32 kHz signal present

All modules disabled

USBPHY PLL off

External (MHz) crystal and on-chip oscillator powered and generating reference clock

No external resistive loads that cause current flow

T A = 25

°C

Supply

VDDGP

VCC

VDDA

NVCC_OSC

Total

Nominal Unit mA 50

2

1.15

1.5

63 mW

4.1.2

USB PHY Current Consumption

Table 17

shows the USB PHY current consumption.

Table 17. USB PHY Current Consumption

Parameter Conditions

Analog Supply

VDDA33 (3.3 V)

Analog Supply

NVCC_USBPHY (2.5 V)

Digital Supply

VCC (1.2 V)

VDDA33 + NVCC_USBPHY + VCC

Full Speed

High Speed

Full Speed

High Speed

Full Speed

High Speed

Suspend

RX

TX

RX

TX

RX

TX

RX

TX

RX

TX

RX

TX

Typical @ 25 °C

6.5

6.5

12

21

5.5

7

5

5

6

6

6

6

50

Max

7

7

13

22

6

8

6

6

7

7

7

7

100

Unit mA mA

mA

μA

4.2

Supply Power-Up/Power-Down Requirements and Restrictions

The system design must comply with the power-up and power-down sequence guidelines as described in this section to guarantee reliable operation of the device. Any deviation from these sequences may result in the following situations:

• Excessive current during power-up phase

• Prevention of the device from booting

• Irreversible damage to the i.MX51A processor (worst-case scenario)

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

21

Electrical Characteristics

4.2.1

Power-Up Sequence

Figure 2

shows the power-up sequence.

NVCC_SRTC_POW

VCC

VDDGP

4

NVCC_EMI_DRAM

NVCC_NANDF_x

NVCC_PER15

NVCC_PER17

VDDA

NVCC_HS4_1

NVCC_HS4_2

NVCC_HS6

NVCC_HS10

NVCC_PERx

2

NVCC_EMI

NVCC_IPU

NVCC_I2C

AHVDDRGB

NVCC_TV_BACK

TVDAC_DHVDD

VDD_DIG_PLL_A/B

VDD_ANA_PLL_A/B

NVCC_OSC

NVCC_USBPHY

VDDA33

VDD_FUSE

1

1. VDD_FUSE should only be powered when writing.

2. NVCC_PERx refers to NVCC_PER 3, 5, 8, 9, 10, 11, 12, 13, 14.

3. No power-up sequence dependencies exist between the supplies shown in the block diagram shaded in gray.

4. There is no requirement for VDDGP to be preceded by any other power supply other than NVCC_SRTC_POW.

5. If all of the UHVIO supplies (NVCC_NANDFx, NVCC_PER15 and NVCC_PER17) are less than 2.75 V then there is no requirement on the power up sequence order between NVCC_EMI_DRAM and the UHVIO supplies. However, if the voltage is 2.75 V and above, then NVCC_EMI_DRAM needs to power up before the UHVIO supplies as shown here.

Figure 2. Power-Up Sequence

NOTE

The POR_B input must be immediately asserted at power-up and remain asserted until after the last power rail is at its working voltage.

For more information on power up, see i.MX51 Power-Up Sequence

(AN4053).

4.3

I/O DC Parameters

This section includes the DC parameters of the following I/O types:

• General Purpose I/O and High-Speed General Purpose I/O (GPIO/HSGPIO)

• Double Data Rate 2 (DDR2)

• Low Voltage I/O (LVIO)

• Ultra High Voltage I/O (UHVIO)

• High-Speed I

2

C and I

2

C

• Enhanced Secure Digital Host Controller (eSDHC)

22 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Electrical Characteristics

NOTE

The term OVDD in this section refers to the associated supply rail of an input or output. The association is shown in

Table 128 .

4.3.1

GPIO/HSGPIO DC Parameters

The parameters in Table 18 are guaranteed per the operating ranges in

Table 13

, unless otherwise noted.

Table 18. GPIO/HSGPIO DC Electrical Characteristics

Parameter Symbol Test Conditions Min Typ Max Unit

High-level output voltage Voh Iout = -1 mA OVDD –0.15

— OVDD + 0.3

V

Low-level output voltage

High-level output current

Low-level output current

High-Level DC input voltage

1

Low-Level DC input voltage 1

Vol

Ioh

Iol

VIH

VIL

Iout = 1mA

Vout = 0.8

×

OVDD

Low drive

Medium drive

High drive

Max drive

Vout = 0.2

×

OVDD

Low drive

Medium drive

High drive

Max drive

—

—

—

–1.9

–3.7

–5.2

–6.6

—

1.9

3.7

5.2

6.6

0.7

×

OVDD —

0

—

—

—

0.15

—

—

OVDD

0.3

×

OVDD

—

V mA mA

V

V

Input Hysteresis VHYS OVDD = 1.875

OVDD = 2.775

0.25

0.34

0.45

V

Schmitt trigger VT+ 1,

2

Schmitt trigger VT1, 2

VT+

VT-

—

—

0.5OVDD

—

—

—

—

0.5

×

OVDD

See Note

3

V

V

Input current (no pull-up/down) Iin Vin = OVDD or 0 — — —

Input current (22 k

Input current (47 k

Ω Pull-up)

Ω Pull-up)

Input current (100 k

Input current (100 k

Ω Pull-up)

Ω Pull-down)

Iin

Iin

Iin

Iin

Vin = 0

Vin = 0

Vin = 0

Vin = OVDD

—

—

—

—

—

—

—

—

161

76

36

36

Keeper Circuit Resistance — OVDD = 1.875V

OVDD = 2.775V

—

—

22

17

—

—

2

3

1

To maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current DC level through to the target DC level, VIL or VIH. Monotonic input transition time is from 0.1 ns to 1 s.

Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled.

I/O leakage currents are listed in

Table 25 .

μA

μA

μA

μA k

Ω

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

23

Electrical Characteristics

4.3.2

DDR2 I/O DC Parameters

The parameters in Table 19 are guaranteed per the operating ranges in

Table 13

, unless otherwise noted.

Table 19. DDR2 I/O DC Electrical Parameters

Parameters

High-level output voltage

Low-level output voltage

Output minimum Source Current

Output min Sink Current

DC input Logic High

DC input Logic Low

VIH

VIL

Input voltage range of each differential input Vin

Differential input voltage required for switching Vid

Termination Voltage

Input current (no pull-up/down)

Vtt

Iin

Symbol

Voh

Vol

Ioh

Iol

Test Conditions Min Max Unit

—

—

OVDD = 1.7 V

Vout = 1.42 V

OVDD = 1.7 V

Vout = 0.28 V

OVDD – 0.28

—

–13.4

13.4

—

0.28

—

—

V

V mA mA

—

—

—

—

OVDD/2 + 0.125

–0.3

–0.3

0.25

OVDD + 0.3

OVDD/2 – 0.125

OVDD + 0.3

OVDD + 0.6

Vtt tracking OVDD/2 OVDD/2 – 0.04

OVDD/2 + 0.04

VI = 0

VI = OVDD

—

—

See Note

1

V

V

V

V

V

—

1

I/O leakage currents are listed in

Table 25 .

4.3.3

Low Voltage I/O (LVIO) DC Parameters

The parameters in Table 20 are guaranteed per the operating ranges in

Table 13

, unless otherwise noted.

Table 20. LVIO DC Electrical Characteristics

DC Electrical Characteristics

High-level output voltage

Low-level output voltage

High-level output current

Low-level output current

Symbol

Voh

Vol

I

Ioh

I

Iol

High-Level DC input voltage

1

VIH

Low-Level DC input voltage

1

VIL

Input Hysteresis VHYS

Test Conditions

Iout = –1 mA

Iout = 1 mA

Vout = 0.8

× OVDD

Low Drive

Medium Drive

High Drive

Max Drive

Vout = 0.2

× OVDD

Low Drive

Medium Drive

High Drive

Max Drive

—

—

OVDD = 1.875

OVDD = 2.775

Min

OVDD – 0.15

—

–2.1

–4.2

–6.3

–8.4

2.1

4.2

6.3

8.4

0.7

× OVDD

0

0.35

—

—

—

0.62

1.27

Typ

—

—

—

Max

—

0.15

—

—

OVDD

0.3

× OVDD

—

V

V

V

Unit

V

V mA mA

24 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Electrical Characteristics

Table 20. LVIO DC Electrical Characteristics (continued)

DC Electrical Characteristics Symbol Test Conditions Min Typ Max Unit

Schmitt trigger VT+

Schmitt trigger VT–

1, 2

1, 2

VT+

VT–

—

—

0.5

× OVDD

—

—

—

—

0.5

× OVDD

See Note

3

V

V

Input current (no pull-up/down) Iin VI = 0 or OVDD — — —

Input current (22 k

Input current (47 k

Ω Pull-up)

Ω Pull-up)

Input current (100 k

Input current (100 k

Ω Pull-up)

Ω Pull-down)

Iin

Iin

Iin

Iin

VI = 0

VI = 0

VI = 0

VI = OVDD

—

—

—

—

—

—

—

—

161

76

36

36

Keeper Circuit Resistance — OVDD = 1.875 V

OVDD = 2.775 V

—

—

22

17

—

—

1

2

3

To maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current DC level through to the target DC level, VIL or VIH. Monotonic input transition time is from 0.1 ns to 1 s.

Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled.

I/O leakage currents are listed in

Table 25

.

μA

μA

μA

μA k

Ω

4.3.4

Ultra-High Voltage I/O (UHVIO) DC Parameters

The parameters in Table 21 are guaranteed per the operating ranges in

Table 13

, unless otherwise noted.

Table 21. UHVIO DC Electrical Characteristics

DC Electrical Characteristics

High-level output voltage

Low-level output voltage

High-level output current, low voltage mode

High-level output current, high voltage mode

Low-level output current, low voltage mode

Low-level output current, high voltage mode

Symbol

Voh

Vol

Ioh_lv

Ioh_hv

Iol_lv

Iol_hv

High-Level DC input voltage

1

,

2

VIH

Low-Level DC input voltage

2,3

VIL

Test Conditions

Iout = –1mA

Iout = 1mA

Vout = 0.8

× OVDD

Low Drive

Medium Drive

High Drive

Vout = 0.8

× OVDD

Low Drive

Medium Drive

High Drive

Vout = 0.2

× OVDD

Low Drive

Medium Drive

High Drive

Vout = 0.2

× OVDD

Low Drive

Medium Drive

High Drive

—

—

Min Typ Max

OVDD–0.15

—

— —

—

–2.2

–4.4

–6.6

—

0.15

—

— —

–5.1

–10.2

–15.3

— —

2.2

4.4

6.6

— —

5.1

10.2

15.3

0.7

× OVDD

—

0

OVDD

— 0.3

× OVDD

Unit

V

V mA mA mA mA

V

V

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

25

Electrical Characteristics

Table 21. UHVIO DC Electrical Characteristics (continued)

DC Electrical Characteristics Symbol Test Conditions Min Typ Max Unit

Input Hysteresis VHYS Low voltage mode

High voltage mode

0.38

0.95

— 0.43

1.33

V

Schmitt trigger VT+

Schmitt trigger VT–

2,3

2,4

VT+

VT–

—

—

0.5OVDD

—

— —

— 0.5

× OVDD

— See Note

4

V

V

Input current (no pull-up/down) Iin Vin = 0

Vin = OVDD

— —

Input current (22 k

Ω Pull-up)

Input current (75 k

Ω Pull-up)

Input current (100 k

Ω Pull-up)

Input current (360 k

Ω Pull-down)

Iin

Iin

Iin

Iin

Vin = 0

Vin = 0

Vin = 0

Vin = OVDD

—

—

—

—

—

—

—

—

202

61

47

5.7

μA

μA

μA

μA

Keeper Circuit Resistance — NA — 17 — k

Ω

3

4

1

2

To maintain a valid level, the transitioning edge of the input must sustain a constant slew rate (monotonic) from the current DC level through to the target DC level, VIL or VIH. Monotonic input transition time is from 0.1 ns to 1 s.

Overshoot and undershoot conditions (transitions above OVDD and below OVSS) on switching pads must be held below 0.6 V, and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/undershoot must be controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other methods.

Non-compliance to this specification may affect device reliability or cause permanent damage to the device.

Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled.

I/O leakage currents are listed in Table 25 .

The UHVIO type of I/O cells have to be configured properly according to their supply voltage level, in order to prevent permanent damage to them and in order to not degrade their timing performance.

The HVE control bit of the I/O cell (in IOMUX control registers) should be set to 1 for Low voltage operation and to 0 for High voltage operation.

The HVE bit should be set as follows:

• HVE = 0: High output voltage mode (3.0V to 3.6V)

• HVE = 1: Low output voltage mode (1.65V to 3.1V)

This is related to power domains, such as NVCC_NANDF, NVCC_PER15, and NVCC_PER17.

If HVE bit is not set properly when high voltage level is applied for long durations, it may cause permanent damage over a period of time, causing reduced timing performance of the pad. Similarly, not setting HVE bit properly for low voltage will degrade pad timing performance.

The below discussion clarifies concerns about boot-up period.

The HVE bit is set, by default, to 1 for low voltage operation. As a result, there might be a short period conflict between the HVE bit value and the applied voltage. This conflict is acceptable under the following conditions:

26 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Electrical Characteristics

• The UHVIO pads receive supply voltage up to 3.3V (3.6V max); however, the pads do not toggle during the boot-up sequence (using another interface as a boot code source), for boot-up period of about 22 msec.

• The UHVIO pads receive up to 3.15V (3.3V max) and are used for accessing the boot code, for boot-up period of about 11 msec.

In any case, it is recommended to try to minimize the duration of this period and reduce the amount of toggling on the pads as much as possible. For this, it is recommended to add proper HVE bit programming to the DCD boot-up tables. DCD is a table located in the start of the image that can hold up to 60 address/values. ROM code reads addresses and writes values to it. This space should be sufficient to reprogram the NAND Flash pads for HVE bits.

4.3.5

I

2

C I/O DC Parameters

NOTE

See the errata for HS-I2C in i.MX51 Chip Errata document. The two standard I

2

C modules have no errata.

The DC Electrical Characteristics listed in Table 22

are guaranteed using operating ranges per Table 13 ,

unless otherwise noted.

Table 22. I

2

C Standard/Fast/High-Speed Mode Electrical Parameters for Low/Medium Drive Strength

Parameter Symbol Test Conditions Min Typ Max Unit

Low-level output voltage

High-Level DC input voltage

Low-Level DC input voltage

1

1

Vol

VIH

VIL

Iol = 3 mA

—

—

0.7

—

× OVDD

0

—

—

—

0.4

OVDD

0.3

× OVDD

V

V

V

Input Hysteresis VHYS — 0.25

— — V

Schmitt trigger VT+

1,2

VT+ — 0.5

× OVDD

— — V

Schmitt trigger VT–

1,2

VT– — — — 0.5

× OVDD

See Note

3

V

I/O leakage current (no pull-up) Iin VI = OVDD or 0 — — —

1

2

3

To maintain a valid level, the transitioning edge of the input must sustain a constant slew rate (monotonic) from the current

DC level through to the target DC level, VIL or VIH. Monotonic input transition time is from 0.1 ns to 1 s.

Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled.

I/O leakage currents are listed in

Table 25

.

4.3.6

USBOTG Electrical DC Parameters

This section describes the electrical DC parameters of USBOTG.

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

27

Electrical Characteristics

4.3.7

USB Port Electrical DC Characteristics

Table 23 and Table 24 list the electrical DC characteristics.

Table 23. USBOTG Interface Electrical Specification

Parameter

Input High Voltage

Input low Voltage

Output High Voltage

Output Low Voltage

Symbol

VIH

VIL

VOH

VOL

Signals

USB_VPOUT

USB_VMOUT

USB_XRXD,

USB_VPIN,

USB_VMIN

USB_VPOUT

USB_VMOUT

USB_XRXD,

USB_VPIN,

USB_VMIN

USB_VPOUT

USB_VMOUT

USB_TXENB

USB_VPOUT

USB_VMOUT

USB_TXENB

Min

VDD x 0.7

0

VDD – 0.43

—

Max

VDD

VDD

× 0.3

—

0.43

Unit

V

V

V

V

Parameter

Input High Voltage

Input Low Voltage

Output High Voltage

Output Low Voltage

Test Conditions

—

—

7 mA Drv at IOH = 5 mA

7 mA Drv at IOH = 5 mA

Table 24. USB Interface Electrical Specification

Max Symbol

VIH

VIL

VOH

VOL

Signals

USB_DAT_VP

USB_SE0_VM

USB_RCV,

USB_VP1,

USB_VM1

USB_DAT_VP

USB_SE0_VM

USB_RCV,

USB_VP1,

USB_VM1

USB_DAT_VP

USB_SE0_VM

USB_TXOE_B

USB_DAT_VP

USB_SE0_VM

USB_TXOE_B

Min

VDD x 0.7

0

VDD –0.43

—

VDD

VDD x 0.3

0.43

—

V

Unit

V

V

V

Test Conditions

—

—

7 mA Drv at Iout = 5 mA

7 mA Drv at Iout = 5 mA

28 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Electrical Characteristics

Table 25

shows the I/O leakage currents that are based on the operating ranges in Table 13

and the operating temperatures in

Table 1 .

.

Table 25. I/O Leakage Current

NANDF

Contact Group

EIM

DRAM

CSI1, CSI2, DISP1_Data[5:0] NVCC_HSx

I

2

C1

DI1_DAT[23:6],

DISPB_SER_x, DI_GPx

CKIL, PMIC_x

EXTAL, XTAL

ID, GPANAIO

Supply Rail

NVCC_NANDF

NVCC_EMI

NVCC_DRAM

NVCC_I2C

NVCC_IPU

NVCC_SRTC_POW

NVCC_OSC

NVCC_USBPHY

DISP2_DAT[0:15] NVCC_IPU,

NVCC_HS

SD1, SD2 NVCC_PER15,

NVCC_PER17

Peripherals except SD1, SD2 NVCC_PERx

Test Condition

V[I/O] = GND or Positive

Supply Rail, I/O = High Z

V[I/O] = GND or Positive

Supply Rail, I/O = High Z

V[I/O] = GND or Positive

Supply Rail, I/O = High Z

V[I/O] = GND or Positive

Supply Rail, I/O = High Z

V[I/O] = GND or Positive

Supply Rail, I/O = High Z

V[I/O] = GND or Positive

Supply Rail, I/O = High Z

V[I/O] = GND or Positive

Supply Rail, I/O = High Z

V[I/O] = GND or Positive

Supply Rail, I/O = High Z

V[I/O] = GND or Positive

Supply Rail, I/O = High Z

V[I/O] = GND or Positive

Supply Rail, I/O = High Z

V[I/O] = GND or Positive

Supply Rail, I/O = High Z

V[I/O] = GND or Positive

Supply Rail, I/O = High Z

Min

—

—

—

—

—

—

—

—

—

—

—

—

Typ

—

—

—

—

—

—

—

—

—

—

—

—

Max

±1

±1

±2.5

±1.5

±1

±2

±1

±170

±170

±2

±10

±2

Unit

μA

μA

μA

μA

μA

μA

μA

μA

μA

μA

μA

μA

4.4

Output Buffer Impedance Characteristics

This section defines the I/O Impedance parameters of the i.MX51A processor.

4.4.1

LVIO I/O Output Buffer Impedance

Table 26 shows the LVIO I/O output buffer impedance.

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

29

Electrical Characteristics

Parameter Symbol

Output Driver

Impedance

Output Driver

Impedance

Table 26. LVIO I/O Output Buffer Impedance

Typical

Conditions Min

Rpu Low Drive Strength, Ztl = 150

Ω

Medium Drive Strength, Ztl = 75

Ω

High Drive Strength, Ztl = 50

Ω

Max Drive Strength, Ztl = 37.5

Ω

Rpd Low Drive Strength, Ztl = 150

Ω

Medium Drive Strength, Ztl = 75

Ω

High Drive Strength, Ztl = 50

Ω

Max Drive Strength, Ztl = 37.5

Ω

64

32

21

16

80

40

27

20

OVDD 2.775 V OVDD 1.875 V

104

52

35

26

88

44

30

22

150

75

51

38

134

66

44

34

Max

250

125

83

62

243

122

81

61

Unit

Ω

Ω

4.4.2

DDR2 Output Buffer Impedance

Table 27 shows the DDR2 output buffer impedance.

Table 27. DDR2 I/O Output Buffer Impedance HVE = 0

Parameter Symbol

Output Driver

Impedance

Output Driver

Impedance

Test Conditions

Rpu Low Drive Strength, Ztl = 150

Ω

Medium Drive Strength, Ztl = 75

Ω

High Drive Strength, Ztl = 50

Ω

Max Drive Strength

Rpd Low Drive Strength, Ztl = 150

Ω

Medium Drive Strength, Ztl = 75

Ω

High Drive Strength, Ztl = 50

Ω

Max Drive Strength

Best Case

T j

= –40 °C

OVDD = 1.95 V

VCC = 1.3 V

Typical

T j

= 25 °C

OVDD = 1.8 V

VCC = 1.2 V

Worst Case

T j

= 105 °C

OVDD = 1.6 V

VCC = 1.1 V Unit s0–s5

000000

185

92.5

61.7

26.5

190.3

95.1

63.4

27.6

s0–s5

101010

140

70

47

19.5

145.4

72.7

48.5

19.9

s0–s5

111111

111.4

55.7

37.2

15.4

120.6

60.3

40.2

16.9

Ω

Ω

30 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Electrical Characteristics

4.4.3

UHVIO Output Buffer Impedance

Table 28 shows the UHVIO output buffer impedance.

Table 28. UHVIO Output Buffer Impedance

Parameter Symbol

Output Driver

Impedance

Output Driver

Impedance

Test Conditions

Rpu Low Drive Strength, Ztl = 150

Ω

Medium Drive Strength, Ztl = 75

Ω

High Drive Strength, Ztl = 50

Ω

Rpd Low Drive Strength, Ztl =1 50

Ω

Medium Drive Strength, Ztl = 75

Ω

High Drive Strength, Ztl = 50

Ω

OVDD

1.95 V

OVDD

3.0 V

OVDD

1.875 V

OVDD

3.3 V

98

49

32

97

49

32

Min

114

57

38

118

59

40

124

62

41

126

63

42

Typ

135

67

45

154

77

51

Max

OVDD

1.65 V

OVDD

3.6 V

Unit

Ω

198

99

66

179

89

60

206

103

69

217

109

72

Ω

NOTE

Output driver impedance is measured with long transmission line of impedance Ztl attached to I/O pad and incident wave launched into transmission lime. Rpu/Rpd and Ztl form a voltage divider that defines specific voltage of incident wave relative to OVDD. Output driver

impedance is calculated from this voltage divider (see Figure 3 ).

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

31

Electrical Characteristics ipp_do predriver

U,(V)

VDD

OVDD

PMOS (Rpu) pad

Ztl

Ω, L = 20 inches

NMOS (Rpd)

OVSS

Vin (do)

Cload = 1p

U,(V)

OVDD

0

Vref

Vref1

Vref2 t,(ns)

Vout (pad)

0

Rpu =

Vovdd – Vref1

Vref1

× Ztl

Rpd =

Vref2

Vovdd – Vref2

× Ztl

Figure 3. Impedance Matching Load for Measurement t,(ns)

32 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Electrical Characteristics

4.5

I/O AC Parameters

The load circuit and output transition time waveforms are shown in Figure 4 and Figure 5 . AC electrical

characteristics for slow and fast I/O are presented in the

Table 29 and

Table 30

, respectively.

From Output

Under Test

Test Point

CL

CL includes package, probe and fixture capacitance

Figure 4. Load Circuit for Output

Output (at I/O)

80% tr

20% tf

Figure 5. Output Transition Time Waveform

80%

NVCC

20%

0V

4.5.1

Slow I/O AC Parameters

Table 29 shows the slow I/O AC parameters.

Table 29. Slow I/O AC Parameters

Parameter

Output Pad Transition Times (Max Drive)

Output Pad Transition Times (High Drive)

Output Pad Transition Times (Medium Drive)

Output Pad Transition Times (Low Drive)

Output Pad Slew Rate (Max Drive)

Output Pad Slew Rate (High Drive)

Output Pad Slew Rate (Medium Drive)

Output Pad Slew Rate (Low Drive)

Output Pad di/dt (Max Drive)

Output Pad di/dt (High Drive)

Output Pad di/dt (Medium drive)

Symbol Test Condition Min Rise/Fall Typ Max Rise/Fall tr, tf — — tr, tf tr, tf tr, tf tps tps tps tps tdit tdit tdit

15 pF

35 pF

15 pF

35 pF

15 pF

35 pF

15 pF

35 pF

15 pF

35 pF

15 pF

35 pF

15 pF

35 pF

15 pF

35 pF

—

—

—

—

—

—

0.5/0.65

0.32/0.37

0.43/0.54

0.26/0.41

0.34/0.41

0.18/0.2

0.20/0.22

0.09/0.1

—

—

—

—

—

—

—

—

—

—

—

—

—

1.98/1.52

3.08/2.69

2.31/1.838

3.8/2.4

2.92/2.43

5.37/4.99

4.93/4.53

10.55/9.79

—

—

—

—

30

23

15

Unit ns ns ns ns

V/ns

V/ns

V/ns

V/ns mA/ns mA/ns mA/ns

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

33

Electrical Characteristics

Table 29. Slow I/O AC Parameters (continued)

Parameter Symbol Test Condition Min Rise/Fall Typ Max Rise/Fall

Output Pad di/dt (Low drive)

Input Transition Times

1 tdit trm

—

—

—

—

1

Hysteresis mode is recommended for inputs with transition times greater than 25 ns.

—

—

7

25

Unit mA/ns ns

4.5.2

Fast I/O AC Parameters

Table 30

shows the fast I/O AC parameters.

Table 30. Fast I/O AC Parameters

Parameter Symbol

Test

Condition

Min Rise/Fall

Output Pad Transition Times (Max Drive)

Output Pad Transition Times (High

Drive)

Output Pad Transition Times (Medium

Drive)

Output Pad Transition Times (Low Drive)

Output Pad Slew Rate (Max Drive)

Output Pad Slew Rate (High Drive)

Output Pad Slew Rate (Medium Drive) tr, tf tr, tf tr, tf tr, tf tps tps tps

15 pF

35 pF

15 pF

35 pF

15 pF

35 pF

15 pF

35 pF

15 pF

35 pF

15 pF

35 pF

15 pF

35 pF

—

—

—

—

0.69/0.78

0.36/0.39

0.55/0.62

0.28/0.30

0.39/0.44

0.19/0.20

Output Pad Slew Rate (Low Drive)

Output Pad di/dt (Max Drive)

Output Pad di/dt (High Drive) tps tdit tdit

15 pF

35 pF

—

—

0.21/0.22

0.09/0.1

—

—

Output Pad di/dt (Medium drive) tdit — —

Output Pad di/dt (Low drive)

Input Transition Times

1 tdit trm

—

—

—

—

1

Hysteresis mode is recommended for inputs with transition time greater than 25 ns.

Typ

—

—

—

—

—

—

—

—

—

—

—

—

—

Max Rise/Fall

1.429/1.275

2.770/2.526

1.793/1.607

3.565/3.29

2.542/2.257

5.252/4.918

4.641/4.456

10.699/10.0

—

—

—

—

70

53

35

18

25

4.5.3

I

2

C AC Parameters

NOTE

See the errata for HS-I

2

C in the i.MX51 Chip Errata document. The two standard I

2

C modules have no errata

Unit ns ns ns ns

V/ns

V/ns

V/ns

V/ns mA/ns mA/ns mA/ns mA/ns ns

34 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Electrical Characteristics

Figure 6 depicts the load circuit for output pads for standard- and fast-mode. Figure 7 depicts the output

pad transition time definition.

Figure 8 depicts load circuit with external pull-up current source for

HS-mode.

Figure 9

depicts HS-mode timing definition.

From Output

Under Test

Test Point

CL

CL includes package, probe and fixture capacitance

Figure 6. Load Circuit for Standard and Fast-Mode

Output

OVDD

70%

30%

0V tf

Figure 7. Definition of Timing for Standard and Fast-Mode

OVDD

From Output

Under Test

3 mA

1

Test Point

CL

2

Notes:

1

Load current when output is between 0.3

×

OVDD and 0.7

2

CL includes package, probe, and fixture capacitance.

×

OVDD

Figure 8. Load Circuit for HS-Mode with External Pull-Up Current Source

70%

Output (at pad)

30% t

TLH t

THL

PA3Max = max of t

TLH

and t

THL

PA4Max = max t

THL

Figure 9. Definition of Timing for HS-Mode

70%

30%

OVDD

0V

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

35

Electrical Characteristics

The electrical characteristics for I

2

C I/O are listed in Table 31

to

Table 34 . Characteristics are guaranteed

using operating ranges per Table 13 , unless otherwise noted.

Table 31. I

2

C Standard- and Fast-Mode Electrical Parameters for Low/Medium Drive Strength and OVDD = 2.7 V–3.3 V

Parameter

Output fall time,

(low driver strength)

Output fall time,

(medium driver strength)

Symbol tf

Test Conditions from V

IHmin

to V

ILmax

with C

L

from 10 pF to 400 pF tf from V

IHmin

to V

ILmax

with C

L

from 10 pF to 400 pF

Min

—

—

Typ Max Unit

— 52 ns

— 28 ns

Parameter

Output fall time,

(low driver strength)

Output fall time,

(medium driver strength)

Table 32. I

2

C Standard- and Fast-Mode Electrical Parameters for Low/Medium Drive Strength and OVDD = 1.65 V–1.95 V

Symbol t of

Test Conditions from V

IHmin

to V

ILmax

with C

L

from 10 pF to 400 pF

Min

— t of from V

IHmin

to V

ILmax

with C

L

from 10 pF to 400 pF —

Typ Max Unit

— 70 ns

— 35 ns

Table 33. I

2

C High-Speed Mode Electrical Parameters for Low/Medium Drive Strength and OVDD = 2.7 V–3.3 V

Parameter

Output rise time (current-source enabled) and fall time at SCLH

(low driver strength)

Output rise time (current-source enabled) and fall time at SCLH

(medium driver strength)

Output fall time at SDAH

(low driver strength)

Output fall time at SDAH

(medium driver strength)

Output fall time at SDAH

(low driver strength)

Output fall time at SDAH

(medium driver strength)

Symbol t rCL

, t fCL t rCL

, t fCL t fDA t fDA t fDA t fDA

Test Conditions with a 3mA external pull-up current source and C

L

= 100 pF with a 3mA external pull-up current source and C

L

= 100 pF with C

L

from 10 pF to

100 pF with C

L

from 10 pF to

100 pF

C

L

= 400 pF

Min Typ

— —

—

—

—

—

—

—

—

—

C

L

= 400 pF — —

Max

18/21

9/9

14

8

52

27

Unit ns ns ns ns ns ns

36 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Parameter

Output rise time (current-source enabled) and fall time at SCLH

(low driver strength)

Output rise time (current-source enabled) and fall time at SCLH

(medium driver strength)

Output fall time at SDAH

(low driver strength)

Output fall time at SDAH

(medium driver strength)

Output fall time at SDAH

(low driver strength)

Output fall time at SDAH

(medium driver strength)

Table 34. I

2

C High-Speed Mode Electrical Parameters for Low/Medium Drive Strength and OVDD = 1.65 V–1.95 V

Symbol t rCL

, t fCL

Test Conditions with a 3 mA external pull-up current source and C

L

= 100 pF

Min

— t rCL

, t fCL t fDA t fDA t fDA t fDA with a 3 mA external pull-up current source and C

L

= 100 pF with C

L

from 10 pF to 100 pF with C

L

from 10 pF to 100 pF

C

L

= 400 pF

C

L

= 400 pF

—

0

0

30

15

Electrical Characteristics

Typ Max

— 10/74

Unit ns

—

—

—

—

—

7/14

17

9

67

34 ns ns ns ns ns

Table 35. Low Voltage I

2

C I/O Parameters

Parameter Symbol Test Condition Min Rise/Fall

Output Pad di/dt (Medium drive) tdit — —

Output Pad di/dt (Low drive) tdit — —

Input Transition Times

1 trm — —

1

Hysteresis mode is recommended for inputs with transition time greater than 25 ns

Table 36. High Voltage I

2

C I/O Parameters

Parameter Symbol Test Condition Min Rise/Fall Typ

— — Output Pad Transition Times (Medium Drive)

Output Pad Transition Times (Low Drive)

Output Pad Slew Rate (Medium Drive) tr, tf tr, tf tps

15 pF

35 pF

15 pF

35 pF

15 pF

35 pF

Output Pad Slew Rate (Low Drive) tps 15 pF

35 pF

— Output Pad di/dt (Medium drive) tdit

Output Pad di/dt (Low drive) tdit —

Input Transition Times

1 trm —

1

Hysteresis mode is recommended for inputs with transition time > 25 ns

—

0/0

0/0

0/0

0/0

—

—

—

—

—

—

—

—

—

Typ

—

—

—

Max Rise/Fall

22

11

25

Unit mA/ns mA/ns ns

Max Rise/Fall

3/3

6/5

5/5

9/9

—

—

36

16

25

Unit ns ns

V/ns

V/ns mA/ns mA/ns ns

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

37

Electrical Characteristics

4.5.4

AC Electrical Characteristics for DDR2

The load circuit for output pads, the output pad transition time waveform and the output pad propagation and transition time waveform are below.

Figure 10

shows the output pad transition time waveform.

Figure 10. Output Pad Transition Time Waveform

Figure 11

shows the output pad propagation and transition time waveform.

Figure 11. Output Pad Propagation and Transition Time Waveform

AC electrical characteristics in DDR2 mode for fast mode and for ovdd = 1.65 – 1.95 V, ipp_hve = 0 are

placed in Table 37

.

Table 37. AC Electrical Characteristics of DDR2 IO Pads for Fast mode and for ovdd=1.65–1.95 V (ipp_hve=0)

Parameter

Output Pad Transition Times

1

Output Pad Propagation Delay, 50%-50%

1

Output Pad Slew Rate

1

Symbol

Test

Condition

Min rise/fall tpr tpo tps

15pF

35pF

15pF

35pF

15pF

35pF

0.57/0.57

1.29/1.29

0.98/0.96

1.47/1.50

2.05/2.05

0.91/0.91

Typ

0.45/0.44

0.97/0.94

1.27/1.19

1.63/1.57

2.40/2.45

1.11/1.15

Max rise/fall

0.45/0.45

0.82/0.85

1.89/1.72

2.20/2.07

2.20/2.20

1.21/1.16

Units ns ns

V/ns

38 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Electrical Characteristics

Table 37. AC Electrical Characteristics of DDR2 IO Pads for Fast mode and for ovdd=1.65–1.95 V (ipp_hve=0) (continued)

Parameter Symbol

Test

Condition

Min rise/fall

Typ

Max rise/fall

Units

Output Pad di/dt

1

Input Pad Transition Times

2

Input Pad Propagation Delay without Hysteresis

(CMOS input), 50%-50%

2

Input Pad Propagation Delay with Hysteresis

(CMOS input), 50%-50%

2 di/dt trfi tpi tpi

—

1.2 pF

1.2 pF

1.2 pF

390

0.09/0.09

0.45/0.93

0.55/0.55

201

0.132/0.128

0.6/0.58

0.71/0.7

99

0.212/0.213

0.9/0.88

1.03/0.98

mA/ns ns ns ns

Input Pad Propagation Delay (DDR input),

50%-50%

2

Maximum Input Transition Times

3 tpi 1.2 pF 0.38/0.38

0.58/0.61

1.014/1.07

ns trm — — — 5 ns

1

2

3

Max condition for tpr, tpo, tps and didt: wcs model, 1.1 V, IO 1.65 V, 105 °C and s0-s5=111111. Typ condition for tpr, tpo, tps and didt: typ model, 1.2 V, IO 1.8 V, 25 °C and s0-s5 = 101010. Min condition for tpr, tpo, tps and didt: bcs model, 1.3 V,

IO 1.95 V, –40 °C and s0-s5=000000.

Max condition for trfi and tpi: wcs model, 1.1 V, IO 1.65 V and 105 °C. Typ condition for trfi and tpi: typ model, 1.2 V, IO

1.8 V and 25 °C. Min condition for trfi and tpi: bcs model, 1.3 V, IO 1.95 V and –40 °C.

Hysteresis mode is recommended for input with transition time greater than 25 ns.

AC electrical characteristics in DDR2 mode for Slow mode and for ovdd=1.65 – 1.95 V, ipp_hve = 0 are

placed in Table 38

:

Table 38. AC Electrical Characteristics of DDR2 IO Pads for Slow Mode and for ovdd=1.65–1.95 V (ipp_hve=0)

Parameter

Output Pad Transition Times

1

Output Pad Propagation Delay, 50%-50%

1

Output Pad Slew Rate

1

Output Pad di/dt

1

Input Pad Transition Times

2

Input Pad Propagation Delay without Hysteresis

(CMOS input), 50%-50%

2

Input Pad Propagation Delay with Hysteresis

(CMOS input), 50%-50%

2

Input Pad Propagation Delay (DDR input),

50%-50%

2

Maximum Input Transition Times

3

Symbol tpr tpo tps di/dt trfi tpi

Test

Condition

Min rise/fall

Typ

Max rise/fall

Units

15pF

35pF

15pF

35pF

0.75/0.76

1.39/1.40

1.50/1.55

2.05/2.16

0.70/0.74

1.18/1.21

1.90/1.95

2.36/2.48

1.06/1.00

1.49/1.47

3.23/3.10

3.82/3.75

ns ns

15pF

35pF

1.56/1.54

0.84/0.84

1.54/1.46

0.92/0.89

0.93/0.99

0.66/0.67

V/ns

— 82 40 19 mA/ns

1.2 pF 0.09/0.09

0.132/0.128

0.212/0.213

ns

1.2 pF 0.45/0.93

0.6/0.58

0.9/0.88

ns tpi tpi trm

1.2 pF 0.55/0.55

0.71/0.7

1.2 pF 0.38/0.38

0.58/0.61

— — —

1.03/0.98

1.014/1.07

5 ns ns ns

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

39

Electrical Characteristics

1

2

3

Max condition for tpr, tpo, tps and didt: wcs model, 1.1 V, IO 1.65 V, 105 °C and s0-s5=111111. Typ condition for tpr, tpo, tps and didt: typ model, 1.2 V, IO 1.8 V, 25 °C and s0-s5 = 101010. Min condition for tpr, tpo, tps and didt: bcs model, 1.3 V,

IO 1.95 V, –40 °C and s0-s5 = 000000.

Max condition for trfi and tpi: wcs model, 1.1 V, IO 1.65 V and 105 °C. Typ condition for trfi and tpi: typ model, 1.2 V, IO

1.8 V and 25 °C. Min condition for trfi and tpi: bcs model, 1.3 V, IO 1.95 V and –40 °C.

Hysteresis mode is recommended for input with transition time greater than 25 ns.

AC electrical characteristics in DDR mobile for Fast mode and ovdd=1.65 – 1.95 V, ipp_hve=0 are placed

in Table 39 .

Table 39. AC Electrical Characteristics of DDR mobile IO Pads for Fast Mode and ovdd=1.65–1.95 V (ipp_hve=0)

Parameter

Output Pad Transition Times (High Drive)

1

Output Pad Transition Times (Medium Drive)

1

Output Pad Transition Times (Low Drive)

1

Output Pad Propagation Delay (High Drive)

1

Output Pad Propagation Delay (Medium Drive)

1

Output Pad Propagation Delay (Low Drive)

1

Output Pad Slew Rate (High Drive)

1

Output Pad Slew Rate (Medium Drive)

1

Output Pad Slew Rate (Low Drive)

1

Output Pad di/dt (High Drive)

1

Output Pad di/dt (Medium drive)

1

Output Pad di/dt (Low drive)

1

Input Pad Transition Times

2

Input Pad Propagation Delay without Hysteresis

(CMOS input), 50%-50%

2

Input Pad Propagation Delay with Hysteresis

(CMOS input), 50%-50%

2

Input Pad Propagation Delay (DDR input),

50%-50%

2

Maximum Input Transition Times

3

Symbol tpr tpr tpr tpo tpo tpo tps tps tps di/dt di/dt di/dt trfi tpi

Test

Condition

Min rise/fall

Typ

Max rise/fall

Units

15pF

35pF

15pF

35pF

15pF

35pF

15pF

35pF

15pF

35pF

15pF

35pF

1.35/1.31

2.99/2.94

2.00/1.99

4.55/4.44

4.08/3.92

8.93/8.95

1.54/1.52

2.69/2.75

2.00/2.02

3.75/3.86

3.43/3.52

6.92/7.20

1.02/1.03

2.28/2.29

1.56/1.53

3.38/3.45

3.11/3.06

6.84/6.81

1.73/1.62

2.59/2.55

2.08/2.00

3.38/3.39

3.13/3.13

5.72/5.94

0.89/0.89

1.85/1.94

1.28/1.32

2.79/2.85

2.50/2.61

5.56/5.76

2.36/2.09

3.04/2.86

2.64/2.40

3.65/3.56

3.47/3.34

5.49/5.65

ns ns ns ns ns ns

15pF

35pF

15pF

35pF

15pF

35pF

0.87/0.89

0.39/0.40

0.58/0.59

0.26/0.26

0.29/0.30

0.13/0.13

1.06/1.05

0.47/0.47

0.69/0.71

0.32/0.31

0.35/0.35

0.16/0.16

1.11/1.11

0.54/0.51

0.77/0.75

0.35/0.35

0.40/0.38

0.18/0.17

V/ns

V/ns

V/ns

—

—

185

124

91

61

46

31 mA/ns mA/ns

— 62 30 16 mA/ns

1.2 pF 0.09/0.09

0.132/0.128

0.212/0.213

ns

1.2 pF 0.45/0.93

0.6/0.58

0.9/0.88

ns tpi tpi trm

1.2 pF 0.55/0.55

0.71/0.7

1.2 pF 0.38/0.38

0.58/0.61

— — —

1.03/0.98

1.014/1.07

5 ns

— ns

40 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Electrical Characteristics

1

2

3

Max condition for tpr, tpo, tps and didt: wcs model, 1.1 V, IO 1.65 V, 105 °C and s0-s5=111111. Typ condition for tpr, tpo, tps and didt: typ model, 1.2 V, IO 1.8 V, 25 °C and s0-s5 = 101010. Min condition for tpr, tpo, tps and didt: bcs model, 1.3 V,

IO 1.95 V, –40 °C and s0-s5 = 000000.

Max condition for trfi and tpi: wcs model, 1.1 V, IO 1.65 V and 105 °C. Typ condition for trfi and tpi: typ model, 1.2 V, IO

1.8 V and 25 °C. Min condition for trfi and tpi: bcs model, 1.3 V, IO 1.95 V and –40 °C.

Hysteresis mode is recommended for input with transition time greater than 25 ns.

AC electrical characteristics in DDR mobile for Slow mode and ovdd=1.65-1.95V, ipp_hve=0 are placed

in Table 40 .

Table 40. AC Electrical Characteristics of DDR mobile IO Pads for Slow Mode ovdd=1.65–1.95 V (ipp_hve=0)

Parameter

Output Pad Transition Times (High Drive)

1

Output Pad Transition Times (Medium Drive)

1

Output Pad Transition Times (Low Drive)

1

Output Pad Propagation Delay (High Drive)

1

Output Pad Propagation Delay (Medium Drive)

1

Output Pad Propagation Delay (Low Drive)

1

Output Pad Slew Rate (High Drive)

1

Output Pad Slew Rate (Medium Drive)

1

Output Pad Slew Rate (Low Drive)

1

Output Pad di/dt (High Drive)

1

Output Pad di/dt (Medium drive)

1

Output Pad di/dt (Low drive)

1

Input Pad Transition Times

2

Input Pad Propagation Delay without Hysteresis

(CMOS input), 50%-50%

2

Input Pad Propagation Delay with Hysteresis

(CMOS input), 50%-50%

2

Input Pad Propagation Delay (DDR input),

50%-50%

2

Maximum Input Transition Times

3

Symbol tpr tpr tpr tpo tpo tpo tps tps tps di/dt di/dt di/dt trfi tpi

Test

Condition

Min rise/fall

Typ

Max rise/fall

Units

15pF

35pF

15pF

35pF

15pF

35pF

15pF

35pF

15pF

35pF

15pF

35pF

1.42/1.43

3.03/2.92

2.04/2.04

4.51/4.49

4.08/3.93

9.06/8.93

2.00/2.17

3.15/3.42

2.47/2.68

4.2/4.53

3.87/4.18

7.32/7.86

1.20/1.27

2.39/2.38

1.68/1.74

3.47/3.50

3.16/3.19

6.92/6.93

2.33/2.50

3.24/3.52

2.72/2.92

4.01/4.37

3.78/4.10

6.35/6.90

1.43/1.49

2.35/2.46

1.82/1.91

3.16/3.30

2.90/3.01

5.74/5.96

3.70/3.70

4.63/4.75

4.10/4.16

5.33/5.55

5.13/5.30

7.25/7.73

ns ns ns ns ns ns

15pF

35pF

15pF

35pF

15pF

35pF

0.82/0.82

0.39/0.40

0.57/0.57

0.26/0.26

0.29/0.30

0.13/0.13

0.90/0.85

0.45/0.49

0.70/0.62

0.31/0.31

0.34/0.34

0.16/0.16

0.69/0.66

0.42/0.40

0.54/0.52

0.31/0.30

0.34/0.33

0.17/0.17

V/ns

V/ns

V/ns

—

—

47

27

12

14

9

5

9

6

3 mA/ns mA/ns mA/ns

1.2 pF 0.09/0.09

0.132/0.128

0.212/0.213

ns

1.2 pF 0.45/0.93

0.6/0.58

0.9/0.88

ns tpi tpi trm

1.2 pF 0.55/0.55

0.71/0.7

1.2 pF 0.38/0.38

0.58/0.61

— — —

1.03/0.98

1.014/1.07

5 ns

— ns

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

41

Electrical Characteristics

1

2

3

Max condition for tpr, tpo, tps and didt: wcs model, 1.1 V, IO 1.65 V, 105 °C and s0-s5=111111. Typ condition for tpr, tpo, tps and didt: typ model, 1.2 V, IO 1.8 V, 25 °C and s0-s5=101010. Min condition for tpr, tpo, tps and didt: bcs model, 1.3 V,

IO 1.95 V, –40 °C and s0-s5=000000.

Max condition for trfi and tpi: wcs model, 1.1 V, IO 1.65 V and 105 °C. Typ condition for trfi and tpi: typ model, 1.2 V, IO

1.8 V and 25 °C. Min condition for trfi and tpi: bcs model, 1.3 V, IO 1.95 V and –40 °C.

Hysteresis mode is recommended for input with transition time greater than 25 ns.

AC electrical characteristics in DDR2 mode for Fast mode and for ovdd=1.65–1.95V, ipp_hve=0 are

placed in Table 41

.

Table 41. AC Electrical Characteristics of DDR2_clk IO Pads for Fast mode and for ovdd=1.65–1.95 V

Parameter Symbol

Test

Condition

Min rise/fall

Typ

Max rise/fall

Units

Output Pad Transition Times

1 tpr 15pF

35pF

0.58/0.57

1.29/1.28

0.45/0.44

0.97/0.93

0.45/0.45

0.82/0.85

ns

Output Pad Propagation Delay, 50%-50%

Output Pad Slew Rate

1

1 tpo tps

15pF

35pF

15pF

35pF

1.05/1.03

1.54/1.56

2.02/2.05

0.91/0.91

1.40/1.31

1.75/1.69

2.40/2.45

1.11/1.16

2.12/1.96

2.43/2.31

2.20/2.20

1.21/1.16

ns

V/ns

Output Pad di/dt

1

Input Pad Transition Times

2 di/dt trfi

—

1.2 pF

390

0.09/0.09

201

0.132/0.128

99

0.212/0.213

mA/ns ns

Input Pad Propagation Delay (DDR input),

50%-50%

2

Maximum Input Transition Times

3 tpi 1.2 pF 0.3/0.36

0.5/0.52

0.82/0.94

ns trm — — — 5 ns

1

2

3

Max condition for tpr, tpo, tps and didt: wcs model, 1.1 V, IO 1.65 V, 105 °C and s0-s5=111111. Typ condition for tpr, tpo, tps and didt: typ model, 1.2 V, IO 1.8 V, 25 °C and s0-s5=101010. Min condition for tpr, tpo, tps and didt: bcs model, 1.3 V,

IO 1.95 V, -40 °C and s0-s5=000000.

Max condition for trfi and tpi: wcs model, 1.1 V, IO 1.65 V and 105 °C. Typ condition for trfi and tpi: typ model, 1.2 V, IO 1.8

V and 25 °C. Min condition for trfi and tpi: bcs model, 1.3 V, IO 1.95 V and -40 °C.

Hysteresis mode is recommended for input with transition time greater than 25 ns.

AC electrical characteristics in DDR2 mode for Slow mode and for ovdd=1.65-1.95V, ipp_hve=0 are

placed in Table 42

.

Table 42. AC Electrical Characteristics of DDR2_clk IO Pads for Slow mode and for ovdd=1.65 – 1.95 V (ipp_hve=0)

Parameter

Output Pad Transition Times

1

Output Pad Propagation Delay, 50%-50%

1

Output Pad Slew Rate

1

Symbol

Test

Condition

Min rise/fall tpr tpo tps

15pF

35pF

15pF

35pF

15pF

35pF

0.74/0.76

1.40/1.39

1.56/1.61

2.12/2.22

1.58/1.54

0.84/0.84

Typ

0.69/0.72

1.18/1.20

2.02/2.08

2.49/2.61

1.57/1.50

0.92/0.90

Max rise/fall

1.04/1.01

1.48/1.47

3.45/3.33

4.05/3.98

0.95/0.98

0.67/0.67

Units ns ns

V/ns

42 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Electrical Characteristics

Table 42. AC Electrical Characteristics of DDR2_clk IO Pads for Slow mode and for ovdd=1.65 – 1.95 V (ipp_hve=0) (continued)

Parameter Symbol

Test

Condition

Min rise/fall

Typ

Max rise/fall

Units

Output Pad di/dt

1

Input Pad Transition Times

2 di/dt trfi

—

1.2 pF

82

0.09/0.09

40

0.132/0.128

19

0.212/0.213

mA/ns ns

Input Pad Propagation Delay (DDR input),

50%-50%

2 tpi 1.2 pF 0.3/0.36

0.5/0.52

0.82/0.94

ns

Maximum Input Transition Times

3 trm — — — 5 ns

1

2

3

Max condition for tpr, tpo, tps and didt: wcs model, 1.1 V, IO 1.65 V, 105 °C and s0-s5=111111. Typ condition for tpr, tpo, tps and didt: typ model, 1.2 V, IO 1.8 V, 25 °C and s0-s5=101010. Min condition for tpr, tpo, tps and didt: bcs model, 1.3 V,

IO 1.95 V, -40 °C and s0-s5=000000.

Max condition for trfi and tpi: wcs model, 1.1 V, IO 1.65 V and 105 °C. Typ condition for trfi and tpi: typ model, 1.2 V, IO 1.8

V and 25 °C. Min condition for trfi and tpi: bcs model, 1.3 V, IO 1.95 V and -40 °C.

Hysteresis mode is recommended for input with transition time greater than 25 ns.

AC electrical characteristics in DDR mobile for Fast mode and ovdd=1.65-1.95V, ipp_hve=0 are placed in

Table 43 .

Table 43. AC Electrical Characteristics of DDR_clk mobile IO Pads for Fast mode and ovdd=1.65 – 1.95 V (ipp_hve=0)

Parameter

Output Pad Transition Times (High Drive)

1

Output Pad Transition Times (Medium Drive)

1

Output Pad Transition Times (Low Drive)

1

Output Pad Propagation Delay (High Drive)

1

Output Pad Propagation Delay (Medium Drive)

1

Output Pad Propagation Delay (Low Drive)

1

Output Pad Slew Rate (High Drive)

1

Output Pad Slew Rate (Medium Drive)

1

Output Pad Slew Rate (Low Drive)

1

Output Pad di/dt (High Drive)

1

Output Pad di/dt (Medium drive)

1

Symbol

Test

Condition

Min rise/fall tpr tpr tpr tpo tpo tpo tps tps tps di/dt di/dt

15pF

35pF

15pF

35pF

15pF

35pF

15pF

35pF

—

—

15pF

35pF

15pF

35pF

15pF

35pF

15pF

35pF

15pF

35pF

3.47/3.57

6.94/7.26

0.87/0.89

0.39/0.40

0.59/0.59

0.26/0.27

0.29/0.30

0.13/0.13

185

124

1.35/1.32

3.01/2.96

1.98/1.98

4.52/4.38

3.99/3.94

8.93/8.86

1.60/1.58

2.74/2.81

2.07/2.08

3.79/3.92

Typ

3.23/3.25

5.84/6.06

1.05/1.05

0.47/0.47

0.70/0.70

0.31/0.31

0.35/0.36

0.16/0.16

91

61

1.03/1.03

2.29/2.30

1.55/1.54

3.46/3.45

3.10/3.04

6.77/6.85

1.85/1.74

2.71/2.67

2.19/2.12

3.46/3.51

Max rise/fall

3.69/3.55

5.73/5.87

1.11/1.11

0.54/0.52

0.77/0.76

0.35/0.34

0.40/0.39

0.18/0.17

46

31

0.89/0.89

1.84/1.92

1.29/1.30

2.80/2.88

2.50/2.57

5.40/5.68

2.58/2.31

3.26/3.08

2.86/2.62

3.87/3.77

Units ns ns ns ns ns ns

V/ns

V/ns

V/ns mA/ns mA/ns

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

43

Electrical Characteristics

Table 43. AC Electrical Characteristics of DDR_clk mobile IO Pads for Fast mode and ovdd=1.65 – 1.95 V (ipp_hve=0) (continued)

Parameter Symbol

Test

Condition

Min rise/fall

Typ

Max rise/fall

Units

Output Pad di/dt (Low drive)

1

Input Pad Transition Times

2 di/dt trfi

—

1.2 pF

62

0.09/0.09

30

0.132/0.128

16

0.212/0.213

mA/ns ns

Input Pad Propagation Delay (DDR input),

50%-50%

2 tpi 1.2 pF 0.3/0.36

0.5/0.52

0.82/0.94

—

Maximum Input Transition Times

3 trm — — — 5 ns

1

2

3

Max condition for tpr, tpo, tps and didt: wcs model, 1.1 V, IO 1.65 V, 105 °C and s0-s5=111111. Typ condition for tpr, tpo, tps and didt: typ model, 1.2 V, IO 1.8 V, 25 °C and s0-s5=101010. Min condition for tpr, tpo, tps and didt: bcs model, 1.3 V,

IO 1.95 V, –40 °C and s0-s5=000000.

Max condition for trfi and tpi: wcs model, 1.1 V, IO 1.65 V and 105 °C. Typ condition for trfi and tpi: typ model, 1.2 V, IO

1.8 V and 25 °C. Min condition for trfi and tpi: bcs model, 1.3 V, IO 1.95 V and –40 °C.

Hysteresis mode is recommended for input with transition time greater than 25 ns.

AC electrical characteristics in DDR mobile for Slow mode and ovdd=1.65-1.95V, ipp_hve=0 are placed

in Table 44 .

Table 44. AC Electrical Characteristics of DDR mobile IO Pads for Slow Mode and ovdd=1.65 – 1.95 V (ipp_hve=0)

Parameter

Output Pad Transition Times (High Drive)

1

Output Pad Transition Times (Medium Drive)

1

Output Pad Transition Times (Low Drive)

1

Output Pad Propagation Delay (High Drive)

1

Output Pad Propagation Delay (Medium Drive)

1

Output Pad Propagation Delay (Low Drive)

1

Output Pad Slew Rate (High Drive)

1

Output Pad Slew Rate (Medium Drive)

1

Output Pad Slew Rate (Low Drive)

1

Output Pad di/dt (High Drive)

1

Output Pad di/dt (Medium drive)

1

Symbol

Test

Condition

Min rise/fall tpr tpr tpr tpo tpo tpo tps tps tps di/dt di/dt

15pF

35pF

15pF

35pF

15pF

35pF

15pF

35pF

—

—

15pF

35pF

15pF

35pF

15pF

35pF

15pF

35pF

15pF

35pF

3.93/4.23

7.38/7.91

0.82/0.82

0.39/0.40

0.57/0.57

0.26/0.26

0.29/0.29

0.13/0.13

47

27

1.42/1.42

3.01/2.96

2.05/2.04

4.50/4.42

4.06/3.98

8.94/8.86

2.07/2.23

3.21/3.48

2.53/2.74

4.26/4.58

Typ

3.89/4.21

6.43/7.01

0.90/0.85

0.45/0.45

0.65/0.63

0.31/0.31

0.34/0.34

0.16/0.16

14

9

1.20/1.27

2.38/2.40

1.67/1.71

3.48/3.52

3.15/3.17

6.92/6.93

2.46/2.62

3.35/3.63

2.83/3.04

4.12/4.49

Max rise/fall

Units

5.37/5.51

7.45/7.94

0.69/0.66

0.42/0.41

0.54/0.53

0.31/0.30

0.34/0.33

0.17/0.17

9

6

1.43/1.49

2.37/2.44

1.82/1.87

3.16/3.28

2.92/ 3.02

5.69/5.96

3.92/3.93

4.84/4.97

4.32/4.35

5.55/5.76

ns ns ns ns ns ns

V/ns

V/ns

V/ns mA/ns mA/ns

44 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Electrical Characteristics

Table 44. AC Electrical Characteristics of DDR mobile IO Pads for Slow Mode and ovdd=1.65 – 1.95 V (ipp_hve=0) (continued)

Parameter Symbol

Test

Condition

Min rise/fall

Typ

Max rise/fall

Units

Output Pad di/dt (Low drive)

1

Input Pad Transition Times

2 di/dt trfi

—

1.2 pF

12

0.09/0.09

5

0.132/0.128

3

0.212/0.213

mA/ns ns

Input Pad Propagation Delay (DDR input),

50%-50%

2 tpi 1.2 pF 0.3/0.36

0.5/0.52

0.82/0.94

—

Maximum Input Transition Times

3 trm — — — 5 ns

1

2

3

Max condition for tpr, tpo, tps and didt: wcs model, 1.1 V, IO 1.65 V, 105 °C and s0-s5=111111. Typ condition for tpr, tpo, tps and didt: typ model, 1.2 V, IO 1.8 V, 25 °C and s0-s5=101010. Min condition for tpr, tpo, tps and didt: bcs model, 1.3 V,

IO 1.95 V, –40 °C and s0-s5=000000.

Max condition for trfi and tpi: wcs model, 1.1 V, IO 1.65 V and 105 °C. Typ condition for trfi and tpi: typ model, 1.2 V, IO

1.8 V and 25 °C. Min condition for trfi and tpi: bcs model, 1.3 V, IO 1.95 V and –40 °C.

Hysteresis mode is recommended for input with transition time greater than 25 ns.

4.6

Module Timing

This section contains the timing and electrical parameters for the modules in the i.MX51 processor.

4.6.1

Reset Timings Parameters

Figure 12

shows the reset timing and

Table 45 lists the timing parameters.

RESET_IN

(Input)

CC1

Figure 12. Reset Timing Diagram

Table 45. Reset Timing Parameters

ID Parameter

CC1 Duration of RESET_IN to be qualified as valid (input slope = 5 ns)

Min

50

Max

—

Unit ns

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

45

Electrical Characteristics

4.6.2

WDOG Reset Timing Parameters

Figure 13 shows the WDOG reset timing and Table 46

lists the timing parameters.

WATCHDOG_RST

(Input)

CC5

Figure 13. WATCHDOG_RST Timing Diagram

Table 46. WATCHDOG_RST Timing Parameters

ID Parameter

CC5 Duration of WATCHDOG_RESET Assertion

Min

1

Max

—

NOTE

CKIL is approximately 32 kHz. T

CKIL

is one period or approximately 30

μs.

Unit

T

CKIL

4.6.3

AUDMUX Timing Parameters

The AUDMUX provides a programmable interconnect logic for voice, audio and data routing between internal serial interfaces (SSIs) and external serial interfaces (audio and voice codecs). The AC timing of

AUDMUX external pins is hence governed by the SSI module.

4.6.4

Clock Amplifier Parameters (CKIH1, CKIH2)

The input to Clock Amplifier (CAMP) is internally ac-coupled allowing direct interface to a square wave

or sinusoidal frequency source. No external series capacitors are required. Table 47 shows the CAMP

electrical parameters.

Table 47. CAMP Electrical Parameters (CKIH1, CKIH2)

Parameter

Input frequency

VIL (for square wave input)

VIH (for square wave input)

Sinusoidal input amplitude

Output duty cycle

Min

8.0

0

NVCC_PER3 - 0.25

0.4

45

Typ

—

—

—

—

50

Max

40.0

0.3

NVCC_PER3

VDD

55

Unit

MHz

V

V

Vp-p

%

46 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Electrical Characteristics

4.6.5

DPLL Electrical Parameters

Table 48

shows the DPLL electrical parameters.

Table 48. DPLL Electrical Parameters

Parameter

Reference clock frequency range

1

Test Conditions/Remarks

Reference clock frequency range after pre-divider

Output clock frequency range (dpdck_2)

Pre-division factor

2

Multiplication factor integer part

Multiplication factor numerator

3

Multiplication factor denominator

2

—

—

—

—

—

Should be less than denominator

—

Min

10

10

Typ

—

—

300

1

—

—

5 —

–67108862 —

1 —

Max

100

40

1025

16

15

67108862

67108863

Unit

MHz

MHz

MHz

—

—

—

—

Output Duty Cycle

Frequency lock time

4

(FOL mode or non-integer MF)

—

—

48.5

—

50

—

51.5

398

%

T d pdref

Phase lock time — — — 100 µ s

Frequency jitter

5

(peak value)

Phase jitter (peak value)

Power dissipation f f

—

FPL mode, integer and fractional MF dck dck

= 300 MHz @ avdd = 1.8 V, dvdd = 1.2 V

= 650 MHz @ avdd = 1.8 V, dvdd = 1.2 V

—

—

—

0.02

2.0

0.04

3.5

— 0.65 (avdd)

0.92 (dvdd)

1.98 (avdd)

1.8 (dvdd)

T dck ns mW

1

2

3

4

5

Device input range cannot exceed the electrical specifications of the CAMP, see

Table 47

.

The values specified here are internal to DPLL. Inside the DPLL, a “1” is added to the value specified by the user.Therefore, the user has to enter a value “1” less than the desired value at the inputs of DPLL for PDF and MFD.

The maximum total multiplication factor (MFI + MFN/MFD) allowed is 15.Therefore, if the MFI value is 15, MFN value must be zero.

T dpdref

is the time period of the reference clock after predivider.According to the specification, the maximum lock time in FOL mode is 398 cycles of divided reference clock when DPLL starts after full reset.

Tdck is the time period of the output clock, dpdck_2.

4.6.6

NAND Flash Controller (NFC) Parameters

This section provides the relative timing requirements among different signals of NFC at the module level in the different operational modes.

Timing parameters in Figure 14 , Figure 15 , Figure 16

, Figure 17 ,

Figure 19 , and Table 50

show the default

NFC mode (asymmetric mode) using two Flash clock cycles per one access of RE_B and WE_B. Timing parameters in

Figure 14 , Figure 15 , Figure 16

, Figure 18 ,

Figure 19

, and

Table 50 show symmetric NFC

mode using one Flash clock cycle per one access of RE_B and WE_B.

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

47

Electrical Characteristics

With reference to the timing diagrams, a high is defined as 80% of signal value and low is defined as 20% of signal value. All parameters are given in nanoseconds. The BGA contact load used in calculations is 20 pF (except for NF16 - 40 pF) and there is max drive strength on all contacts.

All timing parameters are a function of T, which is the period of the flash_clk clock (“enfc_clk” at system level). This clock frequency can be controlled by the user, configuring CCM (SoC clock controller). The clock is derived from emi_slow_clk after single divider.

Table 49 demonstrates few examples for clock

frequency settings.

Table 49. NFC Clock Settings Examples emi_slow_clk (MHz) nfc_podf (Division Factor) enfc_clk (MHz) T—Clock Period (ns)

1

133 (max value)

133

133

1

Rounded up to whole nanoseconds.

5 (reset value)

4

3

26.6

33.25

44.33

38

31

23

NOTE

A potential limitation for minimum clock frequency may exist for some devices. When the clock frequency is too low the actual data bus capturing might occur after the specified trhoh (RE_B high to output hold) period.

Setting the clock frequency above 25.6 MHz (T = 39 ns) guarantees proper operation for devices having trhoh > 15 ns. It is also recommended to set the

NFC_FREQ_SEL Fuse accordingly to initiate the boot with 33.33 MHz clock.

Lower frequency operation can be supported for most available devices in the market, relying on data lines Bus-Keeper logic. This depends on device behavior on the data bus in the time interval between data output valid to data output high-Z state. In NAND device parameters this period is marked between trhoh and trhz (RE_B high to output high-Z). In most devices, the data transition from valid value to high-Z occurs without going through other states. Setting the data bus pads to Bus-Keeper mode in the IOMUX registers, keeps the data bus valid internally after the specified hold time, allowing proper capturing with slower clock.

48 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Electrical Characteristics

NFCLE

NFCE_B

NF1

NF3

NF2

NF4

NFWE_B

NFIO[7:0]

NFCE_B

NFWE_B

NFALE

NFIO[7:0]

NFCE_B

NFWE_B

NFIO[15:0]

NF5

NF8 command

NF9

Figure 14. Command Latch Cycle Timing

NF3 NF4

NF5

NF10

NF11

NF7 NF6

NF8

NF9

Address

Figure 15. Address Latch Cycle Timing

NF3

NF5

NF10

NF11

NF8

NF9

Data to NF

Figure 16. Write Data Latch Timing

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

49

Electrical Characteristics

NFCE_B

NF14

NF13

NF15

NFRE_B

NF16 NF17

NFRB_B

NF12

NFIO[15:0] Data from NF

Figure 17. Read Data Latch Timing—Asymmetric Mode

NFCE_B

NF13

NF14

NF15

NFRE_B

NF16

NF18

NFRB_B

NF12

NFIO[15:0] Data from NF

Figure 18. Read Data Latch Timing—Symmetric Mode

50 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Electrical Characteristics

NF19

NFCLE

NFCE_B

NFWE_B

NF20

NF22

NF21

NFRE_B

ID

NF9

NF10

NF11

NF12

NF13

NF14

NF15

NF16

1

NF17

3

NF18

4

NF19

NF20

NF5

NF6

NF7

NF8

NF1

NF2

NF3

NF4

NFRB_B

Figure 19. Other Timing Parameters

Table 50. NFC—Timing Characteristics

Parameter

NFCLE setup Time

NFCLE Hold Time

NFCE_B Setup Time

NFCE_B Hold Time

NFWE_B Pulse Width

NFALE Setup Time

NFALE Hold Time

Data Setup Time

Data Hold Time

Write Cycle Time

NFWE_B Hold Time

Ready to NFRE_B Low

NFRE_B Pulse Width

READ Cycle Time

NFRE_B High Hold Time

Data Setup on READ

Data Hold on READ

Data Hold on READ

CLE to RE delay

CE to RE delay

Symbol tDH tWC tWH tRR tRP tRC tREH tDSR tCLS tCLH tCS tCH tWP tALS tALH tDS tDHR tDHR tCLR tCRE

Asymmetric

Mode Min

2T-1

T-4.45

2T-1

2T-5.55

T-2.5

2T-2.7

T-4.45

T-2.25

T-6.55

2T

T-1.25

9T

1.5T-2.7

2T

0.5T-1.5

11.2+0.5T-Tdl

2

0

—

13T

T-3.45

Symmetric

Mode Min

0.5T-5.55

T

0.5T-1.25

9T

0.5T

T

0.5T-1.5

11.2-Tdl

2

—

Tdl

2

13T

1.5T-3.45

2T-1

T-4.45

T-1

0.5T-5.55

0.5T-1.5

2T-2.7

T-4.45

0.5T-2.25

Max

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

2T aclk +T

2T aclk +T

—

—

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

51

Electrical Characteristics

Table 50. NFC—Timing Characteristics (continued)

ID Parameter Symbol

Asymmetric

Mode Min

Symmetric

Mode Min

Max

NF21 WE high to RE low tWHR 14T-5.45

14T-5.45

—

NF22 WE high to busy tWB — — 6T

1

2

3

4 t

DSR

is calculated by the following formula:

Asymmetric mode: t DSR = t REpd + t Dpd +

1

/

2

T – Tdl

2

Symmetric mode: t DSR = t REpd + t Dpd – Tdl

2 t REpd + t Dpd = 11.2 ns (including clock skew) where t REpd is RE propogation delay in the chip including IO pad delay, and t Dpd is Data propogation delay from IO pad to EMI including IO pad delay. t DSR can be used to determine t REA max parameter with the following formula: t REA = 1.5T – t DSR .

Tdl is composed of 4 delay-line units each generates an equal delay with min 1.25 ns and max 1 aclk period (T aclk ). Default is 1/4 aclk period for each delay-line unit, so all 4 delay lines together generates a total of 1 aclk period. T aclk is “emi_slow_clk” of the system, which default value is 7.5 ns (133 MHz).

NF17 is defined only in asymmetric operation mode.

NF17 max value is equivalent to max t RHZ value that can be used with NFC.

T aclk is “emi_slow_clk” of the system.

NF18 is defined only in Symmetric operation mode. t

DHR

(MIN) is calculated by the following formula: Tdl

2

–

(t

REpd

+ t

Dpd

) where t REpd is RE propogation delay in the chip including IO pad delay, and t Dpd is Data propogation delay from IO pad to EMI including IO pad delay.

NF18 max value is equivalent to max t RHZ value that can be used with NFC.

T aclk is “emi_slow_clk” of the system.

4.6.7

External Interface Module (WEIM)

The following sections provide information on the WEIM.

4.6.7.1

WEIM Signal Cross Reference

Table 51

is a guide to help the user identify signals in the WEIM Chapter of the i.MX51 Multimedia

Applications Processor Reference Manual (MCIMX51RM) that are the same as those mentioned in this data sheet.

Table 51. WEIM Signal Cross Reference

Reference Manual

WEIM Chapter Nomenclature

BCLK

CSx

WE_B

OE_B

BEy_B

ADV

Data Sheet Nomenclature,

Reference Manual External Signals and Pin Multiplexing Chapter, and IOMUX Controller Chapter Nomenclature

EIM_BCLK

EIM_CSx

EIM_RW

EIM_OE

EIM_EBx

EIM_LBA

52 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Electrical Characteristics

ADDR

ADDR/M_DATA

DATA

WAIT_B

Table 51. WEIM Signal Cross Reference (continued)

Reference Manual

WEIM Chapter Nomenclature

Data Sheet Nomenclature,

Reference Manual External Signals and Pin Multiplexing Chapter, and IOMUX Controller Chapter Nomenclature

EIM_A[27:16], EIM_DA[15:0]

EIM_DAx (Addr/Data muxed mode)

EIM_NFC_D (Data bus shared with NAND Flash)

EIM_Dx (dedicated data bus)

EIM_WAIT

4.6.7.2

WEIM Internal Module Multiplexing

Table 52 provides WEIM internal muxing information.

38 4

Table 52. WEIM Interface Pinout in Various Configurations

A[15:0]

A[27:16]

Non Multiplexed Address/Data Mode

(MUM=0)

Multiplexed

Address/Data Mode

(MUM=1)

8-Bit

(DSZ=100)

8-Bit

(DSZ=101)

8-Bit

1

(DSZ=110

)

8-Bit

(DSZ=111

)

16-Bit

(DSZ=001)

16-Bit

(DSZ=010)

32-Bit

(DSZ=011

)

16-Bit

(DSZ=001)

32-Bit

(DSZ=011)

EIM_DA

[15:0]

EIM_A

[27:16]

EIM_DA

[15:0]

EIM_A

[27:16]

EIM_DA

[15:0]

EIM_A

[27:16]

EIM_DA

[15:0]

EIM_A

[27:16]

EIM_DA

[15:0]

EIM_A

[27:16]

EIM_DA

[15:0]

EIM_A

[27:16]

EIM_DA

[15:0]

EIM_A

[27:16]

EIM_DA

[15:0]

EIM_A

[27:16]

EIM_DA

[15:0]

NANDF_D

[11:0]

D[7:0],

EIM_EB0

NANDF_D

[7:0]

— — —

D[15:8],

EIM_EB1

D[23:16],

EIM_EB2

— NANDF_D

[15:8]

—

— —

— EIM_D

[23:16]

—

D[31:24],

EIM_EB3

— — — EIM_D

[31:24]

1

This mode is not supported due to erratum ENGcm11244.

NANDF_D

[7:0]

NANDF_D

[15:8]

—

—

—

—

EIM_D

[23:16]

EIM_D

[31:24]

NANDF_D

[7:0]

NANDF_D

[15:8]

EIM_D

[23:16]

EIM_D

[31:24]

EIM_DA

[7:0]

EIM_DA

[15:8]

—

—

EIM_DA

[7:0]

EIM_DA

[15:8]

NANDF_D

[7:0]

NANDF_D

[15:8]

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

53

Electrical Characteristics

4.6.7.3

General WEIM Timing-Synchronous Mode

Figure 20 , Figure 21 , and Table 53 specify the timings related to the WEIM module. All WEIM output

control signals may be asserted and deasserted by an internal clock synchronized to the BCLK rising edge according to corresponding assertion/negation control fields.

,

WE2

...

WE3

BCLK

WE4

WE1

WE5

Address

CSx_B

WE6

WE7

WE8 WE9

WE_B

WE10

WE11

OE_B

WE12

WE13

BEy_B

WE14 WE15

ADV_B

WE16

WE17

Output Data

Figure 20. WEIM Outputs Timing Diagram

ID Parameter

WE1 BCLK Cycle time

2

WE2 BCLK Low Level

Width

BCLK

WE18

Input Data

WE19

WE20

WAIT_B

WE21

Figure 21. WEIM Inputs Timing Diagram

Table 53. WEIM Bus Timing Parameters

1

BCD = 0 BCD = 1 BCD = 2

Min t

0.4 x t

Max Min

2 x t

0.8 x t

Max Min

3 x t

1.2 x t

Max Min

4 x t

1.6 x t

BCD = 3

Max

54 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Electrical Characteristics

Table 53. WEIM Bus Timing Parameters (continued)

1

BCD = 0 BCD = 1 BCD = 2

ID Parameter

Min Max Min Max Min Max

WE3 BCLK High Level

Width

WE4 Clock rise to address valid

3

WE5 Clock rise to address invalid

WE6 Clock rise to CSx_B valid

WE7 Clock rise to CSx_B invalid

WE8 Clock rise to WE_B

Valid

WE9 Clock rise to WE_B

Invalid

WE10 Clock rise to OE_B

Valid

WE11 Clock rise to OE_B

Invalid

WE12 Clock rise to BEy_B

Valid

WE13 Clock rise to BEy_B

Invalid

WE14 Clock rise to ADV_B

Valid

WE15 Clock rise to ADV_B

Invalid

WE16 Clock rise to Output

Data Valid

WE17 Clock rise to Output

Data Invalid

WE18 Input Data setup time to Clock rise

WE19 Input Data hold time from Clock rise

WE20 WAIT_B setup time to

Clock rise

WE21 WAIT_B hold time from Clock rise

0.4 x t 0.8 x t 1.2 x t

-0.5 x t -

1.25

0.5 x t -

1.25

-0.5 x t +

1.75

-t - 1.25

-t + 1.75

-1.5 x t -

1.25

0.5 x t + 1.75

t - 1.25

t + 1.75

1.5 x t -

1.25

-0.5 x t -

1.25

0.5 x t -

1.25

-0.5 x t +

1.75

-t - 1.25

-t + 1.75

-1.5 x t -

1.25

0.5 x t + 1.75

t - 1.25

t + 1.75

1.5 x t -

1.25

-0.5 x t -

1.25

0.5 x t -

1.25

-0.5 x t +

1.75

-t - 1.25

-t + 1.75

-1.5 x t -

1.25

0.5 x t + 1.75

t - 1.25

t + 1.75

1.5 x t -

1.25

-0.5 x t -

1.25

0.5 x t -

1.25

-0.5 x t +

1.75

-t - 1.25

-t + 1.75

-1.5 x t -

1.25

0.5 x t + 1.75

t - 1.25

t + 1.75

1.5 x t -

1.25

-0.5 x t -

1.25

0.5 x t -

1.25

-0.5 x t +

1.75

-t - 1.25

-t + 1.75

-1.5 x t -

1.25

0.5 x t + 1.75

t - 1.25

t + 1.75

1.5 x t -

1.25

-0.5 x t -

1.25

0.5 x t -

1.25

-0.5 x t +

1.75

-t - 1.25

-t + 1.75

-1.5 x t -

1.25

0.5 x t + 1.75

t - 1.25

t + 1.75

1.5 x t -

1.25

-0.5 x t -

1.25

-0.5 x t +

1.75

-t - 1.25

-t + 1.75

-1.5 x t -

1.25

0.5 x t -

1.25

2 ns

0.5 x t + 1.75

t - 1.25

t + 1.75

1.5 x t -

1.25

— 4 ns — —

-1.5 x t

+1.75

1.5 x t +

1.75

-1.5 x t +

1.75

1.5 x t +

1.75

-1.5 x t +

1.75

1.5 x t +

1.75

-1.5 x t +

1.75

1.5 x t +

1.75

-1.5 x t +

1.75

1.5 x t +

1.75

-1.5 x t +

1.75

1.5 x t +

1.75

-1.5 x t +

1.75

1.5 x t +

1.75

—

2 ns

2 ns

2 ns

—

—

—

2 ns

4 ns

2 ns

—

—

—

—

—

—

—

—

—

Min

BCD = 3

1.6 x t

Max

-2 x t -

1.25

2 x t -

1.25

-2 x t +

1.75

2 x t + 1.75

-2 x t -

1.25

2 x t -

1.25

-2 x t +

1.75

2 x t + 1.75

-2 x t -

1.25

2 x t -

1.25

-2 x t +

1.75

2 x t + 1.75

-2 x t -

1.25

2 x t -

1.25

-2 x t +

1.75

2 x t + 1.75

-2 x t -

1.25

2 x t -

1.25

-2 x t +

1.75

2 x t + 1.75

-2 x t -

1.25

2 x t -

1.25

-2 x t +

1.75

2 x t + 1.75

-2 x t -

1.25

-2 x t +

1.75

2 x t + 1.75

2 x t -

1.25

— —

—

—

—

—

—

—

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

55

Electrical Characteristics

1

2

3 t is the maximal WEIM logic (axi_clk) cycle time. The maximum allowed axi_clk frequency is 133 MHz, whereas the maximum allowed BCLK frequency is 104 MHz. As a result, if BCD = 0, axi_clk must be

≤

104 MHz. If BCD = 1, then 133 MHz is allowed for axi_clk, resulting in a BCLK of 66.5 MHz. When the clock branch to WEIM is decreased to 104 MHz, other busses are impacted which are clocked from this source. See the CCM chapter of the i.MX51 Reference Manual for a detailed clock tree description.

BCLK parameters are being measured from the 50% point, that is, high is defined as 50% of signal value and low is defined as 50% as signal value.

For signal measurements “High” is defined as 80% of signal value and “Low” is defined as 20% of signal value.

4.6.7.4

Examples of WEIM Synchronous Accesses

Figure 22

to

Figure 25 provide few examples of basic WEIM accesses to external memory devices with

the timing parameters mentioned previously for specific control parameters settings.

BCLK

ADDR

CSx_B

WE_B

ADV_B

OE_B

BEy_B

DATA

Last Valid Address

WE4

WE6

WE14

WE10

WE12

Address v1

WE15

WE18

D(v1)

WE5

WE7

WE11

WE13

WE19

Figure 22. Synchronous Memory Read Access, WSC=1

56 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Electrical Characteristics

BCLK

ADDR

CSx_B

WE_B

ADV_B

OE_B

BEy_B

DATA

Last Valid Address

WE4

WE6

WE8

WE14

WE12

WE16

WE5

Address V1

WE7

WE9

WE15

WE13

WE17

D(V1)

Figure 23. Synchronous Memory, Write Access, WSC=1, WBEA=0, and WADVN=0

BCLK

ADDR/

M_DATA

CSx_B

WE4

WE6

WE5

Address V1

WE16 WE17

Write Data

WE7

WE8

WE9

WE_B

ADV_B

OE_B

WE14 WE15

WE10

WE11

BEy_B

Figure 24. Muxed Address/Data (A/D) Mode, Synchronous Write Access, WSC=6, ADVA=0, ADVN=1, and

ADH=1

NOTE

In 32-bit muxed address/data (A/D) mode the 16 MSBs are driven on the data bus.

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

57

Electrical Characteristics

BCLK

ADDR/

M_DATA

CSx_B

WE4

Last Valid Addr

WE6

Address V1

WE5 WE19

Data

WE18

WE7

WE_B

ADV_B

OE_B

WE14 WE15

WE10

WE11

WE12

WE13

BEy_B

Figure 25. 16-Bit Muxed A/D Mode, Synchronous Read Access, WSC=7, RADVN=1, ADH=1, and OEA=0

4.6.7.5

General WEIM Timing-Asynchronous Mode

Figure 26

through

Figure 31

, and

Table 54 help to determine timing parameters relative to the chip select

(CS) state for asynchronous and DTACK WEIM accesses with corresponding WEIM bit fields and the timing parameters mentioned above.

Asynchronous read and write access length in cycles may vary from what is shown in

Figure 26

through

Figure 29

as RWSC, OEN, and CSN is configured differently. See i.MX51 reference manual for the

WEIM programming model.

58 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Electrical Characteristics start of access end of access

INT_CLK

MAXCSO

CSx_B

ADDR/

M_DATA

WE_B

ADV_B

WE31

Last Valid Address

OE_B

BEy_B

DATA[7:0]

Address V1

WE32

WE39

WE35

WE37

WE40

WE36

WE38

WE44

MAXCO

WE43

D(V1)

MAXDI

Figure 26. Asynchronous Memory Read Access (RWSC = 5)

Next Address start of access end of access

INT_CLK

CSx_B

ADDR/

M_DATA

WE_B

ADV_B

OE_B

BEy_B

MAXCSO

WE31

WE39

WE35A

WE37

Addr. V1

WE32A

WE40A

MAXDI

D(V1)

WE36

WE38

WE44

MAXCO

Figure 27. Asynchronous A/D Muxed Read Access (RWSC = 5)

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

59

Electrical Characteristics

CSx_B

ADDR/

M_DATA

WE_B

ADV_B

OE_B

BEy_B

CSx_B

ADDR

WE_B

ADV_B

OE_B

BEy_B

DATA

WE31

Last Valid Address

WE33

WE39

WE45

Address V1

WE32

WE34

WE40

WE46

WE42

D(V1)

WE41

Figure 28. Asynchronous Memory Write Access

Next Address

WE31

WE41A

Addr. V1

WE32A

WE33

WE39

WE40A

D(V1)

WE34

WE42

WE45 WE46

WE42

Figure 29. Asynchronous A/D Muxed Write Access

60 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Electrical Characteristics

CSx_B

ADDR

WE_B

ADV_B

OE_B

BEy_B

DATA

DTACK

CSx_B

ADDR

WE_B

ADV_B

OE_B

BEy_B

DATA[7:0]

WE31

Last Valid Address

WE39

WE35

WE37

DTACK

Address V1

WE32

WE40

WE36

WE38

WE43

D(V1)

WE47

Figure 30. DTACK Read Access (DAP=0)

WE31

Last Valid Address

WE33

WE39

Address V1

WE32

WE34

WE40

Next Address

WE44

WE48

Next Address

WE45 WE46

WE42

D(V1)

WE41

WE47

Figure 31. DTACK Write Access (DAP=0)

WE48

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

61

Electrical Characteristics

Table 54. WEIM Asynchronous Timing Parameters Table Relative Chip Select

Ref No.

Parameter

Determination by

Synchronous measured parameters

12

WE31 CSx_B valid to Address Valid WE4 - WE6 - CSA

3

WE7 - WE5 - CSN

4

WE32 Address Invalid to CSx_B invalid

WE32A( muxed

A/D

CSx_B valid to Address Invalid t

5

+ WE4 - WE7 + (ADVN +

ADVA + 1 - CSA

3

)

WE33 CSx_B Valid to WE_B Valid WE8 - WE6 + (WEA - CSA)

WE34 WE_B Invalid to CSx_B Invalid WE7 - WE9 + (WEN - CSN)

Min

—

—

-3 + (ADVN +

ADVA + 1 - CSA)

Max

(If 133 MHz is supported by SOC)

3 - CSA

3 - CSN

—

Unit ns ns ns

—

—

3 + (WEA - CSA)

3 - (WEN_CSN) ns ns

WE35

WE35A

(muxed

A/D)

WE36

WE37

CSx_B Valid to OE_B Valid

OE_B Invalid to CSx_B Invalid

CSx_B Valid to BEy_B Valid

(Read access)

WE10 - WE6 + (OEA - CSA)

WE7 - WE11 + (OEN - CSN)

WE12 - WE6 + (RBEA - CSA)

—

—

—

3 + (OEA - CSA)

CSx_B Valid to OE_B Valid WE10 - WE6 + (OEA + RADVN

+ RADVA + ADH + 1 - CSA)

-3 + (OEA +

RADVN+RADVA+

ADH+1-CSA)

3 + (OEA +

RADVN+RADVA+AD

H+1-CSA) ns ns

3 - (OEN - CSN) ns

3 + (RBEA

6

- CSA) ns

WE38 BEy_B Invalid to CSx_B Invalid

(Read access)

WE7 - WE13 + (RBEN - CSN) — 3 - (RBEN

7

- CSN) ns

WE39

WE40

CSx_B Valid to ADV_B Valid WE14 - WE6 + (ADVA - CSA)

ADV_B Invalid to CSx_B

Invalid (ADVL is asserted)

WE7 - WE15 - CSN

—

—

3 + (ADVA - CSA)

3 - CSN ns ns ns WE40A

(muxed

A/D)

CSx_B Valid to ADV_B Invalid WE14 - WE6 + (ADVN + ADVA

+ 1 - CSA)

-3 + (ADVN +

ADVA + 1 - CSA)

3 + (ADVN + ADVA +

1 - CSA)

WE41 WE16 - WE6 - WCSA — 3 - WCSA

WE41A

(muxed

A/D)

CSx_B Valid to Output Data

Valid

CSx_B Valid to Output Data

Valid

WE16 - WE6 + (WADVN +

WADVA + ADH + 1 - WCSA)

WE17 - WE7 - CSN

—

—

3 + (WADVN +

WADVA + ADH + 1 -

WCSA)

3 - CSN WE42 Output Data Invalid to CSx_B

Invalid

MAXCO Output max. delay from internal driving ADDR/control FFs to chip outputs.

10 — —

MAXCS

O

Output max. delay from CSx internal driving FFs to CSx out.

MAXDI DATA MAXIMUM delay from chip input data to its internal FF

10

5

—

—

—

— ns ns ns ns

62 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Electrical Characteristics

Table 54. WEIM Asynchronous Timing Parameters Table Relative Chip Select

Ref No.

Parameter

Determination by

Synchronous measured parameters

12

Min

Max

(If 133 MHz is supported by SOC)

Unit

WE43 Input Data Valid to CSx_B

Invalid

MAXCO - MAXCSO + MAXDI MAXCO

-

MAXCSO +

MAXDI

0

— ns

WE44 CSx_B Invalid to Input Data invalid

0

WE45 CSx_B Valid to BEy_B Valid

(Write access)

WE12 - WE6 + (WBEA - CSA)

WE46 BEy_B Invalid to CSx_B Invalid

(Write access)

WE7 - WE13 + (WBEN - CSN)

—

—

—

3 + (WBEA - CSA)

-3 + (WBEN - CSN)

MAXDTI DTACK MAXIMUM delay from chip dtack input to its internal

FF + 2 cycles for synchronization

WE47 Dtack Active to CSx_B Invalid MAXCO - MAXCSO + MAXDTI

— —

MAXCO -

MAXCSO +

MAXDTI

—

WE48 CSx_B Invalid to Dtack invalid 0 0 —

1

2

3

4

5

6

7

Parameters WE4... WE21 value see column BCD = 0 in

Table 53 .

All config. parameters (CSA,CSN,WBEA,WBEN,ADVA,ADVN,OEN,OEA,RBEA & RBEN) are in cycle units.

CS Assertion. This bit field determines when CS signal is asserted during read/write cycles.

CS Negation. This bit field determines when CS signal is negated during read/write cycles.

t is axi_clk cycle time.

BE Assertion. This bit field determines when BE signal is asserted during read cycles.

BE Negation. This bit field determines when BE signal is negated during read cycles.

ns ns ns

— ns ns

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

63

Electrical Characteristics

4.6.8

SDRAM Controller Timing Parameters

4.6.8.1

Mobile DDR SDRAM Timing Parameters

Figure 32

shows the basic timing parameters for mobile DDR (mDDR) SDRAM. The timing parameters for this diagram is shown in

Table 55

.

DD1

SDCLK

SDCLK

DD4 DD3

DD2

CS

DD5

RAS

DD5

DD4

CAS

DD4

DD5

DD5

WE

DD6

ADDR

ROW/BA

DD7

COL/BA

Figure 32. mDDR SDRAM Basic Timing Parameters

Table 55. mDDR SDRAM Timing Parameter Table

200 MHz 166 MHz 133 MHz

ID Parameter Symbol Unit

Min Max Min Max Min Max

DD1

DD2

SDRAM clock high-level width

SDRAM clock low-level width t t

CH

CL

0.45

0.45

0.55

0.55

0.45

0.45

0.55

0.55

0.45

0.45

0.55

0.55

t t CK

CK

DD3

DD4

DD5

SDRAM clock cycle time

CS, RAS, CAS, CKE, WE setup time

CS, RAS, CAS, CKE, WE hold time t CK t IS

1 t IH

1 t IS

1

5

0.9

0.9

—

—

—

6

1.1

1.1

—

—

—

7.5

1.3

1.3

—

—

— ns ns ns

DD6 Address output setup time 0.9

— 1.1

— 1.3

— ns

DD7 Address output hold time t IH

1

0.9

— 1.1

— 1.3

— ns

1

This parameter is affected by pad timing. if the slew rate is < 1 V/ns, 0.2 ns should be added to the value. For cmos65 pads this is true for medium and low drive strengths.

64 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Electrical Characteristics

Figure 33

shows the timing diagram for mDDR SDRAM write cycle. The timing parameters for this

diagram is shown in Table 56

.

SDCLK

SDCLK_B

DQS (output)

DD21

DD17

Data

DD18

Data

DD19

DD22

DD23

DD17

Data Data

DD18

Data Data

DD20

Data Data DQ (output)

DQM (output)

DD17

DM

DM

DD18

DM

DD17

DM DM

DD18

DM DM DM

Figure 33. mDDR SDRAM Write cycle Timing Diagram

Table 56. mDDR SDRAM Write Cycle Parameter Table

1

200 MHz

2

166 MHz 133 MHz

ID Parameter Symbol Unit

Min Max Min Max Min Max

DD17 DQ and DQM setup time to DQS

DD18 DQ and DQM hold time to DQS

DD19 Write cycle DQS falling edge to

SDCLK output setup time

DD20 Write cycle DQS falling edge to

SDCLK output hold time t t t DS t DH

3

1

DSS

DSH

0.48

0.48

0.2

0.2

—

—

—

—

0.6

0.6

0.2

0.2

—

—

—

—

0.8

0.8

0.2

0.2

—

—

—

— ns ns tCK tCK

DD21 Write command to first DQS latching transition

DD22 DQS high level width t

DQSS

0.75

1.25

0.75

1.25

0.75

1.25

tCK t DQSH 0.4

0.6

0.4

0.6

0.4

0.6

tCK

DD23 DQS low level width t DQSL 0.4

0.6

0.4

0.6

0.4

0.6

tCK

1

2

3

Test conditions are: Capacitance 15 pF for DDR PADS. Recommended drive strengths is medium for SDCLK and high for address and controls.

SDRAM CLK and DQS related parameters are being measured from the 50% point. that is, high is defined as 50% of signal value and low is defined as 50% as signal value. DDR SDRAM CLK parameters are measured at the crossing point of SDCLK and SDCLK (inverted clock).

This parameter is affected by pad timing. If the slew rate is < 1 V/ns, 0.1 ns should be increased to this value.

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

65

Electrical Characteristics

Figure 34

shows the timing diagram for mDDR SDRAM DQ versus DQS and SDCLK read cycle. The timing parameters for this diagram is shown in

Table 57

.

SDCLK

SDCLK_B

DQS (input)

DD26

DD24

Data

DD25

Data Data Data Data Data Data Data

DQ (input)

Figure 34. mDDR SDRAM DQ vs. DQS and SDCLK READ Cycle Timing Diagram

Table 57. mDDR SDRAM Read Cycle Parameter Table

1

ID PARAMETER Symbol

200 MHz

2

166 MHz 133 MHz

Min Max Min Max Min Max

Unit

DD24 DQS - DQ Skew (defines the Data valid window in read cycles related to DQS)

DD25 DQS DQ in HOLD time from DQS t

DQSQ

— 0.4

— 0.75

— 0.85

ns t QH 1.75

— 2.05

— 2.6

— ns

DD26 DQS output access time from SDCLK posedge t DQSCK 2 5 2 5.5

2 6.5

ns

1

2

Test conditions are: Capacitance 15 pF for DDR PADS. Recommended drive strengths is medium for SDCLK and high for address and controls

SDRAM CLK and DQS related parameters are being measured from the 50% point. that is, high is defined as 50% of signal value and low is defined as 50% as signal value. DDR SDRAM CLK parameters are measured at the crossing point of SDCLK and SDCLK (inverted clock)

66 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Electrical Characteristics

4.6.9

DDR2 SDRAM Specific Parameters

Figure 35

shows the timing parameters for DDR2. The timing parameters for this diagram appear in

Table 58 .

DDR1

SDCLK

SDCLK

DDR4

CS

DDR5

RAS

DDR5

DDR4

CAS

DDR4

DDR5

DDR5

WE

ODT/CKE

DDR6

ADDR

ROW/BA

DDR7

COL/BA

DDR4

DDR3

DDR2

Figure 35. DDR2 SDRAM Basic Timing Parameters

ID

Table 58. DDR2 SDRAM Timing Parameter Table

SDCLK = 200 MHz

Parameter Symbol

DDR1 SDRAM clock high-level width

DDR2 SDRAM clock low-level width

DDR3 SDRAM clock cycle time

DDR4 CS, RAS, CAS, CKE, WE, ODT setup time

DDR5 CS, RAS, CAS, CKE, WE, ODT hold time t CH t CL t CK t IS

1 t

IH

1

Min

0.45

0.45

5

1.5

1.7

Max

0.55

0.55

—

—

—

Unit t CK t CK ns ns ns

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

67

Electrical Characteristics

Table 58. DDR2 SDRAM Timing Parameter Table (continued)

SDCLK = 200 MHz

ID Parameter Symbol Unit

Min Max

DDR6 Address output setup time t

IS

1

1.7

— ns

DDR7 Address output hold time t

IH

1

1.5

— ns

1

These values are for command/address slew rates of 1 V/ns and SDCLK / SDCLK_B differential slew rate of 2 V/ns. For different values use the settings shown in

Table 59

.

0.4

0.3

0.25

0.2

0.8

0.7

0.6

0.5

0.15

0.1

2.0

1.5

1.0

0.9

4.0

3.5

3.0

2.5

Command /

Address

Slew Rate

(V/ns)

NOTE

Measurements are taken from Vref to Vref (cross-point to cross-point), but

JEDEC timings for single-ended signals are defined from Vref to Vil(ac) max or to Vih(ac) min.

Table 59. Derating Values for DDR2-400 (SDCLK = 200 MHz)

SDCLK Differential Slew Rates

1,2

Δ tlS

+187

–43

–67

–110

–175

–285

–350

–525

–800

–1450

+83

+0

–11

–25

+179

+167

+150

+125

2.0 V/ns

Δ tlH

+94

–54

–83

–125

–188

–292

–375

–500

–708

–1125

+21

+0

–14

–31

+89

+83

+75

+45

Δ tlS

+217

–13

–37

–80

–145

–255

–320

–495

–770

–1420

+209

+197

+180

+155

+113

+30

+19

+5

1.5 V/ns

Δ tlH

+124

–24

–53

–95

–158

–262

–345

–470

–678

–1095

+51

+30

+16

–1

+119

+113

+105

+75

1.0 V/ns

Δ tlH

+154

+6

–23

–65

–128

–232

–315

–440

–648

–1065

+81

+60

+46

+29

+149

+143

+135

+105

Δ tlS

+247

+17

–7

–50

–115

–225

–290

–465

–740

–1390

+239

+227

+210

+185

+143

+60

+49

+35

Unit ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps

68 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Electrical Characteristics

1

2

Test conditions are: Capacitance 15 pF for DDR contacts. Recommended drive strengths: Medium for SDCLK and High for address and controls.

SDCLK and DQS related parameters are measured from the 50% point. For example, a high is defined as 50% of the signal value and a low is defined as 50% of the signal value. DDR SDRAM CLK parameters are measured at the crossing point of

SDCLK and SDCLK_B.

Figure 36

shows the timing diagram for DDR2 SDRM write cycle. The timing parameters for this diagram appear in

Table 60 .

SDCLK

SDCLK_B

DQS (output)

DQ (output)

DQM (output)

DDR20

DDR21 DDR22

DDR23

DDR17

Data

DDR18

Data

DDR17

Data Data

DDR18

Data Data

DDR19

Data Data

DDR17

DM

DM

DDR18

DM

DDR17

DM DM

DDR18

DM DM DM

Figure 36. DDR2 SDRAM Write Cycle Timing Diagram

Table 60. DDR2 SDRAM Write Cycle Parameter Table

SDCLK = 200 MHz

ID Parameter Symbol Unit

DDR17 DQ & DQM setup time to DQS

DDR18 DQ & DQM hold time to DQS

DDR19 DQS falling edge to SDCLK output setup time

DDR20 DQS falling edge SDCLK output hold time t DS t DH t DSS t DSH

Min

0.8

1

0.8

2

1.6

2.4

Max

—

—

—

—

DDR21 DQS latching rising transitions to associated clock edges

DDR22 DQS high level width t t DQSS

DQSH

-0.7

0.35

0.3

— ns tCK

DDR23 DQS low level width t DQSL 0.35

— tCK

1

2

- In order to meet these setup/hold values, write calibration should be performed to place the DQS in the middle of DQ window. The minimum window width is 1.6ns (DDR17+DDR18).

- From DDR controller perspective, the timing is the same for both differential and single ended mode.

- In order to meet these setup/hold values, write calibration should be performed to place the DQS in the middle of DQ window. The minimum window width is 1.6ns (DDR17+DDR18).

- From DDR controller perspective, the timing is the same for both differential and single ended mode.

ns ns ns ns

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

69

Electrical Characteristics

NOTE

Measurements are taken from Vref to Vref (cross-point to cross-point), but

JEDEC timings for single-ended signals are defined from Vref to Vil(ac) max or to Vih(ac) min.

Table 61. Derating values for DDR2 Differential DQS

1

,

2

Table 62. Derating values for DDR2 Single Ended DQS

3

,

4

1. Test conditions are: Capacitance 15 pF for DDR PADS. Recommended drive strengths is medium for SDCLK and high for address and controls.

2. SDRAM CLK and DQS related parameters are being measured from the 50% point. that is, high is defined as 50% of signal value and low is defined as 50% as signal value. DDR SDRAM CLK parameters are measured at the crossing point of SDCLK and SDCLK (inverted clock).

3. Test conditions are: Capacitance 15 pF for DDR PADS. Recommended drive strengths is medium for SDCLK and high for address and controls.

4. SDRAM CLK and DQS related parameters are being measured from the 50% point. that is, high is defined as 50% of signal value and low is defined as 50% as signal value. DDR SDRAM CLK parameters are measured at the crossing point of SDCLK and SDCLK (inverted clock).

70 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Electrical Characteristics

Figure 37

shows the timing diagram for DDR2 SDRM read cycle. The timing parameters for this diagram appear in

Table 63 .

SDCLK

SDCLK_B

DQS (input)

DDR24

DDR25

DQ (input)

DATA DATA DATA DATA DATA DATA DATA DATA

Figure 37. DDR2 SDRAM DQ versus DQS and SDCLK Read Cycle Timing Diagram

Table 63. DDR2 SDRAM Read Cycle Parameter Table

SDCLK = 200 MHz

ID Parameter Symbol Unit

Min Max

DDR24

1

DQS—DQ Skew (defines the Data valid window during read cycles related to DQS).

t DQSQ — 0.5

DDR25

2

DQ HOLD time from DQS t QH 1.8

—

1

2

The actual timing may vary depending on read calibration settings. What is actually important for the controller is

DDR25-DDR24 which results in the minimum required DQ valid window width: 1.8ns-0.5ns = 1.3ns of minimum width.

The actual timing may vary depending on read calibration settings. What is actually important for the controller is

DDR25-DDR24 which results in the minimum required DQ valid window width: 1.8ns-0.5ns = 1.3ns of minimum width.

ns ns

NOTE

It is recommended to perform read calibration process in order to achieve the best performance.

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

71

Electrical Characteristics

4.7

External Peripheral Interfaces

The following sections provide information on external peripheral interfaces.

4.7.1

CSPI Timing Parameters

This section describes the timing parameters of the CSPI. The CSPI has separate timing parameters for master and slave modes. The nomenclature used with the CSPI modules and the respective routing of these signals is shown in

Table 64 .

Table 64. CSPI Nomenclature and Routing

Module I/O Access

CSPI1

1

, USBH1, and DI1 via IOMUX eCSPI1 eCSPI2 NANDF and USBH1 via IOMUX

CSPI NANDF, USBH1, SD1, SD2, and GPIO via IOMUX

1

This set of BGA contacts is labeled CSPI, but is actually an eCSPI channel

4.7.1.1

CSPI Master Mode Timing

Figure 38

depicts the timing of CSPI in Master mode and

Table 65

lists the CSPI Master Mode timing characteristics.

RDY

SSx

SCLK

MOSI

MISO

CS10

CS8

CS1

CS7

CS3

CS3

CS9

CS2

CS2 CS6

CS4

CS5

72

ID

CS1

CS2

CS3

CS4

Figure 38. CSPI Master Mode Timing Diagram

Table 65. CSPI Master Mode Timing Parameters

Parameter

SCLK Cycle Time

SCLK High or Low Time

SCLK Rise or Fall

1

SSx pulse width

Symbol t clk t

SW t

RISE/FALL t

CSLH

Min

60

26

—

26

Max

—

—

—

—

Unit ns ns ns ns i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Electrical Characteristics

Table 65. CSPI Master Mode Timing Parameters (continued)

ID Parameter Symbol Min

CS5 SSx Lead Time (Slave Select setup time) t

SCS

26

CS6

CS7

SSx Lag Time (SS hold time)

MOSI Propagation Delay

(C

LOAD

= 20 pF)

MISO Setup Time t t

HCS

PDmosi

26

–1

CS8 t

Smiso

5

CS9 MISO Hold Time t

Hmiso

5

CS10 RDY to SSx Time

2 t

SDRY

5

1

2

See specific I/O AC parameters

Section 4.5, “I/O AC Parameters

”

SPI_RDY is sampled internally by ipg_clk and is asynchronous to all other CSPI signals.

Max

—

—

21

—

—

—

Unit ns ns ns ns ns ns

4.7.1.2

CSPI Slave Mode Timing

Figure 39

depicts the timing of CSPI in Slave mode.

Table 66 lists the CSPI Slave Mode timing

characteristics.

SSx

SCLK

MISO

CS1

CS9

CS2

CS2 CS6

CS4

CS5

CS7

CS8

MOSI

ID

CS1

CS2

CS4

CS5

CS6

CS7

Figure 39. CSPI Slave Mode Timing Diagram

Table 66. CSPI Slave Mode Timing Parameters

Parameter

SCLK Cycle Time

SCLK High or Low Time

SSx pulse width

SSx Lead Time (SS setup time)

SSx Lag Time (SS hold time)

MOSI Setup Time

Symbol t clk t

SW t

CSLH t

SCS t

HCS t

Smosi

Min

60

26

26

26

26

5

Max

—

—

—

—

—

—

Unit ns ns ns ns ns ns

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

73

Electrical Characteristics

ID

CS8

CS9

Table 66. CSPI Slave Mode Timing Parameters (continued)

Parameter

MOSI Hold Time

MISO Propagation Delay (C

LOAD

= 20 pF)

Symbol t

Hmosi t

PDmiso

Min

5

0

Max

—

35

Unit ns ns

4.7.2

eCSPI Timing Parameters

This section describes the timing parameters of the eCSPI. The eCSPI has separate timing parameters for master and slave modes. The nomenclature used with the CSPI modules and the respective routing of these

signals is shown in Table 64

.

4.7.2.1

eCSPI Master Mode Timing

Figure 40 depicts the timing of eCSPI in Master mode and Table 67

lists the eCSPI Master Mode timing characteristics.

eCSPIx_DRYN1

CS11 eCSPIx_CS_x eCSPIx_CLK

CS7 CS8

CS1

CS3 eCSPIx_DO

CS3

CS9 CS10 eCSPIx_DI

CS2

CS2 CS6

CS4

CS5

74

ID

CS1

CS2

CS3

CS4

CS5

CS6

CS7

Figure 40. eCSPI Master Mode Timing Diagram

Table 67. eCSPI Master Mode Timing Parameters

Parameter eCSPIx_CLK Cycle Time–Read eCSPIx_CLK Cycle Time–Write eCSPIx_CLK High or Low Time eCSPIx_CLK Rise or Fall eCSPIx_CS_x pulse width eCSPIx_CS_x Lead Time (CS setup time) eCSPIx_CS_x Lag Time (CS hold time) eCSPIx_DO Setup Time

Symbol t clk t

SW t

RISE/FALL t

CSLH t

SCS t

HCS t

Smosi

Min

5

5

15

5

60

15

6

—

Max

—

—

—

—

—

—

— i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Unit ns ns ns ns ns ns ns

ID

CS8

CS9

CS10

CS11

Table 67. eCSPI Master Mode Timing Parameters (continued)

Parameter eCSPIx_DO Hold Time eCSPIx_DI Setup Time eCSPIx_DI Hold Time eCSPIx_DRYN Setup Time

Symbol t

Hmosi t

Smiso t

Hmiso t

SDRY

Min

5

5

5

5

Electrical Characteristics

Max

—

—

—

—

Unit ns ns ns ns

4.7.2.2

eCSPI Slave Mode Timing

Figure 41 depicts the timing of eCSPI in Slave mode and Table 68 lists the eCSPI Slave Mode timing

characteristics.

eCSPIx_CS_x eCSPIx_CLK eCSPIx_DI

CS1

CS9CS10

CS3

CS3

CS7 CS8 eCSPIx_DO

CS2

CS2 CS6

CS4

CS5

ID

CS1

CS2

CS3

CS4

CS5

CS6

CS7

CS8

CS9

CS10

Figure 41. eCSPI Slave Mode Timing Diagram

Table 68. eCSPI Slave Mode Timing Parameters

Parameter eCSPIx_CLK Cycle Time–Read eCSPIx_CLK Cycle Time–Write eCSPIx_CLK High or Low Time eCSPIx_CLK Rise or Fall eCSPIx_CS_x pulse width eCSPIx_CS_x Lead Time (CS setup time) eCSPIx_CS_x Lag Time (CS hold time) eCSPIx_DO Setup Time eCSPIx_DO Hold Time eCSPIx_DI Setup Time eCSPIx_DI Hold Time

Symbol t clk t

SW t

RISE/FALL t

CSLH t

SCS t

HCS t

Smosi t

Hmosi t

Smiso t

Hmiso

Min

5

5

15

5

60

15

6

—

5

5

5

Max

—

—

—

—

—

—

—

—

—

—

Unit ns ns ns ns ns ns ns ns ns ns

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

75

Electrical Characteristics

4.7.3

eSDHCv2 Timing Parameters

This section describes the electrical information of the eSDHCv2.

Figure 42 depicts the timing of eSDHCv2, and Table 69

lists the eSDHCv2 timing characteristics.

SD2

SD5

SD4

SD1

MMCx_CLK

SD3

MMCx_CMD

MMCx_DAT_0

MMCx_DAT_1 output from eSDHCv2 to card

MMCx_DAT_7

SD6

SD7 SD8

MMCx_CMD

MMCx_DAT_0

......

MMCx_DAT_3

Figure 42. eSDHCv2 Timing

Table 69. eSDHCv2 Interface Timing Specification

Parameter Symbols Min ID

Card Input Clock

SD1

SD2

SD3

SD4

SD5

Clock Frequency (Low Speed)

Clock Frequency (SD/SDIO Full Speed/High Speed)

Clock Frequency (MMC Full Speed/High Speed)

Clock Frequency (Identification Mode)

Clock Low Time

Clock High Time

Clock Rise Time

Clock Fall Time f

PP

1 f

PP

2 f

PP

3 f

OD t

WL t

WH t

TLH t

THL eSDHC Output/Card Inputs CMD, DAT (Reference to CLK)

0

0

0

100

7

7

—

—

SD6

4 eSDHC Output Delay eSDHC Input / Card Outputs CMD, DAT (Reference to CLK) t

OD

–3

Max

3

3

—

—

400

25/50

20/52

400

3

Unit ns ns ns ns ns kHz

MHz

MHz kHz

76 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Electrical Characteristics

Table 69. eSDHCv2 Interface Timing Specification (continued)

ID Parameter Symbols Min Max Unit

SD7 eSDHC Input Setup Time

SD8 eSDHC Input Hold Time t

ISU t

IH

5

2.5

2.5

—

— ns ns

1

2

3

4

5

In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V.

In normal speed mode for SD/SDIO card, clock frequency can be any value between 0

–

25 MHz. In high-speed mode, clock frequency can be any value between 0

–

50 MHz.

In normal speed mode for MMC card, clock frequency can be any value between 0

–

20 MHz. In high-speed mode, clock frequency can be any value between 0

–

52 MHz.

Measurement taken with CLoad = 20 pF

To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns.

4.7.4

FEC AC Timing Parameters

This section describes the electrical information of the Fast Ethernet Controller (FEC) module. The FEC is designed to support both 10 and 100 Mbps Ethernet/IEEE 802.3 networks. An external transceiver interface and transceiver function are required to complete the interface to the media. The FEC supports the 10/100 Mbps MII (18 pins in total) and the 10 Mbps-only 7-wire interface, which uses 7 of the MII pins, for connection to an external Ethernet transceiver. For the pin list of MII and 7-wire, see i.MX51

Multimedia Applications Processor Reference Manual (MCIMX51RM).

This section describes the AC timing specifications of the FEC.

4.7.4.1

MII Receive Signal Timing

The MII receive signal timing involves the FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER, and

FEC_RX_CLK signals. The receiver functions correctly up to a FEC_RX_CLK maximum frequency of

25 MHz + 1%. There is no minimum frequency requirement but the processor clock frequency must

exceed twice the FEC_RX_CLK frequency. Table 70 lists the MII receive channel signal timing

parameters and

Figure 43

shows MII receive signal timings.

.

Table 70. MII Receive Signal Timing

Num Characteristic

1

Min Max Unit

M1

M2

FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER to FEC_RX_CLK setup

FEC_RX_CLK to FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER hold

5

5

—

— ns ns

M3 FEC_RX_CLK pulse width high 35% 65% FEC_RX_CLK period

M4 FEC_RX_CLK pulse width low 35% 65%

1

FEC_RX_DV, FEC_RX_CLK, and FEC_RXD0 have same timing in 10 Mbps 7-wire interface mode.

FEC_RX_CLK period

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

77

Electrical Characteristics

M3

FEC_RX_CLK (input)

M4

FEC_RXD[3:0] (inputs)

FEC_RX_DV

FEC_RX_ER

M1 M2

Figure 43. MII Receive Signal Timing Diagram

4.7.4.2

MII Transmit Signal Timing

The MII transmit signal timing affects the FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER, and

FEC_TX_CLK signals. The transmitter functions correctly up to a FEC_TX_CLK maximum frequency of 25 MHz + 1%. There is no minimum frequency requirement. In addition, the processor clock frequency must exceed twice the FEC_TX_CLK frequency.

Table 71

lists MII transmit channel timing parameters and

Figure 44 shows MII transmit signal timing diagram for the values listed in Table 71 .

Table 71. MII Transmit Signal Timing

Num Characteristic

1

Min Max Unit

M5

M6

FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER invalid

FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER valid

5

—

—

20 ns ns

M7 FEC_TX_CLK pulse width high 35% 65% FEC_TX_CLK period

M8 FEC_TX_CLK pulse width low 35% 65% FEC_TX_CLK period

1

FEC_TX_EN, FEC_TX_CLK, and FEC_TXD0 have the same timing in 10 Mbps 7-wire interface mode.

.

M7

FEC_TX_CLK (input)

M5

M8

FEC_TXD[3:0] (outputs)

FEC_TX_EN

FEC_TX_ER

M6

Figure 44. MII Transmit Signal Timing Diagram

78 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Electrical Characteristics

4.7.4.3

MII Async Inputs Signal Timing (FEC_CRS and FEC_COL)

Table 72

lists MII asynchronous inputs signal timing information.

Figure 45

shows MII asynchronous input timings listed in

Table 72

.

Table 72. MII Async Inputs Signal Timing

Num Characteristic

M9

1

FEC_CRS to FEC_COL minimum pulse width

1

FEC_COL has the same timing in 10 Mbit 7-wire interface mode.

Min

1.5

Max

—

Unit

FEC_TX_CLK period

.

FEC_CRS, FEC_COL

M9

Figure 45. MII Async Inputs Timing Diagram

4.7.4.4

MII Serial Management Channel Timing (FEC_MDIO and FEC_MDC)

Table 73 lists MII serial management channel timings.

Figure 46

shows MII serial management channel timings listed in

Table 73 . The MDC frequency should be equal to or less than 2.5 MHz to be compliant

with the IEEE 802.3 MII specification. However the FEC can function correctly with a maximum MDC frequency of 15 MHz.

Table 73. MII Transmit Signal Timing

ID Characteristic

M10 FEC_MDC falling edge to FEC_MDIO output invalid (minimum propagation delay)

M11 FEC_MDC falling edge to FEC_MDIO output valid (max propagation delay)

M12 FEC_MDIO (input) to FEC_MDC rising edge setup

M13 FEC_MDIO (input) to FEC_MDC rising edge hold

M14 FEC_MDC pulse width high

M15 FEC_MDC pulse width low

Min Max Unit

0

—

—

5

18 —

0 — ns ns ns ns

40% 60% FEC_MDC period

40% 60% FEC_MDC period

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

79

Electrical Characteristics

M14

M15

FEC_MDC (output)

M10

FEC_MDIO (output)

80

M11

FEC_MDIO (input)

M12 M13

Figure 46. MII Serial Management Channel Timing Diagram

4.7.5

Frequency Pre-Multiplier (FPM) Electrical Parameters (CKIL)

The FPM is a DPLL that converts a signal operating in the kilohertz region into a clock signal operating in the megahertz region. The output of the FPM provides the reference frequency for the on-chip DPLLs.

Parameters of the FPM are listed in Table 74 .

Table 74. FPM Specifications

Parameter Min Typ Max Unit

Reference clock frequency range—CKIL

FPM output clock frequency range

32

8

32.768

—

256

33 kHz

MHz

FPM multiplication factor (test condition is changed by a factor of 2)

Lock-in time

1

128

—

—

—

1024

312.5

—

µ s

Cycle-to-cycle frequency jitter (peak to peak) — 8 20 ns

1 plrf = 1 cycle assumed missed + x cycles for reset deassert + y cycles for calibration and lock x[ts] = {2,3,5,9}; y[ts] = {7,8,10,14}; where ts is the chosen time scale of the reference clock. In this case reference clock = 32 kHz which makes ts = 0, therefore total time required for achieving lock is 10(1+2+7) cycles or 312.5 µ s.

4.7.6

High-Speed I

2

C (HS-I

2

C) Timing Parameters

This section describes the timing parameters of the HS-I

2

C module. This module can operate in the following modes: Standard, Fast and High speed.

NOTE

See the errata for the HS-I

2

C module in the i.MX51 Chip Errata. There are two standard I

2

C modules that have no errata.

i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Electrical Characteristics

4.7.6.1

Standard and Fast Mode Timing Parameters

Figure 47

depicts the standard and fast mode timings of HS-I

2

C module, and

Table 75

lists the timing characteristics.

IC10

IC11

IC9

SDAH

SCLH

IC2

IC8

IC4 IC7 IC3

START IC10

IC6

IC1

IC5

IC11 START STOP

Figure 47. HS-I

2

C Standard and Fast Mode Bus Timing

Table 75. HS-I

2

C Timing Parameters—Standard and Fast Mode

START

Standard Mode Fast Mode

ID Parameter Unit

Min Max Min Max

IC1 SCLH cycle time

IC2 Hold time (repeated) START condition

IC3 Set-up time for STOP condition

IC4 Data hold time

IC5 HIGH Period of SCLH Clock

IC6 LOW Period of the SCLH Clock

10

4.0

4.0

0

1

4.0

4.7

—

—

—

3.45

2

—

—

2.5

0.6

0.6

0

1

0.6

1.3

—

—

—

0.9

2

—

—

IC7 Set-up time for a repeated START condition

IC8 Data set-up time

4.7

250

—

—

0.6

100

3

—

— ns

IC9

IC10

IC11

Bus free time between a STOP and START condition

Rise time of both SDAH and SCLH signals

Fall time of both SDAH and SCLH signals

4.7

—

—

—

1000

300

1.3

20+0.1C

b

4

20+0.1C

b

4

—

300

300

µ s ns ns

IC12 Capacitive load for each bus line (C b

) — 100 — 100 pF

1

2

3

A device must internally provide a hold time of at least 300 ns for SDAH signal in order to bridge the undefined region of the falling edge of SCLH.

The maximum hold time has only to be met if the device does not stretch the LOW period (ID no IC6) of the SCLH signal

A Fast-mode I

2

C-bus device can be used in a Standard-mode I

2

C-bus system, but the requirement of Set-up time (ID No IC8) of 250 ns must then be met. This automatically is the case if the device does not stretch the LOW period of the SCLH signal.

If such a device does stretch the LOW period of the SCLH signal, it must output the next data bit to the SDAH line max_rise_time

(ID No IC10) + data_setup_time (ID No IC8) = 1000 + 250 = 1250 ns (according to the Standard-mode I

2

C-bus specification) before the SCLH line is released.

4

C b

= total capacitance of one bus line in pF.

µ s

µ s

µ s

µ s

µ s

µ s

µ s

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

81

Electrical Characteristics

4.7.6.2

High-Speed Mode Timing Parameters

Figure 48

depicts the high-speed mode timings of HS-I

2

C module, and Table 76

lists the timing characteristics.

IC11

IC12

SDAH

IC3

IC6

IC7 IC2

SCLH IC13

START IC9

IC4

IC10 START

IC1

IC5 IC8

Figure 48. High-Speed Mode Timing

Table 76. HS-I

2

C High-Speed Mode Timing Parameters

STOP START

ID Parameter

High-Speed Mode

Unit

Min Max

IC1 SCLH cycle time

IC2 Setup time (repeated) START condition

IC3 Hold time (repeated) START condition

IC4 LOW Period of the SCLH Clock

10

160

160

160

3.4

—

—

—

MHz ns ns ns

IC5 HIGH Period of SCLH Clock

IC6

IC8

IC10

IC12

Data set-up time

IC7 Data hold time

Rise time of SCLH

IC9 Rise time of SCLH signal after a repeated START condition and after an acknowledge bit

Fall time of SCLH signal

IC11 Rise time of SDAH signal

Fall time of SDAH signal

IC13 Set-up time for STOP condition

60

10

0

1

10

10

10

10

10

160

—

—

70

40

80

40

80

80

— ns ns ns ns ns ns ns ns ns

IC14 Capacitive load for each bus line (C b

) — 100 pF

1

A device must internally provide a hold time of at least 300 ns for SDAH signal in order to bridge the undefined region of the falling edge of SCLH.

82 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Electrical Characteristics

4.7.7

I

2

C Module Timing Parameters

This section describes the timing parameters of the I

2

C Module. Figure 49 depicts the timing of I

2 module, and

Table 77 lists the I

2

C Module timing characteristics.

C

IC8

IC10

IC4

IC11

IC7

IC3

IC9

I2DAT

I2CLK

IC2

START IC10

IC6

IC11 START

IC1

IC5

Figure 49. I

2

C Bus Timing

Table 77. I

2

C Module Timing Parameters

Parameter

STOP START

Standard Mode

Supply Voltage =

1.65 V–1.95 V, 2.7 V–3.3 V

Fast Mode

Supply Voltage =

2.7 V–3.3 V Unit ID

Min Max Min Max

IC1

IC2

IC3

IC4

IC5

IC6

I2CLK cycle time

Hold time (repeated) START condition

Set-up time for STOP condition

Data hold time

HIGH Period of I2CLK Clock

LOW Period of the I2CLK Clock

10

4.0

4.0

0

1

4.0

4.7

—

—

—

3.45

2

—

—

2.5

0.6

0.6

0

1

0.6

1.3

—

—

—

0.9

2

—

—

IC7

IC8

Set-up time for a repeated START condition

Data set-up time

4.7

250

—

—

0.6

100

3

—

— ns

IC9

IC10

IC11

Bus free time between a STOP and START condition

Rise time of both I2DAT and I2CLK signals

Fall time of both I2DAT and I2CLK signals

4.7

—

—

—

1000

300

1.3

20 + 0.1C

b

4

20 + 0.1C

b

4

—

300

300

µ s ns ns

IC12 Capacitive load for each bus line (C b

) — 400 — 400 pF

2

3

1

4

A device must internally provide a hold time of at least 300 ns for I2DAT signal in order to bridge the undefined region of the falling edge of I2CLK.

The maximum hold time has only to be met if the device does not stretch the LOW period (ID no IC5) of the I2CLK signal

A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement of Set-up time (ID No IC7) of 250 ns must be met. This automatically is the case if the device does not stretch the LOW period of the I2CLK signal.

If such a device does stretch the LOW period of the I2CLK signal, it must output the next data bit to the I2DAT line max_rise_time (IC9) + data_setup_time (IC7) = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the I2CLK line is released.

C b

= total capacitance of one bus line in pF.

µ s

µ s

µ s

µ s

µ s

µ s

µ s

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

83

Electrical Characteristics

4.7.8

Image Processing Unit (IPU) Module Parameters

The purpose of the IPU is to provide comprehensive support for the flow of data from an image sensor and/or to a display device. This support covers all aspects of these activities:

• Connectivity to relevant devices

— cameras, displays, graphics accelerators, and TV encoders.

• Related image processing and manipulation: display processing, image conversions, and other related functions.

• Synchronization and control capabilities such as avoidance of tearing artifacts.

4.7.8.1

Sensor Interface Timings

There are three camera timing modes supported by the IPU.

4.7.8.1.1

BT.656 and BT.1120 Video Mode

Smart camera sensors, which include imaging processing, usually support video mode transfer. They use an embedded timing syntax to replace the SENSB_VSYNC and SENSB_HSYNC signals. The timing syntax is defined by the BT.656/BT.1120 standards.

This operation mode follows the recommendations of ITU BT.656/ ITU BT.1120 specifications. The only control signal used is SENSB_PIX_CLK. Start-of-frame and active-line signals are embedded in the data stream. An active line starts with a SAV code and ends with a EAV code. In some cases, digital blanking is inserted in between EAV and SAV code. The CSI decodes and filters out the timing-coding from the data stream, thus recovering SENSB_VSYNC and SENSB_HSYNC signals for internal use. On BT.656 one component per cycle is received over the SENSB_DATA bus. On BT.1120 two components per cycle are received over the SENSB_DATA bus.

4.7.8.1.2

Gated Clock Mode

The SENSB_VSYNC, SENSB_HSYNC, and SENSB_PIX_CLK signals are used in this mode. See

Figure 50

.

Active Line

Start of Frame nth frame n+1th frame

SENSB_VSYNC

SENSB_HSYNC

SENSB_PIX_CLK

SENSB_DATA[19:0] invalid invalid

1st byte 1st byte

Figure 50. Gated Clock Mode Timing Diagram

84 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Electrical Characteristics

A frame starts with a rising edge on SENSB_VSYNC (all the timings correspond to straight polarity of the corresponding signals). Then SENSB_HSYNC goes to high and hold for the entire line. Pixel clock is valid as long as SENSB_HSYNC is high. Data is latched at the rising edge of the valid pixel clocks.

SENSB_HSYNC goes to low at the end of line. Pixel clocks then become invalid and the CSI stops receiving data from the stream. For next line the SENSB_HSYNC timing repeats. For next frame the

SENSB_VSYNC timing repeats.

4.7.8.1.3

Non-Gated Clock Mode

The timing is the same as the gated-clock mode (described in Section 4.7.8.1.2, “Gated Clock Mode”

),

except for the SENSB_HSYNC signal, which is not used. See Figure 51 . All incoming pixel clocks are

valid and cause data to be latched into the input FIFO. The SENSB_PIX_CLK signal is inactive (states low) until valid data is going to be transmitted over the bus.

Start of Frame nth frame n+1th frame

SENSB_VSYNC

SENSB_PIX_CLK

SENSB_DATA[19:0] invalid invalid

1st byte 1st byte

Figure 51. Non-Gated Clock Mode Timing Diagram

The timing described in

Figure 51 is that of a typical sensor. Some other sensors may have a slightly

different timing. The CSI can be programmed to support rising/falling-edge triggered SENSB_VSYNC; active-high/low SENSB_HSYNC; and rising/falling-edge triggered SENSB_PIX_CLK.

4.7.8.2

Electrical Characteristics

Figure 52

shows the sensor interface timing diagram. SENSB_PIX_CLK signal described here is not

generated by the IPU. Table 78

shows the timing characteristics for the diagram shown in Figure 52 .

SENSB_PIX_CLK

(Sensor Output)

SENSB_DATA,

SENSB_VSYNC,

SENSB_HSYNC

IP3 IP2 1/IP1

Figure 52. Sensor Interface Timing Diagram

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

85

Electrical Characteristics

ID

IP1

IP2

IP3

Table 78. Sensor Interface Timing Characteristics

Parameter

Sensor output (pixel) clock frequency

Data and control setup time

Data and control holdup time

Symbol

Fpck

Tsu

Thd

Min

0.01

3

2

Max

120

—

—

Unit

MHz ns ns

4.7.8.3

IPU Display Interface Signal Mapping

The IPU supports a number of display output video formats. Table 79

defines the mapping of the Display

Interface Pins used during various supported video interface formats.

86 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Electrical Characteristics

Table 79. Video Signal Cross-Reference i.MX51A

LCD

Port Name

(x=1,2)

RGB,

Signal

Name

(General)

RGB/TV Signal Allocation (Example)

16-bit

RGB

18-bit

RGB

24-bit

RGB

8-bit

YCrCb

2

16-bit

YCrCb

20-bit

YCrCb

Smart

Signal

Name

DISPx_DAT0

DISPx_DAT1

DISPx_DAT2

DISPx_DAT3

DISPx_DAT4

DISPx_DAT5

DISPx_DAT6

DAT[0]

DAT[1]

DAT[2]

DAT[3]

DAT[4]

DAT[5]

DAT[6]

B[0] B[0] B[0] Y/C[0] C[0]

B[1] B[1] B[1] Y/C[1] C[1]

B[2] B[2] B[2] Y/C[2] C[2]

B[3] B[3] B[3] Y/C[3] C[3]

B[4] B[4] B[4] Y/C[4] C[4]

G[0] B[5] B[5] Y/C[5] C[5]

G[1] G[0] B[6] Y/C[6] C[6]

DISPx_DAT7

DISPx_DAT8

DAT[7]

DAT[8]

G[2]

G[3]

G[1]

G[2]

B[7]

G[0]

DISPx_DAT9 DAT[9] G[4] G[3] G[1]

DISPx_DAT10 DAT[10] G[5] G[4] G[2]

Y/C[7]

—

—

—

C[7]

Y[0]

Y[1]

Y[2]

DISPx_DAT11 DAT[11] R[0] G[5] G[3]

DISPx_DAT12 DAT[12] R[1] R[0] G[4]

DISPx_DAT13 DAT[13] R[2] R[1] G[5]

DISPx_DAT14 DAT[14] R[3] R[2] G[6]

DISPx_DAT15 DAT[15] R[4] R[3] G[7]

—

—

—

—

—

Y[3]

Y[4]

Y[5]

Y[6]

Y[7]

DISPx_DAT16 DAT[16]

DISPx_DAT17 DAT[17]

DISPx_DAT18 DAT[18]

DISPx_DAT19 DAT[19]

DISPx_DAT20 DAT[20]

DISPx_DAT21 DAT[21]

—

—

—

—

—

—

R[4] R[0]

R[5] R[1]

—

—

R[2]

R[3]

—

—

R[4]

R[5]

—

—

—

—

—

—

—

—

—

—

—

—

Y[1]

Y[2]

Y[3]

Y[4]

Y[5]

C[7]

C[8]

C[9]

Y[0]

C[0]

C[1]

C[2]

C[3]

C[4]

C[5]

C[6]

Y[6]

Y[7]

Y[8]

Y[9]

—

—

Comment

1

—

—

—

—

—

—

DAT[0] The restrictions are as follows: a) There are maximal three

DAT[1]

DAT[2] continuous groups of bits that could be independently mapped to the external bus.

DAT[3] Groups should not be overlapped.

DAT[4]

DAT[5] b) The bit order is expressed in each of the bit groups, for example

B[0] = least significant blue pixel bit

DAT[6]

DAT[7]

DAT[8]

DAT[9]

DAT[10]

DAT[11]

DAT[12]

DAT[13]

DAT[14]

DAT[15]

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

87

Electrical Characteristics

Table 79. Video Signal Cross-Reference (continued) i.MX51A

LCD

Port Name

(x=1,2)

RGB,

Signal

Name

(General)

RGB/TV Signal Allocation (Example)

16-bit

RGB

18-bit

RGB

24-bit

RGB

8-bit

YCrCb

2

16-bit

YCrCb

20-bit

YCrCb

Smart

Signal

Name

DISPx_DAT22

DISPx_DAT23

DIx_DISP_CLK

DIx_PIN1

DAT[22]

DAT[23]

—

—

—

—

R[6]

R[7]

PixCLK

—

—

—

—

—

—

—

—

—

—

—

Comment

1

— —

VSYNC_IN May be required for anti-tearing

DIx_PIN2

DIx_PIN3

DIx_PIN4

DIx_PIN5

DIx_PIN6

DIx_PIN7

DIx_PIN8

DIx_D0_CS

DIx_D1_CS

HSYNC

VSYNC

—

—

—

—

—

—

—

—

—

—

CS0

CS1

—

—

—

—

—

VSYNC out

Additional frame/row synchronous signals with programmable timing

—

Alternate mode of PWM output for contrast or brightness control

DIx_PIN11

DIx_PIN12

DIx_PIN13

DIx_PIN14

—

—

—

—

WR

RD

RS1

RS2

—

—

Register select signal

Optional RS2

DIx_PIN15 DRDY/DV DRDY Data validation/blank, data enable

DIx_PIN16

DIx_PIN17

—

Q

—

—

Additional data synchronous signals with programmable features/timing

1

2

Signal mapping (both data and control/synchronization) is flexible. The table provides examples.

This mode works in compliance with recommendation ITU-R BT.656. The timing reference signals (frame start, frame end, line start, and line end) are embedded in the 8-bit data bus. Only video data is supported, transmission of non-video related data during blanking intervals is not supported.

88 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Electrical Characteristics

4.7.8.4

IPU Display Interface Timing

The IPU Display Interface supports two kinds of display’s accesses: synchronous and asynchronous. There are two groups of external interface pins to provide synchronous and asynchronous controls accordantly.

4.7.8.4.1

Synchronous Controls

The synchronous control is a signal that changes its value as a function either of a system or of an external clock. This control has a permanent period and a permanent wave form.

There are special physical outputs to provide synchronous controls:

• The ipp_disp_clk is a dedicated base synchronous signal that is used to generate a base display

(component, pixel) clock for a display.

• The ipp_pin_1– ipp_pin_7 are general purpose synchronous pins, that can be used to provide

HSYNC, VSYNC, DRDY or any else independent signal to a display.

The IPU has a system of internal binding counters for internal events (like HSYNC/VSYCN and so on) calculation. The internal event (local start point) is synchronized with internal DI_CLK. A suitable control starts from the local start point with predefined UP and DOWN values to calculate control’s changing points with half DI_CLK resolution. A full description of the counters system is in the IPU chapter of the

i.MX51 Multimedia Applications Processor Reference Manual (MCIMX51RM).

4.7.8.4.2

Asynchronous Controls

The asynchronous control is a data oriented signal that changes its a value with an output data according to an additional internal flags coming with the data.

There are special physical outputs to provide asynchronous controls, as follows:

• The ipp_d0_cs and ipp_d1_cspins are dedicated to provide chip select signals to two displays

• The ipp_pin_11– ipp_pin_17 are general purpose asynchronous pins, that can be used to provide

WR. RD, RS or any else data oriented signal to display.

NOTE

The IPU has independent signal generators for asynchronous signals toggling. When a DI decides to put a new asynchronous data in the bus, a new internal start (local start point) is generated. The signals generators calculate predefined UP and DOWN values to change pins states with half

DI_CLK resolution.

4.7.8.5

Synchronous Interfaces to Standard Active Matrix TFT LCD Panels

4.7.8.5.1

IPU Display Operating Signals

The IPU uses four control signals and data to operate a standard synchronous interface:

• IPP_DISP_CLK—Clock to display

• HSYNC—Horizontal synchronization

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

89

Electrical Characteristics

• VSYNC—Vertical synchronization

• DRDY—Active data

All synchronous display controls are generated on base of an internal generated “local start point”. The synchronous display controls can be placed on time axis with DI’s offset, up and down parameters. The display access can be whole number of DI clock (Tdiclk) only. The IPP_DATA can not be moved relative to the local start point.

4.7.8.5.2

LCD Interface Functional Description

Figure 53

depicts the LCD interface timing for a generic active matrix color TFT panel. In this figure signals are shown with negative polarity. The sequence of events for active matrix interface timing is:

• DI_CLK internal DI clock, used for calculation of other controls.

• IPP_DISP_CLK latches data into the panel on its negative edge (when positive polarity is selected).

In active mode, IPP_DISP_CLK runs continuously.

• HSYNC causes the panel to start a new line. (Usually IPP_PIN_2 is used as HSYNC)

• VSYNC causes the panel to start a new frame. It always encompasses at least one HSYNC pulse.

(Usually IPP_PIN_3 is used as VSYNC)

• DRDY acts like an output enable signal to the CRT display. This output enables the data to be shifted onto the display. When disabled, the data is invalid and the trace is off.

(For DRDY can be used either synchronous or asynchronous generic purpose pin as well.)

VSYNC

HSYNC

LINE 1 LINE 2 LINE 3 LINE 4 LINE n-1 LINE n

HSYNC

DRDY

IPP_DISP_CLK

IPP_DATA

1 2 3 m-1 m

Figure 53. Interface Timing Diagram for TFT (Active Matrix) Panels

4.7.8.5.3

TFT Panel Sync Pulse Timing Diagrams

Figure 54

depicts the horizontal timing (timing of one line), including both the horizontal sync pulse and the data. All shown on the figure parameters are programmable. All controls are started by corresponding

90 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Electrical Characteristics internal events—local start points. The timing diagrams correspond to inverse polarity of the

IPP_DISP_CLK signal and active-low polarity of the HSYNC, VSYNC and DRDY signals.

IP13o

IP5o IP8o IP8

IP7

IP5

DI clock

IPP_DISP_CLK

VSYNC

HSYNC

DRDY

IPP_DATA

D0 D1 Dn

IP9 IP9o IP10

IP6

Figure 54. TFT Panels Timing Diagram—Horizontal Sync Pulse

Figure 55

depicts the vertical timing (timing of one frame). All parameters shown in the figure are programmable.

IP13

Start of frame

End of frame

VSYNC

HSYNC

DRDY

IP11

IP14

IP12

Figure 55. TFT Panels Timing Diagram—Vertical Sync Pulse

IP15

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

91

Electrical Characteristics

Table 80

shows timing characteristics of signals presented in Figure 54 and Figure 55 .

Table 80. Synchronous Display Interface Timing Characteristics (Pixel Level)

ID

IP5

IP6

IP7

IP8

IP9

Parameter Symbol Value Description

Display interface clock period Tdicp

Display pixel clock period Tdpcp

(

1

)

DISP_CLK_PER_PIXEL

×

Tdicp

Display interface clock. IPP_DISP_CLK

Time of translation of one pixel to display,

DISP_CLK_PER_PIXEL—number of pixel components in one pixel (1.n). The

DISP_CLK_PER_PIXEL is virtual parameter to define Display pixel clock period.

The DISP_CLK_PER_PIXEL is received by

DC/DI one access division to n components.

Screen width time Tsw (SCREEN_WIDTH)

×

Tdicp

HSYNC width time

Horizontal blank interval 1

IP10 Horizontal blank interval 2

IP12 Screen height

IP13 VSYNC width

IP14 Vertical blank interval 1

IP15 Vertical blank interval 2

Thsw

Thbi1

Thbi2

Tsh

Tvsw

Tvbi1

Tvbi2

(HSYNC_WIDTH)

BGXP

×

Tdicp

(SCREEN_WIDTH -

BGXP - FW)

×

Tsw

BGYP

×

Tdicp

(SCREEN_HEIGHT)

VSYNC_WIDTH

×

Tsw

(SCREEN_HEIGHT -

BGYP - FH)

×

Tsw

SCREEN_WIDTH—screen width in, interface clocks. horizontal blanking included.

The SCREEN_WIDTH should be built by suitable DI’s counter

2

.

HSYNC_WIDTH—Hsync width in DI_CLK with 0.5 DI_CLK resolution. Defined by DI’s counter.

BGXP—Width of a horizontal blanking before a first active data in a line. (in interface clocks). The BGXP should be built by suitable DI’s counter.

Width a horizontal blanking after a last active data in a line. (in interface clocks)

FW—with of active line in interface clocks.

The FW should be built by suitable DI’s counter.

SCREEN_HEIGHT— screen height in lines with blanking

The SCREEN_HEIGHT is a distance between 2 VSYNCs.

The SCREEN_HEIGHT should be built by suitable DI’s counter.

VSYNC_WIDTH—Vsync width in DI_CLK with 0.5 DI_CLK resolution. Defined by DI’s counter

BGYP—width of first Vertical blanking interval in line.The BGYP should be built by suitable DI’s counter.

width of second Vertical blanking interval in line.The FH should be built by suitable DI’s counter.

Unit ns ns ns ns ns ns ns ns ns ns

92 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Electrical Characteristics

Table 80. Synchronous Display Interface Timing Characteristics (Pixel Level) (continued)

ID Parameter

IP5o Offset of IPP_DISP_CLK

IP13o Offset of VSYNC

IP8o Offset of HSYNC

IP9o Offset of DRDY

Symbol

Todicp

Tovs

Tohs

Todrdy

Value

DISP_CLK_OFFSET

×

Tdiclk

VSYNC_OFFSET

×

Tdiclk

HSYNC_OFFSET

×

Tdiclk

DRDY_OFFSET

×

Tdiclk

Description Unit

DISP_CLK_OFFSET— offset of

IPP_DISP_CLK edges from local start point, in DI_CLK

×

2

(0.5 DI_CLK Resolution)

Defined by DISP_CLK counter

VSYNC_OFFSET—offset of Vsync edges from a local start point, when a Vsync should be active, in DI_CLK

×

2

(0.5 DI_CLK Resolution).The

VSYNC_OFFSET should be built by suitable DI’s counter.

HSYNC_OFFSET—offset of Hsync edges from a local start point, when a Hsync should be active, in DI_CLK

×

2

(0.5 DI_CLK Resolution).The

HSYNC_OFFSET should be built by suitable DI’s counter.

DRDY_OFFSET— offset of DRDY edges from a suitable local start point, when a corresponding data has been set on the bus, in DI_CLK

×

2

(0.5 DI_CLK Resolution)

The DRDY_OFFSET should be built by suitable DI’s counter.

ns ns ns ns

1

Display interface clock period immediate value.

Tdicp =

⎧

⎪

⎪

⎨

⎪

⎪

⎩

T diclk

T diclk

× floor

DI_CLK_PERIOD

,

DISP_CLK_PERIOD

DI_CLK_PERIOD

for integer

+ 0.5

±

0.5

, for fractional

DI_CLK_PERIOD

DI_CLK_PERIOD

DISP_CLK_PERIOD—number of DI_CLK per one Tdicp. Resolution 1/16 of DI_CLK

DI_CLK_PERIOD—relation of between programing clock frequency and current system clock frequency

Display interface clock period average value.

Tdicp = T diclk

×

DI_CLK_PERIOD

2

DI’s counter can define offset, period and UP/DOWN characteristic of output signal according to programed parameters of the counter. Same of parameters in the table are not defined by DI’s registers directly (by name), but can be generated by corresponding DI’s counter. The SCREEN_WIDTH is an input value for DI’s HSYNC generation counter. The distance between HSYNCs is a SCREEN_WIDTH.

The maximal accuracy of UP/DOWN edge of controls is

Accuracy =

(

0.5

×

T diclk

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

93

Electrical Characteristics

The maximal accuracy of UP/DOWN edge of IPP_DATA is

Accuracy = T diclk

±

0.75ns

The DISP_CLK_PERIOD, DI_CLK_PERIOD parameters are programmed via registers.

Figure 56

shows the synchronous display interface timing diagram for access level. The

DISP_CLK_DOWN and DISP_CLK_UP parameters are set by using the register.

Table 81 shows the

timing characteristics for the diagram shown in

Figure 56

.

IP20o IP20

VSYNC

HSYNC

DRDY other controls

IPP_DISP_CLK

Tdicu Tdicd

IPP_DATA

IP16 IP17 IP19 IP18 local start point

Figure 56. Synchronous Display Interface Timing Diagram—Access Level

Table 81. Synchronous Display Interface Timing Characteristics (Access Level)

ID Parameter Symbol Min Typ

1

Tdicd

2

–Tdicu

3

Max Unit

IP16

IP17

IP18

IP19

Display interface clock low time

Display interface clock high time

Data setup time

Data holdup time

Tckl

Tckh

Tdsu

Tdhd

Tdicd-Tdicu–1.5

Tdicp–Tdicd+Tdicu–1.5

Tdicd–1.5

Tdicp–Tdicd–1.5

Tdicp–Tdicd+Tdicu

Tdicu

Tdicp–Tdicu

Tdicd–Tdicu+1.5

Tdicp–Tdicd+Tdicu+1.5

—

— ns ns ns ns

IP20o Control signals offset times (defines for each pin)

Tocsu Tocsu–1.5

Tocsu Tocsu+1.5

—

IP20 Control signals setup time to display interface clock (defines for each pin)

Tcsu Tdicd–1.5–Tocsu%Tdicp Tdicu — ns

1

The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display.

These conditions may be chip specific.

94 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Electrical Characteristics

2

Display interface clock down time

Tdicd =

2 diclk

× ceil

2

×

DISP_CLK_DOWN

DI_CLK_PERIOD

3

Display interface clock up time

Tdicu = --- T

2

⎛

⎝ diclk

× ceil

2

×

DISP_CLK_UP

DI_CLK_PERIOD

⎞

⎠ where CEIL(X) rounds the elements of X to the nearest integers towards infinity.

4.7.8.6

Interface to a TV Encoder

The interface has an 8-bit data bus, transferring a single 8-bit value (Y/U/V) in each cycle. The timing of the interface is described in

Figure 57

.

NOTE

• The frequency of the clock DISP_CLK is 27 MHz (within 10%)

• The HSYNC, VSYNC signals are active low.

• The DRDY signal is shown as active high.

• The transition to the next row is marked by the negative edge of the

HSYNC signal. It remains low for a single clock cycle

• The transition to the next field/frame is marked by the negative edge of the VSYNC signal. It remains low for at least one clock cycles

—

At a transition to an odd field (of the next frame), the negative edges of VSYNC and HSYNC coincide.

—

At a transition is to an even field (of the same frame), they do not coincide.

• The active intervals—during which data is transferred—are marked by the HSYNC signal being high.

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

95

Electrical Characteristics

DISP_CLK

HSYNC

VSYNC

DRDY

IPP_DATA

Cb Y Cr Y

523 524 525

Pixel Data Timing

1 2 3

HSYNC

DRDY

VSYNC

4

Cb

5

Y

6

261

Even Field

262 263 264 265 266 267

Odd Field

268 269

HSYNC

DRDY

VSYNC

Cr

10

273

Even Field Odd Field

621 622 623

Line and Field Timing - NTSC

624 625 1 2 3 4 23

HSYNC

DRDY

VSYNC

Even Field Odd Field

308 309 310 311 312 313 314 315 316 336

HSYNC

DRDY

VSYNC

Odd Field Even Field

Line and Field Timing - PAL

Figure 57. TV Encoder Interface Timing Diagram

96 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

4.7.8.6.1

TV Encoder Performance Specifications

All the parameters in the table are defined under the following conditions:

Rset = 1.05 k

Ω ±1%, resistor on VREFOUT pin to Ground

Rload = 37.5

Ω ±1%, output load to Ground

The TV encoder output specifications are shown in

Table 82 .

Table 82. TV Encoder Video Performance Specifications

Electrical Characteristics

DAC STATIC PERFORMANCE

Resolution

1

Integral Nonlinearity (INL)

2

Differential Nonlinearity (DNL)

2

Channel-to-channel gain matching

Full scale output voltage

2

2

—

—

—

—

Rset = 1.05 k

Ω ±1%

Rload = 37.5

Ω±1%

DAC DYNAMIC PERFORMANCE

Spurious Free Dynamic Range (SFDR) F out

= 3.38 MHz

F samp

= 216 MHz

Spurious Free Dynamic Range (SFDR) F out

= 9.28 MHz

F samp

= 297 MHz

VIDEO PERFORMANCE IN SD MODE

2,

3

Short Term Jitter (Line to Line)

Long Term Jitter (Field to Field)

Frequency Response

Luminance Nonlinearity

Differential Gain

Differential Phase

Signal-to-Noise Ratio (SNR)

Hue Accuracy

Color Saturation Accuracy

Chroma AM Noise

Chroma PM Noise

Chroma Nonlinear Phase

Chroma Nonlinear Gain

Chroma/Luma Intermodulation

—

—

0-4.0 MHz

5.75 MHz

—

—

—

Flat field full bandwidth

—

—

—

—

—

—

—

—

—

—

—

—

—

—

1.24

—

—

—

—

–0.1

–0.7

—

—

—

—

—

—

—

—

10

1

0.6

2

1.35

59

54

0.8

1.5

–70

–47

0.5

2.5

0.1

0.5

0.35

0.6

75

2.5

3.5

—

—

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

—

2

1

—

1.45

Bits

LSBs

LSBs

%

V

—

— dBc dBc

—

—

—

—

—

—

—

—

—

—

—

—

—

0.1

0

±ns

±ns dB dB

±%

%

Degrees dB

±Degrees

±% dB dB

±Degrees

±%

±%

97

Electrical Characteristics

Table 82. TV Encoder Video Performance Specifications (continued)

Chroma/Luma Gain Inequality

Chroma/Luma Delay Inequality

—

—

—

VIDEO PERFORMANCE IN HD MODE

2

Luma Frequency Response

Chroma Frequency Response

Luma Nonlinearity

Chroma Nonlinearity

0-30 MHz

0-15 MHz,

YCbCr 422 mode

—

—

Luma Signal-to-Noise Ratio 0-30 MHz

Chroma Signal-to-Noise Ratio 0-15 MHz

2

3

1

Guaranteed by design

Guaranteed by characterization

R set

= VREFOUT's external resistor to ground = 1.05 k

Ω

–0.2

–0.2

—

—

—

—

—

—

—

3.2

3.4

62

72

1.0

1.0

—

—

—

—

—

—

0.2

0.2

—

—

—

—

%

% dB dB

±%

±ns

— dB dB

4.7.8.7

Asynchronous Interfaces

4.7.8.7.1

Standard Parallel Interfaces

The IPU has four signal generator machines for asynchronous signal. Each machine generates IPU’s internal control levels (0 or 1) by UP and DOWN are defined in Registers. Each asynchronous pin has a dynamic connection with one of the signal generators. This connection is redefined again with a new display access (pixel/component) The IPU can generate control signals according to system 80/68 requirements. The burst length is received as a result from predefined behavior of the internal signal generator machines.

The access to a display is realized by the following:

• CS (IPP_CS) chip select

• WR (IPP_PIN_11) write strobe

• RD (IPP_PIN_12) read strobe

• RS (IPP_PIN_13) Register select (A0)

Both system 80 and system 68k interfaces are supported for all described modes as depicted in

Figure 58

,

Figure 59

, Figure 60

, and Figure 61 . The timing images correspond to active-low IPP_CS, WR and RD

signals.

Each asynchronous access is defined by an access size parameter. This parameter can be different between different kinds of accesses. This parameter defines a length of windows, when suitable controls of the current access are valid. A pause between two different display accesses can be guaranteed by programing of suitable access sizes. There are no minimal/maximal hold/setup time hard defined by DI. Each control signal can be switched at any time during access size.

98 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Electrical Characteristics

IPP_CS

RS

WR

RD

IPP_DATA

Burst access mode with sampling by CS signal

IPP_CS

RS

WR

RD

IPP_DATA

Single access mode (all control signals are not active for one display interface clock after each display access)

Figure 58. Asynchronous Parallel System 80 Interface (Type 1) Timing Diagram

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

99

Electrical Characteristics

IPP_CS

RS

WR

RD

IPP_DATA

Burst access mode with sampling by WR/RD signals

IPP_CS

RS

WR

RD

IPP_DATA

Single access mode (all control signals are not active for one display interface clock after each display access)

Figure 59. Asynchronous Parallel System 80 Interface (Type 2) Timing Diagram

100 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Electrical Characteristics

IPP_CS

RS

WR

(READ/WRITE)

RD

(ENABLE)

IPP_DATA

Burst access mode with sampling by CS signal

IPP_CS

RS

WR

(READ/WRITE)

RD

(ENABLE)

IPP_DATA

Single access mode (all control signals are not active for one display interface clock after each display access)

Figure 60. Asynchronous Parallel System 68k Interface (Type 1) Timing Diagram

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

101

Electrical Characteristics

IPP_CS

RS

WR

(READ/WRITE)

RD

(ENABLE)

IPP_DATA

Burst access mode with sampling by ENABLE signal

IPP_CS

RS

WR

(READ/WRITE)

RD

(ENABLE)

IPP_DATA

Single access mode (all control signals are not active for one display interface clock after each display access)

Figure 61. Asynchronous Parallel System 68k Interface (Type 2) TIming Diagram

Display operation can be performed with IPP_WAIT signal. The DI reacts to the incoming IPP_WAIT signal with 2 DI_CLK delay. The DI finishes a current access and a next access is postponed until

IPP_WAIT release.

102 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Electrical Characteristics

Figure 62

shows timing of the parallel interface with IPP_WAIT control.

DI clock

IPP_CS

IPP_DATA

WR

RD

IPP_WAIT

IPP_DATA_IN

IP39 waiting

Figure 62. Parallel Interface Timing Diagram—Read Wait States waiting

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

103

Electrical Characteristics

4.7.8.7.2

Asynchronous Parallel Interface Timing Parameters

Figure 63

depicts timing of asynchronous parallel interfaces based on the system 80 and system 68k interfaces.

Table 84

shows the timing characteristics at display access level. Table 83

shows the timing characteristics at the logical level—from configuration perspective. All timing diagrams are based on active low control signals (signals polarity is controlled through the DI_DISP_SIG_POL register).

IP29 IP32

IP35

IP33

IP36

IP34

IP47 IP30 IP31

DI clock

IPP_CS

RS

WR

RD

IPP_DATA

PP_DATA_IN

A0 D0 D1

IP28a IP28d IP27

D2 D3

IP37 IP38

Figure 63. Asynchronous Parallel Interface Timing Diagram

Table 83. Asynchronous Display Interface Timing Parameters (Pixel Level)

ID Parameter Symbol

IP27 Read system cycle time Tcycr

IP28a Address Write system cycle time Tcycwa

IP28d Data Write system cycle time

IP29 RS start

Tcycwd

Tdcsrr

IP30 CS start Tdcsc

Value

ACCESS_SIZE_#

ACCESS_SIZE_#

ACCESS_SIZE_#

UP#

UP#

Description Unit predefined value in DI REGISTER ns predefined value in DI REGISTER ns predefined value in DI REGISTER ns

RS strobe switch, predefined value in DI REGISTER ns

CS strobe switch, predefined value in DI REGISTER ns

104 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Electrical Characteristics

Table 83. Asynchronous Display Interface Timing Parameters (Pixel Level) (continued)

ID Parameter Symbol Value Description

IP31

IP32

IP33

IP34

IP35

CS hold

RS hold

Read start

Read hold

Write start

Tdchc

Tdchrr

Tdcsr

Tdchr

Tdcsw

DOWN#

DOWN#

UP#

DOWN#

UP#

CS strobe release, predefined value in DI REGISTER

RS strobe release, predefined value in DI REGISTER read strobe switch, predefined value in DI REGISTER read strobe release signal, predefined value in DI REGISTER write strobe switch, predefined value in DI REGISTER

IP36 Controls hold time for write Tdchw DOWN# write strobe release, predefined value in DI REGISTER

IP37 Slave device data delay

1

Tracc Delay of incoming data Physical delay of display’s data, defined from Read access local start point

IP38

IP47

Slave device data hold time

Read time point

13

3

Troh

Tdrp

Hold time of data on the buss Time that display read data is valid in input bus

Data sampling point Point of input data sampling by DI, predefined in DC Microcode

1

This parameter is a requirement to the display connected to the IPU.

Unit

—

— ns ns ns ns ns ns

—

Table 84. Asynchronous Parallel Interface Timing Parameters (Access Level)

ID

IP27 Read system cycle time

IP28 Write system cycle time

IP29 RS start

IP30 CS start

Parameter Symbol

Tcycr

Tcycw

Min

Tdicpr–1.5

Tdicpw–1.5

Tdicpr

2

Tdicpw

3

Tdicurs

Typ

1

Tdicpr+1.5

Tdicpw+1.5

Max

Tdcsrr Tdicurs–1.5

Tdicurs+1.5

Tdcsc Tdicucs–1.5

Tdicur

Tdchc TdicdcsTdicucs–1.5

Tdicdcs

4

–Tdicucs

5

Tdchrr Tdicdrs–Tdicurs–1.5

Tdicdrs

6

–Tdicurs

7

Tdicucs+1.5

Tdicdcs–Tdicucs+1.5

Tdicdrs–Tdicurs+1.5

Unit

IP31 CS hold

IP32 RS hold ns ns

IP33 Controls setup time for read

IP34 Controls hold time for read

Tdcsr

Tdchr

Tdicur–1.5

Tdicdr–Tdicur–1.5

Tdicur

Tdicdr

8

–Tdicur

9

Tdicur+1.5

Tdicdr–Tdicur+1.5

ns ns

IP35 Controls setup time for write Tdcsw Tdicuw–1.5

IP36 Controls hold time for write Tdchw Tdicdw–Tdicuw–1.5

Tdicpw

10

–Tdicuw

11

IP37 Slave device data delay

12

Tracc 0 —

Tdicdw–Tdicuw+1.5

ns

Tdrp

13

–Tlbd

14

–Tdicur–1.5

ns

IP38 Slave device data hold time

8

Troh Tdrp–Tlbd–Tdicdr+1.5

Tdicuw

—

Tdicuw+1.5

Tdicpr–Tdicdr–1.5

ns ns ns ns ns ns

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

105

Electrical Characteristics

Table 84. Asynchronous Parallel Interface Timing Parameters (Access Level) (continued)

Parameter Symbol Min Typ

1

Max ID Unit

IP39 Setup time for wait signal

IP47 Read time point

13

Tswait

Tdrp Tdrp–1.5

—

Tdrp

—

Tdrp+1.5

— — ns

1

The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display.

These conditions may be chip specific.

2

Display period value for read

Tdicpr = T

DI_CLK

× c eil

DI_CLK_PERIOD

ACCESS_SIZE is predefined in REGISTER

3

Display period value for write

Tdicpw = T

DI_CLK

× ceil DI_CLK_PERIOD

ACCESS_SIZE is predefined in REGISTER

4

Display control down for CS

Tdicdcs =

2

DI_CLK

× ceil

2

×

DISP_DOWN_#

DI_CLK_PERIOD

DISP_DOWN is predefined in REGISTER

5

Display control up for CS

Tdicucs =

1

--- T

2

⎛

⎝

DI_CLK

× ceil

2

×

DISP_UP_#

DI_CLK_PERIOD

⎞

⎠

DISP_UP is predefined in REGISTER

6

Display control down for RS

Tdicdrs =

2

DI_CLK

× ceil

2

×

DISP_DOWN_#

DI_CLK_PERIOD

DISP_DOWN is predefined in REGISTER

7

Display control up for RS

Tdicurs =

2

DI_CLK

× ceil

2

×

DISP_UP_#

DI_CLK_PERIOD

DISP_UP is predefined in REGISTER

8

Display control down for read

Tdicdr =

1

--- T

2

⎛

⎝

DI_CLK

× ceil

2

×

DISP_DOWN_#

DI_CLK_PERIOD

⎞

⎠

DISP_DOWN is predefined in REGISTER

106 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Electrical Characteristics

9

Display control up for read

Tdicur =

2 DI_CLK

× ceil

2

×

DISP_UP_#

DI_CLK_PERIOD

DISP_UP is predefined in REGISTER

10

Display control down for read

Tdicdrw = --- T

2

⎛

⎝

DI_CLK

× ceil

2

×

DISP_DOWN_#

DI_CLK_PERIOD

⎞

⎠

DISP_DOWN is predefined in REGISTER

11

Display control up for write

Tdicuw = --- T

2

DI_CLK

× ceil

2

×

DISP_UP_#

DI_CLK_PERIOD

DISP_UP is predefined in REGISTER

12

This parameter is a requirement to the display connected to the IPU

13

Data read point

Tdrp = T

DI_CLK

× ce il

DI_CLK_PERIOD

Note: DISP#_READ_EN—operand of DC’s MICROCDE READ command to sample incoming data

14

Loop back delay Tlbd is the cumulative propagation delay of read controls and read data. It includes an IPU output delay, a chip-level output delay, board delays, a chip-level input delay, an IPU input delay. This value is chip specific.

4.7.8.8

Standard Serial Interfaces

The IPU supports the following types of asynchronous serial interfaces:

1. 3-wire (with bidirectional data line).

2. 4-wire (with separate data input and output lines).

3. 5-wire type 1 (with sampling RS by the serial clock).

4. 5-wire type 2 (with sampling RS by the chip select signal).

The IPU has four independent outputs and one input. The port can be configured to provide 3, 4, or 5-wire interfaces.

Figure 64

depicts the timing diagram of the 3-wire serial interface. The timing diagrams correspond to active-low IPP#_CS signal and the straight polarity of the IPP_CLK signal.

For this interface, a bidirectional data line is used outside the chip. The IPU still uses separate input and output data lines (IPP_IND_DISPB_SD_D and IPP_DO_DISPB_SD_D). The I/O mux should provide

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

107

Electrical Characteristics joining the internal data lines to the bidirectional external line according to the IPP_OBE_DISPB_SD_D signal provided by the IPU.

DISPB_D#_CS programed delay programed delay

DISPB_SD_D_CLK

DISPB_SD_D RW RS D7 D6 D5 D4 D3 D2 D1 D0

Preamble

Input or output data

Figure 64. 3-Wire Serial Interface Timing Diagram

Figure 65

depicts timing diagram of the 4-wire serial interface. For this interface, there are separate input and output data lines both inside and outside the chip.

Write

DISPB_D#_CS programed delay programed delay

DISPB_SD_D_CLK

DISPB_SD_D

(Output)

Preamble

RW RS D7 D6 D5 D4 D3 D2 D1 D0

Output data

DISPB_SD_D

(Input)

Read programed delay programed delay

DISPB_D#_CS

DISPB_SD_D_CLK

DISPB_SD_D

(Output)

DISPB_SD_D

(Input)

RW RS

Preamble

D7 D6 D5 D4 D3 D2 D1 D0

Input data

Figure 65. 4-Wire Serial Interface Timing Diagram

108 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Electrical Characteristics

Figure 66

depicts timing of the 5-wire serial interface. For this interface, a separate RS line is added.

Write

DISPB_D#_CS programed delay programed delay

DISPB_SD_D_CLK

DISPB_SD_D

(Output)

Preamble

RW D7 D6 D5 D4 D3 D2 D1 D0

Output data

DISPB_SD_D

(Input)

DISPB_SER_RS programed delay

Read

DISPB_D#_CS programed delay programed delay

DISPB_SD_D_CLK

DISPB_SD_D

(Output)

DISPB_SD_D

(Input)

DISPB_SER_RS

RW

Preamble

D7 D6 D5 D4 D3 D2 D1 D0 programed delay

Input data

Figure 66. 5-Wire Serial Interface Timing Diagram

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

109

Electrical Characteristics

4.7.8.8.1

Asynchronous Serial Interface Timing Parameters

Figure 67 depicts timing of the serial interface. Table 85 shows timing characteristics at display access

level.

IP73

IP72

DI clock

IPP_DISPB_DO_SD_D

IPP_DO_DISPB_SER_CS

IP71

IP70

IPP_DO_DISPB_SER_RS

IP68

IP58

IPP_IND_DISPB_SD_D

IP69

IP59

IP50, IP52

IP55, IP57,

IP61

IP60,

IP64, IP66

IP54, IP56,

IP65, IP67

IPP_DO_DISPB_SD_D_CLK

IP51,53

IP48, IP49, IP62, IP63

Figure 67. Asynchronous Serial Interface Timing Diagram

Table 85. Asynchronous Serial Interface Timing Characteristics (Access Level)

ID Parameter

IP48 Read system cycle time

IP49 Write system cycle time

IP50 Read clock low pulse width

IP51 Read clock high pulse width

Symbol

Tcycr

Tcycw

Trl

Trh

Tdicpr–1.5

Tdicpw–1.5

Min Typ

1

Tdicpr

2

Tdicpw

3

Tdicdr

4

–Tdicur

5

Tdicdr–Tdicur–1.5

Tdicpr–Tdicdr+Tdicur–1.5 Tdicpr–Tdicdr+

Tdicur

Max

Tdicpr+1.5

Tdicpw+1.5

Tdicdr–Tdicur+1.5

Tdicpr–Tdicdr+Tdicur+

1.5

Unit ns ns ns ns

110 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Electrical Characteristics

Table 85. Asynchronous Serial Interface Timing Characteristics (Access Level) (continued)

ID Parameter

IP52 Write clock low pulse width

IP53 Write clock high pulse width

IP54 Controls setup time for read

IP55 Controls hold time for read

Symbol

Twl

Twh

Tdcsr

Tdchr

Tdicur–1.5

Min

Tdicdw–Tdicuw–1.5

Tdicpw–Tdicdw+

Tdicuw–1.5

Tdicpr–Tdicdr–1.5

Typ

1

Max

Tdicdw

6

–Tdicuw

7

Tdicdw–Tdicuw+1.5

Tdicpw–Tdicdw+

Tdicuw

Tdicur

Tdicpr–Tdicdr

Tdicpw–Tdicdw+

Tdicuw+1.5

—

—

Unit ns ns ns ns

IP56 Controls setup time for write Tdcsw Tdicuw–1.5

IP57 Controls hold time for write Tdchw Tdicpw–Tdicdw–1.5

IP58 Slave device data delay

8

Tracc 0

IP59 Slave device data hold time

8

Troh Tdrp-Tlbd-Tdicdr+1.5

IP60 Write data setup time Tds Tdicdw-1.5

Tdicuw

Tdicpw–Tdicdw

— ns

— ns

Tdrp

9

–Tlbd

10

-Tdicur-1.5

ns

Tdicdw

—

— Tdicpr-Tdicdr-1.5

— ns ns

IP61 Write data hold time

IP62 Read period

2

IP63 Write period

3

IP64 Read down time

4

IP65 Read up time

5

IP66 Write down time

6

Tdh

Tdicpr

Tdicpw

Tdicdr

Tdicur

Tdicpw-Tdicdw-1.5

Tdicpr-1.5

Tdicpw-1.5

Tdicdr-1.5

Tdicur-1.5

Tdicpw-Tdicdw

Tdicpr

Tdicpw

Tdicdr

Tdicur

Tdicpr+1.5

Tdicpw+1.5

Tdicdr+1.5

Tdicur+1.5

— ns ns ns ns ns

Tdicdw Tdicdw-1.5

Tdicdw Tdicdw+1.5

ns

IP67 Write up time

7

IP68 Read time point

9

Tdicuw Tdicuw-1.5

Tdicuw Tdicuw+1.5

ns

Tdrp Tdrp-1.5

Tdrp Tdrp+1.5

ns

IP69 Clock offset

11

IP70 RS up time

12

IP71 RS down time

13

Toclk

Tdicurs

Toclk-1.5

Tdicurs–1.5

Toclk

Tdicurs

Toclk+1.5

Tdicurs+1.5

ns ns

Tdicdrs Tdicdrs -1.5

Tdicdrs Tdicdrs+1.5

ns

IP72 CS up time

14

Tdicucs Tdicucs –1.5

Tdicucs Tdicucs+1.5

ns

IP73 CS down time

15

Tdicdcs Tdicdcs –1.5

Tdicdcs Tdicdcs+1.5

ns

1

The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display.

These conditions may be chip specific.

2

Display interface clock period value for read

Tdicpr = T

DI_CLK

× ceil

DISP#_IF_CLK_PER_RD

--------------------------------------------------------------------

DI_CLK_PERIOD

3

Display interface clock period value for write

Tdicpw = T

DI_CLK

× ce il

DI_CLK_PERIOD

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

111

Electrical Characteristics

4

Display interface clock down time for read

Tdicdr =

2 DI_CLK

× ceil

2

×

DISP_DOWN_#

DI_CLK_PERIOD

5

Display interface clock up time for read

Tdicur =

2

⎛

⎝

DI_CLK

× ceil

2

×

DISP_UP_#

DI_CLK_PERIOD

⎞

⎠

6

Display interface clock down time for write

Tdicdw =

1

--- T

2

⎛

⎝

DI_CLK

× ceil

2

×

DISP_DOWN_#

DI_CLK_PERIOD

⎞

⎠

7

Display interface clock up time for write

Tdicuw = --- T

2

DI_CLK

× ceil

2

×

DISP_UP_#

DI_CLK_PERIOD

8

This parameter is a requirement to the display connected to the IPU

9

Data read point

Tdrp = T

DI_CLK

× ce il

DI_CLK_PERIOD

DISP_RD_EN is predefined in REGISTER

10

Loop back delay Tlbd is the cumulative propagation delay of read controls and read data. It includes an IPU output delay, a chip-level output delay, board delays, a chip-level input delay, an IPU input delay. This value is chip specific.

11

Display interface clock offset value

To clk = T

DI_CLK

× ce il

DISP_CLK_OFFSET

--------------------------------------------------------

DI_CLK_PERIOD

CLK_OFFSET is predefined in REGISTER

12

Display RS up time

Tdicurs = T

DI_CLK

× ceil

DI_CLK_PERIOD

DISP_RS_UP is predefined in REGISTER

13

Display RS down time

Tdicdrs = T

DI_CLK

× ce il

DI_CLK_PERIOD

DISP_RS_DOWN is predefined in REGISTER

14

Display RS up time

Tdicucs = T

DI_CLK

× ce il

DISP_CS_UP_#

-----------------------------------------------

DI_CLK_PERIOD

DISP_CS_UP is predefined in REGISTER

112 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

15

Display RS down time

Tdicdcs =

(

T

DI_CLK

× ce il

)

DI_CLK_PERIOD

DISP_CS_DOWN is predefined in REGISTER.

4.7.9

1-Wire Timing Parameters

Figure 68

depicts the RPP timing and

Table 86 lists the RPP timing parameters.

One-Wire bus

(BATT_LINE)

1-WIRE Tx

“Reset Pulse”

DS2502 Tx

“Presence Pulse”

OW2

Electrical Characteristics

OW1

OW2

OW3

OW4

ID

OW1 OW3

OW4

Figure 68. Reset and Presence Pulses (RPP) Timing Diagram

Table 86. RPP Sequence Delay Comparisons Timing Parameters

Parameters

Reset Time Low

Presence Detect High

Presence Detect Low

Reset Time High

Symbol t

RSTL t

PDH t

PDL t

RSTH

Min

480

15

60

480

Typ

511

—

—

512

Max

—

60

240

—

Figure 69 depicts Write 0 Sequence timing, and Table 87 lists the timing parameters.

OW6

One-Wire bus

(BATT_LINE)

Unit

µs

µs

µs

µs

ID

OW5

OW6

OW5

Figure 69. Write 0 Sequence Timing Diagram

Table 87. WR0 Sequence Timing Parameters

Parameter

Write 0 Low Time

Transmission Time Slot

Symbol t

WR0_low t

SLOT

Min

60

OW5

Typ

100

117

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Max

120

120

Unit

µs

µs

113

Electrical Characteristics

Figure 70

depicts Write 1 Sequence timing,

Figure 71 depicts the Read Sequence timing, and Table 88

lists the timing parameters.

OW8

One-Wire bus

(BATT_LINE)

OW7

Figure 70. Write 1 Sequence Timing Diagram

OW8

One-Wire bus

(BATT_LINE)

ID

OW7

OW8

OW9

OW7

OW9

Figure 71. Read Sequence Timing Diagram

Table 88. WR1 /RD Timing Parameters

Parameter

Write /Read Low Time

Transmission Time Slot

Release Time

Symbol t

LOW1 t

SLOT t

RELEASE

Min

1

60

15

Typ

5

117

—

Max

15

120

45

Unit

µs

µs

µs

4.7.10

Pulse Width Modulator (PWM) Timing Parameters

This section describes the electrical information of the PWM.The PWM can be programmed to select one of three clock signals as its source frequency. The selected clock signal is passed through a prescaler before being input to the counter. The output is available at the pulse-width modulator output (PWMO) external pin.

114 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Electrical Characteristics

Figure 72 depicts the timing of the PWM, and Table 89 lists the PWM timing parameters.

1

2a

System Clock

2b

3a

4a

PWM Output

Figure 72. PWM Timing

Table 89. PWM Output Timing Parameter

Ref. No.

Parameter

System CLK frequency

1

1

2a

2b

3a

3b

4a

Clock high time

Clock low time

Clock fall time

Clock rise time

Output delay time

4b Output setup time

1

CL of PWMO = 30 pF

Min

0

12.29

9.91

—

—

—

8.71

3b

4b

Max ipg_clk

—

—

0.5

0.5

9.37

—

Unit

MHz ns ns ns ns ns ns

4.7.11

P-ATA Timing Parameters

This section describes the timing parameters of the Parallel ATA module which are compliant with

ATA/ATAPI-5 specification.

Parallel ATA module can work on PIO/Multi-Word DMA/Ultra DMA transfer modes. Each transfer mode has different data transfer rate, Ultra DMA mode 4 data transfer rate is up to 66 Mbyte/s. Parallel ATA module interface consist of a total of 29 pins, Some pins act on different function in different transfer mode. There are different requirements of timing relationships among the function pins conform with

ATA/ATAPI-5 specification and these requirements are configurable by the ATA module registers.

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

115

Electrical Characteristics

Table 90 and Figure 73 define the AC characteristics of all the P-ATA interface signals on all data

transfer modes.

ATA Interface Signals

SI2 SI1

Figure 73. P-ATA Interface Signals Timing Diagram

Table 90. AC Characteristics of All Interface Signals

ID Parameter Symbol Min Max Unit

SI1 Rising edge slew rate for any signal on ATA interface.

1

SI2 Falling edge slew rate for any signal on ATA interface (see note)

S rise

S fall

—

—

1.25

1.25

V/ns

V/ns

SI3 Host interface signal capacitance at the host connector C host

— 20 pF

1

SRISE and SFALL shall meet this requirement when measured at the sender’s connector from 10–90% of full signal amplitude with all capacitive loads from 15

–

40 pF where all signals have the same capacitive load value.

The user needs to use level shifters for 5.0 V compatibility on the ATA interface. The i.MX51 P-ATA interface is 3.3 V compatible.

The use of bus buffers introduces delay on the bus and introduces skew between signal lines. These factors make it difficult to operate the bus at the highest speed (UDMA-4) when bus buffers are used. If fast

UDMA mode operation is needed, this may not be compatible with bus buffers.

Another area of attention is the slew rate limit imposed by the ATA specification on the ATA bus.

According to this limit, any signal driven on the bus should have a slew rate between 0.4 and 1.2 V/ns with a 40 pF load. Not many vendors of bus buffers specify slew rate of the outgoing signals.

When bus buffers are used, the ata_data bus buffer is special. This is a bidirectional bus buffer, so a direction control signal is needed. This direction control signal is ata_buffer_en. When its high, the bus should drive from host to device. When its low, the bus should drive from device to host. Steering of the signal is such that contention on the host and device tri-state busses is always avoided.

In the timing equations, some timing parameters are used. These parameters depend on the implementation of the i.MX51 P-ATA interface on silicon, the bus buffer used, the cable delay and cable skew.

116 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Electrical Characteristics

Table 91

shows ATA timing parameters.

Table 91. P-ATA Timing Parameters

Name Description

Value/

Contributing Factor

1

T ti_ds ti_dh tco

Bus clock period (ipg_clk_ata)

Set-up time ata_data to ata_iordy edge (UDMA-in only)

UDMA0

UDMA1

UDMA2, UDMA3

UDMA4

Hold time ata_iordy edge to ata_data (UDMA-in only)

UDMA0, UDMA1, UDMA2, UDMA3, UDMA4

Peripheral clock frequency

15 ns

10 ns

7 ns

5 ns

5.0 ns

12.0 ns Propagation delay bus clock L-to-H to ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data, ata_buffer_en tsu tsui

Set-up time ata_data to bus clock L-to-H

Set-up time ata_iordy to bus clock H-to-L thi Hold time ata_iordy to bus clock H to L tskew1 Max difference in propagation delay bus clock L-to-H to any of following signals ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data (write), ata_buffer_en tskew2 Max difference in buffer propagation delay for any of following signals ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data (write), ata_buffer_en tskew3 Max difference in buffer propagation delay for any of following signals ata_iordy, ata_data (read)

8.5 ns

8.5 ns

2.5 ns

7 ns

Transceiver

Transceiver tbuf tcable1 tcable2

Max buffer propagation delay

Cable propagation delay for ata_data

Cable propagation delay for control signals ata_dior, ata_diow, ata_iordy, ata_dmack tskew4 Max difference in cable propagation delay between ata_iordy and ata_data (read) tskew5 Max difference in cable propagation delay between (ata_dior, ata_diow, ata_dmack) and ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_data(write) tskew6 Max difference in cable propagation delay without accounting for ground bounce

1

Values provided where applicable.

Transceiver

Cable

Cable

Cable

Cable

Cable

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

117

Electrical Characteristics

4.7.11.1

PIO Mode Read Timing

Figure 74

shows timing for PIO read and

Table 92

lists the timing parameters for PIO read.

Figure 74. PIO Read Timing Diagram

Table 92. PIO Read Timing Parameters

ATA

Parameter

Parameter

from Figure 74

t6 tA trd t9 t5 t1 t2 t0 t6 tA trd1 t1 t2r t9 t5

—

Value

Controlling

Variable t1 (min) = time_1

×

T – (tskew1 + tskew2 + tskew5) t2 min) = time_2r

×

T – (tskew1 + tskew2 + tskew5) t9 (min) = time_9

×

T – (tskew1 + tskew2 + tskew6) t5 (min) = tco + tsu + tbuf + tbuf + tcable1 + tcable2

time_1 time_2r time_3

If not met, increase time_2

0 tA (min) = (1.5 + time_ax)

×

T – (tco + tsui + tcable2 + tcable2 + 2

× tbuf) trd1 (max) = (–trd) + (tskew3 + tskew4) trd1 (min) = (time_pio_rdx – 0.5)

(time_pio_rdx – 0.5)

×

T – (tsu + thi)

×

T > tsu + thi + tskew3 + tskew4 t0 (min) = (time_1 + time_2 + time_9)

×

T

— time_ax time_pio_rdx time_1, time_2r, time_9

118 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Electrical Characteristics

Figure 75

shows timing for PIO write and

Table 93

lists the timing parameters for PIO write.

Figure 75. Multi-word DMA (MDMA) Timing

Table 93. PIO Write Timing Parameters

ATA

Parameter

Parameter from

Figure 75

t4 tA t0 t9 t3 t1 t2

—

— t4 tA

— t1 t2w t9

—

—

—

Value

Controlling

Variable t1 (min) = time_1 t9 (min) = time_9 t4 (min) = time_4

×

T – (tskew1 + tskew2 + tskew5) t2 (min) = time_2w

×

T – (tskew1 + tskew2 + tskew5)

×

T – (tskew1 + tskew2 + tskew6) t3 (min) = (time_2w – time_on)

×

T – tskew1 tA = (1.5 + time_ax)

×

T – (tskew1 + tskew2 +tskew5)

×

T – (tco + tsui + tcable2 + tcable2 + 2

× tbuf) t0(min) = (time_1 + time_2 + time_9)

×

T

Avoid bus contention when switching buffer on by making ton long enough

Avoid bus contention when switching buffer off by making toff long enough

time_1 time_2w time_9

If not met, increase time_2w time_4 time_ax time_1, time_2r, time_9

—

—

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

119

Electrical Characteristics

Figure 76

shows timing for MDMA read,

Figure 77 shows timing for MDMA write, and Table 94 lists

the timing parameters for MDMA read and write.

Figure 76. MDMA Read Timing Diagram

Figure 77. MDMA Write Timing Diagram

ATA

Parameter tm, ti td tk t0 tg(read) tf(read) tg(write) tf(write) tL

Table 94. MDMA Read and Write Timing Parameters

Parameter from

Figure 76 ,

Figure 77

tm td, td1 tk

— tgr tfr

—

—

—

Value tm (min) = ti (min) = time_m

×

T – (tskew1 + tskew2 + tskew5) td1.(min) = td (min) = time_d

×

T – (tskew1 + tskew2 + tskew6) tk.(min) = time_k

×

T – (tskew1 + tskew2 + tskew6) t0 (min) = (time_d + time_k)

×

T tgr (min-read) = tco + tsu + tbuf + tbuf + tcable1 + tcable2 tgr.(min-drive) = td – te(drive) tfr (min-drive) = 0 tg (min-write) = time_d

×

T – (tskew1 + tskew2 + tskew5) tf (min-write) = time_k

×

T – (tskew1 + tskew2 + tskew6) tL (max) = (time_d + time_k–2)

×

T – (tsu + tco + 2

× tbuf + 2

× tcable2)

120

Controlling

Variable time_m time_d time_k time_d, time_k time_d

— time_d time_k time_d, time_k i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Electrical Characteristics

ATA

Parameter tn, tj

—

Table 94. MDMA Read and Write Timing Parameters (continued)

Parameter from

Figure 76 ,

Figure 77 tkjn ton toff

Value tn= tj= tkjn = (max(time_k,. time_jn)

×

T – (tskew1 + tskew2 + tskew6) ton = time_on toff = time_off

×

T – tskew1

×

T – tskew1

Controlling

Variable time_jn

—

4.7.11.2

Ultra DMA (UDMA) Input Timing

Figure 78

shows timing when the UDMA in transfer starts,

Figure 79

shows timing when the UDMA in

host terminates transfer, Figure 80 shows timing when the UDMA in device terminates transfer, and

Table 95 lists the timing parameters for UDMA in burst.

Figure 78. UDMA In Transfer Starts Timing Diagram

Figure 79. UDMA In Host Terminates Transfer Timing Diagram

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

121

Electrical Characteristics

Figure 80. UDMA In Device Terminates Transfer Timing Diagram

Table 95. UDMA In Burst Timing Parameters

ATA

Parameter

Parameter from

Figure 78

,

Figure 79

,

Figure 80

Description Controlling Variable tack tenv tack tenv tack (min) = (time_ack

×

T) – (tskew1 + tskew2) tenv (min) = (time_env tenv (max) = (time_env

×

T) – (tskew1 + tskew2)

×

T) + (tskew1 + tskew2) tds – (tskew3) – ti_ds > 0 time_ack time_env tds tdh tds1 tdh1 tskew3, ti_ds, ti_dh should be low enough tdh – (tskew3) – ti_dh > 0 tcyc trp

— tmli tzah tdzfs tcvh

— tc1 trp tx1

1 tmli1 tzah tdzfs tcvh ton toff

2

(tcyc – tskew) > T trp (min) = time_rp

×

T – (tskew1 + tskew2 + tskew6)

(time_rp

×

T) – (tco + tsu + 3T + 2

× tbuf + 2

× tcable2) > trfs (drive) tmli1 (min) = (time_mlix + 0.4)

×

T tzah (min) = (time_zah + 0.4)

×

T tdzfs = (time_dzfs

×

T) – (tskew1 + tskew2) tcvh = (time_cvh

×

T) – (tskew1 + tskew2) ton = time_on

×

T – tskew1 toff = time_off

×

T – tskew1

T big enough time_rp time_rp time_mlix time_zah time_dzfs time_cvh

—

1

2

There is a special timing requirement in the ATA host that requires the internal DIOW to go only high 3 clocks after the last active edge on the DSTROBE signal. The equation given on this line tries to capture this constraint.

Make ton and toff big enough to avoid bus contention.

122 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Electrical Characteristics

4.7.11.3

UDMA Output Timing

Figure 81

shows timing when the UDMA out transfer starts,

Figure 82 shows timing when the UDMA out

host terminates transfer, Figure 83 shows timing when the UDMA out device terminates transfer, and

Table 96 lists the timing parameters for UDMA out burst.

Figure 81. UDMA Out Transfer Starts Timing Diagram

Figure 82. UDMA Out Host Terminates Transfer Timing Diagram

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

123

Electrical Characteristics tack tenv tdvs tdvh tcyc t2cyc trfs1

— tss tmli tli tli tli tcvh

—

ATA

Parameter

Figure 83. UDMA Out Device Terminates Transfer Timing Diagram

Table 96. UDMA Out Burst Timing Parameters tdvs tdvh tcyc

— trfs tdzfs tss tdzfs_mli tli1 tli2 tli3 tcvh ton toff

Parameter from

Figure 81

,

Figure 82

,

Figure 83

tack tenv

Value tack (min) = (time_ack

×

T) – (tskew1 + tskew2) tenv (min) = (time_env tenv (max) = (time_env

×

T) – (tskew1 + tskew2)

×

T) + (tskew1 + tskew2) tdvs = (time_dvs

×

T) – (tskew1 + tskew2) tdvs = (time_dvh

×

T) – (tskew1 + tskew2) tcyc = time_cyc

×

T – (tskew1 + tskew2) t2cyc = time_cyc

×

2

×

T trfs = 1.6

×

T + tsui + tco + tbuf + tbuf tdzfs = time_dzfs

×

T – (tskew1) tss = time_ss

×

T – (tskew1 + tskew2) tdzfs_mli =max (time_dzfs, time_mli)

×

T – (tskew1 + tskew2) tli1 > 0 tli2 > 0 tli3 > 0 tcvh = (time_cvh

×

T) – (tskew1 + tskew2) ton = time_on

×

T – tskew1 toff = time_off

×

T – tskew1

Controlling

Variable time_ack time_env time_dvs time_dvh time_cyc time_cyc

— time_dzfs time_ss

—

—

—

— time_cvh

—

124 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Electrical Characteristics

4.7.12

SIM (Subscriber Identification Module) Timing

This section describes the electrical parameters of the SIM module. Each SIM module interface consists of 12 signals (two separate ports each containing six signals). Typically a a port uses five signals.

The interface is designed to be used with synchronous SIM cards meaning the SIM module provides the clock used by the SIM card. The clock frequency is typically 372 times the Tx/Rxdata rate, however the

SIM module can work with CLK frequencies of 16 times the Tx/Rx data rate.

There is no timing relationship between the clock and the data. The clock that the SIM module provides to the SIM card is used by the SIM card to recover the clock from the data in the same manner as standard

UART data exchanges. All six signals (5 for bi-directional Tx/Rx) of the SIM module are asynchronous to each other.

There are no required timing relationships between signals in normal mode. The SIM card is initiated by the interface device; the SIM card responds with Answer to Reset. Although the SIM interface has no defined requirements, the ISO-7816 defines reset and power-down sequences. (For detailed information, see ISO-7816.)

Table 97 defines the general timing requirements for the SIM interface.

Table 97. SIM Timing Parameters, High Drive Strength

ID Parameter

SI1

SI2

SIM Clock Frequency (SIMx_CLKy)

1

,

SIM Clock Rise Time (SIMx_CLKy)

2

SIM Clock Fall Time (SIMx_CLKy)

3

SI3

SI4 SIM Input Transition Time

(SIMx_DATAy_RX_TX, SIMx_SIMPDy)

SI5 SIM I/O Rise Time / Fall

Time(SIMx_DATAy_RX_TX)

4

SI6 SIM RST Rise Time / Fall Time(SIMx_RSTy)

5

2

3

4

5

1

50% duty cycle clock

With C = 50 pF

With C = 50 pF

With Cin = 30 pF, Cout = 30 pF

With Cin = 30 pF

Symbol

S freq

S rise

S fall

S trans

Tr/Tf

Tr/Tf

Min

0.01

—

—

10

—

—

Max

25

0.09

×

(1/S freq

)

0.09

×

(1/S freq

)

25

1

1

Unit

MHz ns ns ns

µ s

µ s

1/SI1

SIMx_CLKy

SI3 SI2

Figure 84. SIM Clock Timing Diagram

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

125

Electrical Characteristics

4.7.12.1

Reset Sequence

4.7.12.1.1

Cards with internal reset

The sequence of reset for this kind of SIM Cards is as follows (see Figure 85 ):

• After power up, the clock signal is enabled on SIMx_CLKy(time T0)

• After 200 clock cycles, RX must be high.

• The card must send a response on RX acknowledging the reset between 400 and 40000 clock cycles after T0.

SIMx_SVENy

SIMx_CLKy

SIMx_DATAy_RX_TX response

1

T0

2

400 clock cycles <

1

< 200 clock cycles

2 < 40000 clock cycles

Figure 85. Internal-Reset Card Reset Sequence

4.7.12.1.2

Cards with Active Low Reset

The sequence of reset for this kind of card is as follows (see

Figure 86

):

• After power-up, the clock signal is enabled on SIMx_CLKy (time T0)

• After 200 clock cycles, SIMx_DATAy_RX_TX must be high.

• SIMx_RSTy must remain Low for at least 40000 clock cycles after T0 (no response is to be received on RX during those 40000 clock cycles)

• SIMx_RSTy is set High (time T1)

• SIMx_RSTy must remain High for at least 40000 clock cycles after T1 and a response must be received on SIMx_DATAy_RX_TX between 400 and 40000 clock cycles after T1.

126 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Electrical Characteristics

SIMx_SVENy

SIMx_RSTy

SIMx_CLKy

SIMx_DATAy_RX_TX response

1

2

T0

3 3

T1

400 clock cycles <

400000 clock cycles <

Figure 86. Active-Low-Reset Cards Reset Sequence

3

1

< 200 clock cycles

2 < 40000 clock cycles

4.7.12.2

Power Down Sequence

Power down sequence for SIM interface is as follows:

• SIMx_SIMPDy port detects the removal of the SIM Card

• SIMx_RSTy goes Low

• SIMx_CLKy goes Low

• SIMx_DATAy_RX_TX goes Low

• SIMx_SVENy goes Low

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

127

Electrical Characteristics

Each of these steps is done in one CKIL period (usually 32 kHz). Power-down can be started because of a SIM Card removal detection or launched by the processor.

Figure 87 and Table 98 shows the usual

timing requirements for this sequence, with Fckil = CKIL frequency value.

SI10

SIMx_SIMPDy

SIMx_RSTy

SI7

SIMx_CLKy

SI8

SIMx_DATAy_RX_TX

SI9

SIMx_SVENy

Figure 87. SmartCard Interface Power Down AC Timing

Table 98. Timing Requirements for Power Down Sequence

ID Parameter

SI7 SIM reset to SIM clock stop

SI8 SIM reset to SIM TX data low

SI9 SIM reset to SIM voltage enable low

SI10 SIM presence detect to SIM reset low

Symbol

S rst2clk

S rst2dat

S rst2ven

S pd2rst

Min

0.9

×

1/Fckil

1.8

×

1/Fckil

2.7

×

1/Fckil

0.9

×

1/Fckil

Max

1.1

×

1/Fckil

2.2

×

1/Fckil

3.3

×

1/Fckil

1.1

×

1/Fckil

Unit ns ns ns ns

128 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Electrical Characteristics

4.7.13

SCAN JTAG Controller (SJC) Timing Parameters

Figure 88 depicts the SJC test clock input timing. Figure 89

depicts the SJC boundary scan timing.

Figure 91 depicts the TRST timing with respect to TCK. Figure 90 depicts the SJC test access port. Signal

parameters are listed in

Table 99 .

SJ1

TCK

(Input)

VIH

SJ2

VM

SJ2

VM

VIL

SJ3

SJ3

Figure 88. Test Clock Input Timing Diagram

TCK

(Input)

Data

Inputs

VIL

VIH

SJ4

Input Data Valid

SJ5

SJ6

Data

Outputs

Output Data Valid

SJ7

Data

Outputs

SJ6

Data

Outputs

Output Data Valid

Figure 89. Boundary Scan (JTAG) Timing Diagram

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

129

Electrical Characteristics

TCK

(Input)

VIL

TDI

TMS

(Input)

TDO

(Output)

TDO

(Output)

TDO

(Output)

SJ10

SJ11

SJ8

Input Data Valid

VIH

SJ9

Output Data Valid

SJ10

Output Data Valid

Figure 90. Test Access Port Timing Diagram

130

ID

SJ4

SJ5

SJ6

SJ7

SJ8

SJ0

SJ1

SJ2

SJ3

TRST

(Input)

TCK

(Input)

SJ13

SJ12

Figure 91. TRST Timing Diagram

Table 99. JTAG Timing

Parameter

TCK frequency of operation 1/(3•T

DC

)

1

TCK cycle time in crystal mode

TCK clock pulse width measured at V

M

2

TCK rise and fall times

Boundary scan input data set-up time

Boundary scan input data hold time

TCK low to output data valid

TCK low to output high impedance

TMS, TDI data set-up time

1,2

All Frequencies

Min

5

24

—

—

5

0.001

45

22.5

—

Max

—

—

40

40

—

22

—

—

3

Unit ns ns ns ns ns

MHz ns ns ns i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Electrical Characteristics

Table 99. JTAG Timing (continued)

ID Parameter

1,2

SJ9 TMS, TDI data hold time

SJ10 TCK low to TDO data valid

SJ11 TCK low to TDO high impedance

SJ12 TRST assert time

SJ13 TRST set-up time to TCK low

1

2

T

DC

= target frequency of SJC

V

M

= mid-point voltage

All Frequencies

Min

25

—

—

100

40

Max

—

44

44

—

—

Unit

4.7.14

SPDIF Timing Parameters

Table 100

shows the timing parameters for the Sony/Philips Digital Interconnect Format (SPDIF).

Table 100. SPDIF Timing

All Frequencies

Characteristics Symbol Unit

Min Max

SPDIFOUT output (load = 50 pF)

• Skew

• Transition rising

• Transition falling

SPDIFOUT output (load = 30 pF)

• Skew

• Transition rising

• Transition falling

—

— —

—

—

—

—

—

1.5

24.2

31.3

1.5

13.6

18.0

ns ns ns ns ns ns ns

4.7.15

SSI Timing Parameters

This section describes the timing parameters of the SSI module. The connectivity of the serial synchronous interfaces is summarized in

Table 101 .

Table 101. AUDMUX Port Allocation

Port

AUDMUX port 1

AUDMUX port 2

AUDMUX port 3

AUDMUX port 4

AUDMUX port 5

Signal Nomenclature

SSI 1

SSI 2

AUD3

AUD4

AUD5

Type and Access

Internal

Internal

External—AUD3 I/O

External—EIM or CSPI1 I/O via IOMUX

External—EIM or SD1 I/O via IOMUX

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

131

Electrical Characteristics

Port

AUDMUX port 6

AUDMUX port 7

Table 101. AUDMUX Port Allocation (continued)

Signal Nomenclature

AUD6

SSI 3

Type and Access

External—EIM or DISP2 via IOMUX

Internal

NOTE

• The terms WL and BL used in the timing diagrams and tables refer to

Word Length (WL) and Bit Length (BL).

• The SSI timing diagrams use generic signal names wherein the names used in the i.MX51 Multimedia Applications Processor Reference

Manual (MCIMX51RM) are channel specific signal names. For example, a channel clock referenced in the IOMUXC chapter as

AUD3_TXC appears in the timing diagram as TXC.

4.7.15.1

SSI Transmitter Timing with Internal Clock

Figure 92

depicts the SSI transmitter internal clock timing and

Table 102

lists the timing parameters for the SSI transmitter internal clock.

.

SS1

SS5 SS3

SS2 SS4

TXC

(Output)

SS6 SS8

TXFS (bl)

(Output)

SS10 SS12

TXFS (wl)

(Output)

SS14

SS15

SS16

SS17

SS18

TXD

(Output)

SS43

SS42

SS19

RXD

(Input)

Note: SRXD input in synchronous mode only

Figure 92. SSI Transmitter Internal Clock Timing Diagram

132 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

ID

SS12

SS14

SS15

SS16

SS17

SS18

SS19

SS1

SS2

SS3

SS4

SS5

SS6

SS8

SS10

SS42

SS43

SS52

Electrical Characteristics

Table 102. SSI Transmitter Timing with Internal Clock

Parameter Min

(Tx/Rx) CK clock period

(Tx/Rx) CK clock high period

(Tx/Rx) CK clock rise time

(Tx/Rx) CK clock low period

(Tx/Rx) CK clock fall time

(Tx) CK high to FS (bl) high

(Tx) CK high to FS (bl) low

(Tx) CK high to FS (wl) high

(Tx) CK high to FS (wl) low

(Tx/Rx) Internal FS rise time

(Tx/Rx) Internal FS fall time

(Tx) CK high to STXD valid from high impedance

(Tx) CK high to STXD high/low

(Tx) CK high to STXD high impedance

STXD rise/fall time

Internal Clock Operation

Synchronous Internal Clock Operation

SRXD setup before (Tx) CK falling

SRXD hold after (Tx) CK falling

Loading

30

0.0

—

—

—

—

—

—

—

—

—

—

—

—

81.4

36.0

—

36.0

Max

—

—

25.0

NOTE

• All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync

(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal

STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures.

• All timings are on Audiomux Pads when SSI is being used for data transfer.

• The terms WL and BL refer to Word Length (WL) and Bit Length (BL).

• ”Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.

• For internal Frame Sync operation using external clock, the FS timing is same as that of Tx Data (for example, during AC97 mode of operation).

15.0

6.0

6.0

15.0

15.0

15.0

6.0

6.0

15.0

15.0

15.0

—

—

6.0

—

Unit ns ns pF ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

133

Electrical Characteristics

4.7.15.2

SSI Receiver Timing with Internal Clock

Figure 93

depicts the SSI receiver internal clock timing and

Table 103

lists the timing parameters for the

SSI receiver internal clock.

SS1

SS2

SS5

SS4

SS3

TXC

(Output)

SS7 SS9

TXFS (bl)

(Output)

TXFS (wl)

(Output)

RXD

(Input)

SS11

SS20

SS21

SS48

SS47 SS51

SS50

SS49

RXC

(Output)

ID

SS1

SS2

SS3

SS4

SS5

SS7

SS9

SS11

SS13

SS20

SS21

Figure 93. SSI Receiver Internal Clock Timing Diagram

Table 103. SSI Receiver Timing with Internal Clock

Min Parameter

Internal Clock Operation

(Tx/Rx) CK clock period

(Tx/Rx) CK clock high period

(Tx/Rx) CK clock rise time

(Tx/Rx) CK clock low period

(Tx/Rx) CK clock fall time

(Rx) CK high to FS (bl) high

(Rx) CK high to FS (bl) low

(Rx) CK high to FS (wl) high

(Rx) CK high to FS (wl) low

SRXD setup time before (Rx) CK low

SRXD hold time after (Rx) CK low

—

—

—

—

81.4

36.0

—

36.0

—

30

0.0

SS13

Max

6.0

15.0

15.0

15.0

—

—

6.0

—

15.0

—

—

Unit ns ns ns ns ns ns ns ns ns ns ns

134 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

ID

SS47

SS48

SS49

SS50

SS51

Electrical Characteristics

Table 103. SSI Receiver Timing with Internal Clock (continued)

Parameter Min

Oversampling Clock Operation

Oversampling clock period

Oversampling clock high period

Oversampling clock rise time

Oversampling clock low period

Oversampling clock fall time

15.04

6.0

—

6.0

—

Max

—

—

3.0

—

3.0

Unit ns ns ns ns ns

NOTE

• All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync

(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal

STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures.

• All timings are on Audiomux Pads when SSI is being used for data transfer.

• “Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.

• The terms WL and BL refer to Word Length (WL) and Bit Length (BL).

• For internal Frame Sync operation using external clock, the FS timing is same as that of Tx Data (for example, during AC97 mode of operation).

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

135

Electrical Characteristics

4.7.15.3

SSI Transmitter Timing with External Clock

Figure 94

depicts the SSI transmitter external clock timing and

Table 104

lists the timing parameters for the SSI transmitter external clock.

SS22

SS23 SS25

SS26 SS24

TXC

(Input)

SS27 SS29

TXFS (bl)

(Input)

TXFS (wl)

(Input)

TXD

(Output)

SS31

SS37 SS38

SS39

SS33

SS45

SS44

RXD

(Input)

Note: SRXD Input in Synchronous mode only

SS46

Figure 94. SSI Transmitter External Clock Timing Diagram

Table 104. SSI Transmitter Timing with External Clock

Parameter Min ID

External Clock Operation

SS22 (Tx/Rx) CK clock period

SS23 (Tx/Rx) CK clock high period

SS24 (Tx/Rx) CK clock rise time

SS25 (Tx/Rx) CK clock low period

SS26 (Tx/Rx) CK clock fall time

SS27 (Tx) CK high to FS (bl) high

SS29 (Tx) CK high to FS (bl) low

SS31 (Tx) CK high to FS (wl) high

SS33 (Tx) CK high to FS (wl) low

SS37 (Tx) CK high to STXD valid from high impedance

SS38 (Tx) CK high to STXD high/low

81.4

36.0

—

36.0

—

–10.0

10.0

–10.0

10.0

—

—

Max

6.0

15.0

—

15.0

—

—

6.0

—

—

15.0

30

Unit ns ns ns ns ns ns ns ns ns ns ns

136 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Electrical Characteristics

Table 104. SSI Transmitter Timing with External Clock (continued)

ID Parameter Min

SS39 (Tx) CK high to STXD high impedance

Synchronous External Clock Operation

—

SS44 SRXD setup before (Tx) CK falling

SS45 SRXD hold after (Tx) CK falling

SS46 SRXD rise/fall time

10.0

2.0

—

Max

15.0

—

—

6.0

Unit ns ns ns ns

NOTE

• All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync

(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal

STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures.

• All timings are on Audiomux Pads when SSI is being used for data transfer.

• “Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.

• The terms WL and BL refer to Word Length (WL) and Bit Length (BL).

• For internal Frame Sync operation using external clock, the FS timing is same as that of Tx Data (for example, during AC97 mode of operation).

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

137

Electrical Characteristics

4.7.15.4

SSI Receiver Timing with External Clock

Figure 95

depicts the SSI receiver external clock timing and

Table 105 lists the timing parameters for the

SSI receiver external clock.

SS22

SS23

SS26

SS25

SS24

TXC

(Input)

SS28

TXFS (bl)

(Input)

TXFS (wl)

(Input)

RXD

(Input)

SS30

SS32

SS35

SS40

SS41

SS36

SS34

ID

SS22

SS23

SS24

SS25

SS26

SS28

SS30

SS32

SS34

SS35

SS36

SS40

SS41

Figure 95. SSI Receiver External Clock Timing Diagram

Table 105. SSI Receiver Timing with External Clock

Min Parameter

External Clock Operation

(Tx/Rx) CK clock period

(Tx/Rx) CK clock high period

(Tx/Rx) CK clock rise time

(Tx/Rx) CK clock low period

(Tx/Rx) CK clock fall time

(Rx) CK high to FS (bl) high

(Rx) CK high to FS (bl) low

(Rx) CK high to FS (wl) high

(Rx) CK high to FS (wl) low

(Tx/Rx) External FS rise time

(Tx/Rx) External FS fall time

SRXD setup time before (Rx) CK low

SRXD hold time after (Rx) CK low

—

–10

10

–10

81.4

36

—

36

10

—

—

10

2

Max

6.0

15.0

—

15.0

—

—

6.0

—

—

6.0

6.0

—

—

Unit ns ns ns ns ns ns ns ns ns ns ns ns ns

138 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Electrical Characteristics

NOTE

• All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync

(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal

STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures.

• All timings are on Audiomux Pads when SSI is being used for data transfer.

• “Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.

• The terms WL and BL refer to Word Length (WL) and Bit Length (BL).

• For internal Frame Sync operation using external clock, the FS timing is same as that of Tx Data (for example, during AC97 mode of operation).

4.7.16

UART

Table 106

shows the UART I/O configuration based on which mode is enabled.

Table 106. UART I/O Configuration vs. Mode

Port

RTS

CTS

DTR

DSR

DCD

RI

TXD_MUX

RXD_MUX

DTE Mode

Direction

Output

Input

Output

Input

Input

Input

Input

Output

Description

RTS from DTE to DCE

CTS from DCE to DTE

DTR from DTE to DCE

DSR from DCE to DTE

DCD from DCE to DTE

RING from DCE to DTE

Serial data from DCE to DTE

Serial data from DTE to DCE

DCE Mode

Direction

Input

Output

Input

Output

Output

Output

Output

Input

Description

RTS from DTE to DCE

CTS from DCE to DTE

DTR from DTE to DCE

DSR from DCE to DTE

DCD from DCE to DTE

RING from DCE to DTE

Serial data from DCE to DTE

Serial data from DTE to DCE

4.7.16.1

UART Electrical

This section describes the electrical information of the UART module.

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

139

Electrical Characteristics

4.7.16.1.1

UART RS-232 Serial Mode Timing

UART Transmitter

Figure 96

depicts the transmit timing of UART in RS-232 serial mode, with 8 data bit/1 stop bit format.

Table 107

lists the UART RS-232 serial mode transmit timing characteristics.

Figure 96. UART RS-232 Serial Mode Transmit Timing Diagram

Table 107. UART RS-232 Serial Mode Transmit Timing Diagram

ID Parameter Symbol Min Max Units

UA1 Transmit Bit Time t

Tbit

1/F baud_rate

1

-T ref_clk

2

1/F baud_rate

+T ref_clk

1

2

1/F baud_rate

: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.

T ref_clk

: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider).

—

UART Receiver

Figure 97

depicts the RS-232 serial mode receive timing, with 8 data bit/1 stop bit format.

Table 108 lists

serial mode receive timing characteristics.

Figure 97. UART RS-232 Serial Mode Receive Timing Diagram

Table 108. UART RS-232 Serial Mode Transmit Timing Diagram

ID Parameter Symbol Min Max Units

1

2

UA1 Receive Bit Time

1 t

Rbit

1/F baud_rate

2

-1/(16

×F baud_rate

) 1/F baud_rate

+1/(16

×F baud_rate

) —

The UART receiver can tolerate 1/(16

×Fbaud_rate) tolerance in each bit. But accumulation tolerance in one frame must not exceed 3/(16

×Fbaud_rate).

F baud_rate

: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.

4.7.16.1.2

UART IrDA Mode Timing

The following subsections give the UART transmit and receive timings in IrDA mode.

140 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Electrical Characteristics

UART IrDA Mode Transmitter

Figure 98

depicts the UART IrDA mode transmit timing, with 8 data bit/1 stop bit format.

Table 109 lists

the transmit timing characteristics.

Figure 98. UART IrDA Mode Transmit Timing Diagram

Table 109. IrDA Mode Transmit Timing Parameters

ID Parameter Symbol Min Max

UA3 Transmit Bit Time in

IrDA mode t

TIRbit

1/F baud_rate

1

-T ref_clk

2

1/F baud_rate

+T ref_clk

UA4 Transmit IR Pulse

Duration t

TIRpulse

(3/16)

×(1F baud_rate

)-T ref_clk

(3/16)

×(1F baud_rate

)+T ref_clk

1

2

F baud_rate

: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.

Tref_clk: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider).

Units

—

—

UART IrDA Mode Receiver

Figure 99 depicts the UART IrDA mode receive timing, with 8 data bit/1 stop bit format. Table 110 lists

the receive timing characteristics.

Figure 99. UART IrDA Mode Receive Timing Diagram

Table 110. IrDA Mode Receive Timing Parameters

ID Parameter Symbol Min Max Units

UA5 Receive Bit Time

IrDA mode

1

in t

RIRbit

1/F baud_rate

2

-

1/(16

×F baud_rate

)

1/F baud_rate

+

1/(16

×F baud_rate

)

(5/16)

×(1/F baud_rate

)

—

UA6 Receive IR Pulse

Duration t

RIRpulse

1.41 us —

1

The UART receiver can tolerate 1/(16

×F not exceed 3/(16

×F baud_rate

).

baud_rate

) tolerance in each bit. But accumulation tolerance in one frame must

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

141

Electrical Characteristics

2

Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.

4.7.17

USBOH3 Parameters

This section describes the electrical parameters of the USB OTG port and USB HOST ports. For on-chip

USB PHY parameters see

Section 4.7.19, “USB PHY Parameters .”

4.7.17.1

USB Serial Interface

In order to support four serial different interfaces, the USB serial transceiver can be configured to operate in one of four modes:

• DAT_SE0 bidirectional, 3-wire mode

• DAT_SE0 unidirectional, 6-wire mode

• VP_VM bidirectional, 4-wire mode

• VP_VM unidirectional, 6-wire mode

The USB controller does not support ULPI Serial mode. Only the legacy serial mode is supported.

Table 111

shows the serial mode signal map for 6-pin Full speed/Low speed (FsLs) serial mode.

Table 112

shows the serial mode signal map for 3-pin FsLs serial mode.

Table 111. Serial Mode Signal Map for 6-pin FsLs Serial Mode

Signal tx_enable tx_dat tx_se0 int rx_dp rx_dm rx_rcv

Reserved

Maps to data(0) data(1) data(2) data(3) data(4) data(5) data(6) data(7)

Direction

In

In

In

Out

Out

Out

Out

Out

Description

Active high transmit enable

Transmit differential data on D+/D–

Transmit single-ended zero on D+/D–

Active high interrupt indication

Must be asserted whenever any unmasked interrupt occurs

Single-ended receive data from D+

Single-ended receive data from D–

Differential receive data from D+/D–

Reserved The PHY must drive this signal low

Signal tx_enable dat se0 int

Maps to data(0) data(1) data(2) data(3)

Table 112. Serial Mode Signal Map for 3-pin FsLs Serial Mode

Direction

In

I/O

I/O

Out

Description

Active high transmit enable

Transmit differential data on D+/D– when tx_enable is high

Receive differential data on D+/D– when tx_enable is low

Transmit single-ended zero on D+/D– when tx_enable is high

Receive single-ended zero on D+/D– when tx_enable is low

Active high interrupt indication

Must be asserted whenever any unmasked interrupt occurs

142 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Electrical Characteristics

4.7.17.1.1

USB DAT_SE0 Bi-Directional Mode

Table 113 shows the signal definitions in DAT_SE0 bi-directional mode and Figure 100 shows the USB

transmit waveform in DAT_SE0 bi-directional mode.

Table 113. Signal Definitions—DAT_SE0 Bi-Directional Mode

Name

USB_TXOE_B

USB_DAT_VP

USB_SE0_VM

Direction

Out

Out

In

Out

In

Signal Description

Transmit enable, active low

TX data when USB_TXOE_B is low

Differential RX data when USB_TXOE_B is high

SE0 drive when USB_TXOE_B is low

SE0 RX indicator when USB_TXOE_B is high

Transmit

USB_TXOE_B

US3

USB_DAT_VP

USB_SE0_VM

US1

US4

US2

Figure 100. USB Transmit Waveform in DAT_SE0 Bi-Directional Mode

Figure 101

shows the USB receive waveform in DAT_SE0 bi-directional mode and

Table 114

shows the definitions of USB receive waveform in DAT_SE0 bi-directional mode.

Receive

USB_TXOE_B

USB_DAT_VP

USB_SE0_VM

US7 US8

USB_SE0_VM

Figure 101. USB Receive Waveform in DAT_SE0 Bi-Directional Mode

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

143

Electrical Characteristics

ID

Table 114. Definitions of USB Receive Waveform in DAT_SE0 Bi-Directional Mode

Parameter

US1 TX Rise/Fall Time

US2 TX Rise/Fall Time

US3 TX Rise/Fall Time

US4 TX Duty Cycle

US7 RX Rise/Fall Time

US8 RX Rise/Fall Time

Signal Name

USB_DAT_VP

USB_SE0_VM

USB_TXOE_B

USB_DAT_VP

USB_DAT_VP

USB_SE0_VM

Direction

Out

Out

Out

Out

In

In

Min

—

—

—

49.0

—

—

Max

5.0

5.0

5.0

51.0

3.0

3.0

Unit ns ns ns

% ns ns

Conditions/

Reference Signal

50 pF

50 pF

50 pF

—

35 pF

35 pF

4.7.17.1.2

USB DAT_SE0 Unidirectional Mode

Table 115

shows the signal definitions in DAT_SE0 unidirectional mode

Table 115. Signal Definitions—DAT_SE0 Unidirectional Mode

Name

USB_TXOE_B

USB_DAT_VP

USB_SE0_VM

USB_VP1

USB_VM1

USB_RCV

Direction

Out

Out

Out

In

In

In

Signal Description

Transmit enable, active low

TX data when USB_TXOE_B is low

SE0 drive when USB_TXOE_B is low

Buffered data on DP when USB_TXOE_B is high

Buffered data on DM when USB_TXOE_B is high

Differential RX data when USB_TXOE_B is high

Figure 102

and

Figure 103 shows the USB transmit/receive waveform in DAT_SE0 uni-directional mode

respectively.

US11

Transmit

USB_TXOE_B

USB_DAT_VP

USB_SE0_VM

US9

US12

US10

Figure 102. USB Transmit Waveform in DAT_SE0 Uni-directional Mode

144 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Electrical Characteristics

Receive

USB_TXOE_B

USB_DAT_VP

USB_RCV

US16

US15/US17

USB_SE0_VM

Figure 103. USB Receive Waveform in DAT_SE0 Uni-directional Mode

Table 116

shows the USB port timing specification in DAT_SE0 uni-directional mode.

Table 116. USB Port Timing Specification in DAT_SE0 Uni-Directional Mode

ID Parameter

US9 TX Rise/Fall Time

US10 TX Rise/Fall Time

US11 TX Rise/Fall Time

US12 TX Duty Cycle

US15 RX Rise/Fall Time

US16 RX Rise/Fall Time

US17 RX Rise/Fall Time

Signal Name

USB_DAT_VP

USB_SE0_VM

USB_TXOE_B

USB_DAT_VP

USB_VP1

USB_VM1

USB_RCV

Signal

Source

In

In

In

Out

Out

Out

Out

Min

—

—

—

—

—

—

49.0

Max

5.0

5.0

5.0

51.0

3.0

3.0

3.0

Unit ns ns ns ns ns ns

%

Condition/

Reference Signal

50 pF

50 pF

50 pF

—

35 pF

35 pF

35 pF

4.7.17.1.3

USB VP_VM Bi-Directional Mode

Table 117

shows the signal definitions in VP_VM bi-directional mode.

Figure 104

and

Figure 105

shows the USB transmit/receive waveform in VP_VM bi-directional mode respectively.

Table 117. Signal Definitions—VP_VM Bi-Directional Mode

Name

USB_TXOE_B

USB_DAT_VP

USB_SE0_VM

USB_RCV

Direction

Out

Out (Tx)

In (Rx)

Out (Tx)

In (Rx)

In

Signal Description

Transmit enable, active low

TX VP data when USB_TXOE_B is low

RX VP data when USB_TXOE_B is high

TX VM data when USB_TXOE_B low

RX VM data when USB_TXOE_B high

Differential RX data

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

145

Electrical Characteristics

Transmit

USB_TXOE_B

USB_DAT_VP

USB_SE0_VM

US20

US18

US21 US19

Receive

USB_DAT_VP

US22 US22

Figure 104. USB Transmit Waveform in VP_VM Bi-Directional Mode

US26

USB_SE0_VM

US28 US27

USB_RCV

US29

Figure 105. USB Receive Waveform in VP_VM Bi-Directional Mode

Table 118

shows the USB port timing specification in VP_VM bi-directional mode.

Table 118. USB Port Timing Specification in VP_VM Bi-directional Mode

ID Parameter

US18 TX Rise/Fall Time

US19 TX Rise/Fall Time

US20 TX Rise/Fall Time

US21 TX Duty Cycle

US22 TX Overlap

Signal Name

USB_DAT_VP

USB_SE0_VM

USB_TXOE_B

USB_DAT_VP

USB_SE0_VM

Direction Min Max Unit

Out

Out

Out

Out

Out

—

—

—

49.0

–3.0

5.0

5.0

5.0

51.0

3.0

ns ns ns

% ns

Condition/Reference Signal

50 pF

50 pF

50 pF

—

USB_DAT_VP

146 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Electrical Characteristics

Table 118. USB Port Timing Specification in VP_VM Bi-directional Mode (continued)

ID Parameter

US26 RX Rise/Fall Time

US27 RX Rise/Fall Time

US28 RX Skew

US29 RX Skew

Signal Name

USB_DAT_VP

USB_SE0_VM

USB_DAT_VP

USB_RCV

Direction Min Max Unit

In

In

In

In

—

—

–4.0

–6.0

3.0

3.0

4.0

2.0

ns ns ns ns

Condition/Reference Signal

35 pF

35 pF

USB_SE0_VM

USB_DAT_VP

4.7.17.1.4

USB VP_VM Uni-Directional Mode

Table 119 shows the signal definitions in VP_VM uni-directional mode. Figure 106 and

Figure 107

shows the USB transmit/receive waveform in VP_VM uni-directional mode respectively.

Table 119. USB Signal Definitions—VP_VM Uni-Directional Mode

Name

USB_TXOE_B

USB_DAT_VP

USB_SE0_VM

USB_VP1

USB_VM1

USB_RCV

Direction

Out

Out

Out

In

In

In

Signal Description

Transmit enable, active low

TX VP data when USB_TXOE_B is low

TX VM data when USB_TXOE_B is low

RX VP data when USB_TXOE_B is high

RX VM data when USB_TXOE_B is high

Differential RX data

Transmit

US32

USB_TXOE_B

USB_DAT_VP

USB_SE0_VM

US30

US33 US31

US34 US34

Figure 106. USB Transmit Waveform in VP_VM Unidirectional Mode

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

147

Electrical Characteristics

Receive

USB_TXOE_B

USB_VP1

US38

USB_VM1

USB_RCV

US40

US39

US41

Figure 107. USB Receive Waveform in VP_VM Uni-directional Mode

Table 120

shows the USB port timing specification in VP_VM uni-directional mode.

Table 120. USB Timing Specification in VP_VM Unidirectional Mode

ID Parameter

US30 TX Rise/Fall Time

US31 TX Rise/Fall Time

US32 TX Rise/Fall Time

US33 TX Duty Cycle

US34 TX Overlap

US38 RX Rise/Fall Time

US39 RX Rise/Fall Time

US40 RX Skew

US41 RX Skew

Signal

USB_DAT_VP

USB_SE0_VM

USB_TXOE_B

USB_DAT_VP

USB_SE0_VM

USB_VP1

USB_VM1

USB_VP1

USB_RCV

Direction Min Max Unit

Out

In

In

In

In

Out

Out

Out

Out

—

—

—

49.0

–3.0

—

—

–6.0

5.0

5.0

5.0

51.0

3.0

3.0

3.0

–4.0

4.0

2.0

ns ns ns

% ns ns ns ns ns

Conditions / Reference Signal

50 pF

50 pF

50 pF

—

USB_DAT_VP

35 pF

35 pF

USB_VM1

USB_VP1

148 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Electrical Characteristics

4.7.18

USB Parallel Interface Timing

Electrical and timing specifications of Parallel Interface are presented in the subsequent sections.

Table 121

shows the signal definitions in parallel mode.

Figure 108

shows the USB transmit/receive waveform in parallel mode.

Table 122

shows the USB timing specification for ULPI parallel mode.

Table 121. Signal Definitions—Parallel Interface (Normal ULPI)

Name

USB_Clk

USB_Data[7:0]

USB_Dir

USB_Stp

USB_Nxt

Direction

In

I/O

In

Out

In

Signal Description

Interface clock. All interface signals are synchronous to Clock.

Bi-directional data bus, driven low by the link during idle. Bus ownership is determined by Dir.

Direction. Control the direction of the Data bus.

Stop. The link asserts this signal for 1 clock cycle to stop the data stream currently on the bus.

Next. The PHY asserts this signal to throttle the data.

USB_Clk

USB_Dir/Nxt

US15

US15

USB_Data

USB_Stp

US16

US16

US17 US17

ID

Figure 108. USB Transmit/Receive Waveform in Parallel Mode

Table 122. USB Timing Specification for ULPI Parallel Mode

Parameter Min

US15 Setup Time (Dir, Nxt in, Data in)

US16 Hold Time (Dir, Nxt in, Data in)

US17 Output delay Time (Stp out, Data out) for H3 routed to DISP2 I/O

1 and H1

US17 Output delay Time (Stp out, Data out) for H2

1

H3 routed to NANDF I/O is recommended for Full and Low-Speed use only.

—

6

0

—

Max

—

—

9

11

Unit ns ns ns

Conditions/

Reference Signal

10 pF

10 pF

10 pF ns 10 pF

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

149

Electrical Characteristics

4.7.19

USB PHY Parameters

This section describes the USB PHY parameters.

4.7.19.1

USB PHY AC Parameters

Table 123

lists the AC timing parameters for USB PHY.

Table 123. USB PHY AC Timing Parameters

Parameter trise tfall

Jitter

Conditions

1.5 Mbps

12 Mbps

480 Mbps

1.5 Mbps

12 Mbps

480 Mbps

1.5 Mbps

12 Mbps

480 Mbps

Min

75

4

0.5

75

4

0.5

—

Typ

—

—

—

Max

300

20

300

20

10

1

0.2

4.7.19.2

USB PHY Additional Electrical Parameters

Table 124

lists the parameters for additional electrical characteristics for USB PHY.

Table 124. Additional Electrical Characteristics for USB PHY

Parameter

Vcm DC

(dc level measured at receiver connector)

Crossover Voltage

Power supply ripple noise

(analog 3.3 V)

Power supply ripple noise

(analog 2.5 V)

Power supply ripple noise

(Digital 1.2)

Conditions

HS Mode

LS/FS Mode

LS Mode

FS Mode

<160 MHz

<1.2 MHz

>1.2 MHz

All conditions

Min

–0.05

0.8

1.3

1.3

–50

–10

–50

–50

Typ

—

—

0

0

0

0

4.7.19.3

USB PHY System Clocking (SYSCLK)

Table 125

lists the USB PHY system clocking parameters.

Table 125. USB PHY System Clocking Parameters

Parameter

Clock deviation

Rise/fall time

Conditions

—

—

Min

–150

—

Typ

—

—

Max

150

200

Max

0.5

2.5

2

2

50

10

50

50

Unit ns ns ns

Unit ppm ps

Unit

V

V mV mV mV

150 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Parameter

Jitter (peak-peak)

Jitter (peak-peak)

Duty-cycle

Package Information and Contact Assignments

Table 125. USB PHY System Clocking Parameters (continued)

Conditions

<1.2 MHz

>1.2 MHz

—

Min

0

0

40

Typ

—

—

—

Max

50

100

60

Unit ps ps

%

4.7.19.4

USB PHY Voltage Thresholds

Table 126

lists the USB PHY voltage thresholds.

Table 126. VBUS Comparators Thresholds

Parameter Conditions

A-Device Session Valid

B-Device Session Valid

—

—

B-Device Session End —

VBUS Valid Comparator Threshold

1

—

1

For VBUS maximum rating, see

Table 11 on page 17

Min

0.8

0.8

0.2

4.4

Typ

1.4

1.4

0.45

4.6

Max

2.0

4.0

0.8

4.75

Unit

V

V

V

V

5 Package Information and Contact Assignments

This section includes the contact assignment information and mechanical package drawing.

5.1

19 x 19 mm Package Information

This section contains the outline drawing, signal assignment map, ground/power/reference ID (by ball grid location) for the 19

× 19 mm, 0.8 mm pitch package.

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

151

Package Information and Contact Assignments

5.1.1

BGA—Case 2017, 19 x 19 mm, 0.8 mm Pitch

Figure 109

shows the top view, bottom view, and side view of the 19

×19 mm package.

152

Figure 109. 19 x 19 mm Package: Case 2017-01—0.8 mm Pitch i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Package Information and Contact Assignments

5.1.1.1

19 x 19 mm Package Drawing Notes

5

4

3

2

1

The following notes apply to

Figure 109 .

All dimensions in millimeters.

Dimensioning and tolerancing per ASME Y14.5M-1994.

Maximum solder ball diameter measured parallel to Datum A.

Datum A, the seating plane, is determined by the spherical crowns of the solder balls.

Parallelism measurement shall exclude any effect of mark on top surface of package.

5.1.2

19 x 19 mm Signal Assignments, Power Rails, and I/O

Table 127

shows the device connection list and Table 128

displays an alpha-sorted list of the signal assignments including associated power supplies.

5.1.2.1

19 x 19 mm Ground, Power, Sense, and Reference Contact Assignments

Table 127

shows the device connection list for ground, power, sense, and reference contact signals alpha-sorted by name.

Table 127. 19 x 19 mm Ground, Power, Sense, and Reference Contact Assignments

Contact Name Contact Assignment

AHVDDRGB

AHVSSRGB

GND

GND_ANA_PLL_A

GND_ANA_PLL_B

GND_DIG_PLL_A

GND_DIG_PLL_B

NGND_OSC

NGND_TV_BACK

NGND_USBPHY

NVCC_EMI

Y18, AA18

Y19, AA19

A1 , A23, G5, H9, J8, J9, J10, J12, J13, J14, K8, K9, K10, K11, K12, K13, K14, L8, L9, L10, L11,L12,

L13, L14, M9, M10, M11, M12, M13, M14, M15, N8, N9, N10, N11, N12, N13, N14, N15, N16, P8,

P9, P10, P11, P12, P13, P14, P15, R8, R9, R10, R11,R12, R13, R14, R15, R16, T5, T16, AC1,

AC21, AC23

U7

U17

T7

V18

V17

T15

L16

U8, U9, U10, U11, U12, V7

NVCC_EMI_DRAM H6, J6, K6, L6, M6, N6, P6, R6, T6

NVCC_HS10 M16

NVCC_HS4_1

NVCC_HS4_2

M18

N18

NVCC_HS6

NVCC_I2C

M17

T14

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

153

Package Information and Contact Assignments

Table 127. 19 x 19 mm Ground, Power, Sense, and Reference Contact Assignments (continued)

Contact Name Contact Assignment

NVCC_IPU2

NVCC_IPU4

NVCC_IPU5

NVCC_IPU6

NVCC_IPU7

NVCC_IPU8

NVCC_IPU9

NVCC_NANDF_A

NVCC_NANDF_B

NVCC_NANDF_C

NVCC_OSC

NVCC_PER3

NVCC_PER5

NVCC_PER8

NVCC_PER9

NVCC_PER10

G15

H16

H10

H11

G9

G10

W17

U18

T18

G16

H17

J17

K17

P18

R18

E6, F5

NVCC_PER11

NVCC_PER12

NVCC_PER13

NVCC_PER14

NVCC_PER15

NVCC_PER17

H15

G14

NVCC_SRTC_POW U14

NVCC_TV_BACK U16

G11

G12

G13

U13

NVCC_USBPHY

RREFEXT

SGND

SVCC

SVDDGP

TVDAC_DHVDD

VBUS

VCC

VDD_ANA_PLL_A

L17

K19

J11

H14

F13

V16

K20

H13, J15, J16, K15, K16, L7, L15, M7, N7, N17, P7, P17, R17, T8, T9, T10, T11, T12, T17

V6

154 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Package Information and Contact Assignments

Table 127. 19 x 19 mm Ground, Power, Sense, and Reference Contact Assignments (continued)

Contact Name

VDD_ANA_PLL_B

VDD_DIG_PLL_A

VDD_DIG_PLL_B

VDD_FUSE

VDDA

VDDA33

VDDGP

VREFOUT

VREF

VREG

Contact Assignment

W19

U6

W18

R7

G8, H8, H12, M8, P16, T13

L18

F6, F7, F8, F9, F10, F11, F12, G6, G7, H7, J7, K7

U15

R5

K21

AUD3_BB_CK

AUD3_BB_FS

AUD3_BB_RXD

AUD3_BB_TXD

BOOT_MODE0

BOOT_MODE1

CKIH1

CKIH2

CKIL

CLK_SS

COMP

2

CSI1_D10

CSI1_D11

CSI1_D12

CSI1_D13

CSI1_D14

5.1.2.2

19 x 19 mm, Signal Assignments, Power Rails, and I/O

Table 128

displays an alpha-sorted list of the signal assignments including power rails.

Contact Name

Table 128. 19 x 19 mm Signal Assignments, Power Rails, and I/O

Contact

Assignment

C8

A9

Y17

R22

R23

P22

P23

M20

B9

E9

AB21

AB22

V19

AA20

Y16

AA21

Power Rail

NVCC_PER9

NVCC_PER9

NVCC_PER9

NVCC_PER9

NVCC_PER3

NVCC_PER3

NVCC_PER3

NVCC_PER3

NVCC_SRTC_POW

NVCC_PER3

AHVDDRGB

NVCC_HS10

NVCC_HS10

NVCC_HS10

NVCC_HS10

NVCC_HS10

GPIO

GPIO

GPIO

GPIO

LVIO

LVIO

Analog

Analog

GPIO

LVIO

Analog

HSGPIO

HSGPIO

HSGPIO

HSGPIO

HSGPIO

I/O Buffer Type

Direction after

Reset

1

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Configuraton after Reset

1

Keeper

Keeper

Keeper

Keeper

100 k

Ω pull-up

100 k

Ω pull-up

Analog

Analog

Standard CMOS

100 k

Ω pull-up

Analog

Keeper

Keeper

Keeper

Keeper

Keeper

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

155

Package Information and Contact Assignments

Table 128. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)

Contact Name

CSI2_D18

CSI2_D19

CSI2_HSYNC

CSI2_PIXCLK

CSI2_VSYNC

CSPI1_MISO

CSPI1_MOSI

CSPI1_RDY

CSPI1_SCLK

CSPI1_SS0

CSPI1_SS1

DI_GP1

DI_GP2

DI_GP3

DI_GP4

CSI1_D15

CSI1_D16

CSI1_D17

CSI1_D18

CSI1_D19

CSI1_D8

CSI1_D9

CSI1_HSYNC

CSI1_MCLK

CSI1_PIXCLK

CSI1_VSYNC

CSI2_D12

CSI2_D13

CSI2_D14

CSI2_D15

CSI2_D16

CSI2_D17

NVCC_PER9

NVCC_PER9

NVCC_PER8

NVCC_PER8

NVCC_PER8

NVCC_PER10

NVCC_PER10

NVCC_PER10

NVCC_PER10

NVCC_PER10

NVCC_PER10

NVCC_IPU6

NVCC_IPU6

NVCC_IPU7

NVCC_IPU7

NVCC_HS10

NVCC_HS10

NVCC_HS10

NVCC_HS10

NVCC_HS10

NVCC_PER8

NVCC_PER8

NVCC_PER8

NVCC_PER8

NVCC_PER8

NVCC_PER8

NVCC_PER9

NVCC_PER9

NVCC_HS4_1

NVCC_HS4_1

NVCC_HS4_1

NVCC_HS4_1

Contact

Assignment

A10

E10

B10

H21

J19

H22

J22

F19

C10

D10

C9

D9

A8

C18

E19

C7

L20

L21

L22

L23

B20

F18

G18

B8

M23

E18

A21

A20

M21

N22

N23

M22

Power Rail I/O Buffer Type

Direction after

Reset

1

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

HSGPIO

HSGPIO

HSGPIO

HSGPIO

HSGPIO

HSGPIO

HSGPIO

HSGPIO

HSGPIO

GPIO

GPIO

GPIO

Configuraton after Reset

1

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

100 k

Ω pull-up

100 k

Ω pull-up

Keeper

100 k

Ω pull-up

100 k

Ω pull-up

100 k

Ω pull-up

Keeper

Keeper

100 k

Ω pull-up

100 k

Ω pull-up

156 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Package Information and Contact Assignments

Table 128. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)

Contact Name

DI1_D0_CS

DI1_D1_CS

DI1_DISP_CLK

DI1_PIN11

DI1_PIN12

DI1_PIN13

DI1_PIN15

DI1_PIN2

DI1_PIN3

DI2_DISP_CLK

DI2_PIN2

DI2_PIN3

DI2_PIN4

DISP1_DAT0

DISP1_DAT1

DISP1_DAT10

3

DISP1_DAT11

3

DISP1_DAT12

3

DISP1_DAT13

3

DISP1_DAT14

3

DISP1_DAT15

3

DISP1_DAT16

3

DISP1_DAT17

3

DISP1_DAT18

3

DISP1_DAT19

3

DISP1_DAT2

DISP1_DAT20

3

DISP1_DAT21

3

DISP1_DAT22

3

DISP1_DAT23

3

DISP1_DAT3

DISP1_DAT4

NVCC_IPU4

NVCC_IPU4

NVCC_IPU4

NVCC_IPU4

NVCC_IPU5

NVCC_IPU5

NVCC_IPU5

NVCC_IPU5

NVCC_HS6

NVCC_IPU5

NVCC_IPU5

NVCC_IPU5

NVCC_IPU5

NVCC_HS6

NVCC_HS6

NVCC_IPU2

NVCC_IPU2

NVCC_IPU6

NVCC_IPU2

NVCC_IPU2

NVCC_IPU2

NVCC_IPU6

NVCC_IPU6

NVCC_IPU6

NVCC_IPU7

NVCC_IPU7

NVCC_IPU7

NVCC_IPU7

NVCC_HS6

NVCC_HS6

NVCC_IPU4

NVCC_IPU4

Contact

Assignment

U22

F23

H19

F22

G21

U23

T22

E23

F21

G20

H18

E21

F20

E22

G19

H23

N20

N21

D22

D23

G22

J21

J20

K18

U21

AB23

J18

Y22

AA22

T20

H20

G23

Power Rail I/O Buffer Type

Direction after

Reset

1

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Output

Output

Output

Output

Input

Input

Input

Input

Input

Output

Output

Output

Output

Output

Output

Output

Output

HSGPIO

GPIO

GPIO

GPIO

GPIO

HSGPIO

HSGPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

HSGPIO

HSGPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

Configuraton after Reset

1

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

High

High

High

High

Keeper

Keeper

Keeper

Keeper

Keeper

High

High

Low

High

High

High

High

High

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

157

Package Information and Contact Assignments

Table 128. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)

Contact Name

DISP2_DAT6

DISP2_DAT7

DISP2_DAT8

DISP2_DAT9

DISPB2_SER_CLK

DISPB2_SER_DIN

DISPB2_SER_DIO

DISPB2_SER_RS

DN

DP

DRAM_A0

DRAM_A1

DRAM_A10

DRAM_A11

DRAM_A12

DISP1_DAT5

DISP1_DAT6

3

DISP1_DAT7

3

DISP1_DAT8

3

DISP1_DAT9

3

DISP2_DAT0

DISP2_DAT1

DISP2_DAT10

DISP2_DAT11

DISP2_DAT12

DISP2_DAT13

DISP2_DAT14

DISP2_DAT15

DISP2_DAT2

DISP2_DAT3

DISP2_DAT4

DISP2_DAT5

NVCC_IPU8

NVCC_IPU8

NVCC_IPU9

NVCC_IPU9

NVCC_IPU2

NVCC_IPU2

NVCC_IPU2

NVCC_IPU2

VDDA33

VDDA33

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_HS6

NVCC_IPU4

NVCC_IPU4

NVCC_IPU4

NVCC_IPU4

NVCC_IPU8

NVCC_IPU8

NVCC_IPU9

NVCC_IPU9

NVCC_IPU9

NVCC_IPU9

NVCC_IPU9

NVCC_IPU9

NVCC_HS4_2

NVCC_HS4_2

NVCC_HS4_2

NVCC_HS4_2

Contact

Assignment

K22

K23

AB1

AA2

V2

U4

U2

N19

W23

P19

R20

AC22

U19

V21

W21

R19

Y23

T19

AA23

T21

P20

P21

V22

V23

E20

R21

M19

W22

T23

C22

C23

D21

Power Rail I/O Buffer Type

Direction after

Reset

1

Output

Output

Output

Output

Output

Output

Output

Input

Input

Input

Input

Output

Input

Input

Output

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Analog

Analog

DDR2

DDR2

DDR2

DDR2

DDR2

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

HSGPIO

HSGPIO

HSGPIO

HSGPIO

HSGPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

Configuraton after Reset

1

Keeper

Keeper

Keeper

Keeper

High

100 k

Ω pull-up

100 k

Ω pull-up

High

–

–

High

High

High

High

High

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

158 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Package Information and Contact Assignments

Contact Name

DRAM_D12

DRAM_D13

DRAM_D14

DRAM_D15

DRAM_D16

DRAM_D17

DRAM_D18

DRAM_D19

DRAM_D2

DRAM_D20

DRAM_D21

DRAM_D22

DRAM_D23

DRAM_D24

DRAM_D25

DRAM_A13

DRAM_A14

DRAM_A2

DRAM_A3

DRAM_A4

DRAM_A5

DRAM_A6

DRAM_A7

DRAM_A8

DRAM_A9

DRAM_CAS

DRAM_CS0

DRAM_CS1

DRAM_D0

DRAM_D1

DRAM_D10

DRAM_D11

Table 128. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

Contact

Assignment

J4

K5

H1

R2

K3

K4

J3

L3

L2

L1

K1

M1

M5

L5

L4

Y3

T1

R3

M3

M4

W2

V3

V4

Y4

W4

Y2

W3

Y1

U1

T2

AA3

V5

Power Rail I/O Buffer Type

Direction after

Reset

1

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

DDR2

DDR2

DDR2

DDR2

DDR2

DDR2

DDR2

DDR2

DDR2

DDR2

DDR2

DDR2

DDR2

DDR2

DDR2

DDR2

DDR2

DDR2

DDR2

DDR2

DDR2

DDR2

DDR2

DDR2

DDR2

DDR2

DDR2

DDR2

DDR2

DDR2

DDR2

DDR2

Configuraton after Reset

1

High

High

High

High

High

High

High

High

High

High

High

High

High

High

High

High

High

High

High

High

High

High

High

High

High

High

High

High

High

High

High

High

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

159

Package Information and Contact Assignments

Table 128. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)

Contact Name

DRAM_RAS

DRAM_SDCKE0

DRAM_SDCKE1

DRAM_SDCLK

DRAM_SDCLK_B

DRAM_SDQS0

DRAM_SDQS0_B

DRAM_SDQS1

DRAM_SDQS1_B

DRAM_SDQS2

DRAM_SDQS2_B

DRAM_SDQS3

DRAM_SDQS3_B

DRAM_SDWE

EIM_A16

3

DRAM_D26

DRAM_D27

DRAM_D28

DRAM_D29

DRAM_D3

DRAM_D30

DRAM_D31

DRAM_D4

DRAM_D5

DRAM_D6

DRAM_D7

DRAM_D8

DRAM_D9

DRAM_DQM0

DRAM_DQM1

DRAM_DQM2

DRAM_DQM3

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

Contact

Assignment

N3

J1

J2

H3

H4

U5

AA9

T4

P2

P1

N4

W1

AA1

W5

T3

N1

P3

M2

K2

H5

P5

P4

N5

N2

R1

G3

G4

R4

H2

J5

G1

G2

Power Rail I/O Buffer Type

Direction after

Reset

1

Output

Output

Output

Output

Output

Output

Input

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

DDR2

DDR2

DDR2

DDR2CLK

DDR2CLK

DDR2CLK

DDR2CLK

DDR2CLK

DDR2CLK

DDR2CLK

DDR2CLK

DDR2CLK

DDR2CLK

DDR2

GPIO

DDR2

DDR2

DDR2

DDR2

DDR2

DDR2

DDR2

DDR2

DDR2

DDR2

DDR2

DDR2

DDR2

DDR2

DDR2

DDR2

DDR2

Configuraton after Reset

1

High

High

High

High

High

High

High

High

High

High

High

High

High

High

100 k

Ω pull-up

High

High

High

High

High

High

High

High

High

High

High

High

High

High

High

High

High

160 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Package Information and Contact Assignments

Contact Name

EIM_CS4

EIM_CS5

EIM_D16

EIM_D17

EIM_D18

EIM_D19

EIM_D20

EIM_D21

EIM_D22

EIM_D23

EIM_D24

EIM_D25

EIM_D26

EIM_D27

EIM_D28

EIM_A17

3

EIM_A18

3

EIM_A19

3

EIM_A20

3

EIM_A21

3

EIM_A22

EIM_A23

3

EIM_A24

EIM_A25

EIM_A26

EIM_A27

EIM_BCLK

EIM_CRE

EIM_CS0

EIM_CS1

EIM_CS2

EIM_CS3

Table 128. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)

NVCC_EMI

NVCC_EMI

NVCC_EMI

NVCC_EMI

NVCC_EMI

NVCC_EMI

NVCC_EMI

NVCC_EMI

NVCC_EMI

NVCC_EMI

NVCC_EMI

NVCC_EMI

NVCC_EMI

NVCC_EMI

NVCC_EMI

NVCC_EMI

NVCC_EMI

NVCC_EMI

NVCC_EMI

NVCC_EMI

NVCC_EMI

NVCC_EMI

NVCC_EMI

NVCC_EMI

NVCC_EMI

NVCC_EMI

NVCC_EMI

NVCC_EMI

NVCC_EMI

NVCC_EMI

NVCC_EMI

NVCC_EMI

Contact

Assignment

AC11

V8

AA10

Y9

AB10

W8

AC10

AA6

AA5

AC12

W10

AA11

Y10

AB11

W9

AB2

W6

Y6

Y7

AC3

AB6

AC4

AB5

AA4

AC7

AB7

AC6

AC5

AB9

AC8

AA8

AB8

Power Rail I/O Buffer Type

Direction after

Reset

1

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Output

Output

Output

Input

Input

Input

Input

Input

Input

Input

Output

Input

Input

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Configuraton after Reset

1

100 k

Ω pull-up

100 k

Ω pull-up

100 k

Ω pull-up

100 k

Ω pull-up

100 k

Ω pull-up

High

100 k

Ω pull-up

100 k

Ω pull-up

100 k

Ω pull-up

100 k

Ω pull-up

Keeper

Keeper

High

High

High

Keeper

Keeper

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

161

Package Information and Contact Assignments

Table 128. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)

Contact Name

EIM_DA8

EIM_DA9

EIM_DTACK

EIM_EB0

EIM_EB1

EIM_EB2

EIM_EB3

EIM_LBA

EIM_OE

EIM_RW

EIM_SDBA0

EIM_SDBA1

EIM_SDBA2

EIM_SDODT0

EIM_SDODT1

EIM_D29

EIM_D30

EIM_D31

EIM_DA0

EIM_DA1

EIM_DA10

EIM_DA11

EIM_DA12

EIM_DA13

EIM_DA14

EIM_DA15

EIM_DA2

EIM_DA3

EIM_DA4

EIM_DA5

EIM_DA6

EIM_DA7

NVCC_EMI

NVCC_EMI

NVCC_EMI

NVCC_EMI

NVCC_EMI

NVCC_EMI

NVCC_EMI

NVCC_EMI

NVCC_EMI

NVCC_EMI

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI

NVCC_EMI

NVCC_EMI

NVCC_EMI

NVCC_EMI

NVCC_EMI

NVCC_EMI

NVCC_EMI

NVCC_EMI

NVCC_EMI

NVCC_EMI

NVCC_EMI

NVCC_EMI

NVCC_EMI

NVCC_EMI

NVCC_EMI

NVCC_EMI

Contact

Assignment

AA7

AB3

V1

U3

F1

F3

F2

AB13

Y12

Y5

V12

W12

V10

V9

AC2

W11

AB12

Y11

AA14

AB14

AC14

Y13

AA13

W13

Y8

AC9

W7

AC15

V13

AC13

V11

AA12

Power Rail I/O Buffer Type

Direction after

Reset

1

Output

Output

Output

Output

Output

Output

Output

Input

Input

Input

Output

Output

Input

Input

Output

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

GPIO

GPIO

DDR2

DDR2

DDR2

DDR2

DDR2

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

Configuraton after Reset

1

Keeper

Keeper

100 k

Ω pull-up

High

High

Keeper

Keeper

High

High

High

High

High

High

High

High

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

162 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Package Information and Contact Assignments

Contact

Assignment

C19

B23

C21

C20

W15

A22

D18

B22

D19

AB4

AB20

W20

Y20

J23

D5

B21

D20

AB16

L19

AC19

AB19

AC18

AB18

AC17

AB17

AB15

JTAG_MOD

JTAG_TCK

JTAG_TDI

JTAG_TDO

JTAG_TMS

Table 128. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)

Contact Name

EIM_WAIT

EXTAL

2

FASTR_ANA

2

FASTR_DIG

2

GPANAIO

2

GPIO_NAND

GPIO1_0

GPIO1_1

GPIO1_2

GPIO1_3

GPIO1_4

GPIO1_5

GPIO1_6

GPIO1_7

GPIO1_8

GPIO1_9

I2C1_CLK

I2C1_DAT

ID

IOB

2

IOB_BACK

2

IOG

2

IOG_BACK

2

IOR

2

IOR_BACK

2

JTAG_DE_B

V14

V15

Y14

AA15

AC16

Power Rail

NVCC_EMI

NVCC_OSC

NVCC_PER3

NVCC_PER3

NVCC_USBPHY

NVCC_NANDF_A

NVCC_PER5

NVCC_PER5

NVCC_PER5

NVCC_PER5

NVCC_PER5

NVCC_PER5

NVCC_PER5

NVCC_PER5

NVCC_PER5

NVCC_PER5

NVCC_I2C

NVCC_I2C

NVCC_USBPHY

AHVDDRGB

—

AHVDDRGB

—

AHVDDRGB

—

NVCC_PER14

NVCC_PER14

NVCC_PER14

NVCC_PER14

NVCC_PER14

NVCC_PER14

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

I2CIO

GPIO

Analog

—

—

Analog

UHVIO

GPIO

GPIO

I2CIO

Analog

Analog

Analog

Analog

Analog

Analog

Analog

GPIO

I/O Buffer Type

GPIO

GPIO

GPIO

GPIO

GPIO

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Output

Input

Input

Input

Direction after

Reset

1

Input

Input

Output

Output

Output

Output

Output

Output

Input/Open-drain output

Input

Input

Input

3-state output

Input

—

—

—

—

—

—

47 k

Ω pull-up

100 k

Ω pull-up

100 k

Ω pull-down

47 k

Ω pull-up

Keeper

47 k

Ω pull-up

Configuraton after Reset

1

100 k

Ω pull-up

—

—

—

—

100 k

Ω pull-up

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

47 k

Ω pull-up

47 k

Ω pull-up

Pull-up

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

163

Package Information and Contact Assignments

Table 128. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)

Contact Name

NANDF_CS4

NANDF_CS5

NANDF_CS6

NANDF_CS7

NANDF_D0

NANDF_D1

NANDF_D10

NANDF_D11

NANDF_D12

NANDF_D13

NANDF_D14

NANDF_D15

NANDF_D2

NANDF_D3

NANDF_D4

JTAG_TRSTB

KEY_COL0

KEY_COL1

KEY_COL2

KEY_COL3

4

KEY_COL4

4

KEY_COL5

4

KEY_ROW0

KEY_ROW1

KEY_ROW2

KEY_ROW3

NANDF_ALE

NANDF_CLE

NANDF_CS0

NANDF_CS1

NANDF_CS2

NANDF_CS3

NVCC_NANDF_A

NVCC_NANDF_A

NVCC_NANDF_B

NVCC_NANDF_B

NVCC_NANDF_C

NVCC_NANDF_C

NVCC_NANDF_B

NVCC_NANDF_B

NVCC_NANDF_B

NVCC_NANDF_B

NVCC_NANDF_B

NVCC_NANDF_B

NVCC_NANDF_C

NVCC_NANDF_C

NVCC_NANDF_C

NVCC_PER14

NVCC_PER13

NVCC_PER13

NVCC_PER13

NVCC_PER13

NVCC_PER13

NVCC_PER13

NVCC_PER13

NVCC_PER13

NVCC_PER13

NVCC_PER13

NVCC_NANDF_A

NVCC_NANDF_A

NVCC_NANDF_A

NVCC_NANDF_A

NVCC_NANDF_A

NVCC_NANDF_A

Contact

Assignment

A6

D8

B7

C5

A3

B4

D6

A7

E8

B5

D7

B2

A2

E5

C4

F4

C3

C2

E4

B1

B16

F15

C15

E3

B17

F16

C16

D14

W14

E15

A16

D15

Power Rail I/O Buffer Type

Direction after

Reset

1

Input

Input

Input

Input

Input

Input

Input

Output

Output

Output

Output

Input

Input

Input

Input

Input

Input

Input

Output

Output

Output

Output

Output

Output

Input

Input

Input

Input

Output

Output

Output

Input

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

GPIO

GPIO

GPIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Low

Low

Low

Low

Keeper

Keeper

Keeper

Keeper

Configuraton after Reset

1

47 k

Ω pull-up

100 k

Ω pull-up

100 k

Ω pull-up

100 k

Ω pull-up

High

Low

Low

100 k

Ω pull-up

100 k

Ω pull-up

100 k

Ω pull-up

100 k

Ω pull-up

High

High

High

High

High

High

164 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Package Information and Contact Assignments

Table 128. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)

Contact Name

PMIC_STBY_REQ

POR_B

RESET_IN_B

SD1_CLK

SD1_CMD

SD1_DATA0

SD1_DATA1

SD1_DATA2

SD1_DATA3

SD2_CLK

SD2_CMD

SD2_DATA0

SD2_DATA1

SD2_DATA2

SD2_DATA3

NANDF_D5

NANDF_D6

NANDF_D7

NANDF_D8

NANDF_D9

NANDF_RB0

NANDF_RB1

NANDF_RB2

NANDF_RB3

NANDF_RDY_INT

NANDF_RE_B

NANDF_WE_B

NANDF_WP_B

OWIRE_LINE

PMIC_INT_REQ

PMIC_ON_REQ

PMIC_RDY

NVCC_NANDF_C

NVCC_NANDF_C

NVCC_NANDF_B

NVCC_NANDF_B

NVCC_NANDF_B

NVCC_NANDF_A

NVCC_NANDF_A

NVCC_NANDF_A

NVCC_NANDF_A

NVCC_NANDF_B

NVCC_NANDF_A

NVCC_NANDF_A

NVCC_NANDF_A

NVCC_PER12

NVCC_SRTC_POW

NVCC_SRTC_POW

NVCC_SRTC_POW

NVCC_SRTC_POW

NVCC_PER3

NVCC_PER3

NVCC_PER15

NVCC_PER15

NVCC_PER15

NVCC_PER15

NVCC_PER15

NVCC_PER15

NVCC_PER17

NVCC_PER17

NVCC_PER17

NVCC_PER17

NVCC_PER17

NVCC_PER17

Contact

Assignment

A19

B18

G17

E17

B19

D17

C17

E16

D16

A18

F17

Y15

U20

Y21

A17

D1

E14

AA16

W16

AA17

C1

B3

E2

E1

E7

D2

D4

D3

A5

B6

C6

A4

Power Rail

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

GPIO

LVIO

LVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

GPIO

GPIO

GPIO

GPIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

I/O Buffer Type

Direction after

Reset

1

Configuraton after Reset

1

Keeper

Keeper

Keeper

Keeper

Keeper

100 k

Ω pull-up

100 k

Ω pull-up

100 k

Ω pull-up

100 k

Ω pull-up

100 k

Ω pull-up

—

—

—

100 k

Ω pull-up

100 k

Ω pull-up

100 k

Ω pull-up

100 k

Ω pull-up

100 k

Ω pull-up

100 k

Ω pull-up

100 k

Ω pull-up

—

47 k

Ω pull-up

47 k

Ω pull-up

47 k

Ω pull-up

47 k

Ω pull-up

360 k

Ω pull-down

—

47 k

Ω pull-up

47 k

Ω pull-up

47 k

Ω pull-up

47 k

Ω pull-up

360 k

Ω pull-down

Input

Output

Input

Input

Input

Input

Input

Input

Input

Input

Output

Input

Input

Input

Input

Input

Input

Output

Output

Output

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

165

Package Information and Contact Assignments

Table 128. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)

Contact Name

Contact

Assignment

Power Rail I/O Buffer Type

Direction after

Reset

1

Configuraton after Reset

1

STR

TEST_MODE

UART1_CTS

UART1_RTS

UART1_RXD

UART1_TXD

UART2_RXD

UART2_TXD

UART3_RXD

UART3_TXD

USBH1_CLK

USBH1_DATA0

USBH1_DATA1

USBH1_DATA2

USBH1_DATA3

USBH1_DATA4

USBH1_DATA5

A15

V20

B14

D13

E13

A13

A14

C14

F14

B15

D11

E12

A11

B12

C12

D12

A12

NVCC_PER12

NVCC_PER3

NVCC_PER12

NVCC_PER12

NVCC_PER12

NVCC_PER12

NVCC_PER12

NVCC_PER12

NVCC_PER12

NVCC_PER12

NVCC_PER11

NVCC_PER11

NVCC_PER11

NVCC_PER11

NVCC_PER11

NVCC_PER11

NVCC_PER11

—

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

—

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

—

100 k

Ω pull-down

100 k

Ω pull-up

100 k

Ω pull-up

100 k

Ω pull-up

100 k

Ω pull-up

100 k

Ω pull-up

100 k

Ω pull-up

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

USBH1_DATA6

USBH1_DATA7

USBH1_DIR

USBH1_NXT

B13

C13

B11

C11

NVCC_PER11

NVCC_PER11

NVCC_PER11

NVCC_PER11

GPIO

GPIO

GPIO

GPIO

Input

Input

Input

Input

Keeper

Keeper

Keeper

Keeper

USBH1_STP E11 NVCC_PER11 GPIO Input Keeper

XTAL

2

AC20 NVCC_OSC Analog Output —

2

3

1

4

The state immediately after reset and before ROM firmware or software has executed.

See

Table 3 on page 11

for more information.

During power-on reset this port acts as input for fuse override signal. See Table 129 on page 167

for more information.

During power-on reset this port acts as output for diagnostic signal. See Table 129 on page 167 for more information.

166 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Package Information and Contact Assignments

DISP1_DAT10

DISP1_DAT11

DISP1_DAT12

DISP1_DAT13

DISP1_DAT14

DISP1_DAT15

DISP1_DAT16

DISP1_DAT17

DISP1_DAT18

DISP1_DAT19

DISP1_DAT20

DISP1_DAT21

DISP1_DAT22

DISP1_DAT23

DISP1_DAT6

DISP1_DAT7

DISP1_DAT8

DISP1_DAT9

EIM_A16

EIM_A17

EIM_A18

EIM_A19

EIM_A20

EIM_A21

KEY_COL3

5.1.2.3

Fuse Override Considerations

Table 129

lists the contacts that can be overridden with fuse settings.

Table 129. Fuse Override Contacts

Contact Name

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Output

Direction

After Reset

Configuration

After Reset

Signal Configuration

1

External Termination for Fuse Override

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

High

BT_SPARE_SIZE

BT_LPB_FREQ[2]

BT_MLC_SEL

BT_MEM_CTL[0]

BT_MEM_CTL[1]

BT_BUS_WIDTH

BT_PAGE_SIZE[0]

BT_PAGE_SIZE[1]

BT_WEIM_MUXED[0]

BT_WEIM_MUXED[1]

BT_MEM_TYPE[0]

BT_MEM_TYPE[1]

BT_LPB_FREQ[0]

BT_LPB_FREQ[1]

BT_USB_SRC

BT_EEPROM_CFG

BT_SRC[0]

BT_SRC[1]

2

100 k

Ω pull-up OSC_FREQ_SEL[0]

100 k

Ω pull-up OSC_FREQ_SEL[1]

100 k

Ω pull-up BT_LPB[0]

100 k

Ω pull-up BT_LPB[1]

100 k

Ω pull-up BT_UART_SRC[0]

100 k

Ω pull-up BT_UART_SRC[1]

Output for diagnostic signal

INT_BOOT during power-on reset

—

4.7 k

Ω pull-up or pull-down

4.7 k

Ω pull-up or pull-down

4.7 k

Ω pull-up or pull-down

4.7 k

Ω pull-up or pull-down

4.7 k

Ω pull-up or pull-down

4.7 k

Ω pull-up or pull-down

4.7 k

Ω pull-up or pull-down

4.7 k

Ω pull-up or pull-down

4.7 k

Ω pull-up or pull-down

4.7 k

Ω pull-up or pull-down

4.7 k

Ω pull-up or pull-down

4.7 k

Ω pull-up or pull-down

4.7 k

Ω pull-up or pull-down

4.7 k

Ω pull-up or pull-down

4.7 k

Ω pull-up or pull-down

4.7 k

Ω pull-up or pull-down

4.7 k

Ω pull-up or pull-down

4.7 k

Ω pull-up or pull-down

4.7 k

Ω pull-down or none for high level 3

4.7 k

Ω pull-down or none for high level 2

4.7 k

Ω pull-down or none for high level 2

4.7 k

Ω pull-down or none for high level 2

4.7 k

Ω pull-down or none for high level 2

4.7 k

Ω pull-down or none for high level 2

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

167

Package Information and Contact Assignments

Table 129. Fuse Override Contacts (continued)

Contact Name

Direction

After Reset

Configuration

After Reset

Signal Configuration

1

External Termination for Fuse Override

KEY_COL4 Output Low Output for diagnostic signal

ANY_PU_RST during power-on reset

—

KEY_COL5 Output Low Output for diagnostic signal

JTAG_ACT during power-on reset

—

1

2

3

Signal Configuration as Fuse Override Input at Power Up. These are special I/O lines that control the boot up configuration during product development. In production, the boot configuration is controlled by fuses.

External USB PHY selection is not functional.

Consider using an external 68 k

Ω pull-up if system constraints indicate that the on-chip 100 kΩ pull-up is too weak.

168 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Package Information and Contact Assignments

5.2

19 x 19 mm, 0.8 Pitch Ball Map

Table 130

shows the 19

× 19 mm, 0.8 pitch ball map.

Table 130. 19

× 19 mm, 0.8 Pitch Ball Map

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

169

Package Information and Contact Assignments

Table 130. 19 × 19 mm, 0.8 Pitch Ball Map (continued)

170 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Package Information and Contact Assignments

Table 130. 19 × 19 mm, 0.8 Pitch Ball Map (continued)

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

171

Package Information and Contact Assignments

Table 130. 19 × 19 mm, 0.8 Pitch Ball Map (continued)

172 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

Revision History

6 Revision History

Table 131

provides a revision history for this data sheet.

2

Table 131. i.MX51 Data Sheet Document Revision History

Rev.

Number

Date Substantive Change(s)

Rev. 6 10/2012 • In

Table 25, "I/O Leakage Current," on page 29

, updated supply rail names for SD1 and SD2 to

NVCC_PER15 and NVCC_PER17, respectively.

• Updated

Section 4.6.7.3, “General WEIM Timing-Synchronous Mode.”

• Updated

Section 4.6.7.4, “Examples of WEIM Synchronous Accesses.”

• Updated

Section 4.6.7.5, “General WEIM Timing-Asynchronous Mode.”

Rev. 5 03/2012 • In

Table 4, "JTAG Controller Interface Summary," on page 13 , changed On-Chip Termination column

value for JTAG_MOD from “100 k

Ω pull-down” to “100 kΩ pull-up.”

• In

Section 3.7, “USB-OTG IOMUX Pin Configuration,”

removed the third sentence from the first

paragraph and added a note after Table 9 .

• In

Section 4.3.4, “Ultra-High Voltage I/O (UHVIO) DC Parameters,”

added clarification about UHVIO I/O cell HVE bit functionality after

Table 21

.

• In

Section 4.6.9, “DDR2 SDRAM Specific Parameters

: ”

—Updated

Table 58, "DDR2 SDRAM Timing Parameter Table," on page 67

—Added a note after

Table 58

—Updated

Figure 36, "DDR2 SDRAM Write Cycle Timing Diagram," on page 69

—Updated

Table 60, "DDR2 SDRAM Write Cycle Parameter Table," on page 69

—Added a note after

Table 60

—Updated

Figure 37, "DDR2 SDRAM DQ versus DQS and SDCLK Read Cycle Timing Diagram," on page 71

—Updated

Table 63, "DDR2 SDRAM Read Cycle Parameter Table," on page 71

—Added a note after

Table 63

• In

Section 4.7.8.2, “Electrical Characteristics,”

changed signal name in the second sentence of the first paragraph from “SENSB_MCLK” to “SENSB_PIX_CLK.”

• In

Table 128, "19 x 19 mm Signal Assignments, Power Rails, and I/O," on page 155 , changed

Configuraton after Reset column value for contacts, DI1_D0_CS, DI1_D1_CS, DI1_PIN11, and

DI1_PIN12, from “Low” to “High.”

• In

Table 128, "19 x 19 mm Signal Assignments, Power Rails, and I/O," on page 155 , changed

Configuraton after Reset column value for contact, JTAG_MOD, from “100 k

Ω pull-down” to “100 kΩ pull-up.”

• In

Table 128, "19 x 19 mm Signal Assignments, Power Rails, and I/O," on page 155

, changed Power Rail column value for contacts, UART1_CTS, UART1_RTS, UART1_RXD, UART1_TXD, UART2_RXD,

UART2_TXD, UART3_RXD, and UART3_TXD, from “NVVCC_PER12” to “NVCC_PER12.”

• In

Table 129, "Fuse Override Contacts," on page 167

:

—Added a footnote for contact, DISP1_DAT6

—Removed information about contact, EIM_A23, because the signal configuration it corresponds to,

BT_HPN_EN, is not in use.

• Corrected cross-references throughout the document.

Rev. 4

08/2010 • Removed table footnote in Table 47, "CAMP Electrical Parameters (CKIH1, CKIH2)," on page 46

.

• Updated

Table 52, "WEIM Interface Pinout in Various Configurations," on page 53 .

Freescale Semiconductor i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

173

Revision History

Table 131. i.MX51 Data Sheet Document Revision History (continued)

Rev.

Number

Date Substantive Change(s)

Rev. 3 06/2010 • Updated Max column of

Table 15, "Fuse Supply Current," on page 19 . Deleted eFuse Read Current row

from the same table.

• Updated Symbol, Test Conditions, and Max columns of Table 18, "GPIO/HSGPIO DC Electrical

Characteristics," on page 23

.

• Updated Max and Unit columns of Table 19, "DDR2 I/O DC Electrical Parameters," on page 24 .

• Updated Test Conditions, Max, and Unit columns of

Table 20, "LVIO DC Electrical Characteristics," on page 24

• Updated Symbol, Test Conditions, Max, and Unit columns of

Table 21, "UHVIO DC Electrical

Characteristics," on page 25

.

• Updated Max and Unit columns of Table 22, "I2C Standard/Fast/High-Speed Mode Electrical

Parameters for Low/Medium Drive Strength," on page 27

.

• Added a new table Table 25, "I/O Leakage Current," on page 29

.

Rev. 2 05/2010 • Changed the VREFOUT column in

Table 3, "Special Signal Considerations," on page 11

.

• Added

Section 3, “IOMUX Configuration for Boot Media”

.

• Updated

Figure 2, "Power-Up Sequence," on page 22 .

• Added a note in

Section 4.2.1, “Power-Up Sequence”

.

• Updated

Section 4.2.1, “Power-Up Sequence .

”

• Changed the Input current (47 k

Ω Pull-up) column in

Table 21, "UHVIO DC Electrical Characteristics," on page 25 to Input current (75 kO Pull-up).

• Added new table for parameters for DDR2 Pad output buffer Impedance. See

Table 27, "DDR2 I/O

Output Buffer Impedance HVE = 0," on page 30

.

• Added new section under Section 4.5, “I/O AC Parameters”

. See

Section 4.5.4, “AC Electrical

Characteristics for DDR2”.

• Updated

Table 47, "CAMP Electrical Parameters (CKIH1, CKIH2)," on page 46 . In the VIH (for square

wave input) parameter, the minimum frequency was changed to NVCC_PER3 - 0.25V and the maximum frequency was changed to NVCC_PER3.

• Added a note in

Section 4.6.6, “NAND Flash Controller (NFC) Parameters ” after

Table 49

.

• Updated Asymmetric Mode Min, Symmetric Mode Min, and Max columns of

Table 50 .

• Removed Conditions parameters of the Full scale output voltage row in

Table 82 .

• Updated

Section 4.7.11, “P-ATA Timing Parameters”

. Replaced ATA/ATAPI-6 specification with

ATA/ATAPI-5 specification.

• In

Table 102, "SSI Transmitter Timing with Internal Clock," on page 133 , under the Synchronous Internal

Clock Operation sections for the ID SS42, minimum frequency was changed from 10.0 to 30.

• In

Table 103, "SSI Receiver Timing with Internal Clock," on page 134 , under the Internal Clock

Operation section for ID SS20, minimum frequency was changed from 10.0 to 30.

• In

Table 104, "SSI Transmitter Timing with External Clock," on page 136 , under the External Clock

Operation section for ID SS38, maximum frequency was changed from 15.0 to 30.

• Added a new section Section 4.7.16.1, “UART Electrical” , under Section 4.7.16, “UART”

.

• In

Table 118, "USB Port Timing Specification in VP_VM Bi-directional Mode," on page 146 , for IDs SS28

and SS29, direction was changed from out to in.

• In

Table 120, "USB Timing Specification in VP_VM Unidirectional Mode," on page 148 , for IDs US40 and

US41, direction was changed from out to in and the reference signal was changed to USB_VM1 and

USB_VP1 respectively.

• In

Table 122, "USB Timing Specification for ULPI Parallel Mode," on page 149

, added an extra row for

ID17.

• Updated Signal and Direction columns in

Table 120, "USB Timing Specification in VP_VM Unidirectional

Mode," on page 148

.

• Updated Signal names in

Table 118, "USB Port Timing Specification in VP_VM Bi-directional Mode," on page 146 .

Rev. 1 10/2009 Initial public release.

174 i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

How to Reach Us:

Home Page: freescale.com

Web Support: freescale.com/support

Information in this document is provided solely to enable system and software implementers to use Freescale products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document.

Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by customer’s technical experts. Freescale does not convey any license under its patent rights nor the rights of others. Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: freescale.com/SalesTermsandConditions.

Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc. Reg.

U.S. Pat. & Tm. Off. All other product or service names are the property of their respective owners. ARM is the registered trademark of ARM Limited. ARM Cortex

TM

-A8 is the trademark of ARM Limited.

© 2012 Freescale Semiconductor, Inc. All rights reserved.

Document Number: IMX51AEC

Rev. 6

09/2012