Motorola T1/E1 Specifications

www.maxim-ic.com

GENERAL DESCRIPTION

The DS26503 is a building-integrated timingsupply (BITS) clock-recovery element. It also functions as a basic T1/E1 transceiver. The receiver portion can recover a clock from T1,

E1, and 6312kHz synchronization timing interfaces. In T1 and E1 modes, the

Synchronization Status Message (SSM) can also be recovered. The transmit portion can directly interface to T1 or E1 interfaces as well as source the SSM in T1 and E1 modes. The DS26503 can translate between any of the supported inbound synchronization clock rates to any supported outbound rate. A separate output is provided to source a 6312kHz clock. The device is controlled through a parallel, serial, or hardware controller port.

APPLICATIONS

BITS Timing

Rate Conversion

Basic Transceiver

ORDERING INFORMATION

DS26503L 0°C to +70°C 64 LQFP

DS26503LN -40°C to +85°C 64 LQFP

DESIGN KIT AVAILABLE

DS26503

T1/E1/J1 BITS Element

FEATURES

G.703 2048kHz Synchronization Interface

Compliant

G.703 6312kHz Japanese Synchronization

Interface Compliant

Interfaces to Standard T1/J1 (1.544MHz) and

E1 (2.048MHz)

Interface to CMI-Coded T1/J1 and E1

Short- and Long-Haul Line Interface

Transmit and Receive T1 and E1 SSM

Messages with Message Validation

T1/E1 Jitter Attenuator with Bypass Mode

Fully Independent Transmit and Receive

Functionality

Internal Software-Selectable Receive- and

Transmit-Side Termination for

75

Ω/100Ω/110Ω/120Ω

Monitor Mode for Bridging Applications

Accepts 16.384MHz, 12.8MHz, 8.192MHz,

4.096MHz, 2.048MHz, or 1.544MHz Master

Clock

8-Bit Parallel Control Port, Multiplexed or

Nonmultiplexed, Intel or Motorola

Serial (SPI) Control Port

Hardware Control Mode

Provides LOS, AIS, and LOF Indications

Through Hardware Output Pins

Fast Transmitter-Output Disable Through

Device Pin for Protection Switching

IEEE 1149.1 JTAG Boundary Scan

3.3V Supply with 5V-Tolerant Inputs and

Outputs

Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata .

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DS26503 T1/E1/J1 BITS Element

TABLE OF CONTENTS

1.

FEATURES ....................................................................................................................................7

1.1

G ENERAL .....................................................................................................................................7

1.2

L INE I NTERFACE ...........................................................................................................................7

1.3

J ITTER A TTENUATOR (T1/E1 M ODES O NLY ) ..................................................................................7

1.4

F RAMER /F ORMATTER ...................................................................................................................8

1.5

T EST AND D IAGNOSTICS ...............................................................................................................8

1.6

C ONTROL P ORT ............................................................................................................................8

2.

3.

SPECIFICATIONS COMPLIANCE.................................................................................................9

BLOCK DIAGRAMS.....................................................................................................................11

4.

PIN FUNCTION DESCRIPTION...................................................................................................14

4.1

T RANSMIT PLL ...........................................................................................................................14

4.2

T RANSMIT S IDE ..........................................................................................................................14

4.3

R ECEIVE S IDE ............................................................................................................................15

4.4

C ONTROLLER I NTERFACE ............................................................................................................16

4.5

JTAG.........................................................................................................................................21

4.6

L INE I NTERFACE .........................................................................................................................21

4.7

P OWER ......................................................................................................................................22

5.

6.

PINOUT ........................................................................................................................................23

HARDWARE CONTROLLER INTERFACE .................................................................................26

7.

6.1

T RANSMIT C LOCK S OURCE .........................................................................................................26

6.2

I NTERNAL T ERMINATION ..............................................................................................................26

6.3

L INE B UILD -O UT .........................................................................................................................27

6.4

R ECEIVER O PERATING M ODES ....................................................................................................27

6.5

T RANSMITTER O PERATING M ODES ..............................................................................................28

6.6

MCLK P RE -S CALER ...................................................................................................................28

6.7

O THER H ARDWARE C ONTROLLER M ODE F EATURES ....................................................................29

PROCESSOR INTERFACE .........................................................................................................30

7.1

P ARALLEL P ORT F UNCTIONAL D ESCRIPTION ................................................................................30

7.2

SPI S ERIAL P ORT I NTERFACE F UNCTIONAL D ESCRIPTION ............................................................30

7.2.1

Clock Phase and Polarity......................................................................................................30

7.2.2

Bit Order................................................................................................................................30

7.2.3

Control Byte ..........................................................................................................................30

7.2.4

Burst Mode............................................................................................................................30

7.2.5

Register Writes .....................................................................................................................31

7.2.6

Register Reads .....................................................................................................................31

7.3

R EGISTER M AP ...........................................................................................................................32

7.3.1

Power-Up Sequence.............................................................................................................34

7.3.2

Test Reset Register ..............................................................................................................34

7.3.3

Mode Configuration Register ................................................................................................35

7.4

I NTERRUPT H ANDLING ................................................................................................................38

7.5

S TATUS R EGISTERS ....................................................................................................................38

7.6

I NFORMATION R EGISTERS ...........................................................................................................39

7.7

I NTERRUPT I NFORMATION R EGISTERS .........................................................................................39

8.

T1 FRAMER/FORMATTER CONTROL REGISTERS .................................................................40

8.1

T1 C ONTROL R EGISTERS ............................................................................................................40

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9.


E1 FRAMER/FORMATTER CONTROL REGISTERS .................................................................46

9.1

E1 C ONTROL R EGISTERS ...........................................................................................................46

9.2

E1 I NFORMATION R EGISTERS ......................................................................................................48

10.

I/O PIN CONFIGURATION OPTIONS..........................................................................................52

11.

T1 SYNCHRONIZATION STATUS MESSAGE ...........................................................................55

11.1

T1 B IT -O RIENTED C ODE (BOC) C ONTROLLER ............................................................................55

11.2

T RANSMIT BOC .........................................................................................................................55

11.3

R ECEIVE BOC ...........................................................................................................................56

12.

E1 SYNCHRONIZATION STATUS MESSAGE ...........................................................................64

12.1

S A /S I B IT A CCESS B ASED ON CRC4 M ULTIFRAME ......................................................................64

12.2

A LTERNATE S A /S I B IT A CCESS B ASED ON D OUBLE -F RAME .........................................................74

13.

LINE INTERFACE UNIT (LIU)......................................................................................................77

13.1

LIU O PERATION .........................................................................................................................78

13.2

LIU R ECEIVER ...........................................................................................................................78

13.2.1

Receive Level Indicator.........................................................................................................78

13.2.2

Receive G.703 Section 10 Synchronization Signal...............................................................79

13.2.3

Monitor Mode ........................................................................................................................79

13.3

LIU T RANSMITTER .....................................................................................................................79

13.3.1

Transmit Short-Circuit Detector/Limiter.................................................................................80

13.3.2

Transmit Open-Circuit Detector ............................................................................................80

13.3.3

Transmit BPV Error Insertion ................................................................................................80

13.3.4

Transmit G.703 Section 10 Synchronization Signal (E1 Mode) ............................................80

13.4

MCLK P RE -S CALER ..................................................................................................................80

13.5

J ITTER A TTENUATOR ..................................................................................................................80

13.6

CMI (C ODE M ARK I NVERSION ) O PTION .......................................................................................81

13.7

LIU C ONTROL R EGISTERS ..........................................................................................................82

13.8

R ECOMMENDED C IRCUITS ..........................................................................................................90

14.

LOOPBACK CONFIGURATION ..................................................................................................95

15.

6312KHZ SYNCHRONIZATION INTERFACE .............................................................................96

15.1

R ECEIVE 6312 K H Z S YNCHRONIZATION I NTERFACE O PERATION ...................................................96

15.2

T RANSMIT 6312 K H Z S YNCHRONIZATION I NTERFACE O PERATION .................................................96

16.

JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT ................................97

16.1

I NSTRUCTION R EGISTER ...........................................................................................................101

16.2

T EST R EGISTERS .....................................................................................................................102

16.3

B OUNDARY S CAN R EGISTER ....................................................................................................102

16.4

B YPASS R EGISTER ...................................................................................................................102

16.5

I DENTIFICATION R EGISTER .......................................................................................................102

17.

FUNCTIONAL TIMING DIAGRAMS ..........................................................................................105

17.1

P ROCESSOR I NTERFACE ...........................................................................................................105

17.1.1

Parallel Port Mode ..............................................................................................................105

17.1.2

SPI Serial Port Mode ..........................................................................................................105

18.

OPERATING PARAMETERS ....................................................................................................108

19.

AC TIMING PARAMETERS AND DIAGRAMS..........................................................................110

19.1

M ULTIPLEXED B US ...................................................................................................................110

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19.2

N ONMULTIPLEXED B US .............................................................................................................113

19.3

S ERIAL B US .............................................................................................................................116

19.4

R ECEIVE S IDE AC C HARACTERISTICS .......................................................................................118

19.5

T RANSMIT S IDE AC C HARACTERISTICS .....................................................................................119

20.

REVISION HISTORY..................................................................................................................121

21.

PACKAGE INFORMATION........................................................................................................122

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LIST OF FIGURES

Figure 3-1. Block Diagram........................................................................................................................11

Figure 3-2. Loopback Mux Diagram (T1/E1 Modes Only) ........................................................................12

Figure 3-3. Transmit PLL Clock Mux Diagram..........................................................................................12

Figure 3-4. Master Clock PLL Diagram ....................................................................................................13

Figure 13-1. Basic Network Connection ...................................................................................................77

Figure 13-2. Typical Monitor Application ..................................................................................................79

Figure 13-3. CMI Coding ..........................................................................................................................81

Figure 13-4. Software-Selected Termination, Metallic Protection.............................................................90

Figure 13-5. Software-Selected Termination, Longitudinal Protection .....................................................91

Figure 13-6. E1 Transmit Pulse Template................................................................................................92

Figure 13-7. T1 Transmit Pulse Template ................................................................................................92

Figure 13-8. Jitter Tolerance (T1 Mode)...................................................................................................93

Figure 13-9. Jitter Tolerance (E1 Mode)...................................................................................................93

Figure 13-10. Jitter Attenuation (T1 Mode)...............................................................................................94

Figure 13-11. Jitter Attenuation (E1 Mode) ..............................................................................................94

Figure 16-1. JTAG Functional Block Diagram ..........................................................................................97

Figure 16-2. TAP Controller State Diagram............................................................................................100

Figure 17-1. SPI Serial Port Access, Read Mode, CPOL = 0, CPHA = 0...............................................105




Figure 17-5. SPI Serial Port Access, Write Mode, CPOL = 0, CPHA = 0...............................................106




Figure 19-1. Intel Bus Read Timing (BTS = 0 / BIS[1:0] = 00)...............................................................111

Figure 19-2. Intel Bus Write Timing (BTS = 0 / BIS[1:0] = 00)................................................................111

Figure 19-3. Motorola Bus Timing (BTS = 1 / BIS[1:0] = 00) ..................................................................112

Figure 19-4. Intel Bus Read Timing (BTS = 0 / BIS[1:0] = 01)................................................................114

Figure 19-5. Intel Bus Write Timing (BTS = 0 / BIS[1:0] = 01)................................................................114

Figure 19-6. Motorola Bus Read Timing (BTS = 1 / BIS[1:0] = 01) ........................................................115

Figure 19-7. Motorola Bus Write Timing (BTS = 1 / BIS[1:0] = 01).........................................................115

Figure 19-8. SPI Interface Timing Diagram, CPHA = 0, BIS[1:0] = 10 ...................................................117

Figure 19-9. SPI Interface Timing Diagram, CPHA = 1, BIS[1:0] = 10 ...................................................117

Figure 19-10. Receive Timing, T1/E1.....................................................................................................118

Figure 19-11. Transmit Timing, T1/E1....................................................................................................120

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LIST OF TABLES

Table 2-1. T1-Related Telecommunications Specifications........................................................................9

Table 2-2. E1-Related Telecommunications Specifications .....................................................................10

Table 5-1. LQFP Pinout............................................................................................................................23

Table 6-1. Transmit Clock Source ............................................................................................................26

Table 6-2. Internal Termination ................................................................................................................26

Table 6-3. E1 Line Build-Out ....................................................................................................................27

Table 6-4. T1 Line Build-Out ....................................................................................................................27

Table 6-5. Receive Path Operating Mode ................................................................................................27

Table 6-6.Transmit Path Operating Mode ................................................................................................28

Table 6-7. MCLK Pre-Scaler for T1 Mode ................................................................................................28

Table 6-8. MCLK Pre-Scaler for E1 Mode................................................................................................29

Table 6-9. Other Operational Modes ........................................................................................................29

Table 7-1. Port Mode Select.....................................................................................................................30

Table 7-2. Register Map Sorted By Address ............................................................................................32

Table 8-1. T1 Alarm Criteria .....................................................................................................................45

Table 9-1. E1 Sync/Resync Criteria .........................................................................................................47

Table 9-2. E1 Alarm Criteria .....................................................................................................................49

Table 10-1. TS Pin Functions ...................................................................................................................53

Table 10-2. RLOF Pin Functions ..............................................................................................................53

Table 11-1. T1 SSM Messages ................................................................................................................55

Table 12-1. E1 SSM Messages................................................................................................................64

Table 13-1. Component List (Software-Selected Termination, Metallic Protection) .................................90

Table 13-2. Component List (Software-Selected Termination, Longitudinal Protection) ..........................91

Table 15-1. Specification of 6312kHz Clock Signal at Input Port ............................................................96

Table 15-2. Specification of 6312kHz Clock Signal at Output Port...........................................................96

Table 16-1. Instruction Codes for IEEE 1149.1 Architecture..................................................................101

Table 16-2. ID Code Structure................................................................................................................102

Table 16-3. Device ID Codes .................................................................................................................102

Table 16-4. Boundary Scan Control Bits ................................................................................................103

Table 18-1. Thermal Characteristics ......................................................................................................108

Table 18-2. Theta-JA ( θ

JA

) vs. Airflow.....................................................................................................108

Table 18-3. Recommended DC Operating Conditions ...........................................................................108

Table 18-4. Capacitance ........................................................................................................................108

Table 18-5. DC Characteristics ..............................................................................................................109

Table 19-1. AC Characteristics, Multiplexed Parallel Port......................................................................110

Table 19-2. AC Characteristics, Non-Mux Parallel Port..........................................................................113

Table 19-3. AC Characteristics, Serial Bus ............................................................................................116

Table 19-4. Receive Side AC Characteristics.........................................................................................118

Table 19-5. Transmit Side AC Characteristics........................................................................................119

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1. FEATURES

1.1 General

64-pin, 10mm x 10mm LQFP package

3.3V supply with 5V-tolerant inputs and outputs

Evaluation kits

IEEE 1149.1 JTAG Boundary Scan

Driver source code available from the factory

1.2 Line Interface

Requires a single master clock (MCLK) for E1, T1, or J1 operation. Master clock can be

2.048MHz, 4.096MHz, 8.192MHz, 12.8MHz (available in CPU interface mode only), or

16.384MHz. Option to use 1.544MHz, 3.088MHz, 6.176MHz, or 12.5552MHz for T1-only operation.

Fully software configurable

Short- and long-haul applications

Automatic receive sensitivity adjustments

Ranges include 0dB to -43dB or 0dB to -12dB for E1 applications; 0dB to -36dB or 0dB to -15dB for T1 applications

Receive level indication in 2.5dB steps from -42.5dB to -2.5dB

Internal receive termination option for 75Ω, 100Ω, 110Ω, and 120Ω lines

Monitor application gain settings of 20dB, 26dB, and 32dB

G.703 receive-synchronization signal mode

Flexible transmit-waveform generation

T1 DSX-1 line build-outs

E1 waveforms include G.703 waveshapes for both 75Ω coax and 120Ω twisted cables

AIS generation independent of loopbacks

Alternating ones and zeros generation

Square-wave output

Open-drain output option

Transmitter power-down

Transmitter 50mA short-circuit limiter with exceeded indication of current limit

Transmit open-circuit-detected indication

1.3 Jitter Attenuator (T1/E1 Modes Only)

32-bit or 128-bit crystal-less jitter attenuator

Requires only a 2.048MHz master clock for both E1 and T1 operation with the option to use

1.544MHz for T1 operation

Can be placed in either the receive or transmit path or disabled

Limit trip indication

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1.4 Framer/Formatter

Full receive and transmit path transparency

T1 framing formats include D4 and ESF

E1 framing formats include FAS and CRC4

Detailed alarm and status reporting with optional interrupt support

RLOF, RLOS, and RAIS alarms interrupt on change of state

Japanese J1 support includes:

− Ability to calculate and check CRC6 according to the Japanese standard

− Ability to generate yellow alarm according to the Japanese standard

1.5 Test and Diagnostics

Remote and Local Loopback

1.6 Control Port

8-bit parallel or serial control port

Multiplexed or nonmultiplexed buses

Intel or Motorola formats

Supports polled or interrupt-driven environments

Software access to device ID and silicon revision

Software-reset supported with automatic clear on power-up

Hardware controller port

Hardware reset pin

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2. SPECIFICATIONS COMPLIANCE

The DS26503 meets all applicable sections of the latest telecommunications specifications including those in the following tables.

Table 2-1. T1-Related Telecommunications Specifications

ANSI T1.102 - Digital Hierarchy Electrical Interface

ANSI T1.231 - Digital Hierarchy–Layer 1 in Service Performance Monitoring

ANSI T1.403 - Network and Customer Installation Interface–DS1 Electrical Interface

TR62411

(ANSI) “Digital Hierarchy – Electrical Interfaces”

(ANSI) “Digital Hierarchy – Formats Specification”

(ANSI) “Digital Hierarchy – Layer 1 In-Service Digital Transmission Performance Monitoring”

(ANSI) “Network and Customer Installation Interfaces–DS1 Electrical Interface”

(AT&T) “Requirements for Interfacing Digital Terminal Equipment to Services Employing the Extended

Super frame Format”

(AT&T) “High Capacity Digital Service Channel Interface Specification”

(TTC) “Frame Structures on Primary and Secondary Hierarchical Digital Interfaces”

(TTC) “ISDN Primary Rate User-Network Interface Layer 1 Specification”

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Table 2-2. E1-Related Telecommunications Specifications

ITUT G.703 Physical/Electrical Characteristics of G.703 Hierarchical Digital Interfaces

ITUT G.736 Characteristics of Synchronous Digital Multiplex Equipment operating at 2048kbps

ITUT G.742 Second-Order Digital Multiplex Equipment Operating at 8448kbps

ITUT G.772

ITUT G.775

ITUT G.823 The control of jitter and wander within digital networks, which are based on 2.048kbps hierarchy

ETSI 300 233

(ITU) “Synchronous Frame Structures used at 1544, 6312k, 2048, 8488, and 44,736kbps Hierarchical

Levels”

(ITU) “Frame Alignment and Cyclic Redundancy Check (CRC) Procedures Relating to Basic Frame

Structures Defined in Recommendation G.704”

(ITU) “Characteristics of primary PCM Multiplex Equipment Operating at 2048kbps”

(ITU) Characteristics of a synchronous digital multiplex equipment operating at 2048kbps”

(ITU) “Loss Of Signal (LOS) and Alarm Indication Signal (AIS) Defect Detection and Clearance

Criteria”

(ITU) “The Control of Jitter and Wander Within Digital Networks Which are Based on the 2048kbps

Hierarchy”

(ITU) “Primary Rate User-Network Interface – Layer 1 Specification”

(ITU) “Error Performance Measuring Equipment Operating at the Primary Rate and Above”

(ITU) “In-service code violation monitors for digital systems”

(ETSI) “Integrated Services Digital Network (ISDN); Primary rate User-Network Interface (UNI); Part

1/ Layer 1 specification”

(ETSI) “Transmission and multiplexing; Physical/electrical characteristics of hierarchical digital interfaces for equipment using the 2048kbps-based plesiochronous or synchronous digital hierarchies”

(ETSI) “Integrated Services Digital Network (ISDN); Access digital section for ISDN primary rate”

(ETSI) “Integrated Services Digital Network (ISDN); Attachment requirements for terminal equipment to connect to an ISDN using ISDN primary rate access”

(ETSI) “Business Telecommunications (BT); Open Network Provision (ONP) technical requirements;

2048lkbps digital unstructured leased lines (D2048U) attachment requirements for terminal equipment interface”

(ETSI) “Business Telecommunications (BTC); 2048kbps digital structured leased lines (D2048S);

Attachment requirements for terminal equipment interface”

(ITU) “Synchronous Frame Structures used at 1544, 6312, 2048, 8488, and 44,736kbps Hierarchical

Levels”

(ITU) “Frame Alignment and Cyclic Redundancy Check (CRC) Procedures Relating to Basic Frame

Structures Defined in Recommendation G.704”

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3. BLOCK DIAGRAMS

Figure 3-1. Block Diagram

MCLK

JA CLOCK

DS26503

MASTER CLOCK

RTIP

RRING

RLOS

RAIS

TTIP

LIU

TX

LIU

CLOCK

+ DATA

- DATA

L

O

C

A

L

P

B

A

L

O

O

C

K

M

U

X

JA

ENABLED

AND IN RX

JITTER

ATTENUATOR

CAN BE

ASSIGNED TO

RECEIVE OR

TRANSMIT PATH

OR DISABLED

B

A

C

K

L

O

O

P

JA

ENABLED

AND IN TX

PATH

M

U

X

O

T

E

R

E

M

PLL

CLOCK

MUX

TX CLOCK

+ DATA

- DATA

T1/E1 SSM

FRAMER

T1/E1 SSM

FORMATTER

RCLK

LOF_CCE

RSER

RS

TCLK

PLL_OUT

TSER

TS

JTMS JTRST JTCLK JTDI JTDO

PARALLEL/SERIAL CPU I/F

HARDWARE CONTROLLER

BIS1 BIS0

PARALLEL,

SERIAL, OR

HARDWARE

CONTROLLER

TSTRST

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Figure 3-2. Loopback Mux Diagram (T1/E1 Modes Only)

FROM RX

LIU

TO TX

LIU

CLOCK

+ DATA

- DATA

CLOCK

+ DATA

- DATA

JITTER

ATTENUATOR

ENABLED AND

IN RX PATH

JITTER

ATTENUATOR

ENABLED AND

IN TX PATH

REMOTE

LOOPBACK

(LBCR.4)

LOCAL

LOOPBACK

(LBCR.3)

RCLK

+ DATA

- DATA

TX CLOCK

+ DATA

- DATA

TO RX

FRAMER

FROM TX

FORMATTER

Figure 3-3. Transmit PLL Clock Mux Diagram

TPCR.3

TPCR.4

TPCR.6

TPCR.7

TPCR.5

TPCR.2

IN

SEL

OUT

SEL

PLL_OUT PIN

RECOVERED CLOCK

TCLK PIN

TX PLL

OUTPUT = 1.544MHz,

2.048MHz, 6.312MHz

TX CLOCK

JA CLOCK

(HARDWARE MODE PIN NAME)

TPCR.0

(TCSS0)

TPCR.1

(TCSS1)

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Figure 3-4. Master Clock PLL Diagram


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4. PIN FUNCTION DESCRIPTION

4.1 Transmit PLL

NAME TYPE FUNCTION

Transmit PLL Output. This pin can be selected to output the 1544kHz,

PLL_OUT O 2048kHz, 64kHz, or 6312kHz output from the internal TX PLL or the internal signal, TX CLOCK. See

Figure 3-3 and

Figure 3-4 .

Transmit Clock Input. A 64kHz, 1.544MHz, 2.048MHz, or 6312kHz primary

section. See Figure 3-3 and

Figure 3-4 .

4.2 Transmit Side


Transmit Serial Data. Source of transmit data sampled on the falling edge of

TX CLOCK (an internal signal). See Figure 3-3 ,

Figure 3-4 , and

Figure 19-11

(transmit timing diagram).

TSYNC. When in input mode, this pin is sampled on the falling edge of TX

CLOCK (an internal signal) and a pulse at this pin will establish either frame or

multiframe boundaries for the transmit side. See Figure 3-1 and

Figure 19-11 .

TS I/O

In output mode, the pin is updated on the rising edge of TX CLOCK (an internal signal) and can be programmed to output a frame or multiframe sync

pulse useful for aligning data. See Figure 3-1

and Figure 19-11 .

Transmit Positive-Data Output. In T1 or E1 mode, updated on the rising edge bit. In 6312kHz mode, this pin is low.

Transmit Negative-Data Output. In T1 or E1 mode, updated on the rising edge of TCLKO with the bipolar data out of the transmit-side formatter. In

6312kHz mode, this pin is low.

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4.3 Receive Side

NAME TYPE

RS


FUNCTION

O

Receive Sync

T1/E1 Mode: An extracted pulse, one RCLK wide, is output at this pin that identifies either frame (IOCR1.5 = 0) or multiframe (IOCR1.5 = 1) boundaries. If set to output frame boundaries, then through IOCR1.6, RS can also be set to output double-wide pulses on signaling frames in T1 mode.

6312kHz Mode: This pin will be in a high-impedance state.

Receive Serial Data


Receive Loss Of Frame. This output can be configured to be a Loss Of

Transmit Clock indicator via IOCR.4 when operating in T1 or E1 mode. transitioned for approximately 15 periods of the scaled MCLK (LOTC mode).


Receive Loss Of Signal

T1 Mode: High when 192 consecutive zeros detected.

RLOS O

E1 Mode: High when 255 consecutive zeros detected.

6312kHz Mode: High when consecutive zeros detected for 65 µs typically.

Receive Alarm Indication Signal

T1 Mode: Will toggle high when receive Blue Alarm is detected.

RAIS O

E1 Mode: Will toggle high when receive AIS is detected.


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4.4 Controller Interface


Active-Low Interrupt/Jitter Attenuator Clock Select 0

INT/

JACKS0

I/O

INT

: Flags host controller during events, alarms, and conditions defined in the status registers. Active-low open-drain output.

JACKS0: Hardware Mode: Jitter Attenuator Clock Select 0. Set this pin high for T1 mode operation when either a 2.048MHz, 4.096MHz, 8.192MHz or

16.382MHz signal is applied at MCLK.

Transmit Mode Select 1. In Hardware Mode (BIS[1:0] = 11), this bit is used

TMODE1 I to configure the transmit operating mode.

Transmit Mode Select 2. In Hardware Mode (BIS[1:0] = 11), this bit is used

TMODE2 I to configure the transmit operating mode.

Three-State Control and Device Reset. A dual-function pin. A zero-to-one transition issues a hardware reset to the DS26503 register set. Configuration all output and I/O pins (including the parallel control port). Set low for normal operation. Useful for in-board level testing.

Processor Interface Mode Select 1, 0. These bits select the processor interface mode of operation.

AD[7]/

RITD

AD[6]/

TITD

I/O

I/O

01 = Parallel Port Mode (Nonmultiplexed)

10 = Serial Port Mode

11 = Hardware Mode

Data Bus D[7] or Address/Data Bus AD[7]/Receive Internal Termination

Disable

A[7]: In nonmultiplexed bus operation (BIS[1:0] = 01), it serves as the data bus D[7].

AD[7]: In multiplexed bus operation (BIS[1:0] = 00), it serves as the multiplexed address/data bus AD[7].

RITD: In Hardware Mode (BIS[1:0] = 11), internal receive termination is disabled when RITD = 1.

Data Bus D[6] or Address/Data Bus AD[6]/Transmit Internal Termination

Disable



TITD: In Hardware Mode (BIS[1:0] = 11), internal transmit termination is disabled when TITD = 1.

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NAME TYPE


FUNCTION

Data Bus D[5] or Address/Data Bus AD[5]/Receive Framing Mode Select

Bit 1

AD[5]/

RMODE1

I/O



AD[4]/

RMODE0

I/O

RMODE1: In Hardware Mode (BIS[1:0] = 11), it selects the receive side operating mode.

Data Bus D[4] or Address/Data Bus AD[4]/Receive Framing Mode Select

Bit 0



RMODE0: In Hardware Mode (BIS[1:0] = 11), it selects the receive side operating mode.

Data Bus D[3] or Address/Data Bus AD[3]/TS Mode Select


AD[3]/TSM I/O


TSM: In Hardware Mode (BIS[1:0] = 11), this pin selects the function of TS.

Please see the register descriptions for more detailed information.

Data Bus D[2] or Address/Data Bus AD[2]/RS Mode Select/Serial Port

Clock


AD[2]/RSM/

SCLK

I/O AD[2]: In multiplexed bus operation (BIS[1:0] = 00), it serves as the multiplexed address/data bus AD[2].

RSM: In Hardware Mode (BIS[1:0] = 11), this pin selects the function of RS.

Please see the register descriptions for more detailed information.

SCLK: In Serial Port mode this is the serial clock input.

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NAME TYPE


FUNCTION

Data Bus D[1] or Address/Data Bus AD[1]/Receive Mode Select 3/Master

Out-Slave In

AD[1]/

RMODE3/

MOSI

I/O



RMODE3: In Hardware Mode (BIS[1:0] = 11), this pin selects the receive side operating mode.

MOSI: Serial data input called Master Out-Slave In for clarity of data transfer direction.

Data Bus D[0] or Address/Data Bus AD[0]/Transmit Clock Source Select

0/Master In-Slave Out

AD[0]/

TCSS0/

MISO

I/O



TCSS0: Transmit Clock Source Select 0.

MISO: In serial bus mode (BIS[1:0] = 10), this pin serves as the serial data output Master In-Slave Out.

TCSS1 I Transmit Clock Source Select 1

Address Bus Bit A[6]/MCLK Prescale Select 0

A6: In nonmultiplexed bus operation (BIS[1:0] = 01), this pin serves as A[6].

A5/CPOL/

TMODE0 I

MPS0: In Hardware Mode (BIS[1:0] = 11), MCLK prescale select is used to set the prescale value for the PLL.

Address Bus Bit A[5]/Serial Port Clock Polarity Select/Transmit Mode

Select 0


In multiplexed bus operation (BIS[1:0] = 00), these pins are not used and should be tied low.

CPOL: In Serial Port Mode (BIS[1:0] = 10), this pin selects the serial port clock polarity. Please see the functional timing diagrams for the Serial Port

Interface for more information.

TMODE0: In Hardware Mode (BIS[1:0] = 11), this pin is used to configure the transmit operating mode.

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Address Bus Bit A[4]/Serial Port Clock Phase Select/Line Build-Out

Select 2

A4/CPHA/

L2

I



CPHA: In Serial Port Mode (BIS[1:0] = 10), this pin selects the serial port clock phase. See the functional timing diagrams for the Serial Port Interface for more information.

L2: In Hardware Mode (BIS[1:0] = 11), this pin selects the line build-out value.

Address Bus Bit A[3]/Line Build-Out Select 1


In multiplexed bus operation (BIS[1:0] = 00), these pins are not used and

A3/L1 I should be tied low.


Address Bus Bit A[2]/Line Build-Out Select 0



A2/L0 I should be tied low.


Address Bus Bit A[1]/Transmit AIS

A1/TAIS

I



TAIS: When set to a 0 and in T1/E1 operating modes, the transmitter will transmit an AIS pattern. Set to 1 for normal operation. This pin is ignored in all other operating modes.

Address Bus Bit A[0]/E1 Termination Select



A0/E1TS I should be tied low.

E1TS: In Hardware Mode (BIS[1:0] = 11), selects the E1 internal termination value (0 = 75

Ω, 1 = 120Ω).

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NAME TYPE


FUNCTION

Bus Type Select/Transmit and Receive B8ZS/HDB3 Enable

BTS: Strap high to select Motorola bus timing; strap low to select Intel bus timing. This pin controls the function of the RD (DS), ALE (AS), and WR

BTS/HBE I W) pins. If BTS = 1, then these pins assume the function listed in parentheses ().

RD(DS)/

RMODE2

CS/RLB

I

I

HBE: In Hardware Mode (BIS[1:0] = 11), this pin enables transmit and receive

B8ZS/HDB3 when in T1/E1 operating modes.

Read Input-Data Strobe/Receive Mode Select Bit 2

RD ( DS ): These pins are active-low signals. DS is active high when BIS[1:0]

= 01. See the bus timing diagrams.

RMODE2: In Hardware Mode (BIS[1:0] = 11), this pin selects the receive side operating mode.

Chip Select/Remote Loopback Enable

CS : This active-low signal must be low to read or write to the device. This signal is used for both the parallel port and the serial port modes.

ALE (AS)/

A7/MPS1

I

RLB: In Hardware Mode (BIS[1:0] = 11), when high, remote loopback is enabled. This function is only valid when the transmit side and receive side are in the same operating mode.

Address Latch Enable (Address Strobe)/Address Bus Bit 7/MCLK

Prescale Select 1

ALE (AS): In multiplexed bus operation (BIS[1:0] = 00), it serves to demultiplex the bus on a positive-going edge.


WR (R/W)/

TMODE3

I

MPS1: In Hardware Mode (BIS[1:0] = 11), MCLK prescale select, used to set the prescale value for the PLL.

Write Input (Read/Write)/Transmit Mode Select 3

WR : In Processor Mode, this pin is the active-low write signal.

TMODE3: In Hardware Mode, this pin selects the transmit-side operating mode.

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4.5 JTAG

NAME TYPE


FUNCTION

JTAG Data Input (with Pullup). This input signal is used to input data into on the rising edge of JTCLK.

JTAG Data Output. This output signal is the output of an internal scan shift register enabled by the JTAG controller state machine and is updated on the falling edge of JTCLK. The pin is in the high-impedance mode when a register is not selected or when the JTRST signal is high. The pin goes into and exits the

JTRST I high impedance mode after the falling edge of JTCLK

JTAG Reset (Active Low). This input forces the JTAG controller logic into the reset state and forces the JTDO pin into high impedance when low. This pin should be low while power is applied and set high after the power is stable.

The pin can be driven high or low for normal operation, but must be high for

JTAG operation.

4.6 Line Interface


Master Clock Input. A (50ppm) clock source. This clock is used internally for both clock/data recovery and for the jitter attenuator for both T1 and E1 modes.

The clock rate can be 16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz. When using the DS26503 in T1-only operation, a 1.544MHz (50ppm) clock source can be used.

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4.7 Power

NAME TYPE


FUNCTION

22 of 122


5. PINOUT

Table 5-1. LQFP Pinout

PIN TYPE PARALLEL

PORT

1 I/O AD2

2 I/O AD3

3 I/O AD4

4 I/O AD5

5 I/O AD6

6 I/O AD7

MODE

SERIAL

PORT

HARDWARE

FUNCTION

SCLK RSM

Parallel Port Mode: Address/Data Bus Bit 2

Serial Port Mode: Serial Clock

Hardware Mode: RS Mode Select

— TSM


Serial Port Mode: Unused, should be connected to V

SS

.

Hardware Mode: TS Mode Select


— RMODE0

Hardware Mode: Receive Mode Select 0

SS

.

—


RMODE1


SS

.

—

—

TITD



SS

.

Hardware Mode: Transmit Internal Termination Disable

RITD



SS

.

Hardware Mode: Receive Internal Termination Disable

7, 24,

58

8, 22,

56

9 I A0

10 I A1

11 I A2

12 I A3

13 I A4

14 I A5

15 I A6

—

—

—

—

CPHA

L1

L2

Parallel Port Mode: Address Bus Bit 0


SS

Hardware Mode: E1 Internal Termination Select

.

TAIS



SS

.

Hardware Mode: Transmit AIS

L0



Hardware Mode: Line Build-Out Select 0

SS

.



SS

.



Serial Port Mode: Serial Port Clock Phase Select



CPOL TMODE0

Hardware Mode: Transmit Mode Select 0

— MPS0



SS

.

Hardware Mode: MCLK Pre-Scaler Select 0

MPS1

Parallel Port Mode: Address Latch Enable/Address Bus

Bit 7


SS

Hardware Mode: MCLK Pre-Scaler Select 1

.

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PORT

MODE

SERIAL

PORT

HARDWARE


FUNCTION

23

26

27

I/O

O

—

TS

RS

N.C.

TS

RS

N.C.

TS

RS

N.C.

T1/E1 Mode: Transmit Frame/Multiframe Sync

T1/E1 Mode: Receive Frame/Multiframe Boundary

No Connect. This pin must be left open.

31 I —

34 I JTCLK

—

JTCLK JTCLK

Parallel Port Mode: Unused, should be connected to

V

SS

.


SS

Hardware Mode: Transmit Clock Source Select 1

.

1149.1 Select

IEEE 1149.1 Test Clock Signal

40,

43, 45

41 I RTIP RTIP RTIP Receive Analog Tip Input

46 I/O

48 I

49 I

51 O

INT INT

—

—

TTIP

Parallel Port Mode: Active-Low Interrupt

Serial Port Mode: Active-Low Interrupt

Hardware Mode: Jitter Attenuator Clock Select 0


— TMODE2 SS

.


SS


.

—


TMODE1 SS

.


SS


.

TTIP TTIP Transmit Analog Tip Output

55 I BTS — HBE

Parallel Port Mode: Bus Type Select (Motorola/Intel)


SS

.

Hardware Mode: Receive and Transmit DB3/B8ZS

Enable

BIS0 BIS0 BIS0 Interface Select Mode 0

BIS1 BIS1 BIS1 Interface Select Mode 1

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PORT

MODE

SERIAL

PORT

HARDWARE

FUNCTION

60 I

64 I/O

CS CS RLB

AD1

Parallel Port Mode: Active-Low Chip Select

Serial Port Mode: Active-Low Chip Select

Hardware Mode: Remote Loopback Enable

Parallel Port Mode: Active-Low Read Input (Data

61 I RD (DS) — RMODE2


SS


.

Parallel Port Mode: Active-Low Write Input

62 I WR (R/W) — TMODE3


SS


.

63 I/O AD0 MIS0 TCSS0


Serial Port Mode: Serial Data Out (Master In-Slave

Out)

Hardware Mode: Transmit Clock Source Select 0

MOSI


Serial Port Mode: Serial Data In (Master Out-Slave In)


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6. HARDWARE CONTROLLER INTERFACE

In Hardware Controller mode, the parallel and serial port pins are reconfigured to provide direct access to certain functions in the port. Only a subset of the device’s functionality is available in hardware mode.

Each register description throughout the data sheet indicates the functions that may be controlled in hardware mode and several alarm indicators that are available in both hardware and processor mode.

Also indicated are the fixed states of the functions not controllable in hardware mode.

6.1 Transmit Clock Source

Refer to

Figure 3-3 . In Hardware Controller mode, the input to the TX PLL is always TCLK PIN. TX

CLOCK is selected by the TCSS0 and TCSS1 pins, as shown in

Table 6-1 . The PLL_OUT pin is always

the same signal as select for TX CLOCK. If the user wants to slave the transmitter to the recovered clock, then the RCLK pin must be tied to the TCLK pin externally.

Table 6-1. Transmit Clock Source

TCSS1

PIN 31

TCSS0

PIN 63

TRANSMIT CLOCK SOURCE

0 0 The TCLK pin is the source of transmit clock.

0 1 The PLL_CLK is the source of transmit clock.

1 1 The signal present at RCLK is the transmit clock.

6.2 Internal Termination

In Hardware Controller mode, the internal termination is automatically set according to the receive or transmit mode selected. It can be disabled via the TITD and RITD pins. If internal termination is enabled in E1 mode, the E1TS pin is use to select 75 Ω or 120Ω termination. The E1TS pin applies to both transmit and receive.

Table 6-2. Internal Termination

PIN NAME FUNCTION

TITD

PIN 5

RITD

PIN 6

E1TS

PIN 9

Transmit Internal Termination Disable. Disables the internal transmit termination. The internal transmit termination value is dependent on the state of the TMODEx pins.

Receive Internal Termination Disable. Disables the internal receive termination. The internal receive termination value is dependent on the state of the RMODEx pins.

E1 Termination Select. Selects 120 Ω or 75Ω internal termination when one of the E1 modes is selected and internal termination is enabled. IF E1 is selected for both transmit and receive, then both terminations will be the same.

0 = 75 Ω

1 = 120 Ω

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6.3 Line Build-Out

Table 6-3. E1 Line Build-Out

L2

PIN 13

L1

PIN 12

L0

PIN 11

0 0 0

0 0 1

APPLICATION

75Ω normal

120Ω normal

N

(NOTE 1)

1:2

1:2

1:2

1:2

RETURN

LOSS

N.M.

N.M.

21dB

21dB

Rt

(NOTE 1)

0

0

6.2Ω

11.6Ω

— — —

— — —

1 Reserved

1 Reserved

Table 6-4. T1 Line Build-Out

L2

PIN 13

0

0

0

0

1

L1

PIN 12

0

0

1

1

0

L0

PIN 11

0

1

0

1

0

APPLICATION

DSX-1 (0 to 133 feet)/0dB CSU

DSX-1 (133 to 266 feet)

DSX-1 (266 to 399 feet)

DSX-1 (399 to 533 feet)

DSX-1 (533 to 655 feet)

N

(NOTE 1)

1:2

1:2

RETURN

LOSS

N.M.

N.M.

Rt

(NOTE 1)

0

0

1:2

1:2

N.M.

N.M.

0

0

1:2 N.M. 0

— — —

— — —

— — —

Note 1: Transformer turns ratio.

Note 2: TTD pin must be connected high in this mode.

N.M. = not meaningful

6.4 Receiver Operating Modes

Table 6-5. Receive Path Operating Mode

RMODE3

PIN 64

RMODE2

PIN 61

RMODE1

PIN 4

RMODE0

PIN 3

0 0 0 0

0 0 0 1

RECEIVE PATH OPERATING MODE

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1 E1 CAS and CRC4

1 0 0 0 E1 G.703 2048kHz Synchronization Interface

1 0 0 1 Reserved

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

Reserved

6312kHz Synchronization Interface

Reserved

Reserved

Reserved

Reserved

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6.5 Transmitter Operating Modes

Table 6-6.Transmit Path Operating Mode

TMODE3

PIN 62

TMODE2

PIN 48

TMODE1

PIN 49

TMODE0

PIN 14

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

TRANSMIT PATH OPERATING MODE

0 1 0 0

0 1 0 0

0 1 0 1

0 1 1 0

E1 FAS + CAS (Note 1)

Reserved

0 1 1 0

0 1 1 1

1 0 0 0

Reserved

E1 G.703 2048kHz Synchronization Interface

1 0 0 1

1 0 1 0

Reserved

Reserved

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

Reserved

Reserved

Reserved

Reserved

Note 1: The DS26503 does not have an internal source for CAS signaling and multiframe alignment generation. CAS signaling, and the multiframe alignment word, must be embedded in the transmit data (in the TS16 position) present on the TSER pin and frame aligned to sync signal on the TS pin.

Note 2: In addition to setting the TMODE bits to 6312kHz Synchronization Interface mode, the Transmit PLL must also be configured to transmit a 6312kHz signal through the Transmit PLL Control Register (TPCR.6 and TPCR.7).

6.6 MCLK Pre-Scaler

Table 6-7. MCLK Pre-Scaler for T1 Mode

MPS1

PIN 16

MPS0

PIN 15

JACKS0

PIN 46

MCLK

(MHz)

28 of 122

Table 6-8. MCLK Pre-Scaler for E1 Mode

MPS1

PIN 16

MPS0

PIN 15

JACKS0

PIN 46

MCLK

(MHz)


6.7 Other Hardware Controller Mode Features

Table 6-9. Other Operational Modes

PIN

NAME

DESCRIPTION

RSM

PIN 1

TSM

PIN2

RLB

PIN 60

TAIS

PIN 10

HBE

PIN 55

RS Mode Select: Selects frame or multiframe pulse at RS pin.

0 = frame mode

1 = multiframe mode

TS Mode Select: In T1 or E1 operation, selects frame or multiframe mode for the TS pin.

0 = frame mode

1 = multiframe mode

Remote Loopback Enable: In this loopback, data input to the framer portion of the

DS26503 will be transmitted back to the transmit portion of the LIU. Data will continue to pass through the receive side framer of the DS26503 as it would normally and the data from the transmit side formatter will be ignored.

0 = loopback disabled

1 = loopback enabled

Transmit AIS

0 = transmit AIS alarm

1 = normal transmission

Receive and Transmit HDB3/B8ZS Enable

0 = HDB3/B8ZS disabled

1 = HDB3/B8ZS enabled

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7. PROCESSOR INTERFACE

The DS26503 is controlled via a nonmultiplexed (BIS[1:0] = 01) or a multiplexed (BIS[1:0] = 00) parallel bus. There is also a serial bus mode option, as well as a hardware mode of operation. The bus

interface type is selected by BIS1 and BIS0 as shown in Table 7-1 .

Table 7-1. Port Mode Select

BIS1 BIS0

0

0

1

0

1

0

Parallel Port Mode (Multiplexed)

Parallel Port Mode (Nonmultiplexed)

Serial Port Mode (SPI)

7.1 Parallel Port Functional Description

In parallel mode, the DS26503 can operate with either Intel or Motorola bus timing configurations. If the

BTS pin is tied low, Intel timing will be selected; if tied high, Motorola timing will be selected. All

Motorola bus signals are listed in parentheses (). See the timing diagrams in the AC Electrical

Characteristics section for more details.

7.2 SPI Serial Port Interface Functional Description

A serial SPI bus interface is selected when bus select is 10 (BIS[1:0] = 10). In this mode, a master/slave relationship is enabled on the serial port with three signal lines (SCK, MOSI, and MISO) and a chip select ( CS), with the DS26503 acting as the slave. Port read/write timing is not related to the system read/write timing, thus allowing asynchronous, half-duplex operation. See the AC Electrical

Characteristics section for the AC timing characteristics of the serial port.

7.2.1 Clock Phase and Polarity

Clock Phase and Polarity are selected by the CPHA and CPOL pins. The slave device should always be

configured to match the bus master. See the SPI Serial Port Mode section for detailed functional timing

diagrams.

7.2.2 Bit Order

The most significant bit (MSB) of each byte is transmitted first.

7.2.3 Control Byte

The bus master will transmit two control bytes following a chip select to a slave device. The MSB will be a R/ W bit (1=read, 0=write). The next 6 bits will be padded with 0s. The LSB of the first byte will be

A[7]. The second control byte will be the address bits (A[6:0]) of the target register, followed by a Burst bit in the LSB position (1=Burst, 0=Non-burst).

7.2.4 Burst Mode

The last bit of the second control byte (LSB) is the Burst mode bit. When the Burst bit is enabled (set to

1) and a read operation is performed, the register address is automatically incremented after the LSB of the previous byte read to the next register address. Data will be available on the next clock edge following the LSB of the previous byte read. When the Burst bit is enabled (set to 1) and a write operation is performed, the register address will be automatically incremented to the next byte boundary following the

LSB of the previous register write, and 8 more data bits will be expected on the serial bus. Burst accesses

30 of 122

DS26503 T1/E1/J1 BITS Element are terminated when CS is removed. If CS is removed before all 8 bits of the data are read, the remaining data will be lost. If CS is removed before all 8 bits of data are written to the part, no write access will occur and the target register will not be updated.

Note: During a Burst read access, data must be fetched internally to the part as the LSB of the previous byte is transmitted out. If this pre-fetch read access occurs to a Clear-On-Read register or a FIFO register address, and the Burst access is terminated without reading this byte out of the port, the data will be lost and/or the register cleared. Users should not terminate their Burst Read accesses at the address byte proceeding a Clear-On-Read register or a FIFO register. Data loss could occur due to the internal prefetch operation performed by the interface.

7.2.5 Register Writes

The register write sequence is shown in the functional timing diagrams in Section

17 . After a

CS, the bus master transmits a write control byte containing the R/ W bit, the target register address, and the Burst bit.

These two control bytes will be followed by the data byte to be written. After the first data byte, if the

Burst bit is set, the DS26503 auto-increments its address counter and writes each byte received to the next higher address location. After writing address FFh, the address counter rolls over to 00h and continues to auto-increment.

7.2.6 Register Reads

The register read sequence is shown in Section

17 . After a

CS, the bus master transmits a read control byte containing the R/ W bit, the target register address, and the Burst bit. After these two control bytes, the DS26503 responds with the requested data byte. After the first data byte, if the Burst bit is set, the

DS26503 auto-increments its address counter and transmits the byte stored in the next higher address location. Note the warning mentioned above as data loss could potentially occur due to the data pre-fetch that is required to support this mode. After reading address FFh, the address counter rolls over to 00h and continues to auto-increment.

31 of 122


7.3 Register Map

Table 7-2. Register Map Sorted By Address

ADDRESS TYPE

00

01

17

18

19

1A

1B

1C

1D

1E

1F

20

R/W Test Reset Register

R/W I/O Configuration Register 1

REGISTER

ABBREVIATION

TSTRREG

IOCR1

10

11

12

13

14

15

16

02

03

04

05

06

07

08

R/W I/O Configuration Register 2

R/W T1 Receive Control Register 1

R/W T1 Receive Control Register 2

R/W T1 Transmit Control Register 1

R/W T1 Transmit Control Register 2

R/W T1 Common Control Register

R/W Mode Configuration Register

IOCR2

T1RCR1

T1RCR2

T1TCR1

T1TCR2

T1CCR

MCREG

09 R/W Transmit PLL Control Register

TPCR

0A — Reserved —

0B — Reserved —

0C — Reserved —

0D — Reserved —

0E — Reserved —

0F — Reserved —

R

R

R

R

Device Identification Register

Information Register 1

Information Register 2

Interrupt Information Register

R Status Register 1

R/W Interrupt Mask Register 1

R Status Register 2

IDR

INFO1

INFO2

IIR

SR1

IMR1

SR2


R Status Register 3


R Status Register 4


R Information Register 3

R/W E1 Receive Control Register

R/W E1 Transmit Control Register

R/W BOC Control Register

R/W Loopback Control Register

40

41

42

43

30

31

32

33

34

R/W Line Interface Control 1




R/W Transmit Line Build-Out Control

R/W Transmit Align Frame Register

R/W Transmit Non-Align Frame Register

R/W Transmit Si Align Frame

R/W Transmit Si Non-Align Frame

IMR2

SR3

IMR3

SR4

IMR4

INFO3

E1RCR

E1TCR

BOCC

LBCR

—

LIC1

LIC2

LIC3

LIC4

TLBC

—

TAF

TNAF

TSiAF

TSiNAF

32 of 122

ADDRESS TYPE

44

45

46

47

48

49

4A

R/W Transmit Remote Alarm Bits

R/W Transmit Sa4 Bits





R/W Transmit Sa Bit Control Register

56

57

58

59

5A

5B

5C

5D

5E

5F

50

51

52

53

R Receive FDL Register

R/W Transmit FDL Register

R/W Receive Facility Data Link Match Register 1

R/W Receive Facility Data Link Match Register 2

R

R

R

R

R

R

R

R

R

R

Receive Align Frame Register

Receive Non-Align Frame Register

Receive Si Align Frame

Receive Si Non-Align Frame

Receive Remote Alarm Bits

Receive Sa4 Bits

Receive Sa5 Bits

Receive Sa6 Bits

Receive Sa7 Bits

Receive Sa8 Bits


REGISTER

ABBREVIATION

TRA

TSa4

TSa5

TSa6

TSa7

TSa8

TSACR

—

RFDL

TFDL

RFDLM1

RFDLM2

—

RAF

RNAF

RSiAF

RSiNAF

RRA

RSa4

RSa5

RSa6

RSa7

RSa8

—

TEST1*

TEST2*

TEST3*

TEST4*

TEST5*

TEST6*

TEST7*

TEST8*

TEST9*

TEST10*

TEST11*

TEST12*

TEST13*

TEST14*

TEST15*

TEST16*

*TEST1 to TEST16 registers are used only by the factory.

33 of 122


7.3.1 Power-Up Sequence

The DS26503 contains an on-chip power-up reset function, which automatically clears the writeable register space immediately after power is supplied to the device. The user can issue a chip reset at any time. Issuing a reset will disrupt signals flowing through the DS26503 until the device is reprogrammed.

The reset can be issued through hardware using the TSTRST pin or through software using the SFTRST function in the master mode register. The LIRST (LIC2.6) should be toggled from zero to one to reset the line interface circuitry. (It will take the DS26503 about 40ms to recover from the LIRST bit being toggled.)

7.3.2 Test Reset Register

Register Name:

Register Description:

Register Address:

TSTRREG

Test Reset Register

00h

HW

Mode

X X X X X X X X

Bit 0: Software-Issued Reset (SFTRST). A zero-to-one transition causes the register space in the DS26503 to be cleared. A reset clears all configuration and status registers. The bit automatically clears itself when the reset has completed.

Bits 1, 2, 3, 6, 7: Unused, must be set = 0 for proper operation.

Bits 4 and 5: Test Mode Bits (TEST0, TEST1). Test modes are used to force the output pins of the DS26503 into known states. This can facilitate the checkout of assemblies during the manufacturing process and also be used to isolate devices from shared buses.

TEST1 TEST0 Effect On Output Pins

0

1

1

1

0

1

Force all output pins into three-state (including all I/O pins and parallel port pins)

Force all output pins low (including all I/O pins except parallel port pins)

Force all output pins high (including all I/O pins except parallel port pins)

34 of 122


7.3.3 Mode Configuration Register

Register Name:


Register Address:

MCREG

Mode Configuration Register

08h

Name TMODE3 TMODE2 TMODE1 TMODE0 RMODE3 RMODE2 RMODE1 RMODE0

HW

Mode

TMODE3

PIN 62

TMODE2

PIN 48

TMODE1

PIN 49

TMODE0

PIN 14

RMODE3

PIN 64

RMODE2

PIN 61

RMODE1

PIN 4

RMODE0

PIN 3

Bit 0 to 3: Receive Mode Configuration (RMODE[3:0]). Used to select the operating mode of the receive path for the

DS26503.

Receive Path Operating Mode RMODE3 RMODE2 RMODE1 RMODE0

0 0 0 0

0 0 0 1

0 0 1 0

T1 ESF

J1 ESF 0 0 1 1

0 1 0 0

0

0

1

1

0

1

1

0

0

1

1

0

1

0

1

0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

E1 CAS

E1 CRC4

E1 CAS and CRC4

E1 G.703 2048kHz Synchronization Interface

Reserved

Reserved

6312kHz Synchronization Interface

Reserved

Reserved

Reserved

Reserved

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Bits 4 to 7: Transmit Mode Configuration (TMODE[3:0]). Used to select the operating mode of the transmit path for the

DS26503.

TMODE3 TMODE2 TMODE1 TMODE0 Transmit Path Operating Mode

0 0 0 0

0 0 0 1 ESF

set = 0.)

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 0

J1 ESF

0 1 0 1

0 1 1 0

0

1

1

0

1

1

0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1

1 1 0 0

1 1 0 1

E1 FAS + CAS (Note 1)

Reserved

E1 CRC4 + CAS (Note 1)

Reserved

E1 G.703 2048 kHz Synchronization Interface

Reserved

Reserved

6312kHz Synchronization Interface (Note 2)

Reserved

Reserved

Note 1: The DS26503 does not have an internal source for CAS signaling and multiframe alignment generation. CAS signaling, and the multiframe alignment word, must be embedded in the transmit data (in the TS16 position) present on the TSER pin and frame aligned to sync signal on the TS pin.

Note 2: In addition to setting the TMODE bits to 6312kHz Synchronization Interface mode, the Transmit PLL must also be configured to transmit a 6312kHz signal through the Transmit PLL Control Register (TPCR.6 and TPCR.7)

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Register Name:


Register Address:

Bit

TPCR

Transmit PLL Control Register

09h

HW

Mode

TCSS0

PIN 63

For more information on all the bits in the Transmit PLL control register, refer to

Figure 3-3 .

Bits 0 and 1: Transmit Clock (TX CLOCK) Source Select (TCSS[1:0]). These bits control the output of the TX PLL

Clock Mux function. See Figure 3-3 .

TCSS1 TCSS0

Transmit Clock (TX CLOCK) Source

(See Figure 3-3 )

0

0

0

1

The TCLK pin is the source of transmit clock.

The PLL_CLK is the source of transmit clock.

1

1

0

1

The scaled signal present at MCLK as the transmit clock.

The signal present at RCLK is the transmit clock.

Bit 2: Transmit PLL_CLK Source Select (TPLLSS). Selects the reference signal for the TX PLL.

0 = Use the recovered network clock. This is the same clock available at the RCLK pin (output).

1 = Use the externally provided clock present at the TCLK pin.

Bit 3 and 4: Transmit PLL Input Frequency Select (TPLLIFS[0:1]). These bits are used to indicate the reference frequency being input to the TX PLL.

TPLLIFS1 TPLLIFS0

0 0 1.544MHz

0 1 2.048MHz

1 0

1 1

—

6312kHz

Bit 5: PLL_OUT Select (PLLOS). This bit selects the source for the PLL_OUT pin. See

Figure 3-3 .

0 = PLL_OUT is sourced directly from the TX PLL.

1 = PLL_OUT is the output of the TX PLL mux.

Bits 6 and 7: Transmit PLL Output Frequency Select (TPLLOFS[0:1]). These bits are used to select the TX PLL output frequency.

TPLLOFS1 TPLLOFS0 Output

0 0 1.544MHz

0 1 2.048MHz

1 0 —

1 1 6312kHz

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7.4 Interrupt Handling

Various alarms, conditions, and events in the DS26503 can cause interrupts. For simplicity, these are all referred to as events in this explanation. All STATUS registers can be programmed to produce interrupts.

Each status register has an associated interrupt mask register. For example, SR1 (Status Register 1) has an interrupt control register called IMR1 (Interrupt Mask Register 1). Status registers are the only sources of interrupts in the DS26503. On power-up, all writeable registers are automatically cleared. Since bits in the IMRx registers have to be set = 1 to allow a particular event to cause an interrupt, no interrupts can occur until the host selects which events are to product interrupts. Since there are potentially many sources of interrupts on the DS26503, several features are available to help sort out and identify which event is causing an interrupt. When an interrupt occurs, the host should first read the IIR register

(interrupt information register) to identify which status register(s) is producing the interrupt. Once that is determined, the individual status register or registers can be examined to determine the exact source.

Once an interrupt has occurred, the interrupt handler routine should clear the IMRx registers to stop further activity on the interrupt pin. After all interrupts have been determined and processed, the interrupt hander routine should restore the state of the IMRx registers.

7.5 Status Registers

When a particular event or condition has occurred (or is still occurring in the case of conditions), the appropriate bit in a status register will be set to a one. All the status registers operate in a latched fashion, which means that if an event or condition occurs a bit is set to a one. It will remain set until the user reads that bit. An event bit will be cleared when it is read and it will not be set again until the event has occurred again. Condition bits such as RLOS, etc., will remain set if the alarm is still present.

The user will always precede a read of any of the status registers with a write. The byte written to the register will inform the DS26503 which bits the user wishes to read and have cleared. The user will write a byte to one of these registers, with a one in the bit positions he or she wishes to read and a zero in the bit positions he or she does not wish to obtain the latest information on. When a one is written to a bit location, the read register will be updated with the latest information. When a zero is written to a bit position, the read register will not be updated and the previous value will be held. A write to the status registers will be immediately followed by a read of the same register. This write-read scheme allows an external microcontroller or microprocessor to individually poll certain bits without disturbing the other bits in the register. This operation is key in controlling the DS26503 with higher-order languages.

Status register bits are divided into two groups: condition bits and event bits. Condition bits are typically network conditions such as loss of frame, or all-ones detect. Event bits are typically markers such as the one-second timer. Each status register bit is labeled as a condition or event bit. Some of the status registers have bits for both the detection of a condition and the clearance of the condition. For example,

SR2 has a bit that is set when the device goes into a loss of frame state (SR2.0, a condition bit) and a bit that is set (SR2.4, an event bit) when the loss of frame condition clears (goes in sync). Some of the status register bits (condition bits) do not have a separate bit for the “condition clear” event but rather the status bit can produce interrupts on both edges, setting, and clearing. These bits are marked as “double interrupt bits.” An interrupt will be produced when the condition occurs and when it clears.

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7.6 Information Registers

Information registers operate the same as status registers except they cannot cause interrupts. INFO3 register is a read-only register and it reports the status of the E1 synchronizer in real time. INFO3 information bits are not latched, and it is not necessary to precede a read of these bits with a write.

7.7 Interrupt Information Registers

The Interrupt Information Registers provide an indication of which Status Registers (SR1 through SR4) are generating an interrupt. When an interrupt occurs, the host can read IIR to quickly identify which of the three status registers are causing the interrupt.

Register Name:


Register Address:

IIR

Interrupt Information Register

13h

HW

Mode

X X X X X X X X

Bit 0: Status Register 1 (SR1)

0 = Status Register 1 interrupt not active.

1 = Status Register 1 interrupt active.










Bits 4 to 7: Unused

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8. T1 FRAMER/FORMATTER CONTROL REGISTERS

The T1 framer portion of the DS26503 is configured via a set of five control registers. Typically, the control registers are only accessed when the system is first powered up. Once the DS26503 has been initialized, the control registers will only need to be accessed when there is a change in the system configuration. There are two receive control registers (T1RCR1 and T1RCR2), two transmit control registers (T1TCR1 and T1TCR2), and a common control register (T1CCR). Each of these registers is described in this section.

8.1 T1 Control Registers

Register Name:


Register Address:

T1RCR1

T1 Receive Control Register 1

03h

Default 0 0 0 0 0 0 0 0

HW

Mode

0 0 0 0 0 0 0 0

Bit 0: Resynchronize (RESYNC). When toggled from low to high, a resynchronization of the receive side framer is initiated.

Must be cleared and set again for a subsequent resync.

Bit 1: Sync Enable (SYNCE)

0 = auto resync enabled

1 = auto resync disabled

Bit 2: Sync Time (SYNCT)

0 = qualify 10 bits

1 = qualify 24 bits

Bit 3: Sync Criteria (SYNCC)

In D4 Framing Mode:

0 = search for Ft pattern, then search for Fs pattern

1 = cross couple Ft and Fs pattern

In ESF Framing Mode:

0 = search for FPS pattern only

1 = search for FPS and verify with CRC6

Bits 4 and 5: Out Of Frame Select Bits (OOF2, OOF1)

OOF2

0

0

OOF1

0

1

Out Of Frame Criteria

2/4 frame bits in error


1

1

0

1



Bit 6: Auto Resync Criteria (ARC)

0 = resync on OOF or RLOS event

1 = resync on OOF only

Bit 7: Unused, must be set = 0 for proper operation.

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Register Name:


Register Address:

T1RCR2

T1 Receive Control Register 2

04h

# 7 6 5 4 3 2 1 0

HW

Mode

0 0 0 0 0

Bit 0: Receive Side D4 Yellow Alarm Select (RD4YM)

0 = zeros in bit 2 of all channels

1 = a one in the S-bit position of frame 12 (J1 Yellow Alarm Mode)

Bit 1: Receive Japanese CRC6 Enable (RJC)

0 = use ANSI/AT&T/ITU CRC6 calculation (normal operation)

1 = use Japanese standard JT–G704 CRC6 calculation


Bit 5: Receive B8ZS Enable (RB8ZS)

0 = B8ZS disabled

1 = B8ZS enabled

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Register Name:


Register Address:

T1TCR1

T1 Transmit Control Register 1

05h

# 7 6 5 4 3 2 1 0

Default 0 0 0 0 0 0 0 0

HW

Mode

RMODEx

PINS

0 0 0 0 0 0 0

Bit 0: Transmit Yellow Alarm (TYEL)

0 = do not transmit yellow alarm

1 = transmit yellow alarm

Bits 1 to 4: Unused, must be set = 0 for proper operation.

Bit 5: Transmit CRC Pass-Through (TCPT)

0 = source CRC6 bits internally

1 = CRC6 bits sampled at TSER during F-bit time

Bit 6: Transmit F-Bit Pass-Through (TFPT)

0 = F bits sourced internally

1 = F bits sampled at TSER

Bit 7: Transmit Japanese CRC6 Enable (TJC)

0 = use ANSI/AT&T/ITU CRC6 calculation (normal operation)

1 = use Japanese standard JT–G704 CRC6 calculation

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Register Name:


Register Address:

T1TCR2

T1 Transmit Control Register 2

06h

# 7 6 5 4 3 2 1 0

HW

Mode

HBE

PIN 55

1 0 0 0 0 0 0

Bit 0: Transmit-Side Bit 7 Zero-Suppression Enable (TB7ZS)

0 = no stuffing occurs

1 = bit 7 forced to a 1 in channels with all 0s

Bits 1 and 5: Unused, must be set = 0 for proper operation.

Bit 2: Transmit-Side D4 Yellow Alarm Select (TD4YM)

0 = 0s in bit 2 of all channels

1 = a 1 in the S-bit position of frame 12

Bit 3: F-Bit Corruption Type 1 (FBCT1). A low-to-high transition of this bit causes the next three consecutive Ft (D4 framing mode) or FPS (ESF framing mode) bits to be corrupted causing the remote end to experience a loss of frame (loss of synchronization).

Bit 4: F-Bit Corruption Type 2 (FBCT2). Setting this bit high enables the corruption of one Ft (D4 framing mode) or FPS

(ESF framing mode) bit in every 128 Ft or FPS bits as long as the bit remains set.

Bit 6: Transmit Fs-Bit Insertion Enable (TFSE). Only set this bit to a 1 in D4 framing applications. Must be set to 1 to source the Fs pattern from the TFDL register. In all other modes this bit must be set = 0.

0 = Fs-bit insertion disabled

1 = Fs-bit insertion enabled

Bit 7: Transmit B8ZS Enable (TB8ZS)

0 = B8ZS disabled

1 = B8ZS enabled

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6

T1CCR

T1 Common Control Register

07h

5 4


Register Name:


Register Address:

Bit # 7 3 2 1 0

Default 0 0 0 0 0 0 0 0

HW

Mode

0 0 0 0 0 0 0 0


Bit 1: Pulse-Density Enforcer Enable (PDE). The framer always examines the transmit and receive data streams for violations of these, which are required by ANSI T1.403: No more than 15 consecutive zeros and at least N ones in each and every time window of 8 x (N + 1) bits, where N = 1 through 23. When this bit is set to one, the DS26503 forces the transmitted stream to meet this requirement no matter the content of the transmitted stream. When running B8ZS, this bit should be set to zero, as B8ZS encoded data streams cannot violate the pulse-density requirements.

0 = disable transmit pulse-density enforcer

1 = enable transmit pulse-density enforcer

Bit 3: Transmit AIS-CI Enable (TAIS-CI). Setting this bit causes the AIS-CI code to be transmitted from the framer to the

LIU, as defined in ANSI T1.403.

0 = do not transmit the AIS-CI code

1 = transmit the AIS-CI code

Bit 4: Transmit RAI-CI Enable (TRAI-CI). Setting this bit causes the ESF RAI-CI code to be transmitted in the FDL bit position.

0 = do not transmit the ESF RAI-CI code

1 = transmit the ESF RAI-CI code

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Table 8-1. T1 Alarm Criteria

ALARM SET CRITERIA CLEAR CRITERIA

Blue Alarm (AIS) (Note 1)

Yellow Alarm (RAI)

D4 Bit-2 Mode (T1RCR2.0 = 0)

D4 12th F-bit Mode (T1RCR2.0

= 1; this mode is also referred to as the “Japanese Yellow Alarm”)

ESF Mode

Over a 3ms window, five or fewer zeros are received

Bit 2 of 256 consecutive channels is set to zero for at least 254 occurrences

12th framing bit is set to one for two consecutive occurrences

16 consecutive patterns of

00FF appear in the FDL

Over a 3ms window, six or more zeros are received

Bit 2 of 256 consecutive channels is set to zero for less than 254 occurrences

12th framing bit is set to zero for two consecutive occurrences

14 or fewer patterns of 00FF hex out of

16 possible appear in the FDL

Red Alarm (RLOS) (Also referred to as Loss Of Signal)

192 consecutive zeros are received

14 or more ones out of 112 possible bit positions are received, starting with the first one received

Note: The definition of Blue Alarm (or Alarm Indication Signal) is an unframed, all-ones signal. Blue Alarm detectors should be able to operate properly in the presence of a 10E-3 error rate, and they should not falsely trigger on a framed, all-ones signal. The Blue Alarm criteria in the DS26503 has been set to achieve this performance.

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9. E1 FRAMER/FORMATTER CONTROL REGISTERS

The E1 framer portion of the DS26503 is configured via a set of two control registers. Typically, the control registers are only accessed when the system is first powered up. Once the DS26503 has been initialized, the control registers will only need to be accessed when there is a change in the system configuration. There is one receive control register (E1RCR) and one transmit control register (E1TCR).

There are also two information registers and a status register, as well as an interrupt mask register. Each of these registers is described in this section.

9.1 E1 Control Registers

Register Name: E1RCR


Register Address:

E1 Receive Control Register

1Dh

# 7 6 5 4 3 2 1 0

HW

Mode

0 0 0 0 0

Bit 0: Resync (RESYNC). When toggled from low to high, a resync is initiated. Must be cleared and set again for a subsequent resync.

Bit 1: Sync Enable (SYNCE)

0 = auto resync enabled

1 = auto resync disabled

Bit 2: Frame Resync Criteria (FRC)

0 = resync if FAS received in error three consecutive times

1 = resync if FAS or bit 2 of non-FAS is received in error three consecutive times

Bits 3, 4, 7: Unused, must be set = 0 for proper operation.

Bit 5: Receive HDB3 Enable (RHDB3)

0 = HDB3 disabled

1 = HDB3 enabled

Bit 6: Receive Loss Of Signal (RLOS) Alternate Criteria (RLOSA). Defines the criteria for a Receive Loss Of Signal condition.

0 = RLOS declared upon 255 consecutive zeros (125µs)

1 = RLOS declared upon 2048 consecutive zeros (1ms)

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Table 9-1. E1 Sync/Resync Criteria

FRAME OR

MULTIFRAME

LEVEL

SYNC CRITERIA RESYNC CRITERIA ITU SPEC.

FAS

CRC4

CAS

FAS present in frame N and

N + 2, and FAS not present in frame N + 1

Two valid MF alignment words found within 8ms

Valid MF alignment word found and previous time slot

16 contains code other than all zeros

Three consecutive incorrect FAS received

Alternate: (E1RCR.2 = 1) The above criteria is met or three consecutive incorrect bit 2 of non-FAS received

915 or more CRC4 code words out of

1000 received in error

Two consecutive MF alignment words received in error

G.706

4.1.1

4.1.2

G.706

4.2 and 4.3.2

G.732 5.2

Register Name:


Register Address:

E1TCR

E1 Transmit Control Register

1Eh

# 7 6 5 4 3 2 1 0

HW

Mode


Bit 1: Transmit HDB3 Enable (THDB3)

0 = HDB3 disabled

1 = HDB3 enabled

Bit 4: Transmit International Bit Select (TSiS)

0 = sample Si bits at TSER pin

1 = source Si bits from TAF and TNAF registers (in this mode, E1TCR1.7 must be set to 0)

Bit 7: Transmit Time Slot 0 Pass-Through (TFPT)

0 = FAS bits/Sa bits/remote alarm sourced internally from the TAF and TNAF registers

1 = FAS bits/Sa bits/remote alarm sourced from TSER

0

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9.2 E1 Information Registers

Register Name:


Register Address:

INFO2

Information Register 2

12h

HW

Mode

X X X X X X X X

Bit 0: CAS Resync Criteria Met Event (CASRC). Set when two consecutive CAS MF alignment words are received in error.

Bit 1: FAS Resync Criteria Met Event (FASRC. Set when three consecutive FAS words are received in error.

Bit 2: CRC Resync Criteria Met Event (CRCRC). Set when 915/1000 codewords are received in error.


Register Name:


Register Address:

INFO3

Information Register 3 (Real Time)

1Ch

HW

Mode

X X X X X X X X

Bit 0: CRC4 MF Sync Active (CRC4SA). Set while the synchronizer is searching for the CRC4 MF alignment word.

Bit 1: CAS MF Sync Active (CASSA). Set while the synchronizer is searching for the CAS MF alignment word.

Bit 2: FAS Sync Active (FASSA). Set while the synchronizer is searching for alignment at the FAS level.

Bits 3 to 7: CRC4 Sync Counter Bits (CSC0 and CSC2 to CSC5). The CRC4 sync counter increments each time the 8ms-

CRC4 multiframe search times out. The counter is cleared when the framer has successfully obtained synchronization at the

CRC4 level. The counter can also be cleared by disabling CRC4 mode. This counter is useful for determining the amount of

time the framer has been searching for synchronization at the CRC4 level. ITU G.706 suggests that if synchronization at the

CRC4 level cannot be obtained within 400ms, then the search should be abandoned and proper action taken. The CRC4 sync counter will rollover. CSC0 is the LSB of the 6-bit counter. (Note: The second LSB, CSC1, is not accessible. CSC1 is omitted to allow resolution to >400ms using 5 bits.)

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Table 9-2. E1 Alarm Criteria

ALARM SET CRITERIA

RLOF An RLOF condition exists on power-up prior to initial synchronization, when a resync criteria has been met, or when a manual resync has been initiated via

E1RCR.0

RLOS

RRA

255 or 2048 consecutive zeros received as determined by E1RCR.0

Bit 3 of non-align frame set to one for three consecutive occasions

RUA1 Fewer than three zeros in two frames (512 bits)

RDMA Bit 6 of time slot 16 in frame 0 has been set for two consecutive multiframes

CLEAR CRITERIA

In 255-bit times, at least 32 ones are received

Bit 3 of non-align frame set to zero for three consecutive occasions

More than two zeros in two frames (512 bits)

ITU

SPEC.

G.775/G.962

O.162

2.1.4

O.162

1.6.1.2

V52LNK Two out of three Sa7 bits are zero G.965

Register Name:


Register Address:

IDR

Device Identification Register

10h

# 7 6 5 4 3 2 1 0

Name ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0

HW

Mode

X X X X X X X X

Bits 0 to 3:Chip Revision Bits (ID0 to ID3). The lower four bits of the IDR are used to display the die revision of the chip.

ID0 is the LSB of a decimal code that represents the chip revision.

Bits 4 to 7: Device ID (ID4 to ID7). The upper four bits of the IDR are used to display the DS26503 ID. The DS26503 ID is

0001.

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Register Name:


Register Address:

SR2

Status Register 2

16h

# 7 6 5 4 3 2 1 0

HW

Mode

RLOS

PIN 32

LOF

PIN 30

Bit 0: Receive Loss of Frame Condition (RLOF). Set when the DS26503 is not synchronized to the received data stream.

Bit 1: Receive Loss Of Signal Condition (RLOS). Set when 255 (or 2048 if E1RCR.6 = 1) E1 mode or 192 T1 mode consecutive zeros have been detected. In 6312kHz Synchronization Interface Mode, this bit will be set when the signal received is out of range as defined by the G.703 Appendix II specification.

Bit 2: Receive Alarm Indication Signal (T1= Blue Alarm, E1= AIS) Condition (RAIS). Set when an unframed all-ones code is received.

Bit 3: Receive Yellow Alarm Condition (RYEL). (T1 only) Set when a yellow alarm is received.

Bit 4: Receive Loss of Frame Clear Event (RLOFC). Set when the framer achieves synchronization; will remain set until read.

Bit 5: Receive Loss Of Signal Clear Event (RLOSC). Set when loss of signal condition is no longer detected.

Bit 6: Receive Alarm Indication Signal Clear Event (RAISC). Set when the unframed all-ones condition is no longer detected.

Bit 7: Receive Yellow Alarm Clear Event (RYELC). (T1 only) Set when the yellow alarm condition is no longer detected .

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Register Name:


Register Address:

IMR2

Interrupt Mask Register 2

17h

# 7 6 5 4 3 2 1 0

HW

Mode

X X X X X X X X

Bit 0: Receive Loss of Frame Condition (RLOF)

0 = interrupt masked

1 = interrupt enabled–interrupts on rising edge only

Bit 1: Receive Loss Of Signal Condition (RLOS)



Bit 2: Receive Alarm Indication Signal Condition (RAIS)



Bit 3: Receive Yellow Alarm Condition (RYEL)



Bit 4: Receive Loss of Frame Clear Event (RLOFC)


1 = interrupt enabled

Bit 5: Receive Loss Of Signal Condition Clear (RLOSC)



Bit 6: Receive Alarm Indication Signal Clear Event (RAISC)



Bit 7: Receive Yellow Alarm Clear Event (RYELC)



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10. I/O PIN CONFIGURATION OPTIONS

Register Name:


Register Address:

IOCR1

I/O Configuration Register 1

01h

# 7 6 5 4 3 2 1 0

HW

Mode

Bit 0: Output Data Format (ODF)

0 = bipolar data at TPOS and TNEG

0 0

1 = NRZ data at TPOS; TNEG = 0

Bit 1: TS I/O Select (TSIO). This bit determines whether the TS pin is an input or and output. See

Table 10-1 .

0 = TS is an input

1 = TS is an output

Bit 2: TS Mode Select (TSM). In T1 or E1 operation, selects frame or multiframe mode for the TS pin. In 6312kHz mode,

this bit should be set = 0. See Table 10-1 .

0 = frame mode

1 = multiframe mode

Bit 3: Transmit Signaling Double-Wide Sync (TSDW). In T1 mode, setting this bit = 1 and setting TSIO = 1 will cause the sync-pulse output on TS to be two clocks wide during signaling frames. In E1 or 6312kHz mode, this bit should be set = 0. See

Table 10-1 .

0 = (T1) normal sync pulses

1 = (T1) double-wide sync pulses during signaling frames

Bit 4: RLOF Output Function (RLOFF). In T1 or E1 receive mode this bit determines the function of the RLOF pin. In

6312kHz receive mode, this bit should be set = 0.

0 = receive loss of frame (RLOF)

1 = loss-of-transmit clock (LOTC)

Bit 5: RS Mode Select 1(RSMS1). In T1 or E1 receive mode, this bit selects a frame or multiframe output pulse at RS pin.

IOCR.6 may be used to select other function for the RS pin.

0 = frame mode

1 = multiframe mode

Bit 6: RS Mode Select 2 (RSMS2). In T1 and E1 receive mode, this bit along with IOCR.5 selects the function of the RS pin.

T1 Mode: (when IOCR.5 set = 0)

0 = do not pulse double-wide in signaling frames

1 = do pulse double-wide in signaling frames

E1 Mode: (when IOCR.5 set = 1)

0 = RS outputs CAS multiframe boundaries

1 = RS outputs CRC4 multiframe boundaries

Bit 7: Unused, must be set = 0 for proper operation .

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Table 10-1. TS Pin Functions

TRANSMIT

MODE

IOCR.3 IOCR.2 IOCR.1

TS

FUNCTION

T1/E1 0 0 0

T1/E1 0 0 1 output

T1/E1 0 1 0 Multiframe sync input

Multiframe sync output T1/E1 0 1 1

Table 10-2. RLOF Pin Functions

RECEIVE

MODE

T1/E1

T1/E1

0

1

Indicate loss of frame

Indicates loss of transmit clock

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Register Name:


Register Address:

IOCR2

I/O Configuration Register 2

02h

# 7 6 5 4 3 2 1 0

Name

RCLKINV TCLKINV RSINV TSINV — — — —

HW

Mode

0 0 0 0 0 0 0 0

Bits 0 to 3: Unused, must be set = 0 for proper operation.

Bit 4: TS Invert (TSINV)

0 = no inversion

1 = invert

Bit 5: RS Invert (RSINV)

0 = no inversion

1 = invert

Bit 6: TCLK Invert (TCLKINV)

0 = no inversion

1 = invert

Bit 7: RCLK Invert (RCLKINV)

0 = no inversion

1 = invert

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11. T1 SYNCHRONIZATION STATUS MESSAGE

The DS26503 has a BOC controller to handle SSM services in T1 mode.

Table 11-1. T1 SSM Messages

QUALITY

LEVEL

1

3

4

5

6

7

Stratum 1 Traceable

Stratum 2 Traceable

Stratum 3 Traceable

SONET Minimum Clock Traceable

Stratum 4 Traceable

Do Not Use For Synchronization

0000010011111111

0000100011111111

0000110011111111

0001000011111111

0010001011111111

0010100011111111

0011000011111111

User Assignable Reserved For Network Synchronization Use 0100000011111111

11.1 T1 Bit-Oriented Code (BOC) Controller

The DS26503 contains a BOC generator on the transmit side and a BOC detector on the receive side. The

BOC function is available only in T1 mode. In typical BITS applications, the BOC controller would be used to transmit and receive Synchronization Status Messages in T1 mode over the data link.

11.2 Transmit BOC

Bits 0 through 5 in the TFDL register contain the BOC or synchronization status message to be transmitted. Setting BOCC.0 = 1 causes the transmit BOC controller to immediately begin inserting the

BOC sequence into the FDL bit position. The transmit BOC controller automatically provides the abort sequence. BOC messages will be transmitted as long as BOCC.0 is set. TFSE (T1TCR2.6) must be set =

0 when using the transmit BOC function.

To transmit a BOC, use the following:

1) Write 6-bit code into the TFDL register.

2) Set SBOC bit in BOCC register = 1.

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11.3 Receive BOC

The receive BOC function is enabled by setting BOCC.4 = 1. The RFDL register will now operate as the receive BOC message and information register. The lower six bits of the RFDL register (BOC message bits) are preset to all ones. When the BOC bits change state, the BOC change of state indicator, SR3.0 will alert the host. The host will then read the RFDL register to get the BOC message. A change of state will occur when either a new BOC code has been present for time determined by the receive BOC filter bits, RBF0 and RBF1, in the BOCC register.

To receive a BOC, use the following:

1) Set integration time via BOCC.1 and BOCC.2.

2) Enable the receive BOC function (BOCC.4 = 1).

3) Enable interrupt (IMR3.0 = 1).

4) Wait for interrupt to occur.

5) Read the RFDL register.

6) The lower six bits of the RFDL register is the message.

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Register Name:


Register Address:

BOCC

BOC Control Register

1Fh

# 7 6 5 4 3 2 1 0

HW

Mode

0 0 0 0 0 0 0 0

Bit 0: Send BOC (SBOC). Set = 1 to transmit the BOC code placed in bits 0 to 5 of the TFDL register.

Bits 1 and 2: Receive BOC Filter Bits (RBF0, RBF1). The BOC filter sets the number of consecutive patterns that must be received without error prior to an indication of a valid message.

RBF1 RBF0

CONSECUTIVE BOC CODES FOR VALID

SEQUENCE IDENTIFICATION

0 0

0 1

None

3

1 0

1 1

5

7

Bit 3: Receive BOC Reset (RBR). A 0-to-1 transition will reset the BOC circuitry. Must be cleared and set again for a subsequent reset.

Bit 4: Receive BOC Enable (RBOCE). Enables the receive BOC function. The RFDL register will report the received BOC code.

0 = receive BOC function disabled

1 = receive BOC function enabled. The RFDL register will report BOC messages


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Register Name: RFDL (RFDL register bit usage when BOCC.4 = 1)


Register Address:

Receive FDL Register

50h

# 7 6 5 4 3 2 1 0

Name — — RBOC5 RBOC4 RBOC3 RBOC2 RBOC1 RBOC0

HW

Mode

0 0 0 0 0 0 0 0

Bit 0: BOC Bit 0 (RBOC0)


Bit 2: BOC Bit 2 (RBOC2)




Bits 6 and 7: This bit position is unused when BOCC.4 = 1.

Register Name:


Register Address:

RFDLM1, RFDLM2

Receive FDL Match Register 1

Receive FDL Match Register 2

52h, 53h

Name RFDLM7 RFDLM6 RFDLM5 RFDLM4 RFDLM3 RFDLM2 RFDLM1 RFDLM0

HW

Mode

0 0 0 0 0 0 0 0

Bit 0: Receive FDL Match Bit 0 (RFDLM0). LSB of the FDL Match Code.

Bit 1: Receive FDL Match Bit 1 (RFDLM1)






Bit 7: Receive FDL Match Bit 7 (RFDLM7). MSB of the FDL Match Code.

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Register Name:


Register Address:

SR3


18h

# 7 6 5 4 3 2 1 0

HW

Mode

X X X X X X X X

Bit 0: Receive BOC Detector Change-of-State Event (RBOC). Set whenever the BOC detector sees a change of state to a valid BOC. The setting of this bit prompts the user to read the RFDL register.

Bit 1: Receive FDL Match Event (RMTCH). Set whenever the contents of the RFDL register matches RFDLM1 or

RFDLM2.

Bit 2: TFDL Register Empty Event (TFDLE). Set when the transmit FDL buffer (TFDL) empties.

Bit 3: RFDL Register Full Event (RFDLF). Set when the receive FDL buffer (RFDL) fills to capacity.

Bit 4: RFDL Abort Detect Event (RFDLAD). Set when eight consecutive ones are received on the FDL.

Bit 5: BOC Clear Event (BOCC). Set when 30 FDL bits occur without an abort sequence.

Bit 6: Loss Of Transmit Clock Event (LOTC). Set when the signal at the TCLK pin has not transitioned for approximately

15 periods of the scaled MCLK.

Bit 7: Receive AIS-CI Event (RAIS-CI) (T1 Only). Set when the receiver detects the AIS-CI pattern as defined in ANSI

T1.403.

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Register Name:


Register Address:

IMR3


19h

HW

Mode

X X X X X X X X

Bit 0: Receive BOC Detector Change-of-State Event (RBOC)



Bit 1: Receive FDL Match Event (RMTCH)



Bit 2: TFDL Register Empty Event (TFDLE)



Bit 3: RFDL Register Full Event (RFDLF)



Bit 4: RFDL Abort Detect Event (RFDLAD)



Bit 5: BOC Clear Event (BOCC)



Bit 6: Loss Of Transmit Clock Event (LOTC)



Bit 7: Receive AIS-CI Event (RAIS-CI)



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Register Name:


Register Address:

SR4


1Ah

# 7 6 5 4 3 2 1 0

HW

Mode

X X X X X X X X

Bit 0: Receive Align Frame Event (RAF). (E1 only) Set every 250µs at the beginning of align frames. Used to alert the host that Si and Sa bits are available in the RAF and RNAF registers.

Bit 1: Receive CRC4 Multiframe Event (RCMF). (E1 only) Set on CRC4 multiframe boundaries; will continue to be set every 2ms on an arbitrary boundary if CRC4 is disabled.

Bit 2: Receive Multiframe Event (RMF)

E1 Mode: Set every 2ms (regardless if CAS signaling is enabled or not) on receive multiframe boundaries. Used to alert the host that signaling data is available.

T1 Mode: Set every 1.5ms on D4 MF boundaries or every 3ms on ESF MF boundaries.

Bit 3: Transmit Align Frame Event (TAF). (E1 only) Set every 250µs at the beginning of align frames. Used to alert the host that the TAF and TNAF registers need to be updated.

Bit 4: Transmit Multiframe Event (TMF)

E1 Mode: Set every 2ms (regardless if CRC4 is enabled) on transmit multiframe boundaries. Used to alert the host that signaling data needs to be updated.

T1 Mode: Set every 1.5ms on D4 MF boundaries or every 3ms on ESF MF boundaries.

Bit 5: Receive Signaling All Zeros Event (RSA0). (E1 only) Set when over a full MF, time slot 16 contains all zeros.

Bit 6: Receive Signaling All Ones Event (RSA1). (E1 only) Set when the contents of time slot 16 contains fewer than three zeros over 16 consecutive frames. This alarm is not disabled in the CCS signaling mode.

Bit 7: Unused

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Register Name:


Register Address:

IMR4


1Bh

# 7 6 5 4 3 2 1 0

HW

Mode

X X X X X X X X

Bit 0: Receive Align Frame Event (RAF)



Bit 1: Receive CRC4 Multiframe Event (RCMF)



Bit 2: Receive Multiframe Event (RMF)



Bit 3: Transmit Align Frame Event (TAF)



Bit 4: Transmit Multiframe Event (TMF)



Bit 5: Receive Signaling All Zeros Event (RSA0)



Bit 6: Receive Signaling All Ones Event (RSA1)




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Register Name:


Register Address:

TFDL

Transmit FDL Register

51h

# 7 6 5 4 3 2 1 0

Name TFDL7 TFDL6 TFDL5 TFDL4 TFDL3 TFDL2 TFDL1 TFDL0

HW

Mode

0 0 0 1 1 1 0 0

Note: Also used to insert Fs framing pattern in D4 framing mode.

The transmit FDL register (TFDL) contains the FDL information that is to be inserted on a byte-basis into the outgoing T1 data stream. The LSB is transmitted first.

Bit 0: Transmit FDL Bit 0 (TFDL0). LSB of the transmit FDL code.

Bit 1: Transmit FDL Bit 1 (TFDL1)






Bit 7: Transmit FDL Bit 7 (TFDL7). MSB of the transmit FDL code.

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12. E1 SYNCHRONIZATION STATUS MESSAGE

The DS26503 provides access to both the transmit and receive Sa/Si bits. In E1, the Sa bits are used to transmit and receive the SSM. The primary method to access the Sa (and Si) bits is based on CRC4 multiframe access. An alternate method is based on double-frame access.

Table 12-1. E1 SSM Messages

QUALITY

LEVEL

0

DESCRIPTION

Quality unknown (existing sync network)

1 Reserved

2 Rec. G.811 (Traceable to PRS)

3 Reserved

4 SSU-A (Traceable to SSU type A, see G.812)

5 Reserved

6 Reserved

7 Reserved

8 SSU-B (Traceable to SSU type B, see G.812)

9 Reserved

10 Reserved

11 Synchronous Equipment Timing Source

12 Reserved

13 Reserved

14 Reserved

Sa BIT

MESSAGE

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

15 Do not use for synchronization 01111

In E1 operation, SSMs are transmitted using one of the Sa bits—Sa4, Sa5, Sa6, Sa7, or Sa8. The SSM is transmitted MSB first in the first frame of the multiframe. Each multiframe will contain two SSMs, one in each sub-multiframe. An SSM is declared valid when the message in three sub-multiframes are alike.

12.1 Sa/Si Bit Access Based on CRC4 Multiframe

On the receive side, there is a set of eight registers (RSiAF, RSiNAF, RRA, RSa4 to RSa8) that report the

Si and Sa bits as they are received. These registers are updated on CRC4 multiframes. A bit in status register 4 (SR4.1) indicates the multiframe boundary. The host can use the SR4.1 bit to know when to read these registers. The user has 2ms to retrieve the data before it is lost. The MSB of each register is the first received. See the following register descriptions for more details.

On the transmit side, there is also a set of eight registers (TSiAF, TSiNAF, TRA, TSa4 to TSa8) that, via the transmit Sa bit control register (TSaCR), can be programmed to insert both Si and Sa data. Data is sampled from these registers with the setting of the transmit multiframe bit in status register 2 (SR4.4).

The host can use the SR4.4 bit to know when to update these registers. It has 2ms to update the data or else the old data will be retransmitted. The MSB of each register is the first bit transmitted. See the following register descriptions for details.

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Register Name:


Register Address:

RSiAF

Receive Si Bits of the Align Frame

58h

# 7 6 5 4 3 2 1 0

Name SiF0 SiF2 SiF4 SiF6 SiF8 SiF10 SiF12 SiF14

HW

Mode

X X X X X X X X

Bit 0: Si Bit of Frame 14(SiF14)








Register Name:


Register Address:

RSiNAF

Receive Si Bits of the Non-Align Frame

59h

Name SiF1 SiF3 SiF5 SiF7 SiF9 SiF11 SiF13 SiF15

HW

Mode

X X X X X X X X









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Register Name:


Register Address:

# 7

RRA

Receive Remote Alarm

5Ah

6 5 4 3 2 1 0

Name RRAF1 RRAF3 RRAF5 RRAF7 RRAF9 RRAF11 RRAF13 RRAF15

HW

Mode

X X X X X X X X

Bit 0: Remote Alarm Bit of Frame 15(RRAF15)








Register Name:


Register Address:

RSa4

Receive Sa4 Bits

5Bh

Name RSa4F1 RSa4F3 RSa4F5 RSa4F7 RSa4F9 RSa4F11 RSa4F13 RSa4F15

HW

Mode

X X X X X X X X

Bit 0: Sa4 Bit of Frame 15(RSa4F15)








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Register Name:


Register Address:

RSa5


5Ch

# 7 6 5 4 3 2 1 0


HW

Mode

X X X X X X X X









Register Name:


Register Address:

RSa6


5Dh


HW

Mode

X X X X X X X X









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Register Name:


Register Address:

RSa7


5Eh

# 7 6 5 4 3 2 1 0


HW

Mode

X X X X X X X X









Register Name:


Register Address:

RSa8


5Fh

# 7 6 5 4 3 2 1 0

Name RSa8F1 RSa8F3 RSa8F5 RSa8F7 RSa8F9 RSa8F11 RSa8F15

HW

Mode

X X X X X X X X

Bit 0/Sa8 Bit of Frame 15(RSa8F15)








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Register Name:


Register Address:

TSiAF

Transmit Si Bits of the Align Frame

42h

# 7 6 5 4 3 2 1 0

Name TsiF0 TsiF2 TsiF4 TsiF6 TsiF8 TsiF10 TsiF12 TsiF14

0 0 0 0 0 0 0 0

HW

Mode

0 0 0 0 0 0 0 0

Bit 0: Si Bit of Frame 14(TsiF14)








Register Name:


TSiNAF

Register Address:

Transmit Si Bits of the Non-Align Frame

43h

Bit 1 0

Name TsiF1 TsiF3 TsiF5 TsiF7 TsiF9 TsiF11 TsiF13 TSiF15

HW

Mode

0 0 0 0 0 0 0 0

Bit 0: Si Bit of Frame 15(TSiF15)








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Register Name:


Register Address:

Name

TRA

Transmit Remote Alarm

44h

# 7 6 5 4 3 2 1 0

TRAF1 TRAF3 TRAF5 TRAF7 TRAF9 TRAF11 TRAF13 TRAF15

HW

Mode

0 0 0 0 0 0 0 0

Bit 0: Remote Alarm Bit of Frame 15(TRAF15)








Register Name:


Register Address:

TSa4

Transmit Sa4 Bits

45h

Bit 1 0

Name TSa4F1 TSa4F3 TSa4F5 TSa4F7 TSa4F9 TSa4F11 TSa4F13 TSa4F15

HW

Mode

0 0 0 0 0 0 0 0

Bit 0: Sa4 Bit of Frame 15(TSa4F15)








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Register Name:


Register Address:

TSa5


46h

# 7 6 5 4 3 2 1 0


HW

Mode

0 0 0 0 0 0 0 0









Register Name:


TSa6

Register Address:


47h

Bit 4 3 2 1 0


HW

Mode

0 0 0 0 0 0 0 0









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Register Name:


Register Address:

TSa7


48h

# 7 6 5 4 3 2 1 0


HW

Mode

0 0 0 0 0 0 0 0









Register Name:


Register Address:

TSa8


49h


HW

Mode

0 0 0 0 0 0 0 0









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Register Name:


Register Address:

TSACR

Transmit Sa Bit Control Register

4Ah

# 7 6 5 4 3 2 1 0

SiNAF Sa7 Sa8

HW

Mode

0 0 0 0 0 0 0 0

Bit 0: Additional Bit 8 Insertion Control Bit (Sa8)

0 = do not insert data from the TSa8 register into the transmit data stream

1 = insert data from the TSa8 register into the transmit data stream













Bit 5: Remote Alarm Insertion Control Bit (RA)

0 = do not insert data from the TRA register into the transmit data stream

1 = insert data from the TRA register into the transmit data stream

Bit 6: International Bit in Non-Align Frame Insertion Control Bit (SiNAF)

0 = do not insert data from the TSiNAF register into the transmit data stream

1 = insert data from the TSiNAF register into the transmit data stream

Bit 7: International Bit in Align Frame Insertion Control Bit (SiAF)

0 = do not insert data from the TSiAF register into the transmit data stream

1 = insert data from the TSiAF register into the transmit data stream

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12.2 Alternate Sa/Si Bit Access Based on Double-Frame

On the receive side, the RAF and RNAF registers will always report the data as it received in the Sa and

Si bit locations. The RAF and RNAF registers are updated on align frame boundaries. The setting of the receive align frame bit in status register 4 (SR4.0) will indicate that the contents of the RAF and RNAF have been updated. The host can use the SR4.0 bit to know when to read the RAF and RNAF registers.

The host has 250 µs to retrieve the data before it is lost.

On the transmit side, data is sampled from the TAF and TNAF registers with the setting of the transmit align frame bit in status register 4 (SR4.3). The host can use the SR4.3 bit to know when to update the

TAF and TNAF registers. It has 250 µs to update the data or else the old data will be retransmitted. If the

TAF an TNAF registers are only being used to source the align frame and non-align frame-sync

patterns, then the host need only write once to these registers. Data for the Si bit can come from the Si bits of the RAF and TNAF registers, the TSiAF and TSiNAF registers, or passed through from the TSER pin.

Register Name:


Register Address:

RAF

Receive Align Frame Register

56h

Bit 3 2 1 0

Name Si FAS6 FAS5 FAS4 FAS3 FAS2 FAS1 FAS0

HW

Mode

X X X X X X X X

Bit 0: Frame Alignment Signal Bit 0 (FAS0). In normal operation this bit will be = 1.







Bit 7: International Bit (Si)

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Register Name:


Register Address:

Bit

RNAF

Receive Non-Align Frame Register

57h

5 4 3 2 1 0

Name Si 1 A Sa4 Sa5 Sa6 Sa7 Sa8

HW

Mode

X X X X X X X X

Bit 0: Additional Bit 8 (Sa8)





Bit 5: Remote Alarm (A)

Bit 6: Frame Nonalignment Signal Bit (1). In normal operation this bit will be = 1.


Register Name:


Register Address:

TAF

Transmit Align Frame Register

40h

# 7 6 5 4 3 2 1 0

HW

Mode

0 0 0 1 1 0 1 1

Bit 0: Frame Alignment Signal Bit (1)








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Register Name:


Register Address:

TNAF

Transmit Non-Align Frame Register

41h

# 7 6 5 4 3 2 1 0

Name Si 1 A Sa4 Sa5 Sa6 Sa7 Sa8






Bit 5: Remote Alarm (used to transmit the alarm A)

Bit 6: Frame Nonalignment Signal Bit (1)


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13. LINE INTERFACE UNIT (LIU)

The LIU in the DS26503 contains three sections: the receiver, which handles clock and data recovery; the transmitter, which waveshapes and drives the network line; and the jitter attenuator. These three sections are controlled by the line interface control registers (LIC1–LIC4), which are described below.

The DS26503 can switch between T1 or E1 networks without changing any external components on either the transmit or receive side.

Figure 13-1 shows a network connection using minimal components.

In this configuration the DS26503, using a fixed 120Ω external termination, can connect to T1, J1, E1, or

6312kHz without any component change. The receiver can adjust the 120Ω termination to 100Ω, 110Ω or

75Ω. The transmitter can adjust its output impedance to provide high return loss characteristics for 75Ω,

100Ω, 110Ω, and 120Ω lines. Other components may be added to this configuration to meet safety and network protection requirements. This is covered in the Recommended Circuits section.

Figure 13-1. Basic Network Connection

TTIP

TRANSMIT

LINE

10 µF

BACKPLANE

CONNECTIONS

2:1

TRING

DS26503

RTIP

RECEIVE

LINE

RRING

1:1

60 60

0.01

µF

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13.1 LIU Operation

The LIU interfaces the T1, E1, and 6312kHz signals to the various types of network media through coupling transformers. The LIU transmit and receive functions are independent. For example, the receiver can be in T1 mode while the transmitter is in E1 mode. The 6312kHz transmission is an exception to the other modes. For transmission, 6312kHz is only available as a 0 to 3.3V signal on the TCLKO pin. It is not output to the TTIP and TRING pins for coupling to twisted pair. Because the G.703 specifications of the transmit pulse shape for Japanese 6312kHz are unclear, the user can externally filter this signal to generate a sine wave type of signal. However, on the receive side, 6312kHz can be input through the receive transformer to the RTIP and RRING pins.

13.2 LIU Receiver

The analog AMI/HDB3 E1 waveform or AMI/B8ZS T1 waveform is transformer-coupled into the RTIP and RRING pins of the DS26503. The user has the option to use internal termination, software selectable for 75/100/110/120 Ω application, or external termination. The LIU recovers clock and data from the analog signal and passes it through the jitter attenuation mux. (Note: The jitter attenuator is only available in T1 or E1 mode.) The DS26503 contains an active filter that reconstructs the analog-received signal for the nonlinear losses that occur in long-haul T1 and E1 transmission. The receiver is configurable for various T1 and E1 monitor applications. The device has a usable receive sensitivity of 0dB to –43dB for

E1 and 0dB to –36dB for T1, which allows the device to operate on 0.63mm (22AWG) cables up to

2.5km (E1) and 6000ft (T1) in length.

The DS26503’s LIU is designed to be fully software selectable for E1 and T1 without the need to change any external resistors for the receive-side. The receiver will allow the user to configure the DS26503 for

75Ω, 100Ω, 110Ω, or 120Ω receive termination by setting the RT0(LIC4.0), RT1(LIC4.1), and

RT2(LIC4.2). When using the internal termination feature, the resistors labeled R in

Figure 13-4 should

be 60Ω each. If external termination is used, RT0, RT1, and RT2 should be set to zero and the resistors labeled R in

Figure 13-4 will need to be 37.5Ω, 50Ω, 55Ω, or 60Ω each, depending on the required

termination.

There are two ranges of receive sensitivity for T1 and E1, which is selectable by the user. The EGL bit of

LIC1 (LIC1.4) selects the full or limited sensitivity.

Normally, the clock that is output at the RCLK pin is the recovered clock from the waveform presented at the RTIP and RRING inputs. If the jitter attenuator is placed in the receive path (as is the case in most applications), the jitter attenuator restores the RCLK to an approximate 50% duty cycle. If the jitter attenuator is either placed in the transmit path or is disabled, the RCLK output can exhibit slightly shorter high cycles of the clock. This is due to the highly over-sampled digital clock recovery circuitry. See the

Receive AC Timing Characteristics section for more details. When no signal is present at RTIP and

RRING, a receive loss of signal (RLOS) condition will occur and the signal at RCLK will be derived from the scaled signal present on the MCLK pin.

13.2.1 Receive Level Indicator

The DS26503 will report the signal strength at RTIP and RRING in 2.5dB increments via RL3-RL0 located in the Information Register 1 (INFO1). This feature is helpful when trouble shooting line performance problems.

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13.2.2 Receive G.703 Section 10 Synchronization Signal

The DS26503 can receive a 2.048MHz square-wave synchronization clock as specified in Section 10 of

ITU G.703. To use the DS26503 in this mode, set the mode configuration bits in the Mode Configuration

Register (MCREG).

13.2.3 Monitor Mode

Monitor applications in both E1 and T1 require various flat gain settings for the receive-side circuitry.

The DS26503 can be programmed to support these applications via the monitor mode control bits MM1 and MM0 in the LIC3 register.

Figure 13-2. Typical Monitor Application

T1/E1 LINE

Rm Rm

13.3 LIU Transmitter

PRIMARY

T1/E1 TERMINATING

DEVICE

MONITOR

PORT JACK

X

F

M

R

Rt DS26503

SECONDARY T1/E1

TERMINATING

DEVICE

The DS26503 uses a phase-lock loop along with a precision digital-to-analog converter (DAC) to create the waveforms that are transmitted onto the E1 or T1 line. The waveforms created by the DS26503 meet the latest ETSI, ITU, ANSI, and AT&T specifications. The waveform that is to be generated is set by the transmit mode bits (TMODE[3:0]) in the MCREG register, as well as the L2/L1/L0 bits in register LIC1 if applicable.

ITU specification G.703 requires an accuracy of ±50ppm for both T1 and E1. TR62411 and ANSI specs require an accuracy of ±32ppm for T1 interfaces. The transmit clock can be sourced from the recovered clock (RCLK), the pre-scaled MCLK, the TCLK pin or the TX PLL. See the TX PLL clock mux diagram in

Figure 3-3 . Due to the nature of the design of the transmitter in the DS26503, very little jitter (less than

0.005 UI

P-P

broadband from 10Hz to 100kHz) is added to the jitter present on the selected transmit clock source. Also, the waveforms created are independent of the duty cycle of TCLK. The transmitter in the

DS26503 couples to the transmit twisted pair (or coaxial cable in some applications) via a 1:2 step-up transformer. For the device to create the proper waveforms, the transformer used must meet the

specifications listed in Table 13-1 . The DS26503 has the option of using software-selectable transmit

termination.

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The transmit line drive has two modes of operation: fixed gain or automatic gain. In the fixed gain mode, the transmitter outputs a fixed current into the network load to achieve a nominal pulse amplitude. In the automatic gain mode, the transmitter adjusts its output level to compensate for slight variances in the network load. See the Transmit Line Build-Out Control (TLBC) register for details.

13.3.1 Transmit Short-Circuit Detector/Limiter

The DS26503 has an automatic short-circuit limiter that limits the source current to approximately 50mA

(rms) on the network side of the transformer in E1 modes of operations and 70mA (rms) on the network side of the transformer in T1 modes of operation. These values are approximate and are not guaranteed by production testing. This feature can be disabled by setting the SCLD bit (LIC2.1) = 1. TCLE (SR1.2) provides a real-time indication of when the current limiter is activated. If the current limiter is disabled,

TCLE will indicate that a short-circuit condition exist. Status Register SR1.2 provides a latched version of the information, which can be used to activate an interrupt when enable via the IMR1 register. When set low, the TPD bit (LIC1.0) will power-down the transmit line driver and tri-state the TTIP and TRING pins.

13.3.2 Transmit Open-Circuit Detector

The DS26503 can also detect when the TTIP or TRING outputs are open circuited. TOCD (SR1.1) will provide a real-time indication of when an open circuit is detected. SR1 provides a latched version of the information (SR1.1), which can be used to activate an interrupt when enable via the IMR1 register. The functionality of these bits is not guaranteed by production testing.

13.3.3 Transmit BPV Error Insertion

When IBPV (LIC2.5) is transitioned from a zero to a one, the device waits for the next occurrence of three consecutive ones to insert a BPV. IBPV must be cleared and set again for another BPV error insertion.

13.3.4 Transmit G.703 Section 10 Synchronization Signal (E1 Mode)

The DS26503 can transmit the 2.048MHz square-wave synchronization clock. To transmit the 2.048MHz clock, when in E1 mode, set the mode configuration bits in the Mode Configuration Register (MCREG).

13.4 MCLK Pre-Scaler

A 2.048MHz x 2 N (where N = 0 to 3), 1.544MHz x 2 N (where N = 0 to 3), or 12.8MHz (available in CPU

interface mode only) clock must be applied to MCLK. A pre-scaler (divide by 2, 4, or 8) and PLLs are selected to product an internal 2.048MHz or 1.544MHz clock. ITU specification G.703 requires an accuracy of ±50ppm for both T1 and E1. TR62411 and ANSI specs require an accuracy of ±32ppm for T1 interfaces.

A pre-scaler divides the 16.384MHz, 12.8MHz, 8.192MHz, or 4.096MHz clock down to 2.048MHz. An onboard PLL for the jitter attenuator converts the 2.048MHz clock to a 1.544MHz rate for T1 applications.

Setting JACKS0 (LIC2.3) to logic 0 bypasses this PLL.

13.5 Jitter Attenuator

The DS26503’s jitter attenuator can be set to a depth of either 32 bits or 128 bits via the JABDS bit

(LIC1.2). The 128-bit mode is used in applications where large excursions of wander are expected. The

32-bit mode is used in delay-sensitive applications. The characteristics of the attenuation are shown in

Figure 13-10 and Figure 13-11 . The jitter attenuator can be placed in either the receive path or the transmit path by appropriately setting or clearing the JAS bit (LIC1.3). If the part is configured for hardware mode and the jitter attenuator is enabled, it will automatically be placed in the receive path. The

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DS26503 T1/E1/J1 BITS Element the incoming jitter exceeds either 120 UI

P-P

(buffer depth is 128 bits) or 28 UI

P-P

(buffer depth is 32 bits), then the DS26503 will divide the internal nominal 32.768MHz (E1) or 24.704MHz (T1) clock by either

15 or 17 instead of the normal 16 to keep the buffer from overflowing. When the device divides by either

15 or 17, it also sets the Jitter Attenuator Limit Trip (JALT) bit in Status Register 1 (SR1.4).

13.6 CMI (Code Mark Inversion) Option

The DS26503 provides a CMI interface for connection to optical transports. This interface is a unipolar

1T2B type of signal. Ones are encoded as either a logical one or zero level for the full duration of the clock period. Zeros are encoded as a zero-to-one transition at the middle of the clock period.

Figure 13-3. CMI Coding

CLOCK

DATA 1 1 0 1 0 0 1

CMI

Transmit and receive CMI is enabled via LIC4.7. When this register bit is set, the TTIP pin will output

CMI-coded data at normal levels. This signal can be used to directly drive an optical interface. When

CMI is enabled, the user can also use HDB3/B8ZS coding. When this register bit is set, the RTIP pin will become a unipolar CMI input. The CMI signal will be processed to extract and align the clock with data.

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13.7 LIU Control Registers

Register Name:


Register Address:

LIC1

Line Interface Control 1

30h

# 7 6 5 4 3 2 1 0

HW

Mode

L2

PIN 13

L1

PIN 12

L0

PIN 11

0 0 0 0 1

Bit 0: Transmit Power-Down (TPD)

0 = powers down the transmitter and three-states the TTIP and TRING pins

1 = normal transmitter operation

Bit 1: Disable Jitter Attenuator (DJA)

0 = jitter attenuator enabled

1 = jitter attenuator disabled

Bit 2: Jitter Attenuator Buffer Depth Select (JABDS)

0 = 128 bits

1 = 32 bits (use for delay-sensitive applications)

Bit 3: Jitter Attenuator Select (JAS)

0 = place the jitter attenuator on the receive side

1 = place the jitter attenuator on the transmit side

Bit 4: Receive Equalizer Gain Limit (EGL). This bit controls the sensitivity of the receive equalizer.

T1 Mode: 0 = -36dB (long haul)

1 = -15dB (limited long haul)

E1 Mode: 0 = -43dB (long haul)

1 = -12dB (short haul)

Bits 5 to 7: Line Build-Out Select (L0 to L2). When using the internal termination, the user needs only to select 000 for 75Ω operation or 001 for 120Ω operation. This selects the proper voltage levels for 75Ω or 120Ω operation. Using TT0, TT1, and

TT2 of the LICR4 register, users can then select the proper internal source termination. Line build-outs 100 and 101 are for backwards compatibility with older products only.

E1 Mode

L2 L1 L0 APPLICATION

N

(NOTE 1)

1:2

1:2

1:2

1:2

RETURN LOSS

N.M.

N.M.

21dB

21dB

Rt

(NOTE 1)

0

0

6.2Ω

11.6Ω


Note 2: TT0, TT1, and TT2 of LIC4 register must be set to zero in this configuration.

N.M. = not meaningful

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T1 Mode

L2 L1 L0

0 0

APPLICATION

0 DSX-1 (0 to 133 feet)/0dB CSU

0

0

0

1

1

0

DSX-1 (133 to 266 feet)

DSX-1 (266 to 399 feet)

0

1

1

0

1 DSX-1 (399 to 533 feet)

0 DSX-1 (533 to 655 feet)

1:2

1:2

1:2

1:2

1:2

—

—

—

RETURN LOSS Rt (NOTE 1)

N.M. 0

N.M.

N.M.

N.M.

0

0

0

N.M.

—

—

—

0

—

—

—


N.M. = not meaningful

Register Name:


Register Address:

TLBC

Transmit Line Build-Out Control

34h

# 7 6 5 4 3 2 1 0

HW

Mode

0 0 0 0 0 0 0 0

Bit 0 to 5: Gain Control Bits 0–5 (GC0–GC5). The GC0 through GC5 bits control the gain setting for the non-automatic gain mode. Use the tables below for setting the recommended values. The LBO (line build-out) column refers to the value in the

L0–L2 bits in LIC1 (Line Interface Control 1) register.

NETWORK MODE LB GC5 GC4 GC3 GC2 GC1 GC0

0 1 0 0 1 1 0

T1, Impedance Match Off

1 0 1 1 0 1 1

2 0 1 1 0 1 0

3 1 0 0 0 0 0

4 1 0 0 1 1 1

5 1 0 0 1 1 1

6 0 1 0 0 1 1

7 1 1 1 1 1 1

0 0 1 1 1 1 0

T1, Impedance Match On

1 0 1 0 1 0 1

2 0 1 0 1 0 1

3 0 1 1 0 1 0

4 1 0 0 0 1 0

5 1 0 0 0 0 0

6 0 0 1 1 0 0

7 1 1 1 1 1 1

0 1 0 0 0 0 1

E1, Impedance Match Off

E1, Impedance Match On

1 1 0 0 0 0 1

4 1 0 1 0 1 0

5 1 0 1 0 0 0

0 0 1 1 0 1 0

1 0 1 1 0 1 0

Bit 6: Automatic Gain Control Enable (AGCE)

0 = use Transmit AGC, TLBC bits 0–5 are “don’t care”

1 = do not use Transmit AGC, TLBC bits 0–5 set nominal level


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Register Name:


Register Address:

LIC2


31h

7 6 5 4 3 2 1 0

Name JACKS1 SCLD CLDS

HW

Mode

JACKS0

PIN 46

0 0 0

Bit 0: Custom Line Driver Select (CLDS). Setting this bit to a one will redefine the operation of the transmit line driver.

When this bit is set to a one and LIC1.5 = LIC1.6 = LIC1.7 = 0, then the device will generate a square wave at the TTIP and

TRING outputs instead of a normal waveform. When this bit is set to a one and LIC1.5 = LIC1.6 = LIC1.7 ≠ 0, then the device will force TTIP and TRING outputs to become open-drain drivers instead of their normal push-pull operation. This bit should be set to zero for normal operation of the device.

Bit 1: Short Circuit Limit Disable (in E1 mode) (SCLD). Controls the 50mA (RMS) current limiter.

0 = enable 50mA current limiter

1 = disable 50mA current limiter

Bits 2 and 7: Unused, must be set = 0 for proper operation.

Bit 3: Jitter Attenuator Clock Select 0 (JACKS0). This bit, along with JACKS1 (LIC2.7), MPS0 (LIC4.6), and MPS1

(LIC4.7), controls the source for JA CLOCK from the MCLK pin. Note: This bit must be configured even if the jitter

attenuator is disabled. The clock and data recovery engine also uses the JA CLOCK. Setting this bit enables the 2.048MHz to

1.544MHz conversion PLL for T1 applications. See the table in the LIC4 register description for more details on setting up the

JA CLOCK source.

0 = 2.048MHz to 1.544MHz PLL bypassed

1 = 2.048MHz to 1.544MHz PLL enabled

Bit 4: Transmit Alarm Indication Signal (TAIS)

0 = transmit an unframed all-ones code

1 = transmit data normally

Bit 5: Insert BPV (IBPV). A zero-to-one transition on this bit will cause a single BPV to be inserted into the transmit data stream. Once this bit has been toggled from a zero to a one, the device waits for the next occurrence of three consecutive ones to insert the BPV. This bit must be cleared and set again for a subsequent error to be inserted.

Bit 6: Line Interface Reset (LIRST). Setting this bit from a zero to a one will initiate an internal reset that resets the clock recovery state machine and recenters the jitter attenuator. Normally this bit is only toggled on power-up. Must be cleared and set again for a subsequent reset.

Bit 7: Jitter Attenuator Clock Select 1 (JACKS1). This bit, along with JACKS0 (LIC2.3), MPS0 (LIC4.6), and MPS1

(LIC4.7), controls the source for JA CLOCK from the MCLK pin. Note: This bit must be configured even if the jitter

attenuator is disabled. The clock and data recovery engine also uses the JA CLOCK. Setting this bit enables the 12.8MHz to

2.048MHz conversion PLL. See the table in the LIC4 register description for more details on setting up the JA CLOCK source.

0 = 12.8MHz to 2.048MHz PLL bypassed

1 = 12.8MHz to 2.048MHz PLL enabled

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Register Name:


Register Address:

LIC3


32h

# 7 6 5 4 3 2 1 0

HW

Mode

0 0 0 0 0 0 0 0

Bit 0: Transmit Alternate Ones and Zeros (TAOZ). Transmit a …101010… pattern at TTIP and TRING.

0 = disabled

1 = enabled


Bits 3 and 4: Monitor Mode (MM0 to MM1)

MM1

0

MM0

0

0 1

1 0

INTERNAL LINEAR GAIN BOOST (dB)

Normal operation (no boost)

20

26

1 1 32

Bit 6: CMI Invert (CMII)

0 = CMI normal at TTIP and RTIP

1 = invert CMI signal at TTIP and RTIP

Bit 7: CMI Enable (CMIE)

0 = disable CMI mode

1 = enable CMI mode

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Register Name:


Register Address:

LIC4


33h

7 6 5 4 3 2 1 0

HW

Mode

MPS1

PIN 16

MPS0

PIN 15

— — — — — —

Bits 0 to 2: Receive Termination Select (RT0 to RT2)

RT2 RT1 RT0

INTERNAL RECEIVE

TERMINATION CONFIGURATION

Bits 3 to 5: Transmit Termination Select (TT0 to TT2)

TT2 TT1 TT0

0 0 0

INTERNAL TRANSMIT

TERMINATION CONFIGURATION

Internal Transmit-Side Termination Disabled

1

1

0

1

1

0



1 1 1 Internal Transmit-Side Termination Disabled

Bits 6 and 7: MCLK Pre-Scaler (MPS0 to MPS1) (T1 Mode)

MCLK (MHz) MPS1 MPS0 JACKS1 (LIC2.3) JACKS0 (LIC2.7)

1.544 0 0 0 0

3.088 0 1

6.176 1 0

0

0

0

0

12.352 1 1

12.80 0 0

2.048 0 0

4.096 0 1

0

1

1

1

0

1

0

0

8.192 1 0

16.384 1 1

Bits 6 and 7: MCLK Pre-Scaler (MPS0 to MPS1) (E1 Mode)

1

1

0

0

MCLK (MHz) MPS1 MPS0 JACKS (LIC2.3) JACKS0 (LIC2.7)

2.048 0 0 0 0

4.096 0 1 0

8.192 1 0 0

0

0

12.80 0 0 0

16.384 1 1 0

1

0

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Register Name:


Register Address:

INFO1

Information Register 1

11h

# 7 6 5 4 3 2 1 0

HW

Mode

X X X X X X X X

Bits 0 to 3: Receive Level Bits (RL0 to RL3). Real-time bits.

1 0 0 0


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Register Name:


Register Address:

SR1


14h

# 7 6 5 4 3 2 1 0

HW

Mode

X X X X X X X X


Bit 1: Transmit Open Circuit Detect Condition (TOCD). Set when the device detects that the TTIP and TRING outputs are open-circuited. Note: This function not supported in transmit 6312kHz mode and is not guaranteed by production testing.

Bit 2: Transmit Current Limit Exceeded Condition (TCLE). Set when the current limiter is activated whether the current limiter is enabled or not. This is set at approximately 50mA (RMS) on the network side of the transformer in E1 operating modes and 70mA (RMS) on the network side of the transformer in T1 operating modes. These values are approximate and are not guaranteed by production testing. Note: This function not supported in transmit CMI, 64kHz or 6312kHz mode.

Bit 4: Jitter Attenuator Limit Trip Event (JALT). Set when the jitter attenuator FIFO reaches to within 4 bits of its useful limit. Will be cleared when read. Useful for debugging jitter-attenuation operation.

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Register Name:


Register Address:

IMR1


15h

# 7 6 5 4 3 2 1 0

HW

Mode

X X X X X X X X


Bit 1: Transmit Open-Circuit Detect Condition (TOCD)


1 = interrupt enabled–generates interrupts on rising and falling edges

Bit 2: Transmit Current Limit Exceeded Condition (TCLE)


1 = interrupt enabled–generates interrupts on rising and falling edges

Bit 4: Jitter Attenuator Limit Trip Event (JALT)



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13.8 Recommended Circuits

Figure 13-4. Software-Selected Termination, Metallic Protection

Table 13-1. Component List (Software-Selected Termination, Metallic

Protection)

NAME DESCRIPTION

F1 and F2 1.25A slow blow fuse

S1 and S2 25V (max) transient suppressor

S3 andS4 77V (max) transient suppressor

Transformer 1:1CT and 1:136CT (5.0V, SMT) (Note 1)

T1 and T2


T3 and T4 Dual common-mode choke (SMT)

Note 1:

Note 2:

Note 3:

Note 4:

T3 and T4 are optional. For more information, contact the Telecom Support Group at www.maxim-ic.com/support .

The layout from the transformers to the network interface is critical. Traces should be at least 25 mils wide and separated from other circuit lines by at least 150 mils. The area under this portion of the circuit should not contain power planes.

Some T1 (never in E1) applications source or sink power from the network-side center taps of the Rx/Tx transformers.

A list of transformer part numbers and manufacturers is available by contacting www.maxim-ic.com/support .

90 of 122


Figure 13-5. Software-Selected Termination, Longitudinal Protection

Table 13-2. Component List (Software-Selected Termination, Longitudinal

Protection)

NAME DESCRIPTION

F1 to F4 1.25A slow blow fuse

S1 and S2 25V (max) transient suppressor (Note 1)

S3, S4, S5, S6 180V (max) transient suppressor (Note 1)

S7 and S8 40V (max) transient suppressor


T1 and T2


T3 and T4 Dual common-mode choke (SMT)

Note 1:

Note 2:

Note 3:

Note 4:

Note 5:

T3 and T4 are optional. For more information, contact the Telecom Support Group at www.maxim-ic.com/support .

A list of alternate transformer part numbers and manufacturers is available at www.maxim-ic.com/support .

The layout from the transformers to the network interface is critical. Traces should be at least 25 mils wide and separated from other circuit lines by at least 150 mils. The area under this portion of the circuit should not contain power planes.

Some T1 (never in E1) applications source or sink power from the network-side center taps of the Rx/Tx transformers.

The ground trace connected to the S2/S3 pair and the S4/S5 pair should be at least 50 mils wide to conduct the extra current from a longitudinal power-cross event.

91 of 122


Figure 13-6. E1 Transmit Pulse Template

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

-0.1

-0.2

-250 -200 -150 -100 -50

194ns

219ns

0

TIME (ns)

Figure 13-7. T1 Transmit Pulse Template

50 100

269ns

G.703

Template

150 200 250

0.7

0.6

0.5

0.4

0.3

0.2

0.1

1.2

1.1

1.0

0.9

0.8

0

-0.1

-0.2

-0.3

-0.4

-0.5

T1.102/87, T1.403,

CB 119 (Oct. 79), &

I.431 Template

-500 -400 -300 -200 -100

MAXIMUM CURVE

UI Time Amp.

-0.77

-0.39

-0.27

-0.27

-0.12

0.00

0.27

0.35

0.93

1.16

-500

-255

-175

-175

-75

0

175

225

600

750

0.05

0.05

0.80

1.15

1.15

1.05

1.05

-0.07

0.05

0.05

MINIMUM CURVE

UI Time Amp.

-0.77

-0.23

-0.23

-0.15

0.00

0.15

0.23

0.23

0.46

0.66

0.93

1.16

-500

-150

-150

-100

0

100

150

150

300

430

600

750

-0.05

-0.05

0.50

0.95

0.95

0.90

0.50

-0.45

-0.45

-0.20

-0.05

-0.05

0 100 200

TIME (ns)

300 400 500 600 700

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Figure 13-8. Jitter Tolerance (T1 Mode)

1K

100

10

1

0.1

1

TR 62411 (Dec. 90)

10

ITU-T G.823

100

DS26503

Tolerance

1K

FREQUENCY (Hz)

Figure 13-9. Jitter Tolerance (E1 Mode)

10K


100K

1k

100

40

10

1

0.1

1

DS26503

Tolerance

10

20

1.5

Minimum Tolerance

Level as per

ITU G.823

100 1k

FREQUENCY (Hz)

2.4k

10k

18k

0.2

100k

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Figure 13-10. Jitter Attenuation (T1 Mode)

0

-20

-40

-60

1

Curve B

10

Curve A

DS26503

T1 MODE

100 1K

FREQUENCY (Hz)

Figure 13-11. Jitter Attenuation (E1 Mode)

0

TBR12

Prohibited

Area

TR 62411 (Dec. 90)

Prohibited Area

10K

ITU G.7XX

Prohibited Area

100K

-20

-40

DS26503

E1 MODE

-60

1 10 100 1K

FREQUENCY (Hz)

10K 100K

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14. LOOPBACK CONFIGURATION

Register Name:


Register Address:

LBCR

Loopback Control Register

20h

# 7 6 5 4 3 2 1 0

HW

Mode

0 0

Bits 0, 1, 4 to 7: Unused, must be set = 0 for proper operation.

Bit 2: Remote Loopback (RLB). In this loopback, data received at RTIP and RRING will be looped back to the transmit LIU.

Received data will continue to pass through the receive side framer of the DS26503 as it would normally and the data from the transmit side formatter will be ignored.



Bit 3: Local Loopback (LLB). In this loopback, data will continue to be transmitted as normal through the transmit side of the

DS26503. Data being received at RTIP and RRING will be replaced with the data being transmitted. Data in this loopback will pass through the jitter attenuator if enabled.



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15. 6312kHz SYNCHRONIZATION INTERFACE

The DS26503 has a 6312kHz Synchronization Interface mode of operation that conforms with Appendix

II.2 of G.703, with the exception that the DS26503 transmits a square wave as opposed to the sine wave that is defined in the G.703 specification.

15.1 Receive 6312kHz Synchronization Interface Operation

On the receive interface, a 6312kHz sine wave is accepted conforming to the input port requirements of

G.703 Appendix II. Alternatively, a 6312kHz square wave will also be accepted. A 6312kHz square wave is output on RCLK in the receive direction. RS is not driven in this mode and will be three-stated.

Table 15-1. Specification of 6312kHz Clock

Signal at Input Port

Frequency 6312kHz

Signal format Sinusoidal wave

Alarm condition Alarm should not be occurred against the amplitude ranged

-16dBm to +3dBm

15.2 Transmit 6312kHz Synchronization Interface Operation

On the transmit interface, a nominally 50% duty cycle, 6312kHz square wave at standard logic levels is available from the PLL_OUT pin. In normal operation, the TCLKO pin will output the same signal.

However, if remote loopback is enabled then TCLKO will be replaced with the recovered receive clock.

See

Figure 3-1 . The G.703 requirements for the 6312kHz transmitted signal are shown in

Table 15-2 . The

user must provide an external circuit to convert the TCLKO or PLL_OUT signal to the level and impedance required by G.703. The RSER and TS pins are ignored in this mode. TTIP and TRING will be three-stated in this mode.

Table 15-2. Specification of 6312kHz Clock

Signal at Output Port

Frequency 6312kHz

Load impedance 75

Ω resistive

Transmission media

Amplitude

Coaxial pair cable

0dBm

± 3dBm

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16. JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT

The DS26503 supports the standard IEEE 1149.1 instruction codes SAMPLE/PRELOAD, BYPASS, and

EXTEST. Optional public instructions included are HIGHZ, CLAMP, and IDCODE. The DS26503 contains the following as required by IEEE 1149.1 Standard Test Access Port and Boundary Scan

Architecture:

Test Access Port (TAP)

TAP Controller

Instruction Register

Bypass Register

Boundary Scan Register

Device Identification Register

Details on Boundary Scan Architecture and the Test Access Port can be found in IEEE 1149.1-1990,

IEEE 1149.1a-1993, and IEEE 1149.1b-1994.

The Test Access Port has the necessary interface pins: JTRST, JTCLK, JTMS, JTDI, and JTDO. See the pin descriptions for details.

Figure 16-1. JTAG Functional Block Diagram

V

DD

10k Ω 10k Ω

V

DD

BOUNDRY SCAN

REGISTER

IDENTIFICATION

REGISTER

BYPASS

REGISTER

INSTRUCTION

REGISTER

TEST ACCESS PORT

CONTROLLER

10k Ω

V

DD

MUX

SELECT

OUTPUT ENABLE

JTDI JTMS JTCLK JTRST JTDO

97 of 122


TAP Controller State Machine

The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of

JTCLK. See Figure 16-2 .

Test-Logic-Reset

Upon power-up, the TAP controller will be in the test-logic-reset state. The instruction register will contain the IDCODE instruction. All system logic of the device will operate normally.

Run-Test-Idle

The run-test-idle is used between scan operations or during specific tests. The instruction register and test registers will remain idle.

Select-DR-Scan

All test registers retain their previous state. With JTMS LOW, a rising edge of JTCLK moves the controller into the capture-DR state and will initiate a scan sequence. JTMS HIGH during a rising edge on JTCLK moves the controller to the select-IR-scan state.

Capture-DR

Data can be parallel-loaded into the test-data registers selected by the current instruction. If the instruction does not call for a parallel load or the selected register does not allow parallel loads, the test register will remain at its current value. On the rising edge of JTCLK, the controller will go to the shift-

DR state if JTMS is LOW or it will go to the exit1-DR state if JTMS is HIGH.

Shift-DR

The test-data register selected by the current instruction will be connected between JTDI and JTDO and will shift data one stage toward its serial output on each rising edge of JTCLK. If a test register selected by the current instruction is not placed in the serial path, it will maintain its previous state.

Exit1-DR

While in this state, a rising edge on JTCLK will put the controller in the update-DR state, which terminates the scanning process, if JTMS is HIGH. A rising edge on JTCLK with JTMS LOW will put the controller in the pause-DR state.

Pause-DR

Shifting of the test registers is halted while in this state. All test registers selected by the current instruction will retain their previous state. The controller will remain in this state while JTMS is LOW. A rising edge on JTCLK with JTMS HIGH will put the controller in the exit2-DR state.

Exit2-DR

A rising edge on JTCLK with JTMS HIGH while in this state will put the controller in the update-DR state and terminate the scanning process. A rising edge on JTCLK with JTMS LOW will enter the shift-

DR state.

Update-DR

A falling edge on JTCLK while in the update-DR state will latch the data from the shift register path of the test registers into the data output latches. This prevents changes at the parallel output due to changes in the shift register.

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Select-IR-Scan

All test registers retain their previous state. The instruction register will remain unchanged during this state. With JTMS LOW, a rising edge on JTCLK moves the controller into the capture-IR state and will initiate a scan sequence for the instruction register. JTMS HIGH during a rising edge on JTCLK puts the controller back into the test-logic-reset state.

Capture-IR

The capture-IR state is used to load the shift register in the instruction register with a fixed value. This value is loaded on the rising edge of JTCLK. If JTMS is HIGH on the rising edge of JTCLK, the controller will enter the exit1-IR state. If JTMS is LOW on the rising edge of JTCLK, the controller will enter the shift-IR state.

Shift-IR

In this state, the shift register in the instruction register is connected between JTDI and JTDO and shifts data one stage for every rising edge of JTCLK toward the serial output. The parallel register as well as all test registers remain at their previous states. A rising edge on JTCLK with JTMS HIGH will move the controller to the exit1-IR state. A rising edge on JTCLK with JTMS LOW will keep the controller in the shift-IR state while moving data one stage thorough the instruction shift register.

Exit1-IR

A rising edge on JTCLK with JTMS LOW will put the controller in the pause-IR state. If JTMS is HIGH on the rising edge of JTCLK, the controller will enter the update-IR state and terminate the scanning process.

Pause-IR

Shifting of the instruction shift register is halted temporarily. With JTMS HIGH, a rising edge on JTCLK will put the controller in the exit2-IR state. The controller will remain in the pause-IR state if JTMS is

LOW during a rising edge on JTCLK.

Exit2-IR

A rising edge on JTCLK with JTMS LOW will put the controller in the update-IR state. The controller will loop back to shift-IR if JTMS is HIGH during a rising edge of JTCLK in this state.

Update-IR

The instruction code shifted into the instruction shift register is latched into the parallel output on the falling edge of JTCLK as the controller enters this state. Once latched, this instruction becomes the current instruction. A rising edge on JTCLK with JTMS LOW puts the controller in the run-test-idle state. With JTMS HIGH, the controller will enter the select-DR-scan state.

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Figure 16-2. TAP Controller State Diagram

1

0

Test Logic

Reset

0

Run Test/

Idle

1

0

1

Select

DR-Scan

0

Capture DR

Shift DR

1

Exit DR

0

Pause DR

Update DR

1

Exit2 DR

0

0

1

1

1

0

1

0

0

1

Select

IR-Scan

0

Capture IR

0

Shift IR

1

Exit IR

0

Pause IR

1

Exit2 IR

1

Update IR

1 0

1

0

1

0

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16.1 Instruction Register

The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length.

When the TAP controller enters the shift-IR state, the instruction shift register will be connected between

JTDI and JTDO. While in the shift-IR state, a rising edge on JTCLK with JTMS LOW will shift the data one stage toward the serial output at JTDO. A rising edge on JTCLK in the exit1-IR state or the exit2-IR state with JTMS HIGH will move the controller to the update-IR state. The falling edge of that same

JTCLK will latch the data in the instruction shift register to the instruction parallel output.

Table 16-1. Instruction Codes for IEEE 1149.1 Architecture

INSTRUCTION REGISTER

BYPASS Bypass

010

111

CLAMP Bypass 011

HIGHZ Bypass 100

IDCODE Device 001

SAMPLE/PRELOAD

This is a mandatory instruction for the IEEE 1149.1 specification that supports two functions. The digital

I/Os of the device can be sampled at the boundary scan register without interfering with the normal operation of the device by using the capture-DR state. SAMPLE/PRELOAD also allows the device to shift data into the boundary scan register via JTDI using the shift-DR state.

BYPASS

When the BYPASS instruction is latched into the parallel instruction register, JTDI connects to JTDO through the one-bit bypass test register. This allows data to pass from JTDI to JTDO not affecting the device’s normal operation.

EXTEST

This allows testing of all interconnections to the device. When the EXTEST instruction is latched in the instruction register, the following actions occur. Once enabled via the Update-IR state, the parallel outputs of all digital output pins will be driven. The boundary scan register will be connected between

JTDI and JTDO. The Capture-DR will sample all digital inputs into the boundary scan register.

CLAMP

All digital outputs of the device will output data from the boundary scan parallel output while connecting the bypass register between JTDI and JTDO. The outputs will not change during the CLAMP instruction.

HIGHZ

All digital outputs of the device will be placed in a high-impedance state. The BYPASS register will be connected between JTDI and JTDO.

101 of 122


IDCODE

When the IDCODE instruction is latched into the parallel instruction register, the identification test register is selected. The device identification code will be loaded into the identification register on the rising edge of JTCLK following entry into the capture-DR state. Shift-DR can be used to shift the identification code out serially via JTDO. During test-logic-reset, the identification code is forced into the instruction register’s parallel output. The ID code will always have a 1 in the LSB position. The next 11 bits identify the manufacturer’s JEDEC number and number of continuation bytes followed by 16 bits for the device and 4 bits for the version

Table 16-2 . Table 16-3 lists the device ID codes.

Table 16-2. ID Code Structure

LSB MSB

Version

Contact Factory

4 bits

Device ID

16 bits

Table 16-3. Device ID Codes

JEDEC

00010100001

1

1

DS26503 0035h

16.2 Test Registers

IEEE 1149.1 requires a minimum of two test registers: the bypass register and the boundary scan register.

An optional test register has been included with the DS26503 design. This test register is the identification register and is used with the IDCODE instruction and the test-logic-reset state of the TAP controller.

16.2.1 Boundary Scan Register

This register contains both a shift register path and a latched parallel output for all control cells and digital I/O cells and is n bits in length. See for all the cell bit locations and definitions.

16.2.2 Bypass Register

This is a single 1-bit shift register used with the BYPASS, CLAMP, and HIGHZ instructions that provides a short path between JTDI and JTDO.

16.2.3 Identification Register

The identification register contains a 32-bit shift register and a 32-bit latched parallel output. This register is selected during the IDCODE instruction and when the TAP controller is in the test-logic-reset state.

102 of 122

Table 16-4. Boundary Scan Control Bits

CELL # NAME TYPE

CONTROL

CELL

1 AD1_7_CTRL

15 INT_CTRL Controlr

25

26 TS_CTRL Controlr

103 of 122


CELL #

30

NAME TYPE

CONTROL

CELL

39 A0

40 AD7 Output3 1

41 AD6 Output3 1

42 AD5 Output3 1

43 AD4 Output3 1

44 AD3 Output3 1

45 AD2 Output3 1

* This pin is not bonded out on the DS26503 package, however, it must be

accounted for in the chain.


104 of 122


17. FUNCTIONAL TIMING DIAGRAMS

17.1 Processor Interface

17.1.1 Parallel Port Mode

See the AC Timing section.

17.1.2 SPI Serial Port Mode

Figure 17-1. SPI Serial Port Access, Read Mode, CPOL = 0, CPHA = 0

SCK

CS

MOSI

MISO

1

MSB

0 0 0 0 0 0 A7

LSB

A6

MSB

A5 A4 A3 A2 A1 A0 B

LSB

D7

MSB

D6 D5 D4 D3 D2 D1


SCK

CS

MOSI

MISO

1

MSB

0 0 0 0 0 0 A7

LSB

A6

MSB

A5 A4 A3 A2 A1 A0 B

LSB

D7

MSB

D6 D5 D4 D3 D2 D1


SCK

CS

MOSI

MISO

1

MSB

0 0 0 0 0 0 A7

LSB

A6

MSB

A5 A4 A3 A2 A1 A0 B

LSB

D7

MSB

D6 D5 D4 D3 D2 D1

D0

LSB

D0

LSB

D0

LSB

105 of 122



SCK

CS

MOSI

MISO

1

MSB

0 0 0 0 0 0 A7

LSB

A6

MSB

A5 A4 A3 A2 A1 A0 B

LSB

D7

MSB

D6 D5 D4 D3 D2 D1 D0

Figure 17-5. SPI Serial Port Access, Write Mode, CPOL = 0, CPHA = 0

LSB

SCK

CS

MOSI

MISO

0 0

MSB

0 0 0 0 0 A7 A6 A5

LSB MSB

A4 A3 A2 A1 A0 B

LSB

D7

MSB

D6 D5 D4 D3 D2 D1 D0


LSB

SCK

CS

MOSI

MISO

0

MSB

0 0 0 0 0 0 A7

LSB

A6

MSB

A5 A4 A3 A2 A1 A0 B

LSB

D7

MSB

D6 D5 D4 D3 D2 D1 D0

LSB

106 of 122



SCK

CS

MOSI

MISO

0 0

MSB

0 0 0 0 0 A7 A6 A5

LSB MSB

A4 A3 A2 A1 A0 B

LSB

D7 D6

MSB

D5 D4 D3 D2 D1 D0

LSB


SCK

CS

MOSI

MISO

0 0

MSB

0 0 0 0 0 A7 A6 A5

LSB MSB

A4 A3 A2 A1 A0 B

LSB

D7 D6

MSB

D5 D4 D3 D2 D1 D0

LSB

107 of 122


18. OPERATING PARAMETERS

ABSOLUTE MAXIMUM RATINGS

Voltage Range on Any Pin Relative to Ground………………………………………………………-1.0V to +6.0V

Operating Temperature Range for DS26503L…………………………………………………………0°C to +70°C

Operating Temperature Range for DS26503LN……………………………………………-40°C to +85°C (Note 1)

Storage Temperature Range………………………………………………………………………...-55°C to +125°C

Soldering Temperature………………………………………………….….See IPC/JEDEC J-STD-20 Specification

This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time can affect reliability.

Note 1: Specifications to -40

°C are guaranteed by design (GBD) and not production tested.

Table 18-1. Thermal Characteristics

Ambient Temperature -40°C +85

°C

2

Junction Temperature

Theta-JA (

θ

JA

) in Still Air +46.3

°C/W

+125

°C

3

Table 18-2. Theta-JA (

θ

JA

) vs. Airflow

FORCED AIR

(meters per second)

THETA-JA (

θ

JA

)

0 +45.3°C/W

1 +37.2°C/W

2.5 +34.4°C/W

Note 2: The package is mounted on a four-layer JEDEC standard test board.

Note 3:

Theta-JA (

θ

JA

) is the junction-to-ambient thermal resistance, when the package is mounted on a four-layer JEDEC standard test board.

Table 18-3. Recommended DC Operating Conditions

(T

A

= 0°C to +70°C for DS26503L; T

A

= -40°C to +85°C for DS26503LN.)

Logic 1

Logic 0

V

IH

2.0 5.5

V

IL

-0.3 +0.8

Supply V

DD

3.135 3.3 5

Note 4: Guaranteed by design (GBD).

Note 5: Applies to RVDD, TVDD, and DVDD.

Table 18-4. Capacitance

(T

A

= +25°C)

Input Capacitance

Output Capacitance

C

IN

5

C

OUT

7 pF

108 of 122


Table 18-5. DC Characteristics

(V

DD

= 3.3V

±5%, T

A

= 0°C to +70°C for DS26503L; V

DD

= 3.3V

±5%, T

A

= -40°C to +85°C for

DS26503LN.)

Supply Current I

DD

85

Input Leakage

Output Leakage

Output Current (2.4V)

I

IL

-1.0 6

I

LO

7

I

OH

mA

Output Current (0.4V) I

OL

+4.0

Note 6: 0.0V < V

IN

< V

DD

Note 7: Applied to

INT when three-stated.

109 of 122


19. AC TIMING PARAMETERS AND DIAGRAMS

Capacitive test loads are 40pF for bus signals and 20pF for all others.

19.1 Multiplexed Bus

Table 19-1. AC Characteristics, Multiplexed Parallel Port

(V

DD

= 3.3V ±5%, T

A

= 0°C to +70°C for DS26503L; V

DD

= 3.3V ±5%, T

DS26503LN.) (Note 1, Figure 19-1 , Figure 19-2 , and

Figure 19-3 )

A

= -40°C to +85°C for

PARAMETER SYMBOL MIN MAX

Cycle Time

Pulse Width, DS Low or RD High t

CYC

200 ns

PW

EL

100 ns

Pulse Width, DS High or RD Low

Input Rise/Fall Times

R/ W Hold Time

R/ W Setup Time Before DS High

CS Setup Time Before DS, WR, or

RD Active

PW

EH

100 ns t

R

, t

F

20 ns t

RWH

10 ns t

RWS

50 ns t

CS

20 ns

CS Hold Time

Read-Data Hold Time

Write-Data Hold Time

Muxed Address Valid to AS or

ALE Fall

Muxed Address Hold Time t

CH

0 ns t

DHR

10 50 ns t

DHW

5 ns t

ASL

15 ns t

AHL

10 ns

Delay Time DS, WR, or RD to AS or ALE Rise

Pulse Width AS or ALE High

Delay Time, AS or ALE to DS,

WR, or RD t

ASD

20 ns

PW

ASH

30 ns t

ASED

10 ns

Output Data Delay Time from DS or RD t

DDR

80 ns

Data Setup Time t

DSW

50 ns

Note 1: The timing parameters listed in this table are guaranteed by design (GBD).

110 of 122


Figure 19-1. Intel Bus Read Timing (BTS = 0 / BIS[1:0] = 00)

tCYC

ALE tASD

PW

ASH

WR

RD tASD t

ASED

PW

EH

PW

EL t

CS

CS

AD0-AD7 t

ASL t

AHL t DDR

Figure 19-2. Intel Bus Write Timing (BTS = 0 / BIS[1:0] = 00)

t

CH t

DHR tCYC

ALE

RD tASD t ASD

WR

PW

EL

PW

ASH

CS t

ASL

AD0-AD7 t

ASED t

CS

PW

EH t

CH t

DHW t

AHL t

DSW

111 of 122


Figure 19-3. Motorola Bus Timing (BTS = 1 / BIS[1:0] = 00)

PW

ASH

AS

DS

PW

EL t

ASD t ASED t CYC

PW

EH t RWS t

RWH

R /W

AD0-AD7

(read) t

ASL t

AHL t CS t

DDR t

CH t

DHR

CS

AD0-AD7

(write) t

ASL t

AHL t

DSW t

DHW

A8 & A9

112 of 122


19.2 Nonmultiplexed Bus

Table 19-2. AC Characteristics, Non-Mux Parallel Port

(V

DD

= 3.3V

±5%, T

A

= 0°C to +70°C for DS26503L; V

DD

= 3.3V

±5%, T

A

= -40°C to +85°C for

DS26503LN.)

(Note 1, Figure 19-4 , Figure 19-5 ,

Figure 19-6 , and Figure 19-7 )

Setup Time for A0 to A7, Valid to

CS Active

Setup Time for

CS Active to

Either

RD, WR, or DS Active

Delay Time from Either

RD or

DS Active to Data Valid

Hold Time from Either

RD, WR, or

DS Inactive to CS Inactive

Hold Time from CS Inactive to

Data Bus Three-State

Wait Time from Either

WR or DS

Activate to Latch Data t1 0 ns t2 0 ns t4 0 ns t6 75 ns

Data Setup Time to Either

WR or

DS Inactive

Data Hold Time from Either

WR or

DS Inactive t7 10 ns t8 10 ns

Address Hold from Either

WR or

DS Inactive t9 10 ns

Note 1: The timing parameters listed in this table are guaranteed by design (GBD).

113 of 122


Figure 19-4. Intel Bus Read Timing (BTS = 0 / BIS[1:0] = 01)

A0 to A7

D0 to D7

WR

CS

RD t1

0ns min

Address Valid

0ns min t2 t3

75ns max

Data Valid

5ns min/20ns max t4 t5

0ns min

Figure 19-5. Intel Bus Write Timing (BTS = 0 / BIS[1:0] = 01)

A0 to A7 Address Valid

D0 to D7

RD

CS

WR t1

0ns min

0ns min t2 t6

75ns min t7

10ns min t8

10ns min t4

0ns min

114 of 122


Figure 19-6. Motorola Bus Read Timing (BTS = 1 / BIS[1:0] = 01)

A0 to A7

D0 to D7

R/ W

CS

DS t1

0ns min.

Address Valid

0ns min. t2 t3

75ns max.

Data Valid

5ns min. / 20ns max. t4 t5

0ns min.

Figure 19-7. Motorola Bus Write Timing (BTS = 1 / BIS[1:0] = 01)

A0 to A7

D0 to D7

R/ W

CS

DS t1

0ns min.

Address Valid

0ns min. t2 t6

75ns min.

10ns min. t7 t8 t4

10ns min.

0ns min.

115 of 122


19.3 Serial Bus

Table 19-3. AC Characteristics, Serial Bus

(V

DD

= 3.3V ±5%, T

A

DS26503LN.)

= 0°C to +70°C for DS26503L; V

DD

(Note 1,

Figure 19-8 and Figure 19-9 )

= 3.3V ±5%, T

A

= -40°C to +85°C for

SYMBOL MIN MAX UNITS DIAGRAM

NUMBER

(NOTE 2)

1

2

CHARACTERISTIC (NOTE 3)

Operating Frequency

Slave

Cycle Time: Slave

Enable Lead Time f

BUS(S) t

CYC(S)

100 ns t

LEAD(S)

15 ns t

LAG(S)

15 ns

4

5

6

7

Clock (CLK) High Time

Slave

Clock (CLK) Low Time

Slave

Data Setup Time (inputs)

Slave

Data Hold Time (inputs)

Slave t

CLKH(S)

50 ns t

CLKL(S)

50 ns t

SU(S)

5 ns t

H(S)

15 ns

CPHA = 0 t

A(CP0)

8

Access Time, Slave

(Note 4)

CPHA = 1 t

A(CP1)

20 ns

9 Disable Time, Slave (Note 5)

10

11

Data Valid Time, After Enable Edge

Slave (Note 6)

Data Hold Time, Outputs, After Enable Edge

Slave


Note 2:

Numbers refer to dimensions in the following Figure 19-8 and Figure 19-9 .

t t t

DIS(S)

V(S)

HD(S) ns ns

5 ns

Note 3: All timing is shown with respect to 20% V

DD

and 70% V

DD

, unless otherwise noted. 100pF load on all SPI pins.

Note 4: Time to data active from high-impedance state.

Note 5: Hold time to high-impedance state.

Note 6: With 100pF on all SPI pins.

116 of 122


Figure 19-8. SPI Interface Timing Diagram, CPHA = 0, BIS[1:0] = 10

CS

INPUT

CLK INPUT

CPOL = 0

CLK INPUT

CPOL = 1

MISO

INPUT

MOSI

OUTPUT

8

2

4

5

1

SLAVE MSB

6 7

MSB

5

4

10

BITS 6-1

BITS 6-1

NOTE: NOT DEFINED, BUT USUALLY MSB OF CHARACTER JUST RECEIVED.

11

SLAVE LSB

LSB

3

NOTE

11

Figure 19-9. SPI Interface Timing Diagram, CPHA = 1, BIS[1:0] = 10

CS

INPUT

1

9

CLK INPUT

CPOL = 0

2

4

5

3

CLK INPUT

CPOL = 1

5

4

8

9

10

MISO

OUTPUT

NOTE SLAVE MSB BITS 6-1 SLAVE LSB

6 7

10

11

MOSI

INPUT

MSB BITS 6-1 LSB

NOTE: NOT DEFINED, BUT USUALLY LSB OF CHARACTER PREVIOUSLY

TRANSMITTED

117 of 122


19.4 Receive Side AC Characteristics

Table 19-4. Receive Side AC Characteristics

(V

DD

= 3.3V ±5%, T

A

= 0°C to +70°C for DS26503L; V

DS26503LN.) (Note 1, Figure 19-10 )

DD

= 3.3V ±5%, T

A

= -40°C to +85°C for

RCLK Period

RCLK Pulse Width

RCLK Pulse Width

RCLK to RSER Delay t

CP

488

648 ns

2

3

158.4 t

CH

200

4 t t

CL

200 t

CH

150 ns 5 ns 6

CL

150 t

D1

RCLK to RS Delay t

D2


Note 2:

Note 3:

Note 4:

Note 5:

Note 6:

E1 mode.

T1 or J1 mode.

6312kHz mode.

Jitter attenuator enabled in the receive path.

Jitter attenuator disabled or enabled in the transmit path.

Figure 19-10. Receive Timing, T1/E1

RCLK t D1

RSER

RS t

D2 E1 = MSB of Channel 1

T1 = F-Bit

118 of 122


19.5 Transmit Side AC Characteristics

Table 19-5. Transmit Side AC Characteristics

( V

DD

= 3.3V ±5%, T

A

= -40°C to +85°C.) (Note 1 and

Figure 19-11 )

TCLK Period

TCLK Pulse Width

TCLK Rise and Fall Times

TX CLOCK Setup to TSER, TS

Delay TX CLOCK to TS

Delay TCLK to PLL_OUT, TX

CLOCK

488 ns 2 t

CP

648 ns 3

158.4 ns 4 t t

CH

75 ns t

CL

75 ns

R

, t

F t

SU t

D2 ns 7 t

D3

Delay TCLKO to TPOSO and

TNEGO t

DD


Note 2:

Note 3:

Note 4:

Note 5:

Note 6:

Note 7:

Note 8:

E1 mode.

T1 or J1 mode.

6312kHz mode.

TS in input mode.

TX CLOCK is an internal signal.

TS in output mode.

TX CLOCK is an internal signal that samples TSER and TS when TS is in input mode. ns 8

119 of 122


Figure 19-11. Transmit Timing, T1/E1

t

CL t

CP t

CH

TCLK t

R

RCLK, JA CLOCK 4 t

F

PLL_OUT tD3

TX CLOCK 3 tSU

TSER tHD tD2

TS_8K_4 1 tSU

TS_8K_4 2

(REFER TO THE TRANSMIT PLL BLOCK DIAGRAM, Figure 3-3 .)

NOTE 1: TS IN OUTPUT MODE.

NOTE 2: TS IN INPUT MODE.

NOTE 3: TX CLOCK IS THE INTERNAL CLOCK THAT DRIVES THE TRANSMIT SECTION. THE

SOURCE OF THIS SIGNAL DEPENDS ON THE CONFIGURATION OF THE TRANSMIT PLL. IF TX

CLOCK IS GENERATED BY THE TRANSMIT PLL (CONVERSION FROM ANOTHER CLOCK RATE)

THEN THE USER SHOULD OUTPUT THAT SIGNAL ON THE PLL_OUT PIN AND USE THAT SIGNAL

TO REFERENCE TSER AND TS IF TS IS IN THE INPUT MODE.

NOTE 4: RCLK (THE RECOVERED LINE CLOCK) AND JA CLOCK (AN INTERNAL CLOCK DERIVED

FROM MCLK) MAY BE SELECTED AS THE SOURCE FOR THE TRANSMIT PLL OR USED

UNCONVERTED FOR TX CLOCK.

120 of 122


20. REVISION HISTORY

REVISION DESCRIPTION

070904 New product release.

032405

081105

101805

Updated Table 2-1 and Table 2-2.

Replaced the older recommended LIU circuits in Section 13.8 with newer versions (Figure 13-4 and Figure 13-5, Table 13-1 and Table 13-2).

Modified the value of t

DD

in Table 19-5. Added timing information to Table 19-5 and updated

Figure 19-11.

Corrected the bit order for the TCPR register. Bits 6 and 7 were reversed. Bits 3 and 4 were reversed.

Corrected the polarity of the TAIS pin description for hardware mode operation (pages 18 and

28). The register control bit description for LIC2.4 is correct.

Added thermal values to Table 18-2.

Changed Section 13.4 to read “2.048 x 2

N

(where N = 1 to 3)” instead of “2.048 x N (where N

= 1 to 4).”

Edited Figure 3-4 to show 12.8MHz clock option and added references throughout relevant sections of the document.

Added JACKS1 bit to LIC2.7—This feature is available in Rev B1 and later.

022806

Clarified the open circuit and short circuit wording in Sections 13.3.1 and 13.3.2 and SR1 bits 1 and 2.

053107

100507

121707

(Page 48) Removed reference to E1RCR and E1TCR bit 3 (this bit functionality has been moved to the MCREG).

(Pages 108–109) In the Absolute Maximum Ratings (Section 18), added Note 1: Specifications at -40

°

C are guaranteed by design GBD and not production tested. to Operating Temp Range for DS26503LN. Renumbered notes for Table 18-1 to Table 18-5.

(Page 16) Clarified RITD and TITD descriptions.

(Page 19) For E1TS description, changed 0 = 120

Ω and 1 = 75Ω to 0 = 75Ω and 1 = 120Ω.

(Page 82) Corrected Note 2 in the LIC1[7:5] register description to include TT2 along with TT0 and TT1.

121 of 122


21. PACKAGE INFORMATION

(The package drawing(s) in this data sheet may not reflect the most current specifications. The package number provided for each package is a link to the latest package outline information.)

64-Pin LQFP ( 56-G4019-001 )

122 of 122

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No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.

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