STMicroelectronics STM32U073C8 Reference Manual

RM0503
Reference manual
STM32U0 series advanced Arm®-based 32-bit MCUs
Introduction
This reference manual targets application developers. It provides complete information on
how to use the STM32U0 series microcontroller memory and peripherals.
The STM32U0 series are microcontroller lines with different packages and peripherals.
Refer to the corresponding data briefs for ordering information, mechanical and electrical
device characteristics.
For information on the Arm® Cortex®-M0+ core, refer to the Cortex®-M0+ Technical
Reference Manual.
The STM32U0 series microcontrollers include ST state-of-the-art patented technology.
Related documents
• Cortex®-M0+ Technical Reference Manual, available from: http://infocenter.arm.com
• STM32U0x1 and STM32U0x3 datasheets.
• STM32U031xx and STM32U073/83xx errata sheets.
March 2024
RM0503 Rev 2
1/1325
www.st.com
1
Contents
RM0503
Contents
1
2
3
Documentation conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
1.1
General information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
1.2
List of abbreviations for registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
1.3
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
1.4
Availability of peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Memory and bus architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
2.1
System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
2.2
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
2.2.2
Memory map and register boundary addresses . . . . . . . . . . . . . . . . . . 56
2.3
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
2.4
Flash memory overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
2.5
Boot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Embedded flash memory (FLASH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.1
FLASH introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.2
FLASH main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.3
FLASH functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
3.4
3.5
2/1325
2.2.1
3.3.1
Flash memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
3.3.2
FLASH empty check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
3.3.3
FLASH error code correction (ECC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
3.3.4
FLASH read access latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.3.5
Flash memory acceleration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
3.3.6
FLASH program and erase operations . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.3.7
FLASH main memory erase sequences . . . . . . . . . . . . . . . . . . . . . . . . 70
3.3.8
FLASH main memory programming sequences . . . . . . . . . . . . . . . . . . 71
FLASH option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
3.4.1
FLASH option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
3.4.2
FLASH option byte programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Flash memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
3.5.1
FLASH read protection (RDP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
3.5.2
FLASH write protection (WRP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
RM0503 Rev 2
RM0503
4
Contents
3.5.3
Securable memory area (HDP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
3.5.4
Securable memory area extension (HDP extension) . . . . . . . . . . . . . . . 84
3.5.5
Disabling core debug access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
3.5.6
Forcing boot from main flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . 86
3.6
FLASH interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
3.7
FLASH registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
3.7.1
FLASH access control register (FLASH_ACR) . . . . . . . . . . . . . . . . . . . 86
3.7.2
FLASH key register (FLASH_KEYR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
3.7.3
FLASH option key register (FLASH_OPTKEYR) . . . . . . . . . . . . . . . . . . 88
3.7.4
FLASH status register (FLASH_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
3.7.5
FLASH control register (FLASH_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . 91
3.7.6
FLASH ECC register (FLASH_ECCR) . . . . . . . . . . . . . . . . . . . . . . . . . 92
3.7.7
FLASH option register (FLASH_OPTR) . . . . . . . . . . . . . . . . . . . . . . . . 93
3.7.8
FLASH WRP area A address register (FLASH_WRP1AR) . . . . . . . . . . 95
3.7.9
FLASH WRP area B address register (FLASH_WRP1BR) . . . . . . . . . . 96
3.7.10
FLASH security register (FLASH_SECR) . . . . . . . . . . . . . . . . . . . . . . . 96
3.7.11
FLASH OEM1 key register 1 (FLASH_OEM1KEYR1) . . . . . . . . . . . . . 97
3.7.12
FLASH OEM1 key register 2 (FLASH_OEM1KEYR2) . . . . . . . . . . . . . 97
3.7.13
FLASH OEM1 key register 3 (FLASH_OEM1KEYR3) . . . . . . . . . . . . . 98
3.7.14
FLASH OEM1 key register 4 (FLASH_OEM1KEYR4) . . . . . . . . . . . . . 98
3.7.15
FLASH OEM2 key register 1 (FLASH_OEM2KEYR1) . . . . . . . . . . . . . 98
3.7.16
FLASH OEM2 key register 2 (FLASH_OEM2KEYR2) . . . . . . . . . . . . . 99
3.7.17
FLASH OEM2 key register 3 (FLASH_OEM2KEYR3) . . . . . . . . . . . . . 99
3.7.18
FLASH OEM2 key register 4 (FLASH_OEM2KEYR4) . . . . . . . . . . . . 100
3.7.19
FLASH OEM key status register (FLASH_OEMKEYSR) . . . . . . . . . . 100
3.7.20
FLASH HDP control register (FLASH_HDPCR) . . . . . . . . . . . . . . . . . 101
3.7.21
FLASH HDP extension register (FLASH_HDPEXTR) . . . . . . . . . . . . . 101
3.7.22
FLASH register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Power control (PWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
4.1
Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
4.1.1
Independent analog peripherals supply . . . . . . . . . . . . . . . . . . . . . . . . 106
4.1.2
Independent USB transceivers supply . . . . . . . . . . . . . . . . . . . . . . . . . 107
4.1.3
Independent LCD supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
4.1.4
Battery backup domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
4.1.5
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
4.1.6
Dynamic voltage scaling management . . . . . . . . . . . . . . . . . . . . . . . . 110
RM0503 Rev 2
3/1325
36
Contents
RM0503
4.2
4.3
4.4
4/1325
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
4.2.1
Power-on reset (POR) / power-down reset (PDR) / brown-out reset
(BOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
4.2.2
Programmable voltage detector (PVD) . . . . . . . . . . . . . . . . . . . . . . . . 111
4.2.3
Peripheral Voltage Monitoring (PVM) . . . . . . . . . . . . . . . . . . . . . . . . . 112
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
4.3.1
Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
4.3.2
Low-power run mode (LP run) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
4.3.3
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
4.3.4
Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
4.3.5
Low-power sleep mode (LP sleep) . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
4.3.6
Stop 0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
4.3.7
Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
4.3.8
Stop 2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
4.3.9
Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
4.3.10
Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
4.3.11
Auto-wakeup from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . 132
PWR registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
4.4.1
Power control register 1 (PWR_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . 133
4.4.2
Power control register 2 (PWR_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . 134
4.4.3
Power control register 3 (PWR_CR3) . . . . . . . . . . . . . . . . . . . . . . . . . 135
4.4.4
Power control register 4 (PWR_CR4) . . . . . . . . . . . . . . . . . . . . . . . . . 137
4.4.5
Power status register 1 (PWR_SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . 138
4.4.6
Power status register 2 (PWR_SR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 139
4.4.7
Power status clear register (PWR_SCR) . . . . . . . . . . . . . . . . . . . . . . . 141
4.4.8
Power Port A pull-up control register (PWR_PUCRA) . . . . . . . . . . . . . 142
4.4.9
Power Port A pull-down control register (PWR_PDCRA) . . . . . . . . . . 142
4.4.10
Power Port B pull-up control register (PWR_PUCRB) . . . . . . . . . . . . . 143
4.4.11
Power Port B pull-down control register (PWR_PDCRB) . . . . . . . . . . 144
4.4.12
Power Port C pull-up control register (PWR_PUCRC) . . . . . . . . . . . . 144
4.4.13
Power Port C pull-down control register (PWR_PDCRC) . . . . . . . . . . 145
4.4.14
Power Port D pull-up control register (PWR_PUCRD) . . . . . . . . . . . . 145
4.4.15
Power Port D pull-down control register (PWR_PDCRD) . . . . . . . . . . 146
4.4.16
Power Port E pull-up control register (PWR_PUCRE) . . . . . . . . . . . . . 146
4.4.17
Power Port E pull-down control register (PWR_PDCRE) . . . . . . . . . . 147
4.4.18
Power Port F pull-up control register (PWR_PUCRF) . . . . . . . . . . . . . 148
4.4.19
Power Port F pull-down control register (PWR_PDCRF) . . . . . . . . . . 148
RM0503 Rev 2
RM0503
Contents
4.4.20
5
PWR register map and reset value table . . . . . . . . . . . . . . . . . . . . . . . 149
Reset and clock control (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
5.1
5.2
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
5.1.1
Power reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
5.1.2
System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
5.1.3
RTC domain reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
5.2.1
HSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
5.2.2
HSI16 clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
5.2.3
HSI48 clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
5.2.4
MSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
5.2.5
PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
5.2.6
LSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
5.2.7
LSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
5.2.8
System clock (SYSCLK) selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
5.2.9
Clock source frequency versus voltage scaling . . . . . . . . . . . . . . . . . . 163
5.2.10
Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
5.2.11
Clock security system for LSE clock (LSECSS) . . . . . . . . . . . . . . . . . 164
5.2.12
ADC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
5.2.13
RTC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
5.2.14
Timer clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
5.2.15
Watchdog clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
5.2.16
Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
5.2.17
Internal/external clock measurement with TIM16 . . . . . . . . . . . . . . . . 166
5.2.18
Peripheral clock enable registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
5.3
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
5.4
RCC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
5.4.1
Clock control register (RCC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
5.4.2
Internal clock sources calibration register (RCC_ICSCR) . . . . . . . . . . 172
5.4.3
Clock configuration register (RCC_CFGR) . . . . . . . . . . . . . . . . . . . . . 173
5.4.4
PLL configuration register (RCC_PLLCFGR) . . . . . . . . . . . . . . . . . . . 176
5.4.5
Clock interrupt enable register (RCC_CIER) . . . . . . . . . . . . . . . . . . . . 178
5.4.6
Clock interrupt flag register (RCC_CIFR) . . . . . . . . . . . . . . . . . . . . . . 180
5.4.7
Clock interrupt clear register (RCC_CICR) . . . . . . . . . . . . . . . . . . . . . 181
5.4.8
AHB peripheral reset register (RCC_AHBRSTR) . . . . . . . . . . . . . . . . 182
5.4.9
I/O port reset register (RCC_IOPRSTR) . . . . . . . . . . . . . . . . . . . . . . . 184
RM0503 Rev 2
5/1325
36
Contents
6
6/1325
RM0503
5.4.10
APB peripheral reset register 1 (RCC_APBRSTR1) . . . . . . . . . . . . . . 185
5.4.11
APB peripheral reset register 2 (RCC_APBRSTR2) . . . . . . . . . . . . . . 188
5.4.12
AHB peripheral clock enable register (RCC_AHBENR) . . . . . . . . . . . 189
5.4.13
I/O port clock enable register (RCC_IOPENR) . . . . . . . . . . . . . . . . . . 190
5.4.14
Debug configuration register (RCC_DBGCFGR) . . . . . . . . . . . . . . . . 191
5.4.15
APB peripheral clock enable register 1 (RCC_APBENR1) . . . . . . . . . 192
5.4.16
APB peripheral clock enable register 2(RCC_APBENR2) . . . . . . . . . . 195
5.4.17
AHB peripheral clock enable in Sleep/Stop mode register
(RCC_AHBSMENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
5.4.18
I/O port in Sleep mode clock enable register (RCC_IOPSMENR) . . . 197
5.4.19
APB peripheral clock enable in Sleep/Stop mode register 1
(RCC_APBSMENR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
5.4.20
APB peripheral clock enable in Sleep/Stop mode register 2
(RCC_APBSMENR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
5.4.21
Peripherals independent clock configuration register (RCC_CCIPR) . 202
5.4.22
RTC domain control register (RCC_BDCR) . . . . . . . . . . . . . . . . . . . . . 205
5.4.23
Control/status register (RCC_CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
5.4.24
RCC clock recovery RC register (RCC_CRRCR) . . . . . . . . . . . . . . . . 209
5.4.25
RCC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
6.1
CRS introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
6.2
CRS main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
6.3
CRS implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
6.4
CRS functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
6.4.1
CRS block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
6.4.2
Synchronization input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
6.4.3
Frequency error measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
6.4.4
Frequency error evaluation and automatic trimming . . . . . . . . . . . . . . 217
6.4.5
CRS initialization and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
6.5
CRS in low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
6.6
CRS interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
6.7
CRS registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
6.7.1
CRS control register (CRS_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
6.7.2
CRS configuration register (CRS_CFGR) . . . . . . . . . . . . . . . . . . . . . . 220
6.7.3
CRS interrupt and status register (CRS_ISR) . . . . . . . . . . . . . . . . . . . 221
6.7.4
CRS interrupt flag clear register (CRS_ICR) . . . . . . . . . . . . . . . . . . . . 223
RM0503 Rev 2
RM0503
Contents
6.7.5
7
General-purpose I/Os (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
7.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
7.2
GPIO main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
7.3
GPIO functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
7.4
8
CRS register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
7.3.1
General-purpose I/O (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
7.3.2
I/O pin alternate function multiplexer and mapping . . . . . . . . . . . . . . . 228
7.3.3
I/O port control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
7.3.4
I/O port data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
7.3.5
I/O data bitwise handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
7.3.6
GPIO locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
7.3.7
I/O alternate function input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
7.3.8
External interrupt/wake-up lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
7.3.9
Input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
7.3.10
Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
7.3.11
Alternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
7.3.12
Analog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
7.3.13
Using the HSE or LSE oscillator pins as GPIOs . . . . . . . . . . . . . . . . . 234
7.3.14
Using the GPIO pins in the RTC supply domain . . . . . . . . . . . . . . . . . 234
7.3.15
Using PF3 as GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
GPIO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
7.4.1
GPIO port mode register (GPIOx_MODER) (x = A to F) . . . . . . . . . . . 234
7.4.2
GPIO port output type register (GPIOx_OTYPER) (x = A to F) . . . . . . 235
7.4.3
GPIO port output speed register (GPIOx_OSPEEDR) (x = A to F) . . . 235
7.4.4
GPIO port pull-up/pull-down register (GPIOx_PUPDR) (x = A to F) . . 236
7.4.5
GPIO port input data register (GPIOx_IDR) (x = A to F) . . . . . . . . . . . 236
7.4.6
GPIO port output data register (GPIOx_ODR) (x = A to F) . . . . . . . . . 236
7.4.7
GPIO port bit set/reset register (GPIOx_BSRR) (x = A to F) . . . . . . . . 237
7.4.8
GPIO port configuration lock register (GPIOx_LCKR) (x = A to F) . . . 237
7.4.9
GPIO alternate function low register (GPIOx_AFRL) (x = A to F) . . . . 239
7.4.10
GPIO alternate function high register (GPIOx_AFRH) (x = A to F) . . . 239
7.4.11
GPIO port bit reset register (GPIOx_BRR) (x = A to F) . . . . . . . . . . . . 240
7.4.12
GPIO register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
System configuration controller (SYSCFG) . . . . . . . . . . . . . . . . . . . . 242
8.1
SYSCFG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
RM0503 Rev 2
7/1325
36
Contents
8/1325
RM0503
8.1.1
SYSCFG configuration register 1 (SYSCFG_CFGR1) . . . . . . . . . . . . 242
8.1.2
SYSCFG configuration register 2 (SYSCFG_CFGR2) . . . . . . . . . . . . 245
8.1.3
SYSCFG SRAM2 control and status register (SYSCFG_SCSR) . . . . 246
8.1.4
SYSCFG SRAM2 key register (SYSCFG_SKR) . . . . . . . . . . . . . . . . . 247
8.1.5
SYSCFG TSC comparator register (SYSCFG_TSCCR) . . . . . . . . . . . 247
8.1.6
SYSCFG interrupt line 0 status register (SYSCFG_ITLINE0) . . . . . . . 248
8.1.7
SYSCFG interrupt line 1 status register (SYSCFG_ITLINE1) . . . . . . . 248
8.1.8
SYSCFG interrupt line 2 status register (SYSCFG_ITLINE2) . . . . . . . 249
8.1.9
SYSCFG interrupt line 3 status register (SYSCFG_ITLINE3) . . . . . . . 249
8.1.10
SYSCFG interrupt line 4 status register (SYSCFG_ITLINE4) . . . . . . . 250
8.1.11
SYSCFG interrupt line 5 status register (SYSCFG_ITLINE5) . . . . . . . 250
8.1.12
SYSCFG interrupt line 6 status register (SYSCFG_ITLINE6) . . . . . . . 250
8.1.13
SYSCFG interrupt line 7 status register (SYSCFG_ITLINE7) . . . . . . . 251
8.1.14
SYSCFG interrupt line 8 status register (SYSCFG_ITLINE8) . . . . . . . 251
8.1.15
SYSCFG interrupt line 9 status register (SYSCFG_ITLINE9) . . . . . . . 252
8.1.16
SYSCFG interrupt line 10 status register (SYSCFG_ITLINE10) . . . . . 252
8.1.17
SYSCFG interrupt line 11 status register (SYSCFG_ITLINE11) . . . . . 253
8.1.18
SYSCFG interrupt line 12 status register (SYSCFG_ITLINE12) . . . . . 253
8.1.19
SYSCFG interrupt line 13 status register (SYSCFG_ITLINE13) . . . . . 254
8.1.20
SYSCFG interrupt line 14 status register (SYSCFG_ITLINE14) . . . . . 254
8.1.21
SYSCFG interrupt line 15 status register (SYSCFG_ITLINE15) . . . . . 255
8.1.22
SYSCFG interrupt line 16 status register (SYSCFG_ITLINE16) . . . . . 255
8.1.23
SYSCFG interrupt line 17 status register (SYSCFG_ITLINE17) . . . . . 255
8.1.24
SYSCFG interrupt line 18 status register (SYSCFG_ITLINE18) . . . . . 256
8.1.25
SYSCFG interrupt line 19 status register (SYSCFG_ITLINE19) . . . . . 256
8.1.26
SYSCFG interrupt line 20 status register (SYSCFG_ITLINE20) . . . . . 256
8.1.27
SYSCFG interrupt line 21 status register (SYSCFG_ITLINE21) . . . . . 257
8.1.28
SYSCFG interrupt line 22 status register (SYSCFG_ITLINE22) . . . . . 257
8.1.29
SYSCFG interrupt line 23 status register (SYSCFG_ITLINE23) . . . . . 257
8.1.30
SYSCFG interrupt line 24 status register (SYSCFG_ITLINE24) . . . . . 258
8.1.31
SYSCFG interrupt line 25 status register (SYSCFG_ITLINE25) . . . . . 258
8.1.32
SYSCFG interrupt line 26 status register (SYSCFG_ITLINE26) . . . . . 258
8.1.33
SYSCFG interrupt line 27 status register (SYSCFG_ITLINE27) . . . . . 259
8.1.34
SYSCFG interrupt line 28 status register (SYSCFG_ITLINE28) . . . . . 259
8.1.35
SYSCFG interrupt line 29 status register (SYSCFG_ITLINE29) . . . . . 260
8.1.36
SYSCFG interrupt line 30 status register (SYSCFG_ITLINE30) . . . . . 260
8.1.37
SYSCFG interrupt line 31 status register (SYSCFG_ITLINE31) . . . . . 260
RM0503 Rev 2
RM0503
Contents
8.1.38
9
Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . 264
9.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
9.2
DMA main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
9.3
DMA implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
9.4
10
SYSCFG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
9.3.1
DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
9.3.2
DMA request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
DMA functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
9.4.1
DMA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
9.4.2
DMA pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
9.4.3
DMA transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
9.4.4
DMA arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
9.4.5
DMA channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
9.4.6
DMA data width, alignment, and endianness . . . . . . . . . . . . . . . . . . . . 272
9.4.7
DMA error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
9.5
DMA interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
9.6
DMA registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
9.6.1
DMA interrupt status register (DMA_ISR) . . . . . . . . . . . . . . . . . . . . . . 274
9.6.2
DMA interrupt flag clear register (DMA_IFCR) . . . . . . . . . . . . . . . . . . 277
9.6.3
DMA channel x configuration register (DMA_CCRx) . . . . . . . . . . . . . . 278
9.6.4
DMA channel x number of data to transfer register (DMA_CNDTRx) . 281
9.6.5
DMA channel x peripheral address register (DMA_CPARx) . . . . . . . . 281
9.6.6
DMA channel x memory address register (DMA_CMARx) . . . . . . . . . 282
9.6.7
DMA register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
DMA request multiplexer (DMAMUX) . . . . . . . . . . . . . . . . . . . . . . . . . 285
10.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
10.2
DMAMUX main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
10.3
DMAMUX implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
10.4
10.3.1
DMAMUX instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
10.3.2
DMAMUX mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
DMAMUX functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
10.4.1
DMAMUX block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
10.4.2
DMAMUX signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
10.4.3
DMAMUX channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
RM0503 Rev 2
9/1325
36
Contents
11
12
RM0503
10.4.4
DMAMUX request line multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
10.4.5
DMAMUX request generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
10.5
DMAMUX interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
10.6
DMAMUX registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
10.6.1
DMAMUX request line multiplexer channel x configuration register
(DMAMUX_CxCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
10.6.2
DMAMUX request line multiplexer interrupt channel status register
(DMAMUX_CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
10.6.3
DMAMUX request line multiplexer interrupt clear flag register
(DMAMUX_CFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
10.6.4
DMAMUX request generator channel x configuration register
(DMAMUX_RGxCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
10.6.5
DMAMUX request generator interrupt status register
(DMAMUX_RGSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
10.6.6
DMAMUX request generator interrupt clear flag register
(DMAMUX_RGCFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
10.6.7
DMAMUX register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . 301
11.1
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
11.2
SysTick calibration value register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
11.3
Interrupt and exception vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
Extended interrupt and event controller (EXTI) . . . . . . . . . . . . . . . . . 304
12.1
EXTI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
12.2
EXTI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
12.2.1
12.3
10/1325
EXTI connections between peripherals and CPU . . . . . . . . . . . . . . . . 306
EXTI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
12.3.1
EXTI configurable event input wake-up . . . . . . . . . . . . . . . . . . . . . . . . 307
12.3.2
EXTI direct event input wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
12.3.3
EXTI mux . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
12.4
EXTI functional behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
12.5
EXTI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .311
12.5.1
EXTI rising trigger selection register (EXTI_RTSR1) . . . . . . . . . . . . . . 311
12.5.2
EXTI falling trigger selection register 1 (EXTI_FTSR1) . . . . . . . . . . . . 312
12.5.3
EXTI software interrupt event register 1 (EXTI_SWIER1) . . . . . . . . . . 312
12.5.4
EXTI rising edge pending register 1 (EXTI_RPR1) . . . . . . . . . . . . . . . 313
12.5.5
EXTI falling edge pending register 1 (EXTI_FPR1) . . . . . . . . . . . . . . . 313
RM0503 Rev 2
RM0503
Contents
12.5.6
EXTI external interrupt selection register x (EXTI_EXTICRx) . . . . . . . 314
12.5.7
EXTI CPU wake-up with interrupt mask register (EXTI_IMR1) . . . . . . 315
12.5.8
EXTI CPU wake-up with event mask register (EXTI_EMR1) . . . . . . . 315
12.5.9
EXTI CPU wake-up with interrupt mask register (EXTI_IMR2) . . . . . . 316
12.5.10 EXTI CPU wake-up with event mask register (EXTI_EMR2) . . . . . . . 316
12.5.11 EXTI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
13
Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . 319
13.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
13.2
CRC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
13.3
CRC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
13.4
14
13.3.1
CRC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
13.3.2
CRC internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
13.3.3
CRC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
CRC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
13.4.1
CRC data register (CRC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
13.4.2
CRC independent data register (CRC_IDR) . . . . . . . . . . . . . . . . . . . . 322
13.4.3
CRC control register (CRC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
13.4.4
CRC initial value (CRC_INIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
13.4.5
CRC polynomial (CRC_POL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
13.4.6
CRC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
14.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
14.2
ADC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
14.3
ADC implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
14.4
ADC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
14.4.1
ADC pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
14.4.2
ADC voltage regulator (ADVREGEN) . . . . . . . . . . . . . . . . . . . . . . . . . 331
14.4.3
Calibration (ADCAL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
14.4.4
ADC on-off control (ADEN, ADDIS, ADRDY) . . . . . . . . . . . . . . . . . . . . 333
14.4.5
ADC clock (CKMODE, PRESC[3:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . 334
14.4.6
ADC connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
14.4.7
Configuring the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
14.4.8
Channel selection (CHSEL, SCANDIR, CHSELRMOD) . . . . . . . . . . . 337
14.4.9
Programmable sampling time (SMPx[2:0]) . . . . . . . . . . . . . . . . . . . . . 338
RM0503 Rev 2
11/1325
36
Contents
RM0503
14.4.10 Single conversion mode (CONT = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . 338
14.4.11 Continuous conversion mode (CONT = 1) . . . . . . . . . . . . . . . . . . . . . . 339
14.4.12 Starting conversions (ADSTART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
14.4.13 Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
14.4.14 Stopping an ongoing conversion (ADSTP) . . . . . . . . . . . . . . . . . . . . . 341
14.5
14.6
14.7
14.8
14.9
Conversion on external trigger and trigger polarity (EXTSEL, EXTEN) . 342
14.5.1
Discontinuous mode (DISCEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
14.5.2
Programmable resolution (RES) - Fast conversion mode . . . . . . . . . . 343
14.5.3
End of conversion, end of sampling phase (EOC, EOSMP flags) . . . . 344
14.5.4
End of conversion sequence (EOS flag) . . . . . . . . . . . . . . . . . . . . . . . 344
14.5.5
Example timing diagrams (single/continuous modes
hardware/software triggers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
14.5.6
Low frequency trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
Data management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
14.6.1
Data register and data alignment (ADC_DR, ALIGN) . . . . . . . . . . . . . 347
14.6.2
ADC overrun (OVR, OVRMOD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
14.6.3
Managing a sequence of data converted without using the DMA . . . . 348
14.6.4
Managing converted data without using the DMA without overrun . . . 348
14.6.5
Managing converted data using the DMA . . . . . . . . . . . . . . . . . . . . . . 348
Low-power features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
14.7.1
Wait mode conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
14.7.2
Auto-off mode (AUTOFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
Analog window watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
14.8.1
Description of analog watchdog 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
14.8.2
Description of analog watchdog 2 and 3 . . . . . . . . . . . . . . . . . . . . . . . 353
14.8.3
ADC_AWDx_OUT output signal generation . . . . . . . . . . . . . . . . . . . . 354
14.8.4
Analog Watchdog threshold control . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
Oversampler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356
14.9.1
ADC operating modes supported when oversampling . . . . . . . . . . . . 358
14.9.2
Analog watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
14.9.3
Triggered mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
14.10 Temperature sensor and internal reference voltage . . . . . . . . . . . . . . . . 359
14.11 Battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
14.12 ADC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
14.13 ADC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
14.13.1 ADC interrupt and status register (ADC_ISR) . . . . . . . . . . . . . . . . . . . 363
12/1325
RM0503 Rev 2
RM0503
Contents
14.13.2 ADC interrupt enable register (ADC_IER) . . . . . . . . . . . . . . . . . . . . . . 365
14.13.3 ADC control register (ADC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
14.13.4 ADC configuration register 1 (ADC_CFGR1) . . . . . . . . . . . . . . . . . . . 369
14.13.5 ADC configuration register 2 (ADC_CFGR2) . . . . . . . . . . . . . . . . . . . 372
14.13.6 ADC sampling time register (ADC_SMPR) . . . . . . . . . . . . . . . . . . . . . 373
14.13.7 ADC watchdog threshold register (ADC_AWD1TR) . . . . . . . . . . . . . . 374
14.13.8 ADC watchdog threshold register (ADC_AWD2TR) . . . . . . . . . . . . . . 375
14.13.9 ADC channel selection register (ADC_CHSELR) . . . . . . . . . . . . . . . . 376
14.13.10 ADC channel selection register [alternate] (ADC_CHSELR) . . . . . . . . 377
14.13.11 ADC watchdog threshold register (ADC_AWD3TR) . . . . . . . . . . . . . . 379
14.13.12 ADC data register (ADC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
14.13.13 ADC analog watchdog 2 configuration register (ADC_AWD2CR) . . . . 380
14.13.14 ADC Analog Watchdog 3 Configuration register (ADC_AWD3CR) . . . 380
14.13.15 ADC calibration factor (ADC_CALFACT) . . . . . . . . . . . . . . . . . . . . . . . 381
14.13.16 ADC common configuration register (ADC_CCR) . . . . . . . . . . . . . . . . 381
14.14 ADC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
15
Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
15.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
15.2
DAC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
15.3
DAC implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
15.4
DAC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
15.4.1
DAC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
15.4.2
DAC pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
15.4.3
DAC channel enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388
15.4.4
DAC data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388
15.4.5
DAC conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
15.4.6
DAC output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
15.4.7
DAC trigger selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
15.4.8
DMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
15.4.9
Noise generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
15.4.10 Triangle-wave generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
15.4.11
DAC channel modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
15.4.12 DAC channel buffer calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396
15.4.13 DAC channel conversion modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
15.5
DAC in low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
RM0503 Rev 2
13/1325
36
Contents
RM0503
15.6
DAC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
15.7
DAC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
15.7.1
DAC control register (DAC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
15.7.2
DAC software trigger register (DAC_SWTRGR) . . . . . . . . . . . . . . . . . 402
15.7.3
DAC channel1 12-bit right-aligned data holding register
(DAC_DHR12R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
15.7.4
DAC channel1 12-bit left aligned data holding register
(DAC_DHR12L1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
15.7.5
DAC channel1 8-bit right aligned data holding register
(DAC_DHR8R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
15.7.6
DAC channel1 data output register (DAC_DOR1) . . . . . . . . . . . . . . . . 404
15.7.7
DAC status register (DAC_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404
15.7.8
DAC calibration control register (DAC_CCR) . . . . . . . . . . . . . . . . . . . 405
15.7.9
DAC mode control register (DAC_MCR) . . . . . . . . . . . . . . . . . . . . . . . 405
15.7.10 DAC channel1 sample and hold sample time register
(DAC_SHSR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
15.7.11 DAC sample and hold time register (DAC_SHHR) . . . . . . . . . . . . . . . 407
15.7.12 DAC sample and hold refresh time register (DAC_SHRR) . . . . . . . . . 407
15.7.13 DAC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408
16
17
14/1325
Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . 410
16.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
16.2
VREFBUF functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
16.3
VREFBUF registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .411
16.3.1
VREFBUF control and status register (VREFBUF_CSR) . . . . . . . . . . 411
16.3.2
VREFBUF calibration control register (VREFBUF_CCR) . . . . . . . . . . 411
16.3.3
VREFBUF register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412
Comparator (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413
17.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413
17.2
COMP main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413
17.3
COMP functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
17.3.1
COMP block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
17.3.2
COMP pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
17.3.3
COMP reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416
17.3.4
Comparator LOCK mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416
17.3.5
Window comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416
17.3.6
Hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
RM0503 Rev 2
RM0503
18
19
Contents
17.3.7
Comparator output blanking function . . . . . . . . . . . . . . . . . . . . . . . . . . 417
17.3.8
COMP power and speed modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
17.4
COMP low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
17.5
COMP interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419
17.6
COMP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420
17.6.1
Comparator 1 control and status register (COMP1_CSR) . . . . . . . . . . 420
17.6.2
Comparator 2 control and status register (COMP2_CSR) . . . . . . . . . . 421
17.6.3
COMP register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424
Operational amplifiers (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
18.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
18.2
OPAMP main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
18.3
OPAMP functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
18.3.1
OPAMP reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
18.3.2
Initial configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426
18.3.3
Signal routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426
18.3.4
OPAMP modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426
18.3.5
Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430
18.4
OPAMP low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432
18.5
OPAMP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
18.5.1
OPAMP1 control/status register (OPAMP1_CSR) . . . . . . . . . . . . . . . . 433
18.5.2
OPAMP1 offset trimming register in normal mode (OPAMP1_OTR) . . 434
18.5.3
OPAMP1 offset trimming register in low-power mode
(OPAMP1_LPOTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434
18.5.4
OPAMP register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435
Liquid crystal display controller (LCD) . . . . . . . . . . . . . . . . . . . . . . . . 436
19.1
LCD introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436
19.2
LCD main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436
19.3
LCD functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438
19.3.1
General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438
19.3.2
Frequency generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
19.3.3
Common driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440
19.3.4
Segment driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443
19.3.5
Voltage generator and contrast control . . . . . . . . . . . . . . . . . . . . . . . . 447
19.3.6
Double-buffer memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449
RM0503 Rev 2
15/1325
36
Contents
20
RM0503
19.3.7
COM and SEG multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450
19.3.8
Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451
19.4
LCD low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452
19.5
LCD interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452
19.6
LCD registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453
19.6.1
LCD control register (LCD_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453
19.6.2
LCD frame control register (LCD_FCR) . . . . . . . . . . . . . . . . . . . . . . . . 454
19.6.3
LCD status register (LCD_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456
19.6.4
LCD clear register (LCD_CLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458
19.6.5
LCD display memory (LCD_RAMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . 458
19.6.6
LCD display memory (LCD_RAMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . 459
19.6.7
LCD display memory (LCD_RAMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . 459
19.6.8
LCD register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459
Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462
20.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462
20.2
TSC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462
20.3
TSC implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463
20.4
TSC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464
20.5
20.4.1
TSC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464
20.4.2
Surface charge transfer acquisition overview . . . . . . . . . . . . . . . . . . . 464
20.4.3
Reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467
20.4.4
Charge transfer acquisition sequence . . . . . . . . . . . . . . . . . . . . . . . . . 467
20.4.5
Spread spectrum feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468
20.4.6
Max count error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469
20.4.7
Sampling capacitor I/O and channel I/O mode selection . . . . . . . . . . . 469
20.4.8
Acquisition mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470
20.4.9
I/O hysteresis and analog switch control . . . . . . . . . . . . . . . . . . . . . . . 470
TSC low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471
20.5.1
16/1325
Comparator usage overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471
20.6
TSC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474
20.7
TSC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474
20.7.1
TSC control register (TSC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474
20.7.2
TSC interrupt enable register (TSC_IER) . . . . . . . . . . . . . . . . . . . . . . 477
20.7.3
TSC interrupt clear register (TSC_ICR) . . . . . . . . . . . . . . . . . . . . . . . . 478
20.7.4
TSC interrupt status register (TSC_ISR) . . . . . . . . . . . . . . . . . . . . . . . 478
RM0503 Rev 2
RM0503
Contents
20.7.5
TSC I/O hysteresis control register (TSC_IOHCR) . . . . . . . . . . . . . . . 479
20.7.6
TSC I/O analog switch control register
(TSC_IOASCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479
20.7.7
TSC I/O sampling control register (TSC_IOSCR) . . . . . . . . . . . . . . . . 480
20.7.8
TSC I/O channel control register (TSC_IOCCR) . . . . . . . . . . . . . . . . . 480
20.7.9
TSC I/O group control status register (TSC_IOGCSR) . . . . . . . . . . . . 481
20.7.10 TSC I/O group x counter register (TSC_IOGxCR) . . . . . . . . . . . . . . . . 481
20.7.11 TSC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482
21
True random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . 484
21.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484
21.2
RNG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484
21.3
RNG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485
RNG block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485
21.3.2
RNG internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485
21.3.3
Random number generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486
21.3.4
RNG initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489
21.3.5
RNG operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490
21.3.6
RNG clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491
21.3.7
Error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491
21.3.8
RNG low-power use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492
21.4
RNG interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493
21.5
RNG processing time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494
21.6
RNG entropy source validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494
21.7
22
21.3.1
21.6.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494
21.6.2
Validation conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495
RNG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496
21.7.1
RNG control register (RNG_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496
21.7.2
RNG status register (RNG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498
21.7.3
RNG data register (RNG_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499
21.7.4
RNG noise source control register (RNG_NSCR) . . . . . . . . . . . . . . . . 499
21.7.5
RNG health test control register (RNG_HTCR) . . . . . . . . . . . . . . . . . . 500
21.7.6
RNG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501
AES hardware accelerator (AES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502
22.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502
RM0503 Rev 2
17/1325
36
Contents
RM0503
22.2
AES main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502
22.3
AES implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502
22.4
AES functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503
22.4.1
AES block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503
22.4.2
AES internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503
22.4.3
AES cryptographic core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503
22.4.4
AES procedure to perform a cipher operation . . . . . . . . . . . . . . . . . . . 509
22.4.5
AES decryption round key preparation . . . . . . . . . . . . . . . . . . . . . . . . 512
22.4.6
AES ciphertext stealing and data padding . . . . . . . . . . . . . . . . . . . . . . 512
22.4.7
AES task suspend and resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513
22.4.8
AES basic chaining modes (ECB, CBC) . . . . . . . . . . . . . . . . . . . . . . . 513
22.4.9
AES counter (CTR) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518
22.4.10 AES Galois/counter mode (GCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520
22.4.11 AES Galois message authentication code (GMAC) . . . . . . . . . . . . . . 525
22.4.12 AES counter with CBC-MAC (CCM) . . . . . . . . . . . . . . . . . . . . . . . . . . 527
22.4.13 AES data registers and data swapping . . . . . . . . . . . . . . . . . . . . . . . . 532
22.4.14 AES key registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534
22.4.15 AES initialization vector registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534
22.4.16 AES DMA interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535
22.4.17 AES error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
22.5
AES interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537
22.6
AES processing latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537
22.7
AES registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538
22.7.1
AES control register (AES_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538
22.7.2
AES status register (AES_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540
22.7.3
AES data input register (AES_DINR) . . . . . . . . . . . . . . . . . . . . . . . . . 542
22.7.4
AES data output register (AES_DOUTR) . . . . . . . . . . . . . . . . . . . . . . 542
22.7.5
AES key register 0 (AES_KEYR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543
22.7.6
AES key register 1 (AES_KEYR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543
22.7.7
AES key register 2 (AES_KEYR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544
22.7.8
AES key register 3 (AES_KEYR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544
22.7.9
AES initialization vector register 0 (AES_IVR0) . . . . . . . . . . . . . . . . . . 544
22.7.10 AES initialization vector register 1 (AES_IVR1) . . . . . . . . . . . . . . . . . . 545
22.7.11 AES initialization vector register 2 (AES_IVR2) . . . . . . . . . . . . . . . . . . 545
22.7.12 AES initialization vector register 3 (AES_IVR3) . . . . . . . . . . . . . . . . . . 545
22.7.13 AES key register 4 (AES_KEYR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546
18/1325
RM0503 Rev 2
RM0503
Contents
22.7.14 AES key register 5 (AES_KEYR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546
22.7.15 AES key register 6 (AES_KEYR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546
22.7.16 AES key register 7 (AES_KEYR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547
22.7.17 AES suspend registers (AES_SUSPxR) . . . . . . . . . . . . . . . . . . . . . . . 547
22.7.18 AES register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548
23
Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550
23.1
TIM1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550
23.2
TIM1 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551
23.3
TIM1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553
23.3.1
Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553
23.3.2
Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555
23.3.3
Repetition counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566
23.3.4
External trigger input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568
23.3.5
Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569
23.3.6
Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573
23.3.7
Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575
23.3.8
PWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576
23.3.9
Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577
23.3.10 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578
23.3.11 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579
23.3.12 Asymmetric PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582
23.3.13 Combined PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583
23.3.14 Combined 3-phase PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584
23.3.15 Complementary outputs and dead-time insertion . . . . . . . . . . . . . . . . 585
23.3.16 Using the break function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587
23.3.17 Bidirectional break inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593
23.3.18 Clearing the OCxREF signal on an external event . . . . . . . . . . . . . . . 595
23.3.19 6-step PWM generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596
23.3.20 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597
23.3.21 Retriggerable one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598
23.3.22 Encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599
23.3.23 UIF bit remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601
23.3.24 Timer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602
23.3.25 Interfacing with Hall sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602
23.3.26 Timer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605
23.3.27 ADC synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609
RM0503 Rev 2
19/1325
36
Contents
RM0503
23.3.28 DMA burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609
23.3.29 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610
23.4
TIM1 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .611
23.4.1
TIM1 control register 1 (TIM1_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . 611
23.4.2
TIM1 control register 2 (TIM1_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 612
23.4.3
TIM1 slave mode control register
(TIM1_SMCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615
23.4.4
TIM1 DMA/interrupt enable register
(TIM1_DIER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617
23.4.5
TIM1 status register (TIM1_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619
23.4.6
TIM1 event generation register (TIM1_EGR) . . . . . . . . . . . . . . . . . . . 621
23.4.7
TIM1 capture/compare mode register 1 (TIM1_CCMR1) . . . . . . . . . . 622
23.4.8
TIM1 capture/compare mode register 1 [alternate]
(TIM1_CCMR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623
23.4.9
TIM1 capture/compare mode register 2 (TIM1_CCMR2) . . . . . . . . . . 626
23.4.10 TIM1 capture/compare mode register 2 [alternate]
(TIM1_CCMR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627
23.4.11 TIM1 capture/compare enable register
(TIM1_CCER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629
23.4.12 TIM1 counter (TIM1_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632
23.4.13 TIM1 prescaler (TIM1_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632
23.4.14 TIM1 auto-reload register (TIM1_ARR) . . . . . . . . . . . . . . . . . . . . . . . . 632
23.4.15 TIM1 repetition counter register (TIM1_RCR) . . . . . . . . . . . . . . . . . . . 633
23.4.16 TIM1 capture/compare register 1
(TIM1_CCR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633
23.4.17 TIM1 capture/compare register 2
(TIM1_CCR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634
23.4.18 TIM1 capture/compare register 3
(TIM1_CCR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634
23.4.19 TIM1 capture/compare register 4
(TIM1_CCR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635
23.4.20 TIM1 break and dead-time register
(TIM1_BDTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635
23.4.21 TIM1 DMA control register
(TIM1_DCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639
23.4.22 TIM1 DMA address for full transfer
(TIM1_DMAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640
23.4.23 TIM1 option register 1 (TIM1_OR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 641
23.4.24 TIM1 capture/compare mode register 3
(TIM1_CCMR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641
20/1325
RM0503 Rev 2
RM0503
Contents
23.4.25 TIM1 capture/compare register 5
(TIM1_CCR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642
23.4.26 TIM1 capture/compare register 6
(TIM1_CCR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643
23.4.27 TIM1 alternate function option register 1 (TIM1_AF1) . . . . . . . . . . . . . 644
23.4.28 TIM1 Alternate function register 2 (TIM1_AF2) . . . . . . . . . . . . . . . . . . 645
23.4.29 TIM1 timer input selection register (TIM1_TISEL) . . . . . . . . . . . . . . . . 647
23.4.30 TIM1 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648
24
General-purpose timers (TIM2/TIM3) . . . . . . . . . . . . . . . . . . . . . . . . . . 651
24.1
TIM2/TIM3 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651
24.2
TIM2/TIM3 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651
24.3
TIM2/TIM3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653
24.3.1
Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653
24.3.2
Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655
24.3.3
Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665
24.3.4
Capture/Compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669
24.3.5
Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671
24.3.6
PWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672
24.3.7
Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673
24.3.8
Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673
24.3.9
PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674
24.3.10 Asymmetric PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 678
24.3.11 Combined PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 678
24.3.12 Clearing the OCxREF signal on an external event . . . . . . . . . . . . . . . 679
24.3.13 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 681
24.3.14 Retriggerable one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 682
24.3.15 Encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683
24.3.16 UIF bit remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685
24.3.17 Timer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685
24.3.18 Timers and external trigger synchronization . . . . . . . . . . . . . . . . . . . . 686
24.3.19 Timer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689
24.3.20 DMA burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694
24.3.21 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695
24.4
TIM2/TIM3 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 696
24.4.1
TIMx control register 1 (TIMx_CR1)(x = 2 to 3) . . . . . . . . . . . . . . . . . . 696
24.4.2
TIMx control register 2 (TIMx_CR2)(x = 2 to 3) . . . . . . . . . . . . . . . . . . 697
RM0503 Rev 2
21/1325
36
Contents
RM0503
24.4.3
TIMx slave mode control register (TIMx_SMCR)(x = 2 to 3) . . . . . . . . 699
24.4.4
TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 2 to 3) . . . . . . . 702
24.4.5
TIMx status register (TIMx_SR)(x = 2 to 3) . . . . . . . . . . . . . . . . . . . . . 703
24.4.6
TIMx event generation register (TIMx_EGR)(x = 2 to 3) . . . . . . . . . . . 705
24.4.7
TIMx capture/compare mode register 1 (TIMx_CCMR1)(x = 2 to 3) . . 706
24.4.8
TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)
(x = 2 to 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708
24.4.9
TIMx capture/compare mode register 2 (TIMx_CCMR2)(x = 2 to 3) . . 710
24.4.10 TIMx capture/compare mode register 2 [alternate] (TIMx_CCMR2)
(x = 2 to 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711
24.4.11 TIMx capture/compare enable register
(TIMx_CCER)(x = 2 to 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712
24.4.12 TIMx counter (TIMx_CNT)(x = 2 to 3) . . . . . . . . . . . . . . . . . . . . . . . . . 713
24.4.13 TIMx counter [alternate] (TIMx_CNT)(x = 2 to 3) . . . . . . . . . . . . . . . . . 714
24.4.14 TIMx prescaler (TIMx_PSC)(x = 2 to 3) . . . . . . . . . . . . . . . . . . . . . . . . 714
24.4.15 TIMx auto-reload register (TIMx_ARR)(x = 2 to 3) . . . . . . . . . . . . . . . 715
24.4.16 TIMx capture/compare register 1 (TIMx_CCR1)(x = 2 to 3) . . . . . . . . 715
24.4.17 TIMx capture/compare register 2 (TIMx_CCR2)(x = 2 to 3) . . . . . . . . 716
24.4.18 TIMx capture/compare register 3 (TIMx_CCR3)(x = 2 to 3) . . . . . . . . 716
24.4.19 TIMx capture/compare register 4 (TIMx_CCR4)(x = 2 to 3) . . . . . . . . 717
24.4.20 TIMx DMA control register (TIMx_DCR)(x = 2 to 3) . . . . . . . . . . . . . . . 718
24.4.21 TIMx DMA address for full transfer (TIMx_DMAR)(x = 2 to 3) . . . . . . . 718
24.4.22 TIM2 option register 1 (TIM2_OR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 718
24.4.23 TIM3 option register 1 (TIM3_OR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 719
24.4.24 TIM2 alternate function option register 1 (TIM2_AF1) . . . . . . . . . . . . . 719
24.4.25 TIM3 alternate function option register 1 (TIM3_AF1) . . . . . . . . . . . . . 720
24.4.26 TIM2 timer input selection register (TIM2_TISEL) . . . . . . . . . . . . . . . . 720
24.4.27 TIM3 timer input selection register (TIM3_TISEL) . . . . . . . . . . . . . . . . 721
24.4.28 TIMx register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723
25
22/1325
Basic timers (TIM6/TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726
25.1
TIM6/TIM7 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726
25.2
TIM6/TIM7 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726
25.3
TIM6/TIM7 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 727
25.3.1
Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 727
25.3.2
Counting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 729
25.3.3
UIF bit remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732
25.3.4
Clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732
RM0503 Rev 2
RM0503
Contents
25.3.5
25.4
26
Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 733
TIM6/TIM7 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 733
25.4.1
TIMx control register 1 (TIMx_CR1)(x = 6 to 7) . . . . . . . . . . . . . . . . . . 733
25.4.2
TIMx control register 2 (TIMx_CR2)(x = 6 to 7) . . . . . . . . . . . . . . . . . . 735
25.4.3
TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 6 to 7) . . . . . . . 735
25.4.4
TIMx status register (TIMx_SR)(x = 6 to 7) . . . . . . . . . . . . . . . . . . . . . 736
25.4.5
TIMx event generation register (TIMx_EGR)(x = 6 to 7) . . . . . . . . . . . 736
25.4.6
TIMx counter (TIMx_CNT)(x = 6 to 7) . . . . . . . . . . . . . . . . . . . . . . . . . 736
25.4.7
TIMx prescaler (TIMx_PSC)(x = 6 to 7) . . . . . . . . . . . . . . . . . . . . . . . . 737
25.4.8
TIMx auto-reload register (TIMx_ARR)(x = 6 to 7) . . . . . . . . . . . . . . . 737
25.4.9
TIMx register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738
General-purpose timers (TIM15/TIM16) . . . . . . . . . . . . . . . . . . . . . . . . 739
26.1
TIM15/TIM16 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739
26.2
TIM15 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739
26.3
TIM16 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 740
26.4
TIM15/TIM16 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743
26.4.1
Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743
26.4.2
Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745
26.4.3
Repetition counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749
26.4.4
Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750
26.4.5
Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752
26.4.6
Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 754
26.4.7
PWM input mode (only for TIM15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755
26.4.8
Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 756
26.4.9
Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 757
26.4.10 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758
26.4.11 Combined PWM mode (TIM15 only) . . . . . . . . . . . . . . . . . . . . . . . . . . 759
26.4.12 Complementary outputs and dead-time insertion . . . . . . . . . . . . . . . . 760
26.4.13 Using the break function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762
26.4.14 Bidirectional break inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767
26.4.15 6-step PWM generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 768
26.4.16 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770
26.4.17 Retriggerable one pulse mode (TIM15 only) . . . . . . . . . . . . . . . . . . . . 771
26.4.18 UIF bit remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 772
26.4.19 Timer input XOR function (TIM15 only) . . . . . . . . . . . . . . . . . . . . . . . . 773
26.4.20 External trigger synchronization (TIM15 only) . . . . . . . . . . . . . . . . . . . 774
RM0503 Rev 2
23/1325
36
Contents
RM0503
26.4.21 Slave mode – combined reset + trigger mode . . . . . . . . . . . . . . . . . . . 776
26.4.22 DMA burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776
26.4.23 Timer synchronization (TIM15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778
26.4.24 Using timer output as trigger for other timers (TIM16) . . . . . . . . . . . . . 778
26.4.25 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778
26.5
TIM15 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779
26.5.1
TIM15 control register 1 (TIM15_CR1) . . . . . . . . . . . . . . . . . . . . . . . . 779
26.5.2
TIM15 control register 2 (TIM15_CR2) . . . . . . . . . . . . . . . . . . . . . . . . 780
26.5.3
TIM15 slave mode control register (TIM15_SMCR) . . . . . . . . . . . . . . 782
26.5.4
TIM15 DMA/interrupt enable register (TIM15_DIER) . . . . . . . . . . . . . 783
26.5.5
TIM15 status register (TIM15_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 784
26.5.6
TIM15 event generation register (TIM15_EGR) . . . . . . . . . . . . . . . . . 786
26.5.7
TIM15 capture/compare mode register 1 (TIM15_CCMR1) . . . . . . . . 787
26.5.8
TIM15 capture/compare mode register 1 [alternate]
(TIM15_CCMR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 788
26.5.9
TIM15 capture/compare enable register (TIM15_CCER) . . . . . . . . . . 791
26.5.10 TIM15 counter (TIM15_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 794
26.5.11 TIM15 prescaler (TIM15_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 794
26.5.12 TIM15 auto-reload register (TIM15_ARR) . . . . . . . . . . . . . . . . . . . . . . 794
26.5.13 TIM15 repetition counter register (TIM15_RCR) . . . . . . . . . . . . . . . . . 795
26.5.14 TIM15 capture/compare register 1 (TIM15_CCR1) . . . . . . . . . . . . . . . 795
26.5.15 TIM15 capture/compare register 2 (TIM15_CCR2) . . . . . . . . . . . . . . . 796
26.5.16 TIM15 break and dead-time register (TIM15_BDTR) . . . . . . . . . . . . . 796
26.5.17 TIM15 DMA control register (TIM15_DCR) . . . . . . . . . . . . . . . . . . . . . 799
26.5.18 TIM15 DMA address for full transfer (TIM15_DMAR) . . . . . . . . . . . . . 799
26.5.19 TIM15 alternate register 1 (TIM15_AF1) . . . . . . . . . . . . . . . . . . . . . . . 800
26.5.20 TIM15 input selection register (TIM15_TISEL) . . . . . . . . . . . . . . . . . . 801
26.5.21 TIM15 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 802
26.6
24/1325
TIM16 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804
26.6.1
TIM16 control register 1 (TIM16_CR1) . . . . . . . . . . . . . . . . . . . . . . . . 804
26.6.2
TIM16 control register 2 (TIM16_CR2) . . . . . . . . . . . . . . . . . . . . . . . . 805
26.6.3
TIM16 DMA/interrupt enable register (TIM16_DIER) . . . . . . . . . . . . . 806
26.6.4
TIM16 status register (TIM16_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 807
26.6.5
TIM16 event generation register (TIM16_EGR) . . . . . . . . . . . . . . . . . 808
26.6.6
TIM16 capture/compare mode register 1 (TIM16_CCMR1) . . . . . . . . 809
26.6.7
TIM16 capture/compare mode register 1 [alternate] (TIM16_CCMR1) 810
26.6.8
TIM16 capture/compare enable register (TIM16_CCER) . . . . . . . . . . 812
RM0503 Rev 2
RM0503
Contents
26.6.9
TIM16 counter (TIM16_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814
26.6.10 TIM16 prescaler (TIM16_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 815
26.6.11 TIM16 auto-reload register (TIM16_ARR) . . . . . . . . . . . . . . . . . . . . . . 815
26.6.12 TIM16 repetition counter register (TIM16_RCR) . . . . . . . . . . . . . . . . . 816
26.6.13 TIM16 capture/compare register 1 (TIM16_CCR1) . . . . . . . . . . . . . . . 816
26.6.14 TIM16 break and dead-time register (TIM16_BDTR) . . . . . . . . . . . . . 817
26.6.15 TIM16 DMA control register (TIM16_DCR) . . . . . . . . . . . . . . . . . . . . . 820
26.6.16 TIM16 DMA address for full transfer (TIM16_DMAR) . . . . . . . . . . . . . 820
26.6.17 TIM16 alternate function register 1 (TIM16_AF1) . . . . . . . . . . . . . . . . 821
26.6.18 TIM16 input selection register (TIM16_TISEL) . . . . . . . . . . . . . . . . . . 822
26.6.19 TIM16 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 823
27
Low-power timer (LPTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825
27.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825
27.2
LPTIM main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825
27.3
LPTIM implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826
27.4
LPTIM functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 827
27.4.1
LPTIM block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 827
27.4.2
LPTIM pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 827
27.4.3
LPTIM input and trigger mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829
27.4.4
LPTIM reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 830
27.4.5
Glitch filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 831
27.4.6
Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 831
27.4.7
Trigger multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 832
27.4.8
Operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 832
27.4.9
Timeout function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 834
27.4.10 Waveform generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 834
27.4.11 Register update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 836
27.4.12 Counter mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 836
27.4.13 Timer enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 837
27.4.14 Timer counter reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 837
27.4.15 Encoder mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 838
27.4.16 Repetition Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 839
27.4.17 Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 841
27.4.18 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 841
27.4.19 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 843
27.4.20 DMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 845
RM0503 Rev 2
25/1325
36
Contents
RM0503
27.4.21 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846
27.5
LPTIM low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846
27.6
LPTIM interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846
27.7
LPTIM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 847
27.7.1
LPTIMx interrupt and status register [alternate] (LPTIMx_ISR)
(x = 1 to 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 848
27.7.2
LPTIMx interrupt and status register [alternate] (LPTIMx_ISR)
(x = 1 to 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 850
27.7.3
LPTIMx interrupt clear register [alternate] (LPTIMx_ICR)
(x = 1 to 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 853
27.7.4
LPTIMx interrupt clear register [alternate] (LPTIMx_ICR)
(x = 1 to 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 855
27.7.5
LPTIMx interrupt enable register [alternate] (LPTIMx_DIER)
(x = 1 to 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 856
27.7.6
LPTIMx interrupt enable register [alternate] (LPTIMx_DIER)
(x = 1 to 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 858
27.7.7
LPTIM configuration register (LPTIM_CFGR) . . . . . . . . . . . . . . . . . . . 860
27.7.8
LPTIM control register (LPTIM_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . 863
27.7.9
LPTIM compare register 1 (LPTIM_CCR1) . . . . . . . . . . . . . . . . . . . . . 864
27.7.10 LPTIM autoreload register (LPTIM_ARR) . . . . . . . . . . . . . . . . . . . . . . 865
27.7.11 LPTIM counter register (LPTIM_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . 865
27.7.12 LPTIM configuration register 2 (LPTIM_CFGR2) . . . . . . . . . . . . . . . . 865
27.7.13 LPTIM repetition register (LPTIM_RCR) . . . . . . . . . . . . . . . . . . . . . . . 867
27.7.14 LPTIM capture/compare mode register 1 (LPTIM_CCMR1) . . . . . . . . 867
27.7.15 LPTIM capture/compare mode register 2 (LPTIM_CCMR2) . . . . . . . . 870
27.7.16 LPTIM compare register 2 (LPTIM_CCR2) . . . . . . . . . . . . . . . . . . . . . 872
27.7.17 LPTIM compare register 3 (LPTIM_CCR3) . . . . . . . . . . . . . . . . . . . . . 873
27.7.18 LPTIM compare register 4 (LPTIM_CCR4) . . . . . . . . . . . . . . . . . . . . . 874
27.7.19 LPTIM register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 874
28
26/1325
Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 877
28.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 877
28.2
IWDG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 877
28.3
IWDG implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 877
28.4
IWDG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 878
28.4.1
IWDG block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 878
28.4.2
IWDG internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 879
28.4.3
Software and hardware watchdog modes . . . . . . . . . . . . . . . . . . . . . . 879
RM0503 Rev 2
RM0503
29
30
Contents
28.4.4
Window option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 880
28.4.5
Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 883
28.4.6
Register access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 883
28.5
IWDG low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 883
28.6
IWDG interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 884
28.7
IWDG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 886
28.7.1
IWDG key register (IWDG_KR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 887
28.7.2
IWDG prescaler register (IWDG_PR) . . . . . . . . . . . . . . . . . . . . . . . . . 887
28.7.3
IWDG reload register (IWDG_RLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 888
28.7.4
IWDG status register (IWDG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 888
28.7.5
IWDG window register (IWDG_WINR) . . . . . . . . . . . . . . . . . . . . . . . . 890
28.7.6
IWDG early wake-up interrupt register (IWDG_EWCR) . . . . . . . . . . . 890
28.7.7
IWDG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 892
System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . 893
29.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 893
29.2
WWDG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 893
29.3
WWDG implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 893
29.4
WWDG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 894
29.4.1
WWDG block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 894
29.4.2
WWDG internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 894
29.4.3
Enabling the watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 895
29.4.4
Controlling the down-counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 895
29.4.5
How to program the watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . . 895
29.4.6
Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 896
29.5
WWDG interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 897
29.6
WWDG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 897
29.6.1
WWDG control register (WWDG_CR) . . . . . . . . . . . . . . . . . . . . . . . . . 897
29.6.2
WWDG configuration register (WWDG_CFR) . . . . . . . . . . . . . . . . . . . 898
29.6.3
WWDG status register (WWDG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . 898
29.6.4
WWDG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 899
Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900
30.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900
30.2
RTC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900
30.3
RTC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900
RM0503 Rev 2
27/1325
36
Contents
RM0503
30.3.1
RTC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900
30.3.2
RTC pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 902
30.3.3
GPIOs controlled by the RTC and TAMP . . . . . . . . . . . . . . . . . . . . . . . 903
30.3.4
Clock and prescalers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 905
30.3.5
Real-time clock and calendar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 906
30.3.6
Calendar ultra-low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 906
30.3.7
Programmable alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 907
30.3.8
Periodic auto-wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 907
30.3.9
RTC initialization and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 908
30.3.10 Reading the calendar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 911
30.3.11 Resetting the RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 912
30.3.12 RTC synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 912
30.3.13 RTC reference clock detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 912
30.3.14 RTC smooth digital calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 913
30.3.15 Timestamp function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 915
30.3.16 Calibration clock output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 916
30.3.17 Tamper and alarm output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 917
30.4
RTC low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 917
30.5
RTC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 918
30.6
RTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 918
30.6.1
RTC time register (RTC_TR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 919
30.6.2
RTC date register (RTC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 920
30.6.3
RTC subsecond register (RTC_SSR) . . . . . . . . . . . . . . . . . . . . . . . . . 921
30.6.4
RTC initialization control and status register (RTC_ICSR) . . . . . . . . . 921
30.6.5
RTC prescaler register (RTC_PRER) . . . . . . . . . . . . . . . . . . . . . . . . . 923
30.6.6
RTC wake-up timer register (RTC_WUTR) . . . . . . . . . . . . . . . . . . . . . 924
30.6.7
RTC control register (RTC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 924
30.6.8
RTC write protection register (RTC_WPR) . . . . . . . . . . . . . . . . . . . . . 928
30.6.9
RTC calibration register (RTC_CALR) . . . . . . . . . . . . . . . . . . . . . . . . . 928
30.6.10 RTC shift control register (RTC_SHIFTR) . . . . . . . . . . . . . . . . . . . . . . 929
30.6.11 RTC timestamp time register (RTC_TSTR) . . . . . . . . . . . . . . . . . . . . . 930
30.6.12 RTC timestamp date register (RTC_TSDR) . . . . . . . . . . . . . . . . . . . . 931
30.6.13 RTC timestamp subsecond register (RTC_TSSSR) . . . . . . . . . . . . . . 931
30.6.14 RTC alarm A register (RTC_ALRMAR) . . . . . . . . . . . . . . . . . . . . . . . . 932
30.6.15 RTC alarm A subsecond register (RTC_ALRMASSR) . . . . . . . . . . . . . 933
30.6.16 RTC alarm B register (RTC_ALRMBR) . . . . . . . . . . . . . . . . . . . . . . . . 934
30.6.17 RTC alarm B subsecond register (RTC_ALRMBSSR) . . . . . . . . . . . . 935
28/1325
RM0503 Rev 2
RM0503
Contents
30.6.18 RTC status register (RTC_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 936
30.6.19 RTC masked interrupt status register (RTC_MISR) . . . . . . . . . . . . . . 937
30.6.20 RTC status clear register (RTC_SCR) . . . . . . . . . . . . . . . . . . . . . . . . . 938
30.6.21 RTC alarm A binary mode register (RTC_ALRABINR) . . . . . . . . . . . . 939
30.6.22 RTC alarm B binary mode register (RTC_ALRBBINR) . . . . . . . . . . . . 939
30.6.23 RTC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 940
31
Tamper and backup registers (TAMP) . . . . . . . . . . . . . . . . . . . . . . . . . 942
31.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 942
31.2
TAMP main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 942
31.3
TAMP functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 943
31.3.1
TAMP block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 943
31.3.2
TAMP pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 944
31.3.3
GPIOs controlled by the RTC and TAMP . . . . . . . . . . . . . . . . . . . . . . . 945
31.3.4
TAMP register write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 945
31.3.5
Tamper detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 945
31.3.6
TAMP backup registers and other device secrets erase . . . . . . . . . . . 946
31.3.7
Tamper detection configuration and initialization . . . . . . . . . . . . . . . . . 947
31.4
TAMP low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 948
31.5
TAMP interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 949
31.6
TAMP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 949
31.6.1
TAMP control register 1 (TAMP_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . 949
31.6.2
TAMP control register 2 (TAMP_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . 951
31.6.3
TAMP control register 3 (TAMP_CR3) . . . . . . . . . . . . . . . . . . . . . . . . . 953
31.6.4
TAMP filter control register (TAMP_FLTCR) . . . . . . . . . . . . . . . . . . . . 954
31.6.5
TAMP interrupt enable register (TAMP_IER) . . . . . . . . . . . . . . . . . . . . 955
31.6.6
TAMP status register (TAMP_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 956
31.6.7
TAMP masked interrupt status register (TAMP_MISR) . . . . . . . . . . . . 957
31.6.8
TAMP status clear register (TAMP_SCR) . . . . . . . . . . . . . . . . . . . . . . 959
31.6.9
TAMP backup x register (TAMP_BKPxR) . . . . . . . . . . . . . . . . . . . . . . 960
31.6.10 TAMP register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 961
32
Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . 962
32.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 962
32.2
I2C main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 962
32.3
I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 962
RM0503 Rev 2
29/1325
36
Contents
RM0503
32.4
I2C functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 963
32.4.1
I2C block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 963
32.4.2
I2C pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 964
32.4.3
I2C clock requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 964
32.4.4
I2C mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 964
32.4.5
I2C initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 965
32.4.6
I2C reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 969
32.4.7
I2C data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 970
32.4.8
I2C slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 972
32.4.9
I2C master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 981
32.4.10 I2C_TIMINGR register configuration examples . . . . . . . . . . . . . . . . . . 992
32.4.11 Wake-up from Stop mode on address match . . . . . . . . . . . . . . . . . . . 994
32.4.12 Error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 995
32.5
I2C in low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 996
32.6
I2C interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 996
32.7
I2C DMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 997
32.8
32.7.1
Transmission using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 997
32.7.2
Reception using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 997
I2C registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 998
32.8.1
I2C control register 1 (I2C_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 998
32.8.2
I2C control register 2 (I2C_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000
32.8.3
I2C own address 1 register (I2C_OAR1) . . . . . . . . . . . . . . . . . . . . . . 1002
32.8.4
I2C own address 2 register (I2C_OAR2) . . . . . . . . . . . . . . . . . . . . . . 1003
32.8.5
I2C timing register (I2C_TIMINGR) . . . . . . . . . . . . . . . . . . . . . . . . . . 1004
32.8.6
I2C interrupt and status register (I2C_ISR) . . . . . . . . . . . . . . . . . . . . 1005
32.8.7
I2C interrupt clear register (I2C_ICR) . . . . . . . . . . . . . . . . . . . . . . . . 1007
32.8.8
I2C receive data register (I2C_RXDR) . . . . . . . . . . . . . . . . . . . . . . . 1007
32.8.9
I2C transmit data register (I2C_TXDR) . . . . . . . . . . . . . . . . . . . . . . . 1008
32.8.10 I2C register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1009
33
30/1325
Universal synchronous/asynchronous receiver
transmitter (USART/UART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1010
33.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1010
33.2
USART main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1010
33.3
USART extended features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1011
33.4
USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1011
RM0503 Rev 2
RM0503
Contents
33.5
USART functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1013
33.5.1
USART block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1013
33.5.2
USART pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1013
33.5.3
USART clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1015
33.5.4
USART character description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1015
33.5.5
USART FIFOs and thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1018
33.5.6
USART transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1018
33.5.7
USART receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1021
33.5.8
USART baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1028
33.5.9
Tolerance of the USART receiver to clock deviation . . . . . . . . . . . . . 1030
33.5.10 USART auto baud rate detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1031
33.5.11 USART multiprocessor communication . . . . . . . . . . . . . . . . . . . . . . . 1033
33.5.12 USART Modbus communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1035
33.5.13 USART parity control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1036
33.5.14 USART LIN (local interconnection network) mode . . . . . . . . . . . . . . 1037
33.5.15 USART synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1039
33.5.16 USART single-wire half-duplex communication . . . . . . . . . . . . . . . . . 1043
33.5.17 USART receiver timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1043
33.5.18 USART smartcard mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1044
33.5.19 USART IrDA SIR ENDEC block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1048
33.5.20 Continuous communication using USART and DMA . . . . . . . . . . . . . 1051
33.5.21 RS232 hardware flow control and RS485 driver enable . . . . . . . . . . 1053
33.5.22 USART low-power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1056
33.6
USART in low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1059
33.7
USART interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1059
33.8
USART registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1062
33.8.1
USART control register 1 (USART_CR1) . . . . . . . . . . . . . . . . . . . . . 1062
33.8.2
USART control register 1 [alternate] (USART_CR1) . . . . . . . . . . . . . 1066
33.8.3
USART control register 2 (USART_CR2) . . . . . . . . . . . . . . . . . . . . . 1069
33.8.4
USART control register 3 (USART_CR3) . . . . . . . . . . . . . . . . . . . . . 1073
33.8.5
USART control register 3 [alternate] (USART_CR3) . . . . . . . . . . . . . 1078
33.8.6
USART baud rate register (USART_BRR) . . . . . . . . . . . . . . . . . . . . 1081
33.8.7
USART guard time and prescaler register (USART_GTPR) . . . . . . . 1082
33.8.8
USART receiver timeout register (USART_RTOR) . . . . . . . . . . . . . . 1083
33.8.9
USART request register (USART_RQR) . . . . . . . . . . . . . . . . . . . . . . 1084
33.8.10 USART interrupt and status register (USART_ISR) . . . . . . . . . . . . . 1085
33.8.11 USART interrupt and status register [alternate] (USART_ISR) . . . . . 1091
RM0503 Rev 2
31/1325
36
Contents
RM0503
33.8.12 USART interrupt flag clear register (USART_ICR) . . . . . . . . . . . . . . 1096
33.8.13 USART receive data register (USART_RDR) . . . . . . . . . . . . . . . . . . 1098
33.8.14 USART transmit data register (USART_TDR) . . . . . . . . . . . . . . . . . . 1098
33.8.15 USART prescaler register (USART_PRESC) . . . . . . . . . . . . . . . . . . 1099
33.8.16 USART register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1100
34
Low-power universal asynchronous receiver
transmitter (LPUART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1102
34.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1102
34.2
LPUART main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1102
34.3
LPUART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1103
34.4
LPUART functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1105
34.4.1
LPUART block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1105
34.4.2
LPUART pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 1106
34.4.3
LPUART clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1107
34.4.4
LPUART character description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1107
34.4.5
LPUART FIFOs and thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1109
34.4.6
LPUART transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1109
34.4.7
LPUART receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1113
34.4.8
LPUART baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1117
34.4.9
Tolerance of the LPUART receiver to clock deviation . . . . . . . . . . . . 1119
34.4.10 LPUART multiprocessor communication . . . . . . . . . . . . . . . . . . . . . . 1120
34.4.11 LPUART parity control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1122
34.4.12 LPUART single-wire half-duplex communication . . . . . . . . . . . . . . . . 1123
34.4.13 Continuous communication using DMA and LPUART . . . . . . . . . . . . 1123
34.4.14 RS232 hardware flow control and RS485 driver enable . . . . . . . . . . 1126
34.4.15 LPUART low-power management . . . . . . . . . . . . . . . . . . . . . . . . . . . 1128
32/1325
34.5
LPUART in low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1131
34.6
LPUART interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1132
34.7
LPUART registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1133
34.7.1
LPUART control register 1 (LPUART_CR1) . . . . . . . . . . . . . . . . . . . 1133
34.7.2
LPUART control register 1 [alternate] (LPUART_CR1) . . . . . . . . . . . 1136
34.7.3
LPUART control register 2 (LPUART_CR2) . . . . . . . . . . . . . . . . . . . 1139
34.7.4
LPUART control register 3 (LPUART_CR3) . . . . . . . . . . . . . . . . . . . 1141
34.7.5
LPUART control register 3 [alternate] (LPUART_CR3) . . . . . . . . . . . 1144
34.7.6
LPUART baud rate register (LPUART_BRR) . . . . . . . . . . . . . . . . . . 1147
RM0503 Rev 2
RM0503
Contents
34.7.7
LPUART request register (LPUART_RQR) . . . . . . . . . . . . . . . . . . . . 1147
34.7.8
LPUART interrupt and status register (LPUART_ISR) . . . . . . . . . . . 1148
34.7.9
LPUART interrupt and status register [alternate] (LPUART_ISR) . . . 1152
34.7.10 LPUART interrupt flag clear register (LPUART_ICR) . . . . . . . . . . . . 1155
34.7.11 LPUART receive data register (LPUART_RDR) . . . . . . . . . . . . . . . . 1156
34.7.12 LPUART transmit data register (LPUART_TDR) . . . . . . . . . . . . . . . . 1157
34.7.13 LPUART prescaler register (LPUART_PRESC) . . . . . . . . . . . . . . . . 1157
34.7.14 LPUART register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1158
35
Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1160
35.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1160
35.2
SPI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1160
35.3
SPI implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1161
35.4
SPI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1161
35.4.1
General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1161
35.4.2
Communications between one master and one slave . . . . . . . . . . . . 1162
35.4.3
Standard multislave communication . . . . . . . . . . . . . . . . . . . . . . . . . 1164
35.4.4
Multimaster communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1165
35.4.5
Slave select (NSS) pin management . . . . . . . . . . . . . . . . . . . . . . . . . 1166
35.4.6
Communication formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1167
35.4.7
Configuration of SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1169
35.4.8
Procedure for enabling SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1170
35.4.9
Data transmission and reception procedures . . . . . . . . . . . . . . . . . . 1170
35.4.10 SPI status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1180
35.4.11 SPI error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1181
35.4.12 NSS pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1182
35.4.13 TI mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1182
35.4.14 CRC calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1183
35.5
SPI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1185
35.6
SPI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1186
35.6.1
SPI control register 1 (SPIx_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1186
35.6.2
SPI control register 2 (SPIx_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1188
35.6.3
SPI status register (SPIx_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1190
35.6.4
SPI data register (SPIx_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1191
35.6.5
SPI CRC polynomial register (SPIx_CRCPR) . . . . . . . . . . . . . . . . . . 1192
35.6.6
SPI Rx CRC register (SPIx_RXCRCR) . . . . . . . . . . . . . . . . . . . . . . . 1192
RM0503 Rev 2
33/1325
36
Contents
36
RM0503
35.6.8
SPI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1194
36.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1195
36.2
USB main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1195
36.3
USB implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1195
36.4
USB functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1196
36.6
34/1325
SPI Tx CRC register (SPIx_TXCRCR) . . . . . . . . . . . . . . . . . . . . . . . 1192
Universal serial bus full-speed device interface (USB) . . . . . . . . . . 1195
36.5
37
35.6.7
36.4.1
USB block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1196
36.4.2
USB pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1197
36.4.3
USB reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1197
36.4.4
General description and Device mode functionality . . . . . . . . . . . . . . 1197
36.4.5
Description of USB blocks used in both Device and Host modes . . . 1198
36.4.6
Description of host frame scheduler (HFS) specific to Host mode . . 1199
Programming considerations for Device and Host modes . . . . . . . . . . 1200
36.5.1
Generic USB Device programming . . . . . . . . . . . . . . . . . . . . . . . . . . 1200
36.5.2
System and power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1201
36.5.3
Double-buffered endpoints and usage in Device mode . . . . . . . . . . . 1208
36.5.4
Double buffered channels: usage in Host mode . . . . . . . . . . . . . . . . 1210
36.5.5
Isochronous transfers in Device mode . . . . . . . . . . . . . . . . . . . . . . . 1211
36.5.6
Isochronous transfers in Host mode . . . . . . . . . . . . . . . . . . . . . . . . . 1212
36.5.7
Suspend/resume events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1213
USB and USB SRAM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1217
36.6.1
Common registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1217
36.6.2
USBSRAM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1236
36.6.3
USB register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1240
Debug support (DBG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1242
37.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1242
37.2
DBG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1242
37.2.1
DBG block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1242
37.2.2
DBG pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1243
37.2.3
ID codes and locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . 1243
37.2.4
DBG reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1243
37.2.5
DBG power domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1244
37.2.6
Debug in low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1244
RM0503 Rev 2
RM0503
Contents
37.2.7
37.3
37.4
37.5
37.6
37.7
37.8
37.9
Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1244
Serial-wire debug port (SW-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1245
37.3.1
Serial-wire debug port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1245
37.3.2
Debug port registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1246
37.3.3
DEBUG port registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1247
37.3.4
Debug port register map and reset values . . . . . . . . . . . . . . . . . . . . . 1253
Access ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1254
37.4.1
Access port registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1254
37.4.2
Access port register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1260
ROM tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1262
37.5.1
System ROM table registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1264
37.5.2
System ROM table register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1268
37.5.3
MCU ROM table registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1269
37.5.4
MCU ROM table register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1273
37.5.5
Processor ROM table registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1274
37.5.6
Processor ROM table register map . . . . . . . . . . . . . . . . . . . . . . . . . . 1278
Data watchpoint and trace unit (DWT) . . . . . . . . . . . . . . . . . . . . . . . . . 1279
37.6.1
DWT registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1279
37.6.2
DWT register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1285
Breakpoint unit (BPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1287
37.7.1
BPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1287
37.7.2
BPU register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1292
System control space (SCS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1293
37.8.1
SCS registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1293
37.8.2
SCS register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1298
Microcontroller debug unit (DBGMCU) . . . . . . . . . . . . . . . . . . . . . . . . . 1299
37.9.1
Device ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1299
37.9.2
Low-power mode emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1299
37.9.3
Peripheral clock freeze . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1300
37.9.4
DBGMCU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1301
37.9.5
DBGMCU register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1310
37.10 Reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1312
38
Device electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1313
38.1
Unique device ID register (96 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1313
38.2
Flash memory size data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1314
RM0503 Rev 2
35/1325
36
Contents
RM0503
38.3
Package data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1314
Appendix A OEM key CRC calculation source code . . . . . . . . . . . . . . . . . . . . 1316
36/1325
RM0503 Rev 2
RM0503
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Table 49.
Peripherals versus products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
STM32U073xx and STM32U083xx memory boundary addresses. . . . . . . . . . . . . . . . . . . 57
STM32U031xx memory boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
STM32U0 series peripheral register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . 58
SRAM size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Boot modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Flash memory organization: information block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Flash memory organization: main memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Number of wait states according to flash memory clock (HCLK) frequency . . . . . . . . . . . . 67
Page erase overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Mass erase overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Option byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Organization of option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Flash memory read protection status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Access status versus protection level and execution modes . . . . . . . . . . . . . . . . . . . . . . . 81
HDP extension protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
FLASH interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
FLASH register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
PVM features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Low-power mode summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Functionalities depending on the working mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Low-power run . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Sleep. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Low-power sleep. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Stop 0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Stop 2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
PWR register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Clock source frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
RCC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
CRS features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
CRS internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Effect of low-power modes on CRS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
CRS register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Port bit configuration table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
GPIO register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
SYSCFG register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
DMA implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
DMA internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
Programmable data width and endian behavior (when PINC = MINC = 1) . . . . . . . . . . . 272
DMA interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
DMA register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
DMAMUX instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
DMAMUX: assignment of multiplexer inputs to resources . . . . . . . . . . . . . . . . . . . . . . . . 287
DMAMUX: assignment of trigger inputs to resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
RM0503 Rev 2
37/1325
42
List of tables
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Table 83.
Table 84.
Table 85.
Table 86.
Table 87.
Table 88.
Table 89.
Table 90.
Table 91.
Table 92.
Table 93.
Table 94.
Table 95.
Table 96.
Table 97.
Table 98.
Table 99.
Table 100.
Table 101.
38/1325
RM0503
DMAMUX: assignment of synchronization inputs to resources . . . . . . . . . . . . . . . . . . . . 288
DMAMUX signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
DMAMUX interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
DMAMUX register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
Vector table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
EXTI signal overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
EVG pin overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
EXTI event input configurations and register control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
EXTI line connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
Masking functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
EXTI register map sections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
EXTI controller register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
CRC internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
CRC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
ADC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
ADC input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
ADC internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
External triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
Latency between trigger and start of conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
Configuring the trigger polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
tSAR timings depending on resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
Analog watchdog comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
Analog watchdog 1 channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
Maximum output results vs N and M. Grayed values indicates truncation . . . . . . . . . . . . 357
ADC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
ADC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
DAC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
DAC input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
DAC internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
DAC interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
Sample and refresh timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394
Channel output modes summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395
Effect of low-power modes on DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
DAC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
DAC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408
VREF buffer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
VREFBUF register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412
COMP internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
COMP1 noninverting input assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
COMP1 inverting input assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
COMP2 noninverting input assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
COMP2 inverting input assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
Comparator behavior in the low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
Interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419
COMP register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424
Operational amplifier possible connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426
Operating modes and calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431
Effect of low-power modes on the OPAMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432
OPAMP register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435
Example of frame rate calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
Blink frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447
LCD interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452
RM0503 Rev 2
RM0503
Table 102.
Table 103.
Table 104.
Table 105.
Table 106.
Table 107.
Table 108.
Table 109.
Table 110.
Table 111.
Table 112.
Table 113.
Table 114.
Table 115.
Table 116.
Table 117.
Table 118.
Table 119.
Table 120.
Table 121.
Table 122.
Table 123.
Table 124.
Table 125.
Table 126.
Table 127.
Table 128.
Table 129.
Table 130.
Table 131.
Table 132.
Table 133.
Table 134.
Table 135.
Table 136.
Table 137.
Table 138.
Table 139.
Table 140.
Table 141.
Table 142.
Table 143.
Table 144.
Table 145.
Table 146.
Table 147.
Table 148.
Table 149.
Table 150.
Table 151.
List of tables
LCD register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459
TSC implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463
Acquisition sequence summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466
Spread spectrum deviation versus AHB clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . 468
I/O state depending on its mode and IODEF bit value . . . . . . . . . . . . . . . . . . . . . . . . . . . 469
Effect of low-power modes on TSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471
Interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474
TSC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482
RNG internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485
RNG interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493
RNG initialization times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494
RNG configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495
Configuration selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495
RNG register map and reset map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501
AES internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503
CTR mode initialization vector definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519
GCM last block definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521
Initialization of AES_IVRx registers in GCM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522
Initialization of AES_IVRx registers in CCM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529
Key endianness in AES_KEYRx registers (128- or 256-bit key length) . . . . . . . . . . . . . . 534
AES interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537
Processing latency for ECB, CBC and CTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537
Processing latency for GCM and CCM (in clock cycles). . . . . . . . . . . . . . . . . . . . . . . . . . 538
AES register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548
Behavior of timer outputs versus BRK/BRK2 inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592
Break protection disarming conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594
Counting direction versus encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600
TIM1 internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617
Output control bits for complementary OCx and OCxN channels with break feature . . . . 631
TIM1 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648
Counting direction versus encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684
TIMx internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702
Output control bit for standard OCx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713
TIM2/TIM3 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723
TIMx register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738
Break protection disarming conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767
TIMx Internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 783
Output control bits for complementary OCx and OCxN channels with break feature
(TIM15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793
TIM15 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 802
Output control bits for complementary OCx and OCxN channels with break feature
(TIM16/17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814
TIM16 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 823
STM32U0 series LPTIM features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826
LPTIM1/2/3 input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 827
LPTIM1/2/3 internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 828
LPTIM1/2/3 external trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829
LPTIM1/2/3 input 1 connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829
LPTIM1/2/3 input 2 connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829
LPTIM1/2/3 input capture 1 connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829
LPTIM1 input capture 2 connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 830
LPTIM2 input capture 2 connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 830
RM0503 Rev 2
39/1325
42
List of tables
Table 152.
Table 153.
Table 154.
Table 155.
Table 156.
Table 157.
Table 158.
Table 159.
Table 160.
Table 161.
Table 162.
Table 163.
Table 164.
Table 165.
Table 166.
Table 167.
Table 168.
Table 169.
Table 170.
Table 171.
Table 172.
Table 173.
Table 174.
Table 175.
Table 176.
Table 177.
Table 178.
Table 179.
Table 180.
Table 181.
Table 182.
Table 183.
Table 184.
Table 185.
Table 186.
Table 187.
Table 188.
Table 189.
Table 190.
Table 191.
Table 192.
Table 193.
Table 194.
Table 195.
Table 196.
Table 197.
Table 198.
Table 199.
Table 200.
Table 201.
Table 202.
Table 203.
40/1325
RM0503
LPTIM3 input capture 2 connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 830
Prescaler division ratios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 831
Encoder counting scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 838
Input capture Glitch filter latency (in counter step unit). . . . . . . . . . . . . . . . . . . . . . . . . . . 842
Effect of low-power modes on the LPTIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846
Interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 847
LPTIM register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 874
IWDG features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 877
IWDG internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 879
Effect of low power modes on IWDG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 884
IWDG interrupt request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 886
IWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 892
WWDG features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 893
WWDG internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 894
WWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 899
RTC input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 902
RTC internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 902
RTC interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 903
RTC pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 903
RTC_OUT mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 904
Effect of low-power modes on RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 917
RTC pins functionality over modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 917
Interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 918
RTC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 940
TAMP input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 944
TAMP internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 944
TAMP interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 945
Effect of low-power modes on TAMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 948
TAMP pins functionality over modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 948
Interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 949
TAMP register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 961
I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 962
I2C input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 964
I2C internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 964
Comparison of analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 966
I²C-bus specification data setup and hold times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 968
I2C configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 972
I²C-bus specification clock timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 983
Timing settings for fI2CCLK of 8 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 993
Timing settings for fI2CCLK of 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 993
Timing settings for fI2CCLK of 48 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 994
Effect of low-power modes to I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 996
I2C interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 996
I2C register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1009
Instance implementation on STM32U0 series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1011
USART/LPUART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1012
USART/UART input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1014
USART internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1015
Noise detection from sampled data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1027
Tolerance of the USART receiver when BRR [3:0] = 0000. . . . . . . . . . . . . . . . . . . . . . . 1031
Tolerance of the USART receiver when BRR[3:0] is different from 0000 . . . . . . . . . . . . 1031
USART frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1036
RM0503 Rev 2
RM0503
Table 204.
Table 205.
Table 206.
Table 207.
Table 208.
Table 209.
Table 210.
Table 211.
Table 212.
Table 213.
Table 215.
Table 216.
Table 217.
Table 218.
Table 219.
Table 220.
Table 221.
Table 222.
Table 223.
Table 224.
Table 225.
Table 226.
Table 227.
Table 228.
Table 229.
Table 230.
Table 231.
Table 232.
Table 233.
Table 234.
Table 235.
Table 236.
Table 237.
Table 238.
Table 239.
Table 240.
Table 241.
Table 242.
Table 243.
Table 244.
Table 245.
Table 246.
Table 247.
Table 248.
Table 249.
Table 250.
Table 251.
Table 252.
Table 253.
Table 254.
Table 255.
Table 256.
List of tables
Effect of low-power modes on the USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1059
USART interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1060
USART register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1100
Instance implementation on STM32U0 series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1103
USART/LPUART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1104
LPUART input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1106
LPUART internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1106
Error calculation for programmed baud rates at lpuart_ker_ck_pres= 32.768 kHz . . . . 1117
Error calculation for programmed baud rates at fCK = 100 MHz . . . . . . . . . . . . . . . . . . 1118
Tolerance of the LPUART receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1119
Effect of low-power modes on the LPUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1131
LPUART interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1132
LPUART register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1158
STM32U0 series SPI implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1161
SPI interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1185
SPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1194
STM32U073/83 USB implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1195
USB input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1197
Double-buffering buffer flag definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1209
Bulk double-buffering memory buffers usage (Device mode). . . . . . . . . . . . . . . . . . . . . 1209
Bulk double-buffering memory buffers usage (Host mode) . . . . . . . . . . . . . . . . . . . . . . 1211
Isochronous memory buffers usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1212
Isochronous memory buffers usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1213
Resume event detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1215
Resume event detection for host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1216
Reception status encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1234
Endpoint/channel type encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1234
Endpoint/channel kind meaning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1234
Transmission status encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1234
Definition of allocated buffer memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1238
USB register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1240
SW debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1243
Authentication signal states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1245
Life cycle state and debug states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1245
Packet request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1246
ACK response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1246
Data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1246
Debug port registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1247
Debug port register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1253
MEM-AP registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1254
Access port register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1260
System ROM table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1262
MCU ROM table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1262
Processor ROM table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1263
System ROM table register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1268
MCU ROM table register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1273
CPU ROM table register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1278
DWT register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1285
BPU register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1292
SCS register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1298
Peripheral clock freeze control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1300
Peripheral behavior in debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1300
RM0503 Rev 2
41/1325
42
List of tables
RM0503
Table 257. DBGMCU register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1310
Table 258. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1318
42/1325
RM0503 Rev 2
RM0503
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Changing read protection (RDP) level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Example of HDP extension protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Example of disabling core debug access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Brown-out reset waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
PVD thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Low-power modes possible transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Simplified diagram of the reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
HSE/ LSE clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Frequency measurement with TIM16 in capture mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 166
CRS block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
CRS counter behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Basic structure of an I/O port bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Basic structure of a 5-Volt tolerant I/O port bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Input floating/pull up/pull down configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Alternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
High impedance-analog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
DMA block diagram
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
DMAMUX block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
Synchronization mode of the DMAMUX request line multiplexer channel . . . . . . . . . . . . 292
Event generation of the DMA request line multiplexer channel . . . . . . . . . . . . . . . . . . . . 292
EXTI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
Configurable event trigger logic CPU wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
Direct event trigger logic CPU wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
EXTI GPIO mux . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
CRC calculation unit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
DC calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
Calibration factor forcing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
Enabling/disabling the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334
ADC clock scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334
ADC connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
Analog-to-digital conversion time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
ADC conversion timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
Stopping an ongoing conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
Single conversions of a sequence, software trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
Continuous conversion of a sequence, software trigger . . . . . . . . . . . . . . . . . . . . . . . . . . 345
Single conversions of a sequence, hardware trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
Continuous conversions of a sequence, hardware trigger . . . . . . . . . . . . . . . . . . . . . . . . 346
Data alignment and resolution (oversampling disabled: OVSE = 0). . . . . . . . . . . . . . . . . 347
Example of overrun (OVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
Wait mode conversion (continuous mode, software trigger). . . . . . . . . . . . . . . . . . . . . . . 350
Behavior with WAIT = 0, AUTOFF = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
Behavior with WAIT = 1, AUTOFF = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
RM0503 Rev 2
43/1325
50
List of figures
Figure 49.
Figure 50.
Figure 51.
Figure 52.
Figure 53.
Figure 54.
Figure 55.
Figure 56.
Figure 57.
Figure 58.
Figure 59.
Figure 60.
Figure 61.
Figure 62.
Figure 63.
Figure 64.
Figure 65.
Figure 66.
Figure 67.
Figure 68.
Figure 69.
Figure 70.
Figure 71.
Figure 72.
Figure 73.
Figure 74.
Figure 75.
Figure 76.
Figure 77.
Figure 78.
Figure 79.
Figure 80.
Figure 81.
Figure 82.
Figure 83.
Figure 84.
Figure 85.
Figure 86.
Figure 87.
Figure 88.
Figure 89.
Figure 90.
Figure 91.
Figure 92.
Figure 93.
Figure 94.
Figure 95.
Figure 96.
Figure 97.
Figure 98.
Figure 99.
44/1325
RM0503
Analog watchdog guarded area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
ADC_AWDx_OUT signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354
ADC_AWDx_OUT signal generation (AWDx flag not cleared by software) . . . . . . . . . . . 355
ADC_AWDx_OUT signal generation (on a single channel) . . . . . . . . . . . . . . . . . . . . . . . 355
Analog watchdog threshold update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356
20-bit to 16-bit result truncation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356
Numerical example with 5-bits shift and rounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
Triggered oversampling mode (TOVS bit = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
Temperature sensor and VREFINT channel block diagram . . . . . . . . . . . . . . . . . . . . . . 360
DAC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
Data registers in single DAC channel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
Timing diagram for conversion with trigger disabled TEN = 0 . . . . . . . . . . . . . . . . . . . . . 389
DAC LFSR register calculation algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
DAC conversion (SW trigger enabled) with LFSR wave generation. . . . . . . . . . . . . . . . . 391
DAC triangle wave generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
DAC conversion (SW trigger enabled) with triangle wave generation . . . . . . . . . . . . . . . 392
DAC Sample and hold mode phase diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395
Comparator block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
Window mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
Comparator hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
Comparator output blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
Standalone mode: external gain setting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427
Follower configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428
PGA mode, internal gain setting (x2/x4/x8/x16), inverting input not used . . . . . . . . . . . . 429
PGA mode, internal gain setting (x2/x4/x8/x16), inverting input used for
filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430
LCD controller block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438
1/3 bias, 1/4 duty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440
Static duty case 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441
Static duty case 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442
1/2 duty, 1/2 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443
1/3 duty, 1/3 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444
1/4 duty, 1/3 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445
1/8 duty, 1/4 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446
LCD voltage control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448
Deadtime . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449
Flowchart example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451
TSC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464
Surface charge transfer analog I/O group structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465
Sampling capacitor voltage variation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466
Charge transfer acquisition sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467
Spread spectrum variation principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468
Surface charge transfer with comparator analog I/O group structure . . . . . . . . . . . . . . . . 472
Sensor voltage variation for both normal and comparator mode . . . . . . . . . . . . . . . . . . . 473
RNG block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485
NIST SP800-90B entropy source model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486
RNG initialization overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489
AES block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503
ECB encryption and decryption principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505
CBC encryption and decryption principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506
CTR encryption and decryption principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507
GCM encryption and authentication principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508
RM0503 Rev 2
RM0503
List of figures
Figure 100. GMAC authentication principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508
Figure 101. CCM encryption and authentication principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509
Figure 102. Example of suspend mode management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513
Figure 103. ECB encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514
Figure 104. ECB decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514
Figure 105. CBC encryption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515
Figure 106. CBC decryption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515
Figure 107. ECB/CBC encryption (Mode 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516
Figure 108. ECB/CBC decryption (Mode 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517
Figure 109. Message construction in CTR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518
Figure 110. CTR encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519
Figure 111. CTR decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519
Figure 112. Message construction in GCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521
Figure 113. GCM authenticated encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522
Figure 114. Message construction in GMAC mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526
Figure 115. GMAC authentication mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526
Figure 116. Message construction in CCM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527
Figure 117. CCM mode authenticated encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529
Figure 118. 128-bit block construction with respect to data swap . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533
Figure 119. DMA transfer of a 128-bit data block during input phase . . . . . . . . . . . . . . . . . . . . . . . . . 535
Figure 120. DMA transfer of a 128-bit data block during output phase . . . . . . . . . . . . . . . . . . . . . . . . 536
Figure 121. Advanced-control timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552
Figure 122. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 554
Figure 123. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 554
Figure 124. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556
Figure 125. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556
Figure 126. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557
Figure 127. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557
Figure 128. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . . 558
Figure 129. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . . . . . 558
Figure 130. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560
Figure 131. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560
Figure 132. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561
Figure 133. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561
Figure 134. Counter timing diagram, update event when repetition counter is not used . . . . . . . . . . . 562
Figure 135. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . . . . . . . . . . . 563
Figure 136. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564
Figure 137. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . . 564
Figure 138. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565
Figure 139. Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . . . . . . . . . 565
Figure 140. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . . . . . . . . . . 566
Figure 141. Update rate examples depending on mode and TIMx_RCR register settings . . . . . . . . . 567
Figure 142. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568
Figure 143. TIM1 ETR input circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568
Figure 144. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 569
Figure 145. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570
Figure 146. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571
Figure 147. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571
Figure 148. Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572
Figure 149. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 573
Figure 150. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573
Figure 151. Output stage of capture/compare channel (channel 1, idem ch. 2 and 3) . . . . . . . . . . . . 574
RM0503 Rev 2
45/1325
50
List of figures
RM0503
Figure 152. Output stage of capture/compare channel (channel 4). . . . . . . . . . . . . . . . . . . . . . . . . . . 574
Figure 153. Output stage of capture/compare channel (channel 5, idem ch. 6) . . . . . . . . . . . . . . . . . 575
Figure 154. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577
Figure 155. Output compare mode, toggle on OC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579
Figure 156. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580
Figure 157. Center-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581
Figure 158. Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . . . . . . . . . . . . . . . 583
Figure 159. Combined PWM mode on channel 1 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584
Figure 160. 3-phase combined PWM signals with multiple trigger pulses per period . . . . . . . . . . . . . 585
Figure 161. Complementary output with dead-time insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586
Figure 162. Dead-time waveforms with delay greater than the negative pulse . . . . . . . . . . . . . . . . . . 586
Figure 163. Dead-time waveforms with delay greater than the positive pulse. . . . . . . . . . . . . . . . . . . 587
Figure 164. Break and Break2 circuitry overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589
Figure 165. Various output behavior in response to a break event on BRK (OSSI = 1) . . . . . . . . . . . 591
Figure 166. PWM output state following BRK and BRK2 pins assertion (OSSI=1) . . . . . . . . . . . . . . . 592
Figure 167. PWM output state following BRK assertion (OSSI=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 593
Figure 168. Output redirection (BRK2 request not represented) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594
Figure 169. Clearing TIMx OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595
Figure 170. 6-step generation, COM example (OSSR=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596
Figure 171. Example of one pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597
Figure 172. Retriggerable one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599
Figure 173. Example of counter operation in encoder interface mode. . . . . . . . . . . . . . . . . . . . . . . . . 600
Figure 174. Example of encoder interface mode with TI1FP1 polarity inverted. . . . . . . . . . . . . . . . . . 601
Figure 175. Measuring time interval between edges on 3 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602
Figure 176. Example of Hall sensor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604
Figure 177. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605
Figure 178. Control circuit in Gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606
Figure 179. Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607
Figure 180. Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . 608
Figure 181. General-purpose timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652
Figure 182. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 654
Figure 183. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 654
Figure 184. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655
Figure 185. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656
Figure 186. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656
Figure 187. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657
Figure 188. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded). . . . . 657
Figure 189. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . . . . . 658
Figure 190. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659
Figure 191. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659
Figure 192. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 660
Figure 193. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 660
Figure 194. Counter timing diagram, Update event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661
Figure 195. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . . . . . . . . . . . . 662
Figure 196. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663
Figure 197. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . . 663
Figure 198. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664
Figure 199. Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . . . . . . . . . 664
Figure 200. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . . . . . . . . . . 665
Figure 201. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 666
Figure 202. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666
Figure 203. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667
46/1325
RM0503 Rev 2
RM0503
List of figures
Figure 204. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668
Figure 205. Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669
Figure 206. Capture/Compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . 669
Figure 207. Capture/Compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670
Figure 208. Output stage of Capture/Compare channel (channel 1) . . . . . . . . . . . . . . . . . . . . . . . . . . 670
Figure 209. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672
Figure 210. Output compare mode, toggle on OC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674
Figure 211. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675
Figure 212. Center-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677
Figure 213. Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . . . . . . . . . . . . . . . 678
Figure 214. Combined PWM mode on channels 1 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 679
Figure 215. Clearing TIMx OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 680
Figure 216. Example of one-pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 681
Figure 217. Retriggerable one-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683
Figure 218. Example of counter operation in encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . 684
Figure 219. Example of encoder interface mode with TI1FP1 polarity inverted . . . . . . . . . . . . . . . . . 685
Figure 220. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686
Figure 221. Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687
Figure 222. Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688
Figure 223. Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . 689
Figure 224. Master/Slave timer example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690
Figure 225. Master/slave connection example with 1 channel only timers . . . . . . . . . . . . . . . . . . . . . 690
Figure 226. Gating TIM2 with OC1REF of TIM3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691
Figure 227. Gating TIM2 with Enable of TIM3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 692
Figure 228. Triggering TIM2 with update of TIM3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693
Figure 229. Triggering TIM2 with Enable of TIM3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693
Figure 230. Triggering TIM3 and TIM2 with TIM3 TI1 input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694
Figure 231. Basic timer block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726
Figure 232. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 728
Figure 233. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 728
Figure 234. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 729
Figure 235. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 730
Figure 236. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 730
Figure 237. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731
Figure 238. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not
preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731
Figure 239. Counter timing diagram, update event when ARPE=1 (TIMx_ARR
preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732
Figure 240. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 733
Figure 241. TIM15 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741
Figure 242. TIM16 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742
Figure 243. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 744
Figure 244. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 744
Figure 245. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746
Figure 246. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746
Figure 247. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747
Figure 248. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747
Figure 249. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not
preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 748
Figure 250. Counter timing diagram, update event when ARPE=1 (TIMx_ARR
preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 748
Figure 251. Update rate examples depending on mode and TIMx_RCR register settings . . . . . . . . . 750
RM0503 Rev 2
47/1325
50
List of figures
RM0503
Figure 252. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 751
Figure 253. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751
Figure 254. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752
Figure 255. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 753
Figure 256. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753
Figure 257. Output stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 754
Figure 258. Output stage of capture/compare channel (channel 2 for TIM15) . . . . . . . . . . . . . . . . . . 754
Figure 259. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 756
Figure 260. Output compare mode, toggle on OC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758
Figure 261. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759
Figure 262. Combined PWM mode on channel 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 760
Figure 263. Complementary output with dead-time insertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 761
Figure 264. Dead-time waveforms with delay greater than the negative pulse. . . . . . . . . . . . . . . . . . 761
Figure 265. Dead-time waveforms with delay greater than the positive pulse. . . . . . . . . . . . . . . . . . . 762
Figure 266. Break circuitry overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 764
Figure 267. Output behavior in response to a break . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766
Figure 268. Output redirection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 768
Figure 269. 6-step generation, COM example (OSSR=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 769
Figure 270. Example of one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770
Figure 271. Retriggerable one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 772
Figure 272. Measuring time interval between edges on 2 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 773
Figure 273. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774
Figure 274. Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775
Figure 275. Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776
Figure 276. LPTIM1/2/3 timer block diagram(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 827
Figure 277. Glitch filter timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 831
Figure 278. LPTIM output waveform, single counting mode configuration
when repetition register content is different than zero (with PRELOAD = 1) . . . . . . . . . . 833
Figure 279. LPTIM output waveform, Single counting mode configuration
and Set-once mode activated (WAVE bit is set) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 833
Figure 280. LPTIM output waveform, Continuous counting mode configuration . . . . . . . . . . . . . . . . . 834
Figure 281. Waveform generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 835
Figure 282. Encoder mode counting sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 839
Figure 283. Continuous counting mode when repetition register LPTIM_RCR
different from zero (with PRELOAD = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 840
Figure 284. Capture/compare input stage (channel 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 841
Figure 285. Capture/compare output stage (channel 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 841
Figure 286. Edge-aligned PWM mode (PRELOAD = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 843
Figure 287. Edge-aligned PWM waveforms (ARR=8 and CCxP = 0) . . . . . . . . . . . . . . . . . . . . . . . . . 844
Figure 288. PWM mode with immediate update versus preloaded update . . . . . . . . . . . . . . . . . . . . . 845
Figure 289. Independent watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 878
Figure 290. Reset timing due to timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 880
Figure 291. Reset timing due to refresh in the not allowed area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 881
Figure 292. Example of window comparator update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 883
Figure 293. Independent watchdog interrupt timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 885
Figure 294. Example of early wake-up comparator update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 886
Figure 295. Watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 894
Figure 296. Window watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 896
Figure 297. RTC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 901
Figure 298. TAMP block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 943
Figure 299. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 963
Figure 300. I²C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 965
48/1325
RM0503 Rev 2
RM0503
List of figures
Figure 301. Setup and hold timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 967
Figure 302. I2C initialization flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 969
Figure 303. Data reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 970
Figure 304. Data transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 971
Figure 305. Slave initialization flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 974
Figure 306. Transfer sequence flow for I2C slave transmitter, NOSTRETCH = 0. . . . . . . . . . . . . . . . 976
Figure 307. Transfer sequence flow for I2C slave transmitter, NOSTRETCH = 1. . . . . . . . . . . . . . . . 977
Figure 308. Transfer bus diagrams for I2C slave transmitter (mandatory events only) . . . . . . . . . . . . 978
Figure 309. Transfer sequence flow for I2C slave receiver, NOSTRETCH = 0 . . . . . . . . . . . . . . . . . 979
Figure 310. Transfer sequence flow for I2C slave receiver, NOSTRETCH = 1 . . . . . . . . . . . . . . . . . 980
Figure 311. Transfer bus diagrams for I2C slave receiver
(mandatory events only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 980
Figure 312. Master clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 982
Figure 313. Master initialization flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 984
Figure 314. 10-bit address read access with HEAD10R = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 984
Figure 315. 10-bit address read access with HEAD10R = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 985
Figure 316. Transfer sequence flow for I2C master transmitter, N ≤ 255 bytes. . . . . . . . . . . . . . . . . . 986
Figure 317. Transfer sequence flow for I2C master transmitter, N > 255 bytes . . . . . . . . . . . . . . . . . 987
Figure 318. Transfer bus diagrams for I2C master transmitter
(mandatory events only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 988
Figure 319. Transfer sequence flow for I2C master receiver, N ≤ 255 bytes . . . . . . . . . . . . . . . . . . . 990
Figure 320. Transfer sequence flow for I2C master receiver, N > 255 bytes. . . . . . . . . . . . . . . . . . . . 991
Figure 321. Transfer bus diagrams for I2C master receiver
(mandatory events only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 992
Figure 322. USART block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1013
Figure 323. Word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1017
Figure 324. Configurable stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1019
Figure 325. TC/TXE behavior when transmitting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1021
Figure 326. Start bit detection when oversampling by 16 or 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1022
Figure 327. usart_ker_ck clock divider block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1025
Figure 328. Data sampling when oversampling by 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1026
Figure 329. Data sampling when oversampling by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1027
Figure 330. Mute mode using Idle line detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1034
Figure 331. Mute mode using address mark detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1035
Figure 332. Break detection in LIN mode (11-bit break length - LBDL bit is set) . . . . . . . . . . . . . . . . 1038
Figure 333. Break detection in LIN mode vs. Framing error detection. . . . . . . . . . . . . . . . . . . . . . . . 1039
Figure 334. USART example of synchronous master transmission. . . . . . . . . . . . . . . . . . . . . . . . . . 1040
Figure 335. USART data clock timing diagram in synchronous master mode
(M bits =00). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1040
Figure 336. USART data clock timing diagram in synchronous master mode
(M bits = 01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1041
Figure 337. USART data clock timing diagram in synchronous slave mode
(M bits =00). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1042
Figure 338. ISO 7816-3 asynchronous protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1044
Figure 339. Parity error detection using the 1.5 stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1046
Figure 340. IrDA SIR ENDEC block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1050
Figure 341. IrDA data modulation (3/16) - normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1050
Figure 342. Transmission using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1052
Figure 343. Reception using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1053
Figure 344. Hardware flow control between 2 USARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1053
Figure 345. RS232 RTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1054
Figure 346. RS232 CTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1055
RM0503 Rev 2
49/1325
50
List of figures
RM0503
Figure 347. Wake-up event verified (wake-up event = address match, FIFO disabled) . . . . . . . . . . 1058
Figure 348. Wake-up event not verified (wake-up event = address match,
FIFO disabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1058
Figure 349. LPUART block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1105
Figure 350. LPUART word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1108
Figure 351. Configurable stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1110
Figure 352. TC/TXE behavior when transmitting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1112
Figure 353. lpuart_ker_ck clock divider block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1116
Figure 354. Mute mode using Idle line detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1121
Figure 355. Mute mode using address mark detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1122
Figure 356. Transmission using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1124
Figure 357. Reception using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1125
Figure 358. Hardware flow control between two LPUARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1126
Figure 359. RS232 RTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1126
Figure 360. RS232 CTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1127
Figure 361. Wake-up event verified (wake-up event = address match,
FIFO disabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1130
Figure 362. Wake-up event not verified (wake-up event = address match,
FIFO disabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1130
Figure 363. SPI block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1161
Figure 364. Full-duplex single master/ single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1162
Figure 365. Half-duplex single master/ single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1163
Figure 366. Simplex single master/single slave application (master in transmit-only/
slave in receive-only mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1164
Figure 367. Master and three independent slaves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1165
Figure 368. Multimaster application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1166
Figure 369. Hardware/software slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1167
Figure 370. Data clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1168
Figure 371. Data alignment when data length is not equal to 8-bit or 16-bit . . . . . . . . . . . . . . . . . . . 1169
Figure 372. Packing data in FIFO for transmission and reception . . . . . . . . . . . . . . . . . . . . . . . . . . . 1173
Figure 373. Master full-duplex communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1176
Figure 374. Slave full-duplex communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1177
Figure 375. Master full-duplex communication with CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1178
Figure 376. Master full-duplex communication in packed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1179
Figure 377. NSSP pulse generation in Motorola SPI master mode . . . . . . . . . . . . . . . . . . . . . . . . . . 1182
Figure 378. TI mode transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1183
Figure 379. USB peripheral block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1196
Figure 380. Packet buffer areas with examples of buffer description table locations . . . . . . . . . . . . 1203
Figure 381. Block diagram of debug support infrastructure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1242
Figure 382. CoreSight topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1263
50/1325
RM0503 Rev 2
RM0503
Documentation conventions
1
Documentation conventions
1.1
General information
The STM32U0 series devices have an Arm®(a) Cortex®-M0+ core.
1.2
List of abbreviations for registers
The following abbreviations(b) are used in register descriptions:
read/write (rw)
Software can read and write to this bit.
read-only (r)
Software can only read this bit.
write-only (w)
Software can only write to this bit. Reading this bit returns the reset value.
read/clear write0 (rc_w0)
Software can read as well as clear this bit by writing 0. Writing 1 has no
effect on the bit value.
read/clear write1 (rc_w1)
Software can read as well as clear this bit by writing 1. Writing 0 has no
effect on the bit value.
read/clear write (rc_w)
Software can read as well as clear this bit by writing to the register. The
value written to this bit is not important.
read/clear by read (rc_r)
Software can read this bit. Reading this bit automatically clears it to 0.
Writing this bit has no effect on the bit value.
read/set by read (rs_r)
Software can read this bit. Reading this bit automatically sets it to 1.
Writing this bit has no effect on the bit value.
read/set (rs)
Software can read as well as set this bit. Writing 0 has no effect on the bit
value.
read/write once (rwo)
Software can only write once to this bit and can also read it at any time.
Only a reset can return the bit to its reset value.
toggle (t)
The software can toggle this bit by writing 1. Writing 0 has no effect.
read-only write trigger (rt_w1) Software can read this bit. Writing 1 triggers an event but has no effect on
the bit value.
Reserved (Res.)
Reserved bit, must be kept at reset value.
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
b. This is an exhaustive list of all abbreviations applicable to STMicroelectronics microcontrollers, some of
them may not be used in the current document.
RM0503 Rev 2
51/1325
52
Documentation conventions
1.3
RM0503
Glossary
This section gives a brief definition of acronyms and abbreviations used in this document:
•
1.4
Word: data of 32-bit length.
•
Half-word: data of 16-bit length.
•
Byte: data of 8-bit length.
•
SWD-DP (SWD DEBUG PORT): SWD-DP provides a 2-pin (clock and data) interface
based on the Serial Wire Debug (SWD) protocol. Please refer to the Cortex®-M0+
technical reference manual.
•
IAP (in-application programming): IAP is the ability to re-program the flash memory
of a microcontroller while the user program is running.
•
ICP (in-circuit programming): ICP is the ability to program the flash memory of a
microcontroller using the SWD protocol or the bootloader while the device is mounted
on the user application board.
•
Option bytes: product configuration bits stored in the flash memory.
•
OBL: option byte loader.
•
AHB: advanced high-performance bus.
•
APB: advanced peripheral bus.
Availability of peripherals
For availability of peripherals and their number across all devices, refer to the particular
device datasheet.
The following table shows per-product availability of peripherals that are not common to all
STM32U0 series products.
Table 1. Peripherals versus products
52/1325
Feature
STM32U031xx
STM32U073xx
STM32U083xx
AES
No
No
Yes
USB
No
Yes
Yes
HSI48/CRS
No
Yes
Yes
LCD
No
Yes
Yes
LPTIM3
No
Yes
Yes
LPUART3
No
Yes
Yes
COMP2
No
Yes
Yes
SPI3
No
Yes
Yes
I2C4
No
Yes
Yes
RM0503 Rev 2
RM0503
Memory and bus architecture
2
Memory and bus architecture
2.1
System architecture
The main system consists of:
•
Two masters:
•
–
Cortex®-M0+ core
–
General-purpose DMA
Three slaves:
–
Internal SRAM
–
Internal flash memory
–
AHB with AHB-to-APB bridge that connects all the APB peripherals
These are interconnected using a multilayer AHB bus architecture as shown in Figure 1.
Figure 1. System architecture
Flash memory
interface
Flash memory
SRAM
Arm®
Cortex®-M0+
core
System bus
DMA1/2
DMAMUX
channels 1 to 12
DMA bus
Bus matrix
AHB
AHB-to-APB
bridge
CRC
RCC
AES
RNG
EXTI
GPIO Ports
A,B,C,D,E,F
DMA requests
APB
SYSCFG,
ADC, DAC,
COMP1, COMP2
TIM1, TIM2, TIM3
TIM6, TIM7,
TIM15, TIM16
LPTIM1, LPTIM2, LPTIM3
IWDG, WWDG,
RTC, PWR,
I2C1, I2C2, I2C3, I2C4
USART1, USART2, USART3,
USART4
LPUART1, LPUART2, LPUART3
SPI1, SPI2, SPI3
USB
DBGMCU
MSv71272V2
System bus (S-bus)
This bus connects the system bus of the Cortex®-M0+ core (peripheral bus) to a bus matrix
that manages the arbitration between the core and the DMA.
DMA bus
This bus connects the AHB master interface of the DMA to the bus matrix that manages the
access of CPU and DMA to SRAM, flash memory and AHB/APB peripherals.
RM0503 Rev 2
53/1325
54
Memory and bus architecture
RM0503
Bus matrix
The bus matrix manages the access arbitration between the core system bus and the DMA
master bus. The arbitration uses a Round Robin algorithm. The bus matrix is composed of
masters (CPU, DMA) and slaves (flash memory interface, SRAM and AHB-to-APB bridge).
AHB peripherals are connected on system bus through the bus matrix to allow DMA access.
AHB-to-APB bridge (APB)
The AHB-to-APB bridge provides full synchronous connections between the AHB and the
APB bus.
Refer to Section 2.2: Memory organization for the address mapping of the peripherals
connected to this bridge.
After each device reset, all peripheral clocks are disabled (except for the SRAM and flash
memory). Before using a peripheral its clock in the RCC_AHBENR, RCC_APBENRx or
RCC_IOPENR register must first be enabled.
Note:
54/1325
When a 16- or 8-bit access is performed on an APB register, the access is transformed into
a 32-bit access: the bridge duplicates the 16- or 8-bit data to feed the 32-bit vector.
RM0503 Rev 2
RM0503
2.2
Memory organization
2.2.1
Introduction
Program memory, data memory, registers and I/O ports are organized within the same linear
4-Gbyte address space.
The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word
is considered the word’s least significant byte and the highest numbered byte the most
significant.
RM0503 Rev 2
55/1325
55
RM0503
2.2.2
Memory map and register boundary addresses
Figure 2. Memory map
Used space
Reserved space
0xFFFF FFFF
block 7
0xE000 0000
Arm Cortex M0+
internal peripherals
0x4002 63FF
AHB
block 6
0x4002 0000
0xC000 0000
0x4001 5BFF
block 5
APB
0x4001 0000
0xA000 0000
0x4000 A7FF
block 4
APB
0x8000 0000
0x4000 0000
block 3
0x6000 0000
Option bytes
Engineering bytes
block 2
Peripherals
OTP
0x4000 0000
0x1FFF 7FFF
0x1FFF 7000
0x1FFF 6C00
0x1FFF 6BFF
0x1FFF 6800
System memory
block 1
0x1FFF 0000
SRAM
0x2000 0000
(1)
block 0
Code
Main flash memory
0x0800 0000
0x0000 0000
(1)
Addressable space
Main flash memory /
System memory /
SRAM (2)
0x0000 0000
MSv71271
1. STM32U073xx and STM32U083xx: 0x0803 FFFF; STM32U031xx: 0x0800 FFFF.
2. Depends on boot configuration.
All the memory map areas that are not allocated to on-chip memories and peripherals are
considered as reserved. For the detailed mapping of available memory and register areas,
refer to the following tables.
56/1325
RM0503 Rev 2
RM0503
Table 2. STM32U073xx and STM32U083xx memory boundary addresses
Type
SRAM
Code
Boundary address
Size
Memory Area
Register description
0x2002 A000 - 0x3FFF FFFF
~512 Mbytes
Reserved
-
0x2000 0000 - 0x2002 9FFF
40 Kbytes
SRAM
0x1FFF 8000 - 0x1FFF FFFF
~34 Kbytes
Reserved
0x1FFF 7000 - 0x1FFF 7FFF
4 Kbytes
Option bytes
0x1FFF 6C00 - 0x1FFF 6FFF
1 Kbyte
Engineering bytes
-
0x1FFF 6800 - 0x1FFF 6BFF
1 Kbyte
OTP
-
0x1FFF 0000 - 0x1FFF 67FF
26 Kbytes
System memory
-
0x0808 0000 - 0x1FFF D7FF
~384 Mbytes
Reserved
-
0x0800 0000 - 0x0803 FFFF
256 Kbytes
Main flash memory
Section 3.3.1 on page 65
0x0008 0000 - 0x07FF FFFF
~7.75 Mbytes
Reserved
-
256 Kbytes
Main flash memory,
system memory or SRAM
depending on BOOT
configuration
-
0x0000 0000 - 0x0003 FFFF(1)
Section 2.3 on page 60
Section 3.4 on page 75
1. The memory boundary depends on the memory size of the ordered devices.
Table 3. STM32U031xx memory boundary addresses
Type
SRAM
Code
Boundary address
Size
Memory Area
Register description
0x2000 A000 - 0x3FFF FFFF
~512 Mbytes
Reserved
-
0x2000 0000 - 0x2000 2FFF
12 Kbytes
SRAM
0x1FFF 8000- 0x1FFF FFFF
~34 Kbytes
Reserved
0x1FFF 7000 - 0x1FFF 7FFF
4 Kbytes
Option bytes
0x1FFF 6C00 - 0x1FFF 6FFF
1 Kbyte
Engineering bytes
-
0x1FFF 6800 - 0x1FFF 6BFF
1 Kbyte
OTP
-
0x1FFF 0000 - 0x1FFF 67FF
26 Kbytes
System memory
-
0x0802 0000 - 0x1FFF D7FF
~384 Mbytes
Reserved
-
0x0800 0000 - 0x0801 FFFF
64 Kbytes
Main flash memory
Section 3.3.1 on page 65
0x0002 0000 - 0x07FF FFFF
~8 Mbytes
Reserved
-
64 Kbytes
Main flash memory,
system memory or SRAM
depending on BOOT
configuration
-
0x0000 0000 - 0x0001 FFFF(1)
Section 2.3 on page 60
Section 3.4 on page 75
1. The memory boundary depends on the memory size of the ordered devices.
RM0503 Rev 2
57/1325
63
RM0503
The following table gives the boundary addresses of the peripherals.
Table 4. STM32U0 series peripheral register boundary addresses
Bus
-
AHB
58/1325
Boundary address
Size
Peripheral
®
Cortex -M0+ internal
peripherals
Peripheral register map
0xE000 0000 - 0xE00F FFFF
1Mbytes
0x5000 1800 - 0x5FFF FFFF
~256 Mbytes Reserved
0x5000 1400 - 0x5000 17FF
1 Kbyte
GPIOF
Section 7.4.12 on page 240
0x5000 1000 - 0x5000 13FF
1 Kbyte
GPIOE
Section 7.4.12 on page 240
0x5000 0C00 - 0x5000 0FFF
1 Kbyte
GPIOD
Section 7.4.12 on page 240
0x5000 0800 - 0x5000 0BFF
1 Kbyte
GPIOC
Section 7.4.12 on page 240
0x5000 0400 - 0x5000 07FF
1 Kbyte
GPIOB
Section 7.4.12 on page 240
0x5000 0000 - 0x5000 03FF
1 Kbyte
GPIOA
Section 7.4.12 on page 240
0x4002 6400 - 0x4FFF FFFF
~256 Mbytes Reserved
0x4002 6000 - 0x4002 63FF
1 Kbyte
AES
0x4002 5400 - 0x4002 5FFF
3 Kbytes
Reserved
0x4002 5000 - 0x4002 53FF
1 Kbyte
RNG
0x4002 4400 - 0x4002 4FFF
3 Kbytes
Reserved
0x4002 4000 - 0x4002 43FF
1 Kbyte
TSC
0x4002 3400 - 0x4002 3FFF
3 Kbytes
Reserved
0x4002 3000 - 0x4002 33FF
1 Kbyte
CRC
0x4002 2400 - 0x4002 2FFF
3 Kbyte
Reserved
0x4002 2000 - 0x4002 23FF
1 Kbyte
FLASH
0x4002 1C00 - 0x4002 1FFF
3 Kbytes
Reserved
0x4002 1800 - 0x4002 1BFF
1 Kbyte
EXTI
0x4002 1400 - 0x4002 17FF
1 Kbyte
Reserved
0x4002 1000 - 0x4002 13FF
1 Kbyte
RCC
0x4002 0C00 - 0x4002 0FFF
1 Kbyte
Reserved
0x4002 0800 - 0x4002 0BFF
1 Kbyte
DMAMUX
Section 10.6.7 on page 299
0x4002 0400 - 0x4002 07FF
1 Kbyte
DMA2
Section 9.6.7 on page 282
0x4002 0000 - 0x4002 03FF
1 Kbyte
DMA1
Section 9.6.7 on page 282
RM0503 Rev 2
-
Section 22.7.18 on page 548
Section 21.7.6 on page 501
Section 20.7.11 on page 482
Section 13.4.6 on page 325
Section 3.7.22 on page 103
Section 12.5.11 on page 317
Section 5.4.25 on page 210
-
RM0503
Table 4. STM32U0 series peripheral register boundary addresses (continued)
Bus
Boundary address
Size
Peripheral register map
0x4001 5C00 - 0x4001 FFFF
32 Kbytes
Reserved
0x4001 5800 - 0x4001 5BFF
1 Kbyte
DBG
0x4001 4800 - 0x4001 57FF
4 Kbytes
Reserved
0x4001 4400 - 0x4001 47FF
1 Kbyte
TIM16
Section 26.6.19 on page 823
0x4001 4000 - 0x4001 43FF
1 Kbyte
TIM15
Section 26.6.19 on page 823
0x4001 3C00 - 0x4001 3FFF
1 Kbyte
Reserved
-
0x4001 3800 - 0x4001 3BFF
1 Kbyte
USART1
Section 33.8.16 on page 1100
0x4001 3400 - 0x4001 37FF
1 Kbyte
Reserved
-
0x4001 3000 - 0x4001 33FF
1 Kbyte
SPI1
Section 35.6.8 on page 1194
0x4001 2C00 - 0x4001 2FFF
1 Kbyte
TIM1
Section 23.4 on page 611
0x4001 2800 - 0x4001 2BFF
1 Kbyte
Reserved
0x4001 2400 - 0x4001 27FF
1 Kbyte
ADC
0x4001 0400 - 0x4001 23FF
8 Kbytes
Reserved
0x4001 0200 - 0x4001 03FF
0x4001 0080 - 0x4001 01FF
0x4001 0030 - 0x4001 007F
APB
Peripheral
Section 37.9.5 on page 1310
-
Section 14.14 on page 382
-
COMP
Section 17.6 on page 420
(1)
1 Kbyte
0x4001 0000 - 0x4001 002F
SYSCFG(ITLINE)
Section 8.1.38 on page 261
VREFBUF
Section 16.3.3 on page 412
SYSCFG
Section 8.1.38 on page 261
0x4000 B400- 0x4000 FFFF
19 Kbytes
Reserved
0x4000 B000 - 0x4000 B3FF
1 Kbyte
TAMP (+ BKP registers) Section 31.6.10 on page 961
0x4000 9C00 - 0x4000 AFFF
5 Kbytes
Reserved
-
0x4000 9800 - 0x4000 9BFF
1 Kbyte
USB RAM1
-
0x4000 9400 - 0x4000 97FF
1 Kbyte
LPTIM2
Section 27.7.19 on page 874
0x4000 9000 - 0x4000 93FF
1 Kbyte
LPTIM3
Section 27.7.19 on page 874
0x4000 8C00 - 0x4000 8FFF
1 Kbyte
LPUART3
Section 34.7.14 on page 1158
0x4000 8800 - 0x4000 8BFF
1 Kbyte
I2C3
Section 32.8.10 on page 1009
0x4000 8400 - 0x4000 87FF
1 Kbyte
LPUART2
Section 34.7.14 on page 1158
0x4000 8000 - 0x4000 83FF
1 Kbyte
LPUART1
Section 34.7.14 on page 1158
0x4000 7C00 - 0x4000 7FFF
1 Kbyte
LPTIM1
Section 27.7.19 on page 874
0x4000 7800 - 0x4000 7BFF
1 Kbyte
OPAMP
Section 18.5.4 on page 435
0x4000 7400 - 0x4000 77FF
1 Kbyte
DAC
Section 15.7.13 on page 408
0x4000 7000 - 0x4000 73FF
1 Kbyte
PWR
Section 4.4.20 on page 149
0x4000 6C00 - 0x4000 6FFF
1 Kbyte
CRS
Section 6.7.5 on page 223
0x4000 6000 - 0x4000 6BFF
3 Kbyte
Reserved
0x4000 5C00 - 0x4000 5FFF
1 Kbyte
USB
RM0503 Rev 2
-
Section 36.6.3 on page 1240
59/1325
63
RM0503
Table 4. STM32U0 series peripheral register boundary addresses (continued)
Bus
APB
Boundary address
Size
Peripheral
Peripheral register map
0x4000 5800 - 0x4000 5BFF
1 Kbyte
I2C2
Section 32.8.10 on page 1009
0x4000 5400 - 0x4000 57FF
1 Kbyte
I2C1
Section 32.8.10 on page 1009
0x4000 5000 - 0x4000 53FF
1 Kbyte
Reserved
-
0x4000 4C00 - 0x4000 4FFF
1 Kbyte
USART4
Section 33.8.16 on page 1100
0x4000 4800 - 0x4000 4BFF
1 Kbyte
USART3
Section 33.8.16 on page 1100
0x4000 4400 - 0x4000 47FF
1 Kbyte
USART2
Section 33.8.16 on page 1100
0x4000 4000 - 0x4000 43FF
1 Kbyte
Reserved
-
0x4000 3C00 - 0x4000 3FFF
1 Kbyte
SPI3
Section 35.6.8 on page 1194
0x4000 3800 - 0x4000 3BFF
1 Kbyte
SPI2
Section 35.6.8 on page 1194
0x4000 3400 - 0x4000 37FF
1 Kbyte
Reserved
0x4000 3000 - 0x4000 33FF
1 Kbyte
IWDG
Section 28.7.7 on page 892
0x4000 2C00 - 0x4000 2FFF
1 Kbyte
WWDG
Section 29.6.4 on page 899
0x4000 2800 - 0x4000 2BFF
1 Kbyte
RTC
Section 30.6.23 on page 940
0x4000 2400 - 0x4000 27FF
1 Kbyte
LCD
Section 19.6.8 on page 459
0x4000 1800 - 0x4000 23FF
3 Kbytes
Reserved
-
0x4000 1400 - 0x4000 17FF
1 Kbyte
TIM7
Section 25.4.9 on page 738
0x4000 1000 - 0x4000 13FF
1 Kbyte
TIM6
Section 25.4.9 on page 738
0x4000 0800 - 0x4000 0FFF
2 Kbyte
Reserved
-
0x4000 0400 - 0x4000 07FF
1 Kbyte
TIM3
Section 24.4.28 on page 723
0x4000 0000 - 0x4000 03FF
1 Kbyte
TIM2
Section 24.4.28 on page 723
-
1. SYSCFG (ITLINE) registers use 0x4001 0000 as reference peripheral base address.
2.3
Embedded SRAM
The following table summarizes the SRAM resources on the devices. Enabling or disabling
the parity check does not impact the size of the available SRAM.
.
Table 5. SRAM size
Device
SRAM1 (Kbyte)
SRAM2 (Kbyte)
STM32U083xx
32
8
STM32U073xx
32
8
STM32U031xx
8
4
The SRAM can be accessed by bytes, half-words (16 bits) or full words (32 bits), at
maximum system clock frequency without wait state and thus by both CPU and DMA.
60/1325
RM0503 Rev 2
RM0503
Parity check
The user can enable the parity check using the option bit RAM_PARITY_CHECK in the user
option byte (refer to Section 3.4: FLASH option bytes).
The data bus width is 36 bits because 4 bits are available for parity check (1 bit per byte) in
order to increase memory robustness, as required for instance by Class B or SIL norms.
The parity bits are computed and stored when writing into the SRAM. Then, they are
automatically checked when reading. If one bit fails, an NMI is generated. In addition, to get
the SRAM parity error at the same cycle time that it is occurring, a bus error is generated
(triggering a HardFault exception) together with the NMI. This avoids the corrupted data to
be used by the application, but with the side effect of having both NMI and HardFault
interrupts generated. The same error can also be linked to the BRK_IN Break input of
TIM1/15, with the SRAM_PARITY_LOCK control bit in the SYSCFG configuration register 2
(SYSCFG_CFGR2). The SRAM Parity Error flag (SRAM_PEF) is available in the SYSCFG
configuration register 2 (SYSCFG_CFGR2).
Note:
When enabling the SRAM parity check, it is advised to initialize by software the whole
SRAM at the beginning of the code, to avoid getting parity errors when reading noninitialized locations.
2.4
Flash memory overview
The flash memory is composed of two distinct physical areas:
•
The main flash memory block. It contains the application program and user data if
necessary.
•
The information block. It is composed of three parts:
–
Option bytes for hardware and memory protection user configuration.
–
System memory which contains the proprietary bootloader code.
–
OTP (one-time programmable) area
Refer to Section 3: Embedded flash memory (FLASH) for more details.
The flash interface implements instruction access and data access based on the AHB
protocol. It implements the prefetch buffer that speeds up CPU code execution. It also
implements the logic necessary to carry out the flash memory operations (Program/Erase)
controlled through the flash registers.
RM0503 Rev 2
61/1325
63
RM0503
2.5
Boot configuration
In the STM32U0 series, three different boot modes can be selected through the BOOT0 pin,
BOOT_LOCK bit in FLASH_SECR register, and boot configuration bits nBOOT1,
BOOT_SEL and nBOOT0 in the User option byte, as shown in the following table.
Table 6. Boot modes
Boot mode configuration
Selected boot area
BOOT_
LOCK bit
nBOOT1
bit
BOOT0
pin
nBOOT_SEL
bit
nBOOT0
bit
0
x
0
0
x
Main flash memory
0
1
1
0
x
System memory
0
0
1
0
x
Embedded SRAM
0
x
x
1
1
Main flash memory
0
1
x
1
0
System memory
0
0
x
1
0
Embedded SRAM
1
x
x
x
x
Main flash memory forced
The boot mode configuration is latched on the 4th rising edge of SYSCLK after a reset. It is
up to the user to set boot mode configuration related to the required boot mode.
The boot mode configuration is also re-sampled when exiting from Standby mode.
Consequently they must be kept in the required Boot mode configuration in Standby mode.
After this startup delay has elapsed, the CPU fetches the top-of-stack value from address
0x0000 0000, then starts code execution from the boot memory at 0x0000 0004.
Depending on the selected boot mode, main flash memory, system memory or SRAM is
accessible as follows:
Caution:
62/1325
•
Boot from main flash memory: the main flash memory is aliased in the boot memory
space (0x0000 0000), but still accessible from its original memory space
(0x0800 0000). In other words, the flash memory contents can be accessed starting
from address 0x0000 0000 or 0x0800 0000.
•
Boot from system memory: the system memory is aliased in the boot memory space
(0x0000 0000), but still accessible from its original memory space 0x1FFF0000.
•
Boot from the embedded SRAM: the SRAM is aliased in the boot memory space
(0x0000 0000), but it is still accessible from its original memory space (0x2000 0000).
BOOT0 pin shares the same GPIO with serial wire clock (SWCLK) that is used by the
debugger to connect with the device, based on the fact that these functionalities can be
considered almost completely disjoint. Nevertheless, to ensure system robustness, the
STM32U0 series devices provide an hardware mechanism to force BOOT0 low (boot from
user flash memory) if a debugger access is detected (and BOOT0 information is taken from
the pin), in order to use SWCLK clock for debugger serial communications and at the same
time have a safe boot configuration for the device itself. This configuration is kept until next
power-on following debugger access.
RM0503 Rev 2
RM0503
Forcing boot from flash memory
The BOOT_LOCK bit allows forcing a unique entry point in the main flash memory for boot,
regardless of the other boot mode configuration bits (refer to Section 3.5.6: Forcing boot
from main flash memory).
Empty check
The internal empty check flag (the EMPTY bit of the FLASH access control register
(FLASH_ACR)) is implemented to allow easy programming of virgin devices by the
bootloader. This flag is checked when the boot configuration defines the main flash memory
as the target boot area and the BOOT_LOCK bit is not set. When the EMPTY flag is set, the
device is considered empty and the system memory (bootloader) is selected as boot area
instead of the main flash memory, to allow the programming of the device by the user. Refer
to AN2606 for more details concerning the bootloader and GPIO configuration in system
memory boot mode (some of the GPIOs are reconfigured from the high-Z state).
The EMPTY flag is updated by hardware only during the loading of option bytes: it is set
when the full 72-bit content (including ECC) of the address 0x0800 0000 is read as
0xFF FFFF FFFF FFFF FFFF, otherwise it is cleared. It means that, after programming of a
virgin device, a power-on reset or setting of the OBL_LAUNCH bit in the FLASH_CR
register is needed to clear the EMPTY flag (a system reset has no impact on this flag). The
software can also modify the EMPTY flag directly in the FLASH_ACR register.
Note:
If the device is programmed for the first time but the EMPTY flag is not updated, the device
still selects system memory as a boot area after a system reset.
Physical remap
Once the boot mode is selected, the application software can modify the memory accessible
in the code area. This modification is performed by programming the MEM_MODE bits in
the SYSCFG configuration register 1 (SYSCFG_CFGR1).
Embedded bootloader
The embedded bootloader is located in the system memory, programmed by ST during
production. It is used to reprogram the flash memory using one of the following serial
interfaces:
•
USART, I2C and SPI (applies to all devices)
•
USB (DFU) (applies to STM32U073xx and STM32U083xx)
For further details, refer to the device datasheets and to AN2606.
RM0503 Rev 2
63/1325
63
Embedded flash memory (FLASH)
RM0503
3
Embedded flash memory (FLASH)
3.1
FLASH introduction
The flash memory interface manages CPU (Cortex®-M0+) AHB accesses to the flash
memory. It implements erase and program flash memory operations, read and write
protection, and security mechanisms.
The flash memory interface accelerates code execution with a system of instruction prefetch
and cache lines.
3.2
FLASH main features
•
Up to 256 Kbytes of flash memory (main memory)
•
Memory organization:
–
Main memory block:
Up to 32 Kbytes (4 Kbytes x 72 bits) on STM32U031xx devices
Up to 256 Kbytes (32 bytes x 72 bits) on STM32U073xx and STM32U083xx
devices
–
Information block:
32 Kbytes (4 Kwords x 72 bits)
–
Page size: 2 Kbytes
•
72-bit-wide data read (64 bits plus eight ECC bits)
•
Page erase (2 Kbytes) and mass erase
Flash memory interface features:
64/1325
•
Flash memory read operations
•
Flash memory program/erase operations
•
Read protection activated by option (RDP)
•
Two write protection areas, selected by option (WRP)
•
Securable memory area
•
Flash memory empty check
•
Prefetch buffer
•
CPU instruction cache: 32 cache lines of 4 x 64 bits (1-Kbyte RAM)
•
Error code correction (ECC): eight bits for 64 bits
•
Option byte loader
RM0503 Rev 2
RM0503
Embedded flash memory (FLASH)
3.3
FLASH functional description
3.3.1
Flash memory organization
The flash memory is organized as 72-bit-wide memory cells (64 bits plus eight ECC bits)
that can be used for storing both code and data constants.
The flash memory is organized as follows:
•
Main memory block containing up to 128 pages of 2 Kbytes, each page with eight rows
of 256 bytes
•
Information block containing:
–
System memory from which the CPU boots in system memory bootloader used to
reprogram the flash memory through one of the following interfaces: USART, SPI,
I2C, and USB. On the manufacturing line, the devices are programmed and
protected against spurious write/erase operations. For further details, refer to the
AN2606 available from www.st.com.
–
1 Kbyte (128 double words) OTP (one-time programmable) for user data. The
OTP data cannot be erased and can be written only once. If only one bit is at 0,
the entire double word (64 bits) cannot be written anymore, even with the value
0x0000 0000 0000 0000.
The OTP area cannot be read when the RDP level is 1 and a boot source is not
the main flash memory area.
–
Option bytes for user configuration.
The following table shows the mapping of the flash memory into information block and main
memory area.
Table 7. Flash memory organization: information block
Area
Information block
Addresses
Size (Kbytes)
Memory type
0x1FFF 6C00 - 0x1FFF 7FFF
5
Non-user area
0x1FFF 6800 - 0x1FFF 6BFF
1
OTP area
0x1FFF 0000 - 0x1FFF 67FF
26
System memory
RM0503 Rev 2
65/1325
104
Embedded flash memory (FLASH)
RM0503
Table 8. Flash memory organization: main memory
Area
Main
memory
3.3.2
Addresses
Size
(Kbytes)
64 Kbyte
devices
128 Kbyte
devices
256 Kbyte
devices
0x0803 F800 - 0x0803 FFFF
2
...
2
0x0802 0000 - 0x0802 7FFF
2
0x0801 F800 - 0x0801 FFFF
2
...
...
...
0x0801 0000 - 0x0801 07FF
2
Page 32
0x0800 F800 - 0x0800 FFFF
2
Page 31
...
...
...
0x0800 1000 - 0x0800 17FF
2
Page 2
0x0800 0800 - 0x0800 0FFF
2
Page 1
0x0800 0000 - 0x0800 07FF
2
Page 0
Page 127
-
...
Page 64
-
Page 63
FLASH empty check
During the option byte loading phase, after loading all options, the flash memory interface
checks whether the first location (72 bits) of the main memory is programmed. The result of
this check in conjunction with the boot0 and boot1 information is used to determine where
the system has to boot from. It prevents the system to boot from main flash memory area
when no user code has been programmed.
The main flash memory empty check status can be read from the EMPTY bit in FLASH
access control register (FLASH_ACR). Software can modify the main flash memory empty
status by writing an appropriate value to the EMPTY bit.
3.3.3
FLASH error code correction (ECC)
Data in flash memory words are 72-bits wide: eight bits are added per each double word
(64 bits). The ECC mechanism supports:
•
One error detection and correction
•
Two errors detection
When one error is detected and corrected, the flag ECCC (ECC correction) is set in FLASH
ECC register (FLASH_ECCR). If ECCCIE is set, an interrupt is generated.
When two errors are detected, a flag ECCD (ECC detection) is set in FLASH ECC register
(FLASH_ECCR). In this case, an NMI is generated.
When an ECC error is detected, the address of the failing double word is saved in
ADDR_ECC[16:0] bitfield of the FLASH_ECCR register. ADDR_ECC[2:0] are always
cleared.
While ECCC or ECCD is set, FLASH_ECCR is not updated if a new ECC error occurs.
FLASH_ECCR is updated only when ECC flags are cleared.
66/1325
RM0503 Rev 2
RM0503
Note:
Embedded flash memory (FLASH)
For a virgin data: 0xFF FFFF FFFF FFFF FFFF, one error is detected and corrected, but two
errors detection is not supported.
When an ECC error is reported, a new read at the failing address may not generate an ECC
error if the data is still present in the current buffer, even if ECCC and ECCD are cleared. If
this is not the desired behavior, the user must reset the cache.
3.3.4
FLASH read access latency
To correctly read data from flash memory, the number of wait states (LATENCY) must be
correctly programmed in the FLASH access control register (FLASH_ACR) according to the
frequency of the flash (HCLK) memory clock and the internal voltage range of the device
VCORE. Refer to Section 4.1.6: Dynamic voltage scaling management. Table 9 shows the
correspondence between wait states and flash memory clock frequency.
Table 9. Number of wait states according to flash memory clock (HCLK) frequency
HCLK (MHz)
Wait states (WS)
(LATENCY)
VCORE Range 1
VCORE Range 2
0 WS (1 CPU cycle)
≤ 24
≤8
1 WS (1 CPU cycle)
≤ 48
≤ 16
2 WS (1 CPU cycle)
≤ 56
≤ 18
After power reset, the HCLK clock frequency is 16 MHz in Range 1 and 0 wait state (WS) is
configured in the FLASH_ACR register.
When waking up from Standby, the HCLK clock frequency is 16 MHz in Range 1 and 0 wait
state (WS) is configured in the FLASH_ACR register.
When changing the flash memory clock frequency or Range, the following software
sequences must be applied in order to tune the number of wait states needed to access the
flash memory:
Increasing the CPU frequency
1.
Program the new number of wait states to the LATENCY bits of the FLASH access
control register (FLASH_ACR).
2.
Check that the new number of wait states is taken into account to access the flash
memory by reading back the LATENCY bits of the FLASH access control register
(FLASH_ACR), and wait until the programmed new number is read.
3.
Modify the system cock source by writing the SW bits of the RCC_CFGR register.
4.
If needed, modify the core clock prescaler by writing the HPRE bits of the RCC_CFGR
register.
5.
Optionally, check that the new system clock source or/and the new core clock prescaler
value is/are taken into account by reading the clock source status (SWS bits) of the
RCC_CFGR register, or/and the AHB prescaler value (HPREF bit), of the RCC_CFGR
register.
RM0503 Rev 2
67/1325
104
Embedded flash memory (FLASH)
RM0503
Decreasing the CPU frequency
3.3.5
1.
Modify the system clock source by writing the SW bits of the RCC_CFGR register.
2.
If needed, modify the core clock prescaler by writing the HPRE bits of RCC_CFGR.
3.
Check that the new system clock source or/and the new core clock prescaler value
is/are taken into account by reading the clock source status (SWS bits) of the
RCC_CFGR register, or/and the AHB prescaler value (HPREF bit), of the RCC_CFGR
register, and wait until the programmed new system clock source or/and new flash
memory clock prescaler value is/are read.
4.
Program the new number of wait states to the LATENCY bits of the FLASH access
control register (FLASH_ACR).
5.
Optionally, check that the new number of wait states is used to access the flash
memory by reading back the LATENCY bits of the FLASH access control register
(FLASH_ACR).
Flash memory acceleration
Instruction prefetch
Each flash memory read operation provides 64 bits from either two instructions of 32 bits or
four instructions of 16 bits according to the program launched. This 64-bits current
instruction line is saved in a current buffer. So, in case of sequential code, at least two CPU
cycles are needed to execute the previous read instruction line. Prefetch on the CPU S-bus
can be used to read the next sequential instruction line from the flash memory while the
current instruction line is being requested by the CPU.
Prefetch is enabled by setting the PRFTEN bit of the FLASH access control register
(FLASH_ACR). This feature is useful if at least one wait state is needed to access the flash
memory.
When the code is not sequential (branch), the instruction may not be present in the currently
used instruction line or in the prefetched instruction line. In this case (miss), the penalty in
terms of number of cycles is at least equal to the number of wait states.
If a loop is present in the current buffer, no new access is performed.
Cache memory
To limit the time lost due to jumps, the STM32U0 microcontrollers feature 1 Kbytes of
instruction cache memory. This feature can be enabled by setting the instruction cache
enable (ICEN) bit of the FLASH access control register (FLASH_ACR). Each time a miss
occurs (requested data not present in the currently used instruction line, in the prefetched
instruction line or in the instruction cache memory), the line read is copied into the
instruction cache memory. If some data contained in the instruction cache memory are
requested by the CPU, they are provided without inserting any delay. Once all the
instruction cache memory lines are filled, the LRU (least recently used) policy is used to
determine the line to replace in the instruction memory cache. This feature is particularly
useful in case of code containing loops.
The instruction cache memory is enabled after system reset.
No data cache is available on Cortex®-M0+.
68/1325
RM0503 Rev 2
RM0503
3.3.6
Embedded flash memory (FLASH)
FLASH program and erase operations
The device-embedded flash memory can be programmed using in-circuit programming or
in-application programming.
The in-circuit programming (ICP) method is used to update the entire contents of the flash
memory, using SWD protocol or the supported interfaces by the system bootloader, to load
the user application for the CPU, into the microcontroller. ICP offers quick and efficient
design iterations and eliminates unnecessary package handling or socketing of devices.
In contrast to the ICP method, in-application programming (IAP) can use any
communication interface supported by the microcontroller (I/Os, UART, I2C, SPI, etc.) to
download programming data into memory. IAP allows the user to reprogram the flash
memory while the application is running. Nevertheless, part of the application has to have
been previously programmed in the flash memory using ICP.
The success of a data word programming operation and a page/bank erase operation is not
guaranteed if aborted due to device reset or power loss.
During a program/erase operation to the flash memory, any attempt to read the flash
memory stalls the bus. The read operation proceeds correctly once the program/erase
operation has completed.
Unlocking the flash memory
After reset, write into the FLASH control register (FLASH_CR) is not allowed so as to
protect the flash memory against possible unwanted operations due, for example, to electric
disturbances. The following sequence unlocks these registers:
1.
Write KEY1 = 0x4567 0123 in the FLASH key register (FLASH_KEYR)
2.
Write KEY2 = 0xCDEF 89AB in the FLASH key register (FLASH_KEYR).
Any wrong sequence locks the FLASH_CR registers until the next system reset. In the case
of a wrong key sequence, a bus error is detected and a Hard Fault interrupt is generated.
The FLASH_CR register can be locked again by software by setting the LOCK bit in one of
these registers.
Note:
The FLASH_CR register cannot be written when the BSY1 bit of the FLASH status register
(FLASH_SR) is set. Any attempt to write to this register with the BSY1 bit set causes the
AHB bus to stall until the BSY1 bit is cleared.
Caution:
Due to the structure of the flash memory (64 bits of data associated to 8 bits of ECC), any
ongoing memory operation that is interrupted by a physical event (such as a reset or a
power off) may results in flash memory data corruption, and/or inconsistent ECC bits. The
target address may trigger an ECC interrupt or an NMI when accessed later on. It is
consequently important to always handle flash memory write/erase operations with care,
and manage ECC events in the firmware.
RM0503 Rev 2
69/1325
104
Embedded flash memory (FLASH)
3.3.7
RM0503
FLASH main memory erase sequences
The flash memory erase operation can be performed at page level (page erase), or on the
whole memory (mass erase). Mass erase does not affect the information block (system
flash memory, OTP, and option bytes).
Flash memory page erase
When a page is protected by WRP, it is not erased and the WRPERR bit is set.
Table 10. Page erase overview
HDP1_ACCDIS
[7:0]
0xA3
Any value
different from
0xA3
WRP
Comment
WRPERR CPU bus error
No
Page is erased
No
Yes
Page erase aborted
(no page erase started)
Yes
X
Protected pages only
No
No
Yes
To erase a page (2 Kbytes), follow the procedure below:
Note:
1.
Check that no flash memory operation is ongoing by checking the BSY1 bit of the
FLASH status register (FLASH_SR).
2.
Check and clear all error programming flags due to a previous programming. If not,
PGSERR is set.
3.
Check that the CFGBSY bit of FLASH status register (FLASH_SR) is cleared.
4.
Set the PER bit and select the page to erase (PNB) in the FLASH control register
(FLASH_CR).
5.
Set the STRT bit of the FLASH control register (FLASH_CR).
6.
Wait until the CFGBSY bit of the FLASH status register (FLASH_SR) is cleared again.
The HSI16 internal oscillator is automatically enabled when the STRT bit is set. It is
automatically disabled when the STRT bit is cleared, except if previously enabled with the
HSION bit of the RCC_CR register.
Flash memory bank or mass erase
When WRP is enabled, the flash memory mass erase is aborted, no erase starts, and the
WRPERR bit is set.
Table 11. Mass erase overview
HDP1_ACCDIS
[7:0]
0xA3
Any value
different from
0xA3
70/1325
WRP
Comment
WRPERR
No
Memory is erased
No
Yes
Erase aborted (no erase started)
Yes
X
Erase aborted (no erase started)
No
RM0503 Rev 2
CPU bus error
No
Yes
RM0503
Embedded flash memory (FLASH)
To perform a mass erase, respect the following procedure:
1.
Check that no flash memory operation is ongoing by checking the BSY1 bit of the
FLASH status register (FLASH_SR).
2.
Check and clear all error programming flags due to a previous programming. If not,
PGSERR is set.
3.
Check that the CFGBSY bit of FLASH status register (FLASH_SR) is cleared.
4.
Set the MER1 bit of the FLASH control register (FLASH_CR).
5.
Set the STRT bit of the FLASH control register (FLASH_CR).
6.
Wait until the CFGBSY bit of the FLASH status register (FLASH_SR) is cleared again.
Note:
The HSI16 internal oscillator is automatically enabled when the STRT bit is set. It is
automatically disabled when the STRT bit is cleared, except if previously enabled with the
HSION bit of the RCC_CR register.
3.3.8
FLASH main memory programming sequences
The flash memory is programmed 72 bits (64 bits plus 8-bit ECC).
Programming a previously programmed address with a nonzero data is not allowed. Any
such attempt sets PROGERR flag of the FLASH status register (FLASH_SR).
It is only possible to program a double word (2 x 32-bit data).
•
Any attempt to write byte (8 bits) or half-word (16 bits) sets SIZERR flag of the FLASH
status register (FLASH_SR).
•
Any attempt to write a double word that is not aligned with a double word address sets
PGAERR flag of the FLASH status register (FLASH_SR).
Standard programming
The flash memory programming sequence in fast programming mode is as follows:
1.
Check that no main flash memory operation is ongoing by checking the BSY1 bit of the
FLASH status register (FLASH_SR).
2.
Check and clear all error programming flags due to a previous programming. If not,
PGSERR is set.
3.
Check that the CFGBSY bit of FLASH status register (FLASH_SR) is cleared.
4.
Set the PG bit of the FLASH control register (FLASH_CR).
5.
Perform the data write operation at the desired memory address, inside main memory
block or OTP area. Only double word (64 bits) can be programmed.
a)
Write a first word in an address aligned with double word.
b)
Write the second word.
6.
Wait until the CFGBSY bit of the FLASH status register (FLASH_SR) is cleared again.
7.
Check that the EOP flag in the FLASH status register (FLASH_SR) is set
(programming operation succeeded), and clear it by software.
8.
Clear the PG bit of the FLASH control register (FLASH_CR) if there no more
programming request anymore.
RM0503 Rev 2
71/1325
104
Embedded flash memory (FLASH)
Note:
RM0503
When the flash memory interface has received a good sequence (a double word),
programming is automatically launched, and the BSY1 bit set.
The HSI16 internal oscillator is automatically enabled when the PG bit is set. It is
automatically disabled when the PG bit is cleared, except if previously enabled with the
HSION bit of the RCC_CR register.
Fast programming
The main purpose of this mode is to reduce the page programming time. It is achieved by
eliminating the need for verifying the flash memory locations before they are programmed,
thus saving the time of high voltage ramping and falling for each double word.
This mode allows programming a row (32 double words = 256 bytes).
During fast programming, the flash memory clock (HCLK) frequency must be at least
8 MHz.
Only the main memory can be programmed in Fast programming mode.
The main flash memory programming sequence in standard mode is described below:
Note:
1.
Perform a mass or page erase. If not, PGSERR is set.
2.
Check that no main flash memory operation is ongoing by checking the BSY1 bit of the
FLASH status register (FLASH_SR).
3.
Check and clear all error programming flag due to a previous programming.
4.
Check that the CFGBSY bit of FLASH status register (FLASH_SR) is cleared.
5.
Set the FSTPG bit in FLASH control register (FLASH_CR).
6.
Write 16 double-words to program a row (128 bytes).
7.
Wait until the CFGBSY bit of the FLASH status register (FLASH_SR) is cleared again.
8.
Check that the EOP flag in the FLASH status register (FLASH_SR) is set
(programming operation succeeded), and clear it by software.
9.
Clear the FSTPG bit of the FLASH status register (FLASH_SR) if there are no more
programming requests anymore.
When attempting to write in Fast programming mode while a read operation is ongoing, the
programming is aborted without any system notification (no error flag is set).
When the flash memory interface has received the first double word, programming is
automatically launched. The BSY1 bit is set when the high voltage is applied for the first
double word, and it is cleared when the last double word has been programmed or in case
of error.
The HSI48 internal oscillator (with a divide by three to provide 16 MHz) is automatically
enabled when the FSTPG bit is set. It is automatically disabled when the FSTPG bit is
cleared, except if previously enabled with the HSION bit of the RCC_CR register.
The 16 double words must be written successively. The high voltage is kept on the flash
memory for all the programming. Maximum time between two double words write requests
is the time programming (around 20 µs). If a second double word arrives after this time
programming, fast programming is interrupted, and MISSERR is set.
High voltage must not exceed 8 ms for a full row between two erases. This is guaranteed by
the sequence of 16 double words successively written with a clock system greater or equal
72/1325
RM0503 Rev 2
RM0503
Embedded flash memory (FLASH)
to 8 MHz. An internal time-out counter counts 7 ms when Fast programming is set and stops
the programming when time-out is over. In this case, the FASTERR bit is set.
If an error occurs, high voltage is stopped, and the next double word to programmed is not
programmed. Anyway, all previous double words have been properly programmed.
Programming errors
Several kinds of errors can be detected. In case of error, the flash memory operation
(programming or erasing) is aborted.
•
PROGERR: Programming error
In standard programming: PROGERR is set if the word to write is not previously erased
(except if the value to program is full zero and the target address is in the main
memory).
•
SIZERR: Size programming error
In standard programming or in fast programming: only double word can be
programmed, and only 32-bit data can be written. SIZERR is set if a byte or an
half-word is written.
•
PGAERR: Alignment programming error
PGAERR is set if one of the following conditions occurs:
•
–
In standard programming: the first word to be programmed is not aligned with a
double word address, or the second word does not belong to the same double
word address.
–
In fast programming: the data to program does not belong to the same row than
the previous programmed double words, or the address to program is not greater
than the previous one.
PGSERR: Programming sequence error
PGSERR is set if one of the following conditions occurs:
•
–
In the standard programming sequence or the fast programming sequence: a data
is written when PG and FSTPG are cleared.
–
In the standard programming sequence or the fast programming sequence: MER1
and PER are not cleared when PG or FSTPG is set.
–
In the fast programming sequence: the Mass erase is not performed before setting
the FSTPG bit.
–
In the mass erase sequence: PG, FSTPG, and PER are not cleared when MER1 is
set.
–
In the page erase sequence: PG, FSTPG, and MER1 are not cleared when PER is
set.
–
PGSERR is also set if PROGERR, SIZERR, PGAERR, WRPERR, MISSERR,
FASTERR, or PGSERR is set due to a previous programming error.
WRPERR: Write protection error
WRPERR is set if one of the following conditions occurs:
–
Attempt to program or erase in a write protected area (WRP).
–
Attempt to perform a mass erase when one page or more is protected by WRP.
–
The debug features are connected or the boot is executed from SRAM or from
system flash memory when the read protection (RDP) is set to level 1.
–
Attempt to modify the option bytes when the read protection (RDP) is set to level
2.
RM0503 Rev 2
73/1325
104
Embedded flash memory (FLASH)
•
RM0503
MISSERR: Fast programming data miss error
In fast programming: all the data must be written successively. MISSERR is set if the
previous data programmation is finished and the next data to program is not written yet.
•
FASTERR: Fast programming error
In fast programming: FASTERR is set if one of the following conditions occurs:
•
–
when FSTPG bit is set for more than 8 ms, which generates a time-out detection
–
when the row fast programming has been interrupted by a MISSERR, PGAERR,
WRPERR, or SIZERR
OPERR: Generic error related to program/erase operations.
This flag can be set only if the error interrupt enable flag is set (ERRIE). In this case, it
is set on any error condition (SEQERR, PROGERR, SIZERR, PGAERR, WRPERR,
MISSERR, PGSERR or FASTERR). Once set, it can only be cleared by programming it
to 1.
•
OEMOPTWERR: Key setting error
This flag is set when an invalid configuration is programmed to the OEM keys. It is set
when attempting:
•
–
to modify the OEM1KEYWxR registers when the RDP level 0 is disabled and the
OEM1LOCK bit of the FLASH_SR is set.
–
to modify the OEM2KEYWxR registers when the RDP level 0 is disabled and the
OEM2LOCK bit of the FLASH_SR is set.
–
to perform a regression from RDP level 1 to RDP level 0, while the OEM1LOCK bit
of FLASH_SR is set and a wrong OEM1KEY is transmitted through JTAG or SWD.
HDPOPTWERR: HDP setting error
This flag is set when an invalid configuration is programmed to the HDP option bytes. It
is set when attempting:
–
to modify the HDP1EN[7:0] and/or the HDP1_PEND[6:0] bitfield of the
FLASH_SECR register, when the HDP1_ACCDIS[7:0] and the
HDP1EXT_ACCDIS[7:0 bitfields of the FLASH_HDPCR register are not equal to
their reset value (0xA3).
–
to set the HDP1_ACCDIS[7:0] and/or the HDP1EXT_ACCDIS[7:0] bitfields to a
value different from their reset value (0xA3), while the HDP1EN[7:0] and/or the
HDP1_PEND[6:0] bitfields have been changed, and no option byte modification
and loading (OPTSTRT and OBL_LAUNCH bits set in the FLASH_CR registers)
has been done in between.
If an error occurs during a program or erase operation, one of the following error flags of the
FLASH status register (FLASH_SR) is set:
•
PROGERR, SIZERR, PGAERR, PGSERR, MISSERR (program error flags)
•
WRPERR (protection error flag)
In this case, if the error interrupt enable bit ERRIE of the FLASH control register
(FLASH_CR) is set, an interrupt is generated and the operation error flag OPERR of the
FLASH status register (FLASH_SR) is set.
Note:
74/1325
If several successive errors are detected (for example, in case of DMA transfer to the flash
memory), the error flags cannot be cleared until the end of the successive write request.
RM0503 Rev 2
RM0503
Embedded flash memory (FLASH)
Programming and cache
If an erase operation in flash memory also concerns data in the instruction cache, the user
has to ensure that these data are rewritten before they are accessed during code execution.
Note:
The cache should be flushed only when it is disabled (ICEN = 0).
3.4
FLASH option bytes
3.4.1
FLASH option byte description
The option bytes are configured by the end user depending on the application requirements.
As a configuration example, the watchdog may be selected in hardware or software mode
(refer to Section 3.4.2: FLASH option byte programming).
A double word is split up in option bytes as indicated in Table 12.
Table 12. Option byte format
55-48
47-40
39-32
Complemented Complemented Complemented Complemented
option byte 3
option byte 2
option byte 1
option byte 0
31-24
23-16
15 -8
7-0
Option
byte 3
Option
byte 2
Option
byte 1
Option
byte 0
Table 13 shows the organization of the option bytes (the lower word only) in the flash
memory information block. The software can read the option bytes from these flash memory
locations or from their corresponding option registers referenced in the table. Refer to
sections FLASH option register (FLASH_OPTR) to FLASH security register
(FLASH_SECR) for the description of the option register bitfields, also applicable to the
option byte bitfields.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 13. Organization of option bytes
Option byte 1
BOR_LEV[2:0]
Option byte 2
NBOOT0
NBOOT1
NBOOT_SEL
BKPSRAM_HW_ERASE_DISABLE
RAM_PARITY_CHECK
NOT_VBAT_VDD_OPT
Reserved
WWDG_SW
IWDG_STBY
IWDG_STOP
IWDG_SW
NRST_SHDW
NRST_STDBY
NRST_STOP
NRST_MODE[1:0]
Option byte 3
Option byte 0
Factory value
X X 1 1 1 1 1 1 1 1 1 X 1 1 1 1 1 1 1 X X 1 1 1 1 0 1 0 1 0 1 0
FLASH_
WRP1AR
(Section 3.7.8)
Factory value
IRHEN
FLASH_OPTR
(Section 3.7.7)
Reserved
Corresponding
option register
(section)
Reserved
WRP1A_END
[6:0]
Reserved
63-56
Reserved
RDP[7:0]
WRP1A_STRT
[6:0]
X X X X X X X X X 0 0 0 0 0 0 0 X X X X X X X X X 1 1 1 1 1 1 1
RM0503 Rev 2
75/1325
104
Embedded flash memory (FLASH)
RM0503
Factory value
FLASH_SECR
(Section 3.7.10)
Factory value
Option byte 3
Option byte 2
Option byte 1
Option byte 0
Reserved
WRP1B_END
[6:0]
Reserved
WRP1B_STRT
[6:0]
X X X X X X X X X 0 0 0 0 0 0 0 X X X X X X X X X 1 1 1 1 1 1 1
HDP1EN[7:0]
Reserved.
BOOT_LOCK
FLASH_
WRP1BR
(Section 3.7.9)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 13. Organization of option bytes (continued)
Corresponding
option register
(section)
Reserved
HDP1_PEND
[6:0]
1 0 1 1 0 1 0 0 X X X X X X X 0 X X X X X X X X X 0 0 0 0 0 0 0
Reserved
76/1325
FLASH_
OEM1KEYR1
OEM1KEY[31:0]
Factory value
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
FLASH_
OEM1KEYR2
OEM1KEY[63:32]
Factory value
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
FLASH_
OEM1KEYR3
OEM1KEY[95:64]
Factory value
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
FLASH_
OEM1KEYR4
OEM1KEY[127:96]
Factory value
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
FLASH_
OEM2KEYR1
OEM2KEY[31:0]
Factory value
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
FLASH_
OEM2KEYR2
OEM2KEY[63:32]
Factory value
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
FLASH_
OEM2KEYR3
OEM2KEY[95:64]
Factory value
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
FLASH_
OEM2KEYR4
OEM2KEY[127:96]
Factory value
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
RM0503 Rev 2
RM0503
3.4.2
Embedded flash memory (FLASH)
FLASH option byte programming
After reset, the option related bits of the FLASH control register (FLASH_CR) are writeprotected. To run any operation on the option byte page, the option lock bit OPTLOCK of the
FLASH control register (FLASH_CR) must be cleared. The following sequence is used to
unlock this register:
1.
Unlock the FLASH_CR with the LOCK clearing sequence (refer to Unlocking the flash
memory).
2.
Write OPTKEY1 = 0x0819 2A3B of the FLASH option key register
(FLASH_OPTKEYR).
3.
Write OPTKEY2 = 0x4C5D 6E7F of the FLASH option key register
(FLASH_OPTKEYR).
Any wrong sequence locks up the flash memory option registers until the next system reset.
In the case of a wrong key sequence, a bus error is detected and a Hard Fault interrupt is
generated.
The user options can be protected against unwanted erase/program operations by setting
the OPTLOCK bit by software.
Note:
If LOCK is set by software, OPTLOCK is automatically set as well.
Modifying user options
The option bytes are programmed differently from a main memory user address.
To modify the value of user options, follow the procedure below:
Note:
1.
Clear OPTLOCK option lock bit with the clearing sequence described above
2.
Write the desired values in the FLASH option registers.
3.
Check that no flash memory operation is ongoing, by checking the BSY1 bit of the
FLASH status register (FLASH_SR).
4.
Set the options start bit OPTSTRT of the FLASH control register (FLASH_CR).
5.
Wait for the BSY1 bit to be cleared.
Any modification of the value of one option is automatically performed by erasing user
option byte pages first, and then programming all the option bytes with the values contained
in the flash memory option registers.
The complementary values are automatically computed and written into the complemented
option bytes upon setting the OPTSTRT bit.
Caution:
Upon an option byte programming failure (for any reason, such as loss of power or a reset
during the option byte change sequence), the mismatch values of the option bytes are
loaded after reset. Those mismatch values force a secure configuration that might
permanently lock the device. To prevent this, only program option bytes in a safe
environment-safe supply, no pending watchdog, and clean reset line.
RM0503 Rev 2
77/1325
104
Embedded flash memory (FLASH)
RM0503
Option byte loading
After the BSY1 bit is cleared, all new options are updated into the flash memory, but not
applied to the system. A read from the option registers still returns the last loaded option
byte values. The new options has effect on the system only after they are loaded.
Option byte loading is performed in two cases:
•
when OBL_LAUNCH bit of the FLASH control register (FLASH_CR) is set
•
after a power reset (BOR reset or exit from Standby/Shutdown modes)
Option byte loader performs a read of the options block and stores the data into internal
option registers. These internal registers configure the system and can be read by software.
Setting OBL_LAUNCH generates a reset so the option byte loading is performed under
system reset.
Each option bit has also its complement in the same double word. During option loading, a
verification of the option bit and its complement allows to check that the loading has
correctly taken place.
During option byte loading, the options are read by double word.
If the word and its complement are matching, the option word/byte is copied into the option
register.
If the comparison between the word and its complement fails, a status bit OPTVERR is set.
Mismatch values are forced into the option registers:
•
For USR OPT option, the value of mismatch is 1 for all option bits.
•
For WRP option, the value of mismatch is the default value “No protection”.
•
For RDP option, the value of mismatch is the default value “level 1”.
•
For BOOT_LOCK, the value of mismatch is “boot forced from main flash memory”.
Upon system reset, the option bytes are copied into the following option registers that can
be read and written by software:
•
FLASH_OPTR
•
FLASH_WRP1xR (x = A or B)
•
FLASH_SECR
These registers are also used to modify options. If these registers are not modified by user,
they reflect the options states of the system. See Section : Modifying user options for more
details.
78/1325
RM0503 Rev 2
RM0503
3.5
Embedded flash memory (FLASH)
Flash memory protection
The main flash memory can be protected against external accesses with the read protection
(RDP). The pages can also be protected against unwanted write (WRP) due to loss of
program counter context. The write-protection WRP granularity is 2 Kbytes. Apart from the
RDP and WRP, the flash memory also features an HDP securable area.
3.5.1
FLASH read protection (RDP)
The read protection is activated by setting the RDP option byte and then, by applying a
system reset to reload the new RDP option byte. The read protection protects the main flash
memory, the option bytes, and the backup registers.
Note:
If the read protection is set while the debugger is still connected through JTAG/SWD (or has
been connected since the last power-on), apply a POR (power-on reset) instead of a system
reset. If the read protection is programmed by software, do not set the OBL_LAUNCH bit of
the FLASH control register (FLASH_CR). Instead perform a POR to reload the option byte.
This can be done by a switch to Standby or Shutdown mode followed by a wake-up.
There are three levels of read protection from no protection (level 0) to maximum protection
or no debug (level 2).
The flash memory is protected when the RDP option byte and its complement contain the
pair of values shown in Table 14.
Table 14. Flash memory read protection status
RDP byte value
RDP complement byte value
Read protection level
0xAA
0x55
Level 0
Any values except the combinations [0xAA, 0x55] and [0xCC, 0x33]
0xCC
0x33
Level 1 (default)
Level 2
The system memory area is read-accessible whatever the protection level. It is never
accessible for program/erase operation.
Level 0: no protection
Read, program, and erase operations within the main flash memory area are possible. The
option bytes are also accessible by all operations.
Level 1: Read protection
Level 1 read protection is set when the RDP byte and the RDP complemented byte contain
any value combinations other than [0xAA, 0x55] and [0xCC, 0x33]. Level 1 is the default
protection level when RDP option byte is erased.
•
User mode: Code executing in user mode (boot from user flash memory) can access
main flash memory and option bytes with all operations.
•
Debug, boot from SRAM, and boot from system memory modes: In debug mode
or when code boots from SRAM or system memory, the main flash memory is totally
inaccessible. In these modes, a read or write access to the flash memory generates a
bus error and a Hard Fault interrupt.
RM0503 Rev 2
79/1325
104
Embedded flash memory (FLASH)
RM0503
Level 2: No debug
In this level, the protection level 1 is guaranteed. In addition, the CPU debug port, the boot
from RAM (boot RAM mode) and the boot from system memory (bootloader mode) are no
more available. In user execution mode (boot FLASH mode), all operations are allowed on
the main flash memory.
Note:
The CPU debug port is also disabled under reset.
STMicroelectronics is not able to perform analysis on defective parts on which the level 2
protection has been set.
Changing the read protection level
The read protection level can change:
•
from level 0 to level 1, upon changing the value of the RDP byte to any value except
0xCC
•
from level 0 or level 1 to level 2, upon changing the value of the RDP byte to 0xCC
•
from level 1 to level 0, upon changing the value of the RDP byte to 0xAA
Once in level 2, it is no more possible to modify the read protection level.
The OTP area is not affected by a mass erase and remains unchanged.
Note:
Mass erase (full or partial) is only triggered by the RDP regression from level 1 to level 0.
RDP level increase (level 0 to level 1, 1 to 2, or 0 to 2) does not cause any mass erase.
To validate the protection level change, the option bytes must be reloaded by setting the
OBL_LAUNCH bit of the FLASH control register (FLASH_CR).
Figure 3. Changing read protection (RDP) level
OEM1 key
OB update
OB update
RDP0
Full debug
No intrusion
RDP write
RDP=0xCC write
RDP1
Full debug
Intrusion detect
RDP=0xCC write
OEM2 key
RDP2
No debug
SWAP_BANK
OB update
MSv72611V1
80/1325
RM0503 Rev 2
RM0503
Embedded flash memory (FLASH)
Table 15. Access status versus protection level and execution modes
Protection
level
Area
User execution (Boot from flash)
Debug/ Boot from RAM/ Boot
from loader
Read
Write
Erase
Read
Write
Erase
Main flash
memory
1
Yes
Yes
Yes
No
No
No(3)
2
Yes
Yes
Yes
N/A(1)
N/A(1)
N/A(1)
System
memory(2)
1
Yes
No
No
Yes
No
No
(1)
Option bytes
OTP,
SRAM2, and
backup
registers
(1)
2
Yes
No
No
N/A
N/A
N/A(1)
1
Yes
Yes(3)
Yes
Yes
Yes(3)
Yes
(1)
(1)
2
Yes
No
No
N/A
N/A
N/A(1)
1
Yes
Yes
N/A
No
No
N/A
2
Yes
Yes
N/A
N/A(1)
N/A(1)
N/A(1)
1. When the protection level 2 is active, the Debug port, the boot from RAM and the boot from system memory are disabled.
2. The system memory is only read-accessible, whatever the protection level (0, 1 or 2) and execution mode.
3. The flash main memory is erased when the RDP option byte is programmed with all level of protections disabled (0xAA).
OEM1/2 lock activation
Two 128-bit keys (OEM1KEY and OEM2KEY) can be defined and used to lock the RDP
regression. Each 128-bit key is coded on four registers: FLASH_OEM1KEYW0R
(respectively FLASH_OEM2KEYW0R) to FLASH_OEM1KEYW3R (respectively
FLASH_OEM2KEYW3R).
OEM1KEY and OEM2KEY cannot be read through these registers: they are always read as
zero. However, to verify the keys, their CRC can be accessed through OEM1KEYCRC and
OEM2KEYCRC of the FLASH_OEMKEYSR register.
OEM1KEY can be modified:
•
in readout protection level 0
•
in readout protection level 1 if OEM1LOCK = 0 in FLASH_SR
OEM2KEY can be modified:
•
in readout protection level 0
•
in readout protection level 1 if OEM2LOCK = 0 in FLASH_SR
When attempting to modify FLASH_OEMxKEYWyR (x = 1 or 2, y = 0 to 3) without
respecting the above rules, the user option modification is not performed, and the
OEMOPTWERR bit is set.
Follow the steps below to activate the OEM1/2 lock mechanism:
1.
Check that the OEM1LOCK/OEM2LOCK bit is not set, or that the readout protection is
at level 0.
2.
Write a 128-bit key to FLASH_OEM1KEYWxR/FLASH_OEM2KEYWxR (y = 0 to 3).
3.
Launch the option modification by setting the OPTSTRT bit, and check that
OEMOPTWERR is not set.
4.
Set the OBL_LAUNCH or perform a power-on reset.
5.
Check that OEM1LOCK/OEM2LOCK is set.
RM0503 Rev 2
81/1325
104
Embedded flash memory (FLASH)
Note:
RM0503
The OEM1KEY and OEM2KEY must not contain only 1 or 0.
OEM1 RDP lock mechanism
The OEM1 RDP lock mechanism is active when the OEM1LOCK bit is set in the
FLASH_SR register. It blocks the RDP level 1 to RDP level 0 regression.
Apply the following unlock sequence to perform an RDP level 1 to RDP level 0 regression:
1.
Program the 128-bit OEM1 key in the DBGMCU_DBG_AUTH_HOST register. This
operation must be done using the debug interface under reset.
2.
If this key matches the OEM1KEY value, the RDP regression can be launched by
setting the OPTSTRT bit of the FLASH_CR register.
3.
If the key does not match the OEM1KEY value, the RDP regression and any access to
the flash memory are blocked until the next power-on reset.
Attempting to perform a regression from RDP level 1 to RDP level 0 without following the
above sequence sets the OEMOPTWERR option bit, and the option bytes remain
unchanged.
When the lock mechanism is not activated (OEM1LOCK = 0), the regression from RDP
level 1 to RDP level 0 is always granted.
OEM2 RDP lock mechanism
The OEM2 RDP lock mechanism is active when the OEM2LOCK bit is set in the
FLASH_CR register. It allows the RDP level 2 to RDP level 1 regression.
The following unlock sequence must be applied:
3.5.2
1.
Program the 128-bit OEM2 key in the DBGMCU_DBG_AUTH_HOST register. This
operation must be done using the debug interface under reset.
2.
If this key matches the OEM2KEY value, the RDP regression is launched automatically
by hardware as soon as the reset signal goes high.
3.
If the key does not match the OEM2KEY value, the device boots normally (as if no key
has been provided).
FLASH write protection (WRP)
The user area in flash memory can be protected against unwanted write operations. Two
write-protected (WRP) areas can be defined, with page (2-Kbyte) granularity. Each area is
defined by a start page offset and an end page offset related to the physical flash memory
base address. These offsets are defined in the WRP address registers FLASH WRP area A
address register (FLASH_WRP1AR) and FLASH WRP area B address register
(FLASH_WRP1BR).
The WRP x area (x = A, B) is defined from the address
flash memory Base address + [WRP1x_STRT x 0x0800] (included)
to the address
flash memory Base address + [(WRP1x_END+1) x 0x0800] (excluded).
The minimum WRP area size is one WRP page (2 Kbytes):
WRP1x_END = WRP1x_STRT.
82/1325
RM0503 Rev 2
RM0503
Embedded flash memory (FLASH)
For example, to protect the flash memory by WRP from the address 0x0800 1000 (included)
to the address 0x0800 3FFF (included):
If boot in flash memory is selected, FLASH_WRP1AR register must be programmed
with:
–
WRP1A_STRT = 0x02.
–
WRP1A_END = 0x07.
WRP1B_STRT and WRP1B_END in FLASH_WRP1BR can be used instead (area B in
the flash memory).
When WRP is active, it cannot be erased or programmed. Consequently, a software mass
erase cannot be performed if one area is write-protected.
If an erase/program operation to a write-protected part of the flash memory is attempted, the
write protection error flag (WRPERR) of the FLASH_SR register is set. This flag is also set
for any write access to:
Note:
•
OTP area
•
part of the flash memory that can never be written like the ICP
When the flash memory read protection level is selected (RDP level = 1), it is not possible to
program or erase the memory if the CPU debug features are connected (single wire) or boot
code is being executed from SRAM or system flash memory, even if WRP is not activated.
Any attempt generates a hard fault (BusFault).
Table 16: WRP protection
WRP registers values
(x = A or B)
WRP-protected area
WRP1x_STRT = WRP1x_END
Page WRP1x
WRP1x_STRT > WRP1x_END
None (unprotected)
WRP1x_STRT < WRP1x_END
Pages from WRP1x_STRT to WRP1x_END
Note:
To validate the WRP options, the option bytes must be reloaded by setting the
OBL_LAUNCH bit in the flash memory control register.
3.5.3
Securable memory area (HDP)
The main purpose of the securable memory area is to protect a specific part of flash
memory against undesired access. After system reset, the code in the securable memory
area can only be executed until the securable area becomes secured and never again until
the next system reset. This allows implementing software security services such as secure
key storage or safe boot.
The securable memory area is located in the first pages of the main flash memory. When
not secured, the securable memory behaves like the rest of main flash memory. When
secured (the HDP1_ACCDIS[7:0] value in the FLASH_HDPCR register is different from
0xA3, and the HDP1EN[7:0] value in FLASH_SECR register is different from 0xB4), any
write access (programming, erase) to the securable memory area is rejected and generates
a bus error. Fetch and read accesses return zero (read-as-zero RAZ). The securable area
can only be unsecured by a system reset.
The last page of the securable memory area is defined by the HDP1_PEND[6:0] bitfield of
the FLASH_SECR register. The protection is enabled by the HDP1EN[7:0] bitfield in the
RM0503 Rev 2
83/1325
104
Embedded flash memory (FLASH)
RM0503
same register. After updating the FLASH_SECR register, OPTSTRT and OBL_LAUNCH are
required before activating the protection through HDP1_ACCDIS[7:0] or
HDP1EXT_ACCDIS[7:0].
Note:
The securable memory area start address is 0x0800 0000. Before activating the securable
memory area, move the vector table outside the page 0 if necessary.
3.5.4
Securable memory area extension (HDP extension)
The HDP1 area can be extended through HDP1_EXT[6:0] of the FLASH HDP extension
register (FLASH_HDPEXTR). HDP1_EXT[6:0] indicates the number of pages added to the
HDP area.
The start page offset of the HDP1 extension area depends on the presence of an HDP1
area. If there is an HDP1 area, the HDP1 extension area starts from HDP1_PEND + 1.
Otherwise, it starts from the user flash memory base address.
The behavior of the extension is controlled by the HDP1EXT_ACCDIS[7:0] value (refer to
Table 17).
Table 17. HDP extension protection
HDP1EXT_ACCDIS
[7:0] state
Write to
HDP1EXT_ACCDIS
[7:0]
Write to
HDP1_EXT[6:0]
Access to HDP
memory area
0xA3
OK
OK
Allowed
0x5C
OK, if the value written
is not 0xA3
OK to write larger value
Denied
Others
Write ignored
Write ignored
Denied
There are two determining HDP1EXT_ACCDIS[7:0] values:
•
HDP1EXT_ACCDIS[7:0] = 0xA3 (reset value): the HDP area protection is not active
and can be reconfigured freely.
•
HDP1EXT_ACCDIS[7:0] = 0x5C: the HDP protection is active, but the extension can
be expanded if needed.
•
HDP1EXT_ACCDIS[7:0] = any other value: the HDP protection is active, and there is
no way to modify the settings until the next reset.
When active, the extension also prevents any modification of the HDP1 option bytes,
HDP1EN[7:0] and HDP1_PEND[6:0].
The access to the securable memory area extension is disabled if HDP1_ACCDIS[7:0] is
set to 0xA3 (access granted), and the HDP1EXT_ACCDIS[7:0] is set to a value different
from 0xA3 (access disabled).
Refer to Figure 4 for an example:
84/1325
RM0503 Rev 2
RM0503
Embedded flash memory (FLASH)
Figure 4. Example of HDP extension protection
Last page
User flash memory
Page 12
Page 8
Page 7
HDP1_EXT = 0x5
Pages 8-12 protected by
HDP1EXT_ACCDIS
HDP1_PEND = 0x7
HDP(1[%
Pages 0-7
protected by HDP1_ACCDIS or HDP1EXT_ACCDIS
Page 0
MSv72610V1
As in case of HDP area configured by option bytes, any attempt to program protected pages
is treated as a bus error, and fetch and read operations return zero (read-as-zero RAZ).
3.5.5
Disabling core debug access
For executing sensitive code or manipulating sensitive data in securable memory area, the
debug access to the core can temporarily be disabled.
Figure 5 gives an example of managing DBG_SWEN and SEC_PROT bits.
Figure 5. Example of disabling core debug access
SEC_PROT = 0
Securable memory not secured
Debug
enabled
Option
byte
loading
SEC_PROT = 1
Securable memory secured
Debug
disabled
Debug
enabled
Execution of code
within securable memory
Execution of code
outside securable memory
timeline
Power up
DBG_SWEN = 0
DBG_SWEN = 1
SEC_PROT = 1
Software management
MSv42192V1
RM0503 Rev 2
85/1325
104
Embedded flash memory (FLASH)
3.5.6
RM0503
Forcing boot from main flash memory
To increase the security and establish a chain of trust, the BOOT_LOCK option bit of the
FLASH_SECR register allows forcing the system to boot from the main flash memory
regardless the other boot options. It is always possible to set the BOOT_LOCK bit.
However, it is possible to reset it only when:
•
RDP is set to level 0, or
•
RDP is set to level 1, while level 0 is requested and a full mass-erase is performed.
Caution:
If BOOT_LOCK is set in association with RDP Level 1, the debug capabilities of the device
are stopped, and the reset value of the DBG_SWEN bit of the FLASH_ACR register
becomes zero. If the DBG_SWEN bit is cleared by the application code after reset, there is
no way to recover from this situation.
3.6
FLASH interrupts
Table 18. FLASH interrupt requests
Event flag
Event flag/interrupt
clearing method
Interrupt enable
control bit
End of operation
EOP(1)
Write EOP=1
EOPIE
Operation error
OPERR(2)
Write OPERR=1
ERRIE
Write protection error
WRPERR
Write WRPERR=1
N/A
Size error
SIZERR
Write SIZERR=1
N/A
Programming sequential error
PROGERR
Write PROGERR=1
N/A
Programming alignment error
PGAERR
Write PGAERR=1
N/A
Programming sequence error
PGSERR
Write PGSERR=1
N/A
Data miss during fast programming error
MISSERR
Write MISSERR=1
N/A
Fast programming error
FASTERR
Write FASTERR=1
N/A
Interrupt event
1. EOP is set only if EOPIE is set.
2. OPERR is set only if ERRIE is set.
3.7
FLASH registers
3.7.1
FLASH access control register (FLASH_ACR)
Address offset: 0x000
Reset value: 0x0004 0600
s
31
Res.
30
Res.
29
Res.
28
Res.
27
Res.
26
Res.
25
Res.
24
Res.
23
Res.
22
Res.
21
Res.
20
Res.
19
18
17
16
Res.
DBG
_SWEN
Res.
EMPTY
rw
86/1325
RM0503 Rev 2
rw
RM0503
Embedded flash memory (FLASH)
15
14
13
12
11
10
9
8
7
6
5
4
3
Res.
Res.
Res.
Res.
ICRST
Res.
ICEN
PRFTEN
Res.
Res.
Res.
Res.
Res.
rw
rw
w
2
1
0
LATENCY[2:0]
rw
rw
rw
Bits 31:19 Reserved, must be kept at reset value.
Bit 18 DBG_SWEN: Debug access software enable
Software may use this bit to enable/disable the debugger read access.
0: Debugger disabled
1: Debugger enabled
Bit 17 Reserved, must be kept at reset value.
Bit 16 EMPTY: Main flash memory area empty
This bit indicates whether the first location of the main flash memory area is erased or has a
programmed value.
0: Main flash memory area programmed
1: Main flash memory area empty
The bit can be set and reset by software.
Bits 15:12 Reserved, must be kept at reset value.
Bit 11 ICRST: CPU Instruction cache reset
0: CPU Instruction cache is not reset
1: CPU Instruction cache is reset
This bit is write-only. It can be written only when the instruction cache is disabled. It is always
read as zero.
Bit 10 Reserved, must be kept at reset value.
Bit 9 ICEN: CPU Instruction cache enable
0: CPU Instruction cache is disabled
1: CPU Instruction cache is enabled
Bit 8 PRFTEN: CPU Prefetch enable
0: CPU Prefetch disabled
1: CPU Prefetch enabled
Bits 7:3 Reserved, must be kept at reset value.
Bits 2:0 LATENCY[2:0]: Flash memory access latency
The value in this bitfield represents the number of CPU wait states when accessing the flash
memory.
000: Zero wait states
001: One wait state
Other: Reserved
A new write into the bitfield becomes effective when it returns the same value upon read.
RM0503 Rev 2
87/1325
104
Embedded flash memory (FLASH)
3.7.2
RM0503
FLASH key register (FLASH_KEYR)
Address offset: 0x008
Reset value: 0x0000 0000
s
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
KEY[31:16]
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
KEY[15:0]
w
Bits 31:0 KEY[31:0]: FLASH key
The following values must be written consecutively to unlock the FLASH control register
(FLASH_CR), thus enabling programming/erasing operations:
KEY1: 0x4567 0123
KEY2: 0xCDEF 89AB
3.7.3
FLASH option key register (FLASH_OPTKEYR)
Address offset: 0x00C
Reset value: 0x0000 0000
s
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
OPTKEY[31:16]
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
w
w
w
w
w
w
w
w
w
w
w
w
w
w
OPTKEY[15:0]
w
w
Bits 31:0 OPTKEY[31:0]: Option byte key
The following values must be written consecutively to unlock the flash memory option
registers, enabling option byte programming/erasing operations:
KEY1: 0x0819 2A3B
KEY2: 0x4C5D 6E7F
3.7.4
FLASH status register (FLASH_SR)
Address offset: 0x010
Reset value: 0x000X 0000
es
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
OEM1
LOCK
Res.
CFGBSY
Res.
BSY1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
OEM2
LOCK
r
r
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OPTV
ERR
Res.
Res.
OEMOP
TWERR
HDP
OPT
WERR
Res.
FAST
ERR
MISS
ERR
PGS
ERR
SIZ
ERR
PGA
ERR
WRP
ERR
PROG
ERR
Res.
OP
ERR
EOP
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
88/1325
RM0503 Rev 2
r
r
RM0503
Embedded flash memory (FLASH)
Bits 31:22 Reserved, must be kept at reset value.
Bit 21 OEM2LOCK: OEM2 lock flag
This bit indicates that the OEM2 RDP key, read during the option byte loading, is not virgin.
When set, the OEM2 RDP lock mechanism is active.
Bit 20 OEM1LOCK: OEM1 lock flag
This bit indicates that the OEM1 RDP key, read during the option byte loading, is not virgin.
When set, the OEM1 RDP lock mechanism is active.
Bit 19 Reserved, must be kept at reset value.
Bit 18 CFGBSY: Programming or erase configuration busy flag
This flag is set and cleared by hardware. It is set when the first word is sent for program or
when setting the STRT bit of FLASH control register (FLASH_CR) for erase. It is cleared
when the flash memory program or erase operation completes or ends with an error.
When set, launching any other operation through the FLASH control register (FLASH_CR) is
impossible, and must be postponed (a programming or erase operation is ongoing).
When cleared, the program and erase settings in the FLASH control register (FLASH_CR)
can be modified.
Bit 17 Reserved, must be kept at reset value.
Bit 16 BSY1: Busy flag
This flag indicates that a flash memory operation requested by FLASH control register
(FLASH_CR) is in progress. This bit is set at the beginning of the flash memory operation,
and cleared when the operation finishes or when an error occurs.
Bit 15 OPTVERR: Option and engineering bits loading validity error flag
This flag is set by hardware when the options and engineering bits read may not be the one
configured by the user or production. If options and engineering bits haven’t been properly
loaded, OPTVERR is set again after each system reset. Option bytes that fail loading are
forced to a safe value, see Section 3.4.2: FLASH option byte programming.
It is cleared by programming it to 1.
Bits 14:13 Reserved, must be kept at reset value.
Bit 12 OEMOPTWERR: OEM options byte write error
This flag is set by hardware when the requested modifications of the OEM keys are not
allowed.
Bit 11 HDPOPTWERR: HDP option bytes write error
This flag is set by hardware when the requested HDP related option modifications are not
allowed. It is cleared by programming it to 1.
Bit 10 Reserved, must be kept at reset value.
Bit 9 FASTERR: Fast programming error flag
This flag is set by hardware when a fast programming sequence (activated by FSTPG) is
interrupted due to an error (alignment, size, write protection or data miss). The
corresponding status bit (PGAERR, SIZERR, WRPERR or MISSERR) is set at the same
time.
It is cleared by programming it to 1.
Bit 8 MISSERR: Fast programming data miss error flag
In Fast programming mode, 16 double words (128 bytes) must be sent to flash memory
successively, and the new data must be sent to the logic control before the current data is
fully programmed. MISSERR is set by hardware when the new data is not present in time.
It is cleared by programming it to 1.
RM0503 Rev 2
89/1325
104
Embedded flash memory (FLASH)
RM0503
Bit 7 PGSERR: Programming sequence error flag
This flag is set by hardware when a write access to the flash memory is performed by the
code while PG or FSTPG have not been set previously. Set also by hardware when
PROGERR, SIZERR, PGAERR, WRPERR, MISSERR or FASTERR is set due to a previous
programming error.
It is cleared by programming it to 1.
Bit 6 SIZERR: Size error flag
This flag is set by hardware when the size of the access is a byte or half-word during a
program or a fast program sequence. Only double word programming is allowed
(consequently: word access).
It is cleared by programming it to 1.
Bit 5 PGAERR: Programming alignment error flag
This flag is set by hardware when the data to program cannot be contained in the same
double word (64-bit) flash memory in case of standard programming, or if there is a change
of page during fast programming.
It is cleared by programming it to 1.
Bit 4 WRPERR: Write protection error flag
This flag is set by hardware when an address to be erased/programmed belongs to a writeprotected part (by WRP or RDP level 1) of the flash memory.
It is cleared by programming it to 1.
Bit 3 PROGERR: Programming error flag
This flag is set by hardware when a double-word address to be programmed contains a
value different from 0xFFFF FFFF before programming, except if the data to write is 0x0000
0000.
It is cleared by programming it to 1.
Bit 2 Reserved, must be kept at reset value.
Bit 1 OPERR: Operation error flag
This flag is set by hardware when a flash memory operation (program / erase) completes
unsuccessfully.
This bit is set only if error interrupts are enabled (ERRIE = 1).
It is cleared by programming it to 1.
Bit 0 EOP: End of operation flag
This flag is set by hardware when one or more flash memory operation (programming /
erase) has been completed successfully.
This bit is set only if the end of operation interrupts are enabled (EOPIE = 1).
It is cleared by programming it to 1.
90/1325
RM0503 Rev 2
RM0503
Embedded flash memory (FLASH)
3.7.5
FLASH control register (FLASH_CR)
Address offset: 0x014
Reset value: 0xC000 0000
Access: no wait state when no flash memory operation is ongoing; word, half-word, and byte
access.
This register must not be modified when the CFGBSY bit of the FLASH status register
(FLASH_SR) is set. Otherwise, this would result in:
31
30
LOCK
OPT
LOCK
•
a bus error, when the CFGBSY bit is set due to a double-word programming sequence,
and the write to the FLASH control register (FLASH_CR) is performed after the first
word sent for programming and before the second.
•
a bus stall, when the CFGBSY bit is set for any other reason.
29
28
27
Res.
Res.
OBL_
LAUNCH
26
Res.
rs
rs
15
14
13
12
rc_w1
11
10
Res.
Res.
Res.
Res.
Res.
Res.
25
24
ERRIE
EOPIE
rw
rw
9
8
23
22
21
20
19
Res.
Res.
Res.
Res.
Res.
7
6
5
4
3
PNB[6:0]
rw
rw
rw
rw
rw
rw
rw
18
17
16
FSTPG
OPT
STRT
STRT
rw
rs
rs
2
1
0
MER1
PER
PG
rw
rw
rw
Bit 31 LOCK: FLASH_CR Lock
This bit is set only. When set, the FLASH_CR register is locked. It is cleared by hardware
after detecting the unlock sequence.
In case of an unsuccessful unlock operation, this bit remains set until the next system reset.
Bit 30 OPTLOCK: Options Lock
This bit is set only. When set, all bits concerning user option in FLASH_CR register and so
option page are locked. This bit is cleared by hardware after detecting the unlock sequence.
The LOCK bit must be cleared before doing the unlock sequence for OPTLOCK bit.
In case of an unsuccessful unlock operation, this bit remains set until the next reset.
Bits 29:28 Reserved, must be kept at reset value.
Bit 27 OBL_LAUNCH: Option byte load launch
When set, this bit triggers the load of option bytes into option registers. It is automatically
cleared upon the completion of the load. The high state of the bit indicates pending option
byte load.
The bit cannot be cleared by software. It cannot be written as long as OPTLOCK is set.
Bit 26 Reserved, must be kept at reset value.
Bit 25 ERRIE: Error interrupt enable
This bit enables the interrupt generation upon setting the OPERR flag in the FLASH_SR
register.
0: Disable
1: Enable
Bit 24 EOPIE: End-of-operation interrupt enable
This bit enables the interrupt generation upon setting the EOP flag in the FLASH_SR register.
0: Disable
1: Enable
Bits 23:19 Reserved, must be kept at reset value.
RM0503 Rev 2
91/1325
104
Embedded flash memory (FLASH)
RM0503
Bit 18 FSTPG: Fast programming enable
0: Disable
1: Enable
Bit 17 OPTSTRT: Start of modification of option bytes
This bit triggers an options operation when set.
This bit is set only by software, and is cleared when the BSY1 bit is cleared in FLASH_SR.
Bit 16 STRT: Start erase operation
This bit triggers an erase operation when set.
This bit is possible to set only by software and to clear only by hardware. The hardware
clears it when one of BSY1 and BSY2 flags in the FLASH_SR register transits to zero.
Bits 15:10 Reserved, must be kept at reset value.
Bits 9:3 PNB[6:0]: Page number selection
These bits select the page to erase:
0x0:
page 0
0x1:
page 1
...
0xF:
page 15
Note: Values corresponding to addresses outside the main memory are not allowed.
Bit 2 MER1: Mass erase
When set, this bit triggers the mass erase, that is, all user pages.
Bit 1 PER: Page erase enable
0: Disable
1: Enable
Bit 0 PG: Flash memory programming enable
0: Disable
1: Enable
3.7.6
FLASH ECC register (FLASH_ECCR)
Address offset: 0x018
Reset value: 0x0000 0000
Access: no wait state when no flash memory operation is ongoing; word, half-word, and byte
access.
This register applies to single-bank products and to Bank 1 of dual-bank products.
31
30
ECCD
ECCC
rc_w1
rc_w1
15
14
Res.
Res.
29
Res.
Res.
27
Res.
26
Res.
25
Res.
24
ECCCIE
23
Res.
22
Res.
21
20
19
18
17
16
Res.
SYSF_
ECC
Res.
Res.
Res.
Res.
rw
13
12
11
10
9
8
r
7
6
5
4
3
2
1
0
r
r
r
r
r
r
ADDR_ECC[13:0]
r
92/1325
28
r
r
r
r
r
r
RM0503 Rev 2
r
RM0503
Embedded flash memory (FLASH)
Bit 31 ECCD: ECC detection
This flag is set by hardware when two ECC errors have been detected. When this bit is set, a
NMI is generated.
It is cleared by programming it to 1.
Bit 30 ECCC: ECC correction
This flag is set by hardware when one ECC error has been detected and corrected. An
interrupt is generated if ECCIE is set.
It is cleared by programming it to 1.
Bits 29:25 Reserved, must be kept at reset value.
Bit 24 ECCCIE: ECC correction interrupt enable
0: ECCC interrupt disabled
1: ECCC interrupt enabled
Bits 23:21 Reserved, must be kept at reset value.
Bit 20 SYSF_ECC: System flash memory ECC fail
This bit indicates that the ECC error correction or double ECC error detection is located in
the system flash memory.
Bits 19:14 Reserved, must be kept at reset value.
Bits 13:0 ADDR_ECC[13:0]: ECC fail double-word address offset
In case of ECC error or ECC correction detected, this bitfield contains double-word offset
(multiple of 64 bits) to main flash memory.
3.7.7
FLASH option register (FLASH_OPTR)
Address offset: 0x020
Reset value: 0xXXXX XXXX (The option bits are loaded with values from flash memory at
power-on reset release.)
Access: no wait state when no flash memory operation is ongoing; word, half-word, and byte
access
31
30
29
Res.
Res.
IRHEN
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
Res.
Res.
NRST_ NRST_ NRST_
SHDW STDBY STOP
rw
rw
rw
28
27
26
25
24
23
N
N
NRST_MODE
NBOOT
BOOT BOOT
[1:0]
_SEL
0
1
22
BKPSRAM
RAM_
_HW_
PARITY_
ERASE_
CHECK
DISABLE
21
20
BDRST
Res.
BOR_LEV[2:0]
rw
rw
rw
19
18
17
16
WWDG IWDG
IWDG
_SW _STDBY _STOP
4
IWDG
_SW
rw
rw
rw
rw
3
2
1
0
rw
rw
rw
rw
RDP[7:0]
rw
rw
rw
rw
Bits 31:30 Reserved, must be kept at reset value.
Bit 29 IRHEN: Internal reset holder enable bit
0: Internal resets are propagated as simple pulse on NRST pin
1: Internal resets drives NRST pin low until it is seen as low level
RM0503 Rev 2
93/1325
104
Embedded flash memory (FLASH)
RM0503
Bits 28:27 NRST_MODE[1:0]: NRST pin configuration
00: Reserved
01: Reset input only: a low level on the NRST pin generates system reset; internal RESET
is not propagated to the NRST pin.
10: Standard GPIO: only internal RESET is possible
11: Bidirectional reset: the NRST pin is configured in reset input/output (legacy) mode
Bit 26 NBOOT0: NBOOT0 option bit
0: NBOOT0 = 0
1: NBOOT0 = 1
Bit 25 NBOOT1: Boot configuration
Together with the BOOT0 pin or option bit NBOOT0 (depending on NBOOT_SEL option bit
configuration), this bit selects boot mode from the main flash memory, SRAM or the system
memory. Refer to Section 2.5: Boot configuration.
Bit 24 NBOOT_SEL: BOOT0 signal source selection
This option bit defines the source of the BOOT0 signal.
0: BOOT0 pin (legacy mode)
1: NBOOT0 option bit
Bit 23 BKPSRAM_HW_ERASE_DISABLE: Backup SRAM erase prevention
0: Backup SRAM is erased on system reset
1: Backup SRAM content is kept when a system reset occurs
The bit has no influence on other Backup SRAM erase requests, such as tamper or RDP
regression.
Bit 22 RAM_PARITY_CHECK: SRAM parity check control enable/disable
0: Enable
1: Disable
Bit 21 BDRST: Backup domain reset
0: Backup domain not reset on shutdown exit
1: Reset of backup domain (RTC registers and backup registers) forced on shutdown exit
Bit 20 Reserved, must be kept at reset value.
Bit 19 WWDG_SW: Window watchdog selection
0: Hardware window watchdog
1: Software window watchdog
Bit 18 IWDG_STDBY: Independent watchdog counter freeze in Standby mode
0: Independent watchdog counter is frozen in Standby mode
1: Independent watchdog counter is running in Standby mode
Bit 17 IWDG_STOP: Independent watchdog counter freeze in Stop mode
0: Independent watchdog counter is frozen in Stop mode
1: Independent watchdog counter is running in Stop mode
Bit 16 IWDG_SW: Independent watchdog selection
0: Hardware independent watchdog
1: Software independent watchdog
Bit 15 NRST_SHDW: Reset generated when entering Shutdown mode
0: Reset generated when entering the Shutdown mode
1: No reset generated when entering the Shutdown mode
94/1325
RM0503 Rev 2
RM0503
Embedded flash memory (FLASH)
Bit 14 NRST_STDBY: Reset generated when entering Standby mode
0: Reset generated when entering the Standby mode
1: No reset generate when entering the Standby mode
Bit 13 NRST_STOP: Reset generated when entering Stop mode
0: Reset generated when entering the Stop mode
1: No reset generated when entering the Stop mode
Bits 12:11 Reserved, must be kept at reset value.
Bits 10:8 BOR_LEV[2:0]: BOR reset level
This bitfield contains the VDD supply level threshold that activates/releases the reset.
000: BOR level 0, reset level threshold around 1.7 V
001: BOR level 1, reset level threshold around 2.0 V
010: BOR level 2, reset level threshold around 2.2 V
011: BOR level 3, reset level threshold around 2.5 V
100: BOR level 4, reset level threshold around 2.8 V
Bits 7:0 RDP[7:0]: Read protection level
0xAA: Level 0, read protection not active
0xCC: Level 2, chip read protection active
Others: Level 1, memories read protection active
3.7.8
FLASH WRP area A address register (FLASH_WRP1AR)
Address offset: 0x02C
Reset value: 0x000X 000X (the option bits are loaded with values from flash memory at
power-on reset release.)
Access: no wait state when no flash memory operation is ongoing; word, half-word, and byte
access.
31
30
29
28
27
26
25
24
23
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
22
21
20
19
18
17
16
WRP1A_END[6:0]
rw
rw
rw
rw
rw
rw
rw
6
5
4
3
2
1
0
rw
rw
WRP1A_STRT[6:0]
rw
rw
rw
rw
rw
Bits 31:23 Reserved, must be kept at reset value.
Bits 22:16 WRP1A_END[6:0]: WRP area A end offset
This bitfield contains the offset of the last page of the WRP area A.
Note: The number of effective bits depends on the size of the flash memory in the device.
Bits 15:7 Reserved, must be kept at reset value.
Bits 6:0 WRP1A_STRT[6:0]: WRP area A start offset
This bitfield contains the offset of the first page of the WRP area A.
Note: The number of effective bits depends on the size of the flash memory in the device.
RM0503 Rev 2
95/1325
104
Embedded flash memory (FLASH)
3.7.9
RM0503
FLASH WRP area B address register (FLASH_WRP1BR)
Address offset: 0x030
Reset value: 0x000X 000X (the option bits are loaded with values from flash memory at
power-on reset release.)
Access: no wait state when no flash memory operation is ongoing; word, half-word, and byte
access.
31
30
29
28
27
26
25
24
23
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
22
15
14
13
12
11
10
9
8
7
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
21
20
19
18
17
16
WRP1B_END[6:0]
rw
rw
rw
rw
rw
rw
rw
6
5
4
3
2
1
0
rw
rw
WRP1B_STRT[6:0]
rw
rw
rw
rw
rw
Bits 31:23 Reserved, must be kept at reset value.
Bits 22:16 WRP1B_END[6:0]: WRP area B end offset
This bitfield contains the offset of the last page of the WRP area B.
Note: The number of effective bits depends on the size of the flash memory in the device.
Bits 15:7 Reserved, must be kept at reset value.
Bits 6:0 WRP1B_STRT[6:0]: WRP area B start offset
This bitfield contains the offset of the first page of the WRP area B.
Note: The number of effective bits depends on the size of the flash memory in the device.
3.7.10
FLASH security register (FLASH_SECR)
Address offset: 0x080
Reset value: 0bXXXX XXXX 0000 000X 0000 0000 0XXX XXXX (the option bits are loaded
with values from flash memory at power-on reset release.)
Access: no wait state when no flash memory operation is ongoing; word, half-word access.
31
30
29
28
rw
rw
rw
rw
15
14
13
Res.
Res.
Res.
27
26
25
24
23
22
21
20
19
18
17
16
rw
rw
rw
rw
Res.
Res.
Res.
Res.
Res.
Res.
Res.
BOOT_LOCK
12
11
10
9
8
7
6
5
4
3
2
1
Res.
Res.
Res.
Res.
0
Res.
Res.
rw
rw
HDP1EN[7:0]
rw
HDP1_PEND[6:0]
rw
96/1325
RM0503 Rev 2
rw
rw
rw
rw
RM0503
Embedded flash memory (FLASH)
Bits 31:24 HDP1EN[7:0]: Hide protection area enable
0xB4: no HDP area
Others: HDP area enabled
Bits 23:17 Reserved, must be kept at reset value.
Bit 16 BOOT_LOCK: Forced boot from user area
0: Boot based on the pad/option bit configuration
1: Boot forced from main flash memory
Caution: If BOOT_LOCK is set in association with RDP Level 1, the debug capabilities of the
device are stopped, and the reset value of the DBG_SWEN bit of the FLASH_ACR
register becomes zero. If the DBG_SWEN bit is cleared by the application code
after reset, there is no way to recover from this situation.
Bits 15:7 Reserved, must be kept at reset value.
Bits 6:0 HDP1_PEND[6:0]: Last page of the first hide protection area
This bitfield contains the last page of the HDP area.
3.7.11
FLASH OEM1 key register 1 (FLASH_OEM1KEYR1)
Address offset: 0x088
Reset value: 0xFFFF FFFF
Access: no wait state when no flash memory operation is ongoing; word, half-word access.
31
30
29
28
27
26
25
24
23
w
w
w
w
w
w
w
w
w
15
14
13
12
11
10
9
8
7
22
21
20
19
18
17
16
w
w
w
w
w
w
w
6
5
4
3
2
1
0
w
w
w
w
w
w
w
OEM1KEY[31:16]
OEM1KEY[15:0]
w
w
w
w
w
w
w
w
w
Bits 31:0 OEM1KEY[31:0]: Bits 31 to 0 of the OEM1 key
All bits are write-only and always read as zero.
3.7.12
FLASH OEM1 key register 2 (FLASH_OEM1KEYR2)
Address offset: 0x08C
Reset value: 0xFFFF FFFF
Access: no wait state when no option bytes modification is ongoing; word, half-word, and
byte access
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
OEM1KEY[63:48]
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
w
w
w
w
w
w
w
OEM1KEY[47:32]
w
w
w
w
w
w
w
w
w
RM0503 Rev 2
97/1325
104
Embedded flash memory (FLASH)
RM0503
Bits 31:0 OEM1KEY[63:32]: Bits 63 to 32 of the OEM1 key
All bits are write-only and always read as zero.
3.7.13
FLASH OEM1 key register 3 (FLASH_OEM1KEYR3)
Address offset: 0x090
Reset value: 0xFFFF FFFF
Access: no wait state when no option bytes modification is ongoing; word, half-word, and
byte access
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
OEM1KEY[95:80]
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
w
w
w
w
w
w
w
w
w
w
w
w
w
w
OEM1KEY[79:64]
w
w
Bits 31:0 OEM1KEY[95:64]: Bits 95 to 64 of the OEM1 key
All bits are write-only and always read as zero.
3.7.14
FLASH OEM1 key register 4 (FLASH_OEM1KEYR4)
Address offset: 0x094
Reset value: 0xFFFF FFFF
Access: no wait state when no option bytes modification is ongoing; word, half-word, and
byte access
31
30
29
28
27
26
25
24
w
w
w
w
w
w
w
w
15
14
13
12
11
10
9
8
23
22
21
20
19
18
17
16
w
w
w
w
w
w
w
w
7
6
5
4
3
2
1
0
w
w
w
w
w
w
w
OEM1KEY[127:112]
OEM1KEY[111:96]
w
w
w
w
w
w
w
w
w
Bits 31:0 OEM1KEY[127:96]: Bits 127 to 96 of the OEM1 key
All bits are write-only and always read as zero.
3.7.15
FLASH OEM2 key register 1 (FLASH_OEM2KEYR1)
Address offset: 0x098
Reset value: 0xFFFF FFFF
Access: no wait state when no flash memory operation is ongoing; word, half-word access.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
w
w
w
w
w
w
OEM2KEY[31:16]
w
98/1325
w
w
w
w
w
w
w
w
w
RM0503 Rev 2
RM0503
15
Embedded flash memory (FLASH)
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
w
w
w
w
w
w
w
OEM2KEY[15:0]
w
w
w
w
w
w
w
w
w
Bits 31:0 OEM2KEY[31:0]: Bits 31 to 0 of the OEM2 key
All bits are write-only and always read as zero.
3.7.16
FLASH OEM2 key register 2 (FLASH_OEM2KEYR2)
Address offset: 0x09C
Reset value: 0xFFFF FFFF
Access: no wait state when no option bytes modification is ongoing; word, half-word, and
byte access
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
OEM2KEY[63:48]
w
w
w
w
w
w
w
15
14
13
12
11
10
9
w
w
w
w
w
w
w
w
w
8
7
6
5
4
3
2
1
0
w
w
w
w
w
w
w
OEM2KEY[47:32]
w
w
w
w
w
w
w
w
w
Bits 31:0 OEM2KEY[63:32]: Bits 63 to 32 of the OEM2 key
All bits are write-only and always read as zero.
3.7.17
FLASH OEM2 key register 3 (FLASH_OEM2KEYR3)
Address offset: 0x0A0
Reset value: 0xFFFF FFFF
Access: no wait state when no option bytes modification is ongoing; word, half-word, and
byte access
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
OEM2KEY[95:80]
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
w
w
w
w
w
w
w
w
w
w
w
w
w
w
OEM2KEY[79:64]
w
w
Bits 31:0 OEM2KEY[95:64]: Bits 95 to 64 of the OEM2 key
All bits are write-only and always read as zero.
RM0503 Rev 2
99/1325
104
Embedded flash memory (FLASH)
3.7.18
RM0503
FLASH OEM2 key register 4 (FLASH_OEM2KEYR4)
Address offset: 0x0A4
Reset value: 0xFFFF FFFF
Access: no wait state when no option bytes modification is ongoing; word, half-word, and
byte access
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
OEM2KEY[127:112]
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
w
w
w
w
w
w
w
OEM2KEY[111:96]
w
w
w
w
w
w
w
w
w
Bits 31:0 OEM2KEY[127:96]: Bits 127 to 96 of the OEM2 key
All bits are write-only and always read as zero.
3.7.19
FLASH OEM key status register (FLASH_OEMKEYSR)
Address offset: 0x0A8
Reset value: 0x00XX 00XX (where XX represent the CRC value calculated from the current
OEM keys)
Access: no wait state when no flash memory operation is ongoing; word, half-word access.
31
30
29
28
27
26
25
24
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
23
22
21
20
19
18
17
16
OEM2KEYCRC[7:0]
r
r
r
7
6
5
r
r
r
r
r
4
3
2
1
0
r
r
OEM1KEYCRC[7:0]
r
r
r
r
r
r
Bits 31:24 Reserved, must be kept at reset value.
Bits 23:16 OEM2KEYCRC[7:0]: 8-bit CRC value calculated from the OEM2 key
This bitfield contains the read-only 8-bit CRC value calculated from the OEM2 128-bit key.
This value is calculated using the following CRC parameters:
Polynomial = 0x7
Initial value = 0x0 (128 bits)
Final XoR = 0x5
Bits 15:8 Reserved, must be kept at reset value.
Bits 7:0 OEM1KEYCRC[7:0]: 8-bit CRC value calculated from the OEM1 key
This bitfield contains the read-only 8-bit CRC value calculated from the OEM1 128-bit key.
This value is calculated using the following CRC parameters:
Polynomial = 0x7
Initial value = 0x0 (128 bits)
Final XoR = 0x5
100/1325
RM0503 Rev 2
RM0503
Embedded flash memory (FLASH)
3.7.20
FLASH HDP control register (FLASH_HDPCR)
Address offset: 0x0AC
Reset value: 0x00A3 00A3
Access: no wait state when no flash memory operation is ongoing; word, half-word access.
31
30
29
28
27
26
25
24
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
23
22
21
20
19
18
17
16
HDP1EXT_ACCDIS[7:0]
rw
rw
rw
rw
rw
rw
rw
rw
7
6
5
4
3
2
1
0
rw
rw
HDP1_ACCDIS[7:0]
rw
rw
rw
rw
rw
rw
Bits 31:24 Reserved, must be kept at reset value.
Bits 23:16 HDP1EXT_ACCDIS[7:0]: HDP1 extension area access disable
The access to this register depends on its current value. Refer to Section 3.5.4: Securable
memory area extension (HDP extension) for the full conditions.
0xA3: Access to HDP1 extension area is granted
0x5C: Access to HDP1 extension area is denied, but incrementing HDP1_EXT[6:0] of
FLASH_HDPEXTR register is allowed at any time (modifying
HDP1EN[7:0]/HDP1_PEND[7:0] option bytes is not allowed)
Others: Access to HDP1 extension area is denied, and updating the size of HDP1 extension
area is not possible since writing to HDP1_EXT[6:0] is denied (modifying
HDP1EN[7:0]/HDP1_PEND[7:0] option bytes is not allowed).
Bits 15:8 Reserved, must be kept at reset value.
Bits 7:0 HDP1_ACCDIS[7:0]: HDP1 area access disable
When set to a value different from 0xA3, this bitfield cannot be modified except by a system
reset. In this case, any write access to HDP1_ACCDIS[7:0] is ignored.
0xA3: Access to HDP1 area granted
Others: Access to HDP1 area denied (modifying HDP1EN[7:0]/HDP1_PEND[7:0] option
bytes is not allowed).
3.7.21
FLASH HDP extension register (FLASH_HDPEXTR)
Address offset: 0x0B0
Reset value: 0x0000 0000
Access: no wait state when no flash memory operation is ongoing; word, half-word access.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
6
5
4
3
2
1
0
rw
rw
15
14
13
12
11
10
9
8
7
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
HDP1_EXT[6:0]
rw
RM0503 Rev 2
rw
rw
rw
rw
101/1325
104
Embedded flash memory (FLASH)
RM0503
Bits 31:7 Reserved, must be kept at reset value.
Bits 6:0 HDP1_EXT[6:0]: HDP1 extension area size
Size of the HDP1 extension area expressed in number of 2-Kbyte pages. The extension
starts at page offset HDP1_PEND[7:0] + 1.
Register access depends on the value of HDP1EXT_ACCDIS[7:0] in the FLASH_HDPCR
register.
102/1325
RM0503 Rev 2
0x034 0x07F
Reserved
Reset value
X
X
X
X
RM0503 Rev 2
X
X
X
X
X
X
X
X
Res.
X
Res.
Res.
Res.
Res.
Res.
Res.
0
0
0
0
0
0
0
0
0
0
0
0
Res.
Res.
0
0
0
0
0
0
0
X
X
X
X
EOP
0
OPERR
0
0
0
PG
0
PER
PROGERR
0
MER1
WRPERR
MISERR
PGSERR
PNB[6:0]
FASTERR
Res.
PGAERR
ADDR_ECC[13:0]
0
0
X
X
X
Res.
X
0
Res.
Res.
0
SIZERR
0
Res.
0
Res.
0
0
Res.
Res.
0
0
Res.
Res.
0
0
Res.
Res.
0
0
Res.
Res.
0
0
Res.
X
Res.
Res.
0
0
Res.
X
Res. Res.
Res.
0
HDPOPTWERR
0
Res.
Res.
0
OEMOPTWERR
0
Res.
Res.
0
0
Res.
X
Res. Res.
0
PRFTEN
Res.
Res.
Res.
Res.
Res.
ICEN
Res.
ICRST
Res.
Res.
Res.
Res.
EMPTY
Res.
DBG_SWEN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
0
Res.
0
1
Res.
0
BOR_LEV[2:0]
Res.
OPTKEY[31:0]
0
0
Res.
0
Res.
KEYR[31:0]
0
0
Res. Res.
0
Res. Res.
0
Res.
0
Res.
0
X
Res.
Res.
0
Res.
0
0
0
Res.
X
0
Res.
0
0
Res. Res.
0
Res.
0
Res.
Res.
0
Res.
Res.
0
Res.
X
0
Res.
Res.
0
OPTVERR
STRT
0
Res.
Res.
0
Res.
OPTSTRT
0
Res.
FLASH_OPT
KEYR
X
Res.
CFGBSY
Res.
0
Res.
X
Res. Res.
Res.
Res.
0
BSY1
FSTPG
0
Res.
Res.
Res.
0
Res.
FLASH_SR
Res.
Res.
0
Res.
0
Res.
Res.
0
Res. Res.
NRST_STOP
X
Res. Res.
0
Res.
Res.
0
Res.
NRST_SHDW
NRST_STDBY
X
Res. Res.
0
Res.
Res.
0
Res.
IWDG_SW
X
Res.
0
Res.
Res.
0
Res.
IWDG_STOP
X
Res.
0
Res.
Res.
0
Res.
IWDG_STBY
X
Res.
Res.
0
OEM1LOCK
0
Res.
0
OEM2LOCK
0
Res.
0
Res.
Res.
0
Res.
WWDG_SW
X
Res.
SYSF_ECC
Res.
Res.
0
Res.
Res.
FLASH_KEYR
Res.
Res. Res.
Res.
Res.
0
Res.
1
Res.
X
Res. Res.
Res.
0
Res.
Reset value
Res.
X
Res.
BDRST
X
Res.
RAM_PARITY_CHECK
X
Res. Res.
EOPIE
ECCCIE
0
0
Res.
BKPSRAM_HW_ERASE_DISABLE
X
Res.
NBOOT_SEL
X
Res. Res.
ERRIE
Res.
Res.
Res.
Reset value
0
Res.
Res. Res.
Res.
NBOOT1
X
Res. Res.
0
Res.
Res.
Res.
Res.
Res.
.NBOOT0
OBL_LAUNCH
Reset value
Res.
WRP1B_END
[3:0]
X
Res. Res.
Res.
0
Res.
X
FLASH_
WRP1BR
NRST_MODE[1:0]
Res.
Res.
0
Res.
Res.
Reset value
X
Res. Res.
Res.
Res.
0
Res.
WRP1A_END
[3:0]
Res.
FLASH_
WRP1AR
Res.
Reserved
Res.
Reset value
IRHEN
FLASH_OPTR
Res. Res.
0
Res. Res.
0
Res.
Reset value
Res.
LOCK
FLASH_ECCR
Res.
0x030
1
Res.
0x02C
1
Res.
0x024 0x028
OPTLOCK
0x020
Reset value
ECCC
0x018
FLASH_CR
ECCD
0x014
Res.
0x010
Res.
0x00C
Reset value
Res. Res.
0x008
Reserved
Res. Res.
0x004
FLASH_ACR
Res.
0x000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Register
Res.
Offset
Res.
3.7.22
Res.
RM0503
Embedded flash memory (FLASH)
FLASH register map
Table 19. FLASH register map and reset values
LATENCY
[2:0]
0
0
0
0
0
0
RDP[7:0]
WRP1A_STRT[6:0]
X
X
X
WRP1B_STRT[6:0]
103/1325
104
Embedded flash memory (FLASH)
RM0503
HDP1_PEND[6:0]
Res.
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
OEM1KEY[95:64]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
OEM1KEY[127:96]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
OEM2KEY[31:0]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
OEM2KEY[63:32]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
OEM2KEY[95:64]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Res.
Res.
Res.
X
0
1
0
0
0
1
1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
HDP1EXT_ACCDIS[7:0]
1
OEM1KEYCRC[7:0]
Reset value
0
RM0503 Rev 2
X
X
X
X
X
1
0
0
0
1
1
HDP1_EXT[6:0]
0
Refer to Section 2.2 on page 55 for the register boundary addresses.
X
HDP1_ACCDIS[7:0]
1
Res.
X
X
Res.
X
X
Res.
X
X
Res.
X
X
Res.
X
X
Res.
Res.
OEM2KEYCRC[7:0]
Res.
Res.
X
Res.
Res.
X
Res.
Res.
Res.
Res.
Res.
Res.
X
Res.
Res.
Res.
Res.
X
Res.
Res.
X
X
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
Res.
X
X
Res.
Res.
Res.
Res.
Reset value
X
Res.
FLASH_KEYSR
X
Res.
X
Res.
X
Res.
X
Res.
X
Res.
X
Res.
OEM2KEY[127:96]
X
104/1325
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
X
X
0x0B0
Res.
X
X
FLASH_
HDPEXTR
Res.
X
OEM1KEY[63:32]
Reset value
FLASH_HDPCR
BOOT_LOCK
Res.
Res.
Res.
Res.
Res.
X
FLASH_
OEM2KEYR4
0x0A4
0x0AC
X
Res.
Reset value
Res.
X
FLASH_
OEM2KEYR3
0x0A0
Res.
X
Res.
Reset value
Res.
X
FLASH_
OEM2KEYR2
0x09C
X
Res.
X
Res.
Reset value
X
Res.
X
FLASH_
OEM2KEYR1
0x098
X
Res.
X
Res.
Reset value
X
Res.
X
FLASH_
OEM1KEYR4
0x094
X
Res.
Res.
Reset value
0x0A8
X
FLASH_
OEM1KEYR3
0x090
X
Res.
Res.
Reset value
X
OEM1KEY[31:0]
FLASH_
OEM1KEYR2
0x08C
Res.
Res.
Reset value
Res.
Res.
FLASH_
OEM1KEYR1
Res.
Res.
0x088
X
Res.
X
Res.
X
Res.
X
Res.
X
Res.
X
Res.
X
Res.
Res.
X
Res.
X
Reserved
Res.
Reset value
0x084
Res.
FLASH_SECR
Res.
0x080
Register
HDP1EN[7:0]
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 19. FLASH register map and reset values (continued)
0
0
0
0
0
0
RM0503
Power control (PWR)
4
Power control (PWR)
4.1
Power supplies
The STM32U0 series devices require a 1.71 V to 3.6 V operating supply voltage (VDD).
Several peripherals are supplied through independent power domains: VDDA, VDDUSB,
VLCD. Those supplies must not be provided without a valid operating supply on the VDD pin.
•
VDD = 1.71 V to 3.6 V
VDD is the external power supply for the I/Os, the internal regulator and the system
analog such as reset, power management and internal clocks. It is provided externally
through VDD pins.
•
VDDA = 1.62 V (ADCs/COMPs) / 1.86 V (DACs/OPAMPs) / 2.4 V (VREFBUF) to 3.6 V.
VDDA is the external analog power supply for A/D converters, D/A converters, voltage
reference buffer, operational amplifiers and comparators. The VDDA voltage level is
independent from the VDD voltage. VDDA should be preferably connected to VDD
when these peripherals are not used.
•
VDDUSB = 3.0 V to 3.6 V (available on STM32U0x3xx devices only)
VDDUSB is the external independent power supply for USB transceivers. The VDDUSB
voltage level is independent from the VDD voltage. VDDUSB should be preferably
connected to VDD when the USB is not used.
•
VLCD = 2.5 V to 3.6 V (available on STM32U0x3xx devices only)
The LCD controller can be powered either externally through VLCD pin, or internally
from an internal voltage generated by the embedded step-up converter. VLCD is
multiplexed with PC3 which can be used as GPIO when the LCD is not used.
•
VBAT = 1.55 V to 3.6 V
VBAT is the power supply for RTC, external clock 32 kHz oscillator and backup registers
(through power switch) when VDD is not present.
VBAT is internally bonded to VDD for small packages without dedicated pin.
•
VREF-, VREF+
VREF+ is the input reference voltage for ADCs and DACs. It is also the output of the
internal voltage reference buffer when enabled.
When VDDA < 2 V, VREF+ must be equal to VDDA.
When VDDA ≥ 2 V, VREF+ must be between 2 V and VDDA.
VREF+ can be grounded when ADC and DAC are not active.
The internal voltage reference buffer supports two output voltages, which are
configured with VRS bit in the VREFBUF_CSR register:
–
VREF+ around 2.048 V. This requires VDDA equal to or higher than 2.4 V.
–
VREF+ around 2.5 V. This requires VDDA equal to or higher than 2.8 V.
VREF- and VREF+ pins are not available on all packages. When not available on the
package, they are bonded to VSSA and VDDA, respectively.
When the VREF+ is double-bonded with VDDA in a package, the internal voltage
reference buffer is not available and must be kept disabled (refer to related device
datasheet for packages pinout description).
VREF- must always be equal to VSSA.
RM0503 Rev 2
105/1325
150
Power control (PWR)
RM0503
An embedded linear voltage regulator is used to supply the internal digital power VCORE.
VCORE is the power supply for digital peripherals and memories.
Figure 6. Power supply overview
VDDA domain
VDDA
VSSA
A/D converters
Comparators
D/A converters
Operational amplifiers
Voltage reference buffer
(1)
(1)
VLCD
LCD
VDDUSB
VSS
USB transceivers
VDD domain
VDD
VDDIO1
I/O ring
Reset block
Temp. sensor
PLL, HSI, MSI, HSI48
VSS
Standby circuitry
(Wakeup logic, IWDG)
Voltage regulator
VCORE domain
Core
Memories
Digital peripherals
Low voltage detector
Backup domain
VBAT
LSE crystal 32 K osc
BKP registers
RCC BDCR register
RTC
MSv71800V1
1. Available on STM32U0x3xx devices only.
4.1.1
Independent analog peripherals supply
To improve ADC and DAC conversion accuracy and to extend the supply flexibility, the
analog peripherals have an independent power supply which can be separately filtered and
shielded from noise on the PCB.
•
The analog peripherals voltage supply input is available on a separate VDDA pin.
•
An isolated supply ground connection is provided on VSSA pin.
The VDDA supply voltage can be different from VDD. The presence of VDDA must be checked
before enabling any of the analog peripherals supplied by VDDA (A/D converter, D/A
converter, comparators, operational amplifier, voltage reference buffer).
106/1325
RM0503 Rev 2
RM0503
Power control (PWR)
The VDDA supply can be monitored by the Peripheral Voltage Monitoring, and compared
with two thresholds (1.65 V for PVM3 or 1.86 V for PVM4), refer to Section 4.2.3: Peripheral
Voltage Monitoring (PVM) for more details.
When a single supply is used, VDDA can be externally connected to VDD through the
external filtering circuit in order to ensure a noise-free VDDA reference voltage.
ADC and DAC reference voltage
To ensure a better accuracy on low-voltage inputs and outputs, the user can connect to
VREF+ a separate reference voltage lower than VDDA. VREF+ is the highest voltage,
represented by the full scale value, for an analog input (ADC) or output (DAC) signal.
VREF+ can be provided either by an external reference or by an internal buffered voltage
reference (VREFBUF), except for packages on which VREF+ is bonded with VDDA.
The internal voltage reference is enabled by setting the ENVR bit in the Section 16.3.1:
VREFBUF control and status register (VREFBUF_CSR). The voltage reference is set to
2.5 V when the VRS bit is set and to 2.048 V when the VRS bit is cleared. The internal
voltage reference can also provide the voltage to external components through VREF+ pin.
Refer to the device datasheet and to Section 16: Voltage reference buffer (VREFBUF) for
further information.
4.1.2
Independent USB transceivers supply
This section is applicable to STM32U0x3xx devices only.
The USB transceivers are supplied from a separate VDDUSB power supply pin. VDDUSB
range is from 3.0 V to 3.6 V and is completely independent from VDD or VDDA.
After reset, the USB features supplied by VDDUSB are logically and electrically isolated and
therefore are not available. The isolation must be removed before using the USB FS
peripheral, by setting the USV bit in the PWR_CR2 register, once the VDDUSB supply is
present.
The VDDUSB supply is monitored by the Peripheral Voltage Monitoring (PVM1) and
compared with the internal reference voltage (VREFINT, around 1.2 V), refer to Section 4.2.3:
Peripheral Voltage Monitoring (PVM) for more details.
4.1.3
Independent LCD supply
This section is applicable to STM32U03xx devices only.
The VLCD pin is provided to control the contrast of the glass LCD. This pin can be used in
two ways:
•
It can receive from an external circuitry the desired maximum voltage that is provided
on segment and common lines to the glass LCD by the microcontroller.
•
It can also be used to connect an external capacitor that is used by the microcontroller
for its voltage step-up converter. This step-up converter is controlled by software to
provide the desired voltage to segment and common lines of the glass LCD.
The voltage provided to segment and common lines defines the contrast of the glass LCD
pixels. This contrast can be reduced when you configure the dead time between frames.
•
When an external power supply is provided to the VLCD pin, it should range from 2.5 V
to 3.6 V. It does not depend on VDD.
•
When the LCD is based on the internal step-up converter, the VLCD pin should be
RM0503 Rev 2
107/1325
150
Power control (PWR)
RM0503
connected to a capacitor (see the product datasheet for further information).
4.1.4
Battery backup domain
To retain the content of the Backup registers and supply the RTC function when VDD is
turned off, the VBAT pin can be connected to an optional backup voltage supplied by a
battery or by another source.
VBAT pin is not available on low pin-count packages, VBAT is internally connected to VDD.
The VBAT pin powers the RTC unit, the LSE oscillator and the PC13 to PC15 I/Os, allowing
the RTC to operate even when the main power supply is turned off. The switch to the VBAT
supply is controlled by the power-down reset embedded in the Reset block.
Warning:
During tRSTTEMPO (temporization at VDD startup) or after a PDR
has been detected, the power switch between VBAT and VDD
remains connected to VBAT.
During the startup phase, if VDD is established in less than
tRSTTEMPO (refer to the datasheet for the value of tRSTTEMPO)
and VDD > VBAT + 0.6 V, a current may be injected into VBAT
through an internal diode connected between VDD and the
power switch (VBAT).
If the power supply/battery connected to the VBAT pin cannot
support this current injection, it is strongly recommended to
connect an external low-drop diode between this power
supply and the VBAT pin.
If no external battery is used in the application, it is recommended to connect VBAT
externally to VDD with a 100 nF external ceramic decoupling capacitor.
When the backup domain is supplied by VDD (analog switch connected to VDD), the
following pins are available:
Note:
•
PC13, PC14 and PC15, which can be used as GPIO pins
•
PC13, PC14 and PC15, which can be configured by RTC or LSE (refer to Section 30.3:
RTC functional description on page 900)
•
PA0/RTC_TAMP2 and PE6/RTC_TAMP3 when they are configured by the RTC as
tamper pins
Due to the fact that the analog switch can transfer only a limited amount of current (3 mA),
the use of GPIO PC13 to PC15 in output mode is restricted: the speed has to be limited to
2 MHz with a maximum load of 30 pF and these I/Os must not be used as a current source
(e.g. to drive a LED).
When the backup domain is supplied by VBAT (analog switch connected to VBAT because
VDD is not present), the following functions are available:
108/1325
•
PC13, PC14 and PC15 can be controlled only by RTC or LSE (refer to Section 30.3:
RTC functional description on page 900)
•
PA0/RTC_TAMP2 and PE6/RTC_TAMP3 when they are configured by the RTC as
tamper pins
RM0503 Rev 2
RM0503
Power control (PWR)
Backup domain access
After a system reset, the backup domain (RTC registers and backup registers) is protected
against possible unwanted write accesses. To enable access to the backup domain,
proceed as follows:
1.
Enable the power interface clock by setting the PWREN bits in the Section 5.2.18:
Peripheral clock enable registers
2.
Set the DBP bit in the Power control register 1 (PWR_CR1) to enable access to the
backup domain
3.
Select the RTC clock source in the RTC domain control register (RCC_BDCR).
4.
Enable the RTC clock by setting the RTCEN [15] bit in the RTC domain control register
(RCC_BDCR).
VBAT battery charging
When VDD is present, It is possible to charge the external battery on VBAT through an
internal resistance.
The VBAT charging is done either through a 5 kOhm resistor or through a 1.5 kOhm resistor
depending on the VBRS bit value in the PWR_CR4 register.
The battery charging is enabled by setting VBE bit in the PWR_CR4 register. It is
automatically disabled in VBAT mode.
4.1.5
Voltage regulator
Two embedded linear voltage regulators supply all the digital circuitries, except for the
Standby circuitry and the backup domain. The main regulator output voltage (VCORE) can be
programmed by software to two different power ranges (Range 1 and Range 2) in order to
optimize the consumption depending on the system’s maximum operating frequency (refer
to Section 5.2.9: Clock source frequency versus voltage scaling and to Section 3.3.4:
FLASH read access latency.
The voltage regulators are always enabled after a reset. Depending on the application
modes, the VCORE supply is provided either by the main regulator (MR) or by the low-power
regulator (LPR).
•
In Run, Sleep and Stop 0 modes, both regulators are enabled and the main regulator
(MR) supplies full power to the VCORE domain (core, memories and digital peripherals).
•
In Low-power run and Low-power sleep modes, the main regulator is off and the lowpower regulator (LPR) supplies low power to the VCORE domain, preserving the
contents of the registers, SRAM1 and SRAM2.
•
In Stop 1 and Stop 2 modes, the main regulator is off and the low-power regulator
(LPR) supplies low power to the VCORE domain, preserving the contents of the
registers, SRAM1 and SRAM2.
•
In Standby mode with SRAM2 content preserved (RRS bit is set in the PWR_CR3
register), the main regulator (MR) is off and the low-power regulator (LPR) provides the
supply to SRAM2 only. The core, digital peripherals (except Standby circuitry and
backup domain) and SRAM1 are powered off.
•
In Standby mode, both regulators are powered off. The contents of the registers,
SRAM1 and SRAM2 is lost except for the Standby circuitry and the backup domain.
•
In Shutdown mode, both regulators are powered off. When exiting from Shutdown
mode, a power-on reset is generated. Consequently, the contents of the registers,
RM0503 Rev 2
109/1325
150
Power control (PWR)
RM0503
SRAM1 and SRAM2 is lost, except for the backup domain.
4.1.6
Dynamic voltage scaling management
The dynamic voltage scaling is a power management technique which consists in
increasing or decreasing the voltage used for the digital peripherals (VCORE), according to
the application performance and power consumption needs.
Dynamic voltage scaling to increase VCORE is known as over-volting. It allows to improve
the device performance.
Dynamic voltage scaling to decrease VCORE is known as under-volting. It is performed to
save power, particularly in laptop and other mobile devices where the energy comes from a
battery and is thus limited.
• Range 1: High-performance range.
The main regulator provides a typical output voltage at 1.2 V. The system clock
frequency can be up to 56 MHz. The flash access time for read access is minimum,
write and erase operations are possible.
• Range 2: Low-power range.
The main regulator provides a typical output voltage at 1.0 V. The system clock
frequency can be up to 16 MHz when running from MSI, or up to 18 MHz when running
from PLL or HSE. The flash access time for a read access is increased as compared to
Range 1; write and erase operations are possible.
Voltage scaling is selected through the VOS bit in the PWR_CR1 register.
The sequence to go from Range 1 to Range 2 is:
1.Reduce the system frequency to a value lower than the maximum value allowed
for Range 2.
2. Adjust the number of wait states according to the new frequency target in Range 2
(LATENCY bits in the FLASH_ACR).
3. Program the VOS bits to “10” in the PWR_CR1 register.
The sequence to go from Range 2 to Range 1 is:
1. Program the VOS bits to “01” in the PWR_CR1 register.
2. Wait until the VOSF flag is cleared in the PWR_SR2 register.
3. Adjust number of wait states according new frequency target in Range 1
(LATENCY bits in the FLASH_ACR).
4. Increase the system frequency.
4.2
Power supply supervisor
4.2.1
Power-on reset (POR) / power-down reset (PDR) / brown-out reset
(BOR)
The device has an integrated power-on reset (POR) / power-down reset (PDR), coupled
with a brown-out reset (BOR) circuitry. The BOR is active in all power modes except
Shutdown mode, and cannot be disabled.
Five BOR thresholds can be selected through option bytes.
110/1325
RM0503 Rev 2
RM0503
Power control (PWR)
During power-on, the BOR keeps the device under reset until the supply voltage VDD
reaches the specified VBORx threshold. When VDD drops below the selected threshold, a
device reset is generated. When VDD is above the VBORx upper limit, the device reset is
released and the system can start.
For more details on the brown-out reset thresholds, refer to the electrical characteristics
section in the datasheet.
On STM32U0 devices, continuous monitoring of the power supply might be changed to
periodical sampling to reduce power consumption in Stop 2 and Standby modes by setting
ENULP bit in Power control register 3 (PWR_CR3). When sampling mode is selected, fast
supply drop between two samples is not detected.
Figure 7. Brown-out reset waveform
VDD
VBOR0 (rising edge)
hysteresis
VBOR0 (falling edge)
Temporization
tRSTTEMPO
Reset
MS31444V5
1. The reset temporization tRSTTEMPO is present only for the BOR lowest threshold (VBOR0).
4.2.2
Programmable voltage detector (PVD)
You can use the PVD to monitor the VDD power supply by comparing it to a threshold
selected by the PLS[2:0] bits in the Power control register 2 (PWR_CR2).
The PVD is enabled by setting the PVDE bit.
A PVDO flag is available, in the Power status register 2 (PWR_SR2), to indicate if VDD is
higher or lower than the PVD threshold. This event is internally connected to the EXTI line16
and can generate an interrupt if enabled through the EXTI registers. The rising/falling edge
sensitivity of the EXTI Line16 should be configured according to PVD output behavior i.e. if
the EXTI line 16 is configured to rising edge sensitivity, the interrupt is generated when VDD
drops below the PVD threshold. As an example the service routine could perform
emergency shutdown tasks.
RM0503 Rev 2
111/1325
150
Power control (PWR)
RM0503
Figure 8. PVD thresholds
V DD
V PVD threshold
100 mV
hysteresis
PVD output
MS31445V2
4.2.3
Peripheral Voltage Monitoring (PVM)
Only VDD is monitored by default, as it is the only supply required for all system-related
functions. The other supplies (VDDA and VDDUSB) can be independent from VDD and can be
monitored with four Peripheral Voltage Monitoring (PVM).
Each of the three PVMx (x=1, 3, 4) is a comparator between a fixed threshold VPVMx and
the selected power supply. PVMOx flags indicate if the independent power supply is higher
or lower than the PVMx threshold: PVMOx flag is cleared when the supply voltage is above
the PVMx threshold, and is set when the supply voltage is below the PVMx threshold.
Each PVM output is connected to an EXTI line and can generate an interrupt if enabled
through the EXTI registers. The PVMx output interrupt is generated when the independent
power supply drops below the PVMx threshold and/or when it rises above the PVMx
threshold, depending on EXTI line rising/falling edge configuration.
Each PVM can remain active in Stop 0, Stop 1 and Stop 2 modes, and the PVM interrupt
can wake up from the Stop mode.
Table 20. PVM features
PVM
Power supply
PVM threshold
EXTI line
PVM1(1)
VDDUSB
VPVM1 (around 1.2 V)
19
PVM3
VDDA
VPVM3 (around 1.65 V)
20
PVM4
VDDA
VPVM4 (around 1.86 V)
21
1. Available on STM32 U0x3xx devices only.
The independent supplies (VDDA and VDDUSB) are not considered as present by default,
and a logical and electrical isolation is applied to ignore any information coming from the
peripherals supplied by these dedicated supplies.
112/1325
•
If these supplies are shorted externally to VDD, the application should assume they are
available without enabling any Peripheral Voltage Monitoring.
•
If these supplies are independent from VDD, the Peripheral Voltage Monitoring (PVM)
RM0503 Rev 2
RM0503
Power control (PWR)
can be enabled to confirm whether the supply is present or not.
The following sequence must be done before using the USB FS peripheral on
STM32U0x3xx devices:
1.
2.
If VDDUSB is independent from VDD:
a)
Enable the PVM1 by setting PVME1 bit in the Power control register 2
(PWR_CR2).
b)
Wait for the PVM1 wake-up time
c)
Wait until PVMO1 bit is cleared in the Power status register 2 (PWR_SR2).
d)
Optional: Disable the PVM1 for consumption saving.
Set the USV bit in the Power control register 2 (PWR_CR2) to remove the VDDUSB
power isolation.
The following sequence must be done before using any of these analog peripherals: analog
to digital converters, digital to analog converters, comparators, operational amplifiers,
voltage reference buffer:
1.
2.
4.3
If VDDA is independent from VDD:
a)
Enable the PVM3 (or PVM4) by setting PVME3 (or PVME4) bit in the Power
control register 2 (PWR_CR2).
b)
Wait for the PVM3 (or PVM4) wake-up time
c)
Wait until PVMO3 (or PVMO4) bit is cleared in the Power status register 2
(PWR_SR2).
d)
Optional: Disable the PVM3 (or PVM4) for consumption saving.
Enable the analog peripheral, which automatically removes the VDDA isolation.
Low-power modes
By default, the microcontroller is in Run mode after a system or a power Reset. Several lowpower modes are available to save power when the CPU does not need to be kept running,
for example when waiting for an external event. It is up to the user to select the mode that
gives the best compromise between low-power consumption, short startup time and
available wake-up sources.
The device features seven low-power modes:
•
Sleep mode: CPU clock off, all peripherals including Cortex®-M0+ core peripherals
such as NVIC, SysTick, etc. can run and wake up the CPU when an interrupt or an
event occurs. Refer to Section 4.3.4: Sleep mode.
•
Low-power run mode: This mode is achieved when the system clock frequency is
reduced below 2 MHz. The code is executed from the SRAM or the flash memory. The
regulator is in low-power mode to minimize the regulator's operating current. Refer to
Section 4.3.2: Low-power run mode (LP run).
•
Low-power sleep mode: This mode is entered from the Low-power run mode: Cortex®M0+ is off. Refer to Section 4.3.5: Low-power sleep mode (LP sleep).
•
Stop 0, Stop 1 and Stop 2 modes: SRAM1, SRAM2 and all registers content are
retained. All clocks in the VCORE domain are stopped, the PLL, the MSI, the HSI16 and
the HSE are disabled. The LSI and the LSE can be kept running.
The RTC can remain active (Stop mode with RTC, Stop mode without RTC).
Some peripherals with the wake-up capability can enable the HSI16 RC during the
RM0503 Rev 2
113/1325
150
Power control (PWR)
RM0503
Stop mode to detect their wake-up condition.
In Stop 2 mode, most of the VCORE domain is put in a lower leakage mode.
Stop 1 offers the largest number of active peripherals and wake-up sources, a smaller
wake-up time but a higher consumption than Stop 2. In Stop 0 mode, the main regulator
remains ON, which allows the fastest wake-up time but with much higher consumption.
The active peripherals and wake-up sources are the same as in Stop 1 mode.
The system clock, when exiting from Stop 0, Stop 1 or Stop 2 mode, can be either MSI
up to 48 MHz or HSI16, depending on the software configuration.
Refer to Section 4.3.6: Stop 0 mode and Section 4.3.8: Stop 2 mode.
•
Standby mode: VCORE domain is powered off. However, it is possible to preserve the
SRAM2 contents:
–
Standby mode with SRAM2 retention when the bit RRS is set in PWR_CR3
register. In this case, SRAM2 is supplied by the low-power regulator.
–
Standby mode when the bit RRS is cleared in PWR_CR3 register. In this case the
main regulator and the low-power regulator are powered off.
All clocks in the VCORE domain are stopped, the PLL, the MSI, the HSI16 and the HSE
are disabled. The LSI and the LSE can be kept running.
The RTC can remain active (Standby mode with RTC, Standby mode without RTC).
The system clock, when exiting Standby modes, is MSI from 1 MHz up to 8 MHz.
Refer to Section 4.3.9: Standby mode.
•
Shutdown mode: VCORE domain is powered off. All clocks in the VCORE domain are
stopped, the PLL, the MSI, the HSI16, the LSI and the HSE are disabled. The LSE can
be kept running. The system clock, when exiting the Shutdown mode, is MSI at 4 MHz.
In this mode, the supply voltage monitoring is disabled and the product behavior is not
guaranteed in case of a power voltage drop. Refer to Section 4.3.10: Shutdown mode.
In addition, the power consumption in Run mode can be reduced by one of the following
means:
114/1325
•
Slowing down the system clocks
•
Gating the clocks to the APB and AHB peripherals when they are unused.
RM0503 Rev 2
RM0503
Power control (PWR)
Figure 9. Low-power modes possible transitions
Low power sleep mode
Sleep mode
Low power run mode
Shutdown mode
Stop 1 mode
Run mode
Standby mode
Stop 0 mode
Stop 2 mode
MS33361V2
RM0503 Rev 2
115/1325
150
Power control (PWR)
RM0503
Table 21. Low-power mode summary
Mode name
Entry
WFI or Return
Sleep
(Sleep-now or from ISR
Sleep-on-exit) WFE
Low-power
run
Low-power
sleep
Stop 0
Stop 1
Stop 2
Wake-up
Wake-up
source(1)
system clock
Any interrupt
Wake-up event
Set LPR bit
Clear LPR bit
Set LPR bit +
WFI or Return
from ISR
Any interrupt
Set LPR bit +
WFE
Wake-up event
LPR
Same as before
entering Sleep
mode
CPU clock OFF
no effect on other clocks ON
or analog clock sources
ON
Same as Lowpower run clock
None
OFF
ON
Same as before
entering Lowpower sleep
mode
OFF
CPU clock OFF
no effect on other clocks
or analog clock sources
OFF
ON
ON
ON
HSI16 when
Any EXTI line
STOPWUCK=1 in
(configured in the RCC_CFGR
LPMS=”001” +
SLEEPDEEP bit EXTI registers)
MSI with the
+ WFI or Return Specific
frequency before
from ISR or WFE peripherals
entering the Stop
events
mode when
LPMS=”010” +
STOPWUCK=0.
SLEEPDEEP bit
+ WFI or Return
All clocks OFF except
LSI and LSE
from ISR or WFE
WKUP pin edge,
RTC event,
external reset in
NRST pin,
IWDG reset
Standby
LPMS=”011” +
Clear RRS bit +
SLEEPDEEP bit
+ WFI or Return
from ISR or WFE
WKUP pin edge,
RTC event,
external reset in
NRST pin,
IWDG reset
Shutdown
LPMS=”1--” +
SLEEPDEEP bit
+ WFI or Return
from ISR or WFE
WKUP pin edge,
RTC event,
external reset in
NRST pin
ON
OFF
MSI from 1 MHz
up to 8 MHz
MSI 4 MHz
1. Refer to Table 22: Functionalities depending on the working mode.
116/1325
MR
LPMS=”000” +
SLEEPDEEP bit
+ WFI or Return
from ISR or WFE
LPMS=”011”+
Set RRS bit +
SLEEPDEEP bit
+ WFI or Return
from ISR or WFE
Standby with
SRAM2
Effect on clocks
Voltage
regulators
RM0503 Rev 2
All clocks OFF except
LSE
OFF
OFF
OFF
OFF
RM0503
Power control (PWR)
Table 22. Functionalities depending on the working mode
Legend: Y = Yes (Enable). O = Optional (Disable by default. Can be enabled by software). - = Not available
-
Wake-up capability
-
Wake-up capability
-
CPU
Y
-
Y
-
-
-
-
-
-
-
-
-
-
Flash memory
(1)
O
O(1)
O(1)
O(1)
-
-
-
-
-
-
-
-
-
Y
Y(2)
Y
Y(2)
Y
-
Y
-
-
-
-
-
-
SRAM2
Y
(2)
Y
Y
(2)
Y
Y
-
Y
-
(3)
O
-
-
-
-
Backup Registers
Y
Y
Y
Y
Y
-
Y
-
Y
-
Y
-
Y
Brown-out reset (BOR)
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
-
-
-
Programmable Voltage
Detector (PVD)
O
O
O
O
O
O
O
O
-
-
-
-
-
Peripheral Voltage Monitor
(PVMx; x=1,3,4)
O
O
O
O
O
O
O
O
-
-
-
-
-
DMA
O
O
O
O
-
-
-
-
-
-
-
-
-
-
(4)
-
-
-
-
-
-
Peripheral
SRAM1
Run
Sleep
-
Wake-up capability
Wake-up capability
Standby Shutdown
Low-power sleep
Stop 2
Low-power run
Stop 0/1
VBAT
Oscillator HSI16
O
O
O
O
(4)
Oscillator HSI48
O
O
-
-
-
-
-
-
-
-
-
-
-
High Speed External (HSE)
O
O
O
O
-
-
-
-
-
-
-
-
-
Low Speed Internal (LSI)
O
O
O
O
O
-
O
-
O
-
-
-
-
Low Speed External (LSE)
O
O
O
O
O
-
O
-
O
-
O
-
O
Multi-Speed Internal (MSI)
O
O
O
O
-
-
-
-
-
-
-
-
-
Clock Security System
(CSS)
O
O
O
O
-
-
-
-
-
-
-
-
-
Clock Security System on
LSE
O
O
O
O
O
O
O
O
O
O
-
-
-
RTC / Auto wake-up
O
O
O
O
O
O
O
O
O
O
O
O
O
Number of RTC Tamper pins
2
2
2
2
2
O
2
O
2
O
2
O
2
USARTx (x=1,2,3,4)
O
O
O
O
(5)
-
-
-
-
-
-
-
LUARTx (x = 1, 2, 3)
O
O
O
O
(5)
I2Cx (x=2,4)
O
O
O
O
(6)
O
O
O
RM0503 Rev 2
O
(5)
O
(5)
O
(6)
O
O
(5)
(5)
-
-
-
-
-
-
-
-
-
-
-
-
117/1325
150
Power control (PWR)
RM0503
Table 22. Functionalities depending on the working mode (continued)
Legend: Y = Yes (Enable). O = Optional (Disable by default. Can be enabled by software). - = Not available
O
O
O
O
(6)
(6)
(6)
(6)
-
-
-
-
-
SPIx (x=1,2,3)
O
O
O
O
-
-
-
-
-
-
-
-
-
ADC1
O
O
O
O
-
-
-
-
-
-
-
-
-
DAC1
O
O
O
O
O
-
-
-
-
-
-
-
-
OPAMP1
O
O
O
O
O
-
-
-
-
-
-
-
-
COMPx (x=1,2)
O
O
O
O
O
O
O
O
-
-
-
-
-
Temperature sensor
O
O
O
O
-
-
-
-
-
-
-
-
-
Timers (TIMx)
O
O
O
O
-
-
-
-
-
-
-
-
-
LPTIMx (x = 1, 2, 3)
O
O
O
O
O
O
O
O
-
-
-
-
-
Independent watchdog
(IWDG)
O
O
O
O
O
O
O
O
O
O
-
-
-
Window watchdog (WWDG)
O
O
O
O
-
-
-
-
-
-
-
-
-
SysTick timer
O
O
O
O
-
-
-
-
-
-
-
-
-
Touch sensing controller
(TSC)
O
O
O
O
-
-
-
-
-
-
-
-
-
Random number generator
(RNG)
O(7)
O(7)
-
-
-
-
-
-
-
-
-
-
-
AES hardware accelerator
O
O
O
O
-
-
-
-
-
-
-
-
-
CRC calculation unit
O
O
O
O
-
-
-
-
-
-
-
-
-
O
(8)
5
pins
(10)
up to
5
pins(
GPIOs
Sleep
O
O
O
O
-
O
O
O
O
-
O
O
O
-
(9)
Wake-up capability
I2Cx (x=1,3)
Run
Wake-up capability
-
Peripheral
Wake-up capability
Wake-up capability
Standby Shutdown
Low-power sleep
Stop 2
Low-power run
Stop 0/1
VBAT
9)
1. The flash memory can be configured in power-down mode. By default, it is not in power-down mode.
2. The SRAM clock can be gated on or off.
3. SRAM2 content is preserved when the bit RRS is set in PWR_CR3 register.
4. Some peripherals with wake-up from Stop capability can request HSI16 to be enabled. In this case, HSI16 is woken up by
the peripheral, and only feeds the peripheral which requested it. HSI16 is automatically put off when the peripheral does not
need it anymore.
5. UART and LPUART reception is functional in Stop mode, and generates a wake-up interrupt on Start, address match or
received frame event.
6. I2C address detection is functional in Stop mode, and generates a wake-up interrupt in case of address match.
118/1325
RM0503 Rev 2
-
RM0503
Power control (PWR)
7. Voltage scaling Range 1only.
8. I/Os can be configured with internal pull-up, pull-down or floating in Standby mode.
9. I/Os with wake-up from Standby/Shutdown capability are the following: PA0, PC13, PE6, PA2, PC5.
10. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when
exiting the Shutdown mode.
Debug mode
By default, the debug connection is lost if the application puts the MCU in Stop 0, Stop 1,
Stop 2, Standby or Shutdown mode while the debug features are used. This is due to the
fact that the Cortex®-M0+ core is no longer clocked.
However, by setting some configuration bits in the DBGMCU_CR register, the software can
be debugged even when using the low-power modes extensively. For more details, refer to
Section 37.2.6: Debug in low-power modes.
4.3.1
Run mode
Slowing down system clocks
In Run mode, the speed of the system clocks (SYSCLK, HCLK, PCLK) can be reduced by
programming the prescaler registers. These prescalers can also be used to slow down the
peripherals before entering the Sleep mode.
For more details, refer to Section 5.4.3: Clock configuration register (RCC_CFGR).
Peripheral clock gating
In Run mode, the HCLK and PCLK for individual peripherals and memories can be stopped
at any time to reduce the power consumption.
To further reduce the power consumption in Sleep mode, the peripheral clocks can be
disabled prior to executing the WFI or WFE instructions.
The peripheral clock gating is controlled by the RCC_AHBxENR and RCC_APBxENR
registers.
Disabling the peripherals clocks in Sleep mode can be performed automatically by resetting
the corresponding bit in the RCC_AHBxSMENR and RCC_APBxSMENR registers.
4.3.2
Low-power run mode (LP run)
To further reduce the consumption when the system is in Run mode, the regulator can be
configured in low-power mode. In this mode, the system frequency should not exceed
2 MHz.
Please refer to the product datasheet for more details on voltage regulator and peripherals
operating conditions.
I/O states in Low-power run mode
In Low-power run mode, all I/O pins keep the same state as in Run mode.
Entering the Low-power run mode
To enter the Low-power run mode, proceed as follows:
RM0503 Rev 2
119/1325
150
Power control (PWR)
RM0503
1.
Optional: Jump into the SRAM and power-down the flash by setting the RUN_PD bit in
the FLASH access control register (FLASH_ACR).
2.
Decrease the system clock frequency below 2 MHz.
3.
Force the regulator in low-power mode by setting the LPR bit in the PWR_CR1 register.
Refer to Table 23: Low-power run on how to enter the Low-power run mode.
Exiting the Low-power run mode
To exit the Low-power run mode, proceed as follows:
1.
Force the regulator in main mode by clearing the LPR bit in the PWR_CR1 register.
2.
Wait until REGLPF bit is cleared in the PWR_SR2 register.
3.
Increase the system clock frequency.
Refer to Table 23: Low-power run on how to exit the Low-power run mode.
Table 23. Low-power run
Low-power run mode
4.3.3
Description
Mode entry
Decrease the system clock frequency below 2 MHz
LPR = 1
Mode exit
LPR = 0
Wait until REGLPF = 0
Increase the system clock frequency
Wake-up latency
Regulator wake-up time from low-power mode
Low-power modes
Entering low-power mode
Low-power modes are entered by the MCU by executing the WFI (Wait For Interrupt), or
WFE (Wait for Event) instructions, or when the SLEEPONEXIT bit in the Cortex®-M0+
System Control register is set on Return from ISR.
Entering Low-power mode through WFI or WFE is executed only if no interrupt is pending or
no event is pending.
Exiting low-power mode
From Sleep modes, and Stop modes the MCU exit low-power mode depending on the way
the low-power mode was entered:
•
If the WFI instruction or Return from ISR was used to enter the low-power mode, any
peripheral interrupt acknowledged by the NVIC can wake up the device.
•
If the WFE instruction is used to enter the low-power mode, the MCU exits the lowpower mode as soon as an event occurs. The wake-up event can be generated either
by:
–
NVIC IRQ interrupt.
- When SEVONPEND = 0 in the Cortex®-M0+ System Control register. By
enabling an interrupt in the peripheral control register and in the NVIC. When the
MCU resumes from WFE, the peripheral interrupt pending bit and the NVIC
120/1325
RM0503 Rev 2
RM0503
Power control (PWR)
peripheral IRQ channel pending bit (in the NVIC interrupt clear pending register)
have to be cleared.
Only NVIC interrupts with sufficient priority wakes up and interrupt the MCU.
- When SEVONPEND = 1 in the Cortex®-M0+ System Control register.
By enabling an interrupt in the peripheral control register and optionally in the
NVIC. When the MCU resumes from WFE, the peripheral interrupt pending bit and
when enabled the NVIC peripheral IRQ channel pending bit (in the NVIC interrupt
clear pending register) have to be cleared.
All NVIC interrupts wake up the MCU, even the disabled ones. Only enabled NVIC
interrupts with sufficient priority wake up and interrupt the MCU.
–
Event
Configuring a EXTI line in event mode. When the CPU resumes from WFE, it is
not necessary to clear the EXTI peripheral interrupt pending bit or the NVIC IRQ
channel pending bit as the pending bits corresponding to the event line is not set.
It may be necessary to clear the interrupt flag in the peripheral.
From Standby modes, and Shutdown modes the MCU exit low-power mode through an
external reset (NRST pin), an IWDG reset, a rising edge on one of the enabled WKUPx pins
or a RTC event occurs (see Figure 297: RTC block diagrams).
After waking up from Standby or Shutdown mode, program execution restarts in the same
way as after a Reset (boot pin sampling, option bytes loading, reset vector is fetched, etc.).
4.3.4
Sleep mode
I/O states in Sleep mode
In Sleep mode, all I/O pins keep the same state as in Run mode.
Entering the Sleep mode
The Sleep mode is entered according Section : Entering low-power mode, when the
SLEEPDEEP bit in the Cortex®-M0+ System Control register is clear.
Refer to Table 24: Sleep for details on how to enter the Sleep mode.
Exiting the Sleep mode
The Sleep mode is exit according Section : Exiting low-power mode.
Refer to Table 24: Sleep for more details on how to exit the Sleep mode.
RM0503 Rev 2
121/1325
150
Power control (PWR)
RM0503
Table 24. Sleep
Sleep-now mode
Description
WFI (Wait for Interrupt) or WFE (Wait for Event) while:
– SLEEPDEEP = 0
– No interrupt (for WFI) or event (for WFE) is pending
Refer to the Cortex®-M0+ System Control register.
Mode entry
On return from ISR while:
– SLEEPDEEP = 0 and
– SLEEPONEXIT = 1
– No interrupt is pending
Refer to the Cortex®-M0+ System Control register.
If WFI or return from ISR was used for entry
Interrupt: refer to Table 54: Vector table
Mode exit
If WFE was used for entry and SEVONPEND = 0:
Wake-up event: refer to Section 11: Nested vectored interrupt controller
(NVIC)
If WFE was used for entry and SEVONPEND = 1:
Interrupt even when disabled in NVIC: refer to Table 54: Vector table or
Wake-up event: refer to Section 11: Nested vectored interrupt controller
(NVIC)
Wake-up latency
4.3.5
None
Low-power sleep mode (LP sleep)
Please refer to the product datasheet for more details on voltage regulator and peripherals
operating conditions.
I/O states in Low-power sleep mode
In Low-power sleep mode, all I/O pins keep the same state as in Run mode.
Entering the Low-power sleep mode
The Low-power sleep mode is entered from Low-power run mode according Section :
Entering low-power mode, when the SLEEPDEEP bit in the Cortex®-M0+ System Control
register is clear.
Refer to Table 25: Low-power sleep for details on how to enter the Low-power sleep mode.
Exiting the Low-power sleep mode
The low-power Sleep mode is exit according Section : Exiting low-power mode. When
exiting the Low-power sleep mode by issuing an interrupt or an event, the MCU is in Lowpower run mode.
Refer to Table 25: Low-power sleep for details on how to exit the Low-power sleep mode.
122/1325
RM0503 Rev 2
RM0503
Power control (PWR)
Table 25. Low-power sleep
Low-power sleep-now
mode
Description
Low-power sleep mode is entered from the Low-power run mode.
WFI (Wait for Interrupt) or WFE (Wait for Event) while:
– SLEEPDEEP = 0
– No interrupt (for WFI) or event (for WFE) is pending
Refer to the Cortex®-M0+ System Control register.
Mode entry
Low-power sleep mode is entered from the Low-power run mode.
On return from ISR while:
– SLEEPDEEP = 0 and
– SLEEPONEXIT = 1
– No interrupt is pending
Refer to the Cortex®-M0+ System Control register.
If WFI or Return from ISR was used for entry
Interrupt: refer to Table 54: Vector table
If WFE was used for entry and SEVONPEND = 0:
Wake-up event: refer to Section 11: Nested vectored interrupt controller
(NVIC)
4.3.6
Mode exit
If WFE was used for entry and SEVONPEND = 1:
Interrupt even when disabled in NVIC: refer to Table 54: Vector table
Wake-up event: refer to Section 11: Nested vectored interrupt controller
(NVIC)
After exiting the Low-power sleep mode, the MCU is in Low-power run
mode.
Wake-up latency
None
Stop 0 mode
The Stop 0 mode is based on the Cortex®-M0+ deepsleep mode combined with the
peripheral clock gating. The voltage regulator is configured in main regulator mode. In Stop
0 mode, all clocks in the VCORE domain are stopped; the PLL, the MSI, the HSI16 and the
HSE oscillators are disabled. Some peripherals with the wake-up capability (I2Cx (x=1,2,3),
U(S)ARTx(x=1,2,3) and LPUART) can switch on the HSI16 to receive a frame, and switch
off the HSI16 after receiving the frame if it is not a wake-up frame. In this case, the HSI16
clock is propagated only to the peripheral requesting it.
SRAM1, SRAM2 and register contents are preserved.
The BOR is always available in Stop 0 mode. The consumption is increased when
thresholds higher than VBOR0 are used.
I/O states in Stop 0 mode
In the Stop 0 mode, all I/O pins keep the same state as in the Run mode.
Entering the Stop 0 mode
The Stop 0 mode is entered according Section : Entering low-power mode, when the
SLEEPDEEP bit in the Cortex®-M0+ System Control register is set.
RM0503 Rev 2
123/1325
150
Power control (PWR)
RM0503
Refer to Table 26: Stop 0 mode for details on how to enter the Stop 0 mode.
If flash memory programming is ongoing, the Stop 0 mode entry is delayed until the memory
access is finished.
If an access to the APB domain is ongoing, The Stop 0 mode entry is delayed until the APB
access is finished.
In Stop 0 mode, the following features can be selected by programming individual control
bits:
•
Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by
hardware option. Once started, it cannot be stopped except by a Reset. See
Section 28.4: IWDG functional description.
•
Real-time clock (RTC): this is configured by the RTCEN bit in the RTC domain control
register (RCC_BDCR)
•
Internal RC oscillator (LSI): this is configured by the LSION bit in the Control/status
register (RCC_CSR)
•
External 32.768 kHz oscillator (LSE): this is configured by the LSEON bit in the RTC
domain control register (RCC_BDCR).
Several peripherals can be used in Stop 0 mode and can add consumption if they are
enabled and clocked by LSI or LSE, or when they request the HSI16 clock: LCD, LPTIM1,
LPTIM2, I2Cx (x=1,2,3,4) U(S)ARTx(x=1,2,3,4), LPUART.
The DACx (x=1,2), the OPAMP and the comparators can be used in Stop 0 mode, the PVMx
(x=1,3,4) and the PVD as well. If they are not needed, they must be disabled by software to
save their power consumptions.
The ADCx (x=1), temperature sensor and VREFBUF buffer can consume power during the
Stop 0 mode, unless they are disabled before entering this mode.
Exiting the Stop 0 mode
The Stop 0 mode is exit according Section : Entering low-power mode.
Refer to Table 26: Stop 0 mode for details on how to exit Stop 0 mode.
When exiting Stop 0 mode by issuing an interrupt or a wake-up event, the HSI16 oscillator is
selected as system clock if the bit STOPWUCK is set in Clock configuration register
(RCC_CFGR). The MSI oscillator is selected as system clock if the bit STOPWUCK is
cleared. The wake-up time is shorter when HSI16 is selected as wake-up system clock. The
MSI selection allows wake-up at higher frequency, up to 48 MHz.
When exiting the Stop 0 mode, the MCU is either in Run mode Range 1 or Run Mode Range
2 depending on VOS bit in PWR_CR1.
124/1325
RM0503 Rev 2
RM0503
Power control (PWR)
Table 26. Stop 0 mode
Stop 0 mode
Description
WFI (Wait for Interrupt) or WFE (Wait for Event) while:
– SLEEPDEEP bit is set in Cortex®-M0+ System Control register
– No interrupt (for WFI) or event (for WFE) is pending
– LPMS = “000” in PWR_CR1
Mode entry
On Return from ISR while:
– SLEEPDEEP bit is set in Cortex®-M0+ System Control register
– SLEEPONEXIT = 1
– No interrupt is pending
– LPMS = “000” in PWR_CR1
Note: To enter Stop 0 mode, all EXTI Line pending bits (in EXTI rising
edge pending register 1 (EXTI_RPR1) and EXTI falling edge
pending register 1 (EXTI_FPR1)), and the peripheral flags
generating wake-up interrupts must be cleared. Otherwise, the Stop
0 mode entry procedure is ignored and program execution
continues.
Mode exit
If WFI or Return from ISR was used for entry
Any EXTI Line configured in Interrupt mode (the corresponding EXTI
Interrupt vector must be enabled in the NVIC). The interrupt source can
be external interrupts or peripherals with wake-up capability. Refer to
Table 54: Vector table
If WFE was used for entry and SEVONPEND = 0:
Any EXTI Line configured in event mode. Refer to Section 11: Nested
vectored interrupt controller (NVIC).
If WFE was used for entry and SEVONPEND = 1:
Any EXTI Line configured in Interrupt mode (even if the corresponding
EXTI Interrupt vector is disabled in the NVIC). The interrupt source can
be external interrupts or peripherals with wake-up capability. Refer to
Table 54: Vector table.
Wake-up event: refer to Section 11: Nested vectored interrupt controller
(NVIC)
Wake-up latency
4.3.7
Longest wake-up time between: MSI or HSI16 wake-up time and flash
wake-up time from Stop 0 mode.
Stop 1 mode
The Stop 1 mode is the same as Stop 0 mode except that the main regulator is OFF, and
only the low-power regulator is ON. Stop 1 mode can be entered from Run mode and from
Low-power run mode.
Refer to Table 27: Stop 1 mode for details on how to enter and exit Stop 1 mode.
RM0503 Rev 2
125/1325
150
Power control (PWR)
RM0503
Table 27. Stop 1 mode
Stop 1 mode
Description
WFI (Wait for Interrupt) or WFE (Wait for Event) while:
– SLEEPDEEP bit is set in Cortex®-M0+ System Control register
– No interrupt (for WFI) or event (for WFE) is pending
– LPMS = “001” in PWR_CR1
Mode entry
On Return from ISR while:
– SLEEPDEEP bit is set in Cortex®-M0+ System Control register
– SLEEPONEXIT = 1
– No interrupt is pending
– LPMS = “001” in PWR_CR1
Note: To enter Stop 1 mode, all EXTI Line pending bits (in EXTI rising
edge pending register 1 (EXTI_RPR1) and EXTI falling edge
pending register 1 (EXTI_FPR1)), and the peripheral flags
generating wake-up interrupts must be cleared. Otherwise, the Stop
1 mode entry procedure is ignored and program execution
continues.
Mode exit
If WFI or Return from ISR was used for entry
Any EXTI Line configured in Interrupt mode (the corresponding EXTI
Interrupt vector must be enabled in the NVIC). The interrupt source can
be external interrupts or peripherals with wake-up capability. Refer to
Table 54: Vector table.
If WFE was used for entry and SEVONPEND = 0:
Any EXTI Line configured in event mode. Refer to Section 11: Nested
vectored interrupt controller (NVIC).
If WFE was used for entry and SEVONPEND = 1:
Any EXTI Line configured in Interrupt mode (even if the corresponding
EXTI Interrupt vector is disabled in the NVIC). The interrupt source can
be external interrupts or peripherals with wake-up capability. Refer to
Table 54: Vector table
Wake-up event: refer to Section 11: Nested vectored interrupt controller
(NVIC)
Wake-up latency
4.3.8
Longest wake-up time between: MSI or HSI16 wake-up time and regulator
wake-up time from Low-power mode + flash wake-up time from Stop 1
mode.
Stop 2 mode
The Stop 2 mode is based on the Cortex®-M0+ deepsleep mode combined with peripheral
clock gating. In Stop 2 mode, all clocks in the VCORE domain are stopped, the PLL, the MSI,
the HSI16 and the HSE oscillators are disabled. Some peripherals with wake-up capability
(I2C3 and LPUART) can switch on the HSI16 to receive a frame, and switch off the HSI16
after receiving the frame if it is not a wake-up frame. In this case the HSI16 clock is
propagated only to the peripheral requesting it.
SRAM1, SRAM2 and register contents are preserved.
The BOR is always available in Stop 2 mode. The consumption is increased when
thresholds higher than VBOR0 are used.
126/1325
RM0503 Rev 2
RM0503
Note:
Power control (PWR)
The comparators outputs, the LPUART outputs and the LPTIM1 outputs are forced to low
speed (OSPEEDy=00) during the Stop 2 mode.
I/O states in Stop 2 mode
In the Stop 2 mode, all I/O pins keep the same state as in the Run mode.
Entering Stop 2 mode
The Stop 2 mode is entered according Section : Entering low-power mode, when the
SLEEPDEEP bit in the Cortex®-M0+ System Control register is set.
Refer to Table 28: Stop 2 mode for details on how to enter the Stop 2 mode.
Stop 2 mode can only be entered from Run mode. It is not possible to enter Stop 2 mode
from the Low-power run mode.
If flash memory programming is ongoing, the Stop 2 mode entry is delayed until the memory
access is finished.
If an access to the APB domain is ongoing, The Stop 2 mode entry is delayed until the APB
access is finished.
In Stop 2 mode, the following features can be selected by programming individual control
bits:
•
Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by
hardware option. Once started it cannot be stopped except by a Reset. See
Section 28.4: IWDG functional description in Section 28: Independent watchdog
(IWDG).
•
Real-time clock (RTC): this is configured by the RTCEN bit in the Section 5.4.22: RTC
domain control register (RCC_BDCR)
•
Internal RC oscillator (LSI): this is configured by the LSION bit in the Section 5.4.23:
Control/status register (RCC_CSR).
•
External 32.768 kHz oscillator (LSE): this is configured by the LSEON bit in the RTC
domain control register (RCC_BDCR).
Several peripherals can be used in Stop 2 mode and can add consumption if they are
enabled and clocked by LSI or LSE, or when they request the HSI16 clock: LCD, LPTIM1,
I2C3, LPUART.
The comparators can be used in Stop 2 mode, the PVMx (x=1,3,4) and the PVD as well. If
they are not needed, they must be disabled by software to save their power consumptions.
The ADCx, OPAMPx, DACx, temperature sensor and VREFBUF buffer can consume power
during Stop 2 mode, unless they are disabled before entering this mode.
All the peripherals which cannot be enabled in Stop 2 mode must be either disabled by
clearing the Enable bit in the peripheral itself, or put under reset state by setting the
corresponding bit in the AHB peripheral reset register (RCC_AHBRSTR), APB peripheral
reset register 1 (RCC_APBRSTR1), and APB peripheral reset register 2
(RCC_APBRSTR2).
Exiting Stop 2 mode
The Stop 2 mode is exit according Section : Exiting low-power mode.
Refer to Table 28: Stop 2 mode for details on how to exit Stop 2 mode.
RM0503 Rev 2
127/1325
150
Power control (PWR)
RM0503
When exiting Stop 2 mode by issuing an interrupt or a wake-up event, the HSI16 oscillator is
selected as system clock if the bit STOPWUCK is set in Clock configuration register
(RCC_CFGR). The MSI oscillator is selected as system clock if the bit STOPWUCK is
cleared. The wake-up time is shorter when HSI16 is selected as wake-up system clock. The
MSI selection allows wake-up at higher frequency, up to 48 MHz.
When exiting the Stop 2 mode, the MCU is in Run mode (Range 1 or Range 2 depending on
VOS bit in PWR_CR1).
Table 28. Stop 2 mode
Stop 2 mode
Description
WFI (Wait for Interrupt) or WFE (Wait for Event) while:
– SLEEPDEEP bit is set in Cortex®-M0+ System Control register
– No interrupt (for WFI) or event (for WFE) is pending
– LPMS = “010” in PWR_CR1
Mode entry
On return from ISR while:
– SLEEPDEEP bit is set in Cortex®-M0+ System Control register
– SLEEPONEXIT = 1
– No interrupt is pending
– LPMS = “010” in PWR_CR1
Note: To enter Stop 2 mode, all EXTI Line pending bits (in EXTI rising
edge pending register 1 (EXTI_RPR1) and EXTI falling edge
pending register 1 (EXTI_FPR1)), and the peripheral flags
generating wake-up interrupts must be cleared. Otherwise, the Stop
mode entry procedure is ignored and program execution continues.
Mode exit
Wake-up latency
4.3.9
If WFI or Return from ISR was used for entry:
Any EXTI Line configured in Interrupt mode (the corresponding EXTI
Interrupt vector must be enabled in the NVIC). The interrupt source can
be external interrupts or peripherals with wake-up capability. Refer to .
If WFE was used for entry and SEVONPEND = 0:
Any EXTI Line configured in event mode. Refer to Section 12.3.2: EXTI
direct event input wake-up.
If WFE was used for entry and SEVONPEND = 1:
Any EXTI Line configured in Interrupt mode (even if the corresponding
EXTI Interrupt vector is disabled in the NVIC). The interrupt source can
be external interrupts or peripherals with wake-up capability. Refer to
Table 54: Vector table
Any EXTI Line configured in event mode. Refer to Section 12.3.2: EXTI
direct event input wake-up.
Longest wake-up time between: MSI or HSI16 wake-up time and regulator
wake-up time from Low-power mode + flash wake-up time from Stop 2
mode.
Standby mode
The Standby mode allows to achieve the lowest power consumption with BOR. It is based
on the Cortex®-M0+ deepsleep mode, with the voltage regulators disabled (except when
SRAM2 content is preserved). The PLL, the HSI16, the MSI and the HSE oscillators are
also switched off.
128/1325
RM0503 Rev 2
RM0503
Power control (PWR)
SRAM1 and register contents are lost except for registers in the Backup domain and
Standby circuitry (see Figure 6). SRAM2 content can be preserved if the bit RRS is set in
the PWR_CR3 register. In this case the Low-power regulator is ON and provides the supply
to SRAM2 only.
The BOR is always available in Standby mode. The consumption is increased when
thresholds higher than VBOR0 are used.
I/O states in Standby mode
In the Standby mode, the I/Os are by default in floating state. If the APC bit of PWR_CR3
register has been set, the I/Os can be configured either with a pull-up (refer to
PWR_PUCRx registers (x=A,B,C,D,E,F,G,H)), or with a pull-down (refer to PWR_PDCRx
registers (x=A,B,C,D,E,F,G,H)), or can be kept in analog state if none of the PWR_PUCRx
or PWR_PDCRx register has been set. The pull-down configuration has highest priority over
pull-up configuration in case both PWR_PUCRx and PWR_PDCRx are set for the same I/O.
Some I/Os (listed in Section 7.3.1: General-purpose I/O (GPIO)) are used for JTAG/SW
debug. They can only be configured to their respective reset pull-up or pull-down state
during Standby mode by setting their respective bit in the PWR_PUCRx or PWR_PDCRx
registers, or are configured to floating state if the bit is kept cleared.
The RTC outputs on PC13 are functional in Standby mode. PC14 and PC15 used for LSE
are also functional. Five wake-up pins (WKUPx, x=1,2...5) and the 3 RTC tampers are
available.
Entering Standby mode
The Standby mode is entered according Section : Entering low-power mode, when the
SLEEPDEEP bit in the Cortex®-M0+ System Control register is set.
Refer to Table 29: Standby mode for details on how to enter Standby mode.
In Standby mode, the following features can be selected by programming individual control
bits:
•
Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by
hardware option. Once started it cannot be stopped except by a reset. See
Section 28.4: IWDG functional description in Section 28: Independent watchdog
(IWDG).
•
real-time clock (RTC): this is configured by the RTCEN bit in the Backup domain
control register (RCC_BDCR)
•
Internal RC oscillator (LSI): this is configured by the LSION bit in the Control/status
register (RCC_CSR).
•
External 32.768 kHz oscillator (LSE): this is configured by the LSEON bit in the Backup
domain control register (RCC_BDCR)
Exiting Standby mode
The Standby mode is exited according Section : Entering low-power mode. The SBF status
flag in the Power control register 3 (PWR_CR3) indicates that the MCU was in Standby
mode. All registers are reset after wake-up from Standby except for Power control register 3
(PWR_CR3).
Refer to Table 29: Standby mode for more details on how to exit Standby mode.
RM0503 Rev 2
129/1325
150
Power control (PWR)
RM0503
When exiting Standby mode, I/Os that were configured with pull-up or pull-down during
Standby through the PWR_PUCRx or PWR_PDCRx registers keep this configuration upon
exiting Standby mode until the bit APC of PWR_CR3 register has been cleared. Once the bit
APC is cleared, they are either configured to their reset values or to the pull-up/pull-down
state according the GPIOx_PUPDR registers. The content of the PWR_PUCRx or
PWR_PDCRx registers however is not lost and can be re-used for a sub-sequent entering
into Standby mode.
Some I/Os (listed in Section 7.3.1: General-purpose I/O (GPIO)) are used for JTAG/SW
debug, and have internal pull-up or pull-down activated after reset, so are configured at this
reset value as well when exiting Standby mode.
For I/Os with a pull-up or pull-down pre-defined after reset (some JTAG/SW I/Os) or with
GPIOx_PUPDR programming done after exiting from Standby, when this programming is
different from the PWR_PUCRx or PWR_PDCRx programmed value during Standby, both a
pull-down and pull-up is applied until the bit APC is cleared, releasing the PWR_PUCRx or
PWR_PDCRx programmed value.
Table 29. Standby mode
Standby mode
Description
WFI (Wait for Interrupt) or WFE (Wait for Event) while:
– SLEEPDEEP bit is set in Cortex®-M0+ System Control register
– No interrupt (for WFI) or event (for WFE) is pending
– LPMS = “011” in PWR_CR1
– WUFx bits are cleared in power status register 1 (PWR_SR1)
Mode entry
130/1325
On return from ISR while:
– SLEEPDEEP bit is set in Cortex®-M0+ System Control register
– SLEEPONEXIT = 1
– No interrupt is pending
– LPMS = “011” in PWR_CR1 and
– WUFx bits are cleared in power status register 1 (PWR_SR1)
– The RTC flag corresponding to the chosen wake-up source (RTC Alarm
A, RTC Alarm B, RTC wake-up, tamper or timestamp flags) is cleared
Mode exit
WKUPx pin edge, RTC event, external Reset in NRST pin, IWDG Reset,
BOR reset
Wake-up latency
Reset phase
RM0503 Rev 2
RM0503
4.3.10
Power control (PWR)
Shutdown mode
The Shutdown mode allows to achieve the lowest power consumption. It is based on the
deepsleep mode, with the voltage regulator disabled. The VCORE domain is consequently
powered off. The PLL, the HSI16, the MSI, the LSI and the HSE oscillators are also
switched off.
SRAM1, SRAM2 and register contents are lost except for registers in the Backup domain.
The BOR is not available in Shutdown mode. No power voltage monitoring is possible in this
mode, therefore the switch to Backup domain is not supported.
I/O states in Shutdown mode
In the Shutdown mode, are by default in floating state. If the APC bit of PWR_CR3 register
has been set, the I/Os can be configured either with a pull-up (refer to PWR_PUCRx
registers (x = A, B, C, D, E, F), or with a pull-down (refer to PWR_PDCRx registers
(x = A, B, C, D, E, F)), or can be kept in analog state if none of the PWR_PUCRx or
PWR_PDCRx register has been set. The pull-down configuration has highest priority over
pull-up configuration in case both PWR_PUCRx and PWR_PDCRx are set for the same I/O.
However this configuration is lost when exiting the Shutdown mode due to the power-on
reset.
Some I/Os (listed in Section 7.3.1: General-purpose I/O (GPIO)) are used for JTAG/SW
debug. They can only be configured to their respective reset pull-up or pull-down state
during Standby mode by setting their respective bit in the PWR_PUCRx or PWR_PDCRx
registers, or configured to floating state if the bit is kept cleared.
The RTC outputs on PC13 are functional in Shutdown mode. PC14 and PC15 used for LSE
are also functional. Up to six wake-up pins (WKUPx, x = 1,2...5) and the 3 RTC tampers are
available.
Entering Shutdown mode
The Shutdown mode is entered according Entering low-power mode, when the
SLEEPDEEP bit in the Cortex®-M0+ System Control register is set.
Refer to Table 30: Shutdown mode for details on how to enter Shutdown mode.
In Shutdown mode, the following features can be selected by programming individual
control bits:
•
real-time clock (RTC): this is configured by the RTCEN bit in the Backup domain
control register (RCC_BDCR). Caution: in case of VDD power-down the RTC content is
lost.
•
external 32.768 kHz oscillator (LSE): this is configured by the LSEON bit in the Backup
domain control register (RCC_BDCR)
Exiting Shutdown mode
The Shutdown mode is exit according Section : Exiting low-power mode. A power-on reset
occurs when exiting from Shutdown mode. All registers (except for the ones in the Backup
domain) are reset after wake-up from Shutdown.
Refer to Table 30: Shutdown mode for more details on how to exit Shutdown mode.
When exiting Shutdown mode, I/Os that were configured with pull-up or pull-down during
Shutdown through the PWR_PUCRx or PWR_PDCRx registers lose their configuration and
RM0503 Rev 2
131/1325
150
Power control (PWR)
RM0503
are configured in floating state or to their pull-up pull-down reset value (for some I/Os listed
in Section 7.3.1: General-purpose I/O (GPIO)).
Table 30. Shutdown mode
Shutdown mode
Description
WFI (Wait for Interrupt) or WFE (Wait for Event) while:
– SLEEPDEEP bit is set in Cortex®-M0+ System Control register
– No interrupt (for WFI) or event (for WFE) is pending
– LPMS = “1XX” in PWR_CR1
– WUFx bits are cleared in power status register 1 (PWR_SR1)
Mode entry
4.3.11
On return from ISR while:
– SLEEPDEEP bit is set in Cortex®-M0+ System Control register
– SLEEPONEXT = 1
– No interrupt is pending
– LPMS = “1XX” in PWR_CR1 and
– WUFx bits are cleared in power status register 1 (PWR_SR1)
– The RTC flag corresponding to the chosen wake-up source (RTC
Alarm A, RTC Alarm B, RTC wake-up, tamper or timestamp flags)
is cleared
Mode exit
WKUPx pin edge, RTC event, external Reset in NRST pin
Wake-up latency
Reset phase
Auto-wakeup from low-power mode
The RTC can be used to wake up the MCU from low-power mode without depending on an
external interrupt (Auto-wakeup mode). The RTC provides a programmable time base for
waking up from Stop (0, 1 or 2) or Standby mode at regular intervals. For this purpose, two
of the three alternative RTC clock sources can be selected by programming the
RTCSEL[1:0] bits in the RTC domain control register (RCC_BDCR):
•
Low-power 32.768 kHz external crystal oscillator (LSE OSC)
This clock source provides a precise time base with very low-power consumption.
•
Low-power internal RC Oscillator (LSI)
This clock source has the advantage of saving the cost of the 32.768 kHz crystal. This
internal RC Oscillator is designed to add minimum power consumption.
To wake up from Stop mode with an RTC alarm event, it is necessary to:
•
Configure the EXTI Line 18 to be sensitive to rising edge
•
Configure the RTC to generate the RTC alarm
To wake up from Standby mode, there is no need to configure the EXTI Line 18.
To wake up from Stop mode with an RTC wake-up event, it is necessary to:
•
Configure the EXTI Line 20 to be sensitive to rising edge
•
Configure the RTC to generate the RTC alarm
To wake up from Standby mode, there is no need to configure the EXTI Line 20.
The LCD Start of frame interrupt can also be used as a periodic wake-up from Stop (0, 1 or
2) mode. The LCD is not available in Standby mode.
132/1325
RM0503 Rev 2
RM0503
Power control (PWR)
The LCD clock is derived from the RTC clock selected by RTCSEL[1:0].
4.4
PWR registers
The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).
4.4.1
Power control register 1 (PWR_CR1)
Address offset: 0x00
Reset value: 0x0000 0208
This register is reset after wake-up from Standby mode.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
FPD_L
PSLP
FPD_L
PRUN
FPD_
STOP
rw
rw
rw
Res.
LPR
rw
Res.
Res.
Res.
VOS[1:0]
DBP
rw
rw
rw
Res.
LPMS[2:0]
rw
rw
rw
Bits 31:15 Reserved, must be kept at reset value.
Bit 14 LPR: Low-power run
When this bit is set, the regulator is switched from main mode (MR) to low-power mode
(LPR).
Note: Stop 2 mode cannot be entered when LPR bit is set. Stop 1 is entered instead.
Bits 13:11 Reserved, must be kept at reset value.
Bits 10:9 VOS[1:0]: Voltage scaling range selection
00: Cannot be written (forbidden by hardware)
01: Range 1
10: Range 2
11: Cannot be written (forbidden by hardware)
Bit 8 DBP: Disable backup domain write protection
In reset state, the RTC and backup registers are protected against parasitic write access.
This bit must be set to enable write access to these registers.
0: Access to RTC and Backup registers disabled
1: Access to RTC and Backup registers enabled
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 FPD_LPSLP: Flash memory powered down during Low-power sleep mode.
This bit determines whether the flash memory is put in power-down mode or remains in idle
mode when the device enters Low-power sleep mode.
0: Flash memory idle
1: Flash memory powered down
RM0503 Rev 2
133/1325
150
Power control (PWR)
RM0503
Bit 4 FPD_LPRUN: Flash memory powered down during Low-power run mode.
This bit determines whether the flash memory is put in power-down mode or remains in idle
mode when the device enters Low-power sleep mode.
0: Flash memory idle
1: Flash memory powered down
Bit 3 FPD_STOP: Flash memory powered down during Stop mode.
This bit determines whether the flash memory is put in power-down mode or remains in idle
mode when the device enters Stop mode.
0: Flash memory idle
1: Flash memory powered down
Bits 2:0 LPMS[2:0]: Low-power mode selection
These bits select the low-power mode entered when CPU enters the deepsleep mode.
000: Stop 0 mode
001: Stop 1 mode
010: Stop 2 mode
011: Standby mode
1xx: Shutdown mode
Note: If LPR bit is set, Stop 2 mode cannot be selected and Stop 1 mode shall be entered
instead of Stop 2.
In Standby mode, SRAM2 can be preserved or not, depending on RRS bit configuration
in PWR_CR3.
4.4.2
Power control register 2 (PWR_CR2)
Address offset: 0x04
Reset value: 0x0000 0000
This register is reset when exiting the Standby mode.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
USV(1)
Res.
Res.
Res.
rw
PVME4 PVME3
rw
rw
PVME1
PLS[2:0]
(1)
rw
rw
rw
PVDE
rw
rw
1. Available on STM32U0x3xx devices only.
Bits 31:11 Reserved, must be kept at reset value.
Bit 10 USV(1): VDDUSB USB supply valid
This bit is used to validate the VDDUSB supply for electrical and logical isolation purpose.
Setting this bit is mandatory to use the USB FS peripheral. If VDDUSB is not always
present in the application, the PVM can be used to determine whether this supply is ready or
not.
0: VDDUSB is not present. Logical and electrical isolation is applied to ignore this supply.
1: VDDUSB is valid.
Bits 9:7 Reserved, must be kept at reset value.
134/1325
RM0503 Rev 2
RM0503
Power control (PWR)
Bit 6 PVME4: Peripheral voltage monitoring 4 enable: VDDA vs. 1.86 V
0: PVM4 (VDDA monitoring vs. 1.86 V threshold) disable.
1: PVM4 (VDDA monitoring vs. 1.86 V threshold) enable.
Bit 5 PVME3: Peripheral voltage monitoring 3 enable: VDDA vs. 1.62 V
0: PVM3 (VDDA monitoring vs. 1.62 V threshold) disable.
1: PVM3 (VDDA monitoring vs. 1.62 V threshold) enable.
Bit 4 PVME1(1): Peripheral voltage monitoring 1 enable: VDDUSB vs. 1.2 V
0: PVM1 (VDDUSB monitoring vs. 1.2 V threshold) disable.
1: PVM1 (VDDUSB monitoring vs. 1.2 V threshold) enable.
Bits 3:1 PLS[2:0]: Programmable voltage detector level selection.
These bits select the voltage threshold detected by the programmable voltage detector:
000: VPVD0 around 2.0 V
001: VPVD1 around 2.2 V
010: VPVD2 around 2.4 V
011: VPVD3 around 2.5 V
100: VPVD4 around 2.6 V
101: VPVD5 around 2.8 V
110: VPVD6 around 2.9 V
111: External input analog voltage PVD_IN (compared internally to VREFINT)
Note: These bits are write-protected when the bit PVDL (PVD Lock) is set in the
SYSCFG_CBR register.
These bits are reset only by a system reset.
Bit 0 PVDE: Programmable voltage detector enable
0: Programmable voltage detector disable.
1: Programmable voltage detector enable.
Note: This bit is write-protected when the bit PVDL (PVD Lock) is set in the SYSCFG_CBR
register.
This bit is reset only by a system reset.
1. Available on STM32U0 devices only.
4.4.3
Power control register 3 (PWR_CR3)
Address offset: 0x08
Reset value: 0x0000 8000
This register is neither reset when exiting Standby or Shutdown mode, nor by the PWRRST
bit in the RCC_APB1RSTR1 register.
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
EWUP
7
Res.
EWUP
5
EWUP
4
EWUP
3
EWUP
2
EWUP
1
rw
rw
rw
rw
rw
EIWUL
rw
Res.
Res.
Res.
Res.
APC
ENULP
RRS
rw
rw
rw
RM0503 Rev 2
rw
135/1325
150
Power control (PWR)
RM0503
Bits 31:16 Reserved, must be kept at reset value.
Bit 15 EIWUL: Enable internal wake-up line
0: Internal wake-up line disable.
1: Internal wake-up line enable.
Bits 14:11 Reserved, must be kept at reset value.
Bit 10 APC: Apply pull-up and pull-down configuration
When this bit is set, the I/O pull-up and pull-down configurations defined in the PWR_PUCRx
and PWR_PDCRx registers are applied. When this bit is cleared, the PWR_PUCRx and
PWR_PDCRx registers are not applied to the I/Os, instead the I/Os are in floating mode
during Standby or configured according GPIO controller GPIOx_PUPDR register during RUN
mode.
Bit 9 ENULP: Enable ULP sampling
When this bit is set, the BORL, BORH and PVD are periodically sampled instead continuous
monitoring to reduce power consumption. Fast supply drop between two sample/compare
phases is not detected in this mode. This bit has impact only on Stop 2 and Standby lowpower modes.
Bit 8 RRS: SRAM2 retention in Standby mode
0: SRAM2 is powered off in Standby mode (SRAM2 content is lost).
1: SRAM2 is powered by the low-power regulator in Standby mode (SRAM2 content is kept).
Bit 7 Reserved, must be kept at reset value.
Bit 6 EWUP7: Enable Wake-up pin WKUP7.
When this bit is set, the external wake-up pin WKUP7 is enabled and triggers a wake-up from
Standby or Shutdown event when a rising or a falling edge occurs.The active edge is
configured via the WP7 bit in the PWR_CR4 register.
Bit 5 Reserved, must be kept at reset value.
Bit 4 EWUP5: Enable Wake-up pin WKUP5
When this bit is set, the external wake-up pin WKUP5 is enabled and triggers a wake-up from
Standby or Shutdown event when a rising or a falling edge occurs.The active edge is
configured via the WP5 bit in the PWR_CR4 register.
Bit 3 EWUP4: Enable Wake-up pin WKUP4
When this bit is set, the external wake-up pin WKUP4 is enabled and triggers a wake-up from
Standby or Shutdown event when a rising or a falling edge occurs. The active edge is
configured via the WP4 bit in the PWR_CR4 register.
Bit 2 EWUP3: Enable Wake-up pin WKUP3
When this bit is set, the external wake-up pin WKUP3 is enabled and triggers a wake-up from
Standby or Shutdown event when a rising or a falling edge occurs. The active edge is
configured via the WP3 bit in the PWR_CR4 register.
Bit 1 EWUP2: Enable Wake-up pin WKUP2
When this bit is set, the external wake-up pin WKUP2 is enabled and triggers a wake-up from
Standby or Shutdown event when a rising or a falling edge occurs. The active edge is
configured via the WP2 bit in the PWR_CR4 register.
Bit 0 EWUP1: Enable Wake-up pin WKUP1
When this bit is set, the external wake-up pin WKUP1 is enabled and triggers a wake-up from
Standby or Shutdown event when a rising or a falling edge occurs. The active edge is
configured via the WP1 bit in the PWR_CR4 register.
136/1325
RM0503 Rev 2
RM0503
Power control (PWR)
4.4.4
Power control register 4 (PWR_CR4)
Address offset: 0x0C
Reset value: 0x0000 0000
This register is neither reset when exiting Standby or Shutdown mode, nor by the PWRRST
bit in the RCC_APB1RSTR1 register.
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
VBRS
VBE
Res.
WP7
Res.
WP5
WP4
WP3
WP2
WP1
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:10 Reserved, must be kept at reset value.
Bit 9 VBRS: VBAT battery charging resistor selection
0: Charge VBAT through a 5 kOhms resistor
1: Charge VBAT through a 1.5 kOhms resistor
Bit 8 VBE: VBAT battery charging enable
0: VBAT battery charging disable
1: VBAT battery charging enable
Bit 7 Reserved, must be kept at reset value.
Bit 6 WP7: Wake-up pin WKUP7 polarity
This bit defines the polarity used for an event detection on external wake-up pin, WKUP7
0: Detection on high level (rising edge)
1: Detection on low level (falling edge)
Bit 5 Reserved, must be kept at reset value.
Bit 4 WP5: Wake-up pin WKUP5 polarity
This bit defines the polarity used for an event detection on external wake-up pin, WKUP5
0: Detection on high level (rising edge)
1: Detection on low level (falling edge)
Bit 3 WP4: Wake-up pin WKUP4 polarity
This bit defines the polarity used for an event detection on external wake-up pin, WKUP4
0: Detection on high level (rising edge)
1: Detection on low level (falling edge)
RM0503 Rev 2
137/1325
150
Power control (PWR)
RM0503
Bit 2 WP3: Wake-up pin WKUP3 polarity
This bit defines the polarity used for an event detection on external wake-up pin, WKUP3
0: Detection on high level (rising edge)
1: Detection on low level (falling edge)
Bit 1 WP2: Wake-up pin WKUP2 polarity
This bit defines the polarity used for an event detection on external wake-up pin, WKUP2
0: Detection on high level (rising edge)
1: Detection on low level (falling edge)
Bit 0 WP1: Wake-up pin WKUP1 polarity
This bit defines the polarity used for an event detection on external wake-up pin, WKUP1
0: Detection on high level (rising edge)
1: Detection on low level (falling edge)
4.4.5
Power status register 1 (PWR_SR1)
Address offset: 0x10
Reset value: 0x0000 0000
This register is neither reset when exiting Standby or Shutdown mode, nor by the PWRRST
bit in the RCC_APB1RSTR1 register.
Access: 2 additional APB cycles are needed to read this register vs. a standard APB read.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
WUFI
Res.
Res.
Res.
SBF
Res.
WUF7
Res.
WUF5
WUF4
WUF3
WUF2
WUF1
r
r
r
r
r
r
STOPF[2:0]
r
r
r
r
r
Bits 31:16 Reserved, must be kept at reset value.
Bit 15 WUFI: Wake-up flag internal
This bit is set when a wake-up is detected on the internal wake-up line. It is cleared when all
internal wake-up sources are cleared.
Bits 14:12 Reserved, must be kept at reset value.
Bits 11:9 STOPF[2:0]: Stop Flags
These bits are set by hardware when the device enters any stop mode and are cleared by
setting the CSBF bit in the PWR_SCR register, or by a power-on reset. It is not cleared by the
system reset.
000: The device did not enter any Stop mode.
100: The device entered in Stop 0 mode.
101: The device entered in Stop 1 mode.
110: The device entered in Stop 2 mode.
138/1325
RM0503 Rev 2
RM0503
Power control (PWR)
Bit 8 SBF: Standby flag
This bit is set by hardware when the device enters the Standby mode and is cleared by
setting the CSBF bit in the PWR_SCR register, or by a power-on reset. It is not cleared by the
system reset.
0: The device did not enter the Standby mode
1: The device entered the Standby mode
Bit 7 Reserved, must be kept at reset value.
Bit 6 WUF7: Wake-up flag 7
This bit is set when a wake-up event is detected on wake-up pin, WKUP7. It is cleared by
writing ‘1’ in the CWUF7 bit of the PWR_SCR register.
Bit 5 Reserved, must be kept at reset value.
Bit 4 WUF5: Wake-up flag 5
This bit is set when a wake-up event is detected on wake-up pin, WKUP5. It is cleared by
writing ‘1’ in the CWUF5 bit of the PWR_SCR register.
Bit 3 WUF4: Wake-up flag 4
This bit is set when a wake-up event is detected on wake-up pin,WKUP4. It is cleared by
writing ‘1’ in the CWUF4 bit of the PWR_SCR register.
Bit 2 WUF3: Wake-up flag 3
This bit is set when a wake-up event is detected on wake-up pin, WKUP3. It is cleared by
writing ‘1’ in the CWUF3 bit of the PWR_SCR register.
Bit 1 WUF2: Wake-up flag 2
This bit is set when a wake-up event is detected on wake-up pin, WKUP2. It is cleared by
writing ‘1’ in the CWUF2 bit of the PWR_SCR register.
Bit 0 WUF1: Wake-up flag 1
This bit is set when a wake-up event is detected on wake-up pin, WKUP1. It is cleared by
writing ‘1’ in the CWUF1 bit of the PWR_SCR register.
4.4.6
Power status register 2 (PWR_SR2)
Address offset: 0x14
Reset value: 0x0000 0000
This register is partially reset when exiting Standby/Shutdown modes.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PVMO4 PVMO3
r
r
Res.
PVMO1
(1)
PVDO
VOSF
r
r
r
REGLP REGLP FLASH
F
S
_RDY
r
r
r
1. Available on STM32U0x3xx devices only.
RM0503 Rev 2
139/1325
150
Power control (PWR)
RM0503
Bits 31:16 Reserved, must be kept at reset value.
Bit 15 PVMO4: Peripheral voltage monitoring output: VDDA vs. 2.2 V
0: VDDA voltage is above PVM4 threshold (around 2.2 V).
1: VDDA voltage is below PVM4 threshold (around 2.2 V).
Note: PVMO4 is cleared when PVM4 is disabled (PVME4 = 0). After enabling PVM4, the
PVM4 output is valid after the PVM4 wake-up time.
Bit 14 PVMO3: Peripheral voltage monitoring output: VDDA vs. 1.62 V
0: VDDA voltage is above PVM3 threshold (around 1.62 V).
1: VDDA voltage is below PVM3 threshold (around 1.62 V).
Note: PVMO3 is cleared when PVM3 is disabled (PVME3 = 0). After enabling PVM3, the
PVM3 output is valid after the PVM3 wake-up time.
Bit 13 Reserved, must be kept at reset value.
Bit 12 PVMO1(1): Peripheral voltage monitoring output: VDDUSB vs. 1.2 V
0: VDDUSB voltage is above PVM1 threshold (around 1.2 V).
1: VDDUSB voltage is below PVM1 threshold (around 1.2 V).
Note: PVMO1 is cleared when PVM1 is disabled (PVME1 = 0). After enabling PVM1, the
PVM1 output is valid after the PVM1 wake-up time.
Bit 11 PVDO: Programmable voltage detector output
0: VDD is above the selected PVD threshold
1: VDD is below the selected PVD threshold
Bit 10 VOSF: Voltage scaling flag
A delay is required for the internal regulator to be ready after the voltage scaling has been
changed. VOSF indicates that the regulator reached the voltage level defined with VOS bits
of the PWR_CR1 register.
0: The regulator is ready in the selected voltage range
1: The regulator output voltage is changing to the required voltage level
Bit 9 REGLPF: Low-power regulator flag
This bit is set by hardware when the MCU is in Low-power run mode. When the MCU exits
from the Low-power run mode, this bit remains at 1 until the regulator is ready in main mode.
A polling on this bit must be done before increasing the product frequency.
This bit is cleared by hardware when the regulator is ready.
0: The regulator is ready in main mode (MR)
1: The regulator is in low-power mode (LPR)
140/1325
RM0503 Rev 2
RM0503
Power control (PWR)
Bit 8 REGLPS: Low-power regulator started
This bit provides the information whether the low-power regulator is ready after a power-on
reset or a Standby/Shutdown. If the Standby mode is entered while REGLPS bit is still
cleared, the wake-up from Standby mode time may be increased.
0: The low-power regulator is not ready
1: The low-power regulator is ready
Bit 7 FLASH_RDY: Flash ready flag
This bit is set by hardware to indicate when the flash memory is readey to be accessed after
wake-up from power-down. To place the flash memory in power-down, set either
FPD_LPRUN, FPD_LPSLP or FPD_STP bits.
0: Flash memory in power down
1: Flash memory ready to be accessed
Note: If the system boots from SRAM, the user application must wait until the FLASH_RDY bit
is set, prior to jumping to flash memory.
Bits 6:0 Reserved, must be kept at reset value.
1. Available on STM32U0x3xx devices only.
4.4.7
Power status clear register (PWR_SCR)
Address offset: 0x18
Reset value: 0x0000 0000
Access: 3 additional APB cycles are needed to write this register vs. a standard APB write.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
CWUF
7
Res.
CWUF
5
CWUF
4
CWUF
3
CWUF
2
CWUF
1
w
w
w
w
w
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CSBF
w
w
Bits 31:9 Reserved, must be kept at reset value.
Bit 8 CSBF: Clear standby flag
Setting this bit clears the SBF flag in the PWR_SR1 register.
Bit 7 Reserved, must be kept at reset value.
Bit 6 CWUF7: Clear wake-up flag 7
Setting this bit clears the WUF7 flag in the PWR_SR1 register.
Bit 5 Reserved, must be kept at reset value.
Bit 4 CWUF5: Clear wake-up flag 5
Setting this bit clears the WUF5 flag in the PWR_SR1 register.
Bit 3 CWUF4: Clear wake-up flag 4
Setting this bit clears the WUF4 flag in the PWR_SR1 register.
RM0503 Rev 2
141/1325
150
Power control (PWR)
RM0503
Bit 2 CWUF3: Clear wake-up flag 3
Setting this bit clears the WUF3 flag in the PWR_SR1 register.
Bit 1 CWUF2: Clear wake-up flag 2
Setting this bit clears the WUF2 flag in the PWR_SR1 register.
Bit 0 CWUF1: Clear wake-up flag 1
Setting this bit clears the WUF1 flag in the PWR_SR1 register.
4.4.8
Power Port A pull-up control register (PWR_PUCRA)
Address offset: 0x20
Reset value: 0x0000 0000
This register is neither reset when exiting Standby or Shutdown mode, nor by the PWRRST
bit in the RCC_APB1RSTR1 register.
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PU15
PU14
PU13
PU12
PU11
PU10
PU9
PU8
PU7
PU6
PU5
PU4
PU3
PU2
PU1
PU0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 PUy: Port A pull-up bit y (y = 15 to 0)
When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If
the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is
activated instead with highest priority.
4.4.9
Power Port A pull-down control register (PWR_PDCRA)
Address offset: 0x24
Reset value: 0x0000 0000
This register is neither reset when exiting Standby or Shutdown mode, nor by the PWRRST
bit in the RCC_APB1RSTR1 register.
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PD15
PD14
PD13
PD12
PD11
PD10
PD9
PD8
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
142/1325
RM0503 Rev 2
RM0503
Power control (PWR)
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 PDy: Port A pull-down bit y (y = 15 to 0)
When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register.
4.4.10
Power Port B pull-up control register (PWR_PUCRB)
Address offset: 0x28
Reset value: 0x0000 0000
This register is neither reset when exiting Standby or Shutdown mode, nor by the PWRRST
bit in the RCC_APB1RSTR1 register.
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PU15
PU14
PU13
PU12
PU11
PU10
PU9
PU8
PU7
PU6
PU5
PU4
PU3
PU2
PU1
PU0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 PUy: Port B pull-up bit y (y = 15 to 0)
When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register.
RM0503 Rev 2
143/1325
150
Power control (PWR)
4.4.11
RM0503
Power Port B pull-down control register (PWR_PDCRB)
Address offset: 0x2C
Reset value: 0x0000 0000
This register is neither reset when exiting Standby or Shutdown mode, nor by the PWRRST
bit in the RCC_APB1RSTR1 register.
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PD15
PD14
PD13
PD12
PD11
PD10
PD9
PD8
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 PDy: Port B pull-down bit y (y = 15 to 0)
When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register.
4.4.12
Power Port C pull-up control register (PWR_PUCRC)
Address offset: 0x30
Reset value: 0x0000 0000
This register is neither reset when exiting Standby or Shutdown mode, nor by the PWRRST
bit in the RCC_APB1RSTR1 register.
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PU15
PU14
PU13
PU12
PU11
PU10
PU9
PU8
PU7
PU6
PU5
PU4
PU3
PU2
PU1
PU0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 PUy: Port C pull-up bit y (y = 15 to 0)
When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If
the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is
activated instead with highest priority.
144/1325
RM0503 Rev 2
RM0503
Power control (PWR)
4.4.13
Power Port C pull-down control register (PWR_PDCRC)
Address offset: 0x34
Reset value: 0x0000 0000
This register is neither reset when exiting Standby or Shutdown mode, nor by the PWRRST
bit in the RCC_APB1RSTR1 register.
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PD15
PD14
PD13
PD12
PD11
PD10
PD9
PD8
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 PDy: Port C pull-down bit y (y = 15 to 0)
When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register.
4.4.14
Power Port D pull-up control register (PWR_PUCRD)
Address offset: 0x38
Reset value: 0x0000 0000
This register is neither reset when exiting Standby or Shutdown mode, nor by the PWRRST
bit in the RCC_APB1RSTR1 register.
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
PU13
PU12
PU11
PU10
PU9
PU8
Res.
PU6
PU5
PU4
PU3
PU2
PU1
PU0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:14 Reserved, must be kept at reset value.
RM0503 Rev 2
145/1325
150
Power control (PWR)
RM0503
Bits 13:8 PUy: Port D pull-up bit y (y = 13 to 8)
When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If
the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is
activated instead with highest priority.
Bit 7 Reserved, must be kept at reset value.
Bits 6:0 PUy: Port D pull-up bit y (y = 6 to 0)
When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If
the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated
instead with highest priority.
4.4.15
Power Port D pull-down control register (PWR_PDCRD)
Address offset: 0x3C
Reset value: 0x0000 0000
This register is neither reset when exiting Standby or Shutdown mode, nor by the PWRRST
bit in the RCC_APB1RSTR1 register.
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
PD13
PD12
PD11
PD10
PD9
PD8
Res.
PD6
PD5
PD4
PD3
PD2
PD1
PD0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:14 Reserved, must be kept at reset value.
Bits 13:8 PDy: Port D pull-down bit y (y = 13 to 8)
When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register.
Bit 7 Reserved, must be kept at reset value.
Bits 6:0 PDy: Port D pull-down bit y (y = 6 to 0)
When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register.
4.4.16
Power Port E pull-up control register (PWR_PUCRE)
Address offset: 0x40
Reset value: 0x0000 0000
This register is neither reset when exiting Standby or Shutdown mode, nor by the PWRRST
bit in the RCC_APB1RSTR1 register.
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).
146/1325
RM0503 Rev 2
RM0503
Power control (PWR)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
PU9
PU8
PU7
Res.
Res.
Res.
PU3
Res.
Res.
Res.
rw
rw
rw
rw
Bits 31:10 Reserved, must be kept at reset value.
Bits 9:7 PUy: Port E pull-up bit y (y = 9 to 7)
When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. If
the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is
activated instead with highest priority.
Bits 6:4 Reserved, must be kept at reset value.
Bit 3 PU3: Port E pull-up bit 3
When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. If
the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is
activated instead with highest priority.
Bits 2:0 Reserved, must be kept at reset value.
4.4.17
Power Port E pull-down control register (PWR_PDCRE)
Address offset: 0x44
Reset value: 0x0000 0000
This register is neither reset when exiting Standby or Shutdown mode, nor by the PWRRST
bit in the RCC_APB1RSTR1 register.
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
PD9
PD8
PD7
Res.
Res.
Res.
PD3
Res.
Res.
Res.
rw
rw
rw
rw
Bits 31:10 Reserved, must be kept at reset value.
Bits 9:7 PDy: Port E pull-down bit y (y = 9 to 7)
When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register.
Bits 6:4 Reserved, must be kept at reset value.
Bit 3 PD3: Port E pull-down bit 3
When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register.
Bits 2:0 Reserved, must be kept at reset value.
RM0503 Rev 2
147/1325
150
Power control (PWR)
4.4.18
RM0503
Power Port F pull-up control register (PWR_PUCRF)
Address offset: 0x48
Reset value: 0x0000 0000
This register is neither reset when exiting Standby or Shutdown mode, nor by the PWRRST
bit in the RCC_APB1RSTR1 register.
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PU3
PU2
PU1
PU0
rw
rw
rw
rw
Bits 31:4 Reserved, must be kept at reset value.
Bits 3:0 PUy: Port F pull-up bit y (y = 3 to 0)
When set, this bit activates the pull-up on PH[y] when APC bit is set in PWR_CR3 register.
If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is
activated instead with highest priority.
4.4.19
Power Port F pull-down control register (PWR_PDCRF)
Address offset: 0x4C
Reset value: 0x0000 0000
This register is neither reset when exiting Standby or Shutdown mode, nor by the PWRRST
bit in the RCC_APB1RSTR1 register.
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PD3
PD2
PD1
PD0
rw
rw
rw
rw
Bits 31:4 Reserved, must be kept at reset value.
Bits 3:0 PDy: Port F pull-down bit y (y = 3 to 0)
When set, this bit activates the pull-down on PH[y] when APC bit is set in PWR_CR3 register.
148/1325
RM0503 Rev 2
0x038
PWR_PUCRD
RM0503 Rev 2
PD13
PD12
PD11
PD10
PD9
PD8
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PU13
PU12
PU11
PU10
PU9
PU8
Res.
PU6
PU5
PU4
PU3
PU2
PU1
PU0
Reset value
PU14
PU13
PU12
PU11
PU10
PU9
PU8
PU7
PU6
PU5
PU4
PU3
PU2
PU1
PU0
Reset value
PD14
PD14
PD13
PD12
PD11
PD10
PD9
PD8
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
Reset value
Res.
PU14
PU13
PU12
PU11
PU10
PU9
PU8
PU7
PU6
PU5
PU4
PU3
PU2
PU1
PU0
Reset value
PD14
PD13
PD12
PD11
PD10
PD9
PD8
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PD15
Reset value
PU15
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PU14
PU13
PU12
PU11
PU10
PU9
PU8
PU7
PU6
PU5
PU4
PU3
PU2
PU1
PU0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PU15
Reset value
PD15
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
0
Res.
Res.
CWUF2
CWUF1
0
Res.
0
CWUF3
0
Res.
0
Res.
0
CWUF4
0
CWUF5
0
Res.
0
Res.
WP4
WP3
WP2
WP1
0
0
0
0
0
WUF3
WUF2
WUF1
0
WP5
0
WUF4
Res.
WP7
Res.
LPMS
[2:0]
0
0
1
0
0
0
PVDE
Res.
EWUP1
0
EWUP2
0
FPD_STOP
0
EWUP3
0
FPD_LPRUN
PVME1
0
EWUP4
PVME3
0
FPD_LPSLP
PVME4
0
EWUP7
Res.
DBP
Res.
Res.
Res.
PLS [2:0]
EWUP5
0
WUF5
Res.
0
WUF7
0
Res.
0
Res.
0
Res.
RRS
0
VBE
Res.
Res.
Res.
LPR
Res.
1
USV
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
ENULP
0
VBRS
Res.
Res.
APC
Res.
Res.
0
Res.
Reset value
SBF
STOPF[2:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
VOS
[1:0]
CWUF7
FLASH_RDY
0
Res.
Res.
0
REGLPF
PVDO
0
Res.
Res.
1
REGLPS
PVMO1
0
Res.
Res.
Res.
EIWUL
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
CSBF
PVMO3
0
Res.
WUFI
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
VOSF
PVMO4
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
PU15
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
PD15
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PWR_PDCRC
Res.
0x034
PWR_PUCRC
Res.
0x030
PWR_PDCRB
Res.
0x02C
PWR_PUCRB
Res.
0x028
PWR_PDCRA
Res.
0x024
PWR_PUCRA
Res.
0x020
PWR_SCR
Res.
0x018
PWR_SR2
Res.
0x014
PWR_SR1
Res.
0x010
PWR_CR4
Res.
0x00C
PWR_CR3
Res.
0x008
PWR_CR2
Res.
0x004
PWR_CR1
Res.
0x000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Register
Res.
Offset
Res.
4.4.20
Res.
RM0503
Power control (PWR)
PWR register map and reset value table
Table 31. PWR register map and reset values
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
149/1325
150
0x04C
150/1325
PWR_PDCRF
RM0503 Rev 2
Refer to Section 2.2 on page 55 for the register boundary addresses
Res.
Res.
Res.
PU1
PU0
0
0
0
0
PD1
PD0
PD3
Res.
PU2
Reset value
PD2
Res.
0
PU3
Res.
Res.
Res.
Res.
PD5
PD4
PD3
PD2
PD1
PD0
0
0
0
0
0
0
Res.
Res.
PU3
Res.
Res.
Res.
PD6
0
Res.
0
Res.
Res.
0
Res.
PD8
Res.
0
PD3
Reset value
Res.
0
PU7
PD9
0
Res.
PD7
0
Res.
PD11
PD10
0
PU8
PD12
0
PU9
PD13
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
PD8
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
PWR_PDCRD
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Register
0
Res.
PD9
0
Res.
Res.
Res.
Res.
0
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PWR_PUCRF
Res.
0x048
PWR_PDCRE
Res.
0x044
PWR_PUCRE
Res.
0x040
Res.
0x03C
Res.
Offset
Res.
Power control (PWR)
RM0503
Table 31. PWR register map and reset values (continued)
0
0
0
0
0
RM0503
Reset and clock control (RCC)
5
Reset and clock control (RCC)
5.1
Reset
There are three types of reset, defined as system reset, power reset and RTC domain reset.
5.1.1
Power reset
A power reset is generated when one of the following events occurs:
•
power-on reset (POR) or brown-out reset (BOR)
•
exit from Standby mode
•
exit from Shutdown mode
Power and brown-out reset set all registers to their reset values except the registers of the
RTC domain.
When exiting Standby mode, all registers in the VCORE domain are set to their reset value.
Registers outside the VCORE domain (RTC, WKUP, IWDG, and Standby/Shutdown mode
control) are not impacted.
When exiting Shutdown mode, the brown-out reset is generated, resetting all registers
except those in the RTC domain.
5.1.2
System reset
A system reset sets all registers to their reset value unless otherwise specified in the
register descriptions.
System reset is generated when one of the following events occurs:
•
low level on the NRST pin (external reset)
•
window watchdog event (WWDG reset)
•
independent watchdog event (IWDG reset)
•
software reset (SW reset) (see Software reset)
•
low-power mode security reset (see Low-power mode security reset)
•
option byte loader reset (see Option byte loader reset)
•
power-on reset
The reset source can be identified by checking the reset flags in the RCC_CSR register
(see Section 5.4.23: Control/status register (RCC_CSR)).
NRST pin (external reset):
Through specific option bits, the NRST pin is configurable for operating as:
•
Reset input/output (default at device delivery)
Valid reset signal on the pin is propagated to the internal logic, and each internal reset
source is led to a pulse generator the output of which drives this pin. The GPIO
functionality (PF2) is not available. The pulse generator guarantees a minimum reset
pulse duration of 20 µs for each internal reset source to be output on the NRST pin. An
internal reset holder option can be used, if enabled in the option bytes, to ensure that
the pin is pulled low until its voltage meets VIL threshold. This function allows the
RM0503 Rev 2
151/1325
213
Reset and clock control (RCC)
RM0503
detection of internal reset sources by external components when the line faces a
significant capacitive load.
•
Reset input
In this mode, any valid reset signal on the NRST pin is propagated to device internal
logic, but resets generated internally by the device are not visible on the pin. In this
configuration, GPIO functionality (PF2) is not available.
•
GPIO
In this mode, the pin can be used as PF2 standard GPIO. The reset function of the pin
is not available. Reset is only possible from device internal reset sources and it is not
propagated to the pin.
Figure 10. Simplified diagram of the reset circuit
VDD
RPU
System reset
External
reset
Filter
NRST
Pulse
generator
(min 20 ȝs)
Internal
reset sources
Bidirectional
reset
Reset holder
D
Q
CLEAR
MSv47935V1
Caution:
Upon power reset or wake-up from shutdown mode, the NRST pin is configured as Reset
input/output and driven low by the system until it is reconfigured to the expected mode when
the option bytes are loaded, in the fourth clock cycle after the end of trstempo.
Software reset
The SYSRESETREQ bit in Cortex®-M0+ Application interrupt and reset control register
must be set to force a software reset on the device (refer to the programming manual
PM0223).
152/1325
RM0503 Rev 2
RM0503
Reset and clock control (RCC)
Low-power mode security reset
To prevent that critical applications mistakenly enter a low-power mode, three low-power
mode security resets are available. If enabled in option bytes, the resets are generated in
the following conditions:
•
Entering Standby mode
This type of reset is enabled by resetting nRST_STDBY bit in user option bytes. In this
case, whenever a Standby mode entry sequence is successfully executed, the device
is reset instead of entering Standby mode.
•
Entering Stop mode
This type of reset is enabled by resetting nRST_STOP bit in user option bytes. In this
case, whenever a Stop mode entry sequence is successfully executed, the device is
reset instead of entering Stop mode.
•
Entering Shutdown mode
This type of reset is enabled by resetting nRST_SHDW bit in user option bytes. In this
case, whenever a Shutdown mode entry sequence is successfully executed, the device
is reset instead of entering Shutdown mode.
For further information on the user option bytes, refer to Section 3.4: FLASH option bytes.
Option byte loader reset
The option byte loader reset is generated when the OBL_LAUNCH bit (bit 27) is set in the
FLASH_CR register. This bit is used to launch the option byte loading by software.
5.1.3
RTC domain reset
The RTC domain has three specific resets.
A RTC domain reset is generated when one of the following events occurs:
•
Software reset, triggered by setting the BDRST bit in the RTC domain control register
(RCC_BDCR).
•
VDD or VBAT power on, if both supplies have previously been powered off.
•
Exit from Shutdown, forced when the BDRST bit in the FLASH option register
(FLASH_OPTR) is set.
A RTC domain reset only affects the LSE oscillator, the RTC, the backup registers and the
RCC RTC domain control register.
RM0503 Rev 2
153/1325
213
Reset and clock control (RCC)
5.2
RM0503
Clocks
The device provides the following clock sources producing primary clocks:
•
HSI16 RC - a high-speed fully-integrated RC oscillator producing HSI16 clock (about
16 MHz)
•
HSI48 RC - a high-speed fully-integrated RC oscillator producing HSI48 clock for USB
and RNG (about 48 MHz)
•
MSI - (multispeed internal) RC oscillator clock
•
HSE OSC - a high-speed oscillator with external crystal/ceramic resonator or external
clock source, producing HSE clock (4 to 48 MHz)
•
LSI RC - a low-speed fully-integrated RC oscillator producing LSI clock (about 32 kHz)
•
LSE OSC - a low-speed oscillator with external crystal/ceramic resonator or external
clock source, producing LSE clock (accurate 32.768 kHz or external clock up to
1 MHz)
Each oscillator can be switched on or off independently when it is not used, to optimize
power consumption. Check sub-sections of this section for more functional details. For
electrical characteristics of the internal and external clock sources, refer to the device
datasheet.
The device produces secondary clocks by dividing or/and multiplying the primary clocks:
•
HSISYS - a clock derived from HSI16 through division by a factor programmable from 1
to 128
•
PLLPCLK, PLLQCLK and PLLRCLK - clocks output from the PLL block
•
SYSCLK - a clock obtained through selecting one of LSE, LSI, HSE, MSI, PLLRCLK,
and HSISYS clocks
•
HCLK - a clock derived from SYSCLK through division by a factor programmable from
1 to 512
•
HCLK8 - a clock derived from HCLK through division by eight
•
PCLK - a clock derived from HCLK through division by a factor programmable from 1 to
16
•
LPTIMx_IN - clock from LPTIMx_INx pins, selectable for the LPTIM peripheral
More secondary clocks are generated by fixed division of HSE, HSI16 and HCLK clocks.
The MSI in Range 6 is used as system clock source after startup from reset, delivering a
4 MHz frequency.
The HCLK clock and PCLK clock are used for clocking the AHB and the APB domains,
respectively. Their maximum allowed frequency is 64 MHz.
154/1325
RM0503 Rev 2
RM0503
Reset and clock control (RCC)
The peripherals are clocked with the clocks from the bus they are attached to (HCLK for
AHB, PCLK for APB) except:
•
•
TIMx, with these clock sources to select from:
–
TIMPCLK (selectable for all timers) running at PCLK frequency
–
PLLQCLK selectable for high-speed TIM1 and TIM15 timers
LPTIMx, with these clock sources to select from:
–
LSI
–
LSE
–
HSI16
–
PCLK (APB clock)
–
LPTIMx_IN selected from LPTIMx_INx pins
The functionality in Stop mode (including wake-up) is supported only when the clock is
LSI or LSE.
•
•
ADC, with these clock sources to select from:
–
SYSCLK (system clock)
–
HSI16
–
PLLPCLK
USARTx / LPUARTx, with these clock sources to select from:
–
SYSCLK (system clock)
–
HSI16
–
LSE
–
PCLK (APB clock)
The wake-up from Stop mode is supported only when the clock is HSI16 or LSE.
•
I2C1/I2C3, with these clock sources to select from:
–
SYSCLK (system clock)
–
HSI16
–
PCLK (APB clock)
The wake-up from Stop mode is supported only when the clock is HSI16.
•
RNG, with these clock sources to select from:
–
SYSCLK (system clock)
–
HSI16 clock divided by 8
–
PLLQCLK
The RNG clock can additionally be divided by 2, 4 or 8, using a dedicated prescaler.
RM0503 Rev 2
155/1325
213
Reset and clock control (RCC)
•
RM0503
RTC, with these clock sources to select from:
–
LSE
–
LSI
–
HSE clock divided by 32
The functionality in Stop mode (including wake-up) is supported only when the clock is
LSI or LSE.
•
IWDG, always clocked with LSI clock.
•
USB, with these clocks to select from:
•
–
MSI
–
HSI48
–
PLLQCLK
SysTick (Cortex® core system timer), with these clock sources to select from:
–
HCLK (AHB clock)
–
HCLK clock divided by 8
The selection is done through SysTick control and status register.
HCLK is used as Cortex®-M0+ free-running clock (FCLK). For more details, refer to the
programming manual PM0223.
156/1325
RM0503 Rev 2
RM0503
Reset and clock control (RCC)
Figure 11. Clock tree
to IWDG
LSI
LSI RC
32 kHz
RTC WAKEUP
LSI
LSI
LSCO
HSE
LSE OSC
32.768 kHz
OSC32_IN
/32
LSE
Clock
detector
MCO
LSE
LSI
SYSCLK
HSE
HSI16
HSI48(1)
PLLRCLK
MSI
RTCCLK
RTC WAKEUP
/ 1...1024
MCO2
/ 1...1024
OSC_OUT
HSE OSC
4-48 MHz
OSC_IN
to PWR
to AHB bus, core, memory and DMA
AHB
PRESC
/ 1,2,..512
LSE
MSI
PLLRCLK
CRS
HSISYS
/1…128
HSI16 RC
16 MHz
PLL
fVCO
x
HSI16
fPLLIN
/M
to APB peripherals
PCLK
LSE
HSI16
SYSCLK
to USART1
LPUART1
LPUART2
USART2
LPUART3(1)
PCLK
HSI16
SYSCLK
HSI48
HSI48 RC
48 MHz
to Cortex system timer
PCLK
SYSCLK
HSE
Clock
detector
HCLK8
APB
PRESC
/ 1,2,4,8,16
LSI
HSE
FCLK Cortex free-running clock
HCLK
/8
HSISYS
VCO
from RTC
to RTC
LSE
LSE
OSC32_OUT
RTCCLK
PCLK
LSI
LSE
HSI16
HSE
HSI16
MSI
LPTIMx_IN
to TIM2/3/6/7/16
TIMPCLK
TIMPCLK
/N
to I2C1
I2C3
To
LPTIM1/2/3(1)
to TIM1
TIM15
PLLQCLK
/ R fPLLR
PLLRCLK
fPLLQ
PLLQCLK
fPLLP
PLLPCLK
/Q
/P
SYSCLK
HSI16
PLLPCLK
MSI RC
100 kHz - 48 MHz
HSI48
MSI
PLLQCLK
BOLD: clock origin
async clock to ADC
to USB(1)/RNG
MSv71415V2
1. Only applies to STM32U073xx and STM32U083xx devices.
RM0503 Rev 2
157/1325
213
Reset and clock control (RCC)
5.2.1
RM0503
HSE clock
The high speed external clock signal (HSE) can be generated from two possible clock
sources:
•
HSE external crystal/ceramic resonator
•
HSE user external clock
The resonator and the load capacitors have to be placed as close as possible to the
oscillator pins in order to minimize output distortion and startup stabilization time. The
loading capacitance values must be adjusted according to the selected oscillator.
Figure 12. HSE/ LSE clock sources
Clock source
Hardware configuration
OSC_IN
OSC_OUT
External clock
External
source
GPIO
(OSC_EN as AF)
OSC_IN OSC_OUT
Crystal/Ceramic
resonators
CL1
158/1325
RM0503 Rev 2
Load
capacitors
CL2
RM0503
Reset and clock control (RCC)
External crystal/ceramic resonator (HSE crystal)
The 4 to 48 MHz external oscillator has the advantage of producing a very accurate rate on
the main clock.
The associated hardware configuration is shown in Figure 12. Refer to the electrical
characteristics section of the datasheet for more details.
The HSERDY flag in the Clock control register (RCC_CR) indicates if the HSE oscillator is
stable or not. At startup, the clock is not released until this bit is set by hardware. An
interrupt can be generated if enabled in the Clock interrupt enable register (RCC_CIER).
The HSE Crystal can be switched on and off using the HSEON bit in the Clock control
register (RCC_CR).
External source (HSE bypass)
In this mode, an external clock source must be provided. It can have a frequency of up to
48 MHz. This mode is selected by setting the HSEBYP and HSEON bits in the Clock control
register (RCC_CR). The external clock signal (square, sinus or triangle) with ~40-60 % duty
cycle depending on the frequency (refer to the datasheet) must drive the OSC_IN pin (see
Figure 12).
The OSC_OUT pin can be used as a GPIO or it can be configured as OSC_EN alternate
function, to provide an enable signal to external clock synthesizer. It allows stopping the
external clock source when the device enters low-power modes, as the OSC_EN output is
high in Run mode and low when the device is in low-power mode
Note:
For details on pin availability, refer to the pinout section in the corresponding device
datasheet.
To minimize the consumption, it is recommended to use the square signal.
5.2.2
HSI16 clock
The HSI16 clock signal is generated from an internal 16 MHz RC oscillator.
The HSI16 RC oscillator has the advantage of providing a clock source at low cost (no
external components). It also has a faster startup time than the HSE crystal oscillator.
However, even after calibration, it is less accurate than an oscillator using a frequency
reference such as quartz crystal or ceramic resonator.
The HSISYS clock derived from HSI16 can be selected as system clock after wake-up from
Stop modes (Stop 0 or Stop 1). Refer to Section 5.3: Low-power modes. It can also be used
as a backup clock source (auxiliary clock) if the HSE crystal oscillator fails. Refer to
Section 5.2.10: Clock security system (CSS).
Calibration
RC oscillator frequencies can vary from one chip to another due to manufacturing process
variations. To compensate for this variation, each device is factory calibrated to 1 %
accuracy at TA=25°C.
After reset, the factory calibration value is loaded in the HSICAL[7:0] bits in the Internal
clock sources calibration register (RCC_ICSCR).
Voltage or temperature variations in the application may affect the HSI16 frequency of the
RC oscillator. It can be trimmed using the HSITRIM[6:0] bits in the Internal clock sources
calibration register (RCC_ICSCR).
RM0503 Rev 2
159/1325
213
Reset and clock control (RCC)
RM0503
For more details on how to measure the HSI16 frequency variation, refer to Section 5.2.17:
Internal/external clock measurement with TIM16.
The HSIRDY flag in the Clock control register (RCC_CR) indicates if the HSI16 RC is stable
or not. At startup, the HSI16 RC output clock is not released until this bit is set by hardware.
The HSI16 RC can be switched on and off using the HSION bit in the Clock control register
(RCC_CR).
The HSI16 signal can also be used as a backup source (auxiliary clock) if the HSE crystal
oscillator fails. Refer to Section 5.2.10: Clock security system (CSS) on page 163.
5.2.3
HSI48 clock
The HSI48 clock signal is generated from an internal 48 MHz RC oscillator. It can be used
as clock source for the USB and RNG peripherals.
The internal 48MHz RC oscillator provides a high-precision clock to the USB peripheral
thanks to the clock recovery system (CRS). CRS uses the USB SOF signal, LSE clock or an
external signal as timing reference to precisely adjust the HSI48 RC oscillator frequency.
HSI48 RC oscillator is disabled as soon as the system enters in Stop or Standby mode.
When the CRS is not used, the HSI48 RC oscillator runs on its free-run frequency which is
subject to manufacturing process variations. The devices are factory-calibrated for ~3 %
accuracy at TA = 25°C.
Refer to CRS section for more details on how to configure and use CRS.
The HSI48RDY flag in the RCC_CR register indicates if HSI48 is stable or not. At startup,
the HSI48 clock is not released until this flag is set by hardware.
The HSI48 RC oscillator is enabled/disabled through the HSI48ON bit of the RCC_CR
register. It is automatically enabled (by hardware setting the HSI48ON bit) when selected as
clock source for the USB peripheral, as long as the USB peripheral is enabled.
Furthermore, it is possible to output the HSI48 clock through the MCO and MCO2
multiplexers and use it as a clock source for other application components.
5.2.4
MSI clock
The MSI clock signal is generated from an internal RC oscillator. Its frequency range can be
adjusted by software by using the MSIRANGE[3:0] bits in the Clock control register
(RCC_CR). Twelve frequency ranges are available: 100 kHz, 200 kHz, 400 kHz, 800 kHz,
1 MHz, 2 MHz, 4 MHz (default value), 8 MHz, 16 MHz, 24 MHz, 32 MHz and 48 MHz.
The MSI clock is used as system clock after restart from Reset, wake-up from Standby and
Shutdown low-power modes. After restart from Reset, the MSI frequency is set to its default
value 4 MHz. Refer to Section 5.3: Low-power modes.
The MSI clock can be selected as system clock after a wake-up from Stop mode (Stop 0,
Stop 1 or Stop 2). Refer to Section 5.3: Low-power modes. It can also be used as a backup
clock source (auxiliary clock) if the HSE crystal oscillator fails. Refer to Section 5.2.10: Clock
security system (CSS).
The MSI RC oscillator has the advantage of providing a low-cost (no external components)
low-power clock source. In addition, when used in PLL-mode with the LSE, it provides a
very accurate clock source which can be used by the USB FS device, and feed the main
PLL to run the system at the maximum speed 80 MHz.
160/1325
RM0503 Rev 2
RM0503
Reset and clock control (RCC)
The MSIRDY flag in the Clock control register (RCC_CR) indicates wether the MSI RC is
stable or not. At startup, the MSI RC output clock is not released until this bit is set by
hardware. The MSI RC can be switched on and off by using the MSION bit in the Clock
control register (RCC_CR).
Hardware auto calibration with LSE (PLL-mode)
When a 32.768 kHz external oscillator is present in the application, it is possible to configure
the MSI in a PLL-mode by setting the MSIPLLEN bit in the Clock control register (RCC_CR).
When configured in PLL-mode, the MSI automatically calibrates itself thanks to the LSE.
This mode is available for all MSI frequency ranges. At 48 MHz, the MSI in PLL-mode can
be used for the USB FS device, saving the need of an external high-speed crystal.
Software calibration
The MSI RC oscillator frequency can vary from one chip to another due to manufacturing
process variations, this is why each device is factory calibrated by ST for 1 % accuracy at an
ambient temperature, TA, of 25 °C. After reset, the factory calibration value is loaded in the
MSICAL[7:0] bits in the Internal clock sources calibration register (RCC_ICSCR). If the
application is subject to voltage or temperature variations, this may affect the RC oscillator
speed. You can trim the MSI frequency in the application by using the MSITRIM[7:0] bits in
the RCC_ICSCR register. For more details on how to measure the MSI frequency variation
please refer to Section 5.2.17: Internal/external clock measurement with TIM16.
Note:
Hardware auto calibration with LSE must not be used in conjunction with software
calibration.
5.2.5
PLL
The internal PLL multiplies the frequency of HSI16- or HSE-based clock fetched on its input,
to produce three independent clock outputs. The allowed input frequency range is from 2.66
to 16 MHz. The dedicated divider PLLM with division factor programmable from one to eight
allows setting a frequency within the valid PLL input range. Refer to Figure 11: Clock tree
and PLL configuration register (RCC_PLLCFGR).
The PLL configuration (selection of the input clock and multiplication factor) must be done
before enabling the PLL. Once the PLL is enabled, these parameters cannot be changed.
To modify the PLL configuration, proceed as follows:
1.
Disable the PLL by setting PLLON to 0 in Clock control register (RCC_CR).
2.
Wait until PLLRDY is cleared. The PLL is now fully stopped.
3.
Change the desired parameter.
4.
Enable the PLL again by setting PLLON to 1.
5.
Enable the desired PLL outputs by configuring PLLPEN, PLLQEN, and PLLREN in PLL
configuration register (RCC_PLLCFGR).
An interrupt can be generated when the PLL is ready, if enabled in the Clock interrupt
enable register (RCC_CIER).
The enable bit of each PLL output clock (PLLPEN, PLLQEN, and PLLREN) can be modified
at any time without stopping the PLL. PLLREN cannot be cleared if PLLRCLK is used as
system clock.
RM0503 Rev 2
161/1325
213
Reset and clock control (RCC)
RM0503
OSC32_OUT can be configured as OSC32_EN alternate function to control the external
clock source. The OSC32_EN output is high in Run mode and low when the device is in
low-power mode.
5.2.6
LSE clock
The LSE crystal is a 32.768 kHz crystal or ceramic resonator. It has the advantage of
providing a low-power but highly accurate clock source to the real-time clock peripheral
(RTC) for clock/calendar or other timing functions.
The LSE crystal is switched on and off using the LSEON bit in RTC domain control register
(RCC_BDCR). The crystal oscillator driving strength can be changed at runtime using the
LSEDRV[1:0] bits in the RTC domain control register (RCC_BDCR) to obtain the best
compromise between robustness and short start-up time on one side and low-powerconsumption on the other side. The LSE drive can be decreased to the lower drive
capability (LSEDRV=00) when the LSE is ON. However, once LSEDRV is selected, the
drive capability can not be increased if LSEON=1.
The LSERDY flag in the RTC domain control register (RCC_BDCR) indicates whether the
LSE crystal is stable or not. At startup, the LSE crystal output clock signal is not released
until this bit is set by hardware. An interrupt can be generated if enabled in the Clock
interrupt enable register (RCC_CIER).
External source (LSE bypass)
In this mode, an external clock source must be provided. It can have a frequency of up to
1 MHz. This mode is selected by setting the LSEBYP and LSEON bits in the AHB peripheral
clock enable in Sleep/Stop mode register (RCC_AHBSMENR). The external clock signal
(square, sinus or triangle) with ~50 % duty cycle has to drive the OSC32_IN pin while the
OSC32_OUT pin can be used as GPIO. See Figure 12.
5.2.7
LSI clock
The LSI RC acts as a low-power clock source that can be kept running in Stop and Standby
mode for the independent watchdog (IWDG) and RTC. The clock frequency is 32 kHz. For
more details, refer to the electrical characteristics section of the datasheets.
The LSI RC can be switched on and off using the LSION bit in the Control/status register
(RCC_CSR).
The LSIRDY flag in the Control/status register (RCC_CSR) indicates if the LSI oscillator is
stable or not. At startup, the clock is not released until this bit is set by hardware. An
interrupt can be generated if enabled in the Clock interrupt enable register (RCC_CIER).
5.2.8
System clock (SYSCLK) selection
One of the following clocks can be selected as system clock (SYSCLK):
162/1325
•
LSI
•
LSE
•
MSI
•
HSISYS
•
HSE
•
PLLRCLK
RM0503 Rev 2
RM0503
Reset and clock control (RCC)
The system clock maximum frequency is 56 MHz. Upon system reset, the HSISYS clock
derived from HSI16 oscillator is selected as system clock. When a clock source is used
directly or through the PLL as a system clock, it is not possible to stop it.
A switch from one clock source to another occurs only if the target clock source is ready
(clock stable after startup delay or PLL locked). If a clock source which is not yet ready is
selected, the switch occurs when the clock source becomes ready. Status bits in the Internal
clock sources calibration register (RCC_ICSCR) indicate which clock(s) is (are) ready and
which clock is currently used as a system clock.
5.2.9
Clock source frequency versus voltage scaling
The following table gives the different clock source frequencies depending on the product
voltage range.
Table 32. Clock source frequency
Maximum clock frequency (MHz)
Clock
Range 1
Range 2
HSI16
16
16
HSE
48
19
HSI48
48
N/A
MSI
48
16
PLLPCLK
122(1)
40(2)
PLLQCLK
56(1)
19(2)
PLLRCLK
56(1)
19(2)
SYSCLK
56(1)
19(2)
HCLK
56(1)
19(2)
PCLK
56(1)
19(2)
1. Maximum VCO frequency is 344 MHz.
2. Maximum VCO frequency is 128 MHz.
5.2.10
Clock security system (CSS)
Clock security system can be activated by software. In this case, the clock detector is
enabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped.
If a failure is detected on the HSE clock:
•
the HSE oscillator is automatically disabled
•
a clock failure event is sent to the break input of TIM1, TIM15, TIM16 and TIM17 timers
•
CSSI (clock security system interrupt) is generated
The CSSI is linked to the Cortex®-M0+ NMI (non-maskable interrupt) exception vector. It
makes the software aware of a HSE clock failure to allow it to perform rescue operations.
Note:
If the CSS is enabled and the HSE clock fails, the CSSI occurs and an NMI is automatically
generated. The NMI is executed infinitely unless the CSS interrupt pending bit is cleared. It
RM0503 Rev 2
163/1325
213
Reset and clock control (RCC)
RM0503
is therefore necessary that the NMI ISR clears the CSSI by setting the CSSC bit in the Clock
interrupt clear register (RCC_CICR).
If HSE is selected directly or indirectly (PLLRCLK selected for SYSCLK and HSE selected
as PLL input) as system clock, and a failure of HSE clock is detected, the system clock
switches automatically to HSISYS and the HSE oscillator is disabled. If the HSE clock
(divided or not) is the clock entry of the PLL and PLLRCLK is used as system clock when
the failure occurs, the PLL is disabled, too.
5.2.11
Clock security system for LSE clock (LSECSS)
A clock security system on LSE can be activated by setting the LSECSSON bit in RTC
domain control register (RCC_BDCR). This bit can be cleared only by a hardware reset or
RTC software reset, or after LSE clock failure detection. LSECSSON must be written after
LSE and LSI are enabled (LSEON and LSION enabled) and ready (LSERDY and LSIRDY
flags set by hardware), and after selecting the RTC clock by RTCSEL.
The LSECSS works in all modes except VBAT. It keeps working also under system reset
(excluding power-on reset). If a failure is detected on the LSE oscillator, the LSE clock is no
longer supplied to the RTC but its registers are not impacted.
Note:
If the LSECSS is enabled and the LSE clock fails, the LSECSSI occurs and an NMI is
automatically generated. The NMI is executed infinitely unless the LSECSS interrupt
pending bit is cleared. It is therefore necessary that the NMI ISR clears the LSECSSI by
setting the LSECSSC bit in the Clock interrupt clear register (RCC_CICR).
If LSE is used as system clock, and a failure of LSE clock is detected, the system clock
switches automatically to LSI. In low-power modes, an LSE clock failure generates a wakeup. The interrupt flag must then be cleared within the RCC registers.
The software must then disable the LSECSSON bit, stop the defective 32 kHz oscillator (by
clearing LSEON), and change the RTC clock source (no clock, LSI or HSE, with RTCSEL),
or take any appropriate action to secure the application.
The frequency of the LSE oscillator must exceed 30 kHz to avoid false positive detections.
5.2.12
ADC clock
The ADC clock is derived from the system clock, or from the PLLPCLK output. It can reach
122 MHz and can be divided by the following prescalers values:
1,2,4,6,8,10,12,16,32,64,128 or 256 by configuring the ADC1_CCR register. It is
asynchronous to the AHB clock. Alternatively, the ADC clock can be derived from the AHB
clock of the ADC bus interface, divided by a programmable factor (1, 2 or 4). This
programmable factor is configured using the CKMODE bitfields in the ADC1_CCR.
If the programmed factor is 1, the AHB prescaler must be set to 1.
5.2.13
RTC clock
The RTCCLK clock source can be either the HSE/32, LSE or LSI clock. It is selected by
programming the RTCSEL[1:0] bits in the RTC domain control register (RCC_BDCR). This
selection cannot be modified without resetting the RTC domain. The system must always be
configured so as to get a PCLK frequency greater then or equal to the RTCCLK frequency
for a proper operation of the RTC.
164/1325
RM0503 Rev 2
RM0503
Reset and clock control (RCC)
The LSE clock is in the RTC domain, whereas the HSE and LSI clocks are not.
Consequently:
•
If LSE is selected as RTC clock:
–
•
If LSI is selected as the RTC clock:
–
•
The RTC continues to work even if the VDD supply is switched off, provided the
VBAT supply is maintained.
The RTC state is not guaranteed if the VDD supply is powered off.
If the HSE clock divided by a prescaler is used as the RTC clock:
–
The RTC state is not guaranteed if the VDD supply is powered off or if the internal
voltage regulator is powered off (removing power from the VCORE domain).
When the RTC clock is LSE or LSI, the RTC remains clocked and functional under system
reset.
5.2.14
Timer clock
The timer clock TIMPCLK is equal to the PCLK frequency.
For TIM1 and TIM15, PLLQCLK clock can also be selected, if:
5.2.15
•
PCLK is derived from PLLRCLK, and
•
PLLQCLK frequency is an integer multiplication by 2 or more of the PCLK frequency,
without exceeding 56 MHz.
Watchdog clock
If the Independent watchdog (IWDG) is started by either hardware option or software
access, the LSI oscillator is forced ON and cannot be disabled. After the LSI oscillator
temporization, the clock is provided to the IWDG.
5.2.16
Clock-out capability
MCO and MCO2
The MCO and MCO2 pins output, independently of each other, the clock selected from:
•
LSI
•
LSE
•
SYSCLK
•
HSI16
•
HSI48
•
HSE
•
MSI
•
PLLRCLK
•
RTCCLK
•
RTC WAKEUP
The multiplexers for MCO and MCO2, respectively, are controlled by the MCOSEL[3:0] and
MCO2SEL[3:0] bitfields of the Clock configuration register (RCC_CFGR). Their outputs are
further divided by a factor set through the MCOPRE[2:0] and MCO2PRE[2:0] bitfields of the
Clock configuration register (RCC_CFGR).
RM0503 Rev 2
165/1325
213
Reset and clock control (RCC)
RM0503
LSCO
The LSCO pin allows outputting on of low-speed clocks:
•
LSI
•
LSE
The selection is controlled by the LSCOSEL bit and enabled with the LSCOEN bit of the
RTC domain control register (RCC_BDCR). The configuration registers of the
corresponding GPIO port must be programmed in alternate function mode.
This function remains available in Stop 0, Stop 1 and Standby modes.
5.2.17
Internal/external clock measurement with TIM16
It is possible to indirectly measure the frequency of all on-board clock sources with the
TIM16 channel 1 input capture, as represented in Figure 13.
TIM16
By setting the TI1SEL[3:0] field of the TIM16_TISEL register, the clock selected for the input
capture channel1 of TIM16 can be one of:
•
GPIO (refer to the alternate function mapping in the device datasheets).
•
LSI clock
•
LSE clock
•
RTC wake-up interrupt signal
The last option requires to enable the RTC interrupt.
Figure 13. Frequency measurement with TIM16 in capture mode
TIM 16
TI1SEL[3:0]
GPIO
LSI
LSE
TI1
RTC wakeup interrupt
MSv42175V1
Calibration of the HSI16 or MSI oscillator
For TIM15, the primary purpose of connecting the LSE to the channel 1 input capture is to
precisely measure HSISYS (derived from HSI16 or MSI) selected as system clock. Counting
HSISYS clock pulses between consecutive edges of the LSE clock (the time reference)
allows measuring the HSISYS (and HSI16 or MSI) clock period. Such measurement can
determine the HSI16 or MSI oscillator frequency with nearly the same accuracy as the
accuracy of the 32.768 kHz quartz crystal used with the LSE oscillator (typically a few tens
of ppm). The HSI16 or MSI oscillators can then be trimmed to compensate for deviations
from target frequency, due to manufacturing, process, temperature and/or voltage variation.
166/1325
RM0503 Rev 2
RM0503
Reset and clock control (RCC)
The HSI16 or MSI oscillators have dedicated user-accessible calibration bits for this
purpose.
The basic concept consists in providing a relative measurement (for example, the
HSISYS/LSE ratio): the measurement accuracy is therefore closely related to the ratio
between the two clock sources. Increasing the ratio allows improving the measurement
accuracy.
Generated by the HSE oscillator, the HSE clock (divided by 32) used as time reference is
the second best method for reaching a good HSI16 or MSI frequency measurement
accuracy. It is recommended in absence of the LSE clock.
In order to further improve the precision of the HSI16 or MSI oscillator calibration, it is
advised to employ one or a combination of the following measures to increase the frequency
measurement accuracy:
•
set the HSISYS divider to 1 for HSISYS frequency to be equal to HSI16 or MSI
frequency
•
average the results of multiple consecutive measurements
•
use the input capture prescaler of the timer (one capture every up to eight periods)
•
use LSE clock for the RTC and the RTC wake-up interrupt signal as time reference
The last point significantly increases the reference period for HSI16 or MSI clock pulse
counting, which improves the accuracy of a single measurement. For operation, the RTC
wake-up interrupt must be enabled.
Calibration of the HSI48 oscillator
The HSI48 oscillator is factory-calibrated.
Measurement of the LSI oscillator frequency
The calibration of the LSI oscillator uses the same principle as that for calibrating the HSI16
or MSI oscillator. TIM16 channel1 input capture must be used for LSI clock, and HSE
selected as system clock source. The number of HSE clock pulses between consecutive
edges of the LSI signal, counted by TIM16, is then representative of the LSI clock period.
5.2.18
Peripheral clock enable registers
The clocks to each peripheral can be enabled individually by the corresponding enable bit of
the RCC_AHBENR register or by one of the RCC_APBENRx registers. The clocks to the
I/O ports can be enabled individually through the RCC_IOPENR register.
When the clock to a peripheral or I/O port is not active, the read and write accesses to the
corresponding registers are not effective.
Caution:
The enable bit has a synchronization mechanism to create a glitch-free clock for the
peripheral or I/O port. After the enable bit is set, there is a 2-clock-cycle delay before the
clock be active, which the software must take into account.
5.3
Low-power modes
•
AHB and APB peripheral clocks, including DMA clock, can be disabled by software.
•
Sleep and Low-power Sleep modes stops the CPU clock. The memory interface clocks
(flash memory and SRAM interfaces) can be stopped by software during sleep mode.
RM0503 Rev 2
167/1325
213
Reset and clock control (RCC)
RM0503
The AHB to APB bridge clocks are disabled by hardware during Sleep mode when all
the clocks of the peripherals connected to them are disabled.
•
Stop modes (Stop 0 and Stop 1) stop all the clocks in the VCORE domain and disable
the PLL as well as the HSI16, HSI48, MSI and HSE oscillators.
The USART1, USART2, LPUART1, LPUART2, LPUSART3, I2C1, and I2C3
peripherals can enable the HSI16 oscillator even when the MCU is in Stop mode (if
HSI16 is selected as clock source for one of those peripherals).
The USART1, USART2, LPUART1, LPUART2, LPUSART3, I2C1, and I2C3
peripherals can also operate with the clock from the LSE oscillator when the system is
in Stop mode, if LSE is selected as clock source for that peripheral and the LSE
oscillator is enabled (LSEON set). In that case, the LSE oscillator remains active when
the device enters Stop mode (these peripherals do not have the capability to turn on
the LSE oscillator).
•
Standby and Shutdown modes stop all clocks in the VCORE domain and disable the
PLL, as well as the HSI16, HSI48, and HSE oscillators.
The CPU deepsleep mode can be overridden for debugging, by setting the DBG_STOP or
DBG_STANDBY bits in the DBG_CR register.
When leaving the Stop 0 or Stop 1 modes, HSISYS becomes automatically the system
clock.
When leaving the Standby and Shutdown modes, HSISYS (with frequency equal to HSI16)
becomes automatically the system clock. At wake-up from Standby and Shutdown mode,
the user trim is lost.
If a flash memory programming operation is ongoing, Stop, Standby, and Shutdown entry is
delayed until the flash memory interface access is finished. If an access to the APB domain
is ongoing, the Stop, Standby, and Shutdown entry is delayed until the APB access is
finished.
168/1325
RM0503 Rev 2
RM0503
Reset and clock control (RCC)
5.4
RCC registers
Unless otherwise specified, the RCC registers support word, half-word, and byte access,
without any wait state.
5.4.1
Clock control register (RCC_CR)
This register supports only word and half-word access.
Address offset: 0x00
Power-on reset value: 0x0000 0083
Other types of reset: same as power-on reset, except HSEBYP bit that keeps its previous
value.
31
Res.
15
Res.
30
Res.
14
Res.
29
Res.
13
Res.
28
Res.
12
Res.
27
26
25
Res.
PLL
RDY
PLLON
r
rw
10
9
8
HSI
ASFS
HSI
RDY
HSI
KER
ON
HSION
r
r
rw
rw
Res.
11
24
23
Res.
7
22
Res.
6
21
Res.
5
20
19
18
17
16
Res.
CSS
ON
HSE
BYP
HSE
RDY
HSE
ON
rs
rw
r
rw
3
2
1
0
MSI
RDY
MSION
r
rw
4
MSI
MSI
RGSEL PLLEN
MSIRANGE[3:0]
rw
rw
rw
rw
rs
rw
Bits 31:26 Reserved, must be kept at reset value.
Bit 25 PLLRDY: PLL clock ready flag
Set by hardware to indicate that the PLL is locked.
0: PLL unlocked
1: PLL locked
Bit 24 PLLON: PLL enable
Set and cleared by software to enable the PLL.
Cleared by hardware when entering Stop, Standby or Shutdown mode. This bit cannot be
reset if the PLL clock is used as the system clock.
0: PLL OFF
1: PLL ON
Bits 23:20 Reserved, must be kept at reset value.
Bit 19 CSSON: Clock security system enable
Set by software to enable the clock security system. When CSSON is set, the clock detector
is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if a HSE
clock failure is detected. This bit is set only and is cleared by reset.
0: Clock security system OFF (clock detector OFF)
1: Clock security system ON (Clock detector ON if the HSE oscillator is stable, OFF if not).
Bit 18 HSEBYP: HSE crystal oscillator bypass
Set and cleared by software to bypass the oscillator with an external clock. The external
clock must be enabled with the HSEON bit set, to be used by the device. The HSEBYP bit
can be written only if the HSE oscillator is disabled.
0: HSE crystal oscillator not bypassed
1: HSE crystal oscillator bypassed with external clock
RM0503 Rev 2
169/1325
213
Reset and clock control (RCC)
RM0503
Bit 17 HSERDY: HSE clock ready flag
Set by hardware to indicate that the HSE oscillator is stable.
0: HSE oscillator not ready
1: HSE oscillator ready
Note: Once the HSEON bit is cleared, HSERDY goes low after 6 HSE clock cycles.
Bit 16 HSEON: HSE clock enable
Set and cleared by software.
Cleared by hardware to stop the HSE oscillator when entering Stop, Standby, or Shutdown
mode. This bit cannot be reset if the HSE oscillator is used directly or indirectly as the system
clock.
0: HSE oscillator OFF
1: HSE oscillator ON
Bits 15:12 Reserved, must be kept at reset value.
Bit 11 HSIASFS: HSI16 automatic start from Stop
Set and cleared by software. When the system wake-up clock is MSI, this bit is used to wake
up the HSI16 is parallel of the system wake-up.
0: HSI16 oscillator is not enabled by hardware when exiting Stop mode with MSI as wake-up
clock.
1: HSI16 oscillator is enabled by hardware when exiting Stop mode with MSI as wake-up
clock.
Bit 10 HSIRDY: HSI16 clock ready flag
Set by hardware to indicate that HSI16 oscillator is stable. This bit is set only when HSI16 is
enabled by software by setting HSION.
0: HSI16 oscillator not ready
1: HSI16 oscillator ready
Note: Once the HSION bit is cleared, HSIRDY goes low after 6 HSI16 clock cycles.
Bit 9 HSIKERON: HSI16 always enable for peripheral kernels.
Set and cleared by software to force HSI16 ON even in Stop modes. The HSI16 can only
feed USART1, USART2, CEC and I2C1 peripherals configured with HSI16 as kernel clock.
Keeping the HSI16 ON in Stop mode allows avoiding to slow down the communication speed
because of the HSI16 startup time. This bit has no effect on HSION value.
0: No effect on HSI16 oscillator.
1: HSI16 oscillator is forced ON even in Stop mode.
Bit 8 HSION: HSI16 clock enable
Set and cleared by software.
Cleared by hardware to stop the HSI16 oscillator when entering Stop, Standby, or Shutdown
mode.
Forced by hardware to keep the HSI16 oscillator ON when it is used directly or indirectly as
system clock (also when leaving Stop, Standby, or Shutdown modes, or in case of failure of
the HSE oscillator used for system clock).
0: HSI16 oscillator OFF
1: HSI16 oscillator ON
170/1325
RM0503 Rev 2
RM0503
Reset and clock control (RCC)
Bits 7:4 MSIRANGE[3:0]: MSI clock ranges
These bits are configured by software to choose the frequency range of MSI when
MSIRGSEL is set.12 frequency ranges are available:
0000: range 0 around 100 kHz
0001: range 1 around 200 kHz
0010: range 2 around 400 kHz
0011: range 3 around 800 kHz
0100: range 4 around 1M Hz
0101: range 5 around 2 MHz
0110: range 6 around 4 MHz (reset value)
0111: range 7 around 8 MHz
1000: range 8 around 16 MHz
1001: range 9 around 24 MHz
1010: range 10 around 32 MHz
1011: range 11 around 48 MHz
others: not allowed (hardware write protection)
Note: Warning: MSIRANGE can be modified when MSI is OFF (MSION=0) or when MSI is
ready (MSIRDY=1). MSIRANGE must NOT be modified when MSI is ON and NOT
ready (MSION=1 and MSIRDY=0)
Bit 3 MSIRGSEL: MSI clock range selection
Set by software to select the MSI clock range with MSIRANGE[3:0]. Write 0 has no effect.
After a standby or a reset MSIRGSEL is at 0 and the MSI range value is provided by
MSISRANGE in CSR register.
0: MSI Range is provided by MSISRANGE[3:0] in RCC_CSR register
1: MSI Range is provided by MSIRANGE[3:0] in the RCC_CR register
Bit 2 MSIPLLEN: MSI clock PLL enable
Set and cleared by software to enable/ disable the PLL part of the MSI clock source.
MSIPLLEN must be enabled after LSE is enabled (LSEON enabled) and ready (LSERDY set
by hardware).There is a hardware protection to avoid enabling MSIPLLEN if LSE is not
ready.
This bit is cleared by hardware when LSE is disabled (LSEON = 0) or when the Clock
Security System on LSE detects a LSE failure (refer to RCC_CSR register).
0: MSI PLL OFF
1: MSI PLL ON
Bit 1 MSIRDY: MSI clock ready flag
This bit is set by hardware to indicate that the MSI oscillator is stable.
0: MSI oscillator not ready
1: MSI oscillator ready
Note: Once the MSION bit is cleared, MSIRDY goes low after 6 MSI clock cycles.
Bit 0 MSION: MSI clock enable
This bit is set and cleared by software.
Cleared by hardware to stop the MSI oscillator when entering Stop, Standby or Shutdown
mode.
Set by hardware to force the MSI oscillator ON when exiting Standby or Shutdown mode.
Set by hardware to force the MSI oscillator ON when STOPWUCK=0 when exiting from Stop
modes, or in case of a failure of the HSE oscillator
Set by hardware when used directly or indirectly as system clock.
0: MSI oscillator OFF
1: MSI oscillator ON
RM0503 Rev 2
171/1325
213
Reset and clock control (RCC)
5.4.2
RM0503
Internal clock sources calibration register (RCC_ICSCR)
Address offset: 0x04
Reset value: 0x40XX 00XX
‘X’ is factory-programmed.
Access: no wait state, word, half-word and byte access
31
30
29
28
Res.
27
26
25
24
23
22
21
HSITRIM[6:0]
20
19
18
17
16
HSICAL[7:0]
rw
rw
rw
rw
rw
rw
rw
r
r
r
r
r
r
r
r
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
r
r
r
r
r
r
MSITRIM[7:0]
rw
rw
MSICAL[7:0]
r
r
Bit 31 Reserved, must be kept at reset value.
Bits 30:24 HSITRIM[6:0]: HSI16 clock trimming
These bits provide an additional user-programmable trimming value that is added to the
HSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature
that influence the frequency of the HSI16.
The default value is 64 when added to the HSICAL value, trim the HSI16 to 16 MHz ± 1 %.
Bits 23:16 HSICAL[7:0]: HSI16 clock calibration
These bits are initialized at startup with the factory-programmed HSI16 calibration trim value.
When HSITRIM is written, HSICAL is updated with the sum of HSITRIM and the factory trim
value.
Bits 15:8 MSITRIM[7:0]: MSI clock trimming
These bits provide an additional user-programmable trimming value that is added to the
MSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature
that influence the frequency of the MSI.
Bits 7:0 MSICAL[7:0]: MSI clock calibration
These bits are initialized at startup with the factory-programmed MSI calibration trim value.
When MSITRIM is written, MSICAL is updated with the sum of MSITRIM and the factory trim
value.
172/1325
RM0503 Rev 2
RM0503
Reset and clock control (RCC)
5.4.3
Clock configuration register (RCC_CFGR)
One or two wait states are inserted if this register is accessed during clock source switch,
and between zero and 15 wait states are inserted if during an update of APB or AHB
prescaler values.
Address offset: 0x08
Reset value: 0x0000 0000
31
30
29
28
27
MCOPRE[3:0]
26
25
24
23
MCOSEL[3:0]
22
21
20
19
MCO2PRE[3:0]
18
17
16
MCO2SEL[3:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
STOP
WUCK
rw
PPRE[2:0]
rw
rw
HPRE[3:0]
rw
rw
rw
rw
rw
SWS[2:0]
r
r
SW[2:0]
r
rw
rw
rw
Bits 31:28 MCOPRE[3:0]: Microcontroller clock output prescaler
This bitfield is controlled by software. It sets the division factor of the clock sent to the MCO
output as follows:
0000: 1
0001: 2
0010: 4
...
0111: 128
1000: 256
1001: 512
1010: 1024
Others: reserved
It is highly recommended to set this field before the MCO output is enabled.
Bits 27:24 MCOSEL[3:0]: Microcontroller clock output clock selector
This bitfield is controlled by software. It sets the clock selector for MCO output as follows:
0000: no clock, MCO output disabled
0001: SYSCLK
0010: MSI
0011: HSI16
0100: HSE
0101: PLLRCLK
0110: LSI
0111: LSE
1000: HSI48
1001: RTCCLK
1010: RTC WAKEUP
Others: Reserved
Note: This clock output may have some truncated cycles at startup or during MCO clock
source switching.
RM0503 Rev 2
173/1325
213
Reset and clock control (RCC)
RM0503
Bits 23:20 MCO2PRE[3:0]: Microcontroller clock output 2 prescaler
This bitfield is controlled by software. It sets the division factor of the clock sent to the MCO2
output as follows:
0000: 1
0001: 2
0010: 4
...
0111: 128
1000: 256
1001: 512
1010: 1024
Others: reserved
It is highly recommended to set this field before the MCO2 output is enabled.
Bits 19:16 MCO2SEL[3:0]: Microcontroller clock output 2 clock selector
This bitfield is controlled by software. It sets the clock selector for MCO2 output as follows:
0000: no clock, MCO2 output disabled
0001: SYSCLK
0010: MSI
0011: HSI16
0100: HSE
0101: PLLRCLK
0110: LSI
0111: LSE
1000: HSI48
1001: RTCCLK
1010: RTC WAKEUP
Others: Reserved
Note: This clock output may have some truncated cycles at startup or during MCO2 clock
source switching.
Bit 15 STOPWUCK: Wake-up from Stop and CSS backup clock selection
Set and cleared by software to select the system clock used when exiting Stop mode.
The selected clock is also used as emergency clock for the Clock Security System on HSE.
Warning: STOPWUCK must not be modified when the Clock Security System is enabled by
HSECSSON in RCC_CR register and the system clock is HSE (SWS=”10”) or a switch on
HSE is requested (SW=”10”).
0: MSI oscillator selected as wake-up from stop clock and CSS backup clock.
1: HSI16 oscillator selected as wake-up from stop clock and CSS backup clock
Bits 14:12 PPRE[2:0]: APB prescaler
This bitfield is controlled by software. To produce PCLK clock, it sets the division factor of
HCLK clock as follows:
0xx: 1
100: 2
101: 4
110: 8
111: 16
174/1325
RM0503 Rev 2
RM0503
Reset and clock control (RCC)
Bits 11:8 HPRE[3:0]: AHB prescaler
This bitfield is controlled by software. To produce HCLK clock, it sets the division factor of
SYSCLK clock as follows:
0xxx: 1
1000: 2
1001: 4
1010: 8
1011: 16
1100: 64
1101: 128
1110: 256
1111: 512
Caution: Depending on the device voltage range, the software has to set correctly these bits to
ensure that the system frequency does not exceed the maximum allowed frequency
(for more details, refer to Section 4.1.6: Dynamic voltage scaling management). After
a write operation to these bits and before decreasing the voltage range, this register
must be read to be sure that the new value has been taken into account.
Bits 7:6 Reserved, must be kept at reset value.
Bits 5:3 SWS[2:0]: System clock switch status
This bitfield is controlled by hardware to indicate the clock source used as system clock:
000: MSI
001: HSI16
010: HSE
011: PLLRCLK
100: LSI
101: LSE
Others: Reserved
Bits 2:0 SW[2:0]: System clock switch
This bitfield is controlled by software and hardware. The bitfield selects the clock for
SYSCLK as follows:
000: MSI
001: HSI16
010: HSE
011: PLLRCLK
100: LSI
101: LSE
Others: Reserved
The setting is forced by hardware to 000 (HSISYS selected) when the MCU exits Stop,
Standby, or Shutdown mode, or when the setting is 001 (HSE selected) and HSE oscillator
failure is detected.
RM0503 Rev 2
175/1325
213
Reset and clock control (RCC)
5.4.4
RM0503
PLL configuration register (RCC_PLLCFGR)
Address offset: 0x0C
Reset value: 0x0000 1000
This register configures the PLL clock outputs according to the formulas:
• fVCO = fPLLIN × (N / M)
• fPLLP = fVCO / P
• fPLLQ = fVCO / Q
• fPLLR = fVCO / R
where fPLLIN is the PLL input clock frequency, fVCO is the PLL VCO frequency, and P, Q and
R are fVCO division factors and fPLLP, fPLLQ and fPLLR the clock frequencies of the PLLPCLK,
PLLQCLK and PLLRCLK PLL clock outputs, respectively.
31
30
29
28
27
PLL
REN
PLLR[2:0]
26
25
24
PLL
QEN
PLLQ[2:0]
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
rw
rw
rw
rw
rw
rw
Res.
PLLN[6:0]
rw
23
22
Res.
Res.
7
6
Res.
21
20
18
17
16
PLL
PEN
PLLP[4:0]
rw
rw
rw
rw
rw
rw
5
4
3
2
1
0
Res.
Res.
PLLM[2:0]
rw
19
rw
rw
PLLSRC[1:0]
rw
rw
Bits 31:29 PLLR[2:0]: PLL VCO division factor R for PLLRCLK clock output
This bitfield is controlled by software. It sets the PLL VCO division factor R as follows:
000: Reserved
001: 2
010: 3
011: 4
100: 5
101: 6
110: 7
111: 8
The bitfield can be written only when the PLL is disabled.
The PLLRCLK clock can be selected as system clock.
Caution: The software must set this bitfield so as not to exceed 54 MHz on this clock.
Bit 28 PLLREN: PLLRCLK clock output enable
This bit is controlled by software to enable/disable the PLLRCLK clock output of the PLL:
0: Disable
1: Enable
This bit cannot be written when PLLRCLK output of the PLL is selected for system clock.
Disabling the PLLRCLK clock output, when not used, allows saving power.
176/1325
RM0503 Rev 2
RM0503
Reset and clock control (RCC)
Bits 27:25 PLLQ[2:0]: PLL VCO division factor Q for PLLQCLK clock output
This bitfield is controlled by software. It sets the PLL VCO division factor Q as follows:
000: Reserved
001: 2
010: 3
011: 4
100: 5
101: 6
110: 7
111: 8
The bitfield can be written only when the PLL is disabled.
Caution: The software must set this bitfield so as not to exceed 54 MHz on this clock.
Bit 24 PLLQEN: PLLQCLK clock output enable
This bit is controlled by software to enable/disable the PLLQCLK clock output of the PLL:
0: Disable
1: Enable
Disabling the PLLQCLK clock output, when not used, allows saving power.
Bits 23:22 Reserved, must be kept at reset value.
Bits 21:17 PLLP[4:0]: PLL VCO division factor P for PLLPCLK clock output
This bitfield is controlled by software. It sets the PLL VCO division factor P as follows:
00000: Reserved
00001: 2
...
11111: 32
The bitfield can be written only when the PLL is disabled.
Caution: The software must set this bitfield so as not to exceed 122 MHz on this clock.
Bit 16 PLLPEN: PLLPCLK clock output enable
This bit is controlled by software to enable/disable the PLLPCLK clock output of the PLL:
0: Disable
1: Enable
Disabling the PLLPCLK clock output, when not used, allows saving power.
Bit 15 Reserved, must be kept at reset value.
Bits 14:8 PLLN[6:0]: PLL frequency multiplication factor N
This bit is controlled by software to set the division factor of the fVCO feedback divider (that
determines the PLL multiplication ratio) as follows:
0000000: Invalid
0000001: Reserved
...
0000011: Reserved
0000100: 4
0000101: 5
...
1111110: 126
1111111: 127
The bitfield can be written only when the PLL is disabled.
Caution: The software must set these bits so that the VCO output frequency is between 96
and 344 MHz.
RM0503 Rev 2
177/1325
213
Reset and clock control (RCC)
RM0503
Bit 7 Reserved, must be kept at reset value.
Bits 6:4 PLLM[2:0]: Division factor M of the PLL input clock divider
This bit is controlled by software to divide the PLL input clock before the actual phase-locked
loop, as follows:
000: 1
001: 2
010: 3
011: 4
100: 5
101: 6
110: 7
111: 8
The bitfield can be written only when the PLL is disabled.
Caution: The software must set these bits so that the PLL input frequency after the /M divider
is between 2.66 and 16 MHz.
Bits 3:2 Reserved, must be kept at reset value.
Bits 1:0 PLLSRC[1:0]: PLL input clock source
This bit is controlled by software to select PLL clock source, as follows:
00: No clock
01: MSI
10: HSI16
11: HSE
The bitfield can be written only when the PLL is disabled.
When the PLL is not used, selecting 00 allows saving power.
5.4.5
Clock interrupt enable register (RCC_CIER)
Address offset: 0x18
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
HSI48
RDYIE
LSE
CSSIE
Res.
PLL
RDYIE
HSE
RDYIE
HSI
RDYIE
MSI
RDYIE
LSE
RDYIE
LSI
RDYIE
rw
rw
rw
rw
rw
rw
rw
rw
Res.
Res.
178/1325
Res.
Res.
Res.
Res.
RM0503 Rev 2
RM0503
Reset and clock control (RCC)
Bits 31:11 Reserved, must be kept at reset value.
Bit 10 HSI48RDYIE: HSI48 ready interrupt enable(1)
Set and cleared by software to enable/disable interrupt caused by the internal HSI48
oscillator.
0: HSI48 ready interrupt disabled
1: HSI48 ready interrupt enabled
Bit 9 LSECSSIE: LSE clock security system interrupt enable
Set and cleared by software to enable/disable interrupt caused by the clock security system
on LSE.
0: Clock security interrupt caused by LSE clock failure disabled
1: Clock security interrupt caused by LSE clock failure enabled
Bits 8:6 Reserved, must be kept at reset value.
Bit 5 PLLRDYIE: PLL ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by PLL lock:
0: Disable
1: Enable
Bit 4 HSERDYIE: HSE ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the HSE oscillator
stabilization:
0: Disable
1: Enable
Bit 3 HSIRDYIE: HSI16 ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the HSI16 oscillator
stabilization:
0: Disable
1: Enable
Bit 2 MSIRDYIE: MSI ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the MSI oscillator
stabilization.
0: MSI ready interrupt disabled
1: MSI ready interrupt enabled
Bit 1 LSERDYIE: LSE ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the LSE oscillator
stabilization:
0: Disable
1: Enable
Bit 0 LSIRDYIE: LSI ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the LSI oscillator
stabilization:
0: Disable
1: Enable
1. Only significant on devices integrating the corresponding peripheral, otherwise reserved. Refer to Section 1.4: Availability
of peripherals.
RM0503 Rev 2
179/1325
213
Reset and clock control (RCC)
5.4.6
RM0503
Clock interrupt flag register (RCC_CIFR)
Address offset: 0x1C
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
HSI48
RDYF
LSE
CSSF
CSSF
Res.
Res.
PLL
RDYF
HSE
RDYF
HSI
RDYF
MSI
RDYF
LSE
RDYF
LSI
RDYF
r
r
r
r
r
r
r
r
r
Bits 31:11 Reserved, must be kept at reset value.
Bit 10 HSI48RDYF: HSI48 ready interrupt flag(1)
Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set in a
response to setting the HSI48ON (refer to RCC clock recovery RC register (RCC_CRRCR)).
Cleared by software setting the HSI48RDYC bit.
0: No clock ready interrupt caused by the HSI48 oscillator
1: Clock ready interrupt caused by the HSI48 oscillator
Bit 9 LSECSSF: LSE clock security system interrupt flag
Set by hardware when a failure is detected in the LSE oscillator.
Cleared by software by setting the LSECSSC bit.
0: No clock security interrupt caused by LSE clock failure
1: Clock security interrupt caused by LSE clock failure
Bit 8 CSSF: HSE clock security system interrupt flag
Set by hardware when a failure is detected in the HSE oscillator.
Cleared by software setting the CSSC bit.
0: No clock security interrupt caused by HSE clock failure
1: Clock security interrupt caused by HSE clock failure
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 PLLRDYF: PLL ready interrupt flag
Set by hardware when the PLL locks and PLLRDYIE is set.
Cleared by software setting the PLLRDYC bit.
0: No clock ready interrupt caused by PLL lock
1: Clock ready interrupt caused by PLL lock
Bit 4 HSERDYF: HSE ready interrupt flag
Set by hardware when the HSE clock becomes stable and HSERDYIE is set.
Cleared by software setting the HSERDYC bit.
0: No clock ready interrupt caused by the HSE oscillator
1: Clock ready interrupt caused by the HSE oscillator
180/1325
RM0503 Rev 2
RM0503
Reset and clock control (RCC)
Bit 3 HSIRDYF: HSI16 ready interrupt flag
Set by hardware when the HSI16 clock becomes stable and HSIRDYIE is set in a response
to setting the HSION (refer to Clock control register (RCC_CR)). When HSION is not set
but the HSI16 oscillator is enabled by the peripheral through a clock request, this bit is not
set and no interrupt is generated.
Cleared by software setting the HSIRDYC bit.
0: No clock ready interrupt caused by the HSI16 oscillator
1: Clock ready interrupt caused by the HSI16 oscillator
Bit 2 MSIRDYF: MSI ready interrupt flag
Set by hardware when the MSI clock becomes stable and MSIRDYDIE is set.
Cleared by software setting the MSIRDYC bit.
0: No clock ready interrupt caused by the MSI oscillator
1: Clock ready interrupt caused by the MSI oscillator
Bit 1 LSERDYF: LSE ready interrupt flag
Set by hardware when the LSE clock becomes stable and LSERDYDIE is set.
Cleared by software setting the LSERDYC bit.
0: No clock ready interrupt caused by the LSE oscillator
1: Clock ready interrupt caused by the LSE oscillator
Bit 0 LSIRDYF: LSI ready interrupt flag
Set by hardware when the LSI clock becomes stable and LSIRDYDIE is set.
Cleared by software setting the LSIRDYC bit.
0: No clock ready interrupt caused by the LSI oscillator
1: Clock ready interrupt caused by the LSI oscillator
1. Only significant on devices integrating the corresponding peripheral, otherwise reserved. Refer to Section 1.4: Availability
of peripherals.
5.4.7
Clock interrupt clear register (RCC_CICR)
Address offset: 0x20
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
HSI48
RDYC
LSE
CSSC
CSSC
Res.
Res.
PLL
RDYC
HSE
RDYC
HSI
RDYC
MSI
RDYC
LSE
RDYC
LSI
RDYC
w
w
w
w
w
w
w
w
w
Bits 31:11 Reserved, must be kept at reset value.
Bit 10 HSI48RDYC: HSI48 oscillator ready interrupt clear(1)
This bit is set by software to clear the HSI48RDYF flag.
0: No effect
1: Clear the HSI48RDYC flag
Bit 9 LSECSSC: LSE Clock security system interrupt clear
This bit is set by software to clear the LSECSSF flag.
0: No effect
1: Clear LSECSSF flag
RM0503 Rev 2
181/1325
213
Reset and clock control (RCC)
RM0503
Bit 8 CSSC: Clock security system interrupt clear
This bit is set by software to clear the HSECSSF flag.
0: No effect
1: Clear CSSF flag
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 PLLRDYC: PLL ready interrupt clear
This bit is set by software to clear the PLLRDYF flag.
0: No effect
1: Clear PLLRDYF flag
Bit 4 HSERDYC: HSE ready interrupt clear
This bit is set by software to clear the HSERDYF flag.
0: No effect
1: Clear HSERDYF flag
Bit 3 HSIRDYC: HSI16 ready interrupt clear
This bit is set software to clear the HSIRDYF flag.
0: No effect
1: Clear HSIRDYF flag
Bit 2 MSIRDYC: MSI ready interrupt clear
This bit is set by software to clear the MSIRDYF flag.
0: No effect
1: MSIRDYF cleared
Bit 1 LSERDYC: LSE ready interrupt clear
This bit is set by software to clear the LSERDYF flag.
0: No effect
1: Clear LSERDYF flag
Bit 0 LSIRDYC: LSI ready interrupt clear
This bit is set by software to clear the LSIRDYF flag.
0: No effect
1: Clear LSIRDYF flag
1. Only significant on devices integrating the corresponding peripheral, otherwise reserved. Refer to Section 1.4: Availability
of peripherals.
5.4.8
AHB peripheral reset register (RCC_AHBRSTR)
Address offset: 0x28
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
TSC
RST
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
Res.
CRC
RST
Res.
FLASH
RST
23
22
21
20
19
18
RNG
RST
Res.
Res.
Res.
Res.
Res.
7
6
5
4
3
rw
Res.
Res.
rw
182/1325
Res.
Res.
17
16
Res.
AES
RST
rw
Res.
rw
RM0503 Rev 2
Res.
Res.
Res.
Res.
rw
2
1
0
Res.
DMA2
RST
DMA1
RST
rw
rw
RM0503
Reset and clock control (RCC)
Bits 31:25 Reserved, must be kept at reset value.
Bit 24 TSCRST: Touch sensing controller reset
Set and cleared by software.
0: No effect
1: Reset TSC
Bits 23:19 Reserved, must be kept at reset value.
Bit 18 RNGRST: Random number generator reset
Set and cleared by software.
0: No effect
1: Reset RNG
Bit 17 Reserved, must be kept at reset value.
Bit 16 AESRST: AES hardware accelerator reset(1)
Set and cleared by software.
0: No effect
1: Reset AES
Bits 15:13 Reserved, must be kept at reset value.
Bit 12 CRCRST: CRC reset
Set and cleared by software.
0: No effect
1: Reset CRC
Bits 11:9 Reserved, must be kept at reset value.
Bit 8 FLASHRST: Flash memory interface reset
Set and cleared by software.
0: No effect
1: Reset flash memory interface
This bit can only be set when the flash memory is in power down mode.
Bits 7:2 Reserved, must be kept at reset value.
Bit 1 DMA2RST: DMA2 and DMAMUX reset
Set and cleared by software.
0: No effect
1: Reset DMA2 and DMAMUX
Bit 0 DMA1RST: DMA1 and DMAMUX reset
Set and cleared by software.
0: No effect
1: Reset DMA1 and DMAMUX
1. Only significant on devices integrating the corresponding peripheral, otherwise reserved. Refer to Section 1.4: Availability
of peripherals.
RM0503 Rev 2
183/1325
213
Reset and clock control (RCC)
5.4.9
RM0503
I/O port reset register (RCC_IOPRSTR)
Address offset: 0x2C
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA
RST
RST
RST
RST
RST
RST
rw
Bits 31:6 Reserved, must be kept at reset value.
Bit 5 GPIOFRST: I/O port F reset
This bit is set and cleared by software.
0: no effect
1: Reset I/O port F
Bit 4 GPIOERST: I/O port E reset
This bit is set and cleared by software.
0: no effect
1: Reset I/O port E
Bit 3 GPIODRST: I/O port D reset
This bit is set and cleared by software.
0: no effect
1: Reset I/O port D
Bit 2 GPIOCRST: I/O port C reset
This bit is set and cleared by software.
0: no effect
1: Reset I/O port C
Bit 1 GPIOBRST: I/O port B reset
This bit is set and cleared by software.
0: no effect
1: Reset I/O port B
Bit 0 GPIOARST: I/O port A reset
This bit is set and cleared by software.
0: no effect
1: Reset I/O port A
184/1325
RM0503 Rev 2
rw
rw
rw
rw
rw
RM0503
Reset and clock control (RCC)
5.4.10
APB peripheral reset register 1 (RCC_APBRSTR1)
Address offset: 0x38
Reset value: 0x0000 0000
31
30
LPTIM1 LPTIM2
RST
RST
29
DAC1
RST
28
PWR
RST
27
26
25
24
23
22
21
Res.
LPTIM3
RST
I2C4
RST
OPAMP
RST
I2C3
RST
I2C2
RST
I2C1
RST
20
19
18
17
16
LP
USART USART USART
UART1
4
3
2
RST
RST
RST
RST
CRS
RST
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SPI3
RST
SPI2
RST
USB
RST
LP
UART3
RST
Res.
Res.
LCD
RST
Res.
LP
UART2
RST
Res.
TIM7
RST
TIM6
RST
Res.
Res.
TIM3
RST
TIM2
RST
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bit 31 LPTIM1RST: Low-power timer 1 reset
Set and cleared by software.
0: No effect
1: Reset LPTIM1
Bit 30 LPTIM2RST: Low-power timer 2 reset
Set and cleared by software.
0: No effect
1: Reset LPTIM2
Bit 29 DAC1RST: DAC1 interface reset
Set and cleared by software.
0: No effect
1: Reset DAC1 interface
Bit 28 PWRRST: Power interface reset
Set and cleared by software.
0: No effect
1: Reset PWR
Bit 27 Reserved, must be kept at reset value.
Bit 26 LPTIM3RST: LPTIM3 reset(1)
Set and cleared by software.
0: No effect
1: Reset LPTIM3
Bit 25 I2C4RST: I2C4 reset(1)
Set and cleared by software.
0: No effect
1: Reset I2C4
Bit 24 OPAMPRST: OPAMP reset
Set and cleared by software.
0: No effect
1: Reset the OPAMP
RM0503 Rev 2
185/1325
213
Reset and clock control (RCC)
RM0503
Bit 23 I2C3RST: I2C3 reset
Set and cleared by software.
0: No effect
1: Reset I2C3
Bit 22 I2C2RST: I2C2 reset
Set and cleared by software.
0: No effect
1: Reset I2C2
Bit 21 I2C1RST: I2C1 reset
Set and cleared by software.
0: No effect
1: Reset I2C1
Bit 20 LPUART1RST: LPUART1 reset
Set and cleared by software.
0: No effect
1: Reset LPUART1
Bit 19 USART4RST: USART4 reset
Set and cleared by software.
0: No effect
1: Reset USART4
Bit 18 USART3RST: USART3 reset
Set and cleared by software.
0: No effect
1: Reset USART3
Bit 17 USART2RST: USART2 reset
Set and cleared by software.
0: No effect
1: Reset USART2
Bit 16 CRSRST: CRS reset(1)
Set and cleared by software.
0: No effect
1: Reset CRS
Bit 15 SPI3RST: SPI3 reset(1)
Set and cleared by software.
0: No effect
1: Reset SPI3
Bit 14 SPI2RST: SPI2 reset
Set and cleared by software.
0: No effect
1: Reset SPI2
Bit 13 USBRST: USB reset(1)
Set and cleared by software.
0: No effect
1: Reset USB
186/1325
RM0503 Rev 2
RM0503
Reset and clock control (RCC)
Bit 12 LPUART3RST: LPUART3 reset(1)
Set and cleared by software.
0: No effect
1: Reset LPUART3
Bits 11:10 Reserved, must be kept at reset value.
Bit 9 LCDRST: LCD reset(1)
Set and cleared by software.
0: No effect
1: Reset LCD
Bit 8 Reserved, must be kept at reset value.
Bit 7 LPUART2RST: LPUART2 reset
Set and cleared by software.
0: No effect
1: Reset LPUART2
Bit 6 Reserved, must be kept at reset value.
Bit 5 TIM7RST: TIM7 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM7
Bit 4 TIM6RST: TIM6 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM6
Bits 3:2 Reserved, must be kept at reset value.
Bit 1 TIM3RST: TIM3 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM3
Bit 0 TIM2RST: TIM2 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM2
1. Only significant on devices integrating the corresponding peripheral, otherwise reserved. Refer to Section 1.4: Availability
of peripherals.
RM0503 Rev 2
187/1325
213
Reset and clock control (RCC)
5.4.11
RM0503
APB peripheral reset register 2 (RCC_APBRSTR2)
Address offset: 0x40
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
ADC
RST
19
18
17
16
Res.
Res.
TIM16
RST
TIM15
RST
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
USART
1
RST
Res.
SPI1
RST
TIM1
RST
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
SYS
CFG
RST
rw
rw
rw
rw
rw
Bits 31:21 Reserved, must be kept at reset value.
Bit 20 ADCRST: ADC reset
Set and cleared by software.
0: No effect
1: Reset ADC
Bits 19:18 Reserved, must be kept at reset value.
Bit 17 TIM16RST: TIM16 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM16 timer
Bit 16 TIM15RST: TIM15 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM15 timer
Bit 15 Reserved, must be kept at reset value.
Bit 14 USART1RST: USART1 reset
Set and cleared by software.
0: No effect
1: Reset USART1
Bit 13 Reserved, must be kept at reset value.
Bit 12 SPI1RST: SPI1 reset
Set and cleared by software.
0: No effect
1: Reset SPI1
188/1325
RM0503 Rev 2
RM0503
Reset and clock control (RCC)
Bit 11 TIM1RST: TIM1 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM1 timer
Bits 10:1 Reserved, must be kept at reset value.
Bit 0 SYSCFGRST: SYSCFG, COMP and VREFBUF reset
Set and cleared by software.
0: No effect
1: Reset SYSCFG + COMP + VREFBUF
5.4.12
AHB peripheral clock enable register (RCC_AHBENR)
Address offset: 0x48
Reset value: 0x0000 0100
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
TSC
EN
Res.
Res.
Res.
Res.
Res.
RNG
EN
Res.
AES
EN
15
14
13
12
11
10
9
8
7
6
5
4
3
Res.
CRC
EN
Res.
FLASH
EN
rw
Res.
Res.
Res.
Res.
rw
rw
Res.
Res.
rw
Res.
Res.
Res.
rw
2
1
0
Res.
DMA2
EN
DMA1
EN
rw
rw
Bits 31:25 Reserved, must be kept at reset value.
Bit 24 TSCEN: Touch sensing controller clock enable
Set and cleared by software.
0: TSC clock disable
1: TSC clock enable
Bits 23:19 Reserved, must be kept at reset value.
Bit 18 RNGEN: Random number generator clock enable
Set and cleared by software.
0: Disable
1: Enable
Bit 17 Reserved, must be kept at reset value.
Bit 16 AESEN: AES hardware accelerator(1)
Set and cleared by software.
0: Disable
1: Enable
Bits 15:13 Reserved, must be kept at reset value.
Bit 12 CRCEN: CRC clock enable
Set and cleared by software.
0: Disable
1: Enable
Bits 11:9 Reserved, must be kept at reset value.
RM0503 Rev 2
189/1325
213
Reset and clock control (RCC)
RM0503
Bit 8 FLASHEN: Flash memory interface clock enable
Set and cleared by software.
0: Disable
1: Enable
This bit can only be cleared when the flash memory is in power down mode.
Bits 7:2 Reserved, must be kept at reset value.
Bit 1 DMA2EN: DMA2 and DMAMUX clock enable
Set and cleared by software.
0: Disable
1: Enable
DMAMUX is enabled as long as at least one DMA peripheral is enabled.
Bit 0 DMA1EN: DMA1 and DMAMUX clock enable
Set and cleared by software.
0: Disable
1: Enable
DMAMUX is enabled as long as at least one DMA peripheral is enabled.
1. Only significant on devices integrating the corresponding peripheral, otherwise reserved. Refer to Section 1.4: Availability
of peripherals.
5.4.13
I/O port clock enable register (RCC_IOPENR)
Address offset: 0x4C
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA
EN
EN
EN
EN
EN
EN
rw
Bits 31:6 Reserved, must be kept at reset value.
Bit 5 GPIOFEN: I/O port F clock enable
This bit is set and cleared by software.
0: Disable
1: Enable
Bit 4 GPIOEEN: I/O port E clock enable(1)
This bit is set and cleared by software.
0: Disable
1: Enable
Bit 3 GPIODEN: I/O port D clock enable(1)
This bit is set and cleared by software.
0: Disable
1: Enable
190/1325
RM0503 Rev 2
rw
rw
rw
rw
rw
RM0503
Reset and clock control (RCC)
Bit 2 GPIOCEN: I/O port C clock enable
This bit is set and cleared by software.
0: Disable
1: Enable
Bit 1 GPIOBEN: I/O port B clock enable
This bit is set and cleared by software.
0: Disable
1: Enable
Bit 0 GPIOAEN: I/O port A clock enable
This bit is set and cleared by software.
0: Disable
1: Enable
1. Only significant on devices integrating the corresponding peripheral, otherwise reserved. Refer to Section 1.4: Availability of
peripherals.
5.4.14
Debug configuration register (RCC_DBGCFGR)
Address offset: 0x50
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
DBG
RST
DBG
EN
rw
rw
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 DBGRST: Debug support reset
Set and cleared by software.
0: No effect
1: Reset DBG
Bit 0 DBGEN: Debug support clock enable
Set and cleared by software.
0: Disable
1: Enable
RM0503 Rev 2
191/1325
213
Reset and clock control (RCC)
5.4.15
RM0503
APB peripheral clock enable register 1 (RCC_APBENR1)
Address offset: 0x58
Reset value: 0x0000 0000
31
30
LPTIM1 LPTIM2
EN
EN
29
DAC1
EN
28
PWR
EN
rw
rw
rw
rw
15
14
13
12
SPI3
EN
SPI2
EN
USB
EN
rw
rw
rw
27
25
24
23
21
20
19
18
17
LP
USART USART USART
UART1
4
3
2
EN
EN
EN
EN
16
LPTIM3
EN
I2C4
EN
OPAMP
EN
I2C3
EN
I2C2
EN
I2C1
EN
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
11
10
9
8
7
6
5
4
3
2
1
0
RTC
APB
EN
LCD
EN
Res.
LP
UART2
EN
Res.
TIM7
EN
TIM6
EN
Res.
Res.
TIM3
EN
TIM2
EN
rw
rw
rw
rw
rw
rw
rw
rw
Bit 31 LPTIM1EN: LPTIM1 clock enable
Set and cleared by software.
0: Disable
1: Enable
Bit 30 LPTIM2EN: LPTIM2 clock enable
Set and cleared by software.
0: Disable
1: Enable
Bit 29 DAC1EN: DAC1 interface clock enable
Set and cleared by software.
0: Disable
1: Enable
Bit 28 PWREN: Power interface clock enable
Set and cleared by software.
0: Disable
1: Enable
Bit 27 Reserved, must be kept at reset value.
Bit 26 LPTIM3EN: LPTIM3 clock enable(1)
Set and cleared by software.
0: Disable
1: Enable
Bit 25 I2C4EN: I2C4EN clock enable(1)
Set and cleared by software.
0: Disable
1: Enable
Bit 24 OPAMPEN: OPAMP clock enable
Set and cleared by software.
0: Disable
1: Enable
192/1325
22
Res.
LP
WWDG
UART3
EN
EN
rw
26
RM0503 Rev 2
CRS
EN
RM0503
Reset and clock control (RCC)
Bit 23 I2C3EN: I2C3 clock enable
Set and cleared by software.
0: Disable
1: Enable
Bit 22 I2C2EN: I2C2 clock enable
Set and cleared by software.
0: Disable
1: Enable
Bit 21 I2C1EN: I2C1 clock enable
Set and cleared by software.
0: Disable
1: Enable
Bit 20 LPUART1EN: LPUART1 clock enable
Set and cleared by software.
0: Disable
1: Enable
Bit 19 USART4EN: USART4 clock enable
Set and cleared by software.
0: Disable
1: Enable
Bit 18 USART3EN: USART3 clock enable
Set and cleared by software.
0: Disable
1: Enable
Bit 17 USART2EN: USART2 clock enable
Set and cleared by software.
0: Disable
1: Enable
Bit 16 CRSEN: CRS clock enable(1)
Set and cleared by software.
0: Disable
1: Enable
Bit 15 SPI3EN: SPI3 clock enable(1)
Set and cleared by software.
0: Disable
1: Enable
Bit 14 SPI2EN: SPI2 clock enable
Set and cleared by software.
0: Disable
1: Enable
Bit 13 USBEN: USB clock enable(1)
Set and cleared by software.
0: Disable
1: Enable
RM0503 Rev 2
193/1325
213
Reset and clock control (RCC)
RM0503
Bit 12 LPUART3EN: LPUART3 clock enable
Set and cleared by software.
0: Disable
1: Enable
Bit 11 WWDGEN: WWDG clock enable
Set by software to enable the window watchdog clock. Cleared by hardware system
reset
0: Disable
1: Enable
This bit can also be set by hardware if the WWDG_SW option bit is 0.
Bit 10 RTCAPBEN: RTC APB clock enable
Set and cleared by software.
0: Disable
1: Enable
Bit 9 LCDEN: LCD clock enable(1)
Set and cleared by software.
0: Disable
1: Enable
Bit 8 Reserved, must be kept at reset value.
Bit 7 LPUART2EN: LPUART2 clock enable
Set and cleared by software.
0: Disable
1: Enable
Bit 6 Reserved, must be kept at reset value.
Bit 5 TIM7EN: TIM7 timer clock enable
Set and cleared by software.
0: Disable
1: Enable
Bit 4 TIM6EN: TIM6 timer clock enable
Set and cleared by software.
0: Disable
1: Enable
Bits 3:2 Reserved, must be kept at reset value.
Bit 1 TIM3EN: TIM3 timer clock enable
Set and cleared by software.
0: Disable
1: Enable
Bit 0 TIM2EN: TIM2 timer clock enable
Set and cleared by software.
0: Disable
1: Enable
1. Only significant on devices integrating the corresponding peripheral, otherwise reserved. Refer to Section 1.4: Availability
of peripherals.
194/1325
RM0503 Rev 2
RM0503
Reset and clock control (RCC)
5.4.16
APB peripheral clock enable register 2(RCC_APBENR2)
Address offset: 0x60
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
ADC
EN
19
18
17
16
Res.
Res.
TIM16
EN
TIM15
EN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
USART
1
EN
Res.
SPI1
EN
TIM1
EN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
SYS
CFG
EN
rw
rw
rw
rw
rw
Bits 31:21 Reserved, must be kept at reset value.
Bit 20 ADCEN: ADC clock enable
Set and cleared by software.
0: Disable
1: Enable
Bits 19:18 Reserved, must be kept at reset value.
Bit 17 TIM16EN: TIM16 timer clock enable
Set and cleared by software.
0: Disable
1: Enable
Bit 16 TIM15EN: TIM15 timer clock enable
Set and cleared by software.
0: Disable
1: Enable
Bit 15 Reserved, must be kept at reset value.
Bit 14 USART1EN: USART1 clock enable
Set and cleared by software.
0: Disable
1: Enable
Bit 13 Reserved, must be kept at reset value.
Bit 12 SPI1EN: SPI1 clock enable
Set and cleared by software.
0: Disable
1: Enable
RM0503 Rev 2
195/1325
213
Reset and clock control (RCC)
RM0503
Bit 11 TIM1EN: TIM1 timer clock enable
Set and cleared by software.
0: Disable
1: Enable
Bits 10:1 Reserved, must be kept at reset value.
Bit 0 SYSCFGEN: SYSCFG, COMP and VREFBUF clock enable
Set and cleared by software.
0: Disable
1: Enable
5.4.17
AHB peripheral clock enable in Sleep/Stop mode register
(RCC_AHBSMENR)
Address offset: 0x68
Reset value: 0x0105 1303
31
Res.
30
Res.
29
Res.
28
Res.
27
Res.
26
Res.
25
24
Res.
TSC
SMEN
23
Res.
22
Res.
21
Res.
20
Res.
19
18
Res.
RNG
SMEN
rw
15
Res.
14
Res.
13
12
Res.
CRC
SMEN
rw
11
Res.
10
9
8
Res.
SRAM
SMEN
FLASH
SMEN
rw
rw
16
Res.
AES
SMEN
rw
7
Res.
6
Res.
5
Res.
4
Res.
3
Res.
Bits 31:25 Reserved, must be kept at reset value.
Bit 24 TSCSMEN: TSC clock enable during Sleep and Stop mode
Set and cleared by software.
0: Disable
1: Enable
Bits 23:19 Reserved, must be kept at reset value.
Bit 18 RNGSMEN: RNG clock enable during Sleep and Stop mode
Set and cleared by software.
0: Disable
1: Enable
Bit 17 Reserved, must be kept at reset value.
Bit 16 AESSMEN: AES hardware accelerator clock enable during Sleep mode(1)
Set and cleared by software.
0: Disable
1: Enable
Bits 15:13 Reserved, must be kept at reset value.
Bit 12 CRCSMEN: CRC clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Bits 11:10 Reserved, must be kept at reset value.
196/1325
17
RM0503 Rev 2
rw
2
1
0
Res.
DMA2
SMEN
DMA1
SMEN
rw
rw
RM0503
Reset and clock control (RCC)
Bit 9 SRAMSMEN: SRAM clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Bit 8 FLASHSMEN: Flash memory interface clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
This bit can be activated only when the flash memory is in power down mode.
Bits 7:2 Reserved, must be kept at reset value.
Bit 1 DMA2SMEN: DMA2 and DMAMUX clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Clock to DMAMUX during Sleep mode is enabled as long as the clock in Sleep mode is
enabled to at least one DMA peripheral.
Bit 0 DMA1SMEN: DMA1 and DMAMUX clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Clock to DMAMUX during Sleep mode is enabled as long as the clock in Sleep mode is
enabled to at least one DMA peripheral.
1. Only significant on devices integrating the corresponding peripheral, otherwise reserved. Refer to Section 1.4: Availability
of peripherals.
5.4.18
I/O port in Sleep mode clock enable register (RCC_IOPSMENR)
Address offset: 0x6C
Reset value: 0x0000 003F
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA
SMEN SMEN SMEN SMEN SMEN SMEN
rw
rw
rw
rw
rw
rw
Bits 31:6 Reserved, must be kept at reset value.
Bit 5 GPIOFSMEN: I/O port F clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
RM0503 Rev 2
197/1325
213
Reset and clock control (RCC)
RM0503
Bit 4 GPIOESMEN: I/O port E clock enable during Sleep mode(1)
Set and cleared by software.
0: Disable
1: Enable
Bit 3 GPIODSMEN: I/O port D clock enable during Sleep mode(1)
Set and cleared by software.
0: Disable
1: Enable
Bit 2 GPIOCSMEN: I/O port C clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Bit 1 GPIOBSMEN: I/O port B clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Bit 0 GPIOASMEN: I/O port A clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
1. Only significant on devices integrating the corresponding peripheral, otherwise reserved. Refer to Section 1.4: Availability of
peripherals.
5.4.19
APB peripheral clock enable in Sleep/Stop mode register 1
(RCC_APBSMENR1)
Address offset: 0x78
Reset value: 0b1111 1111 0111 1110 0100 1100 0011 0011
31
30
29
LPTIM1 LPTIM2 DAC1
SMEN SMEN SMEN
28
27
PWR
SMEN
Res.
rw
rw
rw
rw
15
14
13
12
SPI3
SMEN
SPI2
SMEN
USB
SMEN
rw
rw
rw
198/1325
11
26
rw
24
23
LPTIM3 I2C4 OPAMP I2C3
SMEN SMEN SMEN SMEN
22
21
I2C2
SMEN
I2C1
SMEN
20
19
18
17
16
LP
USART USART USART
CRS
UART1
4
3
2
SMEN
SMEN SMEN SMEN SMEN
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
10
9
8
7
6
5
4
3
2
1
0
Res.
LP
UART2
SMEN
Res.
TIM7
SMEN
TIM6
SMEN
Res.
Res.
TIM3
SMEN
TIM2
SMEN
rw
rw
rw
rw
LP
RTC
WWDG
UART3
APB
SMEN
SMEN
SMEN
rw
25
rw
LCD
SMEN
rw
rw
RM0503 Rev 2
RM0503
Reset and clock control (RCC)
Bit 31 LPTIM1SMEN: Low-power timer 1 clock enable during Sleep and Stop modes
Set and cleared by software.
0: Disable
1: Enable
Bit 30 LPTIM2SMEN: Low-power timer 2 clock enable during Sleep and Stop modes
Set and cleared by software.
0: Disable
1: Enable
Bit 29 DAC1SMEN: DAC1 interface clock enable during Sleep and Stop modes
Set and cleared by software.
0: Disable
1: Enable
Bit 28 PWRSMEN: Power interface clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Bit 27 Reserved, must be kept at reset value.
Bit 26 LPTIM3SMEN: Low-power timer 3 clock enable during Sleep mode(1)
Set and cleared by software.
0: Disable
1: Enable
Bit 25 I2C4SMEN: I2C4 clock enable during Sleep mode(1)
Set and cleared by software.
0: Disable
1: Enable
Bit 24 OPAMPSMEN: OPAMP clock enable during Sleep and Stop modes
Set and cleared by software.
0: Disable
1: Enable
Bit 23 I2C3SMEN: I2C3 clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Bit 22 I2C2SMEN: I2C2 clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Bit 21 I2C1SMEN: I2C1 clock enable during Sleep and Stop modes
Set and cleared by software.
0: Disable
1: Enable
Bit 20 LPUART1SMEN: LPUART1 clock enable during Sleep and Stop modes
Set and cleared by software.
0: Disable
1: Enable
RM0503 Rev 2
199/1325
213
Reset and clock control (RCC)
RM0503
Bit 19 USART4SMEN: USART4 clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Bit 18 USART3SMEN: USART3 clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Bit 17 USART2SMEN: USART2 clock enable during Sleep and Stop modes
Set and cleared by software.
0: Disable
1: Enable
Bit 16 CRSSMEN: CRS clock enable during Sleep and Stop modes(1)
Set and cleared by software.
0: Disable
1: Enable
Bit 15 SPI3SMEN: SPI3 clock enable during Sleep mode(1)
Set and cleared by software.
0: Disable
1: Enable
Bit 14 SPI2SMEN: SPI2 clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Bit 13 USBSMEN: USB clock enable during Sleep mode(1)
Set and cleared by software.
0: Disable
1: Enable
Bit 12 LPUART3SMEN: LPUART3 clock enable during Sleep and Stop modes
Set and cleared by software.
0: Disable
1: Enable
Bit 11 WWDGSMEN: WWDG clock enable during Sleep and Stop modes
Set and cleared by software.
0: Disable
1: Enable
Bit 10 RTCAPBSMEN: RTC APB clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Bit 9 LCDSMEN: LCD clock enable during Sleep mode(1)
Set and cleared by software.
0: Disable
1: Enable
Bit 8 Reserved, must be kept at reset value.
200/1325
RM0503 Rev 2
RM0503
Reset and clock control (RCC)
Bit 7 LPUART2SMEN: LPUART2 clock enable during Sleep and Stop modes
Set and cleared by software.
0: Disable
1: Enable
Bit 6 Reserved, must be kept at reset value.
Bit 5 TIM7SMEN: TIM7 timer clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Bit 4 TIM6SMEN: TIM6 timer clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Bits 3:2 Reserved, must be kept at reset value.
Bit 1 TIM3SMEN: TIM3 timer clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Bit 0 TIM2SMEN: TIM2 timer clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
1. Only significant on devices integrating the corresponding peripheral, otherwise reserved. Refer to Section 1.4: Availability
of peripherals.
5.4.20
APB peripheral clock enable in Sleep/Stop mode register 2
(RCC_APBSMENR2)
Address offset: 0x80
Reset value: 0x0017 D801
31
Res.
30
Res.
29
Res.
28
Res.
27
Res.
26
Res.
25
Res.
24
Res.
23
Res.
22
Res.
21
20
Res.
ADC
SMEN
19
Res.
18
17
16
Res.
TIM16
SMEN
TIM15
SMEN
rw
rw
rw
15
14
Res.
USART
1
SMEN
rw
13
Res.
12
11
SPI1
SMEN
TIM1
SMEN
rw
rw
10
Res.
9
Res.
8
Res.
7
Res.
6
Res.
5
Res.
4
Res.
3
Res.
2
Res.
1
0
Res.
SYS
CFG
SMEN
rw
Bits 31:21 Reserved, must be kept at reset value.
Bit 20 ADCSMEN: ADC clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Bits 19:18 Reserved, must be kept at reset value.
RM0503 Rev 2
201/1325
213
Reset and clock control (RCC)
RM0503
Bit 17 TIM16SMEN: TIM16 timer clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Bit 16 TIM15SMEN: TIM15 timer clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Bit 15 Reserved, must be kept at reset value.
Bit 14 USART1SMEN: USART1 clock enable during Sleep and Stop modes
Set and cleared by software.
0: Disable
1: Enable
Bit 13 Reserved, must be kept at reset value.
Bit 12 SPI1SMEN: SPI1 clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Bit 11 TIM1SMEN: TIM1 timer clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Bits 10:1 Reserved, must be kept at reset value.
Bit 0 SYSCFGSMEN: SYSCFG, COMP and VREFBUF clock enable during Sleep and Stop modes
Set and cleared by software.
0: Disable
1: Enable
5.4.21
Peripherals independent clock configuration register (RCC_CCIPR)
Address offset: 0x88
Reset value: 0x0000 0000
31
Res.
30
Res.
15
Res.
14
Res.
202/1325
29
28
ADCSEL[1:0]
rw
rw
13
12
27
26
CLK48SEL[1:0]
rw
rw
11
10
25
24
TIM15
SEL
TIM1
SEL
rw
rw
9
8
23
22
rw
rw
rw
rw
7
6
5
4
I2C1SEL[1:0]
LPUART2SEL
[1:0]
LPUART3SEL
[1:0]
rw
rw
rw
rw
rw
rw
20
19
18
LPTIM3SEL[1:0] LPTIM2SEL[1:0] LPTIM1SEL[1:0]
LPUART1SEL
[1:0]
rw
21
RM0503 Rev 2
rw
Res.
Res.
rw
rw
3
2
17
16
I2C3SEL[1:0]
rw
rw
1
0
USART2SEL
[1:0]
USART1SEL
[1:0]
rw
rw
rw
rw
RM0503
Reset and clock control (RCC)
Bits 31:30 Reserved, must be kept at reset value.
Bits 29:28 ADCSEL[1:0]: ADCs clock source selection
This bitfield is controlled by software to select the clock source for ADC:
00: System clock
01: PLLPCLK
10: HSI16
11: Reserved
Bits 27:26 CLK48SEL[1:0]: 48 MHz clock source selection
This bitfield is controlled by software to select the 48 MHz clock source used by the USB FS
and the RNG:
00: No clock
01: MSI
10: PLLQCLK
11: HSI48(1)
Bit 25 TIM15SEL: TIM15 clock source selection
This bit is set and cleared by software. It selects TIM15 clock source as follows:
0: TIMPCLK
1: PLLQCLK
Bit 24 TIM1SEL: TIM1 clock source selection
This bit is set and cleared by software. It selects TIM1 clock source as follows:
0: TIMPCLK
1: PLLQCLK
Bits 23:22 LPTIM3SEL[1:0]: LPTIM3 clock source selection(1)
This bitfield is controlled by software to select LPTIM3 clock source as follows:
00: PCLK
01: LSI
10: HSI16
11: LSE
Bits 21:20 LPTIM2SEL[1:0]: LPTIM2 clock source selection
This bitfield is controlled by software to select LPTIM2 clock source as follows:
00: PCLK
01: LSI
10: HSI16
11: LSE
Bits 19:18 LPTIM1SEL[1:0]: LPTIM1 clock source selection
This bitfield is controlled by software to select LPTIM1 clock source as follows:
00: PCLK
01: LSI
10: HSI16
11: LSE
Bits 17:16 I2C3SEL[1:0]: I2C3 clock source selection
This bitfield is controlled by software to select I2C3 clock source as follows:
00: PCLK
01: SYSCLK
10: HSI16
11: Reserved
Bits 15:14 Reserved, must be kept at reset value.
RM0503 Rev 2
203/1325
213
Reset and clock control (RCC)
RM0503
Bits 13:12 I2C1SEL[1:0]: I2C1 clock source selection
This bitfield is controlled by software to select I2C1 clock source as follows:
00: PCLK
01: SYSCLK
10: HSI16
11: Reserved
Bits 11:10 LPUART1SEL[1:0]: LPUART1 clock source selection
This bitfield is controlled by software to select LPUART1 clock source as follows:
00: PCLK
01: SYSCLK
10: HSI16
11: LSE
Bits 9:8 LPUART2SEL[1:0]: LPUART2 clock source selection
This bitfield is controlled by software to select LPUART2 clock source as follows:
00: PCLK
01: SYSCLK
10: HSI16
11: LSE
Bits 7:6 LPUART3SEL[1:0]: LPUART3 clock source selection(1)
This bitfield is controlled by software to select LPUART3 clock source as follows:
00: PCLK
01: SYSCLK
10: HSI16
11: LSE
Bits 5:4 Reserved, must be kept at reset value.
Bits 3:2 USART2SEL[1:0]: USART2 clock source selection
This bitfield is controlled by software to select USART2 clock source as follows:
00: PCLK
01: SYSCLK
10: HSI16
11: LSE
Bits 1:0 USART1SEL[1:0]: USART1 clock source selection
This bitfield is controlled by software to select USART1 clock source as follows:
00: PCLK
01: SYSCLK
10: HSI16
11: LSE
1. Only significant on devices integrating the corresponding peripheral, otherwise reserved. Refer to Section 1.4: Availability
of peripherals.
204/1325
RM0503 Rev 2
RM0503
Reset and clock control (RCC)
5.4.22
RTC domain control register (RCC_BDCR)
Up to three wait states are inserted in case of successive accesses to this register. As this
register is outside of the VCORE domain, it is write-protected upon reset. The DBP bit of the
Power control register 1 (PWR_CR1) must be set to allow their modification. Refer to
Section 4.1.4: Battery backup domain on page 108 for further information.
The register bits are only reset upon RTC domain reset (see Section 5.1.3: RTC domain
reset), except the LSCOSEL, LSCOEN, and BDRST bits that are only reset upon RTC
domain power-on reset. Any internal or external reset has no effect on these bits.
Address offset: 0x90
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
LSCO
SEL
LSCO
EN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
BDRST
7
6
5
4
3
2
1
0
LSE
SYSEN
LSE
CSSD
LSE
CSS
ON
LSEDRV[1:0]
LSE
BYP
LSE
RDY
LSEON
rw
r
rw
rw
rw
r
rw
Res.
Res.
Res.
Res.
Res.
Res.
rw
rw
15
14
13
12
11
10
9
8
RTCEN
Res.
Res.
Res.
LSE
SYS
RDY
Res.
RTCSEL[1:0]
rw
r
rw
rw
rw
rw
Bits 31:26 Reserved, must be kept at reset value.
Bit 25 LSCOSEL: Low-speed clock output selection
Set and cleared by software to select the low-speed output clock:
0: LSI
1: LSE
Bit 24 LSCOEN: Low-speed clock output (LSCO) enable
Set and cleared by software.
0: Disable
1: Enable
Bits 23:17 Reserved, must be kept at reset value.
Bit 16 BDRST: RTC domain software reset
Set and cleared by software to reset the RTC domain:
0: No effect
1: Reset
Bit 15 RTCEN: RTC clock enable
Set and cleared by software. The bit enables clock to RTC and TAMP.
0: Disable
1: Enable
Bits 14:12 Reserved, must be kept at reset value.
Bit 11 LSESYSRDY: LSE clock ready for system usage
This flag is set by hardware to indicate that the LSE clock is ready for being used by the
system (see LSESYSEN bit). This flag is set when LSE clock is ready (LSEON = 1 and
LSERDY = 1) and two LSE clock cycles after that LSESYSEN is set.
Cleared by hardware to indicate that the LSE clock is not ready to be used by the system.
0: LSE clock not ready for system
1: LSE clock ready for system
RM0503 Rev 2
205/1325
213
Reset and clock control (RCC)
RM0503
Bit 10 Reserved, must be kept at reset value.
Bits 9:8 RTCSEL[1:0]: RTC clock source selection
Set by software to select the clock source for the RTC as follows:
00: No clock
01: LSE
10: LSI
11: HSE divided by 32
Once the RTC clock source is selected, it cannot be changed anymore unless the RTC
domain is reset, or unless a failure is detected on LSE (LSECSSD is set). The BDRST bit
can be used to reset this bitfield to 00.
Bit 7 LSESYSEN: LSE clock enable for system usage
This bit must be set by software to enable the LSE clock for a system usage.
0: Disabled
1: Enabled, LSE distributed to peripherals including LSCO/MCO/SYSCLK.
Bit 6 LSECSSD: CSS on LSE failure Detection
Set by hardware to indicate when a failure is detected by the clock security system
on the external 32 kHz oscillator (LSE):
0: No failure detected
1: Failure detected
Bit 5 LSECSSON: CSS on LSE enable
Set by software to enable the clock security system on LSE (32 kHz) oscillator as follows:
0: Disable
1: Enable
LSECSSON must be enabled after the LSE oscillator is enabled (LSEON bit enabled) and
ready (LSERDY flag set by hardware), and after the RTCSEL bit is selected.
Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD
=1). In that case the software must disable the LSECSSON bit.
Bits 4:3 LSEDRV[1:0]: LSE oscillator drive capability
Set by software to select the LSE oscillator drive capability as follows:
00: low driving capability
01: medium-low driving capability
10: medium-high driving capability
11: high driving capability
Applicable when the LSE oscillator is in Xtal mode, as opposed to bypass mode.
206/1325
RM0503 Rev 2
RM0503
Reset and clock control (RCC)
Bit 2 LSEBYP: LSE oscillator bypass
Set and cleared by software to bypass the LSE oscillator (in debug mode).
0: Not bypassed
1: Bypassed
This bit can be written only when the external 32 kHz oscillator is disabled (LSEON=0 and
LSERDY=0).
Bit 1 LSERDY: LSE oscillator ready
Set and cleared by hardware to indicate when the external 32 kHz oscillator is ready (stable):
0: Not ready
1: Ready
After the LSEON bit is cleared, LSERDY goes low after 6 external low-speed oscillator clock
cycles.
Bit 0 LSEON: LSE oscillator enable
Set and cleared by software to enable LSE oscillator:
0: Disable
1: Enable
5.4.23
Control/status register (RCC_CSR)
Up to three wait states are inserted in case of successive accesses to this register. The
register is reset upon system reset, except for reset flags that are only reset upon power
reset.
Address offset: 0x94
Reset value: 0xXX00 0000
31
30
LPWR WWDG
RSTF
RSTF
29
28
27
26
25
24
23
22
21
20
19
18
17
16
IWDG
RSTF
SFT
RSTF
PWR
RSTF
PIN
RSTF
OBL
RSTF
Res.
RMVF
Res.
Res.
Res.
Res.
Res.
Res.
Res.
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
LSI
PRE
DIV
LSI
RDY
LSION
rw
r
rw
r
r
r
r
r
r
r
15
14
13
12
11
10
9
Res.
Res.
Res.
Res.
rw
8
MSISRANGE[3:0]
rw
rw
rw
rw
RM0503 Rev 2
207/1325
213
Reset and clock control (RCC)
RM0503
Bit 31 LPWRRSTF: Low-power reset flag
Set by hardware when a reset occurs due to illegal Stop, Standby, or Shutdown mode entry.
Cleared by setting the RMVF bit.
0: No illegal mode reset occurred
1: Illegal mode reset occurred
This operates only if nRST_STOP, nRST_STDBY or nRST_SHDW option bits are cleared.
Bit 30 WWDGRSTF: Window watchdog reset flag
Set by hardware when a window watchdog reset occurs.
Cleared by setting the RMVF bit.
0: No window watchdog reset occurred
1: Window watchdog reset occurred
Bit 29 IWDGRSTF: Independent window watchdog reset flag
Set by hardware when an independent watchdog reset domain occurs.
Cleared by setting the RMVF bit.
0: No independent watchdog reset occurred
1: Independent watchdog reset occurred
Bit 28 SFTRSTF: Software reset flag
Set by hardware when a software reset occurs.
Cleared by setting the RMVF bit.
0: No software reset occurred
1: Software reset occurred
Bit 27 PWRRSTF: BOR or POR/PDR flag
Set by hardware when a BOR or POR/PDR occurs.
Cleared by setting the RMVF bit.
0: No BOR or POR occurred
1: BOR or POR occurred
Bit 26 PINRSTF: Pin reset flag
Set by hardware when a reset from the NRST pin occurs.
Cleared by setting the RMVF bit.
0: No reset from NRST pin occurred
1: Reset from NRST pin occurred
Bit 25 OBLRSTF: Option byte loader reset flag
Set by hardware when a reset from the Option byte loading occurs.
Cleared by setting the RMVF bit.
0: No reset from Option byte loading occurred
1: Reset from Option byte loading occurred
Bit 24 Reserved, must be kept at reset value.
Bit 23 RMVF: Remove reset flags
Set by software to clear the reset flags.
0: No effect
1: Clear reset flags
Bits 22:12 Reserved, must be kept at reset value.
208/1325
RM0503 Rev 2
RM0503
Reset and clock control (RCC)
Bits 11:8 MSISRANGE[3:0]: MSI range after Standby mode
Set by software to chose the MSI frequency at startup. This range is used after exiting
Standby mode until MSIRGSEL is set. After a pad or a power-on reset, the range is always
4 MHz. MSISRANGE[3:0] can be written only when MSIRGSEL = 1.
0100: Range 4 around 1 MHz
0100: Range 5 around 2 MHz
0100: Range 6 around 4 MHz
0100: Range 7 around 8 MHz
Others: Reserved
Note: Changing the MSISRANGE[3:0] does not change the current MSI frequency.
Bits 7:3 Reserved, must be kept at reset value.
Bit 2 LSIPREDIV: Internal low-speed oscillator pre-divided by 128
Set and reset by hardware to indicate when the low-speed internal RC oscillator has to be
divided by 128. The software has to switch off the LSI before changing this bit.
0: LSI RC oscillator is not divided
1: LSI RC oscillator is divided by 128
Bit 1 LSIRDY: LSI oscillator ready
Set and cleared by hardware to indicate when the LSI oscillator is ready (stable):
0: Not ready
1: Ready
After the LSION bit is cleared, LSIRDY goes low after 3 LSI oscillator clock cycles. This bit
can be set even if LSION = 0 if the LSI is requested by the Clock Security System on LSE, by
the Independent Watchdog or by the RTC.
Bit 0 LSION: LSI oscillator enable
Set and cleared by software to enable/disable the LSI oscillator:
0: Disable
1: Enable
5.4.24
RCC clock recovery RC register (RCC_CRRCR)
This register applies to STM32U073xx and STM32U083xx devices only. It is reserved
otherwise.
Address offset: 0x98
Reset value: 0b0000 0000 0000 0000 1000 1000 0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
HSI48
RDY
HSI48
ON
r
rw
HSI48CAL[8:0]
r
r
r
r
r
Res.
r
r
r
r
Res.
Res.
Res.
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:7 HSI48CAL[8:0]: HSI48 clock calibration(1)
These bits are initialized at startup with the factory-programmed HSI48 calibration trim
value.
RM0503 Rev 2
209/1325
213
Reset and clock control (RCC)
RM0503
Bits 6:2 Reserved, must be kept at reset value.
Bit 1 HSI48RDY: HSI48 clock ready flag(1)
The flag is set when the HSI48 clock is ready for use.
Bit 0 HSI48ON: HSI48 RC oscillator enable(1)
0: Disable
1: Enable
1. Only significant on devices integrating the corresponding peripheral, otherwise reserved. Refer to Section 1.4: Availability
of peripherals.
5.4.25
RCC register map
The following table gives the RCC register map and the reset values.
0
0
3
2
1
0
MSIPLLEN
MSIRDY
MSION
4
MSIRGSEL
5
6
8
HSION
MSIRANGE[3:0]
9
HSIKERON
1
0
1
0
0
0
0
PLLN[6:0]
0
0
0
0
0
0
0
0
0
0
PLLSRC[1:0]
0
0
SW[2:0]
0
X X X X X X X X
Res.
0
0
0
0
LSIRDYIE
LSIRDYF
0
0
0
0
LSIRDYC
LSERDYIE
LSERDYF
0
LSERDYC
MSIRDYIE
MSIRDYF
0
MSIRDYC
HSIRDYIE
0
HSIRDYF
0
HSIRDYC
HSERDYIE
0
HSERDYF
0
HSERDYC
PLLRDYIE
Res.
0
PLLRDYF
0
0
PLLRDYC
0
Res.
0
Res.
0
Res.
0
Res.
CSSF
0
CSSC
LSECSSIE.
LSECSSF
HSI48RDYIE
0
LSECSSC
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
RM0503 Rev 2
0
HSI48RDYF
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
210/1325
0
HSI48RDYC
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
RCC_CICR
0
0
Reset value
0x20
1
Res.
Res.
RCC_CIFR
0
Res.
0
0
0
SWS[2:0]
0
0
0
PLLM[2:0]
0
0
0
0
Res.
0
0
0
Res.
0
0
Res.
0
0
HPRE[3:0]
0
0
Reset value
0x1C
7
11
13
10
14
Res.
HSIRDY
15
Res.
12
16
Res.
HSIASFS
17
HSEON
0
Reserved
RCC_CIER
Res.
18
HSERDY
0
0
0
Res.
0
X X
Res.
0
X
PLLP[4:0]
PLLQ[2:0]
0
1
MSICAL[7:0]
Res.
0
0
Res.
0
0
PPRE[2:0]
0
X
STOPWUCK
0
X
Res.
0
X
0
MSITRIM[7:0]
PLLPEN
X
MCOSEL[3:0]
0
19
21
X
0
Res.
0
0
Res.
0
HSEBYP
22
Res.
0
0
MCO2PRE[3:0]
0
0
Res.
0
0
Res.
0
Res.
0x18
0
Res.
0x10 0x14
0
PLLREN
RCC_PLLCFGR
Reset value
0
PLLR[2:0]
0
Res.
0x0C
0
MCOPRE[3:0]
RCC_CFGR
Reset value
0
0
HSICAL[7:0]
PLLQEN
1
Reset value
0x08
HSITRIM[6:0]
0
MCO2SEL[3:0]
Res.
RCC_ICSCR
Res.
0x04
20
23
Res.
0
CSSON
24
Res.
0
Reset value
Res.
25
27
Res.
PLLON
28
Res.
26
29
Res.
PLLRDY
30
RCC_CR
Res.
31
0x00
Register
Res.
Offset
Res.
Table 33. RCC register map and reset values
0
0
0
0
0
0
0x58
0x5C
RCC_APBENR1
Reset value
0
0
0
0
I2C3EN
I2C2EN
I2C1EN
LPUART1EN
USART4EN
USART3EN
USART2EN
CRSEN
SPI3EN
SPI2EN
USBEN
LPUART3EN
WWDGEN
RTCAPBEN
LCDEN
Reserved
RM0503 Rev 2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GPIOAEN
0
0
Reset value
Res.
DBGEN
0
0
0
TIM2EN
GPIOBEN
DMA1EN
Res.
DMA2EN
1
DBGRST
GPIOCEN
0
Res.
Res.
GPIOARST
0
0
0
Res.
Res.
TIM2RST
GPIOBRST
0
0
0
SYSCFGRST
GPIOCRST
0
TIM3RST
GPIODRST
0
Res.
Res.
Res.
GPIOERST
TIM6RST
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
TIM3EN
GPIODEN
0
Res.
Res.
Res.
GPIOFRST
TIM7RST
Res.
Res.
Res.
LPUART2RST
0
Res.
GPIOEEN
0
Res.
Res.
Res.
Res.
0
Res.
TIM6EN
Reset value
GPIOFEN
Res.
0
Res.
Res.
Res.
Res.
LCDRST
Res.
Reset value
TIM7EN
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
LPUART3RST
0
FLASHEN
USBRST
0
Res.
SPI2RST
0
Res.
SPI3RST
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
CRSRST
0
Res.
USART2RST
0
Res.
USART3RST
0
Res.
USART4RST
0
Res.
LPUART1RST
0
Res.
I2C1RST
0
Res.
TIM1RST
0
Res.
I2C2RST
0
Res.
Res.
SPI1RST
Res.
0
CRCEN
Res.
USART1RST
I2C3RST
0
Res.
0
Res.
Res.
0
Res.
Res.
Res.
Res.
OPAMPRST
Res.
Res.
0
LPUART2EN
Reserved
Res.
0
Res.
Reserved
Res.
0
Res.
0
Res.
TIM15RST
Reserved
AESEN.
TIM16RST
I2C4RST
Reserved
Res.
Res.
Res.
Res.
ADCRST
Res.
Res.
Res.
LPTIM3RST
0
Res.
Res.
RNGEN.
Res.
0
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
TSCEN.
Res.
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
Res.
OPAMPEN
Res.
Res.
Res.
PWRRST
0
Res.
Res.
0
Res.
Res.
DAC1RST
0
Res.
Res.
Res.
LPTIM2RST
0
I2C4EN
RCC_DBGCFGR
Res.
RCC_IOPENR
Res.
LPTIM1RST
Reset value
LPTIM3EN
0x54
RCC_APBRSTR1
Res.
0x50
PWREN
0x4C
RCC_AHBENR
Res.
0x48
RCC_APBRSTR2
Res.
0x44
DAC1EN
0x40
Res.
0x3C
Res.
0x38
RCC_IOPRSTR
Res.
0x30 0x34
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
DMA2RST
DMA1RST
11
10
Res.
9
12
Res.
Res.
13
CRCRST.
FLASHRST.
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Res.
Res.
Res.
Res.
AESRST.
Res.
RNGRST.
Res.
Res.
Res.
Res.
Res.
TSCRST.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
RCC_AHBRSTR
Res.
Reserved
Res.
0x24
Res.
Register
Res.
Offset
Res.
0x2C
LPTIM2EN
0x28
LPTIM1EN
RM0503
Reset and clock control (RCC)
Table 33. RCC register map and reset values (continued)
0
0
0
0
0
0
0
Res.
211/1325
213
0x94
212/1325
RCC_CSR
Reset value
0
0
0
0
0
0
0
0
RM0503 Rev 2
LSESYSEN
LSECSSD
LSECSSON
LSE DRV[1:0]
LSEBYP
LSERDY
LSEON
0
0
0
0
0
0
0
0
0
0
0
MSISRANGE
[3:0]
Res.
Res.
Res.
Res.
Res.
LSIPREDIV
LSIRDY
LSION
0
0
0
0
0
Res.
Res.
Res.
0
0
0
0
1
0
1
1
1
1
1
1
0
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
GPIOASMEN
1
1
1
Res.
Res.
TIM2SMEN
GPIOBSMEN
1
1
1
SYSCFGSMEN
GPIOCSMEN
1
TIM3SMEN
GPIODSMEN
1
Res.
Res.
Res.
Res.
Res.
DMA2SMEN
DMA1SMEN
Res.
Res.
Res.
Res.
Res.
Res.
SRAMSMEN
FLASHSMEN
Res.
Res.
11
10
9
8
7
6
5
4
3
2
1
0
TIM1EN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
SYSCFGEN
12
Res.
Res.
Res.
GPIOESMEN
TIM6SMEN
1
Res.
Res.
GPIOFSMEN
Res.
LPUART2SMEN
TIM7SMEN
Res.
1
Res.
0
USART1SEL[1:0]
1
USART2SEL[1:0]
LCDSMEN
Reset value
Res.
RTCAPBSMEN
Res.
13
SPI1EN
Res.
14
19
ADCEN
Res.
20
Res.
15
21
Res.
USART1EN
22
Res.
16
23
Res.
Res.
24
Res.
17
25
Res.
TIM15EN
26
Res.
18
27
Res.
TIM16EN
CRCSMEN
Res.
1
Res.
WWDGSMEN
Res.
Res.
Res.
Res.
AESSMEN.
1
Res.
LPUART3SMEN
1
LPUART3SEL[1:0]
USBSMEN
Res.
1
Res.
SPI2SMEN
Res.
1
Res.
SPI3SMEN
Res.
Res.
28
Res.
Res.
0
Res.
CRSSMEN
Res.
RNGSMEN.
Res.
0
LPUART2SEL[1:0]
USART2SMEN
Res.
Res.
29
Res.
0
RTC SEL[1:0]
USART3SMEN
Res.
Res.
Res.
Res.
30
Res.
0
0
LPUART1SEL[1:0]
0
Res.
Res.
TIM1SMEN
USART1SMEN
1
LSESYSRDY
Res.
SPI1SMEN
I2C1SEL[1:0]
Res.
1
Res.
1
Res.
0
Res.
Reserved
Res.
1
Res.
1
Res.
0
Res.
TIM15SMEN
USART4SMEN
Res.
Res.
1
Res.
0
RTCEN
Reserved
Res.
I2C3SEL[1:0]
LPUART1SMEN
Reserved
BDRST
1
TIM16SMEN
I2C1SMEN
Res.
Res.
TSCSMEN.
Reserved
Res.
0
Res.
I2C2SMEN
Res.
1
Res.
LPTIM1SEL[1:0]
I2C3SMEN
Res.
Res.
0
Res.
0
Res.
OPAMPSMEN
Res.
Res.
31
RCC_APBENR2
Res.
0
ADCSMEN
I2C4SMEN
Res.
Res.
Res.
Res.
Res.
Res.
Register
Res.
Reset value
Res.
LPTIM2SEL[1:0]
Res.
Res.
Res.
Res.
Res.
LPTIM3SMEN
Res.
Res.
Res.
Res.
Res.
Reset value
Res.
0
Res.
0
Res.
LPTIM3SEL[1:0]
0
Res.
Res.
0
Res.
0
Res.
0
Res.
Reset value
TIM1SEL
0
RMVF
0
LSCOEN
0
TIM15SEL
1
Res.
1
LSCOSEL
CLK48SEL[1:0]
PWRSMEN
1
Res.
DAC1SMEN
1
Res.
LPTIM2SMEN
Reset value
Res.
RCC_BDCR
OBLRSTF
0x90
0
Res.
LPTIM1SMEN
Reset value
Res.
0x8C
PINRSTF
Reset value
Res.
RCC_
APBSMENR1
Res.
RCC_CCIPR
PWRRSTF
0x88
ADCSEL[1:0]
0x84
Res.
RCC_
APBSMENR2
SFTRSTF
0x80
Res.
Reserved
IWDGRSTF
0x7C
Res.
0x70 0x74
Res.
0x78
RCC_IOPSMENR
Res.
0x6C
RCC_
AHBSMENR
Res.
0x68
Res.
0x64
Res.
0x60
LPWRRSTF
Offset
WWDGRSTF
Reset and clock control (RCC)
RM0503
Table 33. RCC register map and reset values (continued)
0
1
1
1
0
0
0
RM0503
Reset and clock control (RCC)
1
0
3
16
Res.
4
17
Res.
Res.
18
Res.
5
19
Res.
Res.
20
Res.
6
21
Res.
0
0
HSI48ON
0
2
1
HSI48RDY
0
Res.
0
Res.
22
Res.
7
0
Res.
23
Res.
8
24
Res.
9
25
Res.
11
26
Res.
10
27
Res.
12
28
Res.
13
29
Res.
0
HSI48CAL[8:0]
1
Reset value
14
30
RCC_CRRCR
15
31
0x98
Register
Res.
Offset
Res.
Table 33. RCC register map and reset values (continued)
0
0
Refer to Section 2.2 on page 55 for the register boundary addresses.
RM0503 Rev 2
213/1325
213
Clock recovery system (CRS)
RM0503
6
Clock recovery system (CRS)
6.1
CRS introduction
The clock recovery system (CRS) is an advanced digital controller acting on the internal
fine-granularity trimmable RC oscillator HSI48. The CRS provides powerful means to
evaluate the oscillator output frequency, based on comparison with a selectable
synchronization signal. The CRS can perform automatic trimming adjustments based on the
measured frequency error value, while keeping the possibility of a manual trimming.
The CRS is ideally suited to provide a precise clock to the USB peripheral. In this case, the
synchronization signal can be derived from the start-of-frame (SOF) packet signalization on
the USB bus, sent by a USB host at 1 ms intervals.
The synchronization signal can also be derived from the LSE oscillator output, or generated
by user software.
6.2
CRS main features
•
6.3
Selectable synchronization source with programmable prescaler and polarity:
–
External pin
–
LSE oscillator output
–
USB SOF packet reception
•
Possibility to generate synchronization pulses by software
•
Automatic oscillator trimming capability with no need of CPU action
•
Manual control option for faster startup convergence
•
16-bit frequency error counter with automatic error value capture and reload
•
Programmable limit for automatic frequency error value evaluation and status reporting
•
Maskable interrupts/events:
–
Expected synchronization (ESYNC)
–
Synchronization OK (SYNCOK)
–
Synchronization warning (SYNCWARN)
–
Synchronization or trimming error (ERR)
CRS implementation
Table 34. CRS features
214/1325
Feature
CRS
TRIM width
7 bits
RM0503 Rev 2
RM0503
Clock recovery system (CRS)
Table 35. CRS internal input/output signals
Internal signal name
Signal type
Description
crs_sync_in_1
Input
00: GPIO AF selected as SYNC signal source
crs_sync_in_2
Input
01: LSE selected as SYNC signal source
crs_sync_in_3
Input
10: USB SOF selected as SYNC signal source (default)
crs_sync_in_4
Input
11: Reserved
6.4
CRS functional description
6.4.1
CRS block diagram
Figure 14. CRS block diagram
SYNCSRC
SWSYNC
crs_sync_in_1
crs_sync_in_2
SYNC divider
(/1, /2, /4,…, /128)
crs_sync_in_3
SYNC
crs_sync_in_4
FELIM
TRIM
FEDIR
FECAP
RCC
16-bit counter
RC 48 MHz
RELOAD
48 MHz
To peripherals
MS53564V2
6.4.2
Synchronization input
For more information on the CRS synchronization source configuration, refer to
Section 6.7.2.
RM0503 Rev 2
215/1325
224
Clock recovery system (CRS)
RM0503
It is also possible to generate a synchronization event by software, by setting the SWSYNC
bit in the CRS_CR register.
6.4.3
Frequency error measurement
The frequency error counter is a 16-bit down/up counter, reloaded with the RELOAD value
on each SYNC event. It starts counting down until it reaches the zero value, where the
ESYNC (expected synchronization) event is generated. Then it starts counting up to the
OUTRANGE limit, where it eventually stops (if no SYNC event is received), and generates a
SYNCMISS event. The OUTRANGE limit is defined as the frequency error limit (FELIM field
of the CRS_CFGR register) multiplied by 128.
When the SYNC event is detected, the actual value of the frequency error counter and its
counting direction are stored in the FECAP (frequency error capture) field and in the FEDIR
(frequency error direction) bit of the CRS_ISR register. When the SYNC event is detected
during the down-counting phase (before reaching the zero value), it means that the actual
frequency is lower than the target (the TRIM value must be incremented). When it is
detected during the up-counting phase, it means that the actual frequency is higher (the
TRIM value must be decremented).
Figure 15. CRS counter behavior
CRS counter value
RELOAD
ESYNC
Down
Up
Frequency
error counter
stopped
OUTRANGE
(128 x FELIM)
WARNING LIMIT
(3 x FELIM)
TOLERANCE LIMIT
(FELIM)
Trimming action:
CRS event:
0
+2
SYNCERR
SYNCWARN
+1
0
SYNCOK
-1
-2
0
SYNCWARN
SYNCMISS
MSv32122V1
216/1325
RM0503 Rev 2
RM0503
6.4.4
Clock recovery system (CRS)
Frequency error evaluation and automatic trimming
The measured frequency error is evaluated by comparing its value with a set of limits:
•
TOLERANCE LIMIT, given directly in the FELIM field of the CRS_CFGR register
•
WARNING LIMIT, defined as 3 × FELIM value
•
OUTRANGE (error limit), defined as 128 × FELIM value
The result of this comparison is used to generate the status indication and also to control the
automatic trimming, which is enabled by setting the AUTOTRIMEN bit in the CRS_CR
register:
•
•
•
•
Note:
When the frequency error is below the tolerance limit, it means that the actual trimming
value in the TRIM field is the optimal one, hence no trimming action is needed.
–
SYNCOK status indicated
–
TRIM value not changed in AUTOTRIM mode
When the frequency error is below the warning limit but above or equal to the tolerance
limit, it means that some trimming action is necessary but that adjustment by one
trimming step is enough to reach the optimal TRIM value.
–
SYNCOK status indicated
–
TRIM value adjusted by one trimming step in AUTOTRIM mode
When the frequency error is above or equal to the warning limit but below the error
limit, a stronger trimming action is necessary, and there is a risk that the optimal TRIM
value is not reached for the next period.
–
SYNCWARN status indicated
–
TRIM value adjusted by two trimming steps in AUTOTRIM mode
When the frequency error is above or equal to the error limit, the frequency is out of the
trimming range. This can also happen when the SYNC input is not clean, or when
some SYNC pulse is missing (for example when one USB SOF is corrupted).
–
SYNCERR or SYNCMISS status indicated
–
TRIM value not changed in AUTOTRIM mode
If the actual value of the TRIM field is close to its limits and the automatic trimming can force
it to overflow or underflow, the TRIM value is set to the limit, and the TRIMOVF status is
indicated.
In AUTOTRIM mode (AUTOTRIMEN bit set in the CRS_CR register), the TRIM field of
CRS_CR is adjusted by hardware and is read-only.
6.4.5
CRS initialization and configuration
RELOAD value
The RELOAD value must be selected according to the ratio between the target frequency
and the frequency of the synchronization source after prescaling. This value is decreased
by 1, to reach the expected synchronization on the zero value. The formula is the following:
RELOAD = (fTARGET / fSYNC) - 1
The reset value of the RELOAD field corresponds to a target frequency of 48 MHz and a
synchronization signal frequency of 1 kHz (SOF signal from USB).
RM0503 Rev 2
217/1325
224
Clock recovery system (CRS)
RM0503
FELIM value
The selection of the FELIM value is closely coupled with the HSI48 oscillator characteristics
and its typical trimming step size. The optimal value corresponds to half of the trimming step
size, expressed as a number of oscillator clock ticks. The following formula can be used:
FELIM = (fTARGET / fSYNC) * STEP[%] / 100% / 2
The result must be always rounded up to the nearest integer value to obtain the best
trimming response. If frequent trimming actions are not needed in the application, the
hysteresis can be increased by slightly increasing the FELIM value.
The reset value of the FELIM field corresponds to (fTARGET / fSYNC) = 48000, and to a typical
trimming step size of 0.14%.
Note:
The trimming step size depends upon the product, check the datasheet for accurate setting.
Caution:
There is no hardware protection from a wrong configuration of the RELOAD and FELIM
fields, this can lead to an erratic trimming response. The expected operational mode
requires proper setup of the RELOAD value (according to the synchronization source
frequency), which is also greater than 128 * FELIM value (OUTRANGE limit).
6.5
CRS in low-power modes
Table 36. Effect of low-power modes on CRS
Mode
Description
Sleep
No effect. CRS interrupts cause the device to exit the Sleep mode.
Stop
CRS registers are frozen. The CRS stops operating until the Stop mode is exited and the
HSI48 oscillator is restarted.
Standby
The peripheral is powered down and must be reinitialized after exiting Standby mode.
Shutdown The peripheral is powered down and must be reinitialized after exiting Shutdown mode.
6.6
CRS interrupts
Table 37. Interrupt control bits
218/1325
Interrupt event
Event flag
Enable
control bit
Clear
flag bit
Expected synchronization
ESYNCF
ESYNCIE
ESYNCC
Synchronization OK
SYNCOKF
SYNCOKIE
SYNCOKC
Synchronization warning
SYNCWARNF
SYNCWARNIE
SYNCWARNC
Synchronization or trimming error
(TRIMOVF, SYNCMISS, SYNCERR)
ERRF
ERRIE
ERRC
RM0503 Rev 2
RM0503
Clock recovery system (CRS)
6.7
CRS registers
Refer to Section 1.2 for a list of abbreviations used in register descriptions.
The peripheral registers can be accessed only by words (32-bit).
6.7.1
CRS control register (CRS_CR)
Address offset: 0x00
Reset value: 0x0000 4000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
5
4
3
2
1
0
Res.
ESYNC
IE
ERR
IE
SYNC
WARNIE
SYNC
OKIE
rw
rw
rw
rw
Res.
TRIM[6:0]
rw
rw
rw
rw
rw
rw
rw
7
6
SW
SYNC
AUTO
TRIMEN
CEN
rt_w1
rw
rw
Bits 31:15 Reserved, must be kept at reset value.
Bits 14:8 TRIM[6:0]: HSI48 oscillator smooth trimming
The default value of the HSI48 oscillator smooth trimming is 64, which corresponds to the
middle of the trimming interval.
Bit 7 SWSYNC: Generate software SYNC event
This bit is set by software in order to generate a software SYNC event. It is automatically
cleared by hardware.
0: No action
1: A software SYNC event is generated.
Bit 6 AUTOTRIMEN: Automatic trimming enable
This bit enables the automatic hardware adjustment of TRIM bits according to the measured
frequency error between two SYNC events. If this bit is set, the TRIM bits are read-only. The
TRIM value can be adjusted by hardware by one or two steps at a time, depending on the
measured frequency error value. Refer to Section 6.4.4 for more details.
0: Automatic trimming disabled, TRIM bits can be adjusted by the user.
1: Automatic trimming enabled, TRIM bits are read-only and under hardware control.
Bit 5 CEN: Frequency error counter enable
This bit enables the oscillator clock for the frequency error counter.
0: Frequency error counter disabled
1: Frequency error counter enabled
When this bit is set, the CRS_CFGR register is write-protected and cannot be modified.
Bit 4 Reserved, must be kept at reset value.
Bit 3 ESYNCIE: Expected SYNC interrupt enable
0: Expected SYNC (ESYNCF) interrupt disabled
1: Expected SYNC (ESYNCF) interrupt enabled
Bit 2 ERRIE: Synchronization or trimming error interrupt enable
0: Synchronization or trimming error (ERRF) interrupt disabled
1: Synchronization or trimming error (ERRF) interrupt enabled
RM0503 Rev 2
219/1325
224
Clock recovery system (CRS)
RM0503
Bit 1 SYNCWARNIE: SYNC warning interrupt enable
0: SYNC warning (SYNCWARNF) interrupt disabled
1: SYNC warning (SYNCWARNF) interrupt enabled
Bit 0 SYNCOKIE: SYNC event OK interrupt enable
0: SYNC event OK (SYNCOKF) interrupt disabled
1: SYNC event OK (SYNCOKF) interrupt enabled
6.7.2
CRS configuration register (CRS_CFGR)
This register can be written only when the frequency error counter is disabled (the CEN bit is
cleared in CRS_CR). When the counter is enabled, this register is write-protected.
Address offset: 0x04
Reset value: 0x2022 BB7F
31
30
SYNCPOL
Res.
rw
29
28
SYNCSRC[1:0]
27
26
Res.
25
24
23
22
21
SYNCDIV[2:0]
20
19
18
17
16
FELIM[7:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
RELOAD[15:0]
rw
rw
Bit 31 SYNCPOL: SYNC polarity selection
This bit is set and cleared by software to select the input polarity for the SYNC signal source.
0: SYNC active on rising edge (default)
1: SYNC active on falling edge
Bit 30 Reserved, must be kept at reset value.
Bits 29:28 SYNCSRC[1:0]: SYNC signal source selection
These bits are set and cleared by software to select the SYNC signal source (see Table 35):
00: crs_sync_in_1 selected as SYNC signal source
01: crs_sync_in_2 selected as SYNC signal source
10: crs_sync_in_3 selected as SYNC signal source
11: crs_sync_in_4 selected as SYNC signal source
Note: When using USB LPM (link power management) and the device is in Sleep mode, the
periodic USB SOF is not generated by the host. No SYNC signal is therefore provided
to the CRS to calibrate the HSI48 oscillator on the run. To guarantee the required clock
precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs
must be used as SYNC signal.
Bit 27 Reserved, must be kept at reset value.
Bits 26:24 SYNCDIV[2:0]: SYNC divider
These bits are set and cleared by software to control the division factor of the SYNC signal.
000: SYNC not divided (default)
001: SYNC divided by 2
010: SYNC divided by 4
011: SYNC divided by 8
100: SYNC divided by 16
101: SYNC divided by 32
110: SYNC divided by 64
111: SYNC divided by 128
220/1325
RM0503 Rev 2
RM0503
Clock recovery system (CRS)
Bits 23:16 FELIM[7:0]: Frequency error limit
FELIM contains the value to be used to evaluate the captured frequency error value latched
in the FECAP[15:0] bits of the CRS_ISR register. Refer to Section 6.4.4 for more details
about FECAP evaluation.
Bits 15:0 RELOAD[15:0]: Counter reload value
RELOAD is the value to be loaded in the frequency error counter with each SYNC event.
Refer to Section 6.4.3 for more details about counter behavior.
6.7.3
CRS interrupt and status register (CRS_ISR)
Address offset: 0x08
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
FECAP[15:0]
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FEDIR
Res.
Res.
Res.
Res.
TRIM
OVF
SYNC
MISS
SYNC
ERR
Res.
Res.
Res.
Res.
ESYNCF
ERRF
SYNC
WARNF
SYNC
OKF
r
r
r
r
r
r
r
r
Bits 31:16 FECAP[15:0]: Frequency error capture
FECAP is the frequency error counter value latched in the time of the last SYNC event.
Refer to Section 6.4.4 for more details about FECAP usage.
Bit 15 FEDIR: Frequency error direction
FEDIR is the counting direction of the frequency error counter latched in the time of the last
SYNC event. It shows whether the actual frequency is below or above the target.
0: Up-counting direction, the actual frequency is above the target
1: Down-counting direction, the actual frequency is below the target
Bits 14:11 Reserved, must be kept at reset value.
Bit 10 TRIMOVF: Trimming overflow or underflow
This flag is set by hardware when the automatic trimming tries to over- or under-flow the
TRIM value. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is
cleared by software by setting the ERRC bit in the CRS_ICR register.
0: No trimming error signaled
1: Trimming error signaled
Bit 9 SYNCMISS: SYNC missed
This flag is set by hardware when the frequency error counter reaches value FELIM * 128
and no SYNC is detected, meaning either that a SYNC pulse was missed, or the frequency
error is too big (internal frequency too high) to be compensated by adjusting the TRIM value,
hence some other action must be taken. At this point, the frequency error counter is stopped
(waiting for a next SYNC), and an interrupt is generated if the ERRIE bit is set in the
CRS_CR register. It is cleared by software by setting the ERRC bit in the CRS_ICR register.
0: No SYNC missed error signaled
1: SYNC missed error signaled
RM0503 Rev 2
221/1325
224
Clock recovery system (CRS)
RM0503
Bit 8 SYNCERR: SYNC error
This flag is set by hardware when the SYNC pulse arrives before the ESYNC event and the
measured frequency error is greater than or equal to FELIM * 128. This means that the
frequency error is too big (internal frequency too low) to be compensated by adjusting the
TRIM value, and that some other action has to be taken. An interrupt is generated if the
ERRIE bit is set in the CRS_CR register. It is cleared by software by setting the ERRC bit in
the CRS_ICR register.
0: No SYNC error signaled
1: SYNC error signaled
Bits 7:4 Reserved, must be kept at reset value.
Bit 3 ESYNCF: Expected SYNC flag
This flag is set by hardware when the frequency error counter reached a zero value. An
interrupt is generated if the ESYNCIE bit is set in the CRS_CR register. It is cleared by
software by setting the ESYNCC bit in the CRS_ICR register.
0: No expected SYNC signaled
1: Expected SYNC signaled
Bit 2 ERRF: Error flag
This flag is set by hardware in case of any synchronization or trimming error. It is the logical
OR of the TRIMOVF, SYNCMISS and SYNCERR bits. An interrupt is generated if the ERRIE
bit is set in the CRS_CR register. It is cleared by software in reaction to setting the ERRC bit
in the CRS_ICR register, which clears the TRIMOVF, SYNCMISS and SYNCERR bits.
0: No synchronization or trimming error signaled
1: Synchronization or trimming error signaled
Bit 1 SYNCWARNF: SYNC warning flag
This flag is set by hardware when the measured frequency error is greater than or equal to
FELIM * 3, but smaller than FELIM * 128. This means that to compensate the frequency
error, the TRIM value must be adjusted by two steps or more. An interrupt is generated if the
SYNCWARNIE bit is set in the CRS_CR register. It is cleared by software by setting the
SYNCWARNC bit in the CRS_ICR register.
0: No SYNC warning signaled
1: SYNC warning signaled
Bit 0 SYNCOKF: SYNC event OK flag
This flag is set by hardware when the measured frequency error is smaller than FELIM * 3.
This means that either no adjustment of the TRIM value is needed or that an adjustment by
one trimming step is enough to compensate the frequency error. An interrupt is generated if
the SYNCOKIE bit is set in the CRS_CR register. It is cleared by software by setting the
SYNCOKC bit in the CRS_ICR register.
0: No SYNC event OK signaled
1: SYNC event OK signaled
222/1325
RM0503 Rev 2
RM0503
Clock recovery system (CRS)
6.7.4
CRS interrupt flag clear register (CRS_ICR)
Address offset: 0x0C
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
ESYNCC
ERRC
SYNC
WARNC
SYNC
OKC
rw
rw
rw
rw
Bits 31:4 Reserved, must be kept at reset value.
Bit 3 ESYNCC: Expected SYNC clear flag
Writing 1 to this bit clears the ESYNCF flag in the CRS_ISR register.
Bit 2 ERRC: Error clear flag
Writing 1 to this bit clears TRIMOVF, SYNCMISS, and SYNCERR bits and consequently also
the ERRF flag in the CRS_ISR register.
Bit 1 SYNCWARNC: SYNC warning clear flag
Writing 1 to this bit clears the SYNCWARNF flag in the CRS_ISR register.
Bit 0 SYNCOKC: SYNC event OK clear flag
Writing 1 to this bit clears the SYNCOKF flag in the CRS_ISR register.
6.7.5
CRS register map
0
14
TRIM[6]
1
15
Res.
SYNCOKIE
16
Res.
2
17
Res.
SYNCWARNIE
18
Res.
3
19
Res.
ERRIE
20
Res.
4
21
Res.
ESYNCIE
22
Res.
5
23
Res.
0
0
0
0
0
0
0
0
0
0
0
CRS_ICR
Reset value
RM0503 Rev 2
0
0
0
SYNCOKF
0
0
0
0
0
SYNCOKC
0
SYNCWARNF
0
SYNCWARNC
0
ERRF
0
ERRC
0
ESYNCF
0
ESYNCC
Res.
0
Res.
Res.
0
Res.
Res.
0
Res.
Res.
0
Res.
0
SYNCERR
0
SYNCMISS
0
Res.
Res.
Reset value
Res.
1
TRIMOVF
1
Res.
1
Res.
1
Res.
1
Res.
1
Res.
1
Res.
0
Res.
1
Res.
1
Res.
0
Res.
1
Res.
1
Res.
1
Res.
0
Res.
FECAP[15:0]
1
Res.
0
Res.
1
Res.
0
Res.
0
Res.
0
Res.
1
Res.
RELOAD[15:0]
FEDIR
0
0
Res.
24
Res.
0
8
25
Res.
0
0
6
0
CEN
0
7
0
AUTOTRIMEN
0
FELIM[7:0]
Res.
CRS_ISR
0
TRIM[5:0]
SWSYNC
26
Res.
0
9
27
Res.
Res.
0
11
28
Res.
1
10
29
Res.
Res.
0
SYNC
DIV
[2:0]
Res.
0x0C
Reset value
SYNC
SRC
[1:0]
Res.
0x08
CRS_CFGR
Res.
0x04
1
SYNCPOL
Reset value
12
30
CRS_CR
13
31
0x00
Res.
Offset
Res.
Table 38. CRS register map and reset values
Register
name
Reset value
0
0
0
0
223/1325
224
Clock recovery system (CRS)
RM0503
Refer to Section 2.2 for the register boundary addresses.
224/1325
RM0503 Rev 2
RM0503
General-purpose I/Os (GPIO)
7
General-purpose I/Os (GPIO)
7.1
Introduction
Each general-purpose I/O port has four 32-bit configuration registers (GPIOx_MODER,
GPIOx_OTYPER, GPIOx_OSPEEDR and GPIOx_PUPDR), two 32-bit data registers
(GPIOx_IDR and GPIOx_ODR) and a 32-bit set/reset register (GPIOx_BSRR). In addition,
all GPIOs have a 32-bit locking register (GPIOx_LCKR) and two 32-bit alternate function
selection registers (GPIOx_AFRH and GPIOx_AFRL).
7.2
7.3
GPIO main features
•
Output states: push-pull or open drain + pull-up/down
•
Output data from output data register (GPIOx_ODR) or peripheral (alternate function
output)
•
Speed selection for each I/O
•
Input states: floating, pull-up/down, analog
•
Input data to input data register (GPIOx_IDR) or peripheral (alternate function input)
•
Bit set and reset register (GPIOx_ BSRR) for bitwise write access to GPIOx_ODR
•
Locking mechanism (GPIOx_LCKR) provided to freeze the I/O port configurations
•
Analog function
•
Alternate function selection registers
•
Fast toggle capable of changing every two clock cycles
•
Highly flexible pin multiplexing allows the use of I/O pins as GPIOs or as one of several
peripheral functions
GPIO functional description
Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each
port bit of the general-purpose I/O (GPIO) ports can be individually configured by software in
several modes:
•
Input floating
•
Input pull-up
•
Input-pull-down
•
Analog
•
Output open-drain with pull-up or pull-down capability
•
Output push-pull with pull-up or pull-down capability
•
Alternate function push-pull with pull-up or pull-down capability
•
Alternate function open-drain with pull-up or pull-down capability
Each I/O port bit is freely programmable. However, the I/O port registers have to be
accessed as 32-bit words, half-words, or bytes. The purpose of the GPIOx_BSRR and
GPIOx_BRR registers is to allow atomic read/modify accesses to any of the GPIOx_ODR
registers. In this way, there is no risk of an IRQ occurring between the read and the modify
access.
RM0503 Rev 2
225/1325
241
General-purpose I/Os (GPIO)
RM0503
Figure 16 and Figure 17 show the basic structures of a standard and a 5-Volt tolerant I/O
port bit, respectively. Table 39 gives the possible port bit configurations.
Figure 16. Basic structure of an I/O port bit
Analog
To on-chip
peripheral
Alternate function input
Input data register
on/off
VDDIOxVDDIOx
trigger
on/off
I/O pin
Output driver
VDDIOx
on/off
Protection
diode
Pull
down
P-MOS
VSS
Output
control
VSS
N-MOS
Read/write
VSS
From on-chip
peripheral
Protection
diode
Pull
up
Input driver
Output data register
Write
Bit set/reset registers
Read
Alternate function output
Push-pull,
open-drain or
disabled
Analog
MS31476V1
Figure 17. Basic structure of a 5-Volt tolerant I/O port bit
To on-chip
peripheral
Input data register
Alternate function input
Read/write
From on-chip
peripheral
Output data register
Write
Bit set/reset registers
Read
on/off
VDDIOx VDD_FT
TTL Schmitt
trigger
on/off
Pull
up
(1)
Protection
diode
Input driver
I/O pin
Output driver
VDDIOx
on/off
P-MOS
Output
control
Pull
down
VSS
Protection
diode
VSS
N-MOS
VSS
Alternate function output
Push-pull,
open-drain or
disabled
ai15939d
1. VDD_FT is a potential specific to five-volt tolerant I/Os and different from VDD.
226/1325
RM0503 Rev 2
RM0503
General-purpose I/Os (GPIO)
Table 39. Port bit configuration table(1)
MODE(i)
[1:0]
01
10
00
11
OTYPER(i)
OSPEED(i)
[1:0]
PUPD(i)
[1:0]
I/O configuration
0
0
0
GP output
PP
0
0
1
GP output
PP + PU
0
1
0
GP output
PP + PD
1
1
Reserved
0
0
GP output
OD
1
0
1
GP output
OD + PU
1
1
0
GP output
OD + PD
1
1
1
Reserved (GP output OD)
0
0
0
AF
PP
0
0
1
AF
PP + PU
0
1
0
AF
PP + PD
1
1
Reserved
0
0
AF
OD
1
0
1
AF
OD + PU
1
1
0
AF
OD + PD
1
1
1
Reserved
0
SPEED
[1:0]
1
0
SPEED
[1:0]
1
x
x
x
0
0
Input
Floating
x
x
x
0
1
Input
PU
x
x
x
1
0
Input
PD
x
x
x
1
1
Reserved (input floating)
x
x
x
0
0
Input/output
x
x
x
0
1
x
x
x
1
0
x
x
x
1
1
Analog
Reserved
1. GP = general-purpose, PP = push-pull, PU = pull-up, PD = pull-down, OD = open-drain, AF = alternate
function.
7.3.1
General-purpose I/O (GPIO)
During and just after reset, the alternate functions are not active and most of the I/O ports
are configured in analog mode.
The debug pins are in AF pull-up/pull-down after reset:
•
PA14: SWCLK in pull-down.
•
PA13: SWDIO in pull-up.
PF3/BOOT0 is in input mode during the reset until at least the end of the option byte loading
phase. See Section 7.3.15: Using PF3 as GPIO.
RM0503 Rev 2
227/1325
241
General-purpose I/Os (GPIO)
RM0503
When the pin is configured as output, the value written to the output data register
(GPIOx_ODR) is output on the I/O pin. It is possible to use the output driver in push-pull
mode or open-drain mode (only the low level is driven, high level is HI-Z).
The input data register (GPIOx_IDR) captures the data present on the I/O pin at every AHB
clock cycle.
All GPIO pins have weak internal pull-up and pull-down resistors, which can be activated or
not depending on the value in the GPIOx_PUPDR register.
7.3.2
I/O pin alternate function multiplexer and mapping
The device I/O pins are connected to on-board peripherals/modules through a multiplexer
that allows only one peripheral alternate function (AF) connected to an I/O pin at a time. In
this way, there can be no conflict between peripherals available on the same I/O pin.
Each I/O pin (except PF3) has a multiplexer with up to 16 alternate function inputs (AF0 to
AF15) that can be configured through the GPIOx_AFRL (for pin 0 to 7) and GPIOx_AFRH
(for pin 8 to 15) registers:
•
After reset, the multiplexer selection is alternate function 0 (AF0). The I/Os are
configured in alternate function mode through the GPIOx_MODER register.
•
The specific alternate function assignments for each pin are detailed in the device
datasheet.
In addition to this flexible I/O multiplexing architecture, each peripheral has alternate
functions mapped onto different I/O pins to optimize the number of peripherals available in
smaller packages.
To use an I/O in a given configuration, the user has to proceed as follows:
•
Debug function: after each device reset these pins are assigned as alternate function
pins immediately usable by the debugger host
•
GPIO: configure the desired I/O as output, input, or analog in the GPIOx_MODER
register.
•
Peripheral alternate function:
•
–
Connect the I/O to the desired AFx in one of the GPIOx_AFRL or GPIOx_AFRH
register.
–
Select the type, pull-up/pull-down and output speed via the GPIOx_OTYPER,
GPIOx_PUPDR and GPIOx_OSPEEDER registers, respectively.
–
Configure the desired I/O as an alternate function in the GPIOx_MODER register.
Additional functions:
–
For the ADC, DAC, OPAMP and COMP, configure the desired I/O in analog mode
in the GPIOx_MODER register and configure the required function in the ADC,
DAC, OPAMP, and COMP registers.
–
For the additional functions like RTC, WKUPx and oscillators, configure the
required function in the related RTC, PWR, and RCC registers. These functions
have priority over the configuration in the standard GPIO registers.
Refer to the “Alternate function mapping” table in the device datasheet for the detailed
mapping of the alternate function I/O pins.
228/1325
RM0503 Rev 2
RM0503
7.3.3
General-purpose I/Os (GPIO)
I/O port control registers
Each of the GPIO ports has four 32-bit memory-mapped control registers (GPIOx_MODER,
GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR) to configure up to 16 I/Os. The
GPIOx_MODER register is used to select the I/O mode (input, output, AF, analog). The
GPIOx_OTYPER and GPIOx_OSPEEDR registers are used to select the output type (pushpull or open-drain) and speed. The GPIOx_PUPDR register is used to select the pullup/pull-down whatever the I/O direction.
7.3.4
I/O port data registers
Each GPIO has two 16-bit memory-mapped data registers: input and output data registers
(GPIOx_IDR and GPIOx_ODR). GPIOx_ODR stores the data to be output, it is read/write
accessible. The data input through the I/O is stored into the input data register
(GPIOx_IDR), a read-only register.
See Section 7.4.5: GPIO port input data register (GPIOx_IDR) (x = A to F) and
Section 7.4.6: GPIO port output data register (GPIOx_ODR) (x = A to F) for the register
descriptions.
7.3.5
I/O data bitwise handling
The bit set reset register (GPIOx_BSRR) is a 32-bit register, which allows the application to
set and reset each individual bit in the output data register (GPIOx_ODR). The bit set reset
register has twice the size of GPIOx_ODR.
To each bit in GPIOx_ODR, correspond two control bits in GPIOx_BSRR: BS(i) and BR(i).
When written to 1, bit BS(i) sets the corresponding ODR(i) bit. When written to 1, bit BR(i)
resets the ODR(i) corresponding bit.
Writing any bit to 0 in GPIOx_BSRR does not have an effect on the corresponding bit in
GPIOx_ODR. If there is an attempt to both set and reset a bit in GPIOx_BSRR, the set
action takes priority.
Using the GPIOx_BSRR register to change the values of individual bits in GPIOx_ODR is a
“one-shot” effect that does not lock the GPIOx_ODR bits. The GPIOx_ODR bits can always
be accessed directly. The GPIOx_BSRR register provides a way of performing atomic
bitwise handling.
There is no need for the software to disable interrupts when programming the GPIOx_ODR
at bit level: it is possible to modify one or more bits in a single atomic AHB write access.
7.3.6
GPIO locking mechanism
It is possible to freeze the GPIO control registers by applying a specific write sequence to
the GPIOx_LCKR register. The frozen registers are GPIOx_MODER, GPIOx_OTYPER,
GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
To write the GPIOx_LCKR register, a specific write / read sequence has to be applied. When
the right LOCK sequence is applied to bit 16 in this register, the value of LCKR[15:0] is used
to lock the configuration of the I/Os (during the write sequence the LCKR[15:0] value must
be the same). When the LOCK sequence has been applied to a port bit, the value of the port
bit can no longer be modified until the next MCU reset or peripheral reset. Each
GPIOx_LCKR bit freezes the corresponding bit in the control registers (GPIOx_MODER,
GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
RM0503 Rev 2
229/1325
241
General-purpose I/Os (GPIO)
RM0503
The LOCK sequence (refer to Section 7.4.8: GPIO port configuration lock register
(GPIOx_LCKR) (x = A to F)) can only be performed using a word (32-bit long) access to the
GPIOx_LCKR register due to the fact that GPIOx_LCKR bit 16 has to be set at the same
time as the [15:0] bits.
For more details, refer to the LCKR register description in Section 7.4.8: GPIO port
configuration lock register (GPIOx_LCKR) (x = A to F).
7.3.7
I/O alternate function input/output
Two registers are provided to select one of the alternate function inputs/outputs available for
each I/O. With these registers, the user can connect an alternate function to some other pin
as required by the application.
This means that a number of possible peripheral functions are multiplexed on each GPIO
using the GPIOx_AFRL and GPIOx_AFRH alternate function registers. The application can
thus select any one of the possible functions for each I/O. The AF selection signal being
common to the alternate function input and alternate function output, a single channel is
selected for the alternate function input/output of a given I/O.
To know which functions are multiplexed on each GPIO pin refer to the device datasheet.
No alternate function is mapped on PF3.
7.3.8
External interrupt/wake-up lines
All ports have external interrupt capability. To use external interrupt lines, the port can be
configured in input, output, or alternate function mode (the port must not be configured in
analog mode).
Refer to Section 12: Extended interrupt and event controller (EXTI) and to Section 12.3.2:
EXTI direct event input wake-up.
7.3.9
Input configuration
When the I/O port is programmed as input:
•
The output buffer is disabled.
•
The Schmitt trigger input is activated.
•
The pull-up and pull-down resistors are activated depending on the value in the
GPIOx_PUPDR register.
•
The data present on the I/O pin are sampled into the input data register every AHB
clock cycle.
•
A read access to the input data register provides the I/O state.
Figure 18 shows the input configuration of the I/O port bit.
230/1325
RM0503 Rev 2
RM0503
General-purpose I/Os (GPIO)
Input data register
Figure 18. Input floating/pull up/pull down configurations
Read/write
Output data register
Write
Bit set/reset registers
Read
on
TTL Schmitt
trigger
input driver
VDDIOx VDDIOx
on/off
protection
diode
pull
up
I/O pin
on/off
output driver
pull
down
VSS
protection
diode
VSS
MS31477V1
7.3.10
Output configuration
When the I/O port is programmed as output:
•
The output buffer is enabled:
–
Open drain mode: A “0” in the Output register activates the N-MOS whereas a “1”
in the Output register leaves the port in high-Z (the P-MOS is never activated)
–
Push-pull mode: A “0” in the Output register activates the N-MOS whereas a “1” in
the Output register activates the P-MOS
•
The Schmitt trigger input is activated
•
The pull-up and pull-down resistors are activated depending on the value in the
GPIOx_PUPDR register
•
The data present on the I/O pin are sampled into the input data register every AHB
clock cycle
•
A read access to the input data register gets the I/O state
•
A read access to the output data register gets the last written value
RM0503 Rev 2
231/1325
241
General-purpose I/Os (GPIO)
RM0503
Figure 19 shows the output configuration of the I/O port bit.
Input data register
Figure 19. Output configuration
Read/write
Output data register
Write
Bit set/reset registers
Read
on
VDDIOx VDDIOx
TTL Schmitt
trigger
on/off
Input driver
pull
up
Output driver
VDDIOx
P-MOS
Output
control
N-MOS
Push-pull or
VSS
Open-drain
protection
diode
I/O pin
on/off
protection
pull
down
diode
VSS
VSS
MS31478V1
7.3.11
Alternate function configuration
When the I/O port is programmed as alternate function:
Note:
232/1325
•
The output buffer can be configured in open-drain or push-pull mode.
•
The signals coming from the peripheral (transmitter enable and data) drive the output
buffer.
•
The Schmitt trigger input is activated.
•
The weak pull-up and pull-down resistors are activated or not depending on the value
in the GPIOx_PUPDR register.
•
The data present on the I/O pin are sampled into the input data register every AHB
clock cycle.
•
A read access to the input data register gets the I/O state.
The alternate function configuration described above is not applied when the selected
alternate function is an LCD function or a SWPMI_IO. In this case, the I/O, programmed as
an alternate function output, is configured as described in the analog configuration.
RM0503 Rev 2
RM0503
General-purpose I/Os (GPIO)
Figure 20 shows the alternate function configuration of the I/O port bit.
Figure 20. Alternate function configuration
Input data register
Alternate function input
To on-chip
peripheral
Bit set/reset registers
Read
VDDIOxVDDIOx
TTL Schmitt
trigger
on/off
Read/write
I/O pin
Output driver
on/off
VDD
P-MOS
Output
control
protection
diode
Pull
down
VSS
VSS
N-MOS
VSS
From on-chip
peripheral
protection
diode
Pull
up
Input driver
Output data register
Write
on
push-pull or
open-drain
Alternate function output
MSv34756V1
Analog configuration
When the I/O port is programmed as an analog configuration:
•
The output buffer is disabled.
•
The Schmitt trigger input is deactivated, providing zero consumption for every analog
value of the I/O pin. The output of the Schmitt trigger is forced to a constant value (0).
•
Hardware disables the weak pull-up and pull-down resistors.
•
Read access to the input data register gets the value “0”.
Figure 21 shows the high-Z, analog-input configuration of the I/O port bits.
Figure 21. High impedance-analog configuration
Input data register
Analog
To on-chip
peripheral
Write
Read/write
From on-chip
peripheral
Output data register
Read
Bit set/reset registers
7.3.12
off
0
VDDIOx
TTL Schmitt
trigger
protection
diode
Input driver
I/O pin
protection
diode
VSS
Analog
MS31480V1
RM0503 Rev 2
233/1325
241
General-purpose I/Os (GPIO)
7.3.13
RM0503
Using the HSE or LSE oscillator pins as GPIOs
When the HSE or LSE oscillator is switched OFF (default state after reset), the related
oscillator pins can be used as normal GPIOs.
When the HSE or LSE oscillator is switched ON (by setting the HSEON or LSEON bit in the
RCC_CSR register), the oscillator takes control of its associated pins and the GPIO
configuration of these pins has no effect.
When the oscillator is configured in user external clock mode, only the pin is reserved for
clock input. The OSC_OUT or OSC32_OUT pin can still be used as normal GPIO.
7.3.14
Using the GPIO pins in the RTC supply domain
The PC13/PC14/PC15 GPIO functionality is lost when the core supply domain is powered
off (when the device enters Standby mode). In this case, if their GPIO configuration is not
bypassed by the RTC configuration, these pins are set in an analog input mode.
For details about I/O control by the RTC, refer to Section 30.3: RTC functional description.
7.3.15
Using PF3 as GPIO
PF3 may be used as boot pin (BOOT0) or as a GPIO. Depending on the nSWBOOT0 bit in
the user option byte, it switches from the input mode to the analog input mode:
7.4
•
After the option byte loading phase if nSWBOOT0 = 1.
•
After reset if nSWBOOT0 = 0.
GPIO registers
For a summary of register bits, register address offsets and reset values, refer to Table 40.
The peripheral registers can be written in word, half word, or byte mode.
7.4.1
GPIO port mode register (GPIOx_MODER) (x = A to F)
Address offset: 0x00
Reset value: 0xEBFF FFFF (for port A)
Reset value: 0xFFFF FFFF (for other ports)
31
30
MODE15[1:0]
29
28
27
26
25
24
23
22
21
20
19
18
17
16
MODE14[1:0]
MODE13[1:0]
MODE12[1:0]
MODE11[1:0]
MODE10[1:0]
MODE9[1:0]
MODE8[1:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MODE7[1:0]
MODE6[1:0]
MODE5[1:0]
MODE4[1:0]
MODE3[1:0]
MODE2[1:0]
MODE1[1:0]
MODE0[1:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
234/1325
rw
rw
rw
RM0503 Rev 2
rw
rw
rw
rw
RM0503
General-purpose I/Os (GPIO)
Bits 31:0 MODEy[1:0]: Port x configuration I/O pin y (y = 15 to 0)
These bits are written by software to configure the I/O mode.
00: Input mode
01: General purpose output mode
10: Alternate function mode
11: Analog mode (reset state)
7.4.2
GPIO port output type register (GPIOx_OTYPER) (x = A to F)
Address offset: 0x04
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OT15
OT14
OT13
OT12
OT11
OT10
OT9
OT8
OT7
OT6
OT5
OT4
OT3
OT2
OT1
OT0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 OT[15:0]: Port x configuration I/O pin y (y = 15 to 0)
These bits are written by software to configure the I/O output type.
0: Output push-pull (reset state)
1: Output open-drain
7.4.3
GPIO port output speed register (GPIOx_OSPEEDR) (x = A to F)
Address offset: 0x08
Reset value: 0x0C00 0000 (for port A)
Reset value: 0x0000 0000 (for the other ports)
31
30
OSPEED15
[1:0]
29
28
27
26
25
24
23
22
21
20
19
18
17
16
OSPEED14
[1:0]
OSPEED13
[1:0]
OSPEED12
[1:0]
OSPEED11
[1:0]
OSPEED10
[1:0]
OSPEED9
[1:0]
OSPEED8
[1:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OSPEED7
[1:0]
OSPEED6
[1:0]
OSPEED5
[1:0]
OSPEED4
[1:0]
OSPEED3
[1:0]
OSPEED2
[1:0]
OSPEED1
[1:0]
OSPEED0
[1:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:0 OSPEEDy[1:0]: Port x configuration I/O pin y (y = 15 to 0)
These bits are written by software to configure the I/O output speed.
00: Low speed
01: Medium speed
10: High speed
11: Very high speed
Note: Refer to the device datasheet for the frequency specifications and the power supply
and load conditions for each speed..
RM0503 Rev 2
235/1325
241
General-purpose I/Os (GPIO)
7.4.4
RM0503
GPIO port pull-up/pull-down register (GPIOx_PUPDR) (x = A to F)
Address offset: 0x0C
Reset value: 0x2400 0000 (for port A)
Reset value: 0x0000 0000 (for other ports)
31
30
29
PUPD15[1:0]
28
27
26
25
24
23
22
21
20
19
18
17
16
PUPD14[1:0]
PUPD13[1:0]
PUPD12[1:0]
PUPD11[1:0]
PUPD10[1:0]
PUPD9[1:0]
PUPD8[1:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PUPD7[1:0]
PUPD6[1:0]
PUPD5[1:0]
PUPD4[1:0]
PUPD3[1:0]
PUPD2[1:0]
PUPD1[1:0]
PUPD0[1:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:0 PUPDy[1:0]: Port x configuration I/O pin y (y = 15 to 0)
These bits are written by software to configure the I/O pull-up or pull-down
00: No pull-up, pull-down
01: Pull-up
10: Pull-down
11: Reserved
7.4.5
GPIO port input data register (GPIOx_IDR) (x = A to F)
Address offset: 0x10
Reset value: 0x0000 XXXX
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ID15
ID14
ID13
ID12
ID11
ID10
ID9
ID8
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 ID[15:0]: Port x input data I/O pin y (y = 15 to 0)
These bits are read-only. They contain the input value of the corresponding I/O port.
7.4.6
GPIO port output data register (GPIOx_ODR) (x = A to F)
Address offset: 0x14
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OD15
OD14
OD13
OD12
OD11
OD10
OD9
OD8
OD7
OD6
OD5
OD4
OD3
OD2
OD1
OD0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
236/1325
RM0503 Rev 2
RM0503
General-purpose I/Os (GPIO)
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 OD[15:0]: Port output data I/O pin y (y = 15 to 0)
These bits can be read and written by software.
Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the
GPIOx_BSRR register (x = A..F).
7.4.7
GPIO port bit set/reset register (GPIOx_BSRR) (x = A to F)
Address offset: 0x18
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
BR15
BR14
BR13
BR12
BR11
BR10
BR9
BR8
BR7
BR6
BR5
BR4
BR3
BR2
BR1
BR0
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BS15
BS14
BS13
BS12
BS11
BS10
BS9
BS8
BS7
BS6
BS5
BS4
BS3
BS2
BS1
BS0
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
Bits 31:16 BR[15:0]: Port x reset I/O pin y (y = 15 to 0)
These bits are write-only. A read to these bits returns the value 0x0000.
0: No action on the corresponding ODx bit
1: Resets the corresponding ODx bit
Note: If both BSx and BRx are set, BSx has priority.
Bits 15:0 BS[15:0]: Port x set I/O pin y (y = 15 to 0)
These bits are write-only. A read to these bits returns the value 0x0000.
0: No action on the corresponding ODx bit
1: Sets the corresponding ODx bit
7.4.8
GPIO port configuration lock register (GPIOx_LCKR) (x = A to F)
This register is used to lock the configuration of the port bits when a correct write sequence
is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the
GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the
RM0503 Rev 2
237/1325
241
General-purpose I/Os (GPIO)
RM0503
LOCK sequence has been applied on a port bit, the value of this port bit can no longer be
modified until the next MCU reset or peripheral reset.
Note:
A specific write sequence is used to write to the GPIOx_LCKR register. Only word access
(32-bit long) is allowed during this locking sequence.
Each lock bit freezes a specific configuration register (control and alternate function
registers).
Address offset: 0x1C
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
LCKK
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LCK15
LCK14
LCK13
LCK12
LCK11
LCK10
LCK9
LCK8
LCK7
LCK6
LCK5
LCK4
LCK3
LCK2
LCK1
LCK0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:17 Reserved, must be kept at reset value.
Bit 16 LCKK: Lock key
This bit can be read any time. It can only be modified using the lock key write sequence.
0: Port configuration lock key not active
1: Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU
reset or peripheral reset.
LOCK key write sequence:
WR LCKR[16] = 1 + LCKR[15:0]
WR LCKR[16] = 0 + LCKR[15:0]
WR LCKR[16] = 1 + LCKR[15:0]
RD LCKR
RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active)
Note: During the LOCK key write sequence, the value of LCK[15:0] must not change.
Any error in the lock sequence aborts the lock.
After the first lock sequence on any bit of the port, any read access on the LCKK bit
returns 1 until the next MCU reset or peripheral reset.
Bits 15:0 LCK[15:0]: Port x lock I/O pin y (y = 15 to 0)
These bits are read/write but can only be written when the LCKK bit is 0.
0: Port configuration not locked
1: Port configuration locked
238/1325
RM0503 Rev 2
RM0503
General-purpose I/Os (GPIO)
7.4.9
GPIO alternate function low register (GPIOx_AFRL) (x = A to F)
Address offset: 0x20
Reset value: 0x0000 0000
31
30
29
28
27
AFSEL7[3:0]
26
25
24
23
AFSEL6[3:0]
22
21
20
19
AFSEL5[3:0]
18
17
16
AFSEL4[3:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
AFSEL3[3:0]
rw
rw
rw
AFSEL2[3:0]
rw
rw
AFSEL1[3:0]
rw
rw
AFSEL0[3:0]
rw
rw
rw
Bits 31:0 AFSELy[3:0]: Alternate function selection for port x I/O pin y (y = 7 to 0)
These bits are written by software to configure alternate function I/Os.
0000: AF0
0001: AF1
0010: AF2
0011: AF3
0100: AF4
0101: AF5
0110: AF6
0111: AF7
1000: AF8
1001: AF9
1010: AF10
1011: AF11
1100: AF12
1101: AF13
1110: AF14
1111: AF15
7.4.10
GPIO alternate function high register (GPIOx_AFRH) (x = A to F)
Address offset: 0x24
Reset value: 0x0000 0000
31
30
29
28
27
AFSEL15[3:0]
rw
15
rw
rw
rw
rw
14
13
12
11
AFSEL11[3:0]
rw
rw
rw
26
25
24
23
AFSEL14[3:0]
rw
rw
rw
rw
10
9
8
7
AFSEL10[3:0]
rw
rw
rw
rw
22
21
20
19
AFSEL13[3:0]
rw
rw
rw
rw
6
5
4
3
AFSEL9[3:0]
rw
rw
RM0503 Rev 2
rw
rw
18
17
16
AFSEL12[3:0]
rw
rw
rw
2
1
0
AFSEL8[3:0]
rw
rw
rw
rw
rw
239/1325
241
General-purpose I/Os (GPIO)
RM0503
Bits 31:0 AFSELy[3:0]: Alternate function selection for port x I/O pin y (y = 15 to 8)
These bits are written by software to configure alternate function I/Os.
0000: AF0
0001: AF1
0010: AF2
0011: AF3
0100: AF4
0101: AF5
0110: AF6
0111: AF7
1000: AF8
1001: AF9
1010: AF10
1011: AF11
1100: AF12
1101: AF13
1110: AF14
1111: AF15
7.4.11
GPIO port bit reset register (GPIOx_BRR) (x = A to F)
Address offset: 0x28
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BR15
BR14
BR13
BR12
BR11
BR10
BR9
BR8
BR7
BR6
BR5
BR4
BR3
BR2
BR1
BR0
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 BR[15:0]: Port x reset IO pin y (y = 15 to 0)
These bits are write-only. A read to these bits returns the value 0x0000.
0: No action on the corresponding ODx bit
1: Reset the corresponding ODx bit
7.4.12
GPIO register map
The following table gives the GPIO register map and reset values.
240/1325
RM0503 Rev 2
GPIOx_AFRH
(where x = A to F)
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x28
GPIOx_BRR
(where x = A to F)
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
BR15
BR14
BR13
BR12
BR11
BR10
BR9
BR8
BR7
BR6
BR5
BR4
BR3
BR2
BR1
BR0
0
0
0
0
0
0
0
0
Res.
Res.
Res.
Res.
Res.
Res.
BR6
BR5
BR4
BR3
0
0
0
0
0
0
0
0
0x1C
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset value
RM0503 Rev 2
0
0
0
0
0
0
0
0
0
0
0
LCK8
LCK7
0
0
0
0
0
0
0
0
0
OD5
OD4
OD3
OD2
OD1
OD0
PUPD0[1:0]
PUPD1[1:0]
PUPD2[1:0]
PUPD3[1:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OSPEED0[1:0]
OSPEED1[1:0]
OSPEED2[1:0]
OSPEED3[1:0]
OSPEED4[1:0]
OSPEED5[1:0]
OSPEED6[1:0]
OSPEED7[1:0]
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
GPIOx_OTYPER
(where x = A to F)
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
OT2
OT1
OT0
OT4
OT3
OT5
OT6
OT8
OT7
OT9
OT11
OT12
OT10
OT13
OT14
1
1
OT15
1
1
0
0
0
0
0
0
0
0
0
LCK0
OD6
1
0
OSPEED8[1:0]
1
1
0
LCK1
OD7
PUPD4[1:0]
1
0
OSPEED9[1:0]
1
1
0
LCK2
OD8
0
0
OSPEED10[1:0]
1
1
0
AFSEL0[3:0]
LCK3
OD9
PUPD5[1:0]
0
0
OSPEED11[1:0]
1
1
0
LCK4
OD11
OD10
PUPD6[1:0]
0
0
OSPEED12[1:0]
0
1
0
LCK5
OD12
0
OSPEED13[1:0]
1
1
0
LCK6
OD13
PUPD7[1:0]
Reset value (port A)
Reset value (port B)
OSPEED14[1:0]
0
1
0
AFSEL1[3:0]
LCK9
OD14
PUPD8[1:0]
PUPD9[1:0]
PUPD10[1:0]
PUPD11[1:0]
PUPD12[1:0]
PUPD13[1:0]
PUPD14[1:0]
1
1
0
LCK11
OD15
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
GPIOx_OSPEEDR
(where x = A to F)
OSPEED15[1:0]
1
1
0
LCK10
AFSEL2[3:0]
LCK12
0
LCK13
0
LCK14
LCK15
Reset value
ID0
Res.
BR7
0
ID1
Res.
BR8
0
BS0
Res.
BR9
0
BS1
Res.
BR11
BR10
0
Res.
Reset value
ID2
Res.
BR12
0
Res.
Reset value
ID3
Res.
BR13
Reset value
GPIOx_LCKR
(where x = A to F)
BS2
Res.
0x18
GPIOx_BSRR
(where x = A to F)
BS3
Res.
0x14
GPIOx_ODR
(where x = A to F)
ID4
GPIOx_IDR
(where x = A to F)
ID5
0x10
BS4
0
BS5
0
0
ID6
0
0
ID7
0
0
BS6
0
0
BS7
0
0
ID8
0
0
ID9
0
0
BS8
0
0
BS9
0
0
ID11
0
0
ID10
0
0
BS11
0
0
BS10
0
0
ID12
0
0
ID13
0
0
BS12
0
0
BS13
0
0
LCKK
0
AFSEL3[3:0]
0
0
ID14
0
0
ID15
0
0
BS14
0
0
BS15
0
0
BR0
0
0
BR1
0
0
Res.
0
0
Res.
PUPD15[1:0]
1
0
AFSEL8[3:0]
0
AFSEL4[3:0]
0
0
BR2
1
0
Res.
Reset value (port A)
Reset value (port B to F)
0
AFSEL9[3:0]
0
AFSEL5[3:0]
0
0
Res.
Reset value
AFSEL10[3:0]
Reset value
AFSEL11[3:0]
GPIOx_AFRL
(where x = A to F)
AFSEL12[3:0]
0x20
AFSEL13[3:0]
0
0
Res.
0x0C
GPIOx_PUPDR (where x
= A to F)
AFSEL6[3:0]
1
0
BR14
0x08
MODE15[1:0]
MODE0[1:0]
MODE1[1:0]
MODE2[1:0]
MODE3[1:0]
MODE4[1:0]
MODE5[1:0]
MODE6[1:0]
MODE7[1:0]
MODE8[1:0]
MODE9[1:0]
MODE10[1:0]
MODE11[1:0]
MODE12[1:0]
MODE13[1:0]
MODE14[1:0]
GPIOx_MODER
AFSEL14[3:0]
0
0
BR15
0x00
AFSEL7[3:0]
0
Res.
0x04
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Register name
Res.
Reset value (Port A)
Reset value (Port B to F)
Res.
Offset
AFSEL15[3:0]
0x24
Res.
RM0503
General-purpose I/Os (GPIO)
Table 40. GPIO register map and reset values
0
0
0
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Refer to Section 2.2 on page 55 for the register boundary addresses.
241/1325
241
System configuration controller (SYSCFG)
8
RM0503
System configuration controller (SYSCFG)
The devices feature a set of configuration registers. The main purposes of the system
configuration controller are the following:
•
Enabling/disabling I2C Fast Mode Plus on some I/O ports
•
Enabling/disabling the analog switch booster
•
Configuring the IR modulation signal and its output polarity
•
Remapping of some I/O ports
•
Remapping the memory located at the beginning of the code area
•
Flag pending interrupts from each interrupt line
•
Managing robustness feature
8.1
SYSCFG registers
8.1.1
SYSCFG configuration register 1 (SYSCFG_CFGR1)
This register is used for specific configurations of memory and DMA requests remap and to
control special I/O features.
Two bits are used to configure the type of memory accessible at address 0x0000 0000.
These bits are used to select the physical remap by software and so, bypass the hardware
BOOT selection. After reset these bits take the value selected by the actual boot mode
configuration.
In the reset value, X is the memory mode selected by the actual boot mode configuration.
Address offset: 0x00
Reset value: 0x0000 000X
31
Res.
30
Res.
15
Res.
14
Res.
29
Res.
13
Res.
28
Res.
12
Res.
27
Res.
11
Res.
26
Res.
10
Res.
25
24
23
22
I2C3_
FMP
I2C_
PA10_
FMP
I2C_
PA9_
FMP
rw
rw
rw
9
8
7
6
Res.
BOOST
EN
Res.
Res.
rw
Bits 31:25 Reserved, must be kept at reset value.
242/1325
RM0503 Rev 2
Res.
21
Res.
20
19
18
17
16
Res.
I2C_
PB9_
FMP
I2C_
PB8_
FMP
I2C_
PB7_
FMP
I2C_
PB6_
FMP
rw
rw
rw
rw
2
1
0
5
4
3
Res.
PA12_
RMP
PA11_
RMP
rw
rw
Res.
MEM_MODE
[1:0]
rw
rw
RM0503
System configuration controller (SYSCFG)
Bit 24 I2C3_FMP: Fast Mode Plus (FM+) enable for I2C3
This bit is set and cleared by software. It enables I2C FM+ driving capability on I/O ports
configured as I2C3 through GPIOx_AFR registers.
0: Disable
1: Enable
With this bit in disable state, the I2C FM+ driving capability on I/O ports configured as I2C3
can be enabled through their corresponding I2Cx_FMP bit. When I2C FM+ is enabled, the
speed control is ignored.
Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the
I2Cx_CR1 register instead.
Bit 23 I2C_PA10_FMP: Fast Mode Plus (FM+) enable for PA10
This bit is set and cleared by software. It enables I2C FM+ driving capability on PA10 I/O
port.
0: Disable
1: Enable
With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled
through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored.
Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the
I2Cx_CR1 register instead.
Bit 22 I2C_PA9_FMP: Fast Mode Plus (FM+) enable for PA9
This bit is set and cleared by software. It enables I2C FM+ driving capability on PA9 I/O port.
0: Disable
1: Enable
With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled
through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored.
Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the
I2Cx_CR1 register instead.
Bits 21:20 Reserved, must be kept at reset value.
Bit 19 I2C_PB9_FMP: Fast Mode Plus (FM+) enable for PB9
This bit is set and cleared by software. It enables I2C FM+ driving capability on PB9 I/O port.
0: Disable
1: Enable
With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled
through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored.
Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the
I2Cx_CR1 register instead.
Bit 18 I2C_PB8_FMP: Fast Mode Plus (FM+) enable for PB8
This bit is set and cleared by software. It enables I2C FM+ driving capability on PB8 I/O port.
0: Disable
1: Enable
With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled
through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored.
Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the
I2Cx_CR1 register instead.
RM0503 Rev 2
243/1325
263
System configuration controller (SYSCFG)
RM0503
Bit 17 I2C_PB7_FMP: Fast Mode Plus (FM+) enable for PB7
This bit is set and cleared by software. It enables I2C FM+ driving capability on PB7 I/O port.
0: Disable
1: Enable
With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled
through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored.
Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the
I2Cx_CR1 register instead.
Bit 16 I2C_PB6_FMP: Fast Mode Plus (FM+) enable for PB6
This bit is set and cleared by software. It enables I2C FM+ driving capability on PB6 I/O port.
0: Disable
1: Enable
With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled
through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored.
Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the
I2Cx_CR1 register instead.
Bits 15:9 Reserved, must be kept at reset value.
Bit 8 BOOSTEN: I/O analog switch voltage booster enable
This bit selects the way of supplying I/O analog switches:
0: VDD
1: Dedicated voltage booster (supplied by VDD)
When using the analog inputs , setting to 0 is recommended for high VDD, setting to 1 for low
VDD (less than 2.4 V).
Bits 7:5 Reserved, must be kept at reset value.
Bit 4 PA12_RMP: PA12 pin remapping
This bit is set and cleared by software. When set, it remaps the PA12 pin to operate as PA10
GPIO port, instead as PA12 GPIO port.
0: No remap (PA12)
1: Remap (PA10)
Bit 3 PA11_RMP: PA11 pin remapping
This bit is set and cleared by software. When set, it remaps the PA11 pin to operate as PA9
GPIO port, instead as PA11 GPIO port.
0: No remap (PA11)
1: Remap (PA9)
Bit 2 Reserved, must be kept at reset value.
Bits 1:0 MEM_MODE[1:0]: Memory mapping selection bits
These bits are set and cleared by software. They control the memory internal mapping at
address 0x0000 0000. After reset these bits take on the value selected by the actual boot
mode configuration. Refer to Section 2.5: Boot configuration for more details.
X0: Main flash memory mapped at 0x0000 0000
01: System flash memory mapped at 0x0000 0000
11: Embedded SRAM mapped at 0x0000 0000
244/1325
RM0503 Rev 2
RM0503
System configuration controller (SYSCFG)
8.1.2
SYSCFG configuration register 2 (SYSCFG_CFGR2)
Address offset: 0x18
System reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
SPF
BKPF
Res.
Res.
BKPL
ECCL
PVDL
SPL
CCL
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
Bits 31:9 Reserved, must be kept at reset value.
Bit 8 SPF: SRAM1 parity error flag
This bit is set by hardware when an SRAM1 parity error is detected. It is cleared by software
by writing 1.
0: No SRAM1 parity error detected
1: SRAM1 parity error detected
Bit 7 BKPF: Backup SRAM2 parity error flag
This bit is set by hardware when an SRAM2 parity error is detected. It is cleared by software
by writing 1.
0: No SRAM2 parity error detected
1: SRAM2 parity error detected
Bits 6:5 Reserved, must be kept at reset value.
Bit 4 BKPL: Backup SRAM2 parity lock
This bit is set by software and cleared by a system reset. It can be used to enable and lock
the SRAM2 parity error signal connection to TIM1/15/16 Break input.
0: SRAM2 parity error disconnected from TIM1/15/16 Break input
1: SRAM2 parity error connected to TIM1/15/16 Break input
Bit 3 ECCL: ECC error lock bit
This bit is set by software and cleared by a system reset. It can be used to enable and lock
the flash memory ECC 2-bit error detection signal connection to TIM1/15/16 Break input.
0: ECC error disconnected from TIM1/15/16 Break input
1: ECC error connected to TIM1/15/16 Break input
RM0503 Rev 2
245/1325
263
System configuration controller (SYSCFG)
RM0503
Bit 2 PVDL: PVD lock enable bit
This bit is set by software and cleared by a system reset. It can be used to enable and lock
the PVD connection to TIM1/15/16 Break input, as well as the PVDE and PLS[2:0] in the
PWR_CR register.
0: PVD interrupt disconnected from TIM1/15/16 Break input. PVDE and PLS[2:0] bits can be
programmed by the application.
1: PVD interrupt connected to TIM1/15/16 Break input, PVDE and PLS[2:0] bits are read
only.
Bit 1 SPL: SRAM1 parity lock bit
This bit is set by software and cleared by a system reset. It can be used to enable and lock
the SRAM1 parity error signal connection to TIM1/15/16 Break input.
0: SRAM1 parity error disconnected from TIM1/15/16 Break input
1: SRAM1 parity error connected to TIM1/15/16 Break input
Bit 0 CCL: Cortex®-M0+ LOCKUP bit enable bit
This bit is set by software and cleared by a system reset. It can be use to enable and lock the
connection of Cortex®-M0+ LOCKUP (Hardfault) output to TIM1/15/16 Break input.
0: Cortex®-M0+ LOCKUP output disconnected from TIM1/15/16 Break input
1: Cortex®-M0+ LOCKUP output connected to TIM1/15/16 Break input
8.1.3
SYSCFG SRAM2 control and status register (SYSCFG_SCSR)
Address offset: 0x1C
System reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
SRAM2 SRAM2
BSY
ER
r
rw
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 SRAM2BSY: SRAM2 busy by erase operation
0: No SRAM2 erase operation is ongoing
1: SRAM2 erase operation is ongoing
Bit 0 SRAM2ER: SRAM2 erase
Setting this bit starts a hardware SRAM2 erase operation. This bit is automatically cleared at
the end of the SRAM2 erase operation.
Note:
246/1325
This bit is write-protected: setting this bit is possible only after the correct
key sequence is written in the SYSCFG_SKR register.
RM0503 Rev 2
RM0503
System configuration controller (SYSCFG)
8.1.4
SYSCFG SRAM2 key register (SYSCFG_SKR)
Address offset: 0x20
System reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
w
w
w
w
w
w
w
KEY[7:0]
w
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 KEY[7:0]: SRAM2 write protection key for software erase
The following steps are required to unlock the write protection of the SRAM2ER bit in the
SYSCFG_CFGR2 register:
1.
Write “0xCA” into KEY[7:0]
2.
Write “0x53” into KEY[7:0]
Writing a wrong key reactivates the write protection.
8.1.5
SYSCFG TSC comparator register (SYSCFG_TSCCR)
Address offset: 0x24
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
TSC_I
G7_IO1 G6_IO1 G4_IO3 G2_IO3 G2_IO1
OCTRL
rw
rw
rw
rw
rw
rw
Bits 31:6 Reserved, must be kept at reset value.
Bit 5 TSC_IOCTRL: I/O control in comparator mode
The I/O control in comparator mode can be overwritten by hardware.
0: I/O configured through the corresponding control register
1: I/O configured as analog when TSC AF is activated
Bit 4 G7_IO1: Comparator mode for group 7 on I/O 2
0: Disabled
1: Enable connection of PA9 to COMP1
Bit 3 G6_IO1: Comparator mode for group 6 on I/O 1
0: Disabled
1: Enable connection of PD10 to COMP2
RM0503 Rev 2
247/1325
263
System configuration controller (SYSCFG)
RM0503
Bit 2 G4_IO3: Comparator mode for group 4 on I/O 1
0: Disabled
1: Enable connection of PC6 to COMP1
Bit 1 G2_IO3: Comparator mode for group 2 on I/O 3
0: Disabled
1: Enable connection of PB6 to COMP2
Bit 0 G2_IO1: Comparator mode for group 2 on I/O 1
0: Disabled
1: Enable connection of PB4 to COMP2
8.1.6
SYSCFG interrupt line 0 status register (SYSCFG_ITLINE0)
A dedicated set of registers is implemented on the device to collect all pending interrupt
sources associated with each interrupt line into a single register. This allows users to check
by single read which peripheral requires service in case more than one source is associated
to the interrupt line.
All bits in those registers are read only, set by hardware when there is corresponding
interrupt request pending and cleared by resetting the interrupt source flags in the
peripheral registers.
Address offset: 0x80
System reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
WWDG
r
Bits 31:1 Reserved, must be kept at reset value.
Bit 0 WWDG: Window watchdog interrupt pending flag
8.1.7
SYSCFG interrupt line 1 status register (SYSCFG_ITLINE1)
Address offset: 0x84
System reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
PVM
OUT4
PVM
OUT3
PVM
OUT1
PVD
OUT
r
r
r
r
Res.
Res.
248/1325
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
RM0503 Rev 2
Res.
RM0503
System configuration controller (SYSCFG)
Bits 31:4 Reserved, must be kept at reset value.
Bit 3 PVMOUT4: DAC supply monitoring interrupt request pending (EXTI line 21)
Bit 2 PVMOUT3: ADC supply monitoring interrupt request pending (EXTI line 20)
Bit 1 PVMOUT1: VDDUSB supply monitoring interrupt request pending (EXTI line 19)
Bit 0 PVDOUT: PVD supply monitoring interrupt request pending (EXTI line 16).
8.1.8
SYSCFG interrupt line 2 status register (SYSCFG_ITLINE2)
Address offset: 0x88
System reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
RTC
TAMP
r
r
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 RTC: RTC interrupt request pending (EXTI line 19)
Bit 0 TAMP: Tamper interrupt request pending (EXTI line 21)
8.1.9
SYSCFG interrupt line 3 status register (SYSCFG_ITLINE3)
Address offset: 0x8C
System reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
FLASH FLASH
_ITF
_ECC
r
r
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 FLASH_ITF: Flash interface interrupt request pending
Bit 0 FLASH_ECC: Flash interface ECC interrupt request pending
RM0503 Rev 2
249/1325
263
System configuration controller (SYSCFG)
8.1.10
RM0503
SYSCFG interrupt line 4 status register (SYSCFG_ITLINE4)
Address offset: 0x90
System reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CRS
RCC
r
r
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 CRS: CRS interrupt request pending
Bit 0 RCC: Reset and clock control interrupt request pending
8.1.11
SYSCFG interrupt line 5 status register (SYSCFG_ITLINE5)
Address offset: 0x94
System reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
EXTI1
EXTI0
r
r
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 EXTI1: EXTI line 1 interrupt request pending
Bit 0 EXTI0: EXTI line 0 interrupt request pending
8.1.12
SYSCFG interrupt line 6 status register (SYSCFG_ITLINE6)
Address offset: 0x98
System reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
EXTI3
EXTI2
r
r
250/1325
RM0503 Rev 2
RM0503
System configuration controller (SYSCFG)
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 EXTI3: EXTI line 3 interrupt request pending
Bit 0 EXTI2: EXTI line 2 interrupt request pending
8.1.13
SYSCFG interrupt line 7 status register (SYSCFG_ITLINE7)
Address offset: 0x9C
System reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
11
10
9
8
7
6
15
14
13
12
Res.
Res.
Res.
Res.
EXTI15 EXTI14 EXTI13 EXTI12 EXTI11 EXTI10
r
r
r
r
r
r
5
4
3
2
1
0
EXTI9
EXTI8
EXTI7
EXTI6
EXTI5
EXTI4
r
r
r
r
r
r
Bits 31:12 Reserved, must be kept at reset value.
Bit 11 EXTI15: EXTI line 15 interrupt request pending
Bit 10 EXTI14: EXTI line 14 interrupt request pending
Bit 9 EXTI13: EXTI line 13 interrupt request pending
Bit 8 EXTI12: EXTI line 12 interrupt request pending
Bit 7 EXTI11: EXTI line 11 interrupt request pending
Bit 6 EXTI10: EXTI line 10 interrupt request pending
Bit 5 EXTI9: EXTI line 9 interrupt request pending
Bit 4 EXTI8: EXTI line 8 interrupt request pending
Bit 3 EXTI7: EXTI line 7 interrupt request pending
Bit 2 EXTI6: EXTI line 6 interrupt request pending
Bit 1 EXTI5: EXTI line 5 interrupt request pending
Bit 0 EXTI4: EXTI line 4 interrupt request pending
8.1.14
SYSCFG interrupt line 8 status register (SYSCFG_ITLINE8)
Address offset: 0xA0
System reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
USB
r
RM0503 Rev 2
251/1325
263
System configuration controller (SYSCFG)
RM0503
Bits 31:1 Reserved, must be kept at reset value.
Bit 0 USB: USB interrupt request pending
8.1.15
SYSCFG interrupt line 9 status register (SYSCFG_ITLINE9)
Address offset: 0xA4
System reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
DMA1_
CH1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
r
Bits 31:1 Reserved, must be kept at reset value.
Bit 0 DMA1_CH1: DMA1 channel 1 interrupt request pending
8.1.16
SYSCFG interrupt line 10 status register (SYSCFG_ITLINE10)
Address offset: 0xA8
System reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
DMA1
_CH3
DMA1
_CH2
r
r
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 DMA1_CH3: DMA1 channel 3 interrupt request pending
Bit 0 DMA1_CH2: DMA1 channel 2 interrupt request pending
252/1325
RM0503 Rev 2
Res.
Res.
RM0503
System configuration controller (SYSCFG)
8.1.17
SYSCFG interrupt line 11 status register (SYSCFG_ITLINE11)
Address offset: 0xAC
System reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
DMA1
_CH5
DMA1
_CH4
DMAM
UX
r
r
r
DMA2_ DMA2_ DMA2_ DMA2_ DMA2_ DMA1_ DMA1_
CH5
CH4
CH3
CH2
CH1
CH7
CH6
r
r
r
r
r
r
r
Bits 31:10 Reserved, must be kept at reset value.
Bit 9 DMA2_CH5: DMA2 channel 5 interrupt request pending
Bit 8 DMA2_CH4: DMA2 channel 4 interrupt request pending
Bit 7 DMA2_CH3: DMA2 channel 3 interrupt request pending
Bit 6 DMA2_CH2: DMA2 channel 2 interrupt request pending
Bit 5 DMA2_CH1: DMA2 channel 1 interrupt request pending
Bit 4 DMA1_CH7: DMA1 channel 7 interrupt request pending
Bit 3 DMA1_CH6: DMA1 channel 6 interrupt request pending
Bit 2 DMA1_CH5: DMA1 channel 5 interrupt request pending
Bit 1 DMA1_CH4: DMA1 channel 4 interrupt request pending
Bit 0 DMAMUX: DMAMUX interrupt request pending
8.1.18
SYSCFG interrupt line 12 status register (SYSCFG_ITLINE12)
Address offset: 0xB0
System reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
COMP
2
COMP
1
ADC
r
r
r
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Bits 31:3 Reserved, must be kept at reset value.
Bit 2 COMP2: Comparator 2 interrupt request pending (EXTI line 18)
Bit 1 COMP1: Comparator 1 interrupt request pending (EXTI line 17)
Bit 0 ADC: ADC interrupt request pending
RM0503 Rev 2
253/1325
263
System configuration controller (SYSCFG)
8.1.19
RM0503
SYSCFG interrupt line 13 status register (SYSCFG_ITLINE13)
Address offset: 0xB4
System reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
TIM1_
BRK
TIM1_
UPD
TIM1_
TRG
TIM1_
CCU
r
r
r
r
Bits 31:4 Reserved, must be kept at reset value.
Bit 3 TIM1_BRK: Timer 1 break interrupt request pending
Bit 2 TIM1_UPD: Timer 1 update interrupt request pending
Bit 1 TIM1_TRG: Timer 1 trigger interrupt request pending
Bit 0 TIM1_CCU: Timer 1 commutation interrupt request pending
8.1.20
SYSCFG interrupt line 14 status register (SYSCFG_ITLINE14)
Address offset: 0xB8
System reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
TIM1_
CC4
TIM1_
CC3
TIM1_
CC2
TIM1_
CC1
r
r
r
r
Bits 31:4 Reserved, must be kept at reset value.
Bit 3 TIM1_CC4: Timer 1 capture compare 4 interrupt request pending
Bit 2 TIM1_CC3: Timer 1 capture compare 3 interrupt request pending
Bit 1 TIM1_CC2: Timer 1 capture compare 2 interrupt request pending
Bit 0 TIM1_CC1: Timer 1 capture compare 1 interrupt request pending
254/1325
RM0503 Rev 2
RM0503
System configuration controller (SYSCFG)
8.1.21
SYSCFG interrupt line 15 status register (SYSCFG_ITLINE15)
Address offset: 0xBC
System reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
TIM2
r
Bits 31:1 Reserved, must be kept at reset value.
Bit 0 TIM2: Timer 2 interrupt request pending
8.1.22
SYSCFG interrupt line 16 status register (SYSCFG_ITLINE16)
Address offset: 0xC0
System reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
TIM3
r
Bits 31:1 Reserved, must be kept at reset value.
Bit 0 TIM3: Timer 3 interrupt request pending
8.1.23
SYSCFG interrupt line 17 status register (SYSCFG_ITLINE17)
Address offset: 0xC4
System reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
LPTIM1
DAC
TIM6
r
r
r
Bits 31:3 Reserved, must be kept at reset value.
Bit 2 LPTIM1: Low-power timer 1 interrupt request pending (EXTI line 29)
Bit 1 DAC: DAC underrun interrupt request pending
Bit 0 TIM6: Timer 6 interrupt request pending
RM0503 Rev 2
255/1325
263
System configuration controller (SYSCFG)
8.1.24
RM0503
SYSCFG interrupt line 18 status register (SYSCFG_ITLINE18)
Address offset: 0xC8
System reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
LPTIM2
TIM7
r
r
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 LPTIM2: Low-power timer 2 interrupt request pending (EXTI line 30)
Bit 0 TIM7: Timer 7 interrupt request pending
8.1.25
SYSCFG interrupt line 19 status register (SYSCFG_ITLINE19)
Address offset: 0xCC
System reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
LPTIM3 TIM15
r
r
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 LPTIM3: Low-power timer 3 interrupt request pending
Bit 0 TIM15: Timer 15 interrupt request pending
8.1.26
SYSCFG interrupt line 20 status register (SYSCFG_ITLINE20)
Address offset: 0xD0
System reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
TIM16
r
Bits 31:1 Reserved, must be kept at reset value.
Bit 0 TIM16: Timer 16 interrupt request pending
256/1325
RM0503 Rev 2
RM0503
System configuration controller (SYSCFG)
8.1.27
SYSCFG interrupt line 21 status register (SYSCFG_ITLINE21)
Address offset: 0xD4
System reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
TSC_
EOA
TSC_
MCE
r
r
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 TSC_EOA: TSC end of acquisition interrupt request pending
Bit 0 TSC_MCE: TSC max count error interrupt request pending
8.1.28
SYSCFG interrupt line 22 status register (SYSCFG_ITLINE22)
Address offset: 0xD8
System reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
LCD
r
Bits 31:1 Reserved, must be kept at reset value.
Bit 0 LCD: LCD interrupt request pending
8.1.29
SYSCFG interrupt line 23 status register (SYSCFG_ITLINE23)
Address offset: 0xDC
System reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
I2C1
r
Bits 31:1 Reserved, must be kept at reset value.
Bit 0 I2C1: I2C1 interrupt request pending (EXTI line 33)
RM0503 Rev 2
257/1325
263
System configuration controller (SYSCFG)
8.1.30
RM0503
SYSCFG interrupt line 24 status register (SYSCFG_ITLINE24)
Address offset: 0xE0
System reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
I2C3
I2C4
I2C2
r
r
r
Bits 31:3 Reserved, must be kept at reset value.
Bit 2 I2C3: I2C3 interrupt request pending (EXTI line 23)
Bit 1 I2C4: I2C4 interrupt request pending
Bit 0 I2C2: I2C2 interrupt request pending
8.1.31
SYSCFG interrupt line 25 status register (SYSCFG_ITLINE25)
Address offset: 0xE4
System reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
SPI1
r
Bits 31:1 Reserved, must be kept at reset value.
Bit 0 SPI1: SPI1 interrupt request pending
8.1.32
SYSCFG interrupt line 26 status register (SYSCFG_ITLINE26)
Address offset: 0xE8
System reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
SPI3
SPI2
r
r
258/1325
RM0503 Rev 2
RM0503
System configuration controller (SYSCFG)
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 SPI3: SPI3 interrupt request pending
Bit 0 SPI2: SPI2 interrupt request pending
8.1.33
SYSCFG interrupt line 27 status register (SYSCFG_ITLINE27)
Address offset: 0xEC
System reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
USART
1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
r
Bits 31:1 Reserved, must be kept at reset value.
Bit 0 USART1: USART1 interrupt request pending, combined with EXTI line 25
8.1.34
SYSCFG interrupt line 28 status register (SYSCFG_ITLINE28)
Address offset: 0xF0
System reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
LP
USART
UART2
2
r
r
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 LPUART2: LPUART2 interrupt request pending (EXTI line 31)
Bit 0 USART2: USART2 interrupt request pending (EXTI line 35)
RM0503 Rev 2
259/1325
263
System configuration controller (SYSCFG)
8.1.35
RM0503
SYSCFG interrupt line 29 status register (SYSCFG_ITLINE29)
Address offset: 0xF4
System reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
LP
USART
UART1
3
r
r
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 LPUART1: LPUART1 interrupt request pending (EXTI line 30)
Bit 0 USART3: USART3 interrupt request pending
8.1.36
SYSCFG interrupt line 30 status register (SYSCFG_ITLINE30)
Address offset: 0xF8
System reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
LP
USART
UART3
4
r
r
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 LPUART3: LPUART3 interrupt request pending (EXTI line 32)
Bit 0 USART4: USART4 interrupt request pending
8.1.37
SYSCFG interrupt line 31 status register (SYSCFG_ITLINE31)
Address offset: 0xFC
System reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
AES
RNG
r
r
260/1325
RM0503 Rev 2
0x90
SYSCFG_ITLINE4
RM0503 Rev 2
FLASH_ECC
Reset value
0
0
RCC
PVMOUT1
PVDOUT
0
0
Res.
TAMP
PVMOUT3
0
RTC
Reset value
FLASH_ITF
PVMOUT4
0
Res.
G4_IO3
G2_IO3
G2_IO1
0
0
0
0
0
0
Res.
WWDG
Res.
G6_IO1
0
Res.
0
Res.
0
G7_IO1
0
Res.
0
TSC_IOCTRL
0
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PVDL
SPL
CCL
0
0
0
Res.
Res.
SRAM2ER
ECCL
0
SRAM2BSY
BKPL
Res.
Res.
0
Res.
Res.
Res.
BKPF
Res.
Res.
Res.
Res.
Res.
Res.
Res.
I2C_PA9_FMP
I2C_PB8_FMP
I2C_PB7_FMP
I2C_PB6_FMP
PA11_RMP
MEM_MODE[1:0]
Res.
PA12_RMP
Res.
Res.
Res.
BOOSTEN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
I2C_PB9_FMP
Res.
Res.
I2C_PA10_FMP
0
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
SPF
Res.
Res.
Res.
Res.
0
Res.
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
I2C3_FMP
0
Res.
Res.
Res.
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
CRS
Reset value
Res.
Res.
Res.
Res.
Res.
Reserved
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reserved
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
Res.
Res.
Res.
SYSCFG_ITLINE3
Res.
0x8C
SYSCFG_ITLINE2
Res.
0x88
SYSCFG_ITLINE1
Res.
0x84
SYSCFG_ITLINE0
Res.
0x80
Res.
0x28 to
0x7F
SYSCFG_TSCCR
Res.
0x24
SYSCFG_SKR
Res.
0x20
SYSCFG_SCSR
Res.
0x1C
SYSCFG_CFGR2
Res.
0x18
Res.
0x04 to
0x17
SYSCFG_CFGR1
Res.
0x00
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Register
Res.
Offset
Res.
8.1.38
Res.
RM0503
System configuration controller (SYSCFG)
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 AES: AES interrupt request pending
Bit 0 RNG: RNG interrupt request pending
SYSCFG register map
The following table gives the SYSCFG register map and the reset values.
Table 41. SYSCFG register map and reset values
X X
Res.
KEY[7:0]
0
0
Reset value
0
0
0
0
0
261/1325
263
0xC8
SYSCFG_ITLINE18
262/1325
RM0503 Rev 2
DAC
TIM6
0
0
0
LPTIM2
TIM7
Reset value
TIM1_CC2
TIM1_CC1
0
0
Res.
TIM2
TIM1_UPD
TIM1_TRG
TIM1_CCU
DMA2_CH2
DMA2_CH1
DMA1_CH7
DMA1_CH6
DMA1_CH5
DMA1_CH4
DMAMUX
0
0
0
0
0
0
0
Res.
Res.
Res.
Res.
Res.
Res.
ADC
DMA2_CH3
0
COMP1
DMA2_CH4
0
COMP2
DMA2_CH5
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DMA1_CH2
Reset value
DMA1_CH3
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
Reset value
Reset value
Reset value
DMA1_CH1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
EXTI15
EXTI14
EXTI13
EXTI12
EXTI11
EXTI10
EXTI9
EXTI8
EXTI7
EXTI6
EXTI5
EXTI4
0
0
0
0
0
0
0
0
0
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
USB
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
EXTI2
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
EXTI3
Reset value
TIM3
TIM1_CC3
0
Res.
TIM1_BRK
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
EXTI0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
EXTI1
Reset value
Res.
Res.
TIM1_CC4
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
LPTIM1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
SYSCFG_ITLINE17
Res.
0xC4
SYSCFG_ITLINE16
Res.
0xC0
SYSCFG_ITLINE15
Res.
0xBC
SYSCFG_ITLINE14
Res.
0xB8
SYSCFG_ITLINE13
Res.
0xB4
SYSCFG_ITLINE12
Res.
0xB0
SYSCFG_ITLINE11
Res.
0xAC
SYSCFG_ITLINE10
Res.
0xA8
SYSCFG_ITLINE9
Res.
0xA4
SYSCFG_ITLINE8
Res.
0xA0
SYSCFG_ITLINE7
Res.
0x9C
SYSCFG_ITLINE6
Res.
0x98
SYSCFG_ITLINE5
Res.
0x94
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Register
Res.
Offset
Res.
System configuration controller (SYSCFG)
RM0503
Table 41. SYSCFG register map and reset values (continued)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0xFC
SYSCFG_ITLINE31
RM0503 Rev 2
Reset value
USART4
USART3
Reset value
0
0
RNG
USART2
Reset value
LPUART2
Res.
Res.
Res.
Res.
Res.
SPI3
SPI2
0
USART1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
LPUART1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
I2C3
I2C4
I2C2
0
0
Res.
SPI1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
TSC_EOA
TSC_MCE
0
LCD
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
Reset value
Reset value
Reset value
Reset value
I2C1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
LPUART3
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
LPTIM3
TIM15
0
TIM16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
AES
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
SYSCFG_ITLINE30
Res.
0xF8
SYSCFG_ITLINE29
Res.
0xF4
SYSCFG_ITLINE28
Res.
0xF0
SYSCFG_ITLINE27
Res.
0xEC
SYSCFG_ITLINE26
Res.
0xE8
SYSCFG_ITLINE25
Res.
0xE4
SYSCFG_ITLINE24
Res.
0xE0
SYSCFG_ITLINE23
Res.
0xDC
SYSCFG_ITLINE22
Res.
0xD8
SYSCFG_ITLINE21
Res.
0xD4
SYSCFG_ITLINE20
Res.
0xD0
SYSCFG_ITLINE19
Res.
0xCC
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Register
Res.
Offset
Res.
RM0503
System configuration controller (SYSCFG)
Table 41. SYSCFG register map and reset values (continued)
0
0
0
0
0
0
0
0
0
0
0
Refer to Section 2.2 on page 55 for the register boundary addresses.
263/1325
263
Direct memory access controller (DMA)
RM0503
9
Direct memory access controller (DMA)
9.1
Introduction
The direct memory access (DMA) controller is a bus master and system peripheral.
The DMA is used to perform programmable data transfers between memory-mapped
peripherals and/or memories, upon the control of an off-loaded CPU.
The DMA controller features a single AHB master architecture.
Refer to Section 9.3 for information on DMA implementation.
Each channel is dedicated to managing memory access requests from one or more
peripherals. DMA includes an arbiter for handling the priority between DMA requests.
9.2
DMA main features
•
Single AHB master
•
Peripheral-to-memory, memory-to-peripheral, memory-to-memory and peripheral-toperipheral data transfers
•
Access, as source and destination, to on-chip memory-mapped devices such as flash
memory, SRAM, and AHB and APB peripherals
•
All DMA channels independently configurable:
•
264/1325
–
Each channel is associated either with a DMA request signal coming from a
peripheral, or with a software trigger in memory-to-memory transfers. This
configuration is done by software.
–
Priority between the requests is programmable by software (four levels per
channel: very high, high, medium, low) and by hardware in case of equality (such
as request to channel 1 has priority over request to channel 2).
–
Transfer size of source and destination are independent (byte, half-word, word),
emulating packing and unpacking. Source and destination addresses must be
aligned on the data size.
–
Support of transfers from/to peripherals to/from memory with circular buffer
management
–
Programmable number of data to be transferred: 0 to 216 - 1
Generation of an interrupt request per channel. Each interrupt request is caused from
any of the three DMA events: transfer complete, half transfer, or transfer error.
RM0503 Rev 2
RM0503
Direct memory access controller (DMA)
9.3
DMA implementation
9.3.1
DMA
The devices incorporate one or two DMA controller instances. The following implementation
table shows the number of DMA channels for either instance. A dash indicates that the
instance is not implemented.
Table 42. DMA implementation
9.3.2
Number of channels
STM32U031xx
STM32U073xx
STM32U083xx
DMA1
7
7
DMA2
-
5
DMA request mapping
The DMA controller is connected to DMA requests from the AHB/APB peripherals through
the DMAMUX peripheral.
For the mapping of the different requests, refer to the DMAMUX section.
RM0503 Rev 2
265/1325
284
Direct memory access controller (DMA)
RM0503
9.4
DMA functional description
9.4.1
DMA block diagram
The DMA block diagram is shown in the figure below.
Figure 22. DMA block diagram
DMA
AHB master interface
32-bit AHB bus
AHB slave interface
32-bit AHB bus
Ch 1
Ch 2
...
Ch 7
dma_req [1..7]
dma_ack [1..7]
Arbiter
Interrupt
interface
dma_it[1..7]
MSv48187V1
The DMA controller performs direct memory transfer by sharing the AHB system bus with
other system masters. The bus matrix implements round-robin scheduling. DMA requests
may stop the CPU access to the system bus for a number of bus cycles, when CPU and
DMA target the same destination (memory or peripheral).
According to its configuration through the AHB slave interface, the DMA controller arbitrates
between the DMA channels and their associated received requests. The DMA controller
also schedules the DMA data transfers over the single AHB port master.
The DMA controller generates an interrupt per channel to the interrupt controller.
9.4.2
DMA pins and internal signals
Table 43. DMA internal input/output signals
266/1325
Signal name
Signal type
Description
dma_req[x]
Input
DMA channel x request
dma_ack[x]
Output
DMA channel x acknowledge
dma_it[x]
Output
DMA channel x interrupt
RM0503 Rev 2
RM0503
9.4.3
Direct memory access controller (DMA)
DMA transfers
The software configures the DMA controller at channel level, in order to perform a block
transfer, composed of a sequence of AHB bus transfers.
A DMA block transfer may be requested from a peripheral, or triggered by the software in
case of memory-to-memory transfer.
After an event, the following steps of a single DMA transfer occur:
1.
The peripheral sends a single DMA request signal to the DMA controller.
2.
The DMA controller serves the request, depending on the priority of the channel
associated to this peripheral request.
3.
As soon as the DMA controller grants the peripheral, an acknowledge is sent to the
peripheral by the DMA controller.
4.
The peripheral releases its request as soon as it gets the acknowledge from the DMA
controller.
5.
Once the request is de-asserted by the peripheral, the DMA controller releases the
acknowledge.
The peripheral may order a further single request and initiate another single DMA transfer.
The request/acknowledge protocol is used when a peripheral is either the source or the
destination of the transfer. For example, in case of memory-to-peripheral transfer, the
peripheral initiates the transfer by driving its single request signal to the DMA controller. The
DMA controller reads then a single data in the memory and writes this data to the peripheral.
For a given channel x, a DMA block transfer consists of a repeated sequence of:
•
•
a single DMA transfer, encapsulating two AHB transfers of a single data, over the DMA
AHB bus master:
–
a single data read (byte, half-word, or word) from the peripheral data register or a
location in the memory, addressed through an internal current peripheral/memory
address register.
The start address used for the first single transfer is the base address of the
peripheral or memory, and is programmed in the DMA_CPARx or DMA_CMARx
register.
–
a single data write (byte, half-word, or word) to the peripheral data register or a
location in the memory, addressed through an internal current peripheral/memory
address register.
The start address used for the first transfer is the base address of the peripheral or
memory, and is programmed in the DMA_CPARx or DMA_CMARx register.
post-decrementing of the programmed DMA_CNDTRx register
This register contains the remaining number of data items to transfer (number of AHB
‘read followed by write’ transfers).
This sequence is repeated until DMA_CNDTRx is null.
Note:
The AHB master bus source/destination address must be aligned with the programmed size
of the transferred single data to the source/destination.
RM0503 Rev 2
267/1325
284
Direct memory access controller (DMA)
9.4.4
RM0503
DMA arbitration
The DMA arbiter manages the priority between the different channels.
When an active channel x is granted by the arbiter (hardware requested or software
triggered), a single DMA transfer is issued (such as a AHB ‘read followed by write’ transfer
of a single data). Then, the arbiter considers again the set of active channels and selects the
one with the highest priority.
The priorities are managed in two stages:
•
•
software: priority of each channel is configured in the DMA_CCRx register, to one of
the four different levels:
–
very high
–
high
–
medium
–
low
hardware: if two requests have the same software priority level, the channel with the
lowest index gets priority. For example, channel 2 gets priority over channel 4.
When a channel x is programmed for a block transfer in memory-to-memory mode,
re arbitration is considered between each single DMA transfer of this channel x. Whenever
there is another concurrent active requested channel, the DMA arbiter automatically
alternates and grants the other highest-priority requested channel, which may be of lower
priority than the memory-to-memory channel.
9.4.5
DMA channels
Each channel may handle a DMA transfer between a peripheral register located at a fixed
address, and a memory address. The amount of data items to transfer is programmable.
The register that contains the amount of data items to transfer is decremented after each
transfer.
A DMA channel is programmed at block transfer level.
Programmable data sizes
The transfer sizes of a single data (byte, half-word, or word) to the peripheral and memory
are programmable through, respectively, the PSIZE[1:0] and MSIZE[1:0] fields of the
DMA_CCRx register.
Pointer incrementation
The peripheral and memory pointers may be automatically incremented after each transfer,
depending on the PINC and MINC bits of the DMA_CCRx register.
If the incremented mode is enabled (PINC or MINC set to 1), the address of the next
transfer is the address of the previous one incremented by 1, 2 or 4, depending on the data
size defined in PSIZE[1:0] or MSIZE[1:0]. The first transfer address is the one programmed
in the DMA_CPARx or DMA_CMARx register. During transfers, these registers keep the
initially programmed value. The current transfer addresses (in the current internal
peripheral/memory address register) are not accessible by software.
If the channel x is configured in non-circular mode, no DMA request is served after the last
data transfer (once the number of single data to transfer reaches zero). The DMA channel
268/1325
RM0503 Rev 2
RM0503
Direct memory access controller (DMA)
must be disabled in order to reload a new number of data items into the DMA_CNDTRx
register.
Note:
If the channel x is disabled, the DMA registers are not reset. The DMA channel registers
(DMA_CCRx, DMA_CPARx and DMA_CMARx) retain the initial values programmed during
the channel configuration phase.
In circular mode, after the last data transfer, the DMA_CNDTRx register is automatically
reloaded with the initially programmed value. The current internal address registers are
reloaded with the base address values from the DMA_CPARx and DMA_CMARx registers.
Channel configuration procedure
The following sequence is needed to configure a DMA channel x:
1.
Set the peripheral register address in the DMA_CPARx register.
The data is moved from/to this address to/from the memory after the peripheral event,
or after the channel is enabled in memory-to-memory mode.
2.
Set the memory address in the DMA_CMARx register.
The data is written to/read from the memory after the peripheral event or after the
channel is enabled in memory-to-memory mode.
3.
Configure the total number of data to transfer in the DMA_CNDTRx register.
After each data transfer, this value is decremented.
4.
Configure the parameters listed below in the DMA_CCRx register:
5.
–
the channel priority
–
the data transfer direction
–
the circular mode
–
the peripheral and memory incremented mode
–
the peripheral and memory data size
–
the interrupt enable at half and/or full transfer and/or transfer error
Activate the channel by setting the EN bit in the DMA_CCRx register.
A channel, as soon as enabled, may serve any DMA request from the peripheral connected
to this channel, or may start a memory-to-memory block transfer.
Note:
The two last steps of the channel configuration procedure may be merged into a single
access to the DMA_CCRx register, to configure and enable the channel.
Channel state and disabling a channel
A channel x in the active state is an enabled channel (read DMA_CCRx.EN = 1). An active
channel x is a channel that must have been enabled by the software (DMA_CCRx.EN set
to 1) and afterwards with no occurred transfer error (DMA_ISR.TEIFx = 0). In case there is a
transfer error, the channel is automatically disabled by hardware (DMA_CCRx.EN = 0).
RM0503 Rev 2
269/1325
284
Direct memory access controller (DMA)
RM0503
The three following use cases may happen:
•
Suspend and resume a channel
This corresponds to the two following actions:
–
An active channel is disabled by software (writing DMA_CCRx.EN = 0 whereas
DMA_CCRx.EN = 1).
–
The software enables the channel again (DMA_CCRx.EN set to 1) without
reconfiguring the other channel registers (such as DMA_CNDTRx, DMA_CPARx
and DMA_CMARx).
This case is not supported by the DMA hardware, that does not guarantee that the
remaining data transfers are performed correctly.
•
Stop and abort a channel
If the application does not need any more the channel, this active channel can be
disabled by software. The channel is stopped and aborted but the DMA_CNDTRx
register content may not correctly reflect the remaining data transfers versus the
aborted source and destination buffer/register.
•
Abort and restart a channel
This corresponds to the software sequence: disable an active channel, then
reconfigure the channel and enable it again.
This is supported by the hardware if the following conditions are met:
–
The application guarantees that, when the software is disabling the channel, a
DMA data transfer is not occurring at the same time over its master port. For
example, the application can first disable the peripheral in DMA mode, in order to
ensure that there is no pending hardware DMA request from this peripheral.
–
The software must operate separated write accesses to the same DMA_CCRx
register: First disable the channel. Second reconfigure the channel for a next block
transfer including the DMA_CCRx if a configuration change is needed. There are
read-only DMA_CCRx register fields when DMA_CCRx.EN=1. Finally enable
again the channel.
When a channel transfer error occurs, the EN bit of the DMA_CCRx register is cleared by
hardware. This EN bit cannot be set again by software to reactivate the channel x, until the
TEIFx bit of the DMA_ISR register is set.
Circular mode (in memory-to-peripheral/peripheral-to-memory transfers)
The circular mode is available to handle circular buffers and continuous data flows (such as
ADC scan mode). This feature is enabled using the CIRC bit in the DMA_CCRx register.
Note:
The circular mode must not be used in memory-to-memory mode. Before enabling a
channel in circular mode (CIRC = 1), the software must clear the MEM2MEM bit of the
DMA_CCRx register. When the circular mode is activated, the amount of data to transfer is
automatically reloaded with the initial value programmed during the channel configuration
phase, and the DMA requests continue to be served.
In order to stop a circular transfer, the software needs to stop the peripheral from generating
DMA requests (such as quit the ADC scan mode), before disabling the DMA channel.
The software must explicitly program the DMA_CNDTRx value before starting/enabling a
transfer, and after having stopped a circular transfer.
270/1325
RM0503 Rev 2
RM0503
Direct memory access controller (DMA)
Memory-to-memory mode
The DMA channels may operate without being triggered by a request from a peripheral. This
mode is called memory-to-memory mode, and is initiated by software.
If the MEM2MEM bit in the DMA_CCRx register is set, the channel, if enabled, initiates
transfers. The transfer stops once the DMA_CNDTRx register reaches zero.
Note:
The memory-to-memory mode must not be used in circular mode. Before enabling a
channel in memory-to-memory mode (MEM2MEM = 1), the software must clear the CIRC
bit of the DMA_CCRx register.
Peripheral-to-peripheral mode
Any DMA channel can operate in peripheral-to-peripheral mode:
•
when the hardware request from a peripheral is selected to trigger the DMA channel
This peripheral is the DMA initiator and paces the data transfer from/to this peripheral
to/from a register belonging to another memory-mapped peripheral (this one being not
configured in DMA mode).
•
when no peripheral request is selected and connected to the DMA channel
The software configures a register-to-register transfer by setting the MEM2MEM bit of
the DMA_CCRx register.
Programming transfer direction, assigning source/destination
The value of the DIR bit of the DMA_CCRx register sets the direction of the transfer, and
consequently, it identifies the source and the destination, regardless the source/destination
type (peripheral or memory):
•
•
DIR = 1 defines typically a memory-to-peripheral transfer. More generally, if DIR = 1:
–
The source attributes are defined by the DMA_MARx register, the MSIZE[1:0]
field, and MINC bit of the DMA_CCRx register.
Regardless of their usual naming, these ‘memory’ register, field, and bit are used
to define the source peripheral in peripheral-to-peripheral mode.
–
The destination attributes are defined by the DMA_PARx register, the PSIZE[1:0]
field and the PINC bit of the DMA_CCRx register.
Regardless of their usual naming, these ‘peripheral’ register, field, and bit are used
to define the destination memory in memory-to-memory mode.
DIR = 0 defines typically a peripheral-to-memory transfer. More generally, if DIR = 0:
–
The source attributes are defined by the DMA_PARx register, the PSIZE[1:0] field
and the PINC bit of the DMA_CCRx register.
Regardless of their usual naming, these ‘peripheral’ register, field, and bit are used
to define the source memory in memory-to-memory mode
–
The destination attributes are defined by the DMA_MARx register, the
MSIZE[1:0] field and the MINC bit of the DMA_CCRx register.
Regardless of their usual naming, these ‘memory’ register, field and bit are used to
define the destination peripheral in peripheral-to-peripheral mode.
RM0503 Rev 2
271/1325
284
Direct memory access controller (DMA)
9.4.6
RM0503
DMA data width, alignment, and endianness
When PSIZE[1:0] and MSIZE[1:0] are not equal, the DMA controller performs some data
alignments as described in the table below.
Table 44. Programmable data width and endian behavior (when PINC = MINC = 1)
Source
port
width
(MSIZE
if
DIR = 1,
else
PSIZE)
Destinat
ion port
width
(PSIZE
if
DIR = 1,
else
MSIZE)
Number
of data
items to
transfer
(NDT)
8
8
4
@0x0 / B0
@0x1 / B1
@0x2 / B2
@0x3 / B3
1: read B0[7:0] @0x0 then write B0[7:0] @0x0
2: read B1[7:0] @0x1 then write B1[7:0] @0x1
3: read B2[7:0] @0x2 then write B2[7:0] @0x2
4: read B3[7:0] @0x3 then write B3[7:0] @0x3
@0x0 / B0
@0x1 / B1
@0x2 / B2
@0x3 / B3
8
16
4
@0x0 / B0
@0x1 / B1
@0x2 / B2
@0x3 / B3
1: read B0[7:0] @0x0 then write 00B0[15:0] @0x0
2: read B1[7:0] @0x1 then write 00B1[15:0] @0x2
3: read B2[7:0] @0x2 then write 00B2[15:0] @0x4
4: read B3[7:0] @0x3 then write 00B3[15:0] @0x6
@0x0 / 00B0
@0x2 / 00B1
@0x4 / 00B2
@0x6 / 00B3
8
32
4
@0x0 / B0
@0x1 / B1
@0x2 / B2
@0x3 / B3
1: read B0[7:0] @0x0 then write 000000B0[31:0] @0x0
2: read B1[7:0] @0x1 then write 000000B1[31:0] @0x4
3: read B2[7:0] @0x2 then write 000000B2[31:0] @0x8
4: read B3[7:0] @0x3 then write 000000B3[31:0] @0xC
@0x0 / 000000B0
@0x4 / 000000B1
@0x8 / 000000B2
@0xC / 000000B3
16
8
4
@0x0 / B1B0
@0x2 / B3B2
@0x4 / B5B4
@0x6 / B7B6
1: read B1B0[15:0] @0x0 then write B0[7:0] @0x0
2: read B3B2[15:0] @0x2 then write B2[7:0] @0x1
3: read B5B4[15:0] @0x4 then write B4[7:0] @0x2
4: read B7B6[15:0] @0x6 then write B6[7:0] @0x3
@0x0 / B0
@0x1 / B2
@0x2 / B4
@0x3 / B6
16
16
4
@0x0 / B1B0
@0x2 / B3B2
@0x4 / B5B4
@0x6 / B7B6
1: read B1B0[15:0] @0x0 then write B1B0[15:0] @0x0
2: read B3B2[15:0] @0x2 then write B3B2[15:0] @0x2
3: read B5B4[15:0] @0x4 then write B5B4[15:0] @0x4
4: read B7B6[15:0] @0x6 then write B7B6[15:0] @0x6
@0x0 / B1B0
@0x2 / B3B2
@0x4 / B5B4
@0x6 / B7B6
16
32
4
@0x0 / B1B0
@0x2 / B3B2
@0x4 / B5B4
@0x6 / B7B6
1: read B1B0[15:0] @0x0 then write 0000B1B0[31:0] @0x0
2: read B3B2[15:0] @0x2 then write 0000B3B2[31:0] @0x4
3: read B5B4[15:0] @0x4 then write 0000B5B4[31:0] @0x8
4: read B7B6[15:0] @0x6 then write 0000B7B6[31:0] @0xC
@0x0 / 0000B1B0
@0x4 / 0000B3B2
@0x8 / 0000B5B4
@0xC / 0000B7B6
32
8
4
@0x0 / B3B2B1B0
@0x4 / B7B6B5B4
@0x8 / BBBAB9B8
@0xC / BFBEBDBC
1: read B3B2B1B0[31:0] @0x0 then write B0[7:0] @0x0
2: read B7B6B5B4[31:0] @0x4 then write B4[7:0] @0x1
3: read BBBAB9B8[31:0] @0x8 then write B8[7:0] @0x2
4: read BFBEBDBC[31:0] @0xC then write BC[7:0] @0x3
@0x0 / B0
@0x1 / B4
@0x2 / B8
@0x3 / BC
32
16
4
@0x0 / B3B2B1B0
@0x4 / B7B6B5B4
@0x8 / BBBAB9B8
@0xC / BFBEBDBC
1: read B3B2B1B0[31:0] @0x0 then write B1B0[15:0] @0x0
2: read B7B6B5B4[31:0] @0x4 then write B5B4[15:0] @0x2
3: read BBBAB9B8[31:0] @0x8 then write B9B8[15:0] @0x4
4: read BFBEBDBC[31:0] @0xC then write BDBC[15:0] @0x6
@0x0 / B1B0
@0x2 / B5B4
@0x4 / B9B8
@0x6 / BDBC
32
32
4
@0x0 / B3B2B1B0
@0x4 / B7B6B5B4
@0x8 / BBBAB9B8
@0xC / BFBEBDBC
1: read B3B2B1B0[31:0] @0x0 then write B3B2B1B0[31:0] @0x0
2: read B7B6B5B4[31:0] @0x4 then write B7B6B5B4[31:0] @0x4
3: read BBBAB9B8[31:0] @0x8 then write BBBAB9B8[31:0] @0x8
4: read BFBEBDBC[31:0] @0xC then write BFBEBDBC[31:0] @0xC
@0x0 / B3B2B1B0
@0x4 / B7B6B5B4
@0x8 / BBBAB9B8
@0xC / BFBEBDBC
272/1325
Source content:
address / data
(DMA_CMARx if
DIR = 1, else
DMA_CPARx)
DMA transfers
RM0503 Rev 2
Destination
content:
address / data
(DMA_CPARx if
DIR = 1, else
DMA_CMARx)
RM0503
Direct memory access controller (DMA)
Addressing AHB peripherals not supporting byte/half-word write transfers
When the DMA controller initiates an AHB byte or half-word write transfer, the data are
duplicated on the unused lanes of the AHB master 32-bit data bus (HWDATA[31:0]).
When the AHB slave peripheral does not support byte or half-word write transfers and does
not generate any error, the DMA controller writes the 32 HWDATA bits as shown in the two
examples below:
•
To write the half-word 0xABCD, the DMA controller sets the HWDATA bus to
0xABCDABCD with a half-word data size (HSIZE = HalfWord in the AHB master bus).
•
To write the byte 0xAB, the DMA controller sets the HWDATA bus to 0xABABABAB
with a byte data size (HSIZE = Byte in the AHB master bus).
Assuming the AHB/APB bridge is an AHB 32-bit slave peripheral that does not take into
account the HSIZE data, any AHB byte or half-word transfer is changed into a 32-bit APB
transfer as described below:
9.4.7
•
An AHB byte write transfer of 0xB0 to one of the 0x0, 0x1, 0x2, or 0x3 addresses, is
converted to an APB word write transfer of 0xB0B0B0B0 to the 0x0 address.
•
An AHB half-word write transfer of 0xB1B0 to the 0x0 or 0x2 addresses is converted to
an APB word write transfer of 0xB1B0B1B0 to the 0x0 address.
DMA error management
A DMA transfer error is generated when reading from or writing to a reserved address
space. When a DMA transfer error occurs during a DMA read or write access, the faulty
channel x is automatically disabled through a hardware clear of its EN bit in the
corresponding DMA_CCRx register.
The TEIFx bit of the DMA_ISR register is set. An interrupt is then generated if the TEIE bit of
the DMA_CCRx register is set.
The EN bit of the DMA_CCRx register cannot be set again by software (channel x
reactivated) until the TEIFx bit of the DMA_ISR register is cleared (by setting the CTEIFx bit
of the DMA_IFCR register).
When the software is notified with a transfer error over a channel, which involves a
peripheral, the software has first to stop this peripheral in DMA mode, in order to disable any
pending or future DMA request. Then software may normally reconfigure both DMA and the
peripheral in DMA mode for a new transfer.
RM0503 Rev 2
273/1325
284
Direct memory access controller (DMA)
9.5
RM0503
DMA interrupts
An interrupt can be generated on a half transfer, transfer complete or transfer error for each
DMA channel x. Separate interrupt enable bits are available for flexibility.
Table 45. DMA interrupt requests
Event flag
Interrupt
enable bit
Half transfer on channel x
HTIFx
HTIEx
Transfer complete on channel x
TCIFx
TCIEx
Transfer error on channel x
TEIFx
TEIEx
Half transfer or transfer complete or transfer error on channel x
GIFx
-
Interrupt request
Channel x interrupt
9.6
Interrupt event
DMA registers
Refer to Section 1.2 for a list of abbreviations used in register descriptions.
The DMA registers have to be accessed by words (32-bit).
9.6.1
DMA interrupt status register (DMA_ISR)
Address offset: 0x00
Reset value: 0x0000 0000
Every status bit is cleared by hardware when the software sets the corresponding clear bit
or the corresponding global clear bit CGIFx, in the DMA_IFCR register.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
TEIF7
HTIF7
TCIF7
GIF7
TEIF6
HTIF6
TCIF6
GIF6
TEIF5
HTIF5
TCIF5
GIF5
r
r
r
r
r
r
r
r
r
r
r
r
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TEIF4
HTIF4
TCIF4
GIF4
TEIF3
HTIF3
TCIF3
GIF3
TEIF2
HTIF2
TCIF2
GIF2
TEIF1
HTIF1
TCIF1
GIF1
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
Bits 31:28 Reserved, must be kept at reset value.
Bit 27 TEIF7: Transfer error (TE) flag for channel 7
0: No TE event
1: A TE event occurred.
Bit 26 HTIF7: Half transfer (HT) flag for channel 7
0: No HT event
1: An HT event occurred.
Bit 25 TCIF7: Transfer complete (TC) flag for channel 7
0: No TC event
1: A TC event occurred.
Bit 24 GIF7: Global interrupt flag for channel 7
0: No TE, HT, or TC event
1: A TE, HT, or TC event occurred.
274/1325
RM0503 Rev 2
RM0503
Direct memory access controller (DMA)
Bit 23 TEIF6: Transfer error (TE) flag for channel 6
0: No TE event
1: A TE event occurred.
Bit 22 HTIF6: Half transfer (HT) flag for channel 6
0: No HT event
1:An HT event occurred.
Bit 21 TCIF6: Transfer complete (TC) flag for channel 6
0: No TC event
1: A TC event occurred.
Bit 20 GIF6: Global interrupt flag for channel 6
0: No TE, HT, or TC event
1: A TE, HT, or TC event occurred.
Bit 19 TEIF5: Transfer error (TE) flag for channel 5
0: No TE event
1: A TE event occurred.
Bit 18 HTIF5: Half transfer (HT) flag for channel 5
0: No HT event
1: An HT event occurred.
Bit 17 TCIF5: Transfer complete (TC) flag for channel 5
0: No TC event
1: A TC event occurred.
Bit 16 GIF5: global interrupt flag for channel 5
0: No TE, HT, or TC event
1: A TE, HT, or TC event occurred.
Bit 15 TEIF4: Transfer error (TE) flag for channel 4
0: No TE event
1: A TE event occurred.
Bit 14 HTIF4: Half transfer (HT) flag for channel 4
0: No HT event
1: An HT event occurred.
Bit 13 TCIF4: Transfer complete (TC) flag for channel 4
0: No TC event
1: A TC event occurred.
Bit 12 GIF4: global interrupt flag for channel 4
0: No TE, HT, or TC event
1: A TE, HT, or TC event occurred.
Bit 11 TEIF3: Transfer error (TE) flag for channel 3
0: No TE event
1: A TE event occurred.
Bit 10 HTIF3: Half transfer (HT) flag for channel 3
0: No HT event
1: An HT event occurred.
Bit 9 TCIF3: Transfer complete (TC) flag for channel 3
0: No TC event
1: A TC event occurred.
RM0503 Rev 2
275/1325
284
Direct memory access controller (DMA)
RM0503
Bit 8 GIF3: Global interrupt flag for channel 3
0: No TE, HT, or TC event
1: A TE, HT, or TC event occurred.
Bit 7 TEIF2: Transfer error (TE) flag for channel 2
0: No TE event
1: A TE event occurred.
Bit 6 HTIF2: Half transfer (HT) flag for channel 2
0: No HT event
1: An HT event occurred.
Bit 5 TCIF2: Transfer complete (TC) flag for channel 2
0: No TC event
1: A TC event occurred.
Bit 4 GIF2: Global interrupt flag for channel 2
0: No TE, HT, or TC event
1: A TE, HT, or TC event occurred.
Bit 3 TEIF1: Transfer error (TE) flag for channel 1
0: No TE event
1: A TE event occurred.
Bit 2 HTIF1: Half transfer (HT) flag for channel 1
0: No HT event
1: An HT event occurred.
Bit 1 TCIF1: Transfer complete (TC) flag for channel 1
0: No TC event
1: A TC event occurred.
Bit 0 GIF1: Global interrupt flag for channel 1
0: No TE, HT, or TC event
1: A TE, HT, or TC event occurred.
276/1325
RM0503 Rev 2
RM0503
Direct memory access controller (DMA)
9.6.2
DMA interrupt flag clear register (DMA_IFCR)
Address offset: 0x04
Reset value: 0x0000 0000
Setting the global clear bit CGIFx of the channel x in this DMA_IFCR register, causes the
DMA hardware to clear the corresponding GIFx bit and any individual flag among TEIFx,
HTIFx, TCIFx, in the DMA_ISR register.
Setting any individual clear bit among CTEIFx, CHTIFx, CTCIFx in this DMA_IFCR register,
causes the DMA hardware to clear the corresponding individual flag and the global flag
GIFx in the DMA_ISR register, provided that none of the two other individual flags is set.
Writing 0 into any flag clear bit has no effect.
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
27
26
25
24
23
22
21
20
19
18
17
16
CTEIF7 CHTIF7 CTCIF7 CGIF7 CTEIF6 CHTIF6 CTCIF6 CGIF6 CTEIF5 CHTIF5 CTCIF5 CGIF5
w
w
w
w
w
w
w
w
w
w
w
w
11
10
9
8
7
6
5
4
3
2
1
0
CTEIF4 CHTIF4 CTCIF4 CGIF4 CTEIF3 CHTIF3 CTCIF3 CGIF3 CTEIF2 CHTIF2 CTCIF2 CGIF2 CTEIF1 CHTIF1 CTCIF1 CGIF1
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
Bits 31:28 Reserved, must be kept at reset value.
Bit 27 CTEIF7: Transfer error flag clear for channel 7
Bit 26 CHTIF7: Half transfer flag clear for channel 7
Bit 25 CTCIF7: Transfer complete flag clear for channel 7
Bit 24 CGIF7: Global interrupt flag clear for channel 7
Bit 23 CTEIF6: Transfer error flag clear for channel 6
Bit 22 CHTIF6: Half transfer flag clear for channel 6
Bit 21 CTCIF6: Transfer complete flag clear for channel 6
Bit 20 CGIF6: Global interrupt flag clear for channel 6
Bit 19 CTEIF5: Transfer error flag clear for channel 5
Bit 18 CHTIF5: Half transfer flag clear for channel 5
Bit 17 CTCIF5: Transfer complete flag clear for channel 5
Bit 16 CGIF5: Global interrupt flag clear for channel 5
Bit 15 CTEIF4: Transfer error flag clear for channel 4
Bit 14 CHTIF4: Half transfer flag clear for channel 4
Bit 13 CTCIF4: Transfer complete flag clear for channel 4
Bit 12 CGIF4: Global interrupt flag clear for channel 4
Bit 11 CTEIF3: Transfer error flag clear for channel 3
Bit 10 CHTIF3: Half transfer flag clear for channel 3
Bit 9 CTCIF3: Transfer complete flag clear for channel 3
Bit 8 CGIF3: Global interrupt flag clear for channel 3
Bit 7 CTEIF2: Transfer error flag clear for channel 2
RM0503 Rev 2
277/1325
284
Direct memory access controller (DMA)
RM0503
Bit 6 CHTIF2: Half transfer flag clear for channel 2
Bit 5 CTCIF2: Transfer complete flag clear for channel 2
Bit 4 CGIF2: Global interrupt flag clear for channel 2
Bit 3 CTEIF1: Transfer error flag clear for channel 1
Bit 2 CHTIF1: Half transfer flag clear for channel 1
Bit 1 CTCIF1: Transfer complete flag clear for channel 1
Bit 0 CGIF1: Global interrupt flag clear for channel 1
9.6.3
DMA channel x configuration register (DMA_CCRx)
Address offset: 0x08 + 0x14 * (x - 1), (x = 1 to 7)
Reset value: 0x0000 0000
The register fields/bits MEM2MEM, PL[1:0], MSIZE[1:0], PSIZE[1:0], MINC, PINC, and DIR
are read-only when EN = 1.
The states of MEM2MEM and CIRC bits must not be both high at the same time.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
MEM2
MEM
MINC
PINC
CIRC
DIR
TEIE
HTIE
TCIE
EN
rw
rw
rw
rw
rw
rw
rw
rw
rw
PL[1:0]
rw
rw
MSIZE[1:0]
PSIZE[1:0]
rw
rw
rw
rw
Bits 31:15 Reserved, must be kept at reset value.
Bit 14 MEM2MEM: Memory-to-memory mode
0: Disabled
1: Enabled
Note: This bit is set and cleared by software. It must not be written when the channel is
enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).
Bits 13:12 PL[1:0]: Priority level
00: Low
01: Medium
10: High
11: Very high
Note: This bitfield is set and cleared by software. It must not be written when the channel is
enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).
278/1325
RM0503 Rev 2
RM0503
Direct memory access controller (DMA)
Bits 11:10 MSIZE[1:0]: Memory size
Defines the data size of each DMA transfer to the identified memory.
In memory-to-memory mode, this bitfield identifies the memory source if DIR = 1 and the
memory destination if DIR = 0.
In peripheral-to-peripheral mode, this bitfield identifies the peripheral source if DIR = 1 and
the peripheral destination if DIR = 0.
00: 8 bits
01: 16 bits
10: 32 bits
11: Reserved
Note: This bitfield is set and cleared by software. It must not be written when the channel is
enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).
Bits 9:8 PSIZE[1:0]: Peripheral size
Defines the data size of each DMA transfer to the identified peripheral.
In memory-to-memory mode, this bitfield identifies the memory destination if DIR = 1 and the
memory source if DIR = 0.
In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination if DIR = 1
and the peripheral source if DIR = 0.
00: 8 bits
01: 16 bits
10: 32 bits
11: Reserved
Note: This bitfield is set and cleared by software. It must not be written when the channel is
enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).
Bit 7 MINC: Memory increment mode
Defines the increment mode for each DMA transfer to the identified memory.
In memory-to-memory mode, this bit identifies the memory source if DIR = 1 and the memory
destination if DIR = 0.
In peripheral-to-peripheral mode, this bit identifies the peripheral source if DIR = 1 and the
peripheral destination if DIR = 0.
0: Disabled
1: Enabled
Note: This bit is set and cleared by software. It must not be written when the channel is
enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).
Bit 6 PINC: Peripheral increment mode
Defines the increment mode for each DMA transfer to the identified peripheral.
n memory-to-memory mode, this bit identifies the memory destination if DIR = 1 and the
memory source if DIR = 0.
In peripheral-to-peripheral mode, this bit identifies the peripheral destination if DIR = 1 and
the peripheral source if DIR = 0.
0: Disabled
1: Enabled
Note: This bit is set and cleared by software. It must not be written when the channel is
enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).
Bit 5 CIRC: Circular mode
0: Disabled
1: Enabled
Note: This bit is set and cleared by software. It must not be written when the channel is
enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1).
RM0503 Rev 2
279/1325
284
Direct memory access controller (DMA)
RM0503
Bit 4 DIR: Data transfer direction
This bit must be set only in memory-to-peripheral and peripheral-to-memory modes.
0: Read from peripheral
–
Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register.
This is still valid in a memory-to-memory mode.
–
Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx
register. This is still valid in a peripheral-to-peripheral mode.
1: Read from memory
–
Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx
register. This is still valid in a memory-to-memory mode.
–
Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register.
This is still valid in a peripheral-to-peripheral mode.
Note: This bit is set and cleared by software. It must not be written when the channel is
enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).
Bit 3 TEIE: Transfer error interrupt enable
0: Disabled
1: Enabled
Note: This bit is set and cleared by software. It must not be written when the channel is
enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1).
Bit 2 HTIE: Half transfer interrupt enable
0: Disabled
1: Enabled
Note: This bit is set and cleared by software. It must not be written when the channel is
enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1).
Bit 1 TCIE: Transfer complete interrupt enable
0: Disabled
1: Enabled
Note: This bit is set and cleared by software. It must not be written when the channel is
enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1).
Bit 0 EN: Channel enable
When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again
by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared
(by setting the CTEIFx bit of the DMA_IFCR register).
0: Disabled
1: Enabled
Note: This bit is set and cleared by software.
280/1325
RM0503 Rev 2
RM0503
Direct memory access controller (DMA)
9.6.4
DMA channel x number of data to transfer register (DMA_CNDTRx)
Address offset: 0x0C + 0x14 * (x - 1), (x = 1 to 7)
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
NDT[15:0]
rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 NDT[15:0]: Number of data to transfer (0 to 216 - 1)
This bitfield is updated by hardware when the channel is enabled:
–
It is decremented after each single DMA ‘read followed by write’ transfer, indicating
the remaining amount of data items to transfer.
–
It is kept at zero when the programmed amount of data to transfer is reached, if the
channel is not in circular mode (CIRC = 0 in the DMA_CCRx register).
–
It is reloaded automatically by the previously programmed value, when the transfer
is complete, if the channel is in circular mode (CIRC = 1).
If this bitfield is zero, no transfer can be served whatever the channel status (enabled or not).
Note: This bitfield is set and cleared by software. It must not be written when the channel is
enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).
9.6.5
DMA channel x peripheral address register (DMA_CPARx)
Address offset: 0x10 + 0x14 * (x - 1), (x = 1 to 7)
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
PA[31:16]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
PA[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
RM0503 Rev 2
281/1325
284
Direct memory access controller (DMA)
RM0503
Bits 31:0 PA[31:0]: Peripheral address
It contains the base address of the peripheral data register from/to which the data is
read/written.
When PSIZE[1:0] = 01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned
to a half-word address.
When PSIZE[1:0] = 10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically
aligned to a word address.
In memory-to-memory mode, this bitfield identifies the memory destination address if DIR = 1
and the memory source address if DIR = 0.
In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination address if
DIR = 1 and the peripheral source address if DIR = 0.
Note: This bitfield is set and cleared by software. It must not be written when the channel is
enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1).
9.6.6
DMA channel x memory address register (DMA_CMARx)
Address offset: 0x14 + 0x14 * (x - 1), (x = 1 to 7)
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
MA[31:16]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
MA[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:0 MA[31:0]: Peripheral address
It contains the base address of the memory from/to which the data is read/written.
When MSIZE[1:0] = 01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned
to a half-word address.
When MSIZE[1:0] = 10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically
aligned to a word address.
In memory-to-memory mode, this bitfield identifies the memory source address if DIR = 1 and
the memory destination address if DIR = 0.
In peripheral-to-peripheral mode, this bitfield identifies the peripheral source address if
DIR = 1 and the peripheral destination address if DIR = 0.
Note: This bitfield is set and cleared by software. It must not be written when the channel is
enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1).
9.6.7
DMA register map
282/1325
HTIF7
TCIF7
GIF7
TEIF6
HTIF6
TCIF6
GIF6
TEIF5
HTIF5
TCIF5
GIF5
TEIF4
HTIF4
TCIF4
GIF4
TEIF3
HTIF3
TCIF3
GIF3
TEIF2
HTIF2
TCIF2
GIF2
TEIF1
HTIF1
TCIF1
GIF1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CHTIF7
CTCIF7
CGIF7
CTEIF6
CHTIF6
CTCIF6
CGIF6
CTEIF5
CHTIF5
CTCIF5
CGIF5
CTEIF4
CHTIF4
CTCIF4
CGIF4
CTEIF3
CHTIF3
CTCIF3
CGIF3
CTEIF2
CHTIF2
CTCIF2
CGIF2
CTEIF1
CHTIF1
CTCIF1
CGIF1
Res.
Res.
TEIF7
Reset value
Res.
DMA_IFCR
Res.
0x004
Res.
Reset value
CTEIF7
Res.
DMA_ISR
Res.
0x000
Res.
Offset Register name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 46. DMA register map and reset values
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RM0503 Rev 2
RM0503
Direct memory access controller (DMA)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PSIZE[1:0]
MSIZE[1:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CIRC
DIR
TEIE
HTIE
TCIE
EN
0
PINC
PSIZE[1:0]
PL[1:0]
0
MSIZE[1:0]
MEM2MEM
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
NDTR[15:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MA[31:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Res.
CIRC
DIR
TEIE
HTIE
TCIE
EN
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CIRC
DIR
TEIE
HTIE
TCIE
EN
0
PINC
NDTR[15:0]
MINC
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
PINC
0
PSIZE[1:0]
PL[1:0]
0
MSIZE[1:0]
MEM2MEM
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reserved.
0
0
0
0
0
0
0
0
0
0
0
0
PA[31:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MA[31:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RM0503 Rev 2
0
PSIZE[1:0]
0
MSIZE[1:0]
PL[1:0]
Res.
MEM2MEM
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reserved.
Res.
Reserved
DMA_CCR5
0
NDTR[15:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
0x058
0
MINC
0
DMA_CMAR4
Reset value
0
0
0
Res.
0x054
0
PA[31:0]
Res.
0x050
0
EN
0
DMA_CPAR4
Reset value
0
TCIE
0
Reset value
0x04C
0
Reserved.
Res.
0x048
0
0
Reset value
DMA_CNDTR4
0
HTIE
0
Reserved
DMA_CCR4
0
DIR
0
Res.
0x044
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
DMA_CMAR3
Reset value
0
TEIE
0
Res.
0x040
0
CIRC
0
Res.
0x03C
0
PINC
0
DMA_CPAR3
Reset value
0
MINC
0
Reset value
0x038
0
MA[31:0]
Res.
0x034
0
0
Reset value
DMA_CNDTR3
0
PL[1:0]
0
Reserved
DMA_CCR3
0
MEM2MEM
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
0x030
0
DMA_CMAR2
Reset value
0
PA[31:0]
Res.
0x02C
0
0
0
Res.
0x028
0
Reserved.
DMA_CPAR2
Reset value
EN
0
Reset value
0x024
0
MA[31:0]
Res.
DMA_CNDTR2
TCIE
0
Reset value
0x020
HTIE
0
Reserved
DMA_CCR2
DIR
0
Res.
Reset value
TEIE
0
Res.
0x01C
0
DMA_CMAR1
Res.
0x018
0
PA[31:0]
Res.
0x014
Reset value
0
NDTR[15:0]
0
Res.
0x010
0
MINC
Reset value
DMA_CPAR1
PSIZE[1:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DMA_CNDTR1
Res.
0x00C
0
PINC
0
CIRC
0
MINC
0
Reset value
MSIZE[1:0]
PL[1:0]
Res.
MEM2MEM
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DMA_CCR1
Res.
0x008
Res.
Offset Register name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 46. DMA register map and reset values (continued)
0
283/1325
284
Direct memory access controller (DMA)
RM0503
Res.
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PINC
CIRC
DIR
TEIE
HTIE
TCIE
EN
PSIZE[1:0]
MSIZE[1:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PSIZE[1:0]
EN
0
TCIE
0
HTIE
0
0
DIR
0
TEIE
0
CIRC
0
PINC
0
MSIZE[1:0]
PL[1:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
NDTR[15:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MA[31:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Refer to Section 2.2 for the register boundary addresses.
284/1325
0
PA[31:0]
DMA_CMAR7
Reset value
0
MEM2MEM
0x08C
0
0
0
DMA_CPAR7
Reset value
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
0x088
0
PL[1:0]
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DMA_CNDTR7
0
NDTR[15:0]
Reset value
0x084
0
Reserved.
Res.
Reserved
DMA_CCR7
0
MA[31:0]
Res.
Reset value
0
MINC
0
Res.
0x080
0
DMA_CMAR6
Res.
0x07C
0
PA[31:0]
Res.
0x078
0
0
0
DMA_CPAR6
Reset value
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
0x074
0
MEM2MEM
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0x070
0
0
Reset value
DMA_CNDTR6
0
Reserved.
Res.
Reserved
DMA_CCR6
0
Res.
Reset value
0
MA[31:0]
Res.
0x06C
0
DMA_CMAR5
Res.
0x068
Reset value
0
PA[31:0]
Res.
0x064
0
DMA_CPAR5
Res.
0x060
NDTR[15:0]
MINC
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DMA_CNDTR5
Res.
0x05C
Res.
Offset Register name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 46. DMA register map and reset values (continued)
RM0503 Rev 2
RM0503
DMA request multiplexer (DMAMUX)
10
DMA request multiplexer (DMAMUX)
10.1
Introduction
A peripheral indicates a request for DMA transfer by setting its DMA request signal. The
DMA request is pending until served by the DMA controller that generates a DMA
acknowledge signal, and the corresponding DMA request signal is deasserted.
In this document, the set of control signals required for the DMA request/acknowledge
protocol is not explicitly shown or described, and it is referred to as DMA request line.
The DMAMUX request multiplexer enables routing a DMA request line between the
peripherals and the DMA controllers of the product. The routing function is ensured by a
programmable multi-channel DMA request line multiplexer. Each channel selects a unique
DMA request line, unconditionally or synchronously with events from its DMAMUX
synchronization inputs. The DMAMUX may also be used as a DMA request generator from
programmable events on its input trigger signals.
The number of DMAMUX instances and their main characteristics are specified in
Section 10.3.1.
The assignment of DMAMUX request multiplexer inputs to the DMA request lines from
peripherals and to the DMAMUX request generator outputs, the assignment of DMAMUX
request multiplexer outputs to DMA controller channels, and the assignment of DMAMUX
synchronizations and trigger inputs to internal and external signals depend upon product
implementation. They are detailed in Section 10.3.2.
RM0503 Rev 2
285/1325
300
DMA request multiplexer (DMAMUX)
10.2
RM0503
DMAMUX main features
•
Up to 12-channel programmable DMA request line multiplexer output
•
4-channel DMA request generator
•
23 trigger inputs to DMA request generator
•
23 synchronization inputs
•
Per DMA request generator channel:
•
–
DMA request trigger input selector
–
DMA request counter
–
Event overrun flag for selected DMA request trigger input
Per DMA request line multiplexer channel output:
–
Up to 76 input DMA request lines from peripherals
–
One DMA request line output
–
Synchronization input selector
–
DMA request counter
–
Event overrun flag for selected synchronization input
–
One event output, for DMA request chaining
10.3
DMAMUX implementation
10.3.1
DMAMUX instantiation
DMAMUX instantiated with the hardware configuration parameters listed in the following
table.
Table 47. DMAMUX instantiation
Feature
DMAMUX
Number of DMAMUX output request channels
12(1)/7(2)
Number of DMAMUX request generator channels
4
Number of DMAMUX request trigger inputs
23
Number of DMAMUX synchronization inputs
23
Number of DMAMUX peripheral request inputs
Up to 76
1. STM32U073xx and STM32U083xx devices.
2. STM32U031xx devices.
10.3.2
DMAMUX mapping
The mapping of resources to DMAMUX is hardwired.
286/1325
RM0503 Rev 2
RM0503
DMA request multiplexer (DMAMUX)
Table 48. DMAMUX: assignment of multiplexer inputs to resources
DMA
request
MUX
input
Resource
DMA
request
MUX
input
1
dmamux_req_gen0
2
Resource
DMA
request
MUX
input
Resource
27
LPTIM3_IC3
53
TIM2_UP
dmamux_req_gen1
28
LPTIM3_IC4
54
TIM3_CH1
3
dmamux_req_gen2
29
LPTIM3_UE
55
TIM3_CH2
4
dmamux_req_gen3
30
LPUART1_RX
56
TIM3_CH3
5
ADC
31
LPUART1_TX
57
TIM3_CH4
6
AES_IN
32
LPUART2_RX
58
TIM3_TRIG
7
AES_OUT
33
LPUART2_TX
59
TIM3_UP
8
DAC_Channel1
34
LPUART3_RX
60
TIM6_UP
9
I2C1_RX
35
LPUART3_TX
61
TIM7_UP
10
I2C1_TX
36
SPI1_RX
62
TIM15_CH1
11
I2C2_RX
37
SPI1_TX
63
TIM15_CH2
12
I2C2_TX
38
SPI2_RX
64
TIM15_TRIG_COM
13
I2C3_RX
39
SPI2_TX
65
TIM15_UP
14
I2C3_TX
40
SPI3_RX
66
TIM16_CH1
15
I2C4_RX
41
SPI3_TX
67
TIM16_COM
16
I2C4_TX
42
TIM1_CH1
68
TIM16_UP
17
LPTIM1_IC1
43
TIM1_CH2
69
USART1_RX
18
LPTIM1_IC2
44
TIM1_CH3
70
USART1_TX
19
LPTIM1_IC3
45
TIM1_CH4
71
USART2_RX
20
LPTIM1_IC4
46
TIM1_TRIG_COM
72
USART2_TX
21
LPTIM1_UE
47
TIM1_UP
73
USART3_RX
22
LPTIM2_IC1
48
TIM2_CH1
74
USART3_TX
23
LPTIM2_IC2
49
TIM2_CH2
75
USART4_RX
24
LPTIM2_UE
50
TIM2_CH3
76
USART4_TX
25
LPTIM3_IC1
51
TIM2_CH4
-
-
26
LPTIM3_IC2
52
TIM2_TRIG
-
-
Table 49. DMAMUX: assignment of trigger inputs to resources
Trigger input
Resource
Trigger input
Resource
0
EXTI LINE0
12
EXTI LINE12
1
EXTI LINE1
13
EXTI LINE13
2
EXTI LINE2
14
EXTI LINE14
3
EXTI LINE3
15
EXTI LINE15
4
EXTI LINE4
16
dmamux_evt0
5
EXTI LINE5
17
dmamux_evt1
RM0503 Rev 2
287/1325
300
DMA request multiplexer (DMAMUX)
RM0503
Table 49. DMAMUX: assignment of trigger inputs to resources (continued)
Trigger input
Resource
Trigger input
Resource
6
EXTI LINE6
18
dmamux_evt2
7
EXTI LINE7
19
dmamux_evt3
8
EXTI LINE8
20
LPTIM1_OUT
9
EXTI LINE9
21
LPTIM2_OUT
10
EXTI LINE10
22
LPTIM3_OUT
11
EXTI LINE11
23
Reserved
Table 50. DMAMUX: assignment of synchronization inputs to resources
288/1325
Sync. input
Resource
Sync. input
Resource
0
EXTI LINE0
12
EXTI LINE12
1
EXTI LINE1
13
EXTI LINE13
2
EXTI LINE2
14
EXTI LINE14
3
EXTI LINE3
15
EXTI LINE15
4
EXTI LINE4
16
dmamux_evt0
5
EXTI LINE5
17
dmamux_evt1
6
EXTI LINE6
18
dmamux_evt2
7
EXTI LINE7
19
dmamux_evt3
8
EXTI LINE8
20
LPTIM1_OUT
9
EXTI LINE9
21
LPTIM2_OUT
10
EXTI LINE10
22
LPTIM3_OUT
11
EXTI LINE11
23
Reserved
RM0503 Rev 2
RM0503
DMA request multiplexer (DMAMUX)
10.4
DMAMUX functional description
10.4.1
DMAMUX block diagram
Figure 23 shows the DMAMUX block diagram.
Figure 23. DMAMUX block diagram
32-bit AHB bus
dmamux_hclk
DMAMUX
Request multiplexer
AHB slave
interface
Channel m
DMAMUX_CmCR
Channel 1
p
DMAMUX_C0CR
mu
1
Channel Ctrl
select
dm
a
DMA requests
from peripherals:
dmamux_req_inx
x_
re
q
x
Channel 0
0
n+p+2
Request generator
n
Channel 1
DMAMUX_RGC1CR
1
Channel 0
DMAMUX_RGC0CR
0
DMA requests
to DMA controllers:
dmamux_req_outx
m
1
0
DMA channels
events:
dmamux_evtx
n+3
dmamux_req_genx
Channel n
DMAMUX_RGCnCR
m
1
0
Sync
n+2
n+1
s
1 0
2
1
Interrupt
interface
t
Control registers
1
s
0
Trigger inputs:
dmamux_trgx
Interrupt:
dmamux_ovr_it
1
0
Synchronization inputs:
dmamux_syncx
MSv39745V1
DMAMUX features two main sub-blocks: the request line multiplexer and the request line
generator.
The implementation assigns:
•
DMAMUX request multiplexer sub-block inputs (dmamux_reqx) from peripherals
(dmamux_req_inx) and from channels of the DMAMUX request generator sub-block
(dmamux_req_genx)
•
DMAMUX request outputs to channels of DMA controllers (dmamux_req_outx)
•
Internal or external signals to DMA request trigger inputs (dmamux_trgx)
•
Internal or external signals to synchronization inputs (dmamux_syncx)
RM0503 Rev 2
289/1325
300
DMA request multiplexer (DMAMUX)
10.4.2
RM0503
DMAMUX signals
Table 51 lists the DMAMUX signals.
Table 51. DMAMUX signals
Signal name
dmamux_hclk
dmamux_req_inx
dmamux_trgx
dmamux_req_genx
10.4.3
Description
DMAMUX AHB clock
DMAMUX DMA request line inputs from peripherals
DMAMUX DMA request triggers inputs (to request generator sub-block)
DMAMUX request generator sub-block channels outputs
dmamux_reqx
DMAMUX request multiplexer sub-block inputs (from peripheral
requests and request generator channels)
dmamux_syncx
DMAMUX synchronization inputs (to request multiplexer sub-block)
dmamux_req_outx
DMAMUX requests outputs (to DMA controllers)
dmamux_evtx
DMAMUX events outputs
dmamux_ovr_it
DMAMUX overrun interrupts
DMAMUX channels
A DMAMUX channel is a request multiplexer channel that can include, depending upon the
selected input of the request multiplexer, an additional DMAMUX request generator
channel.
A DMAMUX request multiplexer channel is connected and dedicated to a single channel of
DMA controller(s).
Channel configuration procedure
Follow the sequence below to configure a DMAMUX x channel and the related DMA
channel y:
10.4.4
1.
Set and configure completely the DMA channel y, except enabling the channel y.
2.
Set and configure completely the related DMAMUX y channel.
3.
Last, activate the DMA channel y by setting the EN bit in the DMA y channel register.
DMAMUX request line multiplexer
The DMAMUX request multiplexer with its multiple channels ensures the actual routing of
DMA request/acknowledge control signals, named DMA request lines.
Each DMA request line is connected in parallel to all the channels of the DMAMUX request
line multiplexer.
A DMA request is sourced either from the peripherals, or from the DMAMUX request
generator.
The DMAMUX request line multiplexer channel x selects the DMA request line number as
configured by the DMAREQ_ID field in the DMAMUX_CxCR register.
Note:
290/1325
The null value in the field DMAREQ_ID corresponds to no DMA request line selected.
RM0503 Rev 2
RM0503
DMA request multiplexer (DMAMUX)
Caution:
A same non-null DMAREQ_ID cannot be programmed to different x and y DMAMUX
request multiplexer channels (via DMAMUX_CxCR and DMAMUX_CyCR), except when the
application guarantees that the two connected DMA channels are not simultaneously active.
On top of the DMA request selection, the synchronization mode and/or the event generation
may be configured and enabled, if required.
Synchronization mode and channel event generation
Each DMAMUX request line multiplexer channel x can be individually synchronized by
setting the synchronization enable (SE) bit in the DMAMUX_CxCR register.
DMAMUX has multiple synchronization inputs. The synchronization inputs are connected in
parallel to all the channels of the request multiplexer.
The synchronization input is selected via the SYNC_ID field in the DMAMUX_CxCR register
of a given channel x.
When a channel is in this synchronization mode, the selected input DMA request line is
propagated to the multiplexer channel output, once a programmable rising/falling edge is
detected on the selected input synchronization signal, via the SPOL[1:0] field of the
DMAMUX_CxCR register.
Additionally, internally to the DMAMUX request multiplexer, there is a programmable DMA
request counter, which can be used for the channel request output generation, and for an
event generation. An event generation on the channel x output is enabled through the EGE
bit (event generation enable) of the DMAMUX_CxCR register.
As shown in Figure 25, upon the detected edge of the synchronization input, the pending
selected input DMA request line is connected to the DMAMUX multiplexer channel x output.
Note:
If a synchronization event occurs while there is no pending selected input DMA request line,
it is discarded. The following asserted input request lines is not connected to the DMAMUX
multiplexer channel output until a synchronization event occurs again.
From this point on, each time the connected DMAMUX request is served by the DMA
controller (a served request is deasserted), the DMAMUX request counter is decremented.
At its underrun, the DMA request counter is automatically loaded with the value in the
NBREQ field of the DMAMUX_CxCR register and the input DMA request line is
disconnected from the multiplexer channel x output.
Thus, the number of DMA requests transferred to the multiplexer channel x output following
a detected synchronization event, is equal to the value in the NBREQ field, plus one.
Note:
The NBREQ field value can be written by software only when both synchronization enable
bit (SE) and event generation enable bit (EGE) of the corresponding multiplexer channel x
are disabled.
RM0503 Rev 2
291/1325
300
DMA request multiplexer (DMAMUX)
RM0503
Figure 24. Synchronization mode of the DMAMUX request line multiplexer channel
Selected DMA request line transferred to the output
DMA requests served
DMA request pending
Selected
dmamux_reqx
Not pending
dmamux_syncx
dmamux_req_outx
DMA request counter
4
3
2
1
0
4
dmamux_evtx
DMA request counter underrun
DMA request counter auto-reload to NBREQ
Input DMA request line disconnected from output
Synchronization event
Input DMA request line connected to output
Example: DMAMUX_CCRx configured with: NBREQ=4, SE=1, EGE=1, SPOL=01 (rising edge)
MSv41974V1
Figure 25. Event generation of the DMA request line multiplexer channel
Selected DMA request line transferred to the output
Selected
dmamux_reqx
DMA request pending
Not pending
dmamux_req_outx
DMA request counter
3
2
1
0
3
2
1
0
3
2
1
0
SE
EGE
dmamux_evtx
DMA request counter reaches zero
Event is generated on the output
DMA request counter auto-reloads with NBREQ value
Example with: DMAMUX_CCRx configured with: NBREQ=3, SE=0, EGE=1
MSv41975V1
If EGE is enabled, the multiplexer channel generates a channel event, as a pulse of one
AHB clock cycle, when its DMA request counter is automatically reloaded with the value of
the programmed NBREQ field, as shown in Figure 24 and Figure 25.
292/1325
RM0503 Rev 2
RM0503
DMA request multiplexer (DMAMUX)
Note:
If EGE is enabled and NBREQ = 0, an event is generated after each served DMA request.
Note:
A synchronization event (edge) is detected if the state following the edge remains stable for
more than two AHB clock cycles.
Upon writing into DMAMUX_CxCR register, the synchronization events are masked during
three AHB clock cycles.
Synchronization overrun and interrupt
If a new synchronization event occurs before the request counter underrun (the internal
request counter programmed via the NBREQ field of the DMAMUX_CxCR register), the
synchronization overrun flag bit SOFx is set in the DMAMUX_CSR register.
Note:
The request multiplexer channel x synchronization must be disabled
(DMAMUX_CxCR.SE = 0) when the use of the related channel of the DMA controller is
completed. Else, upon a new detected synchronization event, there is a synchronization
overrun due to the absence of a DMA acknowledge (that is, no served request) received
from the DMA controller.
The overrun flag SOFx is reset by setting the associated clear synchronization overrun flag
bit CSOFx in the DMAMUX_CFR register.
Setting the synchronization overrun flag generates an interrupt if the synchronization
overrun interrupt enable bit SOIE is set in the DMAMUX_CxCR register.
10.4.5
DMAMUX request generator
The DMAMUX request generator produces DMA requests following trigger events on its
DMA request trigger inputs.
The DMAMUX request generator has multiple channels. DMA request trigger inputs are
connected in parallel to all channels.
The outputs of DMAMUX request generator channels are inputs to the DMAMUX request
line multiplexer.
Each DMAMUX request generator channel x has an enable bit GE (generator enable) in the
corresponding DMAMUX_RGxCR register.
The DMA request trigger input for the DMAMUX request generator channel x is selected
through the SIG_ID (trigger signal ID) field in the corresponding DMAMUX_RGxCR register.
Trigger events on a DMA request trigger input can be rising edge, falling edge or either
edge. The active edge is selected through the GPOL (generator polarity) field in the
corresponding DMAMUX_RGxCR register.
Upon the trigger event, the corresponding generator channel starts generating DMA
requests on its output. Each time the DMAMUX generated request is served by the
connected DMA controller (a served request is deasserted), a built-in (inside the DMAMUX
request generator) DMA request counter is decremented. At its underrun, the request
generator channel stops generating DMA requests and the DMA request counter is
automatically reloaded to its programmed value upon the next trigger event.
Thus, the number of DMA requests generated after the trigger event is GNBREQ + 1.
RM0503 Rev 2
293/1325
300
DMA request multiplexer (DMAMUX)
Note:
RM0503
The GNBREQ field value can be written by software only when the enable GE bit of the
corresponding generator channel x is disabled.
There is no hardware write protection.
A trigger event (edge) is detected if the state following the edge remains stable for more
than two AHB clock cycles.
Upon writing into DMAMUX_RGxCR register, the trigger events are masked during three
AHB clock cycles.
Trigger overrun and interrupt
If a new DMA request trigger event occurs before the DMAMUX request generator counter
underrun (the internal counter programmed via the GNBREQ field of the DMAMUX_RGxCR
register), and if the request generator channel x was enabled via GE, then the request
trigger event overrun flag bit OFx is asserted by the hardware in the DMAMUX_RGSR
register.
Note:
The request generator channel x must be disabled (DMAMUX_RGxCR.GE = 0) when the
usage of the related channel of the DMA controller is completed. Else, upon a new detected
trigger event, there is a trigger overrun due to the absence of an acknowledge (that is, no
served request) received from the DMA.
The overrun flag OFx is reset by setting the associated clear overrun flag bit COFx in the
DMAMUX_RGCFR register.
Setting the DMAMUX request trigger overrun flag generates an interrupt if the DMA request
trigger event overrun interrupt enable bit OIE is set in the DMAMUX_RGxCR register.
10.5
DMAMUX interrupts
An interrupt can be generated upon:
•
a synchronization event overrun in each DMA request line multiplexer channel
•
a trigger event overrun in each DMA request generator channel
For each case, per-channel in.dividual interrupt enable, status, and clear flag register bits
are available.
Table 52. DMAMUX interrupts
Interrupt signal
dmamuxovr_it
294/1325
Interrupt event
Event flag
Clear bit
Enable bit
Synchronization event overrun
on channel x of the
DMAMUX request line multiplexer
SOFx
CSOFx
SOIE
Trigger event overrun
on channel x of the
DMAMUX request generator
OFx
COFx
OIE
RM0503 Rev 2
RM0503
DMA request multiplexer (DMAMUX)
10.6
DMAMUX registers
Refer to the table containing register boundary addresses for the DMAMUX base address.
DMAMUX registers may be accessed per byte (8-bit), half-word (16-bit), or word (32-bit).
The address must be aligned with the data size.
10.6.1
DMAMUX request line multiplexer channel x configuration register
(DMAMUX_CxCR)
Address offset: 0x000 + 0x04 * x (x = 0 to 11)
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
28
27
26
25
24
23
22
SYNC_ID[4:0]
rw
rw
rw
21
20
19
NBREQ[4:0]
rw
rw
18
17
16
SPOL[1:0]
SE
rw
rw
rw
rw
rw
rw
rw
rw
6
5
4
3
2
1
0
rw
rw
15
14
13
12
11
10
9
8
7
Res.
Res.
Res.
Res.
Res.
Res.
EGE
SOIE
Res.
rw
rw
DMAREQ_ID[6:0]
rw
rw
rw
rw
rw
Bits 31:29 Reserved, must be kept at reset value.
Bits 28:24 SYNC_ID[4:0]: Synchronization identification
Selects the synchronization input (see Table 50: DMAMUX: assignment of synchronization
inputs to resources).
Bits 23:19 NBREQ[4:0]: Number of DMA requests minus 1 to forward
Defines the number of DMA requests to forward to the DMA controller after a synchronization
event, and/or the number of DMA requests before an output event is generated.
This field must only be written when both SE and EGE bits are low.
Bits 18:17 SPOL[1:0]: Synchronization polarity
Defines the edge polarity of the selected synchronization input:
00: No event (no synchronization, no detection).
01: Rising edge
10: Falling edge
11: Rising and falling edges
Bit 16 SE: Synchronization enable
0: Synchronization disabled
1: Synchronization enabled
Bits 15:10 Reserved, must be kept at reset value.
Bit 9 EGE: Event generation enable
0: Event generation disabled
1: Event generation enabled
Bit 8 SOIE: Synchronization overrun interrupt enable
0: Interrupt disabled
1: Interrupt enabled
RM0503 Rev 2
295/1325
300
DMA request multiplexer (DMAMUX)
RM0503
Bit 7 Reserved, must be kept at reset value.
Bits 6:0 DMAREQ_ID[6:0]: DMA request identification
Selects the input DMA request. See the DMAMUX table about assignments of multiplexer
inputs to resources.
10.6.2
DMAMUX request line multiplexer interrupt channel status register
(DMAMUX_CSR)
Address offset: 0x080
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
SOF11
SOF10
SOF9
SOF8
SOF7
SOF6
SOF5
SOF4
SOF3
SOF2
SOF1
SOF0
r
r
r
r
r
r
r
r
r
r
r
r
Bits 31:12 Reserved, must be kept at reset value.
Bits 11:0 SOF[11:0]: Synchronization overrun event flag
The flag is set when a synchronization event occurs on a DMA request line multiplexer
channel x, while the DMA request counter value is lower than NBREQ.
The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register.
10.6.3
DMAMUX request line multiplexer interrupt clear flag register
(DMAMUX_CFR)
Address offset: 0x084
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
CSOF
11
CSOF
10
CSOF
9
CSOF
8
CSOF
7
CSOF
6
CSOF
5
CSOF
4
CSOF
3
CSOF
2
CSOF
1
CSOF
0
w
w
w
w
w
w
w
w
w
w
w
w
Res.
Res.
Res.
Bits 31:12 Reserved, must be kept at reset value.
Bits 11:0 CSOF[11:0]: Clear synchronization overrun event flag
Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR
register.
296/1325
RM0503 Rev 2
RM0503
DMA request multiplexer (DMAMUX)
10.6.4
DMAMUX request generator channel x configuration register
(DMAMUX_RGxCR)
Address offset: 0x100 + 0x04 * x (x = 0 to 3)
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
23
22
21
20
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
Res.
Res.
Res.
Res.
Res.
Res.
Res.
OIE
Res.
Res.
Res.
19
17
16
GPOL[1:0]
GE
rw
rw
rw
rw
3
2
1
0
rw
rw
GNBREQ[4:0]
rw
18
SIG_ID[4:0]
rw
rw
rw
Bits 31:24 Reserved, must be kept at reset value.
Bits 23:19 GNBREQ[4:0]: Number of DMA requests to be generated (minus 1)
Defines the number of DMA requests to be generated after a trigger event. The actual
number of generated DMA requests is GNBREQ +1.
Note: This field must be written only when GE bit is disabled.
Bits 18:17 GPOL[1:0]: DMA request generator trigger polarity
Defines the edge polarity of the selected trigger input
00: No event, i.e. no trigger detection nor generation.
01: Rising edge
10: Falling edge
11: Rising and falling edges
Bit 16 GE: DMA request generator channel x enable
0: DMA request generator channel x disabled
1: DMA request generator channel x enabled
Bits 15:9 Reserved, must be kept at reset value.
Bit 8 OIE: Trigger overrun interrupt enable
0: Interrupt on a trigger overrun event occurrence is disabled
1: Interrupt on a trigger overrun event occurrence is enabled
Bits 7:5 Reserved, must be kept at reset value.
Bits 4:0 SIG_ID[4:0]: Signal identification
Selects the DMA request trigger input used for the channel x of the DMA request generator
RM0503 Rev 2
297/1325
300
DMA request multiplexer (DMAMUX)
10.6.5
RM0503
DMAMUX request generator interrupt status register
(DMAMUX_RGSR)
Address offset: 0x140
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
OF3
OF2
OF1
OF0
r
r
r
r
Bits 31:4 Reserved, must be kept at reset value.
Bits 3:0 OF[3:0]: Trigger overrun event flag
The flag is set when a new trigger event occurs on DMA request generator channel x, before
the request counter underrun (the internal request counter programmed via the GNBREQ
field of the DMAMUX_RGxCR register).
The flag is cleared by writing 1 to the corresponding COFx bit in the DMAMUX_RGCFR
register.
10.6.6
DMAMUX request generator interrupt clear flag register
(DMAMUX_RGCFR)
Address offset: 0x144
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
COF3
COF2
COF1
COF0
w
w
w
w
Bits 31:4 Reserved, must be kept at reset value.
Bits 3:0 COF[3:0]: Clear trigger overrun event flag
Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RGSR
register.
298/1325
RM0503 Rev 2
RM0503
10.6.7
DMA request multiplexer (DMAMUX)
DMAMUX register map
The following table summarizes the DMAMUX registers and reset values. Refer to the
register boundary address table for the DMAMUX register base address.
Res.
SOIE
SOIE
Res.
Res.
SOIE
SOIE
Res.
Res.
SOIE
SOIE
Res.
Res.
SOIE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DMAREQ_ID[6:0]
0
Res.
SOIE
0
0
0
0
0
0
0
DMAREQ_ID[6:0]
0
Res.
SOIE
0
DMAREQ_ID[6:0]
0
0
0
0
0
0
DMAREQ_ID[6:0]
0
Res.
SOIE
0
0
0
0
0
0
0
DMAREQ_ID[6:0]
0
Res.
SOIE
0
DMAREQ_ID[6:0]
0
0
0
0
0
0
DMAREQ_ID[6:0]
0
Res.
0
0
0
0
0
0
DMAREQ_ID[6:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CSOF0
0
0
0
0
0
0
Res.
0
CSOF1
0
Res.
0
CSOF2
0
Res.
0
CSOF3
0
Res.
SOF0 Res.
0
SOF1 Res.
0
SOF2 Res.
0
SOF3 Res.
0
SOF4 Res.
SOIE
Res.
Res.
EGE
EGE
EGE
EGE
EGE
EGE
EGE
EGE
EGE
EGE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
SOF5 Res.
Res.
Res.
Res.
Res. Res.
0
0
CSOF4
Res.
Res.
0
0
CSOF5
Res.
Res.
Res.
Res.
Res. Res.
Res. Res.
0
0
DMAREQ_ID[6:0]
Res.
Res.
Res.
0
0
Res. Res.
Res.
Res.
Res.
Res.
GE
Res.
RM0503 Rev 2
Res. Res.
0
0
0
0
SOF6 Res.
Res.
Res.
Res.
0
0
0
CSOF6
Res.
Res.
Res.
GPOL Res.
[1:0] Res.
0
0
0
Res. Res.
Res.
Res.
Res.
Res.
Res.
0
0
0
SOF7 Res.
Res.
Res.
Res.
Res.
Res.
0
0
0
SOF8 Res.
Res.
Res.
0
0
0
DMAREQ_ID[6:0]
CSOF7
Res.
Res.
Res.
Res.
Res.
0
0
0
CSOF8
Res.
Res.
Res.
Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
GNBREQ[4:0]
0
0
OIE Res.
Res.
Res.
Reset value
Res. Res.
DMAMUX_RG0CR
Res. Res.
0x100
Reserved
Res. Res.
Reset value
0x088 0x0FC
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DMAMUX_CFR
Res.
0x084
Res.
Reset value
Res.
Res.
Res.
DMAMUX_CSR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
SE
SE
Res.
Res.
SE
SE
Res.
Res.
SE
SE
0
0
Res.
SPOL
[1:0]
SPOL
[1:0]
SPOL
[1:0]
SPOL
[1:0]
0
Res.
0
Res.
0
Res.
0
Res.
0
Reserved
Res.
0
0
0
0
0
Res. Res.
NBREQ[4:0]
0
0
EGE
0
Res.
0
0
Res.
0
0
Res.
0
0
0
0
0
EGE
0
0
Res.
0
0
NBREQ[4:0]
SYNC_ID[4:0]
0
0
0
0
SOF9 Res.
0
0
0
0
DMAREQ_ID[6:0]
CSOF9
0
0
0
0
Res.
0
0
0
Res. Res.
0
0
Res.
0
0
0
0
SOF10 Res.
0
0
0
CSOF10
0
0
NBREQ[4:0]
0
Res. Res.
0
0
0
Res.
NBREQ[4:0]
0
Res.
0
0
Res.
0
0
0
DMAREQ_ID[6:0]
SOF11 Res.
0
0
0
CSOF11
0
0
Res.
0
0
0
Res.
NBREQ[4:0]
0
0
Res. Res.
0
0
Res.
0
0
Res.
0
0
Res.
0
0
Res.
0
0
0
Res.
NBREQ[4:0]
0
Res.
0
0
Res.
0
0
Res.
0
0
Res.
0
0
0
0
Res.
0
0
Res.
0
0
SE
0
0
SE
0
0
Res.
0
0
NBREQ[4:0]
SE
0
0
0
Res.
NBREQ[4:0]
0
SE
0
0
Res.
0
0
SPOL
[1:0]
0
0
0
0
SPOL
[1:0]
0
0
0
Res.
0x080
0
0
Res.
Reset value
0x0300x07C
0
0
0
0
Res.
Res.
DMAMUX_C11CR
Res.
0x02C
0
SYNC_ID[4:0]
0
Res.
Reset value
0
0
0
Res.
Res.
DMAMUX_C10CR
Res.
0x028
0
0
NBREQ[4:0]
SYNC_ID[4:0]
0
Res.
Reset value
0
0
SE
Res.
Res.
0x024
0
SYNC_ID[4:0]
0
Res.
Reset value
DMAMUX_C9CR
0
0
0
0
Res.
Res.
DMAMUX_C8CR
Res.
0x020
0
SYNC_ID[4:0]
0
Res.
Reset value
0
0
0
SE
Res.
DMAMUX_C7CR
Res.
0x01C
0
0
NBREQ[4:0]
SYNC_ID[4:0]
0
Res.
Reset value
0
0
Res.
Res.
DMAMUX_C6CR
Res.
0x018
0
SYNC_ID[4:0]
0
Res.
Reset value
0
0
SPOL
[1:0]
Res.
Res.
0x014
0
SYNC_ID[4:0]
0
Res.
Reset value
DMAMUX_C5CR
0
0
SPOL
[1:0]
Res.
DMAMUX_C4CR
Res.
0x010
0
0
NBREQ[4:0]
SYNC_ID[4:0]
0
Res.
Reset value
0
SPOL
[1:0]
Res.
DMAMUX_C3CR
Res.
0x00C
0
SYNC_ID[4:0]
0
Res.
Reset value
0
SPOL
[1:0]
Res.
DMAMUX_C2CR
Res.
0x008
0
SYNC_ID[4:0]
0
Res.
Reset value
0
NBREQ[4:0]
SPOL
[1:0]
Res.
Res.
0x004
0
Res.
Reset value
DMAMUX_C1CR
SYNC_ID[4:0]
SPOL
[1:0]
Res.
DMAMUX_C0CR
Res.
0x000
Register
Res.
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 53. DMAMUX register map and reset values
SIG_ID[4:0]
0
0
0
0
0
299/1325
300
0x148 0x3FC
300/1325
Reserved
RM0503 Rev 2
Refer to Section 2.2 on page 55 for the register boundary addresses.
COF1
COF0
0
0
0
0
Res.
Res.
Reset value
COF2
0
0
OF0 Res.
0
OF1 Res.
0
OF2 Res.
0
OF3 Res.
Reset value
COF3
Res.
Res.
Res.
OIE
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
0
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
GE
Res.
Res.
Res.
OIE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
GE
Res.
Res.
Res.
OIE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
GPOL
[1:0]
0
Res.
Res. Res.
GPOL
[1:0]
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res. Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
GE
0
Res.
0
Res. Res.
0
Res.
Res.
GPOL
[1:0]
0
Res. Res.
0
Res.
Res.
0
Res.
Res.
0
Res. Res.
0
0
Res.
0
0
Res.
0
Res. Res.
0
0
Res.
0
0
Res.
0
Res. Res.
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
0
Res.
0
Res. Res.
Res.
Res.
Res.
Res.
Res.
Res.
GNBREQ[4:0]
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
GNBREQ[4:0]
0
Res.
Res.
Reset value
GNBREQ[4:0]
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res.
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res. Res.
Reset value
Res.
Res.
Res.
Res.
DMAMUX_RGCFR
Res.
0x144
DMAMUX_RGSR
Res.
0x140
Reserved
Res.
0x110 0x13C
DMAMUX_RG3CR
Res. Res.
0x10C
DMAMUX_RG2CR
Res.
0x108
DMAMUX_RG1CR
Res.
0x104
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Register
Res.
Offset
Res.
DMA request multiplexer (DMAMUX)
RM0503
Table 53. DMAMUX register map and reset values (continued)
SIG_ID[4:0]
0
0
0
0
0
0
SIG_ID[4:0]
0
0
SIG_ID[4:0]
0
0
0
0
RM0503
Nested vectored interrupt controller (NVIC)
11
Nested vectored interrupt controller (NVIC)
11.1
Main features
•
32 maskable interrupt channels (not including the sixteen Cortex®-M0+ system
exceptions)
•
4 programmable priority levels (2 bits of interrupt priority are used)
•
Low-latency exception and interrupt handling
•
Power management control
•
Implementation of system control registers
The NVIC and the processor core interface are closely coupled, which enables low-latency
interrupt processing and efficient processing of late arriving interrupts.
All interrupts including the core exceptions are managed by the NVIC. For more information
on exceptions and NVIC programming, refer to the programming manual PM0223.
11.2
SysTick calibration value register
The SysTick calibration value is set to 1000, which gives a reference time base of 1 ms with
the SysTick clock set to 1 MHz.
11.3
Interrupt and exception vectors
Table 54 is the vector table. Information pertaining to a peripheral only applies to devices
containing that peripheral.
Table 54. Vector table(1)
Position
Priority
Type of
priority
-
-
-
-
-3
fixed
Acronym
Description
Address
-
Reserved
0x0000_0000
Reset
Reset
0x0000_0004
0x0000_0008
-
-2
fixed
NMI_Handler
Non maskable interrupt. The SRAM
parity error, flash ECC double err.,
HSE CSS and LSE CSS are linked
to the NMI vector.
-
-1
fixed
HardFault_Handler
All class of fault
0x0000_000C
-
Reserved
0x0000_0010
0x0000_0014
0x0000_0018
0x0000_001C
0x0000_0020
0x0000_0024
0x0000_0028
SVC_Handler
System service call via SVC
instruction
0x0000_002C
-
-
-
-
3
settable
RM0503 Rev 2
301/1325
303
Nested vectored interrupt controller (NVIC)
RM0503
Table 54. Vector table(1) (continued)
Position
Priority
Type of
priority
-
-
-
-
5
-
Acronym
Description
Address
-
Reserved
0x0000_0030
0x0000_0034
settable
PendSV_Handler
Pendable request for system service
0x0000_0038
6
settable
SysTick_Handler
System tick timer
0x0000_003C
0
7
settable
WWDG
Window watchdog and independent
watchdog interrupt
0x0000_0040
1
8
settable
PVD_PVM
PVD/PVM1/PVM2/PVM3 interrupt
(combined with EXTI lines
16 & 19 & 20 & 21)
0x0000_0044
2
9
settable
RTC / TAMP
RTC and TAMP interrupts
(combined EXTI lines 19 & 21)
0x0000_0048
3
10
settable
FLASH
Flash global interrupt
0x0000_004C
4
11
settable
RCC / CRS
RCC and CRS global interrupt
0x0000_0050
5
12
settable
EXTI0_1
EXTI lines 0 & 1 interrupt
0x0000_0054
6
13
settable
EXTI2_3
EXTI lines 2 & 3 interrupt
0x0000_0058
7
14
settable
EXTI4_15
EXTI lines 4 to 15 interrupt
0x0000_005C
8
15
settable
USB
USB global interrupt (combined with
EXTI line 33)
0x0000_0060
9
16
settable
DMA1_Channel1
DMA1 channel 1 interrupt
0x0000_0064
10
17
settable
DMA1_Channel2_3
DMA1 channel 2 & 3 interrupts
0x0000_0068
11
18
settable
DMA1_Channel4_5_6
DMA1 channel 4, 5, 6, 7, DMAMUX,
_7 / DMAMUX /
DMA2_Channel1_2_3 DMA2 channel 1, 2, 3, 4, 5 interrupts
_4_5
12
19
settable
ADC_COMP
ADC and COMP interrupts (ADC
combined with EXTI lines 17 & 18)
0x0000_0070
13
20
settable
TIM1_BRK_UP_TRG
_COM
TIM1 break, update, trigger and
commutation interrupts
0x0000_0074
14
21
settable
TIM1_CC
TIM1 Capture Compare interrupt
0x0000_0078
15
22
settable
TIM2
TIM2 global interrupt
0x0000_007C
16
23
settable
TIM3
TIM3 global interrupt
0x0000_0080
17
24
settable
TIM6_DAC / LPTIM1
TIM6, LPTIM1 and DAC global
interrupt (combined with EXTI line
29)
0x0000_0084
18
25
settable
TIM7 / LPTIM2
TIM7 and LPTIM2 global interrupt
(combined with EXTI line 30)
0x0000_0088
19
26
settable
TIM15 / LPTIM3
TIM15 and LPTIM3 global interrupt
(combined with EXTI line 29)
0x0000_008C
20
27
settable
TIM16
TIM16 global interrupt
0x0000_0090
302/1325
RM0503 Rev 2
0x0000_006C
RM0503
Nested vectored interrupt controller (NVIC)
Table 54. Vector table(1) (continued)
Position
Priority
Type of
priority
21
28
settable
TSC
TSC global interrupt
0x0000_0094
22
29
settable
LCD
LCD global interrupt (combined with
EXTI line 32)
0x0000_0098
23
30
settable
I2C1
I2C1 global interrupt (combined with
EXTI line 23)
0x0000_009C
24
31
settable
I2C2 / I2C3 / I2C4
I2C2/3/4 global interrupt
0x0000_00A0
25
32
settable
SPI1
SPI1 global interrupt
0x0000_00A4
26
33
settable
SPI2 / SPI3
SPI2/3 global interrupt
0x0000_00A8
27
34
settable
USART1
USART1 global interrupt (combined
with EXTI line 25)
0x0000_00AC
28
35
settable
USART2 / LPUART2
USART2 and LPUART2 global
interrupt (combined with EXTI lines
26 & 35)
0x0000_00B0
29
36
settable
USART3 / LPUART1
USART3 and LPUART1 global
interrupt (combined with EXTI lines
24 & 28)
0x0000_00B4
30
37
settable
USART4 / LPUART3
USART4 and LPUART3 global
interrupt (combined with EXTI lines
20 & 34)
0x0000_00B8
31
38
settable
AES / RNG
AES and RNG global interrupts
0x0000_00BC
1.
Acronym
Description
Address
The grayed cells correspond to the Cortex®-M0+ system exceptions.
RM0503 Rev 2
303/1325
303
Extended interrupt and event controller (EXTI)
12
RM0503
Extended interrupt and event controller (EXTI)
The Extended interrupt and event controller (EXTI) manages the CPU and system wake-up
through configurable and direct event inputs (lines). It provides wake-up requests to the
power control, and generates an interrupt request to the CPU NVIC and events to the CPU
event input. For the CPU an additional event generation block (EVG) is needed to generate
the CPU event signal.
The EXTI wake-up requests allow the system to be woken up from Stop modes.
The interrupt request and event request generation can also be used in Run modes.
The EXTI also includes the EXTI I/O port mux.
12.1
EXTI main features
The EXTI main features are the following:
•
System wake-up upon event on any input
•
Wake-up flag and CPU interrupt generation for events not having a wake-up flag in
their source peripheral
•
Configurable events (from I/Os, peripherals not having an associated interrupt pending
status bit, or peripherals generating a pulse)
•
•
12.2
–
Selectable active trigger edge
–
Independent rising and falling edge interrupt pending status bits
–
Individual interrupt and event generation mask, used for conditioning the CPU
wake-up, interrupt and event generation
–
SW trigger possibility
Direct events (from peripherals having an associated flag and interrupt pending status
bit)
–
Fixed rising edge active trigger
–
No interrupt pending status bit in the EXTI
–
Individual interrupt and event generation mask for conditioning the CPU wake-up
and event generation
–
No SW trigger possibility
I/O port selector
EXTI block diagram
The EXTI consists of a register block accessed via an AHB interface, the event input trigger
block, the masking block, and EXTI mux as shown in Figure 26.
The register block contains all the EXTI registers.
The event input trigger block provides an event input edge trigger logic.
The masking block provides the event input distribution to the different wake-up, interrupt
and event outputs, and the masking of these.
The EXTI mux provides the I/O port selection on to the EXTI event signal.
304/1325
RM0503 Rev 2
RM0503
Extended interrupt and event controller (EXTI)
Figure 26. EXTI block diagram
AHB interface
Registers
Peripherals
exti[15:0]
EXTImux
GPIO
hclk
IOPort
Configurable event(15:0)
Direct event(x) or
configurable event(y)
Wake-up
Interrupt
To interconnect
sys_wakeup
c_wakeup
PWR
it_exti_per(y)*
Event
Trigger events
Masking
c_evt_exti
c_evt_rst
Pulse
Direct
event(x)
c_event
EVG
rxev
c_fclk
CPU
EXTI
* it_exti_per(y) are only available for
configurable events (y)
MSv71277V1
Table 55. EXTI signal overview
Signal name
I/O
Description
AHB interface
I/O
EXTI register bus interface. When one event is configured to allow
security, the AHB interface support secure accesses
hclk
I
AHB bus clock and EXTI system clock
Configurable
event(y)
I
Asynchronous wake-up events from peripherals that do not have an
associated interrupt and flag in the peripheral
Direct event(x)
I
Synchronous and asynchronous wake-up events from peripherals having
an associated interrupt and flag in the peripheral
IOPort(n)
I
GPIO ports[15:0]
exti[15:0]
O
EXTI output port to trigger other IPs
it_exti_per (y)
O
Interrupts to the CPU associated with configurable event (y)
c_evt_exti
O
High-level sensitive event output for CPU synchronous to hclk
c_evt_rst
I
Asynchronous reset input to clear c_evt_exti
sys_wakeup
O
Asynchronous system wake-up request to PWR for ck_sys and hclk
c_wakeup
O
Wake-up request to PWR for CPU, synchronous to hclk
Table 56. EVG pin overview
Pin name
I/O
Description
c_fclk
I
CPU free-running clock
c_evt_in
I
High-level sensitive event input from EXTI, asynchronous to CPU clock
RM0503 Rev 2
305/1325
318
Extended interrupt and event controller (EXTI)
RM0503
Table 56. EVG pin overview (continued)
12.2.1
Pin name
I/O
Description
c_event
O
Event pulse, synchronous to CPU clock
c_evt_rst
O
Event reset signal, synchronous to CPU clock
EXTI connections between peripherals and CPU
The peripherals able to generate wake-up or interrupt events when the system is in Stop
mode are connected to the EXTI.
•
Peripheral wake-up signals that generate a pulse or that do not have an interrupt status
bits in the peripheral, are connect to an EXTI configurable line. For these events the
EXTI provides a status pending bit which requires to be cleared. It is the EXTI interrupt
associated with the status bit that interrupts the CPU.
•
Peripheral interrupt and wake-up signals that have a status bit in the peripheral which
requires to be cleared in the peripheral, are connected to an EXTI direct line. There is
no status pending bit within the EXTI. The interrupt or wake-up is cleared by the CPU in
the peripheral. It is the peripheral interrupt that interrupts the CPU directly.
•
All GPIO ports input to the EXTI multiplexer, allowing to select a port to wake up the
system via a configurable event.
The EXTI configurable event interrupts are connected to the NVIC(a) of the CPU.
The dedicated EXTI/EVG CPU event is connected to the CPU rxev input.
The EXTI CPU wake-up signals are connected to the PWR block, and are used to wake up
the system and CPU sub-system bus clocks.
12.3
EXTI functional description
Depending on the EXTI line type and wake-up target(s), different logic implementations are
used. The applicable features and control or status registers are:
•
–
EXTI rising trigger selection register (EXTI_RTSR1)
–
EXTI falling trigger selection register 1 (EXTI_FTSR1)
•
software trigger through EXTI software interrupt event register 1 (EXTI_SWIER1)
•
pending interrupt flagging through
•
•
306/1325
rising and falling edge event enable through
–
EXTI rising edge pending register 1 (EXTI_RPR1)
–
EXTI falling edge pending register 1 (EXTI_FPR1)
–
EXTI external interrupt selection register x (EXTI_EXTICRx)
CPU wake-up and interrupt enable through
–
EXTI CPU wake-up with interrupt mask register (EXTI_IMR1)
–
EXTI CPU wake-up with interrupt mask register (EXTI_IMR2)
CPU wake-up and event enable through
–
EXTI CPU wake-up with event mask register (EXTI_EMR1)
–
EXTI CPU wake-up with event mask register (EXTI_EMR2)
RM0503 Rev 2
RM0503
Extended interrupt and event controller (EXTI)
12.3.1
Event input
type
Logic implementation
EXTI_RTSR1
EXTI_FTSR1
EXTI_SWIER1
EXTI_R/FPR1
EXTI_IMRx
EXTI_EMRx
Table 57. EXTI event input configurations and register control
Configurable
Configurable event input wake-up logic
x
x
x
x
x
x
Direct
Direct event input wake-up logic
-
-
-
-
x
x
EXTI configurable event input wake-up
Figure 27 is a detailed representation of the logic associated with configurable event inputs
which wake up the CPU sub-system bus clocks and generated an EXTI pending flag and
interrupt to the CPU and or a CPU wake-up event.
Figure 27. Configurable event trigger logic CPU wake-up
Peripheral interface
AHB interface
hclk
Falling
trigger
selection
register
Rising
trigger
selection
register
Software
interrupt
event
register
CPU
event
mask
register
CPU
interrupt
mask
register
Pending
request
register
it_exti_per(y)
Asynchronous edge
detection circuit
rst
Configurable
Event input(y)
Delay
hclk
Same circuit for
configurable and direct
eventshclk
Rising edge
detect pulse
generator
Rising
edge
detectrst
CPU Event(y)
Other CPU Events(x,y)
EVG
ck_fclk_c
c_evt_rst
c_evt_exti
CPU rising
edge detect c_event
pulse
generator
Synch
hclk
Other CPU Wake-ups
CPU Wake-up(y)
c_wakeup
Other Wake-ups
Wake-up(y)
sys_wakeup
EXTI
MSv71278V1
The software interrupt event register allows triggering configurable events by software,
writing the corresponding register bit, irrespective of the edge selection setting.
The rising edge and falling edge selection registers allow to enable and select the
configurable event active trigger edge or both edges.
The CPU has its dedicated interrupt mask register and a dedicated event mask registers.
The enabled event allows generating an event on the CPU. All events for a CPU are OR-ed
together into a single CPU event signal. The event pending registers (EXTI_RPR1 and
EXTI_FPR1) is not set for an unmasked CPU event.
The configurable events have unique interrupt pending request registers, shared by the
CPU. The pending register is only set for an unmasked interrupt. Each configurable event
provides a common interrupt to the CPU. The configurable event interrupts need to be
acknowledged by software in the EXTI_RPR1 and/or EXTI_FPR1 registers.
When a CPU interrupt or CPU event is enabled, the asynchronous edge detection circuit is
reset by the clocked delay and rising edge detect pulse generator. This guarantees the
wake-up of the EXTI hclk clock before the asynchronous edge detection circuit is reset.
RM0503 Rev 2
307/1325
318
Extended interrupt and event controller (EXTI)
RM0503
Note:
A detected configurable event interrupt pending request can be cleared by the CPU. The
system cannot enter low-power modes as long as an interrupt pending request is active.
12.3.2
EXTI direct event input wake-up
Figure 28 is a detailed representation of the logic associated with direct event inputs waking
up the system.
The direct events do not have an associated EXTI interrupt. The EXTI only wakes up the
system and CPU sub-system clocks and may generate a CPU wake-up event. The
peripheral synchronous interrupt, associated with the direct wake-up event wakes up the
CPU.
The EXTI direct event is able to generate a CPU event. This CPU event wakes up the CPU.
The CPU event may occur before the interrupt flag of the associated peripheral is set.
Figure 28. Direct event trigger logic CPU wake-up
AHB
interface
Peripheral interface
CPU event
mask
register
hclk
Delay
hclk
Other CPU Events(x,y)
EVG
c_evt_rst
Rising edge
detect
rst
c_evt_exti
ck_fclk_c
CPU rising
edge detect
pulse
generator
c_event
CPU Wake-up(x)
Other CPU
Wake-ups
Synch
hclk
Falling edge
detect
pulse
generator
EXTI
Same circuit for configurable
and direct events
hclk
CPU Event(x)
Asynchronous
rising edge
detect circuit
rst
Direct
event
input(x)
CPU
interrupt
mask
register
Other Wake-ups
c_wakeup
sys_wakeup
Wake-up(x)
hclk
MSv71279V1
12.3.3
EXTI mux
The EXTI mux allows selecting GPIOs as interrupts and wake-up. The GPIOs are
connected via 16 EXTI mux lines to the first 16 EXTI events as configurable event. The
selection of GPIO port as EXTI mux output is controlled through the EXTI external interrupt
selection register x (EXTI_EXTICRx) register.
308/1325
RM0503 Rev 2
RM0503
Extended interrupt and event controller (EXTI)
Figure 29. EXTI GPIO mux
EXTI_EXTICR1.EXTI0
EXTI_EXTICR1.EXTI1
EXTI_EXTICR1.EXTI15
PA0
PA1
PA15
PB0
PB1
PB15
………....
PC1
………....
EXTI0
Px0
Px1
EXTI1
………....
PC15
EXTI15
………....
PC0
Px15
MS44726V1
The EXTIs mux outputs are available as output signals from the EXTI, to trigger other
functional blocks. The EXTI mux outputs are available independently of mask setting
through the EXTI_IMR and EXTI_EMR registers.
The EXTI lines (event inputs) are connected as shown in the following table.
Table 58. EXTI line connections(1)
EXTI line
Line source
Line type
0-15
GPIO
Configurable
16
PVD output
Configurable
17
COMP1 output
Configurable
18
COMP2 output
Configurable
19
VDDUSB monitoring
Configurable
20
ADC supply monitoring
Configurable
21
DAC supply monitoring
Configurable
22
LCD wake-up
Direct
23
I2C3 wake-up
Direct
24
LPTIM1 wake-up
Direct
25
LPTIM2 wake-up
Direct
26
LPTIM3 wake-up
Direct
27
LSE_CSS
Direct
28
RTC
Direct
29
TAMP
Direct
30
LPUART1 wake-up
Direct
31
LPUART2 wake-up
Direct
32
LPUART3 wake-up
Direct
33
I2C1 wake-up
Direct
RM0503 Rev 2
309/1325
318
Extended interrupt and event controller (EXTI)
RM0503
Table 58. EXTI line connections(1) (continued)
EXTI line
Line source
Line type
34
USART1 wake-up
Direct
35
USART2 wake-up
Direct
36
USB
Direct
37
WWDG
Direct
1. EXTI lines 18, 19, 22, 26, 32 and 36 are reserved on STM32U031xx devices.
12.4
EXTI functional behavior
The direct event inputs are enabled in the respective peripheral generating the wake-up
event. The configurable events are enabled by enabling at least one of the trigger edges.
Once an event input is enabled, the generation of a CPU wake-up is conditioned by the
CPU interrupt mask and CPU event mask.
Table 59. Masking functionality
CPU interrupt
enable
IMn of EXTI_IMR
0
1
CPU event enable
EMn of EXTI_EMR
Configurable
event inputs
RPIFn of
EXTI_RPR,
FPIFn of
EXTI_FPR
exti(n)
interrupt(1)
CPU
event
CPU wake-up
0
No
Masked
Masked
Masked
1
No
Masked
Yes
Yes
0
Status latched
Yes
Masked
Yes(2)
1
Status latched
Yes
Yes
Yes
1. The single exti(n) interrupt goes to the CPU. If no interrupt is required for CPU, the exti(n) interrupt must be masked in the
CPU NVIC.
2. Only if CPU interrupt is enabled in EXTI_IMR.IMn.
For configurable event inputs, upon an edge on the event input, an event request is
generated if that edge (rising or/and falling) is enabled. When the associated CPU interrupt
is unmasked, the corresponding RPIFn and/or FPIFn bit is/are set in the EXTI_RPR or/and
EXTI_FPR register, waking up the CPU subsystem and activating CPU interrupt signal. The
RPIFn and/or FPIFn pending bit is cleared by writing 1 to it, which clears the CPU interrupt
request.
For direct event inputs, when enabled in the associated peripheral, an event request is
generated on the rising edge only. There is no corresponding CPU pending bit in the EXTI.
When the associated CPU interrupt is unmasked, the corresponding CPU subsystem is
woken up. The CPU is woken up (interrupted) by the peripheral synchronous interrupt.
The CPU event must be unmasked to generate an event. Upon an enabled edge occurring
on an event input, a CPU event pulse is generated. There is no event pending bit.
For the configurable event inputs, the software can generate an event request by setting the
corresponding bit of the software interrupt/event register EXTI_SWIER1, which has the
310/1325
RM0503 Rev 2
RM0503
Extended interrupt and event controller (EXTI)
effect of a rising edge on the event input. The pending rising edge event flag is set in the
EXTI_RPR1 register, irrespective of the EXTI_RTSR1 register setting.
12.5
EXTI registers
The EXTI register map is divided in the following sections:
Table 60. EXTI register map sections
Address
Description
0x000 - 0x01C
General configurable event [31:0] configuration
0x060 - 0x06C
EXTI I/O port multiplexer
0x080 - 0x0BC
CPU input event configuration
All the registers can be accessed with word (32-bit), half-word (16-bit) and byte (8-bit)
access.
12.5.1
EXTI rising trigger selection register (EXTI_RTSR1)
Address offset: 0x000
Reset value: 0x0000 0000
Contains only register bits for configurable events.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
RT21
RT20
RT19
RT18
RT17
RT16
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RT15
RT14
RT13
RT12
RT11
RT10
RT9
RT8
RT7
RT6
RT5
RT4
RT3
RT2
RT1
RT0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:22 Reserved, must be kept at reset value.
Bits 21:0 RTx: Rising trigger event configuration bit of configurable line x (x = 21 to 0)
Each bit enables/disables the rising edge trigger for the event and interrupt on the
corresponding line.
0: Disable
1: Enable
Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on
STM32U031xx devices.
RM0503 Rev 2
311/1325
318
Extended interrupt and event controller (EXTI)
12.5.2
RM0503
EXTI falling trigger selection register 1 (EXTI_FTSR1)
Address offset: 0x004
Reset value: 0x0000 0000
Contains only register bits for configurable events.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
FT21
FT20
FT19
FT18
FT17
FT16
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FT15
FT14
FT13
FT12
FT11
FT10
FT9
FT8
FT7
FT6
FT5
FT4
FT3
FT2
FT1
FT0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:22 Reserved, must be kept at reset value.
Bits 21:0 FTx: Falling trigger event configuration bit of configurable line x (x = 21 to 0)
Each bit enables/disables the falling edge trigger for the event and interrupt on the
corresponding line.
0: Disable
1: Enable
Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on
STM32U031xx devices.
12.5.3
EXTI software interrupt event register 1 (EXTI_SWIER1)
Address offset: 0x008
Reset value: 0x0000 0000
Contains only register bits for configurable events.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
SWI21
SWI20
SWI19
SWI18
SWI17
SWI16
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SWI15
SWI14
SWI13
SWI12
SWI11
SWI10
SWI9
SWI8
SWI7
SWI6
SWI5
SWI4
SWI3
SWI2
SWI1
SWI0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:22 Reserved, must be kept at reset value.
Bits 21:0 SWIx: Software rising edge event trigger on line x (x = 21 to 0)
Setting of any bit by software triggers a rising edge event on the corresponding line x,
resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits
are automatically cleared by HW. Reading of any bit always returns 0.
0: No effect
1: Rising edge event generated on the corresponding line, followed by an interrupt
Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on
STM32U031xx devices.
312/1325
RM0503 Rev 2
RM0503
Extended interrupt and event controller (EXTI)
12.5.4
EXTI rising edge pending register 1 (EXTI_RPR1)
Address offset: 0x00C
Reset value: 0x0000 0000
Contains only register bits for configurable events.
31
30
29
28
27
26
25
24
23
22
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RPIF15 RPIF14 RPIF13 RPIF12 RPIF11 RPIF10
RPIF9
RPIF8
RPIF7
RPIF6
RPIF5
RPIF4
RPIF3
RPIF2
RPIF1
RPIF0
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
21
20
19
18
17
16
RPIF21 RPIF20 RPIF19 RPIF18 RPIF17 RPIF16
Bits 31:22 Reserved, must be kept at reset value.
Bits 21:0 RPIFx: Rising edge event pending for configurable line x (x = 21 to 0)
Each bit is set upon a rising edge event generated by hardware or by software (through the
EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it.
0: No rising edge trigger request occurred
1: Rising edge trigger request occurred
Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on
STM32U031xx devices.
12.5.5
EXTI falling edge pending register 1 (EXTI_FPR1)
Address offset: 0x010
Reset value: 0x0000 0000
Contains only register bits for configurable events.
31
30
29
28
27
26
25
24
23
22
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
FPIF15 FPIF14 FPIF13 FPIF12 FPIF11 FPIF10
FPIF9
FPIF8
FPIF7
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
21
20
19
18
17
16
FPIF21 FPIF20 FPIF19 FPIF18 FPIF17
FPIF16
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
5
4
3
2
1
0
FPIF6
FPIF5
FPIF4
FPIF3
FPIF2
FPIF1
FPIF0
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
Bits 31:22 Reserved, must be kept at reset value.
Bits 21:0 FPIFx: Falling edge event pending for configurable line x (x = 21 to 0)
Each bit is set upon a falling edge event generated by hardware or by software (through the
EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it.
0: No falling edge trigger request occurred
1: Falling edge trigger request occurred
Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on
STM32U031xx devices.
RM0503 Rev 2
313/1325
318
Extended interrupt and event controller (EXTI)
12.5.6
RM0503
EXTI external interrupt selection register x (EXTI_EXTICRx)
Address offset: 0x060 + 0x4 * (x - 1), (x = 1 to 4)
Reset value: 0x0000 0000
EXTIm fields contain only the number of bits in line with the nb_ioport configuration.
31
30
29
28
27
26
25
24
23
22
21
EXTI{4 * (x - 1) + 3}[7:0]
20
19
18
17
16
EXTI{4 * (x - 1) + 2}[7:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
EXTI{4 * (x - 1) + 1}[7:0]
rw
rw
rw
rw
rw
EXTI{4 * (x - 1)}[7:0]
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:24 EXTI{4 * (x - 1) + 3}[7:0]: EXTI{4 * (x - 1) + 3} GPIO port selection
These bits are written by software to select the source input for EXTI{4 * (x - 1) + 3} external
interrupt.
0x00: PA[4 * (x - 1) + 3] pin
0x01: PB[4 * (x - 1) + 3] pin
0x02: PC[4 * (x - 1) + 3] pin
0x03: PD[4 * (x - 1) + 3] pin
0x04: reserved, must not be used
0x05: PF[4 * (x - 1) + 3] pin
Others: reserved, must not be used
Bits 23:16 EXTI{4 * (x - 1) + 2}[7:0]: EXTI{4 * (x - 1) + 2} GPIO port selection
These bits are written by software to select the source input for EXTI{4 * (x - 1) + 2} external
interrupt.
0x00: PA[4 * (x - 1) + 2] pin
0x01: PB[4 * (x - 1) + 2] pin
0x02: PC[4 * (x - 1) + 2] pin
0x03: PD[4 * (x - 1) + 2] pin
0x04: reserved, must not be used
0x05: PF[4 * (x - 1) + 2] pin
Others: reserved, must not be used
Bits 15:8 EXTI{4 * (x - 1) + i}[7:0]: EXTI{4 * (x - 1) + 1} GPIO port selection
These bits are written by software to select the source input for EXTI{4 * (x - 1) + 1} external
interrupt.
0x00: PA[4 * (x - 1) + 1] pin
0x01: PB[4 * (x - 1) + 1] pin
0x02: PC[4 * (x - 1) + 1] pin
0x03: PD[4 * (x - 1) + 1] pin
0x04: reserved, must not be used
0x05: PF[4 * (x - 1) + 1] pin
Others: reserved, must not be used
314/1325
RM0503 Rev 2
RM0503
Extended interrupt and event controller (EXTI)
Bits 7:0 EXTI{4 * (x - 1)}[7:0]: EXTI{4 * (x - 1)} GPIO port selection
These bits are written by software to select the source input for EXTI{4 * (x - 1)} external
interrupt.
0x00: PA[4 * (x - 1)] pin
0x01: PB[4 * (x - 1)] pin
0x02: PC[4 * (x - 1)] pin
0x03: PD[4 * (x - 1)] pin
0x04: reserved, must not be used
0x05: PF[4 * (x - 1)] pin
Others: reserved, must not be used
12.5.7
EXTI CPU wake-up with interrupt mask register (EXTI_IMR1)
Address offset: 0x080
Reset value: 0xFFF8 0000
Contains register bits for configurable events and direct events.
The reset value is set such as to, by default, enable interrupt from direct lines, and disable
interrupt from configurable lines.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
IM31
IM30
IM29
IM28
IM27
IM26
IM25
IM24
IM23
IM22
IM21
IM20
IM19
IM18
IM17
IM16
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IM15
IM14
IM13
IM12
IM11
IM10
IM9
IM8
IM7
IM6
IM5
IM4
IM3
IM2
IM1
IM0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:0 IMx: CPU wake-up with interrupt mask on line x (x = 31 to 0)
Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on
the corresponding line.
0: wake-up with interrupt masked
1: wake-up with interrupt unasked
Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on
STM32U031xx devices.
12.5.8
EXTI CPU wake-up with event mask register (EXTI_EMR1)
Address offset: 0x084
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
EM31
EM30
EM29
EM28
EM27
EM26
EM25
EM24
EM23
EM22
EM21
EM20
EM19
EM18
EM17
EM16
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
EM15
EM14
EM13
EM12
EM11
EM10
EM9
EM8
EM7
EM6
EM5
EM4
EM3
EM2
EM1
EM0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
RM0503 Rev 2
315/1325
318
Extended interrupt and event controller (EXTI)
RM0503
Bits 31:0 EMx: CPU wake-up with event generation mask on line x (x = 31 to 0)
Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the
corresponding line.
0: wake-up with event generation masked
1: wake-up with event generation unmasked
Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on
STM32U031xx devices.
12.5.9
EXTI CPU wake-up with interrupt mask register (EXTI_IMR2)
Address offset: 0x090
Reset value: 0xFFFF FFFF
Contains register bits for configurable events and direct events.
The reset value is set such as to, by default, enable interrupt from direct lines, and disable
interrupt from configurable lines.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
IM37
IM36
IM35
IM34
IM33
IM32
rw
rw
rw
rw
rw
rw
Bits 31:6 Reserved, must be kept at reset value.
Bits 5:0 IMx: CPU wake-up with interrupt mask on line x (x = 37 to 32)
Setting/clearing this bit unmasks/masks the CPU wake-up with interrupt, by an event on the
corresponding line.
0: wake-up with interrupt request from Line x is masked
1: wake-up with interrupt request from Line x is unmasked
Bit IM36 is available only on STM32U0x3xx devices, it is reserved on STM32U031xx devices.
12.5.10
EXTI CPU wake-up with event mask register (EXTI_EMR2)
Address offset: 0x094
Reset value: 0x0000 0000
Contains register bits for configurable events and direct events.
The reset value is set such as to, by default, enable interrupt from direct lines, and disable
interrupt from configurable lines.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
EM37
EM36
EM35
EM34
EM33
EM32
rw
rw
rw
rw
rw
rw
316/1325
RM0503 Rev 2
RM0503
Extended interrupt and event controller (EXTI)
Bits 31:6 Reserved, must be kept at reset value.
Bits 5:0 EMx: CPU wake-up with event generation mask on line x, (x = 37 to 32)
Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the
corresponding line.
0: wake-up with event generation masked
1: wake-up with event generation unmasked
Bit IM36 is available only on STM32U0x3xx devices, it is reserved on STM32U031xx
devices.
12.5.11
EXTI register map
The following table gives the EXTI register map and the reset values.
Res.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
0
0
0
EXTI1[7:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
EXTI_IMR1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EXTI12[7:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Res.
0
0
Res.
0
0
Res.
0
Reserved
0
EXTI8[7:0]
EXTI13[7:0]
Res.
EXTI14[7:0]
0
0
EXTI4[7:0]
EXTI9[7:0]
0
0
EXTI0[7:0]
EXTI5[7:0]
Res.
EXTI15[7:0]
0
0
0
0
0
0
EXTI10[7:0]
0
0
0
Reset value
Reset value
0
Res.
0
0
Res.
0
0
Res.
0
0
Res.
EXTI_EXTICR4
0
0
Res.
0
0
FPIF[21:0].
0
EXTI11[7:0]
0
0
EXTI6[7:0]
0
0
Res.
0
0
Res.
0
0
Res.
0
0
Res.
0
0
Res.
0
0
Res.
0
0
Res.
0
0
Res.
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
0
Res.
0x080
0
0
Res.
0x0700x07C
0
0
EXTI2[7:0]
EXTI7[7:0]
EXTI_EXTICR3
Reset value
0x06C
0
EXTI_EXTICR2
Reset value
0x068
EXTI3[7:0]
0
0
Res.
Reset value
0x064
Res.
EXTI_EXTICR1
0
Res.
0x060
Reserved
Res.
Reset value
0x0140x05C
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
EXTI_FPR1
0
RPIF[21:0]
0
Res.
Reset value
0x010
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
EXTI_RPR1
0
SWI[21:0]
0
Res.
Reset value
0x00C
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
EXTI_SWIER1
0
FT[21:0]
0
Res.
Reset value
0x008
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
EXTI_FTSR1
Res.
0x004
0
Res.
Reset value
RT[21:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
EXTI_RTSR1
Res.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x000
Register
Res.
Offset
Res.
Table 61. EXTI controller register map and reset values
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IM[31:0]
1
1
1
1
1
1
1
1
1
1
0
0
RM0503 Rev 2
0
0
0
317/1325
318
0x094
318/1325
EXTI_EMR2
RM0503 Rev 2
Refer to Section 2.2 on page 55 for the register boundary addresses.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
IM36
IM35
IM34
IM33
IM32
1
1
1
1
1
1
EM36
EM35
EM34
EM33
EM32
Reset value
IM37
Reset value
0
EM37
Res.
0
Res.
Res.
0
Res.
Res.
Res.
0
Res.
Res.
Res.
0
Res.
Res.
Res.
0
Res.
Res.
Res.
0
Res.
Res.
Res.
0
Res.
Res.
Res.
0
Res.
Res.
Res.
0
Res.
Res.
Res.
0
Res.
Res.
Res.
0
Res.
Res.
Res.
0
Res.
Res.
Res.
0
Res.
Res.
Res.
0
Res.
Res.
Res.
0
Res.
Res.
Res.
0
Res.
Res.
Res.
0
Res.
Res.
Res.
0
Res.
Res.
Res.
0
Res.
Res.
Res.
0
Res.
Res.
Res.
0
Res.
Res.
Res.
0
Res.
Res.
Res.
0
Res.
Res.
EXTI_IMR2
Res.
0
Res.
Res.
Reset value
Res.
Res.
0x090
Reserved
Res.
0x0880x08C
Res.
Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x084
Res.
Offset
Res.
Extended interrupt and event controller (EXTI)
RM0503
Table 61. EXTI controller register map and reset values (continued)
EXTI_EMR1
EM[31:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
RM0503
Cyclic redundancy check calculation unit (CRC)
13
Cyclic redundancy check calculation unit (CRC)
13.1
Introduction
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from 8-, 16or 32-bit data word and a generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the functional safety standards, they offer a means of
verifying the flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link
time and stored at a given memory location.
13.2
CRC main features
•
Uses CRC-32 (Ethernet) polynomial: 0x4C11DB7
X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 +X8 + X7 + X5 + X4 + X2+ X +1
•
Alternatively, uses fully programmable polynomial with programmable size (7, 8, 16, 32
bits)
•
Handles 8-,16-, 32-bit data size
•
Programmable CRC initial value
•
Single input/output 32-bit data register
•
Input buffer to avoid bus stall during calculation
•
CRC computation done in 4 AHB clock cycles (HCLK) for the 32-bit data size
•
General-purpose 8-bit register (can be used for temporary storage)
•
Reversibility options on I/O data
•
Accessed through AHB slave peripheral by 32-bit words only, with the exception of
CRC_DR register that can be accessed by words, right-aligned half-words and rightaligned bytes
RM0503 Rev 2
319/1325
325
Cyclic redundancy check calculation unit (CRC)
13.3
CRC functional description
13.3.1
CRC block diagram
RM0503
Figure 30. CRC calculation unit block diagram
32-bit AHB bus
read access
write access
Data register
(output)
crc_hclk
32-bit accesses
Data register
(input)
CRC_INIT
CRC_CR
CRC computation
CRC_POL
CRC_IDR
MS19882V3
13.3.2
CRC internal signals
Table 62. CRC internal input/output signals
13.3.3
Signal name
Signal type
crc_hclk
Digital input
Description
AHB clock
CRC operation
The CRC calculation unit has a single 32-bit read/write data register (CRC_DR). It is used to
input new data (write access), and holds the result of the previous CRC calculation (read
access).
Each write operation to the data register creates a combination of the previous CRC value
(stored in CRC_DR) and the new one. CRC computation is done on the whole 32-bit data
word or byte by byte depending on the format of the data being written.
The CRC_DR register can be accessed by word, right-aligned half-word and right-aligned
byte. When the RTYPE_IN bit is set in CRC_CR, non-word accesses to CRC_DR register
are ignored. For the other registers only 32-bit accesses are allowed.
The duration of the computation depends on data width:
•
4 AHB clock cycles for 32 bits
•
2 AHB clock cycles for 16 bits
•
1 AHB clock cycles for 8 bits
An input buffer allows a second data to be immediately written without waiting for any
wait-states due to the previous CRC calculation.
320/1325
RM0503 Rev 2
RM0503
Cyclic redundancy check calculation unit (CRC)
The data size can be dynamically adjusted to minimize the number of write accesses for a
given number of bytes. For instance, a CRC for 5 bytes can be computed with a word write
followed by a byte write.
The input data can be reversed to manage the various endianness schemes. The reversing
operation can be performed on 8 bits, 16 bits and 32 bits depending on the REV_IN[1:0] bits
in the CRC_CR register. If RTYPE_IN bit is set in this register, the input reversing operation
can be performed with a byte or half-word granularity, but not with single bit granularity.
For example, with RTYPE_IN cleared, 0x1A2B3C4D input data are used for CRC
calculation as:
•
0x58D43CB2 with bit-reversal done by byte (REV_IN[1:0] = 01)
•
0xD458B23C with bit-reversal done by half-word (REV_IN[1:0] = 10)
•
0xB23CD458 with bit-reversal done on the full word (REV_IN[1:0] = 11)
With RTYPE_IN set, 0x1A2B3C4D input data are used for CRC calculation as:
•
0x3C4D1A2B with half-word reversal done by word (REV_IN[1:0] = 01)
•
0x4D3C2B1A with byte-reversal done by word (REV_IN[1:0] = 10)
The output data can also be reversed by setting the REV_OUT[1:0] bits in the CRC_CR
register. If RTYPE_OUT is set in this register, the output reversing operation is performed
with a byte or half-word granularity, but not with single bit granularity.
With RTYPE_OUT cleared, the operation is done at bit level. For example, 0x11223344
output data are converted to 0x22CC4488.
With RTYPE_OUT set, 0x11223344 output data are converted as:
•
0x33441122 with half-word reversal done by word (REV_IN[1:0] = 01)
•
0x44332211 with byte-reversal done by word (REV_IN[1:0] = 10)
The CRC calculator can be initialized to a programmable value using the RESET control bit
in the CRC_CR register (the default value is 0xFFFFFFFF).
The initial CRC value can be programmed with the CRC_INIT register. The CRC_DR
register is automatically initialized upon CRC_INIT register write access.
The CRC_IDR register can be used to hold a temporary value related to CRC calculation. It
is not affected by the RESET bit in the CRC_CR register.
Polynomial programmability
The polynomial coefficients are fully programmable through the CRC_POL register, and the
polynomial size can be configured to be 7, 8, 16 or 32 bits by programming the
POLYSIZE[1:0] bits in the CRC_CR register. Even polynomials are not supported.
Note:
The type of an even polynomial is X+X2+..+Xn, while the type of an odd polynomial is
1+X+X2+..+Xn.
If the CRC data is less than 32-bit, its value can be read from the least significant bits of the
CRC_DR register.
To obtain a reliable CRC calculation, the change on-fly of the polynomial value or size can
not be performed during a CRC calculation. As a result, if a CRC calculation is ongoing, the
application must either reset it or perform a CRC_DR read before changing the polynomial.
The default polynomial value is the CRC-32 (Ethernet) polynomial: 0x4C11DB7.
RM0503 Rev 2
321/1325
325
Cyclic redundancy check calculation unit (CRC)
13.4
RM0503
CRC registers
The CRC_DR register can be accessed by words, right-aligned half-words and right-aligned
bytes when RTYPE bit is cleared in CRC_CR. When RTYPE is set, only word accesses are
allowed. For the other registers only 32-bit accesses are allowed.
13.4.1
CRC data register (CRC_DR)
Address offset: 0x00
Reset value: 0xFFFF FFFF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
DR[31:16]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
DR[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:0 DR[31:0]: Data register bits
This register is used to write new data to the CRC calculator.
It holds the previous CRC calculation result when it is read.
If the data size is less than 32 bits, the least significant bits are used to write/read the correct
value.
13.4.2
CRC independent data register (CRC_IDR)
Address offset: 0x04
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
IDR[31:16]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
IDR[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:0 IDR[31:0]: General-purpose 32-bit data register bits
These bits can be used as a temporary storage location for four bytes.
This register is not affected by CRC resets generated by the RESET bit in the CRC_CR
register
322/1325
RM0503 Rev 2
RM0503
Cyclic redundancy check calculation unit (CRC)
13.4.3
CRC control register (CRC_CR)
Address offset: 0x08
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
RESET
Res.
Res.
Res.
Res.
Res.
RTYPE RTYPE
_OUT
_IN
rw
rw
REV_OUT[1:0]
REV_IN[1:0]
rw
rw
rw
POLYSIZE[1:0]
rw
rw
rw
rs
Bits 31:11 Reserved, must be kept at reset value.
Bit 10 RTYPE_OUT: Reverse type output
This bit controls the reversal granularity of the output data.
0: Bit level output
1: Byte or half-word level output
Bit 9 RTYPE_IN: Reverse type input
This bit controls the reversal granularity of the input data.
0: Bit level input
1: Byte or half-word level input
Bits 8:7 REV_OUT[1:0]: Reverse output data
This bitfield controls the reversal of the bit order of the output data.
00: Bit order not affected (RTYPE_OUT = 0 or 1)
01: Bit-reversed output format (RTYPE_OUT = 0) or half-word reversal done by word
(RTYPE_OUT = 1)
10: Bit order not affected (RTYPE_OUT = 0) or byte reversal done by word
(RTYPE_OUT = 1)
11: Bit order not affected (RTYPE_OUT = 0 or 1)
Bits 6:5 REV_IN[1:0]: Reverse input data
This bitfield controls the reversal of the bit order of the input data
00: Bit order not affected (RTYPE_IN = 0 or 1)
01: Bit reversal done by byte (RTYPE_IN = 0) or half-word reversal done by word
(RTYPE_IN = 1)
10: Bit reversal done by half-word (RTYPE_IN = 0) or byte reversal done by word
(RTYPE_IN = 1)
11: Bit reversal done by word (RTYPE_IN = 0) or bit order is not affected (RTYPE_IN = 1)
RM0503 Rev 2
323/1325
325
Cyclic redundancy check calculation unit (CRC)
RM0503
Bits 4:3 POLYSIZE[1:0]: Polynomial size
These bits control the size of the polynomial.
00: 32 bit polynomial
01: 16 bit polynomial
10: 8 bit polynomial
11: 7 bit polynomial
Bits 2:1 Reserved, must be kept at reset value.
Bit 0 RESET: RESET bit
This bit is set by software to reset the CRC calculation unit and set the data register to the
value stored in the CRC_INIT register. This bit can only be set, it is automatically cleared by
hardware
13.4.4
CRC initial value (CRC_INIT)
Address offset: 0x10
Reset value: 0xFFFF FFFF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
CRC_INIT[31:16]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
22
21
20
19
18
17
16
CRC_INIT[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:0 CRC_INIT[31:0]: Programmable initial CRC value
This register is used to write the CRC initial value.
13.4.5
CRC polynomial (CRC_POL)
Address offset: 0x14
Reset value: 0x04C1 1DB7
31
30
29
28
27
26
25
24
23
POL[31:16]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
POL[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:0 POL[31:0]: Programmable polynomial
This register is used to write the coefficients of the polynomial to be used for CRC
calculation.
If the polynomial size is less than 32 bits, the least significant bits have to be used to program
the correct value.
324/1325
RM0503 Rev 2
RM0503
13.4.6
Cyclic redundancy check calculation unit (CRC)
CRC register map
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CRC_CR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
0x10
CRC_INIT
Reset value
0x14
0
0
0
0
0
0
0
0
CRC_INIT[31:0]
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CRC_POL
Reset value
0
Res.
0
POLYSIZE[1:0]
0
REV_IN[1:0]
0
REV_OUT[0]
0
REV_OUT[1]
Reset value
Res.
IDR[31:0]
Res.
CRC_IDR
1
Res.
0x08
1
Res.
0x04
1
RTYPE_OUT[1]
Reset value
Res.
DR[31:0]
RESET
CRC_DR
Res.
0x00
Register
name
RTYPE_IN[1]
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 63. CRC register map and reset values
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
1
0
1
1
0
1
1
1
POL[31:0]
0
0
0
0
0
1
0
0
1
1
0
0
0
0
0
1
0
0
Refer to Section 2.2 on page 55 for the register boundary addresses.
RM0503 Rev 2
325/1325
325
Analog-to-digital converter (ADC)
RM0503
14
Analog-to-digital converter (ADC)
14.1
Introduction
The 12-bit ADC is a successive approximation analog-to-digital converter. It has up to 20
multiplexed channels allowing it to measure signals from 16 external and 4 internal sources.
A/D conversion of the various channels can be performed in single, continuous, scan or
discontinuous mode. The result of the ADC is stored in a left-aligned or right-aligned 16-bit
data register.
The analog watchdog feature allows the application to detect if the input voltage goes
outside the user-defined higher or lower thresholds.
An efficient low-power mode is implemented to allow very low consumption at low
frequency.
A built-in hardware oversampler allows analog performances to be improved while offloading the related computational burden from the CPU.
326/1325
RM0503 Rev 2
RM0503
14.2
Analog-to-digital converter (ADC)
ADC main features
•
•
•
•
•
High performance
–
12-bit, 10-bit, 8-bit or 6-bit configurable resolution
–
ADC conversion time: 0.4 µs for 12-bit resolution (2.5Msps), faster conversion
times can be obtained by lowering resolution.
–
Self-calibration
–
Programmable sampling time
–
Data alignment with built-in data coherency
–
DMA support
Low-power
–
The application can reduce PCLK frequency for low-power operation while still
keeping optimum ADC performance. For example, 0.4 µs conversion time is kept,
whatever the PCLK frequency
–
Wait mode: prevents ADC overrun in applications with low PCLK frequency
–
Auto off mode: ADC is automatically powered off except during the active
conversion phase. This dramatically reduces the power consumption of the ADC.
Analog input channels
–
16 external analog inputs
–
1 channel for internal temperature sensor (VSENSE)
–
1 channel for internal reference voltage (VREFINT)
–
1 channel for monitoring external VBAT power supply pin
–
1 channel for monitoring DAC internal channel input
Start-of-conversion can be initiated:
–
By software
–
By hardware triggers with configurable polarity (timer events or GPIO input
events)
Conversion modes
–
Can convert a single channel or can scan a sequence of channels.
–
Single mode converts selected inputs once per trigger
–
Continuous mode converts selected inputs continuously
–
Discontinuous mode
•
Interrupt generation at the end of sampling, end of conversion, end of sequence
conversion, and in case of analog watchdog or overrun events
•
Analog watchdog
•
Oversampler
•
–
16-bit data register
–
Oversampling ratio adjustable from 2 to 256x
–
Programmable data shift up to 8-bits
ADC input range: VSSA ≤ VIN ≤ VREF+
RM0503 Rev 2
327/1325
384
Analog-to-digital converter (ADC)
14.3
RM0503
ADC implementation
Table 64. ADC main features
ADC modes/features
328/1325
STM32U0xx
Resolution
12 bits
Maximum sampling speed
2.5 Msps
Hardware offset calibration
X
Single-ended inputs
X
Differential inputs
-
Oversampling mode
X
Data register
16 bits
DMA support
X
Number of analog watchdogs
3
Number of external channels
16
Number of internal channels
4
RM0503 Rev 2
RM0503
14.4
Analog-to-digital converter (ADC)
ADC functional description
Figure 31 shows the ADC block diagram and Table 65 gives the ADC pin description.
Figure 31. ADC block diagram
Analog
supply VREF+
(VDDA)
AUTOFF
Auto-off mode
CONT
single/continuous
VBAT/3
dac_out1
VREFINT
VSENSE
ADC_IN[18:14,
10:0]
Input
selection &
Analog input scan
channels control
VIN[X]
Suppy and
reference
LFTRIG
ADCAL selfcalibration
VIN
SMP[2:0]
sampling time
SAR ADC
slave
DMA request
DMAEN
DMACFG
Oversampler
CONVERTED
DATA
start
Start & Stop
control
AUTDLY
Auto-delayed
conversion
ADSTP
stop conversion
AHB
interface
APB
interface
DATA[15:0]
ADC interrupt
AHB
ADEN/ADDIS
SCANDIR
up/down
CHSEL[19:0]
ADREADY
EOSMP
EOS
EOC
OVR
AWDx
ADC_AWDx
_OUT
to analog
watchdogs
OVRMOD
(overrun mode)
ALIGN
(left/right)
RES[1:0]
(12, 10, 8 bits)
ADSTART
SW trigger
AWDxEN
AWDxSGL
AWDCHx[4:0]
LTx[11:0]
TOVS
TRG0
OVSS[3:0]
TRG1
OVSR[2:0]
TRG2
HW
TRG3
TRG4
TRG5
HTx[11:0]
EXTEN[1:0] trigger
trigger enable
and edge selection
DISCEN
Discontinuous
mode enable
OVSE
TRG6
TRG7
EXTSEL[2:0]
trigger selection
MSv71275V1
1. TRGi are mapped at product level. Refer to Table External triggers in Section 14.4.1: ADC pins and internal signals.
RM0503 Rev 2
329/1325
384
Analog-to-digital converter (ADC)
14.4.1
RM0503
ADC pins and internal signals
Table 65. ADC input/output pins
Name
Signal type
Remarks
VDDA
Input, analog power
supply
Analog power supply and positive reference voltage
for the ADC
VSSA
Input, analog supply
ground
Ground for analog power supply
VREF+
Input, analog reference
positive
The higher/positive reference voltage for the ADC.
ADC_INx
Analog input signals
16 external analog input channels
Table 66. ADC internal input/output signals
Internal signal
name
Signal type
VIN[x]
Analog Input
channels
TRGx
Input
ADC conversion triggers
VSENSE
Input
Internal temperature sensor output voltage
VREFINT
Input
Internal voltage reference output voltage
VBAT/3
Input
VBAT pin input voltage divided by 3
dac_out1
Input
DAC internal channel1 input
ADC_AWDx_OUT
Output
Internal analog watchdog output signal connected to onchip timers (x = Analog watchdog number = 1,2,3)
Description
Connected either to internal channels or to ADC_INi
external channels
Table 67. External triggers
Name
330/1325
Source
EXTSEL[2:0]
TRG0
TIM1_TRGO2
000
TRG1
TIM1_CC4
001
TRG2
TIM2_TRGO
010
TRG3
TIM3_TRGO
011
TRG4
TIM15_TRGO
100
TRG5
TIM6_TRGO
101
TRG6
Reserved
110
TRG7
EXTI11
111
RM0503 Rev 2
RM0503
14.4.2
Analog-to-digital converter (ADC)
ADC voltage regulator (ADVREGEN)
The ADC has a specific internal voltage regulator which must be enabled and stable before
using the ADC.
The ADC internal voltage regulator can be enabled by setting ADVREGEN bit to 1 in the
ADC_CR register. The software must wait for the ADC voltage regulator startup time
(tADCVREG_STUP) before launching a calibration or enabling the ADC. This delay must be
managed by software (for details on tADCVREG_STUP, refer to the device datasheet).
After ADC operations are complete, the ADC is disabled (ADEN = 0). To keep power
consumption low, it is important to disable the ADC voltage regulator before entering lowpower mode (LPRun, LPSleep or Stop mode). Refer to Section : ADC voltage regulator
disable sequence).
Note:
When the internal voltage regulator is disabled, the internal analog calibration is kept.
Analog reference from the power control unit
The internal ADC voltage regulator internally uses an analog reference delivered by the
power control unit through a buffer. This buffer is always enabled when the main voltage
regulator of the power control unit operates in normal Run mode (refer to Reset and clock
control and power control sections).
If the main voltage regulator enters low-power mode (such as Low-power run mode), this
buffer is disabled and the ADC cannot be used.
ADC Voltage regulator enable sequence
To enable the ADC voltage regulator, set ADVREGEN bit to 1 in ADC_CR register.
ADC voltage regulator disable sequence
To disable the ADC voltage regulator, follow the sequence below:
14.4.3
1.
Make sure that the ADC is disabled (ADEN = 0).
2.
Clear ADVREGEN bit in ADC_CR register.
Calibration (ADCAL)
The ADC has a calibration feature. During the procedure, the ADC calculates a calibration
factor which is internally applied to the ADC until the next ADC power-off. The application
must not use the ADC during calibration and must wait until it is complete.
Calibration should be performed before starting A/D conversion. It removes the offset error
which may vary from chip to chip due to process variation.
The calibration is initiated by software by setting bit ADCAL to 1. It can be initiated only
when all the following conditions are met:
•
the ADC voltage regulator is enabled (ADVREGEN = 1 and LDORDY = 1),
•
the ADC is disabled (ADEN = 0), and
•
the Auto-off mode is disabled (AUTOFF = 0).
ADCAL bit stays at 1 during all the calibration sequence. It is then cleared by hardware as
soon the calibration completes. After this, the calibration factor can be read from the
ADC_DR register (from bits 6 to 0).
RM0503 Rev 2
331/1325
384
Analog-to-digital converter (ADC)
RM0503
The internal analog calibration is kept if the ADC is disabled (ADEN = 0). When the ADC
operating conditions change (VREF+ changes are the main contributor to ADC offset
variations and temperature change to a lesser extend), it is recommended to re-run a
calibration cycle.
The calibration factor is lost in the following cases:
•
The power supply is removed from the ADC (for example when the product enters
Standby or VBAT mode)
•
The ADC peripheral is reset.
The calibration factor is lost each time power is removed from the ADC (for example when
the product enters Standby or VBAT mode). Still, it is possible to save and restore the
calibration factor by software to save time when re-starting the ADC (as long as temperature
and voltage are stable during the ADC power-down).
The calibration factor can be written if the ADC is enabled but not converting (ADEN = 1 and
ADSTART = 0). Then, at the next start of conversion, the calibration factor is automatically
injected into the analog ADC. This loading is transparent and does not add any cycle
latency to the start of the conversion.
Software calibration procedure
1.
Ensure that ADEN = 0, AUTOFF = 0, ADVREGEN = 1 and DMAEN = 0.
2.
Set ADCAL = 1.
3.
Wait until ADCAL = 0 (or until EOCAL = 1). This can be handled by interrupt if the
interrupt is enabled by setting the EOCALIE bit in the ADC_IER register
4.
The calibration factor can be read from bits 6:0 of ADC_DR or ADC_CALFACT
registers.
5.
To reduce the noise effect of the calibration factor extraction, the software can make
average of eight CALFACT[6:0] values (optional).
Figure 32. DC calibration
t CAB
ADCAL
ADC State
OFF
Startup
CALIBRATE
0x00
ADC_DR[6:0]
OFF
CALIBRATION
FACTOR
ADC_CALFACT[6:0]
by S/W
by H/W
MS33703V1
332/1325
RM0503 Rev 2
RM0503
Analog-to-digital converter (ADC)
Calibration factor forcing software procedure
1.
Ensure that ADEN = 1 and ADSTART = 0 (ADC started with no conversion ongoing)
2.
Write ADC_CALFACT with the saved calibration factor
3.
The calibration factor is used as soon as a new conversion is launched.
Figure 33. Calibration factor forcing
ADC state
Internal
calibration factor[6:0]
Start conversion
(hardware or software)
Ready (not converting)
Converting channel
Updating
(Single ended)
calibration
Ready
Converting channel
(Single ended)
F2
F1
WRITE ADC_CALFACT
CALFACT[6:0]
by S/W
F2
by H/W
MS31925V1
14.4.4
ADC on-off control (ADEN, ADDIS, ADRDY)
At power-up, the ADC is disabled and put in power-down mode (ADEN = 0).
As shown in Figure 34, the ADC needs a stabilization time of tSTAB before it starts
converting accurately.
Two control bits are used to enable or disable the ADC:
•
Set ADEN = 1 to enable the ADC. The ADRDY flag is set as soon as the ADC is ready
for operation.
•
Set ADDIS = 1 to disable the ADC and put the ADC in power down mode. The ADEN
and ADDIS bits are then automatically cleared by hardware as soon as the ADC is fully
disabled.
Conversion can then start either by setting ADSTART to 1 (refer to Section 14.5: Conversion
on external trigger and trigger polarity (EXTSEL, EXTEN)) or when an external trigger event
occurs if triggers are enabled.
Follow this procedure to enable the ADC:
1.
Clear the ADRDY bit in ADC_ISR register by programming this bit to 1.
2.
Set ADEN = 1 in the ADC_CR register.
3.
Wait until ADRDY = 1 in the ADC_ISR register (ADRDY is set after the ADC startup
time). This can be handled by interrupt if the interrupt is enabled by setting the
ADRDYIE bit in the ADC_IER register.
Follow this procedure to disable the ADC:
1.
Check that ADSTART = 0 in the ADC_CR register to ensure that no conversion is
ongoing. If required, stop any ongoing conversion by writing 1 to the ADSTP bit in the
ADC_CR register and waiting until this bit is read at 0.
2.
Set ADDIS = 1 in the ADC_CR register.
3.
If required by the application, wait until ADEN = 0 in the ADC_CR register, indicating
that the ADC is fully disabled (ADDIS is automatically reset once ADEN = 0).
4.
Clear the ADRDY bit in ADC_ISR register by programming this bit to 1 (optional).
RM0503 Rev 2
333/1325
384
Analog-to-digital converter (ADC)
RM0503
Figure 34. Enabling/disabling the ADC
ADEN
t STAB
ADR DY
ADDIS
ADC
stat
by S/W
OFF
Startup
RDY
CONVERTING CH
REQ
-OF
RDY
OFF
by H/W
MS30264V2
Note:
In Auto-off mode (AUTOFF = 1) the power-on/off phases are performed automatically, by
hardware and the ADRDY flag is not set.
When the bus clock is much faster than the analog ADC_CK clock, a minimum delay of ten
analog ADC_CK cycles must be respected between ADEN and ADDIS bit settings.
14.4.5
ADC clock (CKMODE, PRESC[3:0])
The ADC has a dual clock-domain architecture, so that the ADC can be fed with a clock
(ADC asynchronous clock) independent from the APB clock (PCLK).
Figure 35. ADC clock scheme
ADITF
RCC
(Reset & Clock Controller)
APB interface
PCLK
Bits CKMODE[1:0]
of ADC_CFGR2
ADC
asynchronous
clock
/1 or /2 or /4
Others
/1,2,4,6,8,10,12
16,32,64,128,256
00
Bits PRESC[3:0]
of ADC_CCR
Analog ADC_CK Analog
ADC
Bits CKMODE[1:0]
of ADC_CFGR2
MSv31926V2
1. Refer to Section Reset and clock control (RCC) for how the PCLK clock and ADC asynchronous clock are
enabled.
334/1325
RM0503 Rev 2
RM0503
Analog-to-digital converter (ADC)
The input clock of the analog ADC can be selected between two different clock sources (see
Figure 35: ADC clock scheme to see how the PCLK clock and the ADC asynchronous clock
are enabled):
a)
The ADC clock can be a specific clock source, named “ADC asynchronous clock“
which is independent and asynchronous with the APB clock.
Refer to RCC Section for more information on generating this clock source.
To select this scheme, bits CKMODE[1:0] of the ADC_CFGR2 register must be
reset.
b)
The ADC clock can be derived from the APB clock of the ADC bus interface,
divided by a programmable factor (1, 2 or 4) according to bits CKMODE[1:0].
To select this scheme, bits CKMODE[1:0] of the ADC_CFGR2 register must be
different from “00”.
In option a), the generated ADC clock can eventually be divided by a prescaler (1, 2, 4, 6, 8,
10, 12, 16, 32, 64, 128, 256) when programming the bits PRESC[3:0] in the ADC_CCR
register).
Option a) has the advantage of reaching the maximum ADC clock frequency whatever the
APB clock scheme selected.
Option b) has the advantage of bypassing the clock domain resynchronizations. This can be
useful when the ADC is triggered by a timer and if the application requires that the ADC is
precisely triggered without any uncertainty (otherwise, an uncertainty of the trigger instant is
added by the resynchronizations between the two clock domains).
Table 68. Latency between trigger and start of conversion(1)
Latency between the trigger event
and the start of conversion
ADC clock source
CKMODE[1:0]
SYSCLK, PLLPCLK, or
HSI16 clock(2)
00
Latency is not deterministic (jitter)
PCLK divided by 2
01
Latency is deterministic (no jitter) and equal to
3.25 ADC clock cycles
PCLK divided by 4
10
Latency is deterministic (no jitter) and equal to
3.125 ADC clock cycles
PCLK divided by 1
11
Latency is deterministic (no jitter) and equal to
3 ADC clock cycles
1. Refer to the device datasheet for the maximum ADC_CLK frequency.
2. Selected with ADCSEL bitfield of the RCC_CCIPR register.
Caution:
When selecting CKMODE[1:0] = 11 (PCLK divided by 1), the user must ensure that the
PCLK has a 50% duty cycle. This is done by selecting a system clock with a 50% duty cycle
and configuring the APB prescaler in bypass modes in the RCC (refer to there Reset and
clock controller section). If an internal source clock is selected, the AHB and APB prescalers
do not divide the clock.
RM0503 Rev 2
335/1325
384
Analog-to-digital converter (ADC)
14.4.6
RM0503
ADC connectivity
ADC inputs are connected to the external channels as well as internal sources as described
in Figure 36.
Figure 36. ADC connectivity
SRTM32U0xx
ADC
Channel selection
VIN[0]
ADC_IN0
VIN[1]
ADC_IN1
VIN[2]
ADC_IN2
VIN[3]
ADC_IN3
VIN[4]
ADC_IN4
VIN[5]
ADC_IN5
VIN[6]
ADC_IN6
VIN[7]
ADC_IN7
VIN[8]
ADC_IN8
VIN[9]
ADC_IN9
VDDA
VIN[10]
ADC_IN10
VSENSE
VREFINT
VBAT/3
VIN[11]
VIN[12]
VIN
SAR
ADC1
VIN[13]
ADC_IN14
VIN[14]
ADC_IN15
VIN[15]
ADC_IN16
VIN[16]
VSSA
VIN[17]
ADC_IN17
VIN[18]
ADC_IN18
dac_out1
VIN[19]
MSv71276V1
14.4.7
Configuring the ADC
The software must write the ADCAL and ADEN bits in the ADC_CR register and configure
the ADC_CFGR1 and ADC_CFGR2 registers only when the ADC is disabled (ADEN must
be cleared).
The software must only write to the ADSTART and ADDIS bits in the ADC_CR register only
if the ADC is enabled and there is no pending request to disable the ADC (ADEN = 1 and
ADDIS = 0).
336/1325
RM0503 Rev 2
RM0503
Analog-to-digital converter (ADC)
For all the other control bits in the ADC_IER, ADC_SMPR, ADC_CHSELR and ADC_CCR
registers, refer to the description of the corresponding control bit in Section 14.13: ADC
registers.
ADC_AWDTRx registers can be modified when conversion is ongoing.
The software must only write to the ADSTP bit in the ADC_CR register if the ADC is enabled
(and possibly converting) and there is no pending request to disable the ADC (ADSTART =
1 and ADDIS = 0).
Note:
There is no hardware protection preventing software from making write operations forbidden
by the above rules. If such a forbidden write access occurs, the ADC may enter an
undefined state. To recover correct operation in this case, the ADC must be disabled (clear
ADEN = 0 and all the bits in the ADC_CR register).
14.4.8
Channel selection (CHSEL, SCANDIR, CHSELRMOD)
There are up to 20 multiplexed channels:
•
16 analog inputs from GPIO pins (ADC_INx)
•
4 internal analog inputs (temperature sensor, internal reference voltage, DAC internal
channel1, VBAT channel)
It is possible to convert a single channel or a sequence of channels.
The sequence of the channels to be converted can be programmed in the ADC_CHSELR
channel selection register: each analog input channel has a dedicated selection bit
(CHSELx).
The ADC scan sequencer can be used in two different modes:
•
Sequencer not fully configurable:
The order in which the channels are scanned is defined by the channel number
(CHSELRMOD bit must be cleared in ADC_CFGR1 register):
•
–
Sequence length configured through CHSELx bits in ADC_CHSELR register
–
Sequence direction: the channels are scanned in a forward direction (from the
lowest to the highest channel number) or backward direction (from the highest to
the lowest channel number) depending on the value of SCANDIR bit
(SCANDIR = 0: forward scan, SCANDIR = 1: backward scan)
–
Any channel can belong to in these sequences
Sequencer fully configurable
The CHSELRMOD bit is set in ADC_CFGR1 register.
–
Sequencer length is up to 8 channels
–
The order in which the channels are scanned is independent from the channel
number. Any order can be configured through SQ1[3:0] to SQ8[3:0] bits in
ADC_CHSELR register.
–
Only channel 0 to channel 14 can be selected in this sequence
–
If the sequencer detects SQx[3:0] = 0b1111, the following SQx[3:0] registers are
ignored.
–
If no 0b1111 is programmed in SQx[3:0], the sequencer scans full eight channels.
After programming ADC CHSELR, SCANDIR and CHSELRMOD bits, it is mandatory to wait
for CCRDY flag before starting conversions. It indicates that the new channel setting has
RM0503 Rev 2
337/1325
384
Analog-to-digital converter (ADC)
RM0503
been applied. If a new configuration is required, the CCRDY flag must be cleared prior to
starting the conversion.
The software is allowed to program the CHSEL, SCANDIR, CHSELRMOD bits only when
ADSTART bit is cleared (which ensures that no conversion is ongoing).
Temperature sensor, DAC output, VREFINT and VBAT internal channels
The temperature sensor is connected to channel ADC VIN[11].
The internal voltage reference VREFINT is connected to channel ADC VIN[12].
VBAT channel is connected to ADC VIN[13] channel.
The internal dac_out1 output voltage is connected to ADC VIN[19] channel.
When VREF+ is lower than VDDA, this channel is not converted.
14.4.9
Programmable sampling time (SMPx[2:0])
Before starting a conversion, the ADC needs to establish a direct connection between the
voltage source to be measured and the embedded sampling capacitor of the ADC. This
sampling time must be enough for the input voltage source to charge the sample and hold
capacitor to the input voltage level.
Having a programmable sampling time allows the conversion speed to be trimmed
according to the input resistance of the input voltage source.
The ADC samples the input voltage for a number of ADC clock cycles that can be modified
using the SMP1[2:0] and SMP2[2:0] bits in the ADC_SMPR register.
Each channel can choose one out of two sampling times configured in SMP1[2:0] and
SMP2[2:0] bitfields, through SMPSELx bits in ADC_SMPR register.
The total conversion time is calculated as follows:
tCONV = Sampling time + 12.5 x ADC clock cycles
Example:
With ADC_CLK = 16 MHz and a sampling time of 1.5 ADC clock cycles:
tCONV = 1.5 + 12.5 = 14 ADC clock cycles = 0.875 µs
The ADC indicates the end of the sampling phase by setting the EOSMP flag.
14.4.10
Single conversion mode (CONT = 0)
In Single conversion mode, the ADC performs a single sequence of conversions, converting
all the channels once. This mode is selected when CONT = 0 in the ADC_CFGR1 register.
Conversion is started by either:
•
Setting the ADSTART bit in the ADC_CR register
•
Hardware trigger event
Inside the sequence, after each conversion is complete:
338/1325
•
The converted data are stored in the 16-bit ADC_DR register
•
The EOC (end of conversion) flag is set
•
An interrupt is generated if the EOCIE bit is set
RM0503 Rev 2
RM0503
Analog-to-digital converter (ADC)
After the sequence of conversions is complete:
•
The EOS (end of sequence) flag is set
•
An interrupt is generated if the EOSIE bit is set
Then the ADC stops until a new external trigger event occurs or the ADSTART bit is set
again.
Note:
To convert a single channel, program a sequence with a length of 1.
14.4.11
Continuous conversion mode (CONT = 1)
In continuous conversion mode, when a software or hardware trigger event occurs, the ADC
performs a sequence of conversions, converting all the channels once and then
automatically re-starts and continuously performs the same sequence of conversions. This
mode is selected when CONT = 1 in the ADC_CFGR1 register. Conversion is started by
either:
•
Setting the ADSTART bit in the ADC_CR register
•
Hardware trigger event
Inside the sequence, after each conversion is complete:
•
The converted data are stored in the 16-bit ADC_DR register
•
The EOC (end of conversion) flag is set
•
An interrupt is generated if the EOCIE bit is set
After the sequence of conversions is complete:
•
The EOS (end of sequence) flag is set
•
An interrupt is generated if the EOSIE bit is set
Then, a new sequence restarts immediately and the ADC continuously repeats the
conversion sequence.
Note:
To convert a single channel, program a sequence with a length of 1.
It is not possible to have both discontinuous mode and continuous mode enabled: it is
forbidden to set both bits DISCEN = 1 and CONT = 1.
14.4.12
Starting conversions (ADSTART)
Software starts ADC conversions by setting ADSTART = 1.
When ADSTART is set, the conversion:
•
Starts immediately if EXTEN = 00 (software trigger)
•
At the next active edge of the selected hardware trigger if EXTEN ≠ 00
The ADSTART bit is also used to indicate whether an ADC operation is currently ongoing. It
is possible to re-configure the ADC while ADSTART = 0, indicating that the ADC is idle.
RM0503 Rev 2
339/1325
384
Analog-to-digital converter (ADC)
RM0503
The ADSTART bit is cleared by hardware:
•
In single mode with software trigger (CONT = 0, EXTEN = 00)
–
•
In discontinuous mode with software trigger (CONT = 0, DISCEN = 1, EXTEN = 00)
–
•
At end of conversion (EOC = 1)
In all cases (CONT = x, EXTEN = XX)
–
Note:
At any end of conversion sequence (EOS = 1)
After execution of the ADSTP procedure invoked by software (see
Section 14.4.14: Stopping an ongoing conversion (ADSTP) on page 341)
In continuous mode (CONT = 1), the ADSTART bit is not cleared by hardware when the
EOS flag is set because the sequence is automatically relaunched.
When hardware trigger is selected in single mode (CONT = 0 and EXTEN = 01), ADSTART
is not cleared by hardware when the EOS flag is set (except if DMAEN = 1 and
DMACFG = 0 in which case ADSTART is cleared at end of the DMA transfer). This avoids
the need for software having to set the ADSTART bit again and ensures the next trigger
event is not missed.
After changing channel selection configuration (by programming ADC_CHSELR register or
changing CHSELRMOD or SCANDIR), it is mandatory to wait until CCRDY flag is asserted
before asserting ADSTART, otherwise the value written to ADSTART is ignored.
14.4.13
Timings
The elapsed time between the start of a conversion and the end of conversion is the sum of
the configured sampling time plus the successive approximation time depending on data
resolution:
tCONV = tSMPL + tSAR = [1.5 |min + 12.5 |12bit] x tADC_CLK
tCONV = tSMPL + tSAR = 42.9 ns |min + 357.1 ns |12bit = 0.400 µs |min (for fADC_CLK = 35 MHz)
Figure 37. Analog-to-digital conversion time
ADC state
RDY
Analog channel
Converting Ch(N)
Sampling Ch(N+1)
Ch(N+1)
Ch(N)
Internal S/H
ADSTART
Sampling Ch(N)
Sample AIN(N)
Hold AIN(N)
tSMPL(1)
tSAR(2)
Sample AIN(N+1)
Set by
SW
EOSMP
Set by
HW
Cleared
by SW
Set by
HW
EOC
ADC_DR
Data N-1
Cleared by
HW/SW
Data N
Indicative timings
MSv30532V2
1. tSMPL depends on SMP[2:0].
2. tSAR depends on RES[2:0].
340/1325
RM0503 Rev 2
RM0503
Analog-to-digital converter (ADC)
Figure 38. ADC conversion timings
ADSTART(1)
ADC state
tLATENCY (2)
Ready
S0
Conversion 0
S1
Conversion 1
WLATENCY (3)
S2
Conversion 2
WLATENCY (3)
S3
Conversion 3
WLATENCY (3)
ADC_DR
Data 0
Data 1
Data 2
MSv33174V1
1. EXTEN = 00 or EXTEN ≠ 00
2. Trigger latency (refer to datasheet for more details)
3. ADC_DR register write latency (refer to datasheet for more details)
14.4.14
Stopping an ongoing conversion (ADSTP)
The software can decide to stop any ongoing conversions by setting ADSTP = 1 in the
ADC_CR register.
This resets the ADC operation and the ADC is idle, ready for a new operation.
When the ADSTP bit is set by software, any ongoing conversion is aborted and the result is
discarded (ADC_DR register is not updated with the current conversion).
The scan sequence is also aborted and reset (meaning that restarting the ADC would restart a new sequence).
Once this procedure is complete, the ADSTP and ADSTART bits are both cleared by
hardware and the software must wait until ADSTART=0 before starting new conversions.
Figure 39. Stopping an ongoing conversion
ADC state
RDY
ADSTART
set by SW
SAMPLING CH(N)
CONVERTING CH(N)
set by SW
ADSTOP
ADC_DR
RDY
cleared by HW
cleared by HW
DATA N-1
MS30337V1
RM0503 Rev 2
341/1325
384
Analog-to-digital converter (ADC)
14.5
RM0503
Conversion on external trigger and trigger polarity (EXTSEL,
EXTEN)
A conversion or a sequence of conversion can be triggered either by software or by an
external event (for example timer capture). If the EXTEN[1:0] control bits are not equal to
“0b00”, then external events are able to trigger a conversion with the selected polarity. The
trigger selection is effective once software has set bit ADSTART = 1.
Any hardware triggers which occur while a conversion is ongoing are ignored.
If bit ADSTART = 0, any hardware triggers which occur are ignored.
Table 69 provides the correspondence between the EXTEN[1:0] values and the trigger
polarity.
Table 69. Configuring the trigger polarity
Source
Note:
EXTEN[1:0]
Trigger detection disabled
00
Detection on rising edge
01
Detection on falling edge
10
Detection on both rising and falling edges
11
The polarity of the external trigger can be changed only when the ADC is not converting
(ADSTART = 0).
The EXTSEL[2:0] control bits are used to select which of 8 possible events can trigger
conversions.
Refer to Table 67: External triggers in Section 14.4.1: ADC pins and internal signals for the
list of all the external triggers that can be used for regular conversion.
The software source trigger events can be generated by setting the ADSTART bit in the
ADC_CR register.
Note:
The trigger selection can be changed only when the ADC is not converting (ADSTART = 0).
14.5.1
Discontinuous mode (DISCEN)
This mode is enabled by setting the DISCEN bit in the ADC_CFGR1 register.
In this mode (DISCEN = 1), a hardware or software trigger event is required to start each
conversion defined in the sequence. On the contrary, if DISCEN = 0, a single hardware or
software trigger event successively starts all the conversions defined in the sequence.
342/1325
RM0503 Rev 2
RM0503
Analog-to-digital converter (ADC)
Example:
•
•
DISCEN = 1, channels to be converted = 0, 3, 7, 10
–
1st trigger: channel 0 is converted and an EOC event is generated
–
2nd trigger: channel 3 is converted and an EOC event is generated
–
3rd trigger: channel 7 is converted and an EOC event is generated
–
4th trigger: channel 10 is converted and both EOC and EOS events are
generated.
–
5th trigger: channel 0 is converted an EOC event is generated
–
6th trigger: channel 3 is converted and an EOC event is generated
–
...
DISCEN = 0, channels to be converted = 0, 3, 7, 10
–
1st trigger: the complete sequence is converted: channel 0, then 3, 7 and 10. Each
conversion generates an EOC event and the last one also generates an EOS
event.
–
Any subsequent trigger events restarts the complete sequence.
Note:
It is not possible to have both discontinuous mode and continuous mode enabled: it is
forbidden to set both bits DISCEN = 1 and CONT = 1.
14.5.2
Programmable resolution (RES) - Fast conversion mode
It is possible to obtain faster conversion times (tSAR) by reducing the ADC resolution.
The resolution can be configured to be either 12, 10, 8, or 6 bits by programming the
RES[1:0] bits in the ADC_CFGR1 register. Lower resolution allows faster conversion times
for applications where high data precision is not required.
Note:
The RES[1:0] bit must only be changed when the ADEN bit is reset.
The result of the conversion is always 12 bits wide and any unused LSB bits are read as
zeros.
Lower resolution reduces the conversion time needed for the successive approximation
steps as shown in Table 70.
Table 70. tSAR timings depending on resolution
RES[1:0]
bits
tSAR
(ADC clock
cycles)
tSAR (ns) at
fADC = 35 MHz
tSMPL (min)
tCONV
(ADC clock
cycles)
(ADC clock cycles)
(with min. tSMPL)
tCONV (ns) at
fADC = 35 MHz
12
12.5
357
1.5
14
400
10
10.5
300
1.5
12
343
8
8.5
243
1.5
10
286
6
6.5
186
1.5
8
229
RM0503 Rev 2
343/1325
384
Analog-to-digital converter (ADC)
14.5.3
RM0503
End of conversion, end of sampling phase (EOC, EOSMP flags)
The ADC indicates each end of conversion (EOC) event.
The ADC sets the EOC flag in the ADC_ISR register as soon as a new conversion data
result is available in the ADC_DR register. An interrupt can be generated if the EOCIE bit is
set in the ADC_IER register. The EOC flag is cleared by software either by writing 1 to it, or
by reading the ADC_DR register.
The ADC also indicates the end of sampling phase by setting the EOSMP flag in the
ADC_ISR register. The EOSMP flag is cleared by software by writing1 to it. An interrupt can
be generated if the EOSMPIE bit is set in the ADC_IER register.
The aim of this interrupt is to allow the processing to be synchronized with the conversions.
Typically, an analog multiplexer can be accessed in hidden time during the conversion
phase, so that the multiplexer is positioned when the next sampling starts.
Note:
As there is only a very short time left between the end of the sampling and the end of the
conversion, it is recommenced to use polling or a WFE instruction rather than an interrupt
and a WFI instruction.
14.5.4
End of conversion sequence (EOS flag)
The ADC notifies the application of each end of sequence (EOS) event.
The ADC sets the EOS flag in the ADC_ISR register as soon as the last data result of a
conversion sequence is available in the ADC_DR register. An interrupt can be generated if
the EOSIE bit is set in the ADC_IER register. The EOS flag is cleared by software by writing
1 to it.
14.5.5
Example timing diagrams (single/continuous modes
hardware/software triggers)
Figure 40. Single conversions of a sequence, software trigger
ADSTART(1)
EOC
EOS
SCANDIR
ADC state(2)
RDY
ADC_DR
by S/W
CH0
CH9
CH10 CH17
D0
D9
RDY
D10
D17
CH17 CH10 CH9
CH0
RDY
D17
D9
D0
D10
by H/W
MSv30338V3
1. EXTEN = 00, CONT = 0
2. CHSEL = 0x20601, WAIT = 0, AUTOFF = 0
344/1325
RM0503 Rev 2
RM0503
Analog-to-digital converter (ADC)
Figure 41. Continuous conversion of a sequence, software trigger
ADSTART(1)
EOC
EOS
ADSTP
SCANDIR
ADC state(2)
RDY
CH0
ADC_DR
by S/W
CH9
CH10 CH17
CH0
CH9
D0
D9
D17
D0
D10
RDY
CH10 STP
CH17
D9
CH10
D17
by H/W
MSv30339V2
1. EXTEN = 00, CONT = 1,
2. CHSEL = 0x20601, WAIT = 0, AUTOFF = 0
Figure 42. Single conversions of a sequence, hardware trigger
ADSTART(1)
EOC
EOS
TRGx(1)
ADC state(2)
RDY
ADC_DR
by S/W
by H/W
triggered
ignored
CH0
CH1
CH2
CH3
RDY CH0
CH1
CH2
CH3
RDY
D0
D1
D2
D3
D0
D1
D2
D3
MSv30340V2
1. EXTSEL = TRGx (over-frequency), EXTEN = 01 (rising edge), CONT = 0
2. CHSEL = 0xF, SCANDIR = 0, WAIT = 0, AUTOFF = 0
RM0503 Rev 2
345/1325
384
Analog-to-digital converter (ADC)
RM0503
Figure 43. Continuous conversions of a sequence, hardware trigger
ADSTART(1)
EOC
EOS
ADSTP
TRGx(1)
ADC state(2)
RDY
ADC_DR
by S/W
by H/W
triggered
ignored
CH0
CH1
CH2
CH3
CH0
CH1
CH2
CH3
CH0 STOP
D0
D1
D2
D3
D0
D1
D2
D3
RDY
MSv30341V2
1. EXTSEL = TRGx, EXTEN = 10 (falling edge), CONT = 1
2. CHSEL = 0xF, SCANDIR = 0, WAIT = 0, AUTOFF = 0
14.5.6
Low frequency trigger mode
Once the ADC is enabled or the last ADC conversion is complete, the ADC is ready to start
a new conversion. The ADC needs to be started at a predefined time (tidle) otherwise ADC
converted data might be corrupted due to the transistor leakage (refer to the device
datasheet for the maximum value of tidle).
If the application has to support a time longer than the maximum tidle value (between one
trigger to another for single conversion mode or between the ADC enable and the first ADC
conversion), then the ADC internal state needs to be rearmed. This mechanism can be
enabled by setting LFTRIG bit to 1 in ADC_CFGR2 register. By setting this bit, any trigger
(software or hardware) sends a rearm command to ADC. The conversion starts after a one
ADC clock cycle delay compared to LFTRIG cleared.
It is not necessary to use this mode when AUTOFF bit is set. For Wait mode, only the first
trigger generates an internal rearm command.
346/1325
RM0503 Rev 2
RM0503
Analog-to-digital converter (ADC)
14.6
Data management
14.6.1
Data register and data alignment (ADC_DR, ALIGN)
At the end of each conversion (when an EOC event occurs), the result of the converted data
is stored in the ADC_DR data register which is 16-bit wide.
The format of the ADC_DR depends on the configured data alignment and resolution.
The ALIGN bit in the ADC_CFGR1 register selects the alignment of the data stored after
conversion. Data can be right-aligned (ALIGN = 0) or left-aligned (ALIGN = 1) as shown in
Figure 44.
Figure 44. Data alignment and resolution (oversampling disabled: OVSE = 0)
15
ALIGN RES
0
14
13
12
11
9
8
7
6
0x0
0x0
5
4
2
1
0
DR[9:0]
0x00
0x2
3
DR[11:0]
0x00
0x1
DR[7:0]
0x00
0x3
1
10
DR[5:0]
DR[11:0]
0x0
0x0
0x00
DR[9:0]
0x1
0x2
DR[7:0]
0x3
0x00
0x00
DR[5:0]
0x0
MS30342V1
14.6.2
ADC overrun (OVR, OVRMOD)
The overrun flag (OVR) indicates a data overrun event, when the converted data was not
read in time by the CPU or the DMA, before the data from a new conversion is available.
The OVR flag is set in the ADC_ISR register if the EOC flag is still at ‘1’ at the time when a
new conversion completes. An interrupt can be generated if the OVRIE bit is set in the
ADC_IER register.
When an overrun condition occurs, the ADC keeps operating and can continue to convert
unless the software decides to stop and reset the sequence by setting the ADSTP bit in the
ADC_CR register.
The OVR flag is cleared by software by writing 1 to it.
It is possible to configure if the data is preserved or overwritten when an overrun event
occurs by programming the OVRMOD bit in the ADC_CFGR1 register:
•
OVRMOD = 0
–
•
An overrun event preserves the data register from being overwritten: the old data
is maintained and the new conversion is discarded. If OVR remains at 1, further
conversions can be performed but the resulting data is discarded.
OVRMOD = 1
–
The data register is overwritten with the last conversion result and the previous
unread data is lost. If OVR remains at 1, further conversions can be performed
and the ADC_DR register always contains the data from the latest conversion.
RM0503 Rev 2
347/1325
384
Analog-to-digital converter (ADC)
RM0503
Figure 45. Example of overrun (OVR)
ADSTART(1)
EOC
EOS
OVR
ADSTP
TRGx(1)
ADC state(2)
RDY
CH0
CH1
CH2
CH0
CH1
CH0 STOP
RDY
OVERRUN
ADC_DR read
access
ADC_DR
(OVRMOD=0)
D0
D1
D2
D0
ADC_DR
(OVRMOD=1)
D0
D1
D2
D0
by S/W
CH2
D1
D2
by H/W
triggered
MSv30343V3
14.6.3
Managing a sequence of data converted without using the DMA
If the conversions are slow enough, the conversion sequence can be handled by software.
In this case the software must use the EOC flag and its associated interrupt to handle each
data result. Each time a conversion is complete, the EOC bit is set in the ADC_ISR register
and the ADC_DR register can be read. The OVRMOD bit in the ADC_CFGR1 register
should be configured to 0 to manage overrun events as an error.
14.6.4
Managing converted data without using the DMA without overrun
It may be useful to let the ADC convert one or more channels without reading the data after
each conversion. In this case, the OVRMOD bit must be configured at 1 and the OVR flag
should be ignored by the software. When OVRMOD = 1, an overrun event does not prevent
the ADC from continuing to convert and the ADC_DR register always contains the latest
conversion data.
14.6.5
Managing converted data using the DMA
Since all converted channel values are stored in a single data register, it is efficient to use
DMA when converting more than one channel. This avoids losing the conversion data
results stored in the ADC_DR register.
348/1325
RM0503 Rev 2
RM0503
Analog-to-digital converter (ADC)
When DMA mode is enabled (DMAEN bit set in the ADC_CFGR1 register), a DMA request
is generated after the conversion of each channel. This allows the transfer of the converted
data from the ADC_DR register to the destination location selected by the software.
Note:
The DMAEN bit in the ADC_CFGR1 register must be set after the ADC calibration phase.
Despite this, if an overrun occurs (OVR = 1) because the DMA could not serve the DMA
transfer request in time, the ADC stops generating DMA requests and the data
corresponding to the new conversion is not transferred by the DMA. Which means that all
the data transferred to the RAM can be considered as valid.
Depending on the configuration of OVRMOD bit, the data is either preserved or overwritten
(refer to Section 14.6.2: ADC overrun (OVR, OVRMOD) on page 347).
The DMA transfer requests are blocked until the software clears the OVR bit.
Two different DMA modes are proposed depending on the application use and are
configured with bit DMACFG in the ADC_CFGR1 register:
•
DMA one shot mode (DMACFG = 0).
This mode should be selected when the DMA is programmed to transfer a fixed
number of data words.
•
DMA circular mode (DMACFG = 1)
This mode should be selected when programming the DMA in circular mode or double
buffer mode.
DMA one shot mode (DMACFG = 0)
In this mode, the ADC generates a DMA transfer request each time a new conversion data
word is available and stops generating DMA requests once the DMA has reached the last
DMA transfer (when a transfer complete interrupt occurs, see Section 9: Direct memory
access controller (DMA) on page 264) even if a conversion has been started again.
When the DMA transfer is complete (all the transfers configured in the DMA controller have
been done):
•
The content of the ADC data register is frozen.
•
Any ongoing conversion is aborted and its partial result discarded
•
No new DMA request is issued to the DMA controller. This avoids generating an
overrun error if there are still conversions which are started.
•
The scan sequence is stopped and reset
•
The DMA is stopped
DMA circular mode (DMACFG = 1)
In this mode, the ADC generates a DMA transfer request each time a new conversion data
word is available in the data register, even if the DMA has reached the last DMA transfer.
This allows the DMA to be configured in circular mode to handle a continuous analog input
data stream.
RM0503 Rev 2
349/1325
384
Analog-to-digital converter (ADC)
RM0503
14.7
Low-power features
14.7.1
Wait mode conversion
Wait mode conversion can be used to simplify the software as well as optimizing the
performance of applications clocked at low frequency where there might be a risk of ADC
overrun occurring.
When the WAIT bit is set in the ADC_CFGR1 register, a new conversion can start only if the
previous data has been treated, once the ADC_DR register has been read or if the EOC bit
has been cleared.
This is a way to automatically adapt the speed of the ADC to the speed of the system that
reads the data.
Note:
Any hardware triggers which occur while a conversion is ongoing or during the wait time
preceding the read access are ignored.
Figure 46. Wait mode conversion (continuous mode, software trigger)
ADSTART
EOC
EOS
ADSTP
ADC_DR Read access
ADC state
RDY
ADC_DR
by S/W
CH1
CH2
DLY
DLY CH3
D2
D1
DLY
D3
CH1
DLY
STOP
RDY
D1
by H/W
MSv30344V2
1. EXTEN = 00, CONT = 1
2. CHSEL = 0x3, SCANDIR = 0, WAIT = 1, AUTOFF = 0
14.7.2
Auto-off mode (AUTOFF)
The ADC has an automatic power management feature which is called auto-off mode, and
is enabled by setting AUTOFF = 1 in the ADC_CFGR1 register.
When AUTOFF = 1, the ADC is always powered off when not converting and automatically
wakes-up when a conversion is started (by software or hardware trigger). A startup-time is
automatically inserted between the trigger event which starts the conversion and the
sampling time of the ADC. The ADC is then automatically disabled once the sequence of
conversions is complete.
Auto-off mode can cause a dramatic reduction in the power consumption of applications
which need relatively few conversions or when conversion requests are timed far enough
350/1325
RM0503 Rev 2
RM0503
Analog-to-digital converter (ADC)
apart (for example with a low frequency hardware trigger) to justify the extra power and
extra time used for switching the ADC on and off.
Auto-off mode can be combined with the wait mode conversion (WAIT = 1) for applications
clocked at low frequency. This combination can provide significant power savings if the ADC
is automatically powered-off during the wait phase and restarted as soon as the ADC_DR
register is read by the application (see Figure 48: Behavior with WAIT = 1, AUTOFF = 1).
Figure 47. Behavior with WAIT = 0, AUTOFF = 1
TRGx
EOC
EOS
ADC_DR Read
access
ADC state
RDY Startup
ADC_DR
by S/W
CH1
CH2
CH3
CH4
D1
D2
D3
OFF
Startup
D4
by H/W
triggered
MSv30345V2
1. EXTSEL = TRGx, EXTEN = 01 (rising edge), CONT = x, ADSTART = 1, CHSEL = 0xF, SCANDIR = 0, WAIT = 1,
AUTOFF = 1
RM0503 Rev 2
351/1325
384
Analog-to-digital converter (ADC)
RM0503
Figure 48. Behavior with WAIT = 1, AUTOFF = 1
TRGx
EOC
ADC state
RDY
Startup
CH1
DLY
OFF
Startup CH2
DLY
DLY
Startup
D1
ADC_DR
by S/W
DLY
CH3
D2
OFF
Startup
CH1
OFF
ADC_DR Read
access
OFF
EOS
D3
CH2
D4
by H/W
triggered
MSv30346V2
1. EXTSEL = TRGx, EXTEN = 01 (rising edge), CONT = x, ADSTART = 1, CHSEL = 0xF, SCANDIR = 0, WAIT = 1,
AUTOFF = 1
14.8
Analog window watchdogs
The three AWD analog watchdogs monitor whether some channels remain within a
configured voltage range (window).
14.8.1
Description of analog watchdog 1
AWD1 analog watchdog is enabled by setting the AWD1EN bit in the ADC_CFGR1 register.
It is used to monitor that either one selected channel or all enabled channels (see Table 72:
Analog watchdog 1 channel selection) remain within a configured voltage range (window) as
shown in Figure 49.
The AWD1 analog watchdog status bit is set if the analog voltage converted by the ADC is
below a lower threshold or above a higher threshold. These thresholds are programmed in
HT1[11:0] and LT1[11:0] bits of ADC_AWD1TR register. An interrupt can be enabled by
setting the AWD1IE bit in the ADC_IER register.
The AWD1 flag is cleared by software by programing it to 1.
When converting data with a resolution of less than 12-bit (according to bits DRES[1:0]), the
LSB of the programmed thresholds must be kept cleared because the internal comparison
is always performed on the full 12-bit raw converted data (left aligned).
Table 71 describes how the comparison is performed for all the possible resolutions.
352/1325
RM0503 Rev 2
RM0503
Analog-to-digital converter (ADC)
Table 71. Analog watchdog comparison
Resolution
Analog Watchdog comparison between:
bits
RES[1:0]
Raw converted
data, left aligned(1)
Thresholds
00: 12-bit
DATA[11:0]
LTx[11:0] and HTx[11:0] -
01: 10-bit
DATA[11:2],00
LTx[11:0] and HTx[11:0] The user must configure LTx[1:0] and HTx[1:0] to “00”
10: 8-bit
DATA[11:4],0000
LTx[11:0] and HTx[11:0]
The user must configure LTx[3:0] and HTx[3:0] to
“0000”
11: 6-bit
DATA[11:6],000000 LTx[11:0] and HTx[11:0]
The user must configure LTx[5:0] and HTx[5:0] to
“000000”
Comments
1. The watchdog comparison is performed on the raw converted data before any alignment calculation.
Table 72 shows how to configure the AWD1SGL and AWD1EN bits in the ADC_CFGR1
register to enable the analog watchdog on one or more channels.
Figure 49. Analog watchdog guarded area
Analog voltage
Higher threshold
HTx
Guarded area
Lower threshold
LTx
MS45396V1
Table 72. Analog watchdog 1 channel selection
Channels guarded by the analog watchdog
AWD1SGL bit
AWD1EN bit
x
0
0
1
1
1
None
All channels
(1)
Single
channel
1. Selected by the AWD1CH[4:0] bits
14.8.2
Description of analog watchdog 2 and 3
The second and third analog watchdogs are more flexible and can guard several selected
channels by programming the AWDxCHy in ADC_AWDxCR (x = 2, 3).
The corresponding watchdog is enabled when any AWDxCHy bit (x = 2,3) is set in
ADC_AWDxCR register.
When converting data with a resolution of less than 12 bits (configured through DRES[1:0]
bits), the LSB of the programmed thresholds must be kept cleared because the internal
comparison is always performed on the full 12-bit raw converted data (left aligned).
Table 71 describes how the comparison is performed for all the possible resolutions.
The AWD2/3 analog watchdog status bit is set if the analog voltage converted by the ADC is
below a low threshold or above a high threshold. These thresholds are programmed in
RM0503 Rev 2
353/1325
384
Analog-to-digital converter (ADC)
RM0503
HTx[11:0] and LTx[11:0] of ADC_AWDxTR registers (x = 2 or 3). An interrupt can be
enabled by setting the AWDxIE bit in the ADC_IER register.
The AWD2 and ADW3 flags are cleared by software by programming them to 1.
14.8.3
ADC_AWDx_OUT output signal generation
Each analog watchdog is associated to an internal hardware signal, ADC_AWDx_OUT (x
being the watchdog number) that is directly connected to the ETR input (external trigger) of
some on-chip timers (refer to the timers section for details on how to select the
ADC_AWDx_OUT signal as ETR).
ADC_AWDx_OUT is activated when the associated analog watchdog is enabled:
•
ADC_AWDx_OUT is set when a guarded conversion is outside the programmed
thresholds.
•
ADC_AWDx_OUT is reset after the end of the next guarded conversion which is inside
the programmed thresholds. It remains at 1 if the next guarded conversions are still
outside the programmed thresholds.
•
ADC_AWDx_OUT is also reset when disabling the ADC (when setting ADDIS to 1).
Note that stopping conversions (ADSTP set), might clear the ADC_AWDx_OUT state.
•
ADC_AWDx_OUT state does not change when the ADC converts the none-guarded
channel (see Figure 52)
AWDx flag is set by hardware and reset by software: AWDx flag has no influence on the
generation of ADC_AWDx_OUT (as an example, ADC_AWDx_OUT can toggle while AWDx
flag remains at 1 if the software has not cleared the flag).
The ADC_AWDx_OUT signal is generated by the ADC_CLK domain. This signal can be
generated even the APB clock is stopped.
The AWD comparison is performed at the end of each ADC conversion. The
ADC_AWDx_OUT rising edge and falling edge occurs two ADC_CLK clock cycles after the
comparison.
As ADC_AWDx_OUT is generated by the ADC_CLK domain and AWD flag is generated by
the APB clock domain, the rising edges of these signals are not synchronized.
Figure 50. ADC_AWDx_OUT signal generation
ADC STATE
RDY
Conversion1
Conversion2
Conversion3
Conversion4
Conversion5
Conversion6
Conversion7
inside
outside
inside
outside
outside
outside
inside
Cleared
by SW
Cleared
by SW
Cleared
by SW
EOC FLAG
Cleared
by SW
AWDx FLAG
ADC_AWDx_OUT
- Converted channels: 1,2,3,4,5,6,7
- Guarded converted channels: 1,2,3,4,5,6,7
MSv45362V1
354/1325
RM0503 Rev 2
RM0503
Analog-to-digital converter (ADC)
Figure 51. ADC_AWDx_OUT signal generation (AWDx flag not cleared by software)
ADC STATE RDY
Conversion1
Conversion2
Conversion3
inside
outside
inside
Conversion4
Conversion5
Conversion6
Conversion7
outside
outside
outside
inside
EOC FLAG
not cleared by SW
AWDx FLAG
ADC_AWDx_OUT
- Converted channels: 1,2,3,4,5,6,7
- Guarded converted channels: 1,2,3,4,5,6,7
MSv45363V1
Figure 52. ADC_AWDx_OUT signal generation (on a single channel)
ADC STATE
Conversion1
Conversion2
outside
Conversion1
Conversion2
inside
Conversion1
Conversion2
outside
Conversion1
Conversion2
outside
EOC FLAG
EOS FLAG
AWDx FLAG
Cleared
by SW
Cleared
by SW
ADCy_AWDx_OUT
- Converted channels: 1 and 2
- Only channel 1 is guarded
MSv45364V1
14.8.4
Analog Watchdog threshold control
LTx[11:0] and HTx[11:0] can be changed during an analog-to-digital conversion (that is
between the start of the conversion and the end of conversion of the ADC internal state). If
HTx and LTx bits are programmed during the ADC guarded channel conversion, the
watchdog function is masked for this conversion. This mask is cleared when starting a new
conversion, and the resulting new AWD threshold is applied starting the next ADC
conversion result. AWD comparison is performed at each end of conversion. If the current
ADC data are out of the new threshold interval, this does not generated any interrupt or an
ADC_AWDx_OUT signal. The Interrupt and the ADC_AWDx_OUT generation only occurs
at the end of the ADC conversion that started after the threshold update. If
ADC_AWDx_OUT is already asserted, programming the new threshold does not deassert
the ADC_AWDx_OUT signal.
RM0503 Rev 2
355/1325
384
Analog-to-digital converter (ADC)
RM0503
Figure 53. Analog watchdog threshold update
ADC state
Conversion
Conversion
Conversion
Conversion
Threshold updated
LTx, HTx
XXXX
XXXY
XXXZ
Masked
Active
Comparison
Active
MSv45365V1
14.9
Oversampler
The oversampling unit performs data preprocessing to offload the CPU. It can handle
multiple conversions and average them into a single data with increased data width, up to
16-bit.
It provides a result with the following form, where N and M can be adjusted:
1
Result = ----- ×
M
n = N–1
∑ Conversion ( tn )
n=0
It allows the following functions to be performed by hardware: averaging, data rate
reduction, SNR improvement, basic filtering.
The oversampling ratio N is defined using the OVFS[2:0] bits in the ADC_CFGR2 register. It
can range from 2x to 256x. The division coefficient M consists of a right bit shift up to 8 bits.
It is configured through the OVSS[3:0] bits in the ADC_CFGR2 register.
The summation unit can yield a result up to 20 bits (256 x 12-bit), which is first shifted right.
The upper bits of the result are then truncated, keeping only the 16 least significant bits
rounded to the nearest value using the least significant bits left apart by the shifting, before
being finally transferred into the ADC_DR data register.
Note:
If the intermediate result after the shifting exceeds 16 bits, the upper bits of the result are
simply truncated.
Figure 54. 20-bit to 16-bit result truncation
19
15
11
7
3
0
Raw 20-bit data
Shifting
15
0
Truncation
and rounding
MS31928V2
356/1325
RM0503 Rev 2
RM0503
Analog-to-digital converter (ADC)
The Figure 55 gives a numerical example of the processing, from a raw 20-bit accumulated
data to the final 16-bit result.
Figure 55. Numerical example with 5-bits shift and rounding
19
Raw 20-bit data:
15
3
11
7
3
B
7
D
7
1
D
B
F
15
Final result after 5-bits shift
and rounding to nearest
0
MS31929V1
Table 73 gives the data format for the various N and M combination, for a raw conversion
data equal to 0xFFF.
Table 73. Maximum output results vs N and M. Grayed values indicates truncation
No-shift
Oversa
Max
mpling
OVSS =
Raw data
ratio
0000
1-bit
shift
2-bit
shift
3-bit
shift
4-bit
shift
5-bit
shift
6-bit
shift
7-bit
shift
8-bit
shift
OVSS =
0001
OVSS =
0010
OVSS =
0011
OVSS =
0100
OVSS =
0101
OVSS =
0110
OVSS = OVSS =
0111
1000
2x
0x1FFE
0x1FFE
0x0FFF
0x0800
0x0400
0x0200
0x0100
0x0080
0x0040
0x0020
4x
0x3FFC
0x3FFC
0x1FFE
0x0FFF
0x0800
0x0400
0x0200
0x0100
0x0080
0x0040
8x
0x7FF8
0x7FF8
0x3FFC
0x1FFE
0x0FFF
0x0800
0x0400
0x0200
0x0100
0x0080
16x
0xFFF0
0xFFF0
0x7FF8
0x3FFC
0x1FFE
0x0FFF
0x0800
0x0400
0x0200
0x0100
32x
0x1FFE0
0xFFE0
0xFFF0
0x7FF8
0x3FFC
0x1FFE
0x0FFF
0x0800
0x0400
0x0200
64x
0x3FFC0
0xFFC0
0xFFE0
0xFFF0
0x7FF8
0x3FFC
0x1FFE
0x0FFF
0x0800
0x0400
128x
0x7FF80
0xFF80
0xFFC0
0xFFE0
0xFFF0
0x7FF8
0x3FFC
0x1FFE
0x0FFF
0x0800
256x
0xFFF00
0xFF00
0xFF80
0xFFC0
0xFFE0
0xFFF0
0x7FF8
0x3FFC
0x1FFE
0x0FFF
The conversion timings in oversampled mode do not change compared to standard
conversion mode: the sample time is maintained equal during the whole oversampling
sequence. New data are provided every N conversion, with an equivalent delay equal to N x
tCONV = N x (tSMPL + tSAR). The flags features are raised as following:
•
the end of the sampling phase (EOSMP) is set after each sampling phase
•
the end of conversion (EOC) occurs once every N conversions, when the oversampled
result is available
•
the end of sequence (EOCSEQ) occurs once the sequence of oversampled data is
completed (i.e. after N x sequence length conversions total)
RM0503 Rev 2
357/1325
384
Analog-to-digital converter (ADC)
14.9.1
RM0503
ADC operating modes supported when oversampling
In oversampling mode, most of the ADC operating modes are available:
•
Single or continuous mode conversions, forward or backward scanned sequences
•
ADC conversions start either by software or with triggers
•
ADC stop during a conversion (abort)
•
Data read via CPU or DMA with overrun detection
•
Low-power modes (WAIT, AUTOFF)
•
Programmable resolution: in this case, the reduced conversion values (as per RES[1:0]
bits in ADC_CFGR1 register) are accumulated, truncated, rounded and shifted in the
same way as 12-bit conversions are
Note:
The alignment mode is not available when working with oversampled data. The ALIGN bit in
ADC_CFGR1 is ignored and the data are always provided right-aligned.
14.9.2
Analog watchdog
The analog watchdog functionality is available, with the following differences:
•
the RES[1:0] bits are ignored, comparison is always done on using the full 12-bits
values HTx[11:0] and LTx[11:0]
•
the comparison is performed on the most significant 12 bits of the 16 bits oversampled
results ADC_DR[15:4]
Note:
Care must be taken when using high shifting values. This reduces the comparison range.
For instance, if the oversampled result is shifted by 4 bits thus yielding a 12-bit data rightaligned, the affective analog watchdog comparison can only be performed on 8 bits. The
comparison is done between ADC_DR[11:4] and HTx[7:0] / LTx[[7:0], and HTx[11:8] /
LTx[11:8] must be kept reset.
14.9.3
Triggered mode
The averager can also be used for basic filtering purposes. Although not a very efficient filter
(slow roll-off and limited stop band attenuation), it can be used as a notch filter to reject
constant parasitic frequencies (typically coming from the mains or from a switched mode
power supply). For this purpose, a specific discontinuous mode can be enabled with TOVS
bit in ADC_CFGR2, to be able to have an oversampling frequency defined by a user and
independent from the conversion time itself.
Figure 56 below shows how conversions are started in response to triggers in discontinuous
mode.
If the TOVS bit is set, the content of the DISCEN bit is ignored and considered as 1.
358/1325
RM0503 Rev 2
RM0503
Analog-to-digital converter (ADC)
Figure 56. Triggered oversampling mode (TOVS bit = 1)
Trigger
CONT = 0
(DISCEN = 1)*
TOVS = 0
Trigger
Ch(N) Ch(N) Ch(N) Ch(N)
0
1
2
3
Ch(N) Ch(N) Ch(N) Ch(N)
0
1
2
3
EOC flag set
Trigger Trigger Trigger
CONT = 0
(DISCEN = 1)*
TOVS = 1
Ch(N)
0
Ch(N)
1
Ch(N)
2
Trigger Trigger Trigger Trigger
Ch(N)
3
Ch(N)
0
Ch(N)
1
Ch(N)
2
EOC flag set
(DISCEN = 1)*: DISCEN bit is forced to 1 by software when TOVS bit is set
MS33700V1
14.10
Temperature sensor and internal reference voltage
The temperature sensor can be used to measure the junction temperature (TJ) of the
device. The temperature sensor is internally connected to the ADC VIN[11] input channel
which is used to convert the sensor’s output voltage to a digital value. The sampling time for
the temperature sensor analog pin must be greater than the minimum TS_temp value
specified in the datasheet. When not in use, the sensor can be put in power down mode.
The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the
ADC. VREFINT is internally connected to the ADC VIN[12] input channel. The precise voltage
of VREFINT is individually measured for each part by ST during production test and stored in
the system memory area.
Figure 57 shows the block diagram of connections between the temperature sensor, the
internal voltage reference and the ADC.
The TSEN bit must be set to enable the conversion of ADC VIN[11] (temperature sensor)
and the VREFEN bit must be set to enable the conversion of ADC VIN[12] (VREFINT).
RM0503 Rev 2
359/1325
384
Analog-to-digital converter (ADC)
RM0503
Figure 57. Temperature sensor and VREFINT channel block diagram
TSEN control bit
Temperature
sensor
VSENSE
+
-
converted data
VREFEN control bit
VREFINT
+
Internal power
block
ADC
ADC VIN[12]
Address/data bus
ADC VIN[11]
-
MSv71290V1
Reading the temperature
1.
Select the ADC VIN[11] input channel.
2.
Select an appropriate sampling time specified in the device datasheet (TS_temp).
3.
Set the TSEN bit in the ADC_CCR register to wake up the temperature sensor from
power down mode and wait for its stabilization time (tSTART).
4.
Start the ADC conversion by setting the ADSTART bit in the ADC_CR register (or by
external trigger).
5.
Read the resulting VSENSE data in the ADC_DR register.
6.
Calculate the temperature using the following formula
TS_CAL2_TEMP – TS_CAL1_TEMP
Temperature ( in °C ) = ---------------------------------------------------------------------------------------------------- × ( TS_DATA – TS_CAL1 ) + TS_CAL1_TEMP
TS_CAL2 – TS_CAL1
Where:
•
TS_CAL2 is the temperature sensor calibration value acquired at TS_CAL2_TEMP
(refer to the datasheet for TS_CAL2 value)
•
TS_CAL1 is the temperature sensor calibration value acquired at TS_CAL1_TEMP
(refer to the datasheet for TS_CAL1 value)
•
TS_DATA is the actual temperature sensor output value converted by ADC
Refer to the specific device datasheet for more information about TS_CAL1 and
TS_CAL2 calibration points.
Note:
360/1325
The sensor has a startup time after waking from power down mode before it can output
VSENSE at the correct level. The ADC also has a startup time after power-on, so to minimize
the delay, the ADEN and TSEN bits should be set at the same time.
RM0503 Rev 2
RM0503
Analog-to-digital converter (ADC)
Calculating the actual VREF+ voltage using the internal reference voltage
VREF+ voltage may be subject to variation or not precisely known. The embedded internal
reference voltage (VREFINT) and its calibration data acquired by the ADC during the
manufacturing process at VREF+_charac can be used to evaluate the actual VREF+ voltage
level.
The following formula gives the actual VREF+ voltage supplying the device:
V REF+ = V REF + _Charac × VREFINT_CAL ⁄ VREFINT_DATA
Where:
•
VREF+_Charac is the value of VREF+ voltage characterized at VREFINT during the
manufacturing process. It is specified in the device datasheet.
•
VREFINT_CAL is the VREFINT calibration value
•
VREFINT_DATA is the actual VREFINT output value converted by ADC
Converting a supply-relative ADC measurement to an absolute voltage value
The ADC is designed to deliver a digital value corresponding to the ratio between the analog
power supply and the voltage applied on the converted channel. For most application use
cases, it is necessary to convert this ratio into a voltage independent of VREF+. For
applications where VREF+ is known and ADC converted values are right-aligned you can
use the following formula to get this absolute value:
V REF+
V CHANNELx = -------------------------------------- × ADC_DATA x
NUM_CODES
For applications where VREF+ value is not known, you must use the internal voltage
reference and VREF+ can be replaced by the expression provided in Section : Calculating
the actual VREF+ voltage using the internal reference voltage, resulting in the following
formula:
V REF+_Charac × VREFINT_CAL × ADC_DATA x
V CHANNELx = -----------------------------------------------------------------------------------------------------------------------------------VREFINT_DATA × NUM_CODES
Where:
•
VREF+_Charac is the value of VREF+ voltage characterized at VREFINT during the
manufacturing process. It is specified in the device datasheet.
•
VREFINT_CAL is the VREFINT calibration value
•
ADC_DATAx is the value measured by the ADC on channelx (right-aligned)
•
VREFINT_DATA is the actual VREFINT output value converted by the ADC
•
NUM_CODES is the number of ADC output codes. For example with 12-bit resolution,
it is 212 = 4096 or with 8-bit resolution, 28 = 256.
Note:
If ADC measurements are done using an output format other than 12 bit right-aligned, all the
parameters must first be converted to a compatible format before the calculation is done.
14.11
Battery voltage monitoring
The VBATEN bit in the ADC_CCR register allows the application to measure the backup
battery voltage on the VBAT pin. As the VBAT voltage can be higher than VREF+, to ensure
RM0503 Rev 2
361/1325
384
Analog-to-digital converter (ADC)
RM0503
the correct operation of the ADC, the VBAT pin is internally connected to a bridge divider.
This bridge is automatically enabled when VBATEN is set, to connect VBAT to the ADC
VIN[13] input channel. As a consequence, the converted digital value is VBAT/3. To prevent
any unwanted consumption on the battery, it is recommended to enable the bridge divider
only when needed for ADC conversion.
14.12
ADC interrupts
An interrupt can be generated by any of the following events:
•
End Of Calibration (EOCAL flag)
•
ADC power-up, when the ADC is ready (ADRDY flag)
•
End of any conversion (EOC flag)
•
End of a sequence of conversions (EOS flag)
•
When an analog watchdog detection occurs (AWD1, AWD2, AWD3 flags)
•
When the Channel configuration is ready (CCRDY flag)
•
When the end of sampling phase occurs (EOSMP flag)
•
when a data overrun occurs (OVR flag)
Separate interrupt enable bits are available for flexibility.
Table 74. ADC interrupts
Interrupt event
Event flag
Enable control bit
End Of Calibration
EOCAL
EOCALIE
ADC ready
ADRDY
ADRDYIE
End of conversion
EOC
EOCIE
End of sequence of conversions
EOS
EOSIE
Analog watchdog 1 status bit is set
AWD1
AWD1IE
Analog watchdog 2 status bit is set
AWD2
AWD2IE
Analog watchdog 3 status bit is set
AWD3
AWD3IE
Channel Configuration Ready
CCRDY
CCRDYIE
End of sampling phase
EOSMP
EOSMPIE
OVR
OVRIE
Overrun
362/1325
RM0503 Rev 2
RM0503
14.13
Analog-to-digital converter (ADC)
ADC registers
Refer to Section 1.2 for a list of abbreviations used in register descriptions.
14.13.1
ADC interrupt and status register (ADC_ISR)
Address offset: 0x00
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
CCRDY
Res.
EOCAL
Res.
AWD3
AWD2
AWD1
Res.
Res.
OVR
EOS
EOC
EOSMP ADRDY
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
Bits 31:14 Reserved, must be kept at reset value.
Bit 13 CCRDY: Channel Configuration Ready flag
This flag bit is set by hardware when the channel configuration is applied after programming to
ADC_CHSELR register or changing CHSELRMOD or SCANDIR. It is cleared by software by
programming it to it.
0: Channel configuration update not applied.
1: Channel configuration update is applied.
Note: When the software configures the channels (by programming ADC_CHSELR or changing
CHSELRMOD or SCANDIR), it must wait until the CCRDY flag rises before configuring again
or starting conversions, otherwise the new configuration (or the START bit) is ignored. Once the
flag is asserted, if the software needs to configure again the channels, it must clear the CCRDY
flag before proceeding with a new configuration.
Bit 12 Reserved, must be kept at reset value.
Bit 11 EOCAL: End Of Calibration flag
This bit is set by hardware when calibration is complete. It is cleared by software writing 1 to it.
0: Calibration is not complete
1: Calibration is complete
Bit 10 Reserved, must be kept at reset value.
Bit 9 AWD3: Analog watchdog 3 flag
This bit is set by hardware when the converted voltage crosses the values programmed in
ADC_AWD3TR and ADC_AWD3TR registers. It is cleared by software by programming it to 1.
0: No analog watchdog event occurred (or the flag event was already acknowledged and cleared by
software)
1: Analog watchdog event occurred
Bit 8 AWD2: Analog watchdog 2 flag
This bit is set by hardware when the converted voltage crosses the values programmed in
ADC_AWD2TR and ADC_AWD2TR registers. It is cleared by software programming it it.
0: No analog watchdog event occurred (or the flag event was already acknowledged and cleared by
software)
1: Analog watchdog event occurred
RM0503 Rev 2
363/1325
384
Analog-to-digital converter (ADC)
RM0503
Bit 7 AWD1: Analog watchdog 1 flag
This bit is set by hardware when the converted voltage crosses the values programmed in ADC_TR1
and ADC_HR1 registers. It is cleared by software by programming it to 1.
0: No analog watchdog event occurred (or the flag event was already acknowledged and cleared by
software)
1: Analog watchdog event occurred
Bits 6:5 Reserved, must be kept at reset value.
Bit 4 OVR: ADC overrun
This bit is set by hardware when an overrun occurs, meaning that a new conversion has complete
while the EOC flag was already set. It is cleared by software writing 1 to it.
0: No overrun occurred (or the flag event was already acknowledged and cleared by software)
1: Overrun has occurred
Bit 3 EOS: End of sequence flag
This bit is set by hardware at the end of the conversion of a sequence of channels selected by the
CHSEL bits. It is cleared by software writing 1 to it.
0: Conversion sequence not complete (or the flag event was already acknowledged and cleared by
software)
1: Conversion sequence complete
Bit 2 EOC: End of conversion flag
This bit is set by hardware at the end of each conversion of a channel when a new data result is
available in the ADC_DR register. It is cleared by software writing 1 to it or by reading the ADC_DR
register.
0: Channel conversion not complete (or the flag event was already acknowledged and cleared by
software)
1: Channel conversion complete
Bit 1 EOSMP: End of sampling flag
This bit is set by hardware during the conversion, at the end of the sampling phase.It is cleared by
software by programming it to ‘1’.
0: Not at the end of the sampling phase (or the flag event was already acknowledged and cleared by
software)
1: End of sampling phase reached
Bit 0 ADRDY: ADC ready
This bit is set by hardware after the ADC has been enabled (ADEN = 1) and when the ADC reaches
a state where it is ready to accept conversion requests.
It is cleared by software writing 1 to it.
0: ADC not yet ready to start conversion (or the flag event was already acknowledged and cleared
by software)
1: ADC is ready to start conversion
364/1325
RM0503 Rev 2
RM0503
14.13.2
Analog-to-digital converter (ADC)
ADC interrupt enable register (ADC_IER)
Address offset: 0x04
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
CCRD
YIE
Res.
EOCAL
IE
Res.
rw
rw
Res.
AWD3I AWD2I AWD1I
E
E
E
rw
rw
rw
Res.
Res.
OVRIE
EOSIE
rw
rw
EOSMP ADRDY
EOCIE
IE
IE
rw
rw
rw
Bits 31:14 Reserved, must be kept at reset value.
Bit 13 CCRDYIE: Channel Configuration Ready Interrupt enable
This bit is set and cleared by software to enable/disable the channel configuration ready interrupt.
0: Channel configuration ready interrupt disabled
1: Channel configuration ready interrupt enabled
Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no
conversion is ongoing).
Bit 12 Reserved, must be kept at reset value.
Bit 11 EOCALIE: End of calibration interrupt enable
This bit is set and cleared by software to enable/disable the end of calibration interrupt.
0: End of calibration interrupt disabled
1: End of calibration interrupt enabled
Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no
conversion is ongoing).
Bit 10 Reserved, must be kept at reset value.
Bit 9 AWD3IE: Analog watchdog 3 interrupt enable
This bit is set and cleared by software to enable/disable the analog watchdog interrupt.
0: Analog watchdog interrupt disabled
1: Analog watchdog interrupt enabled
Note: The Software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no
conversion is ongoing).
Bit 8 AWD2IE: Analog watchdog 2 interrupt enable
This bit is set and cleared by software to enable/disable the analog watchdog interrupt.
0: Analog watchdog interrupt disabled
1: Analog watchdog interrupt enabled
Note: The Software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no
conversion is ongoing).
Bit 7 AWD1IE: Analog watchdog 1 interrupt enable
This bit is set and cleared by software to enable/disable the analog watchdog interrupt.
0: Analog watchdog interrupt disabled
1: Analog watchdog interrupt enabled
Note: The Software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no
conversion is ongoing).
Bits 6:5 Reserved, must be kept at reset value.
RM0503 Rev 2
365/1325
384
Analog-to-digital converter (ADC)
RM0503
Bit 4 OVRIE: Overrun interrupt enable
This bit is set and cleared by software to enable/disable the overrun interrupt.
0: Overrun interrupt disabled
1: Overrun interrupt enabled. An interrupt is generated when the OVR bit is set.
Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no
conversion is ongoing).
Bit 3 EOSIE: End of conversion sequence interrupt enable
This bit is set and cleared by software to enable/disable the end of sequence of conversions
interrupt.
0: EOS interrupt disabled
1: EOS interrupt enabled. An interrupt is generated when the EOS bit is set.
Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no
conversion is ongoing).
Bit 2 EOCIE: End of conversion interrupt enable
This bit is set and cleared by software to enable/disable the end of conversion interrupt.
0: EOC interrupt disabled
1: EOC interrupt enabled. An interrupt is generated when the EOC bit is set.
Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no
conversion is ongoing).
Bit 1 EOSMPIE: End of sampling flag interrupt enable
This bit is set and cleared by software to enable/disable the end of the sampling phase interrupt.
0: EOSMP interrupt disabled.
1: EOSMP interrupt enabled. An interrupt is generated when the EOSMP bit is set.
Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no
conversion is ongoing).
Bit 0 ADRDYIE: ADC ready interrupt enable
This bit is set and cleared by software to enable/disable the ADC Ready interrupt.
0: ADRDY interrupt disabled.
1: ADRDY interrupt enabled. An interrupt is generated when the ADRDY bit is set.
Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no
conversion is ongoing).
366/1325
RM0503 Rev 2
RM0503
14.13.3
Analog-to-digital converter (ADC)
ADC control register (ADC_CR)
Address offset: 0x08
Reset value: 0x0000 0000
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
ADVR
EGEN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
ADSTP
Res.
ADSTA
RT
ADDIS
ADEN
rs
rs
rs
ADCAL
30
rs
rw
rs
Bit 31 ADCAL: ADC calibration
This bit is set by software to start the calibration of the ADC.
It is cleared by hardware after calibration is complete.
0: Calibration complete
1: Write 1 to calibrate the ADC. Read at 1 means that a calibration is in progress.
Note: The software is allowed to set ADCAL only when the ADC is disabled (ADCAL = 0,
ADSTART = 0, ADSTP = 0, ADDIS = 0, AUTOFF = 0, and ADEN = 0).
The software is allowed to update the calibration factor by writing ADC_CALFACT only when
ADEN = 1 and ADSTART = 0 (ADC enabled and no conversion is ongoing).
Bits 30:29 Reserved, must be kept at reset value.
Bit 28 ADVREGEN: ADC Voltage Regulator Enable
This bit is set by software, to enable the ADC internal voltage regulator. The voltage regulator output
is available after tADCVREG_STUP.
It is cleared by software to disable the voltage regulator. It can be cleared only if ADEN is et to 0.
0: ADC voltage regulator disabled
1: ADC voltage regulator enabled
Note: The software is allowed to program this bit field only when the ADC is disabled (ADCAL = 0,
ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).
Bits 27:5 Reserved, must be kept at reset value.
Bit 4 ADSTP: ADC stop conversion command
This bit is set by software to stop and discard an ongoing conversion (ADSTP Command).
It is cleared by hardware when the conversion is effectively discarded and the ADC is ready to
accept a new start conversion command.
0: No ADC stop conversion command ongoing
1: Write 1 to stop the ADC. Read 1 means that an ADSTP command is in progress.
Note: Setting ADSTP to ‘1’ is only effective when ADSTART = 1 and ADDIS = 0 (ADC is enabled and
may be converting and there is no pending request to disable the ADC)
Bit 3 Reserved, must be kept at reset value.
RM0503 Rev 2
367/1325
384
Analog-to-digital converter (ADC)
RM0503
Bit 2 ADSTART: ADC start conversion command
This bit is set by software to start ADC conversion. Depending on the EXTEN [1:0] configuration bits,
a conversion either starts immediately (software trigger configuration) or once a hardware trigger
event occurs (hardware trigger configuration).
It is cleared by hardware:
– In single conversion mode (CONT = 0, DISCEN = 0), when software trigger is selected
(EXTEN = 00): at the assertion of the end of Conversion Sequence (EOS) flag.
– In discontinuous conversion mode(CONT = 0, DISCEN = 1), when the software trigger is selected
(EXTEN = 00): at the assertion of the end of Conversion (EOC) flag.
– In all other cases: after the execution of the ADSTP command, at the same time as the ADSTP bit is
cleared by hardware.
0: No ADC conversion is ongoing.
1: Write 1 to start the ADC. Read 1 means that the ADC is operating and may be converting.
Note: The software is allowed to set ADSTART only when ADEN = 1 and ADDIS = 0 (ADC is enabled
and there is no pending request to disable the ADC).
After writing to ADC_CHSELR register or changing CHSELRMOD or SCANDIRW, it is
mandatory to wait until CCRDY flag is asserted before setting ADSTART, otherwise, the value
written to ADSTART is ignored.
Bit 1 ADDIS: ADC disable command
This bit is set by software to disable the ADC (ADDIS command) and put it into power-down state
(OFF state).
It is cleared by hardware once the ADC is effectively disabled (ADEN is also cleared by hardware at
this time).
0: No ADDIS command ongoing
1: Write 1 to disable the ADC. Read 1 means that an ADDIS command is in progress.
Note: Setting ADDIS to ‘1’ is only effective when ADEN = 1 and ADSTART = 0 (which ensures that no
conversion is ongoing)
Bit 0 ADEN: ADC enable command
This bit is set by software to enable the ADC. The ADC is effectively ready to operate once the
ADRDY flag has been set.
It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS command.
0: ADC is disabled (OFF state)
1: Write 1 to enable the ADC.
Note: The software is allowed to set ADEN only when all bits of ADC_CR registers are 0 (ADCAL = 0,
ADSTP = 0, ADSTART = 0, ADDIS = 0 and ADEN = 0)
368/1325
RM0503 Rev 2
RM0503
Analog-to-digital converter (ADC)
14.13.4
ADC configuration register 1 (ADC_CFGR1)
Address offset: 0x0C
Reset value: 0x0000 0000
The software is allowed to program ADC_CFGR1 only when ADEN is cleared in ADC_CR.
31
30
29
Res.
15
28
27
26
AWD1CH[4:0]
rw
rw
rw
rw
rw
14
13
12
11
10
AUTOF
F
WAIT
CONT
OVRM
OD
rw
rw
rw
rw
EXTEN[1:0]
rw
rw
25
24
Res.
Res.
9
8
Res.
23
22
21
AWD1E AWD1S CHSEL
N
GL
RMOD
rw
rw
rw
7
6
5
EXTSEL[2:0]
rw
rw
ALIGN
rw
rw
20
19
18
17
16
DISCE
N
Res.
Res.
Res.
Res.
4
3
2
1
rw
RES[1:0]
rw
rw
0
SCAND DMAC
IR
FG
rw
rw
DMAE
N
rw
Bit 31 Reserved, must be kept at reset value.
Bits 30:26 AWD1CH[4:0]: Analog watchdog channel selection
These bits are set and cleared by software. They select the input channel to be guarded by
the analog watchdog.
00000: ADC analog input Channel 0 monitored by AWD
00001: ADC analog input Channel 1 monitored by AWD
.....
10011: ADC analog input Channel 19 monitored by AWD
Others: Reserved
Note: The channel selected by the AWDCH[4:0] bits must be also set into the CHSELR
register.
Bits 25:24 Reserved, must be kept at reset value.
Bit 23 AWD1EN: Analog watchdog enable
This bit is set and cleared by software.
0: Analog watchdog 1 disabled
1: Analog watchdog 1 enabled
Bit 22 AWD1SGL: Enable the watchdog on a single channel or on all channels
This bit is set and cleared by software to enable the analog watchdog on the channel
identified by the AWDCH[4:0] bits or on all the channels
0: Analog watchdog 1 enabled on all channels
1: Analog watchdog 1 enabled on a single channel
Bit 21 CHSELRMOD: Mode selection of the ADC_CHSELR register
This bit is set and cleared by software to control the ADC_CHSELR feature:
0: Each bit of the ADC_CHSELR register enables an input
1: ADC_CHSELR register is able to sequence up to 8 channels
Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register
or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
Bits 20:17 Reserved, must be kept at reset value.
RM0503 Rev 2
369/1325
384
Analog-to-digital converter (ADC)
RM0503
Bit 16 DISCEN: Discontinuous mode
This bit is set and cleared by software to enable/disable discontinuous mode.
0: Discontinuous mode disabled
1: Discontinuous mode enabled
Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is
forbidden to set both bits DISCEN = 1 and CONT = 1.
Bit 15 AUTOFF: Auto-off mode
This bit is set and cleared by software to enable/disable auto-off mode..
0: Auto-off mode disabled
1: Auto-off mode enabled
Bit 14 WAIT: Wait conversion mode
This bit is set and cleared by software to enable/disable wait conversion mode..
0: Wait conversion mode off
1: Wait conversion mode on
Bit 13 CONT: Single / continuous conversion mode
This bit is set and cleared by software. If it is set, conversion takes place continuously until it
is cleared.
0: Single conversion mode
1: Continuous conversion mode
Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is
forbidden to set both bits DISCEN = 1 and CONT = 1.
Bit 12 OVRMOD: Overrun management mode
This bit is set and cleared by software and configure the way data overruns are managed.
0: ADC_DR register is preserved with the old data when an overrun is detected.
1: ADC_DR register is overwritten with the last conversion result when an overrun is
detected.
Bits 11:10 EXTEN[1:0]: External trigger enable and polarity selection
These bits are set and cleared by software to select the external trigger polarity and enable
the trigger.
00: Hardware trigger detection disabled (conversions can be started by software)
01: Hardware trigger detection on the rising edge
10: Hardware trigger detection on the falling edge
11: Hardware trigger detection on both the rising and falling edges
Bit 9 Reserved, must be kept at reset value.
370/1325
RM0503 Rev 2
RM0503
Analog-to-digital converter (ADC)
Bits 8:6 EXTSEL[2:0]: External trigger selection
These bits select the external event used to trigger the start of conversion (refer to Table 67:
External triggers for details):
000: TRG0
001: TRG1
010: TRG2
011: TRG3
100: TRG4
101: TRG5
110: TRG6
111: TRG7
Bit 5 ALIGN: Data alignment
This bit is set and cleared by software to select right or left alignment. Refer to Figure 44:
Data alignment and resolution (oversampling disabled: OVSE = 0) on page 347
0: Right alignment
1: Left alignment
Bits 4:3 RES[1:0]: Data resolution
These bits are written by software to select the resolution of the conversion.
00: 12 bits
01: 10 bits
10: 8 bits
11: 6 bits
Bit 2 SCANDIR: Scan sequence direction
This bit is set and cleared by software to select the direction in which the channels is scanned
in the sequence. It is effective only if CHSELMOD bit is cleared.
0: Upward scan (from CHSEL0 to CHSEL)
1: Backward scan (from CHSEL to CHSEL0)
Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register
or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
Bit 1 DMACFG: Direct memory access configuration
This bit is set and cleared by software to select between two DMA modes of operation and is
effective only when DMAEN = 1.
0: DMA one shot mode selected
1: DMA circular mode selected
For more details, refer to Section 14.6.5: Managing converted data using the DMA on
page 348.
Bit 0 DMAEN: Direct memory access enable
This bit is set and cleared by software to enable the generation of DMA requests. This allows
the DMA controller to be used to manage automatically the converted data. For more details,
refer to Section 14.6.5: Managing converted data using the DMA on page 348.
0: DMA disabled
1: DMA enabled
RM0503 Rev 2
371/1325
384
Analog-to-digital converter (ADC)
14.13.5
RM0503
ADC configuration register 2 (ADC_CFGR2)
Address offset: 0x10
Reset value: 0x0000 0000
The software is allowed to program ADC_CFGR2 only when ADEN is cleared in ADC_CR.
31
30
CKMODE[1:0]
29
28
27
26
25
24
23
22
21
20
19
18
17
16
LFTRIG
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
8
7
6
5
4
3
2
1
0
Res.
OVSE
rw
rw
rw
15
14
13
12
11
10
9
Res.
Res.
Res.
Res.
Res.
Res.
TOVS
rw
OVSS[3:0]
rw
rw
rw
OVSR[2:0]
rw
rw
rw
rw
rw
Bits 31:30 CKMODE[1:0]: ADC clock mode
These bits are set and cleared by software to define how the analog ADC is clocked:
00: ADCCLK (Asynchronous clock mode), generated at product level (refer to RCC section)
01: PCLK/2 (Synchronous clock mode)
10: PCLK/4 (Synchronous clock mode)
In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of a
conversion.
Note: The software is allowed to write these bits only when the ADC is disabled (ADCAL = 0,
ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).
Bit 29 LFTRIG: Low frequency trigger mode enable
This bit is set and cleared by software.
0: Low Frequency Trigger Mode disabled
1: Low Frequency Trigger Mode enabled
Note: The software is allowed to write this bit only when ADEN bit is cleared.
Bits 28:10
Reserved, must be kept at reset value.
Bit 9 TOVS: Triggered Oversampling
This bit is set and cleared by software.
0: All oversampled conversions for a channel are done consecutively after a trigger
1: Each oversampled conversion for a channel needs a trigger
Note: The software is allowed to write this bit only when ADEN bit is cleared.
Bits 8:5 OVSS[3:0]: Oversampling shift
This bit is set and cleared by software.
0000: No shift
0001: Shift 1-bit
0010: Shift 2-bits
0011: Shift 3-bits
0100: Shift 4-bits
0101: Shift 5-bits
0110: Shift 6-bits
0111: Shift 7-bits
1000: Shift 8-bits
Others: Reserved
Note: The software is allowed to write this bit only when ADEN bit is cleared.
372/1325
RM0503 Rev 2
RM0503
Analog-to-digital converter (ADC)
Bits 4:2 OVSR[2:0]: Oversampling ratio
This bit filed defines the number of oversampling ratio.
000: 2x
001: 4x
010: 8x
011: 16x
100: 32x
101: 64x
110: 128x
111: 256x
Note: The software is allowed to write this bit only when ADEN bit is cleared.
Bit 1
Reserved, must be kept at reset value.
Bit 0 OVSE: Oversampler Enable
This bit is set and cleared by software.
0: Oversampler disabled
1: Oversampler enabled
Note: The software is allowed to write this bit only when ADEN bit is cleared.
14.13.6
ADC sampling time register (ADC_SMPR)
Address offset: 0x14
Reset value: 0x0000 0000
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
27
26
25
24
rw
rw
rw
22
21
20
19
18
17
16
SMPSE SMPSE SMPSE SMPSE SMPSE SMPSE SMPSE SMPSE SMPSE SMPSE SMPSE SMPSE
L19
L18
L17
L16
L15
L14
L13
L12
L11
L10
L9
L8
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
11
10
9
8
7
6
5
4
3
2
1
0
SMPSE SMPSE SMPSE SMPSE SMPSE SMPSE SMPSE SMPSE
L7
L6
L5
L4
L3
L2
L1
L0
rw
23
rw
rw
rw
Res.
rw
SMP2[2:0]
rw
rw
Res.
rw
SMP1[2:0]
rw
rw
rw
Bits 27:8 SMPSELx: Channel-x sampling time selection (x = 19 to 0)
These bits are written by software to define which sampling time is used.
0: Sampling time of CHANNELx use the setting of SMP1[2:0] register.
1: Sampling time of CHANNELx use the setting of SMP2[2:0] register.
Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no
conversion is ongoing).
Bit 7 Reserved, must be kept at reset value.
RM0503 Rev 2
373/1325
384
Analog-to-digital converter (ADC)
RM0503
Bits 6:4 SMP2[2:0]: Sampling time selection 2
These bits are written by software to select the sampling time that applies to all channels.
000: 1.5 ADC clock cycles
001: 3.5 ADC clock cycles
010: 7.5 ADC clock cycles
011: 12.5 ADC clock cycles
100: 19.5 ADC clock cycles
101: 39.5 ADC clock cycles
110: 79.5 ADC clock cycles
111: 160.5 ADC clock cycles
Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no
conversion is ongoing).
Bit 3 Reserved, must be kept at reset value.
Bits 2:0 SMP1[2:0]: Sampling time selection 1
These bits are written by software to select the sampling time that applies to all channels.
000: 1.5 ADC clock cycles
001: 3.5 ADC clock cycles
010: 7.5 ADC clock cycles
011: 12.5 ADC clock cycles
100: 19.5 ADC clock cycles
101: 39.5 ADC clock cycles
110: 79.5 ADC clock cycles
111: 160.5 ADC clock cycles
Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no
conversion is ongoing).
14.13.7
ADC watchdog threshold register (ADC_AWD1TR)
Address offset: 0x20
Reset value: 0x0FFF 0000
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
27
26
25
24
23
22
21
20
19
18
17
16
HT1[11:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
LT1[11:0]
rw
rw
rw
rw
rw
rw
rw
Bits 31:28 Reserved, must be kept at reset value.
Bits 27:16 HT1[11:0]: Analog watchdog 1 higher threshold
These bits are written by software to define the higher threshold for the analog watchdog.
Refer to Section 14.8: Analog window watchdogs on page 352.
Bits 15:12 Reserved, must be kept at reset value.
Bits 11:0 LT1[11:0]: Analog watchdog 1 lower threshold
These bits are written by software to define the lower threshold for the analog watchdog.
Refer to Section 14.8: Analog window watchdogs on page 352.
374/1325
RM0503 Rev 2
RM0503
Analog-to-digital converter (ADC)
14.13.8
ADC watchdog threshold register (ADC_AWD2TR)
Address offset: 0x24
Reset value: 0x0FFF 0000
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
27
26
25
24
23
22
21
20
19
18
17
16
HT2[11:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
LT2[11:0]
rw
rw
rw
rw
rw
rw
rw
Bits 31:28 Reserved, must be kept at reset value.
Bits 27:16 HT2[11:0]: Analog watchdog 2 higher threshold
These bits are written by software to define the higher threshold for the analog watchdog.
Refer to Section 14.8: Analog window watchdogs on page 352.
Bits 15:12 Reserved, must be kept at reset value.
Bits 11:0 LT2[11:0]: Analog watchdog 2 lower threshold
These bits are written by software to define the lower threshold for the analog watchdog.
Refer to Section 14.8: Analog window watchdogs on page 352.
RM0503 Rev 2
375/1325
384
Analog-to-digital converter (ADC)
14.13.9
RM0503
ADC channel selection register (ADC_CHSELR)
Address offset: 0x28
Reset value: 0x0000 0000
The same register can be used in two different modes:
– Each ADC_CHSELR bit enables an input (CHSELRMOD = 0 in ADC_CFGR1). Refer to
the current section.
– ADC_CHSELR is able to sequence up to 8 channels (CHSELRMOD = 1 in
ADC_CFGR1). Refer to next section.
CHSELRMOD = 0 in ADC_CFGR1
31
30
29
28
27
26
25
24
23
22
21
20
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
19
18
17
16
CHSEL CHSEL CHSEL CHSEL
19
18
17
16
rw
rw
rw
rw
3
2
1
0
CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:20 Reserved, must be kept at reset value.
Bits 19:0 CHSEL[19:0]: Channel-x selection
These bits are written by software and define which channels are part of the sequence of channels
to be converted.
0: Input Channel-x is not selected for conversion
1: Input Channel-x is selected for conversion
Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no
conversion is ongoing).
If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or
changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
376/1325
RM0503 Rev 2
RM0503
Analog-to-digital converter (ADC)
14.13.10 ADC channel selection register [alternate] (ADC_CHSELR)
Address offset: 0x28
Reset value: 0x0000 0000
The same register can be used in two different modes:
– Each ADC_CHSELR bit enables an input (CHSELRMOD = 0 in ADC_CFGR1). Refer to
the current previous section.
– ADC_CHSELR is able to sequence up to 8 channels (CHSELRMOD = 1 in
ADC_CFGR1). Refer to this section.
CHSELRMOD = 1 in ADC_CFGR1:
31
30
29
28
27
SQ8[3:0]
26
25
24
23
SQ7[3:0]
22
21
20
19
SQ6[3:0]
18
17
16
SQ5[3:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SQ4[3:0]
rw
rw
rw
SQ3[3:0]
rw
rw
rw
rw
SQ2[3:0]
rw
rw
rw
rw
SQ1[3:0]
rw
rw
rw
rw
rw
Bits 31:28 SQ8[3:0]: 8th conversion of the sequence
These bits are programmed by software with the channel number (0...14) assigned to the 8th
conversion of the sequence. 0b1111 indicates the end of the sequence.
When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are
ignored.
0000: CH0
0001: CH1
...
1100: CH12
1101: CH13
1110: CH14
1111: No channel selected (End of sequence)
Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no
conversion is ongoing).
Bits 27:24 SQ7[3:0]: 7th conversion of the sequence
These bits are programmed by software with the channel number (0...14) assigned to the 8th
conversion of the sequence. 0b1111 indicates end of the sequence.
When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are
ignored.
Refer to SQ8[3:0] for a definition of channel selection.
Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no
conversion is ongoing).
Bits 23:20 SQ6[3:0]: 6th conversion of the sequence
These bits are programmed by software with the channel number (0...14) assigned to the 8th
conversion of the sequence. 0b1111 indicates end of the sequence.
When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are
ignored.
Refer to SQ8[3:0] for a definition of channel selection.
Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no
conversion is ongoing).
RM0503 Rev 2
377/1325
384
Analog-to-digital converter (ADC)
RM0503
Bits 19:16 SQ5[3:0]: 5th conversion of the sequence
These bits are programmed by software with the channel number (0...14) assigned to the 8th
conversion of the sequence. 0b1111 indicates end of the sequence.
When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are
ignored.
Refer to SQ8[3:0] for a definition of channel selection.
Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no
conversion is ongoing).
Bits 15:12 SQ4[3:0]: 4th conversion of the sequence
These bits are programmed by software with the channel number (0...14) assigned to the 8th
conversion of the sequence. 0b1111 indicates end of the sequence.
When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are
ignored.
Refer to SQ8[3:0] for a definition of channel selection.
Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no
conversion is ongoing).
Bits 11:8 SQ3[3:0]: 3rd conversion of the sequence
These bits are programmed by software with the channel number (0...14) assigned to the 8th
conversion of the sequence. 0b1111 indicates end of the sequence.
When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are
ignored.
Refer to SQ8[3:0] for a definition of channel selection.
Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no
conversion is ongoing).
Bits 7:4 SQ2[3:0]: 2nd conversion of the sequence
These bits are programmed by software with the channel number (0...14) assigned to the 8th
conversion of the sequence. 0b1111 indicates end of the sequence.
When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are
ignored.
Refer to SQ8[3:0] for a definition of channel selection.
Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no
conversion is ongoing).
Bits 3:0 SQ1[3:0]: 1st conversion of the sequence
These bits are programmed by software with the channel number (0...14) assigned to the 8th
conversion of the sequence. 0b1111 indicates end of the sequence.
When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are
ignored.
Refer to SQ8[3:0] for a definition of channel selection.
Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no
conversion is ongoing).
378/1325
RM0503 Rev 2
RM0503
Analog-to-digital converter (ADC)
14.13.11 ADC watchdog threshold register (ADC_AWD3TR)
Address offset: 0x2C
Reset value: 0x0FFF 0000
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
27
26
25
24
23
22
21
20
19
18
17
16
HT3[11:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
LT3[11:0]
rw
rw
rw
rw
rw
rw
rw
Bits 31:28 Reserved, must be kept at reset value.
Bits 27:16 HT3[11:0]: Analog watchdog 3 higher threshold
These bits are written by software to define the higher threshold for the analog watchdog.
Refer to Section 14.8: Analog window watchdogs on page 352.
Bits 15:12 Reserved, must be kept at reset value.
Bits 11:0 LT3[11:0]: Analog watchdog 3lower threshold
These bits are written by software to define the lower threshold for the analog watchdog.
Refer to Section 14.8: Analog window watchdogs on page 352.
14.13.12 ADC data register (ADC_DR)
Address offset: 0x40
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r
r
r
r
r
r
r
DATA[15:0]
r
r
r
r
r
r
r
r
r
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 DATA[15:0]: Converted data
These bits are read-only. They contain the conversion result from the last converted channel. The
data are left- or right-aligned as shown in Figure 44: Data alignment and resolution (oversampling
disabled: OVSE = 0) on page 347.
Just after a calibration is complete, DATA[6:0] contains the calibration factor.
RM0503 Rev 2
379/1325
384
Analog-to-digital converter (ADC)
RM0503
14.13.13 ADC analog watchdog 2 configuration register (ADC_AWD2CR)
Address offset: 0xA0
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
AWD2
CH19
AWD2
CH18
AWD2
CH17
AWD2
CH16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
AWD2
CH15
AWD2
CH14
AWD2
CH13
AWD2
CH12
AWD2
CH11
AWD2
CH10
AWD2
CH9
AWD2
CH8
AWD2
CH7
AWD2
CH6
AWD2
CH5
AWD2
CH4
AWD2
CH3
AWD2
CH2
AWD2
CH1
AWD2
CH0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:20 Reserved, must be kept at reset value.
Bits 19:0 AWD2CH[19:0]: Analog watchdog channel selection
These bits are set and cleared by software. They enable and select the input channels to be guarded
by analog watchdog 2 (AWD2).
0: ADC analog channel-x is not monitored by AWD2
1: ADC analog channel-x is monitored by AWD2
Note: The channels selected through ADC_AWD2CR must be also configured into the
ADC_CHSELR registers. The software is allowed to write this bit only when ADEN = 0.
14.13.14 ADC Analog Watchdog 3 Configuration register (ADC_AWD3CR)
Address offset: 0xA4
Reset value: 0x0000 0000
31
Res.
30
Res.
29
Res.
28
Res.
27
Res.
26
Res.
25
Res.
24
Res.
23
Res.
22
Res.
21
Res.
20
19
18
17
16
Res.
AWD3
CH19
AWD3
CH18
AWD3
CH17
AWD3
CH16
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
AWD3
CH15
AWD3
CH14
AWD3
CH13
AWD3
CH12
AWD3
CH11
AWD3
CH10
AWD3
CH9
AWD3
CH8
AWD3
CH7
AWD3
CH6
AWD3
CH5
AWD3
CH4
AWD3
CH3
AWD3
CH2
AWD3
CH1
AWD3
CH0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:20 Reserved, must be kept at reset value.
Bits 19:0 AWD3CH[19:0]: Analog watchdog channel selection
These bits are set and cleared by software. They enable and select the input channels to be guarded
by analog watchdog 3 (AWD3).
0: ADC analog channel-x is not monitored by AWD3
1: ADC analog channel-x is monitored by AWD3
Note: The channels selected through ADC_AWD3CR must be also configured into the
ADC_CHSELR registers. The software is allowed to write this bit only when ADEN = 0.
380/1325
RM0503 Rev 2
RM0503
Analog-to-digital converter (ADC)
14.13.15 ADC calibration factor (ADC_CALFACT)
Address offset: 0xB4
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
rw
rw
rw
CALFACT[6:0]
rw
rw
rw
rw
Bits 31:7 Reserved, must be kept at reset value.
Bits 6:0 CALFACT[6:0]: Calibration factor
These bits are written by hardware or by software.
– Once a calibration is complete, they are updated by hardware with the calibration factors.
– Software can write these bits with a new calibration factor. If the new calibration factor is different
from the current one stored into the analog ADC, it is then applied once a new conversion is
launched.
– Just after a calibration is complete, DATA[6:0] contains the calibration factor.
Note: Software can write these bits only when ADEN=1 (ADC is enabled and no calibration is ongoing
and no conversion is ongoing).
14.13.16 ADC common configuration register (ADC_CCR)
Address offset: 0x308
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
VBAT
EN
TSEN
VREF
EN
21
20
19
18
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
RM0503 Rev 2
PRESC[3:0]
17
381/1325
384
Analog-to-digital converter (ADC)
RM0503
Bits 31:25 Reserved, must be kept at reset value.
Bit 24 VBATEN: VBAT enable
This bit is set and cleared by software to enable/disable the VBAT channel.
0: VBAT channel disabled
1: VBAT channel enabled
Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no
conversion is ongoing)
Bit 23 TSEN: Temperature sensor enable
This bit is set and cleared by software to enable/disable the temperature sensor.
0: Temperature sensor disabled
1: Temperature sensor enabled
Note: Software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion
is ongoing).
Bit 22 VREFEN: VREFINT enable
This bit is set and cleared by software to enable/disable the VREFINT.
0: VREFINT disabled
1: VREFINT enabled
Note: Software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion
is ongoing).
Bits 21:18 PRESC[3:0]: ADC prescaler
Set and cleared by software to select the frequency of the clock to the ADC.
0000: input ADC clock not divided
0001: input ADC clock divided by 2
0010: input ADC clock divided by 4
0011: input ADC clock divided by 6
0100: input ADC clock divided by 8
0101: input ADC clock divided by 10
0110: input ADC clock divided by 12
0111: input ADC clock divided by 16
1000: input ADC clock divided by 32
1001: input ADC clock divided by 64
1010: input ADC clock divided by 128
1011: input ADC clock divided by 256
Other: Reserved
Note: Software is allowed to write these bits only when the ADC is disabled (ADCAL = 0,
ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).
Bits 17:0 Reserved, must be kept at reset value.
14.14
ADC register map
The following table summarizes the ADC registers.
382/1325
RM0503 Rev 2
EOS
EOSMP
ADRDY
0
EOC
0
Res.
0
OVR
AWD1
0
Res.
AWD2
0
Res.
0
AWD3
Res.
EOCAL
Res.
Res.
CCRDY.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
ADC_ISR
Res.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x00
Register
name
Res.
Offset
Res.
Table 75. ADC register map and reset values
0
0
0
0
...
Reset value
Reserved
0xA0
ADC_AWD2CR
AWD2CH12
AWD2CH11
AWD2CH10
AWD2CH9
AWD2CH8
AWD2CH7
AWD2CH6
AWD2CH5
AWD2CH4
AWD2CH3
AWD2CH2
AWD2CH1
AWD2CH0
1
AWD2CH13
1
AWD2CH14
1
0
AWD2CH15
0
1
0
1
Reserved
HT3[11:0]
0
1
RM0503 Rev 2
0
0
0
0
0
Res.
SQ5[3:0]
0 0
Reserved
0
0
0
0
0
CHSEL0
0
0
CHSEL1
0
0
CHSEL2
CHSEL13
0
0
CHSEL3
CHSEL14
0
0
CHSEL4
CHSEL15
0
0
CHSEL5
CHSEL16
0
0
CHSEL6
CHSEL17
0
0
CHSEL7
1
CHSEL8
1
CHSEL9
1
CHSEL10
1
CHSEL11
1
CHSEL18
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
SMPSEL14
SMPSEL13
SMPSEL12
SMPSEL11
SMPSEL10
SMPSEL9
SMPSEL6
SMPSEL5
SMPSEL4
SMPSEL3
SMPSEL2
SMPSEL1
SMPSEL0
0
0
0
0
0
0
0
0
0
0
0 0 0 0
Reserved
Reserved
0
0
0
0
0
0
Res.
CHSELRMOD
Res.
WAIT
CONT
OVRMOD
EXTEN[1:0]
0
0
0
0
0
1
0
SQ4[3:0]
1
0
0
Res.
Res.
Res.
Res.
Res.
0
0
0
0
0
0
0
0
0
0
0
SQ3[3:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SMP2
[2:0]
0
0
0
0
SQ2[3:0]
EOSMPIE
ADRDYIE
ADEN
0
ADDIS
0
0
0
0
DMAEN
0
DMACFG
EOSIE
EOCIE
0
ADSTART
0
Res.
Res.
OVRIE
ADSTP
Res.
0
SCANDIR
0
Res.
OVSE
AWD1IE
Res.
Res.
AWD2IE
Res.
Res.
AWD3IE
0
OVSR[2:0]
Res.
EOCALIE
Res.
CCRDYIE.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
0
0
Res.
RES
[1:0]
OVSS[3:0]
EXTSEL
[2:0]
ALIGN
Res.
AUTOFF
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
TOVS
DISCEN
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
AWD1SGL
Res.
Res.
AWD1EN
Res.
Res.
Res.
Res.
Res.
Res.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ADC_IER
Res.
Register
name
0
Res.
SMPSEL7
SMPSEL8
SMPSEL15
Res.
Res.
ADVREGEN
Reset value
CHSEL12
1
CHSEL19
1
Res.
1
Res
HT2[11:0]
Res.
1
Res
HT1[11:0]
Res.
SQ6[3:0]
1
Res.
1
0
AWD2CH16
0
1
Res.
0
1
AWD2CH17
SQ7[3:0]
1
Res.
1
Res
1
AWD2CH18
1
Res.
SMPSEL16
Res.
0
Res.
1
0
Res.
1
0
0
Res
1
0
1
Res.
1
0
1
Res
0
1
Res.
SQ8[3:0]
1
Res
1
Res.
0
Res.
0
Res.
Reset value
SMPSEL17
0
Res.
0
SMPSEL18.
0
LFTRIG
Res.
AWDCH[4:0]
Res.
ADCAL
ADC_CFGR1
Res.
0
SMPSEL19.
Res..
Res..
CKMODE[1:0]
0
Res.
0
1
Res.
Res.
Res.
Res.
Res..
0
Res.
Reset value
Res.
1
Res.
Reset value
Res.
Res.
Res.
Reset value
Reserved
Reserved
Res.
Res.
Res.
Res.
Reset value
AWD2CH19
Reset value
Res.
ADC_CR
Res.
ADC_DR
0
Res.
ADC_AWD3TR
Res.
Reset value
ADC_CHSELR
(CHSELRMOD=
1)
Reset value
0
Res.
0x40
0
Res.
0x30
0x34
0x38
0x3C
Reset value
Res.
0x2C
ADC_CFGR2
Res.
0x28
ADC_CHSELR
(CHSELRMOD=
0)
0
Res.
0x28
ADC_AWD2TR
Res.
Reset value
Res.
0x24
ADC_AWD1TR
Res.
0x20
Res.
0x18
0x1C
ADC_SMPR
Res.
0x14
Res.
0x10
Res.
0x0C
Res.
0x08
Res.
0x04
Res.
Offset
Res.
RM0503
Analog-to-digital converter (ADC)
Table 75. ADC register map and reset values (continued)
0
0
0
SMP1
[2:0]
0
0
0
0
0
LT1[11:0]
LT2[11:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SQ1[3:0]
LT3[11:0]
0
0
0
0
0
0
0
0
0
0
0
Reserved
DATA[15:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
383/1325
384
0x308
384/1325
ADC_CCR
VREFEN
PRESC3
PRESC2
PRESC1
PRESC0
0
0
0
0
0
0
0
RM0503 Rev 2
Refer to Section 2.2 for the register boundary addresses.
0
0
0
0
0
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Reserved
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
Reserved
Res.
AWD3CH17
AWD3CH14
AWD3CH13
AWD3CH12
AWD3CH11
AWD3CH10
AWD3CH9
AWD3CH8
AWD3CH7
AWD3CH6
AWD3CH5
AWD3CH4
AWD3CH3
AWD3CH2
AWD3CH1
AWD3CH0
0 0 0 0
Reserved
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
AWD3CH15
AWD3CH16
AWD3CH18
0
Res.
AWD3CH19
Res
Res
Res
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
Reserved
Res.
TSEN
Res.
Res.
VBATEN
Reset value
Res.
...
Res.
ADC_CALFACT
Res.
...
Res.
0xB4
ADC_AWD3CR
Res.
0xA4
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Register
name
Res.
Offset
Res.
Analog-to-digital converter (ADC)
RM0503
Table 75. ADC register map and reset values (continued)
CALFACT[6:0]
RM0503
Digital-to-analog converter (DAC)
15
Digital-to-analog converter (DAC)
15.1
Introduction
The DAC module is a 12-bit, voltage output digital-to-analog converter. The DAC can be
configured in 8- or 12-bit mode and may be used in conjunction with the DMA controller.
In 12-bit mode, the data can be left- or right-aligned. The DAC features one single channel.
An input reference pin, VREF+ (shared with others analog peripherals) is available for better
resolution. An internal reference can also be set on the same input. Refer to voltage
reference buffer (VREFBUF) section.
The DACx_OUT1 pin can be used as general purpose input/output (GPIO) when the DAC
output is disconnected from output pad and connected to on chip peripheral. The DAC
output buffer can be optionally enabled to obtain a high drive output current. An individual
calibration can be applied on each DAC output channel. The DAC output channels support
a low power mode, the Sample and hold mode.
15.2
DAC main features
The DAC main features are the following (see Figure 58: DAC block diagram)
•
One DAC interface
•
Left or right data alignment in 12-bit mode
•
Synchronized update capability
•
Noise-wave and Triangular-wave generation
•
Single DAC channel
•
DMA capability including DMA underrun error detection
•
External triggers for conversion
•
DAC output channel buffered/unbuffered modes
•
Buffer offset calibration
•
The DAC output can be disconnected from the DACx_OUT1 output pin
•
DAC output connection to on-chip peripherals
•
Sample and hold mode for low power operation in Stop mode
•
Input voltage reference from VREF+ pin or internal VREFBUF reference
Figure 58 shows the block diagram of a DAC channel and Table 77 gives the pin
description.
RM0503 Rev 2
385/1325
409
Digital-to-analog converter (DAC)
15.3
RM0503
DAC implementation
Table 76. DAC features
DAC features
DAC
Dual channel
-
Output buffer
X
I/O connection
DAC_OUT1 to PA4
Maximum sampling time
1 Msps
Autonomous mode
-
VREF+ pin
X
15.4
DAC functional description
15.4.1
DAC block diagram
Figure 58. DAC block diagram
VDD
Offset
calibration
TRIG
MODE1 bits
dac_ch1_trg15
TSEL1
[3:0]
bits
dac_ch1_dma
dac_unr_it
dac_pclk
OTRIM1[4:0]
bits
DAC_OUT1
dac_ch1_trg1
DAC
converter
DOR1
Buffer
12-bit
Control registers
and logic
channel1
Sample and hold
registers
dac_out1
VREF+
TSAMPLE1
dac_hold_ck
32-bit APB
bus
THOLD1
TREFRESH1
VSS
MSv61355V6
1. MODE1 bits in the DAC_MCR control the output mode and allow switching between the Normal mode in
buffer/unbuffered configuration and the Sample and hold mode.
386/1325
RM0503 Rev 2
RM0503
15.4.2
Digital-to-analog converter (DAC)
DAC pins and internal signals
The DAC includes:
•
One output channel
•
The DACx_OUT1 can be disconnected from the output pin and used as an ordinary
GPIO
•
The dac_outx can use an internal pin connection to on-chip peripherals such as
comparator, operational amplifier and ADC (if available).
•
DAC output channel buffered or non buffered
•
Sample and hold block and registers operational in Stop mode, using the LSI clock
source (dac_hold_ck) for static conversion.
The DAC includes one output channel. The output channel can be connected to on-chip
peripherals such as comparator, operational amplifier and ADC (if available). In this case,
the DAC output channel can be disconnected from the DACx_OUT1 output pin and the
corresponding GPIO can be used for another purpose.
The DAC output can be buffered or not. The Sample and hold block and its associated
registers can run in Stop mode using the LSI clock source (dac_hold_ck).
Table 77. DAC input/output pins
Pin name
Signal type
Remarks
VREF+
Input, analog positive
reference
The higher/positive reference voltage for the DAC,
VREF+ ≤ VDDAmax (refer to datasheet)
VDD
Input, analog supply
Analog power supply
VSS
Input, analog supply ground
Ground for analog power supply
DACx_OUT1 Analog output signal
DACx channel1 analog output
Table 78. DAC internal input/output signals
Internal signal name
dac_ch1_dma
Signal type
Description
Bidirectional DAC channel1 DMA request/acknowledge
dac_ch1_trgx (x = 1 to 14)
Inputs
DAC channel1 trigger inputs/acknowledge
dac_unr_it
Output
DAC underrun interrupt
dac_pclk
Input
DAC peripheral clock
dac_hold_ck
Input
DAC low-power clock used in Sample and hold mode
dac_out1
Analog
output
DAC channel1 output for on-chip peripherals
Table 79. DAC interconnection
Signal name
Source
Source type
dac_hold_ck
ck_lsi
LSI clock
dac_ch1_trg1
tim1_trgo
Internal signal from on-chip
timers TIM1_TGO_CKTIM
RM0503 Rev 2
387/1325
409
Digital-to-analog converter (DAC)
RM0503
Table 79. DAC interconnection (continued)
15.4.3
Signal name
Source
Source type
dac_ch1_trg2
tim2_trgo
Internal signal from on-chip
timers TIM2_TGO_CKTIM
dac_ch1_trg3
tim3_trgo
internal signal from on-chip
timers TIM3_TGO_CKTIM
dac_ch1_trg5
tim6_trgo
internal signal from on-chip
timers TIM6_TGO_CKTIM
dac_ch1_trg6
tim7_trgo
internal signal from on-chip
timers TIM7_TGO_CKTIM
dac_ch1_trg8
tim15_trgo
internal signal from on-chip
timers TIM15_TGO_CKTIM
dac_ch1_trg11
lptim1_out
Internal signal from on-chip
timers LPTIM1_OUT
dac_ch1_trg12
lptim2_out
Internal signal from on-chip
timers LPTIM2_OUT
dac_ch1_trg14
exti9
External pin EXTI[9]
DAC channel enable
The DAC channel can be powered on by setting its corresponding EN1 bit in the DAC_CR
register. The DAC channel is then enabled after a tWAKEUP startup time.
Note:
The EN1 bit enables the analog DAC channel1 only. The DAC channel1 digital interface is
enabled even if the EN1 bit is reset.
15.4.4
DAC data format
Depending on the selected configuration mode, the data have to be written into the specified
register as described below:
•
Single DAC channel
There are three possibilities:
–
8-bit right alignment: the software has to load data into the DAC_DHR8R1[7:0] bits
(stored into the DHR1[11:4] bits)
–
12-bit left alignment: the software has to load data into the DAC_DHR12L1 [15:4]
bits (stored into the DHR1[11:0] bits)
–
12-bit right alignment: the software has to load data into the DAC_DHR12R1 [11:0]
bits (stored into the DHR1[11:0] bits)
Depending on the loaded DAC_DHRyyyx register, the data written by the user is shifted and
stored into the corresponding DHR1 (data holding registerx, which are internal nonmemory-mapped registers). The DHR1 register is then loaded into the DOR1 register either
automatically, by software trigger or by an external event trigger.
388/1325
RM0503 Rev 2
RM0503
Digital-to-analog converter (DAC)
Figure 59. Data registers in single DAC channel mode
31
24
15
7
0
8-bit right aligned
12-bit left aligned
12-bit right aligned
ai14710b
15.4.5
DAC conversion
The DAC_DOR1 cannot be written directly and any data transfer to the DAC channel1 must
be performed by loading the DAC_DHR1 register (write operation to DAC_DHR8R1,
DAC_DHR12L1, DAC_DHR12R1).
Data stored in the DAC_DHR1 register are automatically transferred to the DAC_DOR1
register after one dac_pclk clock cycle, if no hardware trigger is selected (TEN1 bit in
DAC_CR register is reset). However, when a hardware trigger is selected (TEN1 bit in
DAC_CR register is set) and a trigger occurs, the transfer is performed three dac_pclk clock
cycles after the trigger signal.
When DAC_DOR1 is loaded with the DAC_DHR1 contents, the analog output voltage
becomes available after a time tSETTLING that depends on the power supply voltage and the
analog output load.
Figure 60. Timing diagram for conversion with trigger disabled TEN = 0
Bus clock
DHR
0x1AC
0x1AC
DOR
Output voltage available on
DAC_OUT pin
tSETTLING
MSv45319V2
15.4.6
DAC output voltage
Digital inputs are converted to output voltages on a linear conversion between 0 and VREF+.
The analog output voltage on the DAC channel pin is determined by the following equation:
DOR
DACoutput = V REF × -------------4096
where
all voltages are expressed in volt.
RM0503 Rev 2
389/1325
409
Digital-to-analog converter (DAC)
15.4.7
RM0503
DAC trigger selection
If the TEN1 control bit is set, the conversion can then be triggered by an external event (timer
counter, external interrupt line). The TSEL1[3:0] control bits determine which out of 16 possible events triggers the conversion as shown in TSEL1[3:0] bits of the DAC_CR register.
These events can be either the software trigger or hardware triggers. Refer to the interconnection table in Section 15.4.2: DAC pins and internal signals.
Each time a DAC interface detects a rising edge on the selected trigger source (refer to the
table below), the last data stored into the DAC_DHR1 register are transferred into the
DAC_DOR1 register. The DAC_DOR1 register is updated three dac_pclk cycles after the
trigger occurs.
If the software trigger is selected, the conversion starts once the SWTRIG bit is set.
SWTRIG is reset by hardware once the DAC_DOR1 register has been loaded with the
DAC_DHR1 register contents.
Note:
TSEL1[3:0] bit cannot be changed when the EN1 bit is set.
When software trigger is selected, the transfer from the DAC_DHR1 register to the
DAC_DOR1 register takes only one dac_pclk clock cycle.
15.4.8
DMA requests
The DAC channel has a DMA capability. One DMA channel is used to service DAC channel
DMA request.
When an external trigger (but not a software trigger) occurs while the DMAEN1 bit is set, the
value of the DAC_DHR1 register is transferred into the DAC_DOR1 register when the
transfer is complete, and a DMA request is generated.
As DAC_DHR1 to DAC_DOR1 data transfer occurred before the DMA request, the very first
data has to be written to the DAC_DHR1 before the first trigger event occurs.
DMA underrun
The DAC DMA request is not queued so that if a second external trigger arrives before the
acknowledgment for the first external trigger is received (first request), then no new request
is issued and the DMA channel1 underrun flag DMAUDR1 in the DAC_SR register is set,
reporting the error condition. The DAC channel1 continues to convert old data.
The software must clear the DMAUDR1 flag by writing 1, clear the DMAEN bit of the used
DMA stream and re-initialize both DMA and DAC channel1 to restart the transfer correctly.
The software must modify the DAC trigger conversion frequency or lighten the DMA
workload to avoid a new DMA underrun. Finally, the DAC conversion can be resumed
by enabling both DMA data transfer and conversion trigger.
For DAC channel1, an interrupt is also generated if its corresponding DMAUDRIE1 bit in the
DAC_CR register is enabled.
15.4.9
Noise generation
In order to generate a variable-amplitude pseudonoise, an LFSR (linear feedback shift
register) is available. DAC noise generation is selected by setting WAVE1[1:0] to 01. The
preloaded value in LFSR is 0xAAA. This register is updated three dac_pclk clock cycles
after each trigger event, following a specific calculation algorithm.
390/1325
RM0503 Rev 2
RM0503
Digital-to-analog converter (DAC)
Figure 61. DAC LFSR register calculation algorithm
XOR
X6
X 12
11
10
9
8
7
6
X4
5
4
X0
X
3
2
1
0
12
NOR
ai14713c
The LFSR value, that may be masked partially or totally by means of the MAMP1[3:0] bits in
the DAC_CR register, is added up to the DAC_DHR1 contents without overflow and this
value is then transferred into the DAC_DOR1 register.
If LFSR is 0x0000, a ‘1 is injected into it (antilock-up mechanism).
It is possible to reset LFSR wave generation by resetting the WAVE1[1:0] bits.
Figure 62. DAC conversion (SW trigger enabled) with LFSR wave generation
dac_pclk
DHR
DOR
0x00
0xAAA
0xD55
SWTRIG
MS45320V1
Note:
The DAC trigger must be enabled for noise generation by setting the TEN1 bit in the
DAC_CR register.
RM0503 Rev 2
391/1325
409
Digital-to-analog converter (DAC)
15.4.10
RM0503
Triangle-wave generation
It is possible to add a small-amplitude triangular waveform on a DC or slowly varying signal.
DAC triangle-wave generation is selected by setting WAVE1[1:0] to 10. The amplitude is
configured through the MAMP1[3:0] bits in the DAC_CR register. An internal triangle
counter is incremented three dac_pclk clock cycles after each trigger event. The value of
this counter is then added to the DAC_DHR1 register without overflow and the sum is
transferred into the DAC_DOR1 register. The triangle counter is incremented as long as it is
less than the maximum amplitude defined by the MAMP1[3:0] bits. Once the configured
amplitude is reached, the counter is decremented down to 0, then incremented again and so
on.
It is possible to reset triangle wave generation by resetting the WAVE1[1:0] bits.
Figure 63. DAC triangle wave generation
ti
re
m
on ent
a
In
c
n
tio
ta
en
m
e
cr
De
MAMP1[3:0] max amplitude+
DAC_DHR1 base value
DAC_DHR1 base value
0
MSv61371V1
Figure 64. DAC conversion (SW trigger enabled) with triangle wave generation
dac_pclk
DHR
DOR
0xABE
0xABE
0xABF
0xAC0
SWTRIG
MS45321V1
Note:
The DAC trigger must be enabled for triangle wave generation by setting the TEN1 bit in the
DAC_CR register.
The MAMP1[3:0] bits must be configured before enabling the DAC, otherwise they cannot
be changed.
392/1325
RM0503 Rev 2
RM0503
15.4.11
Digital-to-analog converter (DAC)
DAC channel modes
The DAC channel can be configured in Normal mode or Sample and hold mode. The output
buffer can be enabled to obtain a high drive capability. Before enabling output buffer, the
voltage offset needs to be calibrated. This calibration is performed at the factory (loaded
after reset) and can be adjusted by software during application operation.
Normal mode
In Normal mode, there are four combinations, by changing the buffer state and by changing
the DACx_OUT1 pin interconnections.
To enable the output buffer, the MODE1[2:0] bits in DAC_MCR register must be:
•
000: DAC is connected to the external pin
•
001: DAC is connected to external pin and to on-chip peripherals
To disable the output buffer, the MODE1[2:0] bits in DAC_MCR register must be:
•
010: DAC is connected to the external pin
•
011: DAC is connected to on-chip peripherals
Sample and hold mode
In Sample and hold mode, the DAC core converts data on a triggered conversion, and then
holds the converted voltage on a capacitor. When not converting, the DAC cores and buffer
are completely turned off between samples and the DAC output is tri-stated, therefore
reducing the overall power consumption. A stabilization period, which value depends on the
buffer state, is required before each new conversion.
In this mode, the DAC core and all corresponding logic and registers are driven by the LSI
low-speed clock (dac_hold_ck) in addition to the dac_pclk clock, allowing using the DAC
channel in deep low power modes such as Stop mode.
The LSI low-speed clock (dac_hold_ck) must not be stopped when the Sample and hold
mode is enabled.
The sample/hold mode operations can be divided into 3 phases:
1.
Sample phase: the sample/hold element is charged to the desired voltage. The
charging time depends on capacitor value (internal or external, selected by the user).
The sampling time is configured with the TSAMPLE1[9:0] bits in DAC_SHSR1 register.
During the write of the TSAMPLE1[9:0] bits, the BWST1 bit in DAC_SR register is set
to 1 to synchronize between both clocks domains (APB and low speed clock) and
allowing the software to change the value of sample phase during the DAC channel
operation
2.
Hold phase: the DAC output channel is tri-stated, the DAC core and the buffer are
turned off, to reduce the current consumption. The hold time is configured with the
THOLD1[9:0] bits in DAC_SHHR register
3.
Refresh phase: the refresh time is configured with the TREFRESH1[7:0] bits in
DAC_SHRR register
RM0503 Rev 2
393/1325
409
Digital-to-analog converter (DAC)
RM0503
The timings for the three phases above are in units of LSI clock periods. As an example, to
configure a sample time of 350 µs, a hold time of 2 ms and a refresh time of 100 µs
assuming LSI ~32 KHz is selected:
12 cycles are required for sample phase: TSAMPLE1[9:0] = 11,
62 cycles are required for hold phase: THOLD1[9:0] = 62,
and 4 cycles are required for refresh period: TREFRESH1[7:0] = 4.
In this example, the power consumption is reduced by almost a factor of 15 versus Normal
modes.
The formulas to compute the right sample and refresh timings are described in the table
below, the Hold time depends on the leakage current.
Table 80. Sample and refresh timings
Buffer
State
tSAMP(1)(2)
tREFRESH(2)(3)
Enable
7 μs + (10*RBON*CSH)
7 μs + (RBON*CSH)*ln(2*NLSB)
Disable
3 μs + (10*RBOFF*CSH)
3 μs + (RBOFF*CSH)*ln(2*NLSB)
1. In the above formula the settling to the desired code value with ½ LSB or accuracy requires 10 constant
time for 12 bits resolution. For 8 bits resolution, the settling time is 7 constant time.
2. CSH is the capacitor in Sample and hold mode.
3. The tolerated voltage drop during the hold phase “Vd” is represented by the number of LSBs after the
capacitor discharging with the output leakage current. The settling back to the desired value with ½ LSB
error accuracy requires ln(2*Nlsb) constant time of the DAC.
Example of the sample and refresh time calculation with output buffer on
The values used in the example below are provided as indication only. Refer to the product
datasheet for product data.
CSH = 100 nF
VDD = 3.0 V
Sampling phase:
tSAMP = 7 μs + (10 * 2000 * 100 * 10-9) = 2.007 ms
(where RBON = 2 kΩ)
Refresh phase:
tREFRESH = 7 μs + (2000 * 100 * 10-9) * ln(2*10) = 606.1 μs
(where NLSB = 10 (10 LSB drop during the hold phase)
Hold phase:
Dv = ileak * thold / CSH = 0.0073 V (10 LSB of 12bit at 3 V)
ileak = 150 nA (worst case on the IO leakage on all the temperature range)
thold = 0.0073 * 100 * 10-9 / (150 * 10-9) = 4.867 ms
394/1325
RM0503 Rev 2
RM0503
Digital-to-analog converter (DAC)
Figure 65. DAC Sample and hold mode phase diagram
V1
Vd
V2
t
dac_hold
_ck
Sampling phase
Hold phase
Refresh
phase
Sampling phase
t
DAC
ON
ON
ON
MSv45340V3
Like in Normal mode, the Sample and hold mode has different configurations.
To enable the output buffer, MODE1[2:0] bits in DAC_MCR register must be set to:
•
100: DAC is connected to the external pin
•
101: DAC is connected to external pin and to on chip peripherals
To disabled the output buffer, MODE1[2:0] bits in DAC_MCR register must be set to:
•
110: DAC is connected to external pin and to on chip peripherals
•
111: DAC is connected to on chip peripherals
When MODE1[2:0] bits are equal to 111, an internal capacitor, CLint, holds the voltage
output of the DAC core and then drive it to on-chip peripherals.
All Sample and hold phases are interruptible, and any change in DAC_DHR1 immediately
triggers a new sample phase.
Table 81. Channel output modes summary
MODE1[2:0]
0
0
0
0
0
1
0
1
0
0
1
1
Mode
Buffer
Output connections
Connected to external pin
Enabled
Normal mode
Disabled
Connected to external pin and to on chip-peripherals (such as
comparators)
Connected to external pin
Connected to on chip peripherals (such as comparators)
RM0503 Rev 2
395/1325
409
Digital-to-analog converter (DAC)
RM0503
Table 81. Channel output modes summary (continued)
MODE1[2:0]
1
0
0
1
0
1
1
1
0
1
1
1
15.4.12
Mode
Buffer
Output connections
Connected to external pin
Enabled
Sample and
hold mode
Disabled
Connected to external pin and to on chip peripherals (such as
comparators)
Connected to external pin and to on chip peripherals (such as
comparators)
Connected to on chip peripherals (such as comparators)
DAC channel buffer calibration
The transfer function for an N-bit digital-to-analog converter (DAC) is:
V
= ( ( D ⁄ 2N ) × G × V ) + V
out
ref
OS
Where VOUT is the analog output, D is the digital input, G is the gain, Vref is the nominal fullscale voltage, and VOS is the offset voltage. For an ideal DAC channel, G = 1 and VOS = 0.
Due to output buffer characteristics, the voltage offset may differ from part-to-part and
introduce an absolute offset error on the analog output. To compensate the VOS, a
calibration is required by a trimming technique.
The calibration is only valid when the DAC channel is operating with buffer enabled
(MODE1[2:0] = 0b000 or 0b001 or 0b100 or 0b101). if applied in other modes when the
buffer is off, it has no effect. During the calibration:
•
The buffer output is disconnected from the pin internal/external connections and put in
tristate mode (HiZ).
•
The buffer acts as a comparator to sense the middle-code value 0x800 and compare it
to VREF+/2 signal through an internal bridge, then toggle its output signal to 0 or 1
depending on the comparison result (CAL_FLAG1 bit).
Two calibration techniques are provided:
•
Factory trimming (default setting)
The DAC buffer offset is factory trimmed. The default value of OTRIM1[4:0] bits in
DAC_CCR register is the factory trimming value and it is loaded once DAC digital
interface is reset.
•
User trimming
The user trimming can be done when the operating conditions differs from nominal
factory trimming conditions and in particular when VDDA voltage, temperature, VREF+
values change and can be done at any point during application by software.
Note:
Refer to the datasheet for more details of the nominal factory trimming conditions
In addition, when VDD is removed (example the device enters in Standby or VBAT modes)
the calibration is required.
The steps to perform a user trimming calibration are as below:
396/1325
RM0503 Rev 2
RM0503
Digital-to-analog converter (DAC)
1.
If the DAC channel is active, write 0 to EN1 bit in DAC_CR to disable the channel.
2.
Select a mode where the buffer is enabled, by writing to DAC_MCR register,
MODE1[2:0] = 0b000 or 0b001 or 0b100 or 0b101.
3.
Start the DAC channel calibration, by setting the CEN1 bit in DAC_CR register to 1.
4.
Apply a trimming algorithm:
a)
Write a code into OTRIM1[4:0] bits, starting by 0b00000.
b)
Wait for tTRIM delay.
c)
Check if CAL_FLAG1 bit in DAC_SR is set to 1.
d)
If CAL_FLAG1 is set to 1, the OTRIM1[4:0] trimming code is found and can be
used during device operation to compensate the output value, else increment
OTRIM1[4:0] and repeat sub-steps from (a) to (d) again.
The software algorithm may use either a successive approximation or dichotomy techniques
to compute and set the content of OTRIM1[4:0] bits in a faster way.
The commutation/toggle of CAL_FLAG1 bit indicates that the offset is correctly
compensated and the corresponding trim code must be kept in the OTRIM1[4:0] bits in
DAC_CCR register.
Note:
A tTRIM delay must be respected between the write to the OTRIM1[4:0] bits and the read of
the CAL_FLAG1 bit in DAC_SR register in order to get a correct value.This parameter is
specified into datasheet electrical characteristics section.
If VDDA, VREF+ and temperature conditions do not change during device operation while it
enters more often in Standby and VBAT modes, the software may store the OTRIM1[4:0]
bits found in the first user calibration in the flash or in back-up registers. then to load/write
them directly when the device power is back again thus avoiding to wait for a new calibration
time.
When CEN1 bit is set, it is not allowed to set EN1 bit.
15.4.13
DAC channel conversion modes
Four conversion modes are possible.
Independent trigger without wave generation
To configure the DAC in this conversion mode, the following sequence is required:
1.
Set the DAC channel trigger enable bit, TEN1.
2.
Configure the trigger sources by setting different values in the TSEL1[3:0] bits.
3.
Load the DAC channel data into the desired DHR registers (DAC_DHR12R1,
DAC_DHR12L1 or DAC_DHR8R1).
When a DAC channel trigger arrives, the DHR1 register is transferred into DAC_DOR1
(three dac_pclk clock cycles later).
RM0503 Rev 2
397/1325
409
Digital-to-analog converter (DAC)
RM0503
Independent trigger with single LFSR generation
To configure the DAC in this conversion mode, the following sequence is required:
1.
Set the DAC channel trigger enable bit, TEN1.
2.
Configure the trigger sources by setting different values in the TSEL1[3:0] bits.
3.
Configure the DAC channel WAVE1[1:0] bits as 01 and the same LFSR mask value in
the MAMP1[3:0] bits.
4.
Load the DAC channel data into the desired DHR register (DAC_DHR12R1,
DAC_DHR12L1 or DAC_DHR8R1).
When a DAC channel trigger arrives, the LFSR1 counter, with the same mask, is added to
the DHR1 register and the sum is transferred into DAC_DOR1 (three dac_pclk clock cycles
later). Then the LFSR1 counter is updated.
Independent trigger with single triangle generation
To configure the DAC in this conversion mode, the following sequence is required:
1.
Set the DAC channel trigger enable bits, TEN1.
2.
Configure the trigger sources by setting different values in the TSEL1[3:0] bits.
3.
Configure the DAC channel WAVE1[1:0] bits as 1x and the same maximum amplitude
value in the MAMP1[3:0] bits.
4.
Load the DAC channel data into the desired DHR register (DAC_DHR12R1,
DAC_DHR12L1 or DAC_DHR8R1).
When a DAC channel trigger arrives, the DAC channel triangle counter, with the same
triangle amplitude, is added to the DHR1 register and the sum is transferred into
DAC_DOR1 (three dac_pclk clock cycles later). The DAC channel triangle counter is then
updated.
Independent trigger with single sawtooth generation
To configure the DAC in this conversion mode, the following sequence is required:
1.
Configure the trigger sources by setting different values in STRSTTRIGSEL1[3:0] and
STINCTRIGSEL1[3:0] bits.
2.
Configure the DAC channel WAVE1[1:0] bits to 11 and set the same
STRSTDATA1[11:0], STINCDATA1[15:0] and STDIR1 values for each register.
When a DAC channel trigger arrives, the DAC channel sawtooth counter updates the DHR1
register and transfers it into DAC_DOR1 (three APB clock cycles later).
15.5
DAC in low-power modes
Table 82. Effect of low-power modes on DAC
Mode
398/1325
Description
Sleep
No effect, DAC used with DMA
Stop 0 / Stop 1
The DAC remains active with a static value if the Sample and hold mode is
selected using LSI clock.
RM0503 Rev 2
RM0503
Digital-to-analog converter (DAC)
Table 82. Effect of low-power modes on DAC (continued)
Mode
Description
The DAC registers content is lost and must be reinitialized after exiting
Stop 2. The DAC must be disabled before entering Stop 2.
Stop 2
Standby
The DAC peripheral is powered down and must be reinitialized after exiting
Standby or Shutdown mode.
Shutdown
15.6
DAC interrupts
Table 83. DAC interrupts
Interrupt
acronym
Interrupt
event
Event flag
Enable
Interrupt clear
control bit
method
DAC
DMA
underrun
DMAUDR1
DMAUDRI
E1
Write
DMAUDRx = 1
RM0503 Rev 2
Exit Sleep
mode
Exit Stop
mode
Exit Standby
mode
Yes
No
No
399/1325
409
Digital-to-analog converter (DAC)
15.7
RM0503
DAC registers
Refer to Section 1 on page 51 for a list of abbreviations used in register descriptions.
The peripheral registers have to be accessed by words (32-bit).
15.7.1
DAC control register (DAC_CR)
Address offset: 0x00
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CEN1
DMAU
DRIE1
DMAE
N1
TEN1
EN1
rw
rw
rw
rw
rw
Res.
MAMP1[3:0]
rw
rw
rw
WAVE1[1:0]
rw
rw
rw
TSEL1[3] TSEL1[2] TSEL1[1] TSEL1[0]
rw
rw
rw
rw
Bit 31 Reserved, must be kept at reset value.
Bits 30:16 Reserved, must be kept at reset value.
Bit 15 Reserved, must be kept at reset value.
Bit 14 CEN1: DAC channel1 calibration enable
This bit is set and cleared by software to enable/disable DAC channel1 calibration, it can be
written only if bit EN1 = 0 into DAC_CR (the calibration mode can be entered/exit only when
the DAC channel is disabled) Otherwise, the write operation is ignored.
0: DAC channel1 in Normal operating mode
1: DAC channel1 in calibration mode
Bit 13 DMAUDRIE1: DAC channel1 DMA Underrun Interrupt enable
This bit is set and cleared by software.
0: DAC channel1 DMA Underrun Interrupt disabled
1: DAC channel1 DMA Underrun Interrupt enabled
Bit 12 DMAEN1: DAC channel1 DMA enable
This bit is set and cleared by software.
0: DAC channel1 DMA mode disabled
1: DAC channel1 DMA mode enabled
400/1325
RM0503 Rev 2
RM0503
Digital-to-analog converter (DAC)
Bits 11:8 MAMP1[3:0]: DAC channel1 mask/amplitude selector
These bits are written by software to select mask in wave generation mode or amplitude in
triangle generation mode.
0000: Unmask bit0 of LFSR/ triangle amplitude equal to 1
0001: Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3
0010: Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7
0011: Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15
0100: Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31
0101: Unmask bits[5:0] of LFSR/ triangle amplitude equal to 63
0110: Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127
0111: Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255
1000: Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511
1001: Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023
1010: Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047
≥ 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095
Bits 7:6 WAVE1[1:0]: DAC channel1 noise/triangle wave generation enable
These bits are set and cleared by software.
00: wave generation disabled
01: Noise wave generation enabled
1x: Triangle wave generation enabled
Only used if bit TEN1 = 1 (DAC channel1 trigger enabled).
Bits 5:2 TSEL1[3:0]: DAC channel1 trigger selection
These bits select the external event used to trigger DAC channel1
0000: SWTRIG1
0001: dac_ch1_trg1
0010: dac_ch1_trg2
...
1111: dac_ch1_trg15
Refer to the trigger selection tables in Section 15.4.2: DAC pins and internal signals for
details on trigger configuration and mapping.
Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled).
Bit 1 TEN1: DAC channel1 trigger enable
This bit is set and cleared by software to enable/disable DAC channel1 trigger.
0: DAC channel1 trigger disabled and data written into the DAC_DHR1 register are
transferred one dac_pclk clock cycle later to the DAC_DOR1 register
1: DAC channel1 trigger enabled and data from the DAC_DHR1 register are transferred
three dac_pclk clock cycles later to the DAC_DOR1 register
Note: When software trigger is selected, the transfer from the DAC_DHR1 register to the
DAC_DOR1 register takes only one dac_pclk clock cycle.
Bit 0 EN1: DAC channel1 enable
This bit is set and cleared by software to enable/disable DAC channel1.
0: DAC channel1 disabled
1: DAC channel1 enabled
RM0503 Rev 2
401/1325
409
Digital-to-analog converter (DAC)
15.7.2
RM0503
DAC software trigger register (DAC_SWTRGR)
Address offset: 0x04
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
SWTRIG1
w
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 Reserved, must be kept at reset value.
Bit 0 SWTRIG1: DAC channel1 software trigger
This bit is set by software to trigger the DAC in software trigger mode.
0: No trigger
1: Trigger
Note: This bit is cleared by hardware (one dac_pclk clock cycle later) once the DAC_DHR1
register value has been loaded into the DAC_DOR1 register.
15.7.3
DAC channel1 12-bit right-aligned data holding register
(DAC_DHR12R1)
Address offset: 0x08
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
15
14
13
12
Res.
Res.
Res.
Res.
DACC1DHR[11:0]
rw
rw
rw
rw
rw
rw
rw
Bits 31:12 Reserved, must be kept at reset value.
Bits 11:0 DACC1DHR[11:0]: DAC channel1 12-bit right-aligned data
These bits are written by software. They specify 12-bit data for DAC channel1.
402/1325
RM0503 Rev 2
RM0503
Digital-to-analog converter (DAC)
15.7.4
DAC channel1 12-bit left aligned data holding register
(DAC_DHR12L1)
Address offset: 0x0C
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
DACC1DHR[11:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
3
2
1
0
Res.
Res.
Res.
Res.
rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:4 DACC1DHR[11:0]: DAC channel1 12-bit left-aligned data
These bits are written by software.
They specify 12-bit data for DAC channel1.
Bits 3:0 Reserved, must be kept at reset value.
15.7.5
DAC channel1 8-bit right aligned data holding register
(DAC_DHR8R1)
Address offset: 0x10
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
7
6
5
4
3
2
1
0
rw
rw
rw
15
14
13
12
11
10
9
8
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DACC1DHR[7:0]
rw
rw
rw
rw
rw
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 DACC1DHR[7:0]: DAC channel1 8-bit right-aligned data
These bits are written by software. They specify 8-bit data for DAC channel1.
RM0503 Rev 2
403/1325
409
Digital-to-analog converter (DAC)
15.7.6
RM0503
DAC channel1 data output register (DAC_DOR1)
Address offset: 0x2C
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
r
r
r
r
r
r
r
r
r
r
DACC1DOR[11:0]
r
r
Bits 31:12 Reserved, must be kept at reset value.
Bits 11:0 DACC1DOR[11:0]: DAC channel1 data output
These bits are read-only, they contain data output for DAC channel1.
15.7.7
DAC status register (DAC_SR)
Address offset: 0x34
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BWST1
CAL_
FLAG1
DMAU
DR1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
r
r
rc_w1
Bits 31:16 Reserved, must be kept at reset value.
Bit 15 BWST1: DAC channel1 busy writing sample time flag
This bit is systematically set just after Sample and hold mode enable and is set each time the
software writes the register DAC_SHSR1, It is cleared by hardware when the write operation of
DAC_SHSR1 is complete. (It takes about 3 LSI periods of synchronization).
0:There is no write operation of DAC_SHSR1 ongoing: DAC_SHSR1 can be written
1:There is a write operation of DAC_SHSR1 ongoing: DAC_SHSR1 cannot be written
Bit 14 CAL_FLAG1: DAC channel1 calibration offset status
This bit is set and cleared by hardware
0: calibration trimming value is lower than the offset correction value
1: calibration trimming value is equal or greater than the offset correction value
Bit 13 DMAUDR1: DAC channel1 DMA underrun flag
This bit is set by hardware and cleared by software (by writing it to 1).
0: No DMA underrun error condition occurred for DAC channel1
1: DMA underrun error condition occurred for DAC channel1 (the currently selected trigger is
driving DAC channel1 conversion at a frequency higher than the DMA service capability rate)
404/1325
RM0503 Rev 2
RM0503
Digital-to-analog converter (DAC)
Bit 12 Reserved, must be kept at reset value.
Bit 11 Reserved, must be kept at reset value.
Bits 10:0 Reserved, must be kept at reset value.
15.7.8
DAC calibration control register (DAC_CCR)
Address offset: 0x38
Reset value: 0x0000 00XX
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
4
3
2
1
0
rw
rw
15
14
13
12
11
10
9
8
7
6
5
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
OTRIM1[4:0]
rw
rw
rw
Bits 31:5 Reserved, must be kept at reset value.
Bits 4:0 OTRIM1[4:0]: DAC channel1 offset trimming value
15.7.9
DAC mode control register (DAC_MCR)
Address offset: 0x3C
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
MODE1[2:0]
rw
rw
rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:10 Reserved, must be kept at reset value.
Bit 9 Reserved, must be kept at reset value.
RM0503 Rev 2
405/1325
409
Digital-to-analog converter (DAC)
RM0503
Bit 8 Reserved, must be kept at reset value.
Bits 7:3 Reserved, must be kept at reset value.
Bits 2:0 MODE1[2:0]: DAC channel1 mode
These bits can be written only when the DAC is disabled and not in the calibration mode
(when bit EN1 = 0 and bit CEN1 = 0 in the DAC_CR register). If EN1 = 1 or CEN1 = 1 the
write operation is ignored.
They can be set and cleared by software to select the DAC channel1 mode:
– DAC channel1 in Normal mode
000: DAC channel1 is connected to external pin with Buffer enabled
001: DAC channel1 is connected to external pin and to on chip peripherals with Buffer
enabled
010: DAC channel1 is connected to external pin with Buffer disabled
011: DAC channel1 is connected to on chip peripherals with Buffer disabled
– DAC channel1 in sample & hold mode
100: DAC channel1 is connected to external pin with Buffer enabled
101: DAC channel1 is connected to external pin and to on chip peripherals with Buffer
enabled
110: DAC channel1 is connected to external pin and to on chip peripherals with Buffer
disabled
111: DAC channel1 is connected to on chip peripherals with Buffer disabled
Note: This register can be modified only when EN1 = 0.
15.7.10
DAC channel1 sample and hold sample time register
(DAC_SHSR1)
Address offset: 0x40
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
rw
rw
rw
rw
rw
rw
rw
rw
TSAMPLE1[9:0]
rw
rw
Bits 31:10 Reserved, must be kept at reset value.
Bits 9:0 TSAMPLE1[9:0]: DAC channel1 sample time (only valid in Sample and hold mode)
These bits can be written when the DAC channel1 is disabled or also during normal operation.
in the latter case, the write can be done only when BWST1 of DAC_SR register is low, If
BWST1 = 1, the write operation is ignored.
Note:
406/1325
It represents the number of LSI clocks to perform a sample phase. Sampling time =
(TSAMPLE1[9:0] + 1) x LSI clock period.
RM0503 Rev 2
RM0503
Digital-to-analog converter (DAC)
15.7.11
DAC sample and hold time register (DAC_SHHR)
Address offset: 0x48
Reset value: 0x0001 0001
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
rw
rw
rw
rw
rw
rw
rw
rw
THOLD1[9:0]
rw
rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:10 Reserved, must be kept at reset value.
Bits 9:0 THOLD1[9:0]: DAC channel1 hold time (only valid in Sample and hold mode)
Hold time = (THOLD[9:0]) x LSI clock period
Note: This register can be modified only when EN1 = 0.
Note:
These bits can be written only when the DAC channel is disabled and in Normal operating
mode (when bit EN1 = 0 and bit CEN1 = 0 in the DAC_CR register). If EN1 = 1 or CEN1 = 1
the write operation is ignored.
15.7.12
DAC sample and hold refresh time register (DAC_SHRR)
Address offset: 0x4C
Reset value: 0x0001 0001
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
7
6
5
4
3
2
1
0
rw
rw
rw
15
14
13
12
11
10
9
8
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
TREFRESH1[7:0]
rw
rw
rw
rw
rw
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 TREFRESH1[7:0]: DAC channel1 refresh time (only valid in Sample and hold mode)
Refresh time = (TREFRESH[7:0]) x LSI clock period
Note: This register can be modified only when EN1 = 0.
Note:
These bits can be written only when the DAC channel is disabled and in Normal operating
mode (when bit EN1 = 0 and bit CEN1 = 0 in the DAC_CR register). If EN1 = 1 or CEN1 = 1
the write operation is ignored.
RM0503 Rev 2
407/1325
409
DAC_MCR
0x3C
408/1325
Reset
value
RM0503 Rev 2
Res.
Res.
Res.
OTRIM1[0]
Reset
value
OTRIM1[1]
0
OTRIM1[2]
0
Res.
0
0
OTRIM1[3]
0
X
X
X
X
X
Res.
Reset
value
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
0
Res.
0
Res.
0
OTRIM1[4]
0
0
0
0
MODE1
[2:0]
Res.
0
Res.
Res.
Res.
0
0
Res.
Res.
Res.
0
0
Res.
Res.
Res.
0
0
Res
Res.
Res.
Reset
value
0
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset
value
es.
0
Res.
DACC1DHR[11:0]
0
0
0
0
0
0
0
DACC1DHR[7:0]
0
DACC1DOR[11:0]
Res.
0
0
Res.
0
Res.
0
Res.
Res.
Res.
Reserved
Res.
0x20 0x28
Res.
Res.
Res.
DMAUDR1
0
Res.
Reserved
Res.
0x14 0x1C
Res.
BWST1
CAL_FLAG1
0
Res.
Reset
value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
29
28
Res.
Res.
Res.
Res.
30
Res.
2
1
0
TSEL1[0]
TEN1
EN1
0
0
0
0
0
0
Res.
Res.
Res.
Res.
Res.
Res.
SWTRIG1
5
6
7
8
9
10
TSEL1[3:1]
4
3
WAVE1[1:0]
MAMP1[3:0]
0
11
0
Res.
12
DMAEN1
0
Res.
13
DMAUDRIE1
0
Res.
14
CEN1
0
Res.
15
Res.
0
Res.
16
Res.
0
Res.
17
Res.
0
Res.
18
Res.
19
20
21
22
23
24
25
26
27
31
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset
value
Res.
Res.
Res.
Reserved
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset
value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DAC_CR
Res.
DAC_CCR
Res.
Register
name
reset value
Res.
0x38
Res.
DAC_SR
Res.
0x34
Res.
0x2C
DAC_
DOR1
Res.
0x10
DAC_
DHR8R1
Res.
0x30
DAC_
DHR12L1
Res.
0x0C
DAC_
DHR12R1
Res.
0x08
DAC_
SWTRGR
Res.
0x04
Res.
0x00
Res.
Offset
Res.
15.7.13
Res.
Digital-to-analog converter (DAC)
RM0503
DAC register map
Table 84 summarizes the DAC registers.
Table 84. DAC register map and reset values
Reset
value
0
DACC1DHR[11:0]
0
0
0
0
0
0
0
0
Res.
0
0
0
RM0503
Digital-to-analog converter (DAC)
21
20
19
18
17
16
15
14
13
12
11
10
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
22
Res.
1
23
Res.
2
24
Res.
3
25
Res.
4
26
Res.
5
27
Res.
6
28
Res.
7
29
Res.
8
30
Res.
0
Res.
0
0
0
0
0
0
0
0
1
0
1
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
THOLD1[9:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset
value
DAC_
SHRR
9
31
Res.
DAC_
SHHR
0
Res.
Res.
0x4C
Reserved
0
TSAMPLE1[9:0]
0
Res.
0x48
Reset
value
Res.
0x44
DAC_
SHSR1
Res.
0x40
Register
name
reset value
Res.
Offset
Res.
Table 84. DAC register map and reset values (continued)
Reset
value
0
Reserved
Res.
0x580x60
Reserved
Res.
0x640x68
Reserved
Res.
0
0
0
TREFRESH1[7:0]
0
0x500x54
0
0
0
0
0
0
Refer to Section 2.2 on page 55 for the register boundary addresses.
RM0503 Rev 2
409/1325
409
Voltage reference buffer (VREFBUF)
16
RM0503
Voltage reference buffer (VREFBUF)
This section applies to STM32U073xx and STM32U083xx devices only.
16.1
Introduction
The devices embed a voltage reference buffer which can be used as voltage reference for
ADC and also as voltage reference for external components through the VREF+ pin.
16.2
VREFBUF functional description
The internal voltage reference buffer supports two voltages(a), which are configured with
VRS bits in the VREFBUF_CSR register:
The internal voltage reference can be configured in four different modes depending on
ENVR and HIZ bits configuration. These modes are provided in the table below:
Table 85. VREF buffer modes
ENVR
HIZ
0
0
VREFBUF buffer off mode:
– VREF+ pin pulled-down to VSSA
0
1
External voltage reference mode (default value):
– VREFBUF buffer off
– VREF+ pin input mode
1
0
Internal voltage reference mode:
– VREFBUF buffer on
– VREF+ pin connected to VREFBUF buffer output
1
Hold mode:
– VREF is enable without output buffer, VREF+ pin voltage is hold with the
external capacitor
– VRR detection disabled and VRR bit keeps last state
1
VREF buffer configuration
After enabling the VREFBUF by setting ENVR bit and clearing HIZ bit in the VREFBUF_CSR register,
the user must wait until VRR bit is set, meaning that the voltage reference output has reached its
expected value.
a. The minimum VDDA voltage depends on VRS setting, refer to the product datasheet.
410/1325
RM0503 Rev 2
RM0503
Voltage reference buffer (VREFBUF)
16.3
VREFBUF registers
16.3.1
VREFBUF control and status register (VREFBUF_CSR)
Address offset: 0x00
Reset value: 0x0000 0002
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
VRR
VRS
HIZ
ENVR
r
rw
rw
rw
Bits 31:4 Reserved, must be kept at reset value.
Bit 3 VRR: Voltage reference buffer ready
0: the voltage reference buffer output is not ready.
1: the voltage reference buffer output reached the requested level.
Bit 2 VRS: Voltage reference scale
This bit selects the value generated by the voltage reference buffer.
0: Voltage reference set to VREF_OUT1 (around 2.048 V).
1: Voltage reference set to VREF_OUT2 (around 2.5 V).
Bit 1 HIZ: High impedance mode
This bit controls the analog switch to connect or not the VREF+ pin.
0: VREF+ pin is internally connected to the voltage reference buffer output.
1: VREF+ pin is high impedance.
Refer to Table 85: VREF buffer modes for the mode descriptions depending on ENVR bit
configuration.
Bit 0 ENVR: Voltage reference buffer mode enable
This bit is used to enable the voltage reference buffer mode.
0: Internal voltage reference mode disable (external voltage reference mode).
1: Internal voltage reference mode (reference buffer enable or hold mode) enable.
16.3.2
VREFBUF calibration control register (VREFBUF_CCR)
Address offset: 0x04
Reset value: 0x0000 00XX
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
rw
rw
rw
rw
rw
TRIM[5:0]
rw
Bits 31:6 Reserved, must be kept at reset value.
RM0503 Rev 2
411/1325
412
Voltage reference buffer (VREFBUF)
16.3.3
RM0503
VREFBUF register map
The following table gives the VREFBUF register map and the reset values.
Reset value
RM0503 Rev 2
Res.
Res.
Res.
Res.
Res.
Res.
VRS
HIZ
ENVR
Res.
0
0
1
0
TRIM[5:0]
x
Refer to Section 2.2 for the register boundary addresses.
412/1325
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
VREFBUF_CCR
Res.
0x04
Res.
Reset value
VRR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
VREFBUF_CSR
Res.
0x00
Res.
Offset Register name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 86. VREFBUF register map and reset values
x
x
x
x
x
RM0503
Comparator (COMP)
17
Comparator (COMP)
17.1
Introduction
The devices embed up to two ultra-low-power comparators, COMP1 and COMP2.
The comparators can be used for a variety of functions including:
17.2
•
Wakeup from low-power mode triggered by an analog signal,
•
Analog signal conditioning,
•
Cycle-by-cycle current control loop when combined with a PWM output from a timer.
COMP main features
•
Each comparator has configurable plus and minus inputs used for flexible voltage
selection:
–
Multiplexed I/O pins
–
DAC Channel1
–
Internal reference voltage and three submultiple values (1/4, 1/2, 3/4) provided by
scaler (buffered voltage divider)
•
Programmable hysteresis
•
Programmable speed / consumption
•
The outputs can be redirected to an I/O or to timer inputs for triggering:
–
Break events for fast PWM shutdowns
•
Comparator outputs with blanking source
•
The two comparators can be combined in a window comparator
•
Each comparator has interrupt generation capability with wakeup from Sleep and Stop
modes (through the EXTI controller)
RM0503 Rev 2
413/1325
424
Comparator (COMP)
RM0503
17.3
COMP functional description
17.3.1
COMP block diagram
The block diagram of the comparators is shown in Figure 66.
32-bit APB bus
Figure 66. Comparator block diagram
comp_pclk
COMPx_INPy
compy_inp
COMPx
INPSEL
COMPx WINMODE
compx
_inp
+
COMPx
compx_inm
COMPx
COMPx
POLARITY
INMSEL
COMPx_INMy
DAC_CH1
VREFINT
3/4 VREFINT
1/2 VREFINT
1/4 VREFINT
COMPx_ OUT
GPIO alternate
function
COMPx
VALUE
compx_out
Blank source
COMPy VALUE
COMPx
WINOUT
Wakeup
EXTI line
interrupt
TIMERs
MSv71273V1
17.3.2
COMP pins and internal signals
The I/Os used as comparators inputs must be configured in analog mode in the GPIOs
registers.
The comparator output can be connected to the I/Os using the alternate function channel
given in “Alternate function mapping” table in the datasheet. The output can also be
internally redirected to a variety of timer input for the following purposes:
•
Emergency shut-down of PWM signals, using BKIN and BKIN2 inputs
•
Cycle-by-cycle current control, using OCREF_CLR inputs
•
Input capture for timing measures
It is possible to have the comparator output simultaneously redirected internally and
externally.
Table 87. COMP internal input/output signals
414/1325
Signal name
Signal type
Description
compx_inm
Analog input
Inverting input source for COMPx
compy_inp
Analog input
Noninverting input for COMPy
comp_pclk
Digital input
APB clock for both COMP channels
compx_out
Digital output
COMPx output
RM0503 Rev 2
RM0503
Comparator (COMP)
Table 88. COMP1 noninverting input assignment
COMP1_INP
COMP1 INPSEL[2:0](1)
COMP1_INP1
000
COMP1_INP2
001
COMP1_INP3
010
COMP1_INP4
011
COMP1_INP5
100
Not connected
101
1. Other combinations are reserved.
Table 89. COMP1 inverting input assignment
COMP1_INM
COMP1 INMSEL[3:0](1)
¼ VREFINT
0000
½ VREFINT
0001
¾ VREFINT
0010
VREFINT
0011
DAC Channel1
0100
COMP1_INM1
0101
COMP1_INM2
0110
COMP1_INM3
0111
COMP1_INM4
1000
COMP1_INM5
1001
1. Other combinations are reserved.
Table 90. COMP2 noninverting input assignment
COMP2_INP
COMP2 INPSEL[1:0]
COMP2_INP1
00
COMP2_INP2
01
COMP2_INP3
10
COMP2_INP4
11
Table 91. COMP2 inverting input assignment
COMP2_INM
COMP2 INMSEL[3:0](1)
¼ VREFINT
0000
½ VREFINT
0001
¾ VREFINT
0010
VREFINT
0011
RM0503 Rev 2
415/1325
424
Comparator (COMP)
RM0503
Table 91. COMP2 inverting input assignment (continued)
COMP2_INM
COMP2 INMSEL[3:0](1)
DAC Channel1
0100
COMP2_INM1
0101
COMP2_INM2
0110
COMP2_INM3
0111
COMP2_INM4
1000
COMP2_INM5
1001
1. Other combinations are reserved.
17.3.3
COMP reset and clocks
The COMP clock provided by the clock controller is synchronous with the APB clock.
There is no clock enable control bit provided in the RCC controller. Reset and clock enable
bits are common for COMP and SYSCFG.
Important: The polarity selection logic and the output redirection to the port works
independently from the APB clock. This allows the comparator to work even in Stop mode.
17.3.4
Comparator LOCK mechanism
The comparators can be used for safety purposes, such as over-current or thermal
protection. For applications having specific functional safety requirements, it is necessary to
insure that the comparator programming cannot be altered in case of spurious register
access or program counter corruption.
For this purpose, the comparator control and status registers can be write-protected (readonly).
Once the programming is completed, the COMPx LOCK bit can be set to 1. This causes the
whole register to become read-only, including the COMPx LOCK bit.
The write protection can only be reset by a MCU reset.
17.3.5
Window comparator
The purpose of window comparator is to monitor the analog voltage if it is within specified
voltage range defined by lower and upper threshold.
COMP1 and COMP2 can combine to create a window comparator. The monitored analog
voltage is connected to the noninverting (plus) inputs of comparators connected together
and the upper and lower threshold voltages are connected to the inverting (minus) inputs of
the comparators. Two noninverting inputs can be connected internally together by enabling
WINMODE bit to save one IO for other purposes.
416/1325
RM0503 Rev 2
RM0503
Comparator (COMP)
Figure 67. Window mode
COMPx WINMODE = 0
COMPx WINOUT = 1
COMPx_INP
Input
+
Upper threshold
COMPx_VALUE
COMPx
COMPx_INM
COMPx_OUT
-
COMPy WINMODE = 1
COMPy_INP
COMPy WINOUT = 0
+
Lower threshold
COMPy
COMPy_INM
COMPy_VALUE
COMPy_OUT
MSv42191V1
17.3.6
Hysteresis
The comparator includes a programmable hysteresis to avoid spurious output transitions in
case of noisy signals. The hysteresis can be disabled if it is not needed (for instance when
exiting from low-power mode) to be able to force the hysteresis value using external
components.
Figure 68. Comparator hysteresis
INP
INM
INM - Vhyst
COMP_OUT
MS19984V1
17.3.7
Comparator output blanking function
The purpose of the blanking function is to prevent the current regulation to trip upon short
current spikes at the beginning of the PWM period (typically the recovery current in power
switches anti parallel diodes).It consists of a selection of a blanking window which is a timer
output compare signal. The selection is done by software (refer to the comparator register
description for possible blanking signals). Then, the complementary of the blanking signal is
ANDed with the comparator output to provide the wanted comparator output. See the
example provided in the figure below.
RM0503 Rev 2
417/1325
424
Comparator (COMP)
RM0503
Figure 69. Comparator output blanking
PWM
Current limit
Current
Raw comp output
Blanking window
Final comp output
Comp out
Comp out (to TIM_BK …)
Blank
MS30964V1
17.3.8
COMP power and speed modes
COMPx power consumption versus propagation delay can be adjusted to have the optimum
trade-off for a given application.
The PWRMODE[1:0] bitfileds of the COMPx_CSR registers allow setting the comparators to
high speed with full power or medium speed with medium power. Refer to Section 17.6:
COMP registers.
17.4
COMP low-power modes
Table 92. Comparator behavior in the low-power modes
Mode
Sleep
Low-power run
Description
No effect on the comparators.
Comparator interrupts cause the device to exit the Sleep mode.
No effect.
Low-power sleep No effect. COMP interrupts cause the device to exit the Low-power sleep mode.
Stop 0
Stop 1
418/1325
No effect on the comparators.
Comparator interrupts cause the device to exit the Stop mode.
RM0503 Rev 2
RM0503
Comparator (COMP)
Table 92. Comparator behavior in the low-power modes (continued)
Mode
Standby
Shutdown
17.5
Description
The COMP registers are powered down and must be reinitialized after exiting
Standby or Shutdown mode.
COMP interrupts
The comparator outputs are internally connected to the Extended interrupts and events
controller. Each comparator has its own EXTI line and can generate either interrupts or
events. The same mechanism is used to exit from low-power modes.
Refer to Interrupt and events section for more details.
To enable COMPx interrupt, it is required to follow this sequence:
1.
Configure and enable the EXTI line corresponding to the COMPx output event in
interrupt mode and select the rising, falling or both edges sensitivity
2.
Configure and enable the NVIC IRQ channel mapped to the corresponding EXTI lines
3.
Enable COMPx.
Table 93. Interrupt control bits
Interrupt event
Enable
control bit
Exit from
Sleep mode
Exit from
Stop modes
Exit from
Standby mode
COMP1 output
Through EXTI
Yes
Yes
N/A
COMP2 output
Through EXTI
Yes
Yes
N/A
RM0503 Rev 2
419/1325
424
Comparator (COMP)
RM0503
17.6
COMP registers
17.6.1
Comparator 1 control and status register (COMP1_CSR)
Address offset: 0x00
Reset value: 0x0000 0000
31
30
29
28
27
26
25
LOCK
VALUE
Res.
Res.
Res.
Res.
Res.
13
12
11
10
9
Res.
Res.
WINMODE
rs
r
15
14
POLARITY WINOUT
rw
rw
rw
24
23
rw
21
20
19
18
17
PWRMODE[1:0]
16
HYST[1:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
EN
rw
rw
INPSEL[2:0]
rw
22
BLANKSEL[4:0]
INMSEL[3:0]
rw
rw
rw
rw
Bit 31 LOCK: COMP1_CSR register lock
This bit is set by software and cleared by a system reset. It locks the comparator 3 control
bits. When locked, all register bits are read-only.
0: Not locked
1: Locked
Bit 30 VALUE: Comparator 1 output status
This bit is read-only. It reflects the level of the comparator 1 output after the polarity selector
and blanking, as indicated in Figure 66.
Bits 29:25 Reserved, must be kept at reset value.
Bits 24:20 BLANKSEL[4:0]: Comparator 1 blanking source selector
This bitfield is controlled by software (if not locked). It selects the blanking source:
00000: No blanking
00001: TIM1 OC4 enabled as blanking source
00010: TIM1 OC5 enabled as blanking source
00100: TIM2 OC3 enabled as blanking source
01000: TIM3 OC3 enabled as blanking source
10000: TIM15 OC2 enabled as blanking source
Others: Reserved, must not be used
Bits 19:18 PWRMODE[1:0]: Comparator 1 power mode selector
This bitfield is controlled by software (if not locked). It selects the power consumption and as
a consequence the speed of the comparator 1:
00: High speed/high power
01-10: Medium speed/medium power
11: Low speed/low power
Bits 17:16 HYST[1:0]: Comparator 1 hysteresis selector
This bitfield is controlled by software (if not locked). It selects the hysteresis of the
comparator 1:
00: No hysteresis
01: Low hysteresis
10: Medium hysteresis
11: High hysteresis
420/1325
RM0503 Rev 2
RM0503
Comparator (COMP)
Bit 15 POLARITY: Comparator 1 polarity selector
This bit is controlled by software (if not locked). It selects the comparator 1 output polarity:
0: Non-inverted
1: Inverted
Bit 14 WINOUT: Comparator 1 output selector
This bit is controlled by software (if not locked). It selects the comparator 1 output:
0: COMP1_VALUE
1: COMP1_VALUE XOR COMP2_VALUE (required for window mode, see Figure 67)
Bits 13:12 Reserved, must be kept at reset value.
Bit 11 WINMODE: Comparator 1 noninverting input selector for window mode
This bit is controlled by software (if not locked). It selects the signal for COMP1_INP input of
the comparator 1:
0: Signal selected with INPSEL[2:0] bitfield of this register
1: COMP2_INP signal of the comparator 2 (required for window mode, see Figure 67)
Bits 10:8 INPSEL[2:0]: Comparator 1 signal selector for noninverting input
This bitfield is controlled by software (if not locked). It selects the signal for the noninverting
input COMP1_INP of the comparator 1 (also see the WINMODE bit):
Refer to Table 88: COMP1 noninverting input assignment.
Bits 7:4 INMSEL[3:0]: Comparator 1 signal selector for inverting input INM
This bitfield is controlled by software (if not locked). It selects the signal for the inverting
input COMP1_INM of the comparator 1:
Refer to Table 89: COMP1 inverting input assignment.
Bits 3:1 Reserved, must be kept at reset value.
Bit 0 EN: Comparator 1 enable bit
This bit is controlled by software (if not locked). It enables the comparator 1:
0: Disable
1: Enable
17.6.2
Comparator 2 control and status register (COMP2_CSR)
Address offset: 0x04
Reset value: 0x0000 0000
31
30
29
28
27
26
25
LOCK
VALUE
Res.
Res.
Res.
Res.
Res.
rs
r
15
14
POLARITY WINOUT
rw
rw
24
23
rw
rw
rw
rw
rw
rw
rw
rw
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
EN
12
11
10
9
Res.
Res.
WINMODE
Res.
INPSEL[1:0]
rw
21
20
BLANKSEL[4:0]
13
rw
22
rw
RM0503 Rev 2
rw
18
PWRMODE[1:0]
INMSEL[3:0]
rw
19
rw
rw
17
16
HYST[1:0]
rw
rw
421/1325
424
Comparator (COMP)
RM0503
Bit 31 LOCK: COMP2_CSR register lock
This bit is set by software and cleared by a system reset. It locks the comparator 3 control
bits. When locked, all register bits are read-only.
0: Not locked
1: Locked
Bit 30 VALUE: Comparator 2 output status
This bit is read-only. It reflects the level of the comparator 2 output after the polarity selector
and blanking, as indicated in Figure 66.
Bits 29:25 Reserved, must be kept at reset value.
Bits 24:20 BLANKSEL[4:0]: Comparator 2 blanking source selector
This bitfield is controlled by software (if not locked). It selects the blanking source:
00000: No blanking
00001: TIM1 OC4 enabled as blanking source
00010: TIM1 OC5 enabled as blanking source
00100: TIM2 OC3 enabled as blanking source
01000: TIM3 OC3 enabled as blanking source
10000: TIM15 OC2 enabled as blanking source
Others: Reserved, must not be used
Bits 19:18 PWRMODE[1:0]: Comparator 2 power mode selector
This bitfield is controlled by software (if not locked). It selects the power consumption and as
a consequence the speed of the comparator 2:
00: High speed/high power
01-10: Medium speed/medium power
11: Low speed/low power
Bits 17:16 HYST[1:0]: Comparator 2 hysteresis selector
This bitfield is controlled by software (if not locked). It selects the hysteresis of the
comparator 2:
00: No hysteresis
01: Low hysteresis
10: Medium hysteresis
11: High hysteresis
Bit 15 POLARITY: Comparator 2 polarity selector
This bit is controlled by software (if not locked). It selects the comparator 2 output polarity:
0: Non-inverted
1: Inverted
Bit 14 WINOUT: Comparator 2 output selector
This bit is controlled by software (if not locked). It selects the comparator 2 output:
0: COMP2_VALUE
1: COMP1_VALUE XOR COMP2_VALUE (required for window mode, see Figure 67)
Bits 13:12 Reserved, must be kept at reset value.
Bit 11 WINMODE: Comparator 2 noninverting input selector for window mode
This bit is controlled by software (if not locked). It selects the signal for COMP2_INP input of
the comparator 2:
0: Signal selected with INPSEL[1:0] bitfield of this register
1: COMP1_INP signal of the comparator 1 (required for window mode, see Figure 67)
Bit 10 Reserved, must be kept at reset value.
422/1325
RM0503 Rev 2
RM0503
Comparator (COMP)
Bits 9:8 INPSEL[1:0]: Comparator 2 signal selector for noninverting input
This bitfield is controlled by software (if not locked). It selects the signal for the noninverting
input COMP2_INP of the comparator 2 (also see the WINMODE bit):
Refer to Table 90: COMP2 noninverting input assignment.
Bits 7:4 INMSEL[3:0]: Comparator 2 signal selector for inverting input INM
This bitfield is controlled by software (if not locked). It selects the signal for the inverting
input COMP2_INM of the comparator 2:
Refer to Table 91: COMP2 inverting input assignment.
Bits 3:1 Reserved, must be kept at reset value.
Bit 0 EN: Comparator 2 enable bit
This bit is controlled by software (if not locked). It enables the comparator 2:
0: Disable
1: Enable
RM0503 Rev 2
423/1325
424
Comparator (COMP)
17.6.3
RM0503
COMP register map
The following table summarizes the comparator registers.
The comparator registers share SYSCFG peripheral register base addresses.
0
0
0
0
0
0
0
0
0
0
Refer to Section 2.2 on page 55 for the register boundary addresses.
424/1325
RM0503 Rev 2
0
0
0
EN
Res.
Res.
Res.
0
0
EN
0
0
Res.
0
Res.
0
INMSEL[3:0]
INPSEL[2:0].
WINMODE
0
Res.
0
0
Res.
0
0
INMSEL[3:0]
0
0
INPSEL[1:0].
0
0
0
WINMODE
Res.
0
0
Res.
BLANKSEL[4:0]
0
WINOUT
Res.
0
WINOUT
Res.
0
POL
0
POL
0
0
HYST[1:0]
PWRMODE[1:0]
0
HYST[1:0]
BLANKSEL[4:0]
PWRMODE[1:0]
Res.
Res.
Res.
0
Res.
0
Res.
Reset value
Res.
COMP2_CSR
Res.
0
Res.
0
Res.
Reset value
Res.
LOCK
VALUE
0x04
COMP1_CSR
LOCK
0x00
Register
VALUE
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 94. COMP register map and reset values
0
RM0503
Operational amplifiers (OPAMP)
18
Operational amplifiers (OPAMP)
18.1
Introduction
The device embeds an operational amplifier with two inputs and one output. The three I/Os
can be connected to the external pins. This enables any type of external interconnections.
The operational amplifier can be configured internally as a follower or as an amplifier with a
noninverting gain ranging from 2 to 16.
The positive input can be connected to the internal DAC.
The output can be connected to the internal ADC.
18.2
OPAMP main features
•
18.3
Rail-to-rail input voltage range
•
Low input offset voltage (1.5 mV after calibration, 3 mV with factory calibration)
•
Low-power mode (current consumption reduced to 30 µA instead of 100 µA)
•
Fast wakeup time (10 µs in normal mode, 30 µs in low-power mode)
•
Gain bandwidth of 1.6 MHz
OPAMP functional description
The OPAMP has several modes.
When the OPAMP is disabled, the output is high-Z.
When it is enabled, it can be in calibration mode (where any OPAMP input and output is
disconnected), or in functional mode.
There are two functional modes: the low-power mode or the normal mode. In functional
mode, the OPAMP inputs and output of the OPAMP are connected as described in the
Section 18.3.3: Signal routing.
18.3.1
OPAMP reset and clocks
The operational amplifier clock is necessary for accessing the registers. The clock can be
switched off using the peripheral clock enable register when the application does not need
to have read or write access to those registers. See OPAMPEN bit in Section 5.4.15: APB
peripheral clock enable register 1 (RCC_APBENR1).
The bit OPAEN enables and disables the OPAMP operation. The OPAMP registers
configurations should be changed before enabling the OPAEN bit in order to avoid spurious
effects on the output.
When the output of the operational amplifier is no more needed, the operational amplifier
can be disabled to save power. All the configurations previously set (including the
calibration) are maintained while OPAMP is disabled.
RM0503 Rev 2
425/1325
435
Operational amplifiers (OPAMP)
18.3.2
RM0503
Initial configuration
The default configuration of the operational amplifier is a functional mode where the three
IOs are connected to external pins. In the default mode, the operational amplifier uses the
factory trimming values. See electrical characteristics section of the datasheet for factory
trimming conditions, usually the temperature is 30 °C and the voltage is 3 V. The trimming
values can be adjusted. See Section 18.3.5: Calibration for changing the trimming values.
The default configuration uses the normal mode, which provides the highest performance.
Bit OPALPM can be set in order to switch the operational amplifier to low-power mode and
reduced performance. Both normal and low-power mode characteristics are defined in the
section “electrical characteristics” of the datasheet. Before utilization, the bit OPA_RANGE
of OPAMP_CSR must be set to 1 if VDDA is above 2.4V, or kept at 0 otherwise.
As soon as the OPAEN bit in the OPAMP_CSR register is set, the operational amplifier is
functional. The two input pins and the output pin are connected as defined in Section 18.3.3:
Signal routing and the default connection settings can be changed.
Note:
The inputs and output pins must be configured in analog mode (default state) in the
corresponding GPIOx_MODER register.
18.3.3
Signal routing
The OPAMP_CSR register determines the routing for the operational amplifier pins.
The connections of the operational amplifier OPAMP1 are described in the table below.
Table 95. Operational amplifier possible connections
Signal
Pin
Internal
OPAMP1_VINM
PA1
OPAMP1_OUT
or PGA
controlled by bits OPAMODE
and VM_SEL.
OPAMP1_VINP
PA0
DAC1_OUT1
controlled by bit VP_SEL.
ADC1_IN8 (through
the GPIO)
The pin is connected when the
OPAMP is enabled. The ADC
input is controlled by ADC.
OPAMP1_VOUT PA3
18.3.4
comment
OPAMP modes
The operational amplifier inputs and outputs are all accessible on terminals. The amplifier
can be used in multiple configuration environments:
•
Standalone mode (external gain setting mode)
•
Follower configuration mode
•
PGA modes
Note:
The amplifier output pin is directly connected to the output pad to minimize the output
impedance. It cannot be used as a general purpose I/O, even if the amplifier is configured
as a PGA and only connected to the ADC channel.
Note:
The impedance of the signal must be maintained below a level that avoids the input leakage
to create significant artifacts (due to a resistive drop in the source). Please refer to the
electrical characteristics section in the datasheet for further details.
426/1325
RM0503 Rev 2
RM0503
Operational amplifiers (OPAMP)
Standalone mode (external gain setting mode)
The procedure to use the OPAMP in standalone mode is presented below.
Starting from the default value of OPAMP_CSR, and the default state of GPIOx_MODER,
configure bit OPA_RANGE according to the VDDA voltage. As soon as the OPAEN bit is set,
the two input pins and the output pin are connected to the operational amplifier.
This default configuration uses the factory trimming values and operates in normal mode
(highest performance). The behavior of the OPAMP can be changed as follows:
•
OPALPM can be set to “operational amplifier low-power” mode in order to save power.
•
USERTRIM can be set to modify the trimming values for the input offset.
Figure 70. Standalone mode: external gain setting mode
STM32
GPIO
DAC_OUT
+
ADC
GPIO
-
MS35324V1
Follower configuration mode
The procedure to use the OPAMP in follower mode is presented below.
•
Configure OPAMODE bits as “internal follower”.
•
Configure VP_SEL bits as “GPIO connected to VINP”.
•
As soon as the OPAEN bit is set, the signal on pin OPAMP_VINP is copied to pin
OPAMP_VOUT.
Note:
The pin corresponding to OPAMP_VINM is free for another usage.
Note:
The signal on the operational amplifier output is also seen as an ADC input. As a
consequence, the OPAMP configured in follower mode can be used to perform impedance
adaptation on input signals before feeding them to the ADC input, assuming the input signal
frequency is compatible with the operational amplifier gain bandwidth specification.
RM0503 Rev 2
427/1325
435
Operational amplifiers (OPAMP)
RM0503
Figure 71. Follower configuration
STM32
GPIO
DAC_OUT
+
ADC
GPIO
-
Always connected to
OPAMP output (can be
used during debug)
MS35325V1
428/1325
RM0503 Rev 2
RM0503
Operational amplifiers (OPAMP)
Programmable Gain Amplifier mode
The procedure to use the OPAMP to amplify the amplitude of an input signal is
presented below.
•
Configure OPAMODE bits as “internal PGA enabled”.
•
Configure PGA_GAIN bits as “internal PGA Gain 2, 4, 8 or 16”.
•
Configure VM_SEL bits as “inverting not externally connected”.
•
Configure VP_SEL bits as “GPIO connected to VINP”.
As soon as the OPAEN bit is set, the selected gain amplifies the signal on the
OPAMP_VINP pin. This is visible on the OPAMP_VOUT pin.
Note:
To avoid saturation, the input voltage should stay below VDDA divided by the selected gain.
Figure 72. PGA mode, internal gain setting (x2/x4/x8/x16), inverting input not used
STM32
GPIO
DAC_OUT
+
ADC
GPIO
-
Always connected to
OPAMP output (can be
used during debug)
MS35326V1
RM0503 Rev 2
429/1325
435
Operational amplifiers (OPAMP)
RM0503
Programmable Gain Amplifier mode with external filtering
The procedure to use the OPAMP to amplify the amplitude of an input signal, with an
external filtering, is presented below.
•
Configure OPAMODE bits as “internal PGA enabled”.
•
Configure PGA_GAIN bits as “internal PGA Gain 2, 4, 8 or 16”.
•
Configure VM_SEL bits as “GPIO connected to VINM”.
•
Configure VP_SEL bits as “GPIO connected to VINP”.
Any external connection on VINP can be used in parallel with the internal PGA, for
example a capacitor can be connected between VOUT and VINM for filtering purposes.
See datasheet for the value of resistors used in the PGA resistor network.
Figure 73. PGA mode, internal gain setting (x2/x4/x8/x16), inverting input used for
filtering
STM32
GPIO
DAC_OUT
+
ADC
GPIO
-
Allows optional
low-pass
filtering (1)
Equivalent to
MS35327V1
1. The gain depends on the cutoff frequency.
18.3.5
Calibration
At startup, the trimming values are initialized with the preset ‘factory’ trimming value.
The user can trim the operational amplifier offset. Specific registers allow different trimming
values for normal mode and for low-power mode.
The aim of the calibration is to cancel as much as possible the OPAMP inputs offset voltage.
The calibration circuitry reduces the inputs offset voltage to less than +/-1.5 mV within stable
voltage and temperature conditions.
For each mode of the operational amplifier, two trimming values need to be trimmed, one for
N differential pair and one for P differential pair.
There are two registers for trimming the operational amplifier offset, one for normal mode
(OPAMP_OTR) and one low-power mode (OPAMP_LPOTR). Each register is composed of
five bits for P differential pair trimming, and five bits for N differential pair trimming. These
are the ‘user’ values.
430/1325
RM0503 Rev 2
RM0503
Operational amplifiers (OPAMP)
Using the USERTRIM bit in the OPAMP_CSR register, the user can switch from ‘factory’
values to ‘user’ trimmed values. This bit is reset at startup. The ‘factory’ value is then
applied by default to the OPAMP trimming registers.
User is liable to change the trimming values in calibration or in functional mode.
The offset trimming registers are typically configured after the calibration operation is
initialized by setting bit CALON to 1. When CALON = 1 the inputs of the operational
amplifier are disconnected from the functional environment.
•
Setting CALSEL to 1 initializes the offset calibration for the P differential pair (low
voltage reference used).
•
Resetting CALSEL to 0 initializes the offset calibration for the N differential pair (high
voltage reference used).
When CALON = 1, the CALOUT bit reflects the influence of the trimming value selected by
CALSEL and OPALPM. When the value of CALOUT switches between two consecutive
trimming values, this means that those two values are the best trimming values. The
CALOUT flag needs up to 1 ms after the trimming value is changed to become steady (see
tOFFTRIMmax delay specification in the electrical characteristics section of the datasheet).
Note:
The closer the trimming value is to the optimum trimming value, the longer it takes to
stabilize. The maximum stabilization time remains below 1 ms in any case.
Table 96. Operating modes and calibration
Control bits
Output
Mode
OPAEN
OPALPM
CALON
CALSEL
VOUT
CALOUT
flag
Normal operating
mode
1
0
0
X
analog
0
Low-power mode
1
1
0
X
analog
0
Power down
0
X
X
X
Z
0
Offset cal high for
normal mode
1
0
1
0
analog
X
Offset cal low for
normal mode
1
0
1
1
analog
X
Offset cal high for
low-power mode
1
1
1
0
analog
X
Offset cal low for
low-power mode
1
1
1
1
analog
X
RM0503 Rev 2
431/1325
435
Operational amplifiers (OPAMP)
RM0503
Calibration procedure
Here are the steps to perform full operational amplifier calibration:
1.
Select correct OPA_RANGE in OPAMP_CSR, then set the OPAEN bit in OPAMP_CSR
to 1 to enable the operational amplifier.
2.
Set the USERTRIM bit in the OPAMP_CSR register to 1.
3.
Choose a calibration mode (refer to Table 96: Operating modes and calibration). The
steps 3 to 4 must be repeated four times. For the first iteration, select :
–
Normal mode, offset cal high (N differential pair)
The above calibration mode corresponds to OPALPM=0 and CALSEL=0 in the
OPAMP_CSR register.
4.
Increment TRIMOFFSETN[4:0] in OPAMP_OTR, starting from 00000b and until
CALOUT changes to 1 in OPAMP_CSR.
Note:
CALOUT switches from 0 to 1 for offset cal high and from 1 to 0 for offset cal low.
Note:
Between the write to the OPAMP_OTR register and the read of the CALOUT value, make
sure to wait for the tOFFTRIMmax delay specified in the electrical characteristics section of
the datasheet, to get the correct CALOUT value.
The commutation means that the offset is correctly compensated and that the
corresponding trim code must be saved in the OPAMP_OTR register.
Repeat steps 3 to 4 for:
–
Normal_mode and offset cal low
–
Low power mode and offset cal high
–
Low power mode and offset cal low
If a mode is not in use, you do not need to perform the corresponding calibration.
Note:
During the whole calibration phase the external connection of the operational amplifier
output must not pull up or down currents higher than 500 µA.
During the calibration procedure, it is necessary to set up OPAMODE bits as 00 or 01 (PGA
disable) or 11 (internal follower).
18.4
OPAMP low-power modes
Table 97. Effect of low-power modes on the OPAMP
Mode
Sleep
No effect.
Stop 0 / Stop 1
No effect, OPAMP registers content is kept.
Stop 2
OPAMP registers content is kept. OPAMP must be disabled before entering
Stop 2 mode.
Standby
Shutdown
432/1325
Description
The OPAMP registers are powered down and must be re-initialized after
exiting Standby or Shutdown mode.
RM0503 Rev 2
RM0503
Operational amplifiers (OPAMP)
18.5
OPAMP registers
18.5.1
OPAMP1 control/status register (OPAMP1_CSR)
Address offset: 0x00
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
OPA_
RANGE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
12
11
10
9
8
7
6
5
4
3
2
Res.
VP_
SEL
VM_SEL[9:8]
rw
rw
rw
15
14
13
CAL
OUT
USER
TRIM
CAL
SEL
CALON
r
rw
rw
rw
Res.
Res.
rw
PGA_GAIN[5:4]
rw
rw
OPAMODE[3:2]
rw
w
1
0
OPA
LPM
OPAEN
rw
rw
Bit 31 OPA_RANGE: Operational amplifier power supply range for stability
All AOP must be in power down to allow AOP-RANGE bit write. It applies to all AOP
embedded in the product.
0: Low range (VDDA < 2.4V)
1: High range (VDDA > 2.4V)
Bits 30:16 Reserved, must be kept at reset value.
Bit 15 CALOUT: Operational amplifier calibration output
During calibration mode offset is trimmed when this signal toggle.
Bit 14 USERTRIM: allows to switch from ‘factory’ AOP offset trimmed values to AOP offset ‘user’
trimmed values
This bit is active for both mode normal and low-power.
0: ‘factory’ trim code used
1: ‘user’ trim code used
Bit 13 CALSEL: Calibration selection
0: NMOS calibration (200mV applied on OPAMP inputs)
1: PMOS calibration (VDDA-200mV applied on OPAMP inputs)
Bit 12 CALON: Calibration mode enabled
0: Normal mode
1: Calibration mode (all switches opened by HW)
Bit 11 Reserved, must be kept at reset value.
Bit 10 VP_SEL: Non inverted input selection
0: GPIO connected to VINP
1: DAC connected to VINP
Bits 9:8 VM_SEL[9:8]: Inverting input selection
These bits are used only when OPAMODE = 00, 01 or 10.
00: GPIO connected to VINM (valid also in PGA mode for filtering)
01: Reserved
1x: Inverting input not externally connected. These configurations are valid only when
OPAMODE = 10 (PGA mode)
Bits 7:6 Reserved, must be kept at reset value.
RM0503 Rev 2
433/1325
435
Operational amplifiers (OPAMP)
RM0503
Bits 5:4 PGA_GAIN[5:4]: Operational amplifier Programmable amplifier gain value
00: internal PGA Gain 2
01: internal PGA Gain 4
10: internal PGA Gain 8
11: internal PGA Gain 16
Bits 3:2 OPAMODE[3:2]: Operational amplifier PGA mode
00: internal PGA disable
01: internal PGA disable
10: internal PGA enable, gain programmed in PGA_GAIN
11: internal follower
Bit 1 OPALPM: Operational amplifier Low Power Mode
The operational amplifier must be disable to change this configuration.
0: operational amplifier in normal mode
1: operational amplifier in low-power mode
Bit 0 OPAEN: Operational amplifier Enable
0: operational amplifier disabled
1: operational amplifier enabled
18.5.2
OPAMP1 offset trimming register in normal mode (OPAMP1_OTR)
Address offset: 0x04
Reset value: 0x0000 XXXX (factory trimmed values)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
12
11
10
9
8
4
3
2
1
0
15
14
13
Res.
Res.
Res.
TRIMOFFSETP[12:8]
rw
rw
rw
rw
7
6
5
Res.
Res.
Res.
rw
TRIMOFFSETN[4:0]
rw
Bits 31:13 Reserved, must be kept at reset value.
Bits 12:8 TRIMOFFSETP[12:8]: Trim for PMOS differential pairs
Bits 7:5 Reserved, must be kept at reset value.
Bits 4:0 TRIMOFFSETN[4:0]: Trim for NMOS differential pairs
18.5.3
OPAMP1 offset trimming register in low-power mode
(OPAMP1_LPOTR)
Address offset: 0x08
Reset value: 0x0000 XXXX (factory trimmed values)
434/1325
RM0503 Rev 2
rw
rw
rw
rw
RM0503
Operational amplifiers (OPAMP)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
12
11
10
9
8
4
3
2
1
0
15
14
13
Res.
Res.
Res.
TRIMLPOFFSETP[12:8]
rw
rw
rw
rw
7
6
5
Res.
Res.
Res.
TRIMLPOFFSETN[4:0]
rw
rw
rw
rw
rw
rw
Bits 31:13 Reserved, must be kept at reset value.
Bits 12:8 TRIMLPOFFSETP[12:8]: Low-power mode trim for PMOS differential pairs
Bits 7:5 Reserved, must be kept at reset value.
Bits 4:0 TRIMLPOFFSETN[4:0]: Low-power mode trim for NMOS differential pairs
18.5.4
OPAMP register map
TRIM
OFFSETP[4:0]
0
OPAEN
0
OPALPM
OPAMODE
PGA_GAIN
Res.
0
0
0
0
0
Res.
Res.
0
Res.
0
Res.
VM_SEL
CALON
Res.
CALSEL
0
VP_SEL
USERTRIM
0
Res.
0
Res.
Res.
CALOUT
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
OPA_RANGE
OPAMP1_OTR
Res.
0
TRIM
OFFSETN[4:0]
(1)
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
TRIMLP
OFFSETN[4:0]
Res.
TRIMLP
OFFSETP[4:0]
Res.
OPAMP1_
LPOTR
Res.
(1)
Res.
(1)
Res.
Reset value
Res.
0x08
Reset value
Res.
0x04
OPAMP1_CSR
Res.
0x00
Register
Res.
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 98. OPAMP register map and reset values
(1)
1. Factory trimmed values.
Refer to Section 2.2 on page 55 for the register boundary addresses.
RM0503 Rev 2
435/1325
435
Liquid crystal display controller (LCD)
19
RM0503
Liquid crystal display controller (LCD)
This section applies to STM32U083xx and STM32U073xx devices only.
19.1
LCD introduction
The LCD controller is a digital controller/driver for monochrome passive liquid crystal display
(LCD) with up to eight common terminals, and up to 52 segment terminals to drive 208
(4x52) or 384 (8x48) LCD picture elements (pixels). The exact number of terminals depends
on the device pinout as described in the datasheet.
The LCD is made up of several segments (pixels or complete symbols) that can be turned
visible or invisible. Each segment consists of a layer of liquid crystal molecules aligned
between two electrodes. When a voltage greater than a threshold voltage is applied across
the liquid crystal, the segment becomes visible. The segment voltage must be alternated
to avoid an electrophoresis effect in the liquid crystal (which degrades the display).
The waveform across a segment must then be generated, so to avoid having a direct
current (DC).
Glossary
Bias: number of voltage levels used when driving an LCD
It is defined as 1 / (number of voltage levels used to drive an LCD display - 1).
Boost circuit: contrast controller circuit
Common: electrical connection terminal connected to several segments (52 segments)
Duty ratio: number defined as 1 / (number of common terminals on a given LCD display)
Frame: one period of the waveform written to a segment
Frame rate: number of frames per second (number of times the LCD segments are
energized per second)
LCD (liquid crystal display): passive display panel with terminals leading directly
to a segment
Segment: smallest viewing element (a single bar or dot that is used to help create
a character on an LCD display)
19.2
LCD main features
•
Highly flexible frame rate control
•
Static, 1/2, 1/3, 1/4, and 1/8 duty supported
•
Static, 1/2, 1/3, and 1/4 bias supported
•
Double-buffered memory allowing data in LCD_RAM registers to be updated at any
time by the application firmware without affecting the integrity of the data displayed
–
•
436/1325
LCD data RAM of up to 16 x 32-bit registers which contain pixel information
(active/inactive)
Software selectable LCD output voltage (contrast) from VLCDmin to VLCDmax
RM0503 Rev 2
RM0503
Liquid crystal display controller (LCD)
•
•
–
stepup converter embedded to generate an internal VLCD voltage higher than VDD
–
software selection between external and internal VLCD voltage source. In case of
an external source, the internal boost circuit is disabled to reduce power
consumption.
–
resistive network embedded to generate intermediate VLCD voltages
–
structure of the resistive network configurable by software to adapt the power
consumption to match the capacitive charge required by the LCD panel
–
Integrated voltage output buffers for higher LCD driving capability.
Contrast that can be adjusted using two different methods:
–
When using the internal step-up converter, the software can adjust VLCD between
VLCDmin and VLCDmax.
–
Programmable dead time (up to eight phase periods) between frames
•
Full support of low-power modes: The LCD controller can be displayed in Sleep,
Low-power run, Low-power sleep, and Stop modes, or can be fully disabled to reduce
power consumption.
•
Built-in phase inversion for reduced power consumption and EMI (electromagnetic
interference)
•
Start-of-frame interrupt to synchronize the software when updating the LCD data RAM
•
Blink capability:
•
Note:
No need for external analog components:
–
Up to 1, 2, 3, 4, 8, or all pixels which can be programmed to blink at a configurable
frequency
–
Software adjustable blink frequency to achieve around 0.5 Hz, 1 Hz, 2 Hz, or 4 Hz
Used LCD segment and common pins must be configured as GPIO alternate functions,
and unused segment and common pins can be used for GPIO or for another peripheral
alternate function.
When the LCD relies on the internal stepup converter, the VLCD pin must be connected
to VSS with a capacitor. Its typical value is 1 µF (see CEXT value in the datasheet for details).
RM0503 Rev 2
437/1325
461
Liquid crystal display controller (LCD)
RM0503
19.3
LCD functional description
19.3.1
General description
The LCD controller has five main blocks (see Figure 74):
Figure 74. LCD controller block diagram
Frequency generator
LCDCLK
16-bit prescaler
LCDCLK
LCD
regs
PS[3:0]
LCDCLK/32768
COM0
Clock mux
ck_ps
DIV[3:0]
COM3
Divide by 16 to 31
Interrupt
SEG0
ck_div
COM[3:0]
COM[7:4]
SEG[51:0]
SEG[47:0]
Analog
switch
Analog
arrray
52
48
switch
array
SEG
driver
SEG [31:28]
(32x16 bits)
SEG47
SEG [51:48]
LCD
RAM
8-to-1 mux
Data bus
Address bus
COM
driver
SEG48/
COM4
READY
STATIC
LCD
regs
SEG
COM
MUX
VSEL
SEG49/
COM5
SEG[51:48]
EN
Pulse
generator
Voltage
generator
HD
2/3 -3/4VLCD
BIAS[1:0]
Contrast
controller
CC[2:0]
Analog stepup
converter
Note:
SEG50/
COM6
VSS
1/3-1/4 VLCD
SEG51/
COM7
1/2 VLCD
VLCD
I/O ports
MSv33071V2
LCDCLK is the same as RTCCLK. Refer to the RTC/LCD clock description in the RCC
section of the reference manual.
The frequency generator allows the user to achieve various LCD frame rates starting from
an LCD input clock frequency (LCDCLK) which can vary from 32 kHz up to 1 MHz.
Three different clock sources can be used to provide the LCD clock (LCDCLK/RTCCLK):
438/1325
•
32 kHz low-speed external RC (LSE)
•
32 kHz low-speed internal RC (LSI)
RM0503 Rev 2
RM0503
19.3.2
Liquid crystal display controller (LCD)
Frequency generator
This clock source must be stable in order to obtain accurate LCD timing, and hence
to minimize DC voltage offset across LCD segments. The input clock LCDCLK can be
divided by any value from 1 to 215x 31 (see Section 19.6.2). The frequency generator
consists of a prescaler (16-bit ripple counter), and a 16 to 31 clock divider.
PS[3:0] in LCD_FCR selects LCDCLK divided by 2PS[3:0]. If a finer resolution rate is
required, DIV[3:0] in LCD_FCR can be used to divide the clock further by 16 to 31.
In this way, the user can roughly scale the frequency, and then fine-tune it by linearly scaling
the clock with the counter. The output of the frequency generator block is fck_div, which
constitutes the time base for the entire LCD controller. The ck_div frequency is equivalent to
the LCD phase frequency, rather than the frame frequency (they are equal only in case of
static duty). The frame frequency (fframe) is obtained from fck_div by dividing it by the number
of active common terminals (or by multiplying it for the duty). Thus the relation between the
input clock frequency (fLCDCLK) of the frequency generator and its output clock frequency
fck_div is:
f LCDCLK
f ckdiv = --------------------------------------------PS
2 × ( 16 + DIV )
f frame = f ckdiv × duty
This makes the frequency generator very flexible. An example of frame rate calculation is
shown in the table below.
Table 99. Example of frame rate calculation
LCDCLK
PS[3:0]
DIV[3:0]
Ratio
Duty
fframe
32.768 kHz
3
1
136
1/8
30.12 Hz
32.768 kHz
4
1
272
1/4
30.12 Hz
32.768 kHz
4
6
352
1/3
31.03 Hz
32.768 kHz
5
1
544
1/2
30.12 Hz
32.768 kHz
6
1
1088
static
30.12 Hz
32.768 kHz
1
4
40
1/8
102.40 Hz
32.768 kHz
2
4
80
1/4
102.40 Hz
32.768 kHz
2
11
108
1/3
101.14 Hz
32.768 kHz
3
4
160
1/2
102.40 Hz
32.768 kHz
4
4
320
static
102.40 Hz
1.00 MHz
6
3
1216
1/8
102.80 Hz
1.00 MHz
7
3
2432
1/4
102.80 Hz
1.00 MHz
7
10
3328
1/3
100.16 Hz
1.00 MHz
8
3
4864
1/2
102.80 Hz
1.00 MHz
9
3
9728
static
102.80 Hz
RM0503 Rev 2
439/1325
461
Liquid crystal display controller (LCD)
RM0503
The frame frequency must be selected to be within a range of around ~30 Hz to ~100 Hz.
It is a compromise between power consumption and the acceptable refresh rate. In addition,
a dedicated blink prescaler selects the blink frequency. This frequency is defined as:
fBLINK = fck_div/2(BLINKF + 3),
with BLINKF[2:0] = 0, 1, 2, ... ,7
The blink frequency achieved is in the range of 0.5 Hz, 1 Hz, 2 Hz, or 4 Hz.
19.3.3
Common driver
Common signals are generated by the common driver block (see Figure 74).
COM signal bias
Each COM signal has identical waveforms, but different phases. It has its max amplitude
VLCD or VSS only in the corresponding phase of a frame cycle, while during the other
phases, the signal amplitude is:
•
1/4 VLCD or 3/4 VLCD in case of 1/4 bias
•
1/3 VLCD or 2/3 VLCD in case of 1/3 bias
•
1/2 VLCD in case of 1/2 bias
The selection between 1/2, 1/3, and 1/4 bias mode can be done through BIAS[1:0]
in LCD_CR.
A pixel is activated when both of its corresponding common and segment lines are active
during the same phase: when the voltage difference between common and segment is
maximum during this phase. Common signals are phase inverted in order to reduce EMI.
As shown in the figure below, with phase inversion, there is a mean voltage of 1/2 VLCD at
the end of every odd cycle.
Figure 75. 1/3 bias, 1/4 duty
Segment
Common
Odd frame
Even frame
VLCD
2/3 VLCD
1/3 VLCD
VSS
Com active
Com inactive Com inactive Com inactive
Com active
Com inactive Com inactive Com inactive
Com active
Com active
Com inactive Com inactive
Com active
Com active
Com inactive Com inactive
Phase 0
Phase 1
Phase 2
Phase 0
Phase 1
Phase 2
VLCD
2/3 VLCD
1/3 VLCD
VSS
Phase 3
Phase 3
MS33438V2
In case of 1/2 bias (BIAS = 01), the VLCD pin generates an intermediate voltage equal
to 1/2 VLCD on node b for odd and even frames (see Figure 78).
440/1325
RM0503 Rev 2
RM0503
Liquid crystal display controller (LCD)
COM signal duty
Depending on DUTY[2:0] in LCD_CR, the COM signals are generated with static duty
(see Figure 77), 1/2 duty (see Figure 78), 1/3 duty (see Figure 79), 1/4 duty (see Figure 80),
or 1/8 duty (see Figure 81).
COM[n] n[0 to 7] is active during phase n in the odd frame, so the COM pin is driven
to VLCD.
During phase n of the even frame, the COM pin is driven to VSS.
In the case of 1/3 or 1/4) bias, COM[n] is inactive during phases other than n, so the COM
pin is driven to 1/3 (1/4) VLCD during odd frames, and to 2/3 (3/4) VLCD during even frames.
In the case of 1/2 bias, if COM[n] is inactive during phases other than n, the COM pin is
always driven (odd and even frame) to 1/2 VLCD.
When static duty is selected, the segment lines are not multiplexed, which means that each
segment output corresponds to one pixel. In this way, only up to 51 pixels can be driven.
COM[0] is always active while COM[7:1] are not used and are driven to VSS.
When LCDEN in LCD_CR is reset, all common lines are pulled down to VSS, and the ENS
flag in LCD_SR becomes 0. Static duty means that COM[0] is always active, and only two
voltage levels are used for segment and common lines: VLCD and VSS. A pixel is active
if the corresponding SEG line has a voltage opposite to that of the COM, and inactive when
the voltages are equal. In this way the LCD has maximum contrast (see Figure 76,
Figure 77).
In the figure below, pixel 0 is active while pixel 1 is inactive.
Figure 76. Static duty case 1
Even
Odd frame frame
COM0
VLCD
VSS
SEG0
VLCD
VSS
SEG1
VLCD
VSS
COM0
SEG0
VLCD
0
-VLCD
COM0
SEG1
VLCD
0
-VLCD
Odd frame
Even
frame
MS33439V1
In each frame, there is only one phase, this is why fframe is equal to fLCD. If 1/4 duty is
selected there are four phases in a frame in which COM[0] is active during phase 0, COM[1]
is active during phase 1, COM[2] is active during phase 2, and COM[3] is active
during phase 3.
RM0503 Rev 2
441/1325
461
Liquid crystal display controller (LCD)
RM0503
Figure 77. Static duty case 2
Liquid crystal display
and terminal connection
1/1 V
PIN
COM0
0/1V
1/1 V
PIN
SEG0
0/1V
COM0
1/1 V
SEG7
PIN
SEG1
0/1V
SEG6
1/1 V
SEG5
SEG3
SEG4
SEG2
SEG0
SEG1
COM0-SEG0
selected
waveform
0/1V
-1/1V
COM0-SEG1
non selected waveform
0/1V
MS33440V1
In this mode, the segment terminals are multiplexed, and each of them control four pixels.
A pixel is activated only when both of its corresponding SEG and COM lines are active
in the same phase. In case of 1/4 duty, to deactivate pixel 0 connected to COM[0], SEG[0]
needs to be inactive during the phase 0 when COM[0] is active. To activate pixel 0
connected to COM[1], SEG[0] needs to be active during phase 1 when COM[1] is active
(see Figure 80). To activate pixels from 0 to 51 connected to COM[0], SEG[0:51] needs to
be active during phase 0 when COM[0] is active. These considerations can be extended to
the other pixels.
Eight-to-one mux
When COM[0] is active the common driver block, it also drives the eight-to-one mux shown
in Figure 74 in order to select the content of first two RAM register locations. When COM[7]
is active, the output of the eight-to-one mux is the content of the last two RAM locations.
442/1325
RM0503 Rev 2
RM0503
Liquid crystal display controller (LCD)
Figure 78. 1/2 duty, 1/2 bias
Liquid crystal display
and terminal connection
PIN
COM0
2/2 V
1/2 V
0/2 V
COM1
PIN
COM1
2/2 V
1/2 V
0/2 V
COM0
PIN
SEG0
2/2 V
0/2 V
PIN
SEG1
2/2 V
0/2V
COM0-SEG0
selected waveform
2/2 V
1/2 V
0/2 V
-1/2 V
SEG3
SEG2
SEG1
SEG0
-2/2 V
COM0-SEG1
non selected waveform
1/2 V
0/2 V
-1/2 V
MS33441V1
19.3.4
Segment driver
The segment driver block controls the SEG lines according to the pixel data coming from
the eight-to-one mux driven in each phase by the common driver block.
In the case of 1/4 or 1/8 duty
When COM[0] is active, the pixel information (active/inactive) related to the pixel connected
to COM[0] (content of the first two LCD_RAM locations) goes through the eight-to-one mux.
The SEG[n] pin n [0 to 51] is driven to VSS (indicating pixel n is active when COM[0] is
active) in phase 0 of the odd frame.
The SEG[n] pin is driven to VLCD in phase 0 of the even frame. If pixel n is inactive then the
SEG[n] pin is driven to 2/3 (2/4) VLCD in the odd frame or 1/3 (2/4) VLCD in the even frame
(current inversion in VLCD pad) (see Figure 75).
In case of 1/2 bias, if the pixel is inactive the SEG[n] pin is driven to VLCD in the odd and to
VSS in the even frame.
When the LCD controller is disabled (LCDEN cleared in LCD_CR), then the SEG lines are
pulled down to VSS.
RM0503 Rev 2
443/1325
461
Liquid crystal display controller (LCD)
RM0503
Figure 79. 1/3 duty, 1/3 bias
3/3 V
PIN
COM0
2/3 V
1/3 V
Liquid crystal display
and terminal connection
0/3 V
3/3 V
PIN
COM1
2/3 V
1/3 V
COM2
COM1
0/3 V
3/3 V
PIN
COM2
2/3 V
1/3 V
0/3 V
COM0
3/3 V
PIN
SEG0
2/3 V
1/3 V
0/3 V
3/3 V
PIN
SEG1
2/3 V
1/3 V
0/3 V
3/3 V
SEG0
SEG1
2/3 V
SEG2
1/3 V
COM0-SEG1
selected waveform
0/3 V
-1/3 V
-2/3 V
-3/3 V
1/3 V
COM0-SEG0
non selected waveform
0/3 V
-1/3 V
1 frame
MS33442V1
444/1325
RM0503 Rev 2
RM0503
Liquid crystal display controller (LCD)
Figure 80. 1/4 duty, 1/3 bias
3/3 V
PIN
COM0
2/3 V
1/3 V
0/3 V
Liquid crystal display
and terminal connection
3/3 V
PIN
COM1
COM3
2/3 V
1/3 V
0/3 V
COM2
3/3 V
PIN
COM2
COM1
2/3 V
1/3 V
0/3 V
COM0
3/3 V
PIN
SEG0
2/3 V
1/3 V
0/3 V
3/3 V
PIN
SEG1
2/3 V
1/3 V
0/3 V
3/3 V
2/3 V
SEG0
SEG1
1/3 V
COM0-SEG1
selected waveform
0/3 V
-1/3 V
-2/3 V
-3/3 V
1/3 V
COM0-SEG0
non selected waveform
0/3 V
-1/3 V
1 frame
MS33443V1
RM0503 Rev 2
445/1325
461
Liquid crystal display controller (LCD)
RM0503
Figure 81. 1/8 duty, 1/4 bias
4/4 V
Liquid crystal display
and terminal connection
PIN
COM0
3/4 V
2/4 V
COM7
1/4 V
0/4 V
COM6
COM5
4/4 V
COM4
COM3
PIN
COM1
3/4 V
2/4 V
COM1
1/4 V
0/4 V
COM2
COM0
4/4 V
PIN
COM2
3/4 V
2/4 V
1/4 V
0/4 V
4/4 V
PIN
COM7
3/4 V
2/4 V
1/4 V
SEG0
0/4 V
4/4 V
PIN
SEG0
3/4 V
2/4 V
1/4 V
0/4 V
4/4 V
3/4 V
2/4 V
1/4 V
COM0-SEG0
selected waveform
0/4 V
-1/4 V
-2/4 V
-3/4 V
-4/4 V
4/4 V
3/4 V
2/4 V
1/4 V
COM2-SEG0
non selected waveform
0/4 V
-1/4 V
-2/4 V
-3/4 V
-4/4 V
1 frame
MS33444V1
446/1325
RM0503 Rev 2
RM0503
Liquid crystal display controller (LCD)
Blink
The segment driver also implements a programmable blink feature to allow some pixels to
continuously switch on at a specific frequency. The blink mode can be configured
by BLINK[1:0] in LCD_FCR, making possible to blink up to 1, 2, 4, 8, or all pixels
(see Section 19.6.2). The blink frequency can be selected from eight different values using
BLINKF[2:0] in LCD_FCR.
The table below gives examples of different blink frequencies (as a function of ck_div
frequency).
Table 100. Blink frequency
ck_div frequency (with LCDCLK frequency of 32.768 kHz)
BLINKF[2:0]
19.3.5
32 Hz
64 Hz
128 Hz
256 Hz
0
0
0
4.0 Hz
N/A
N/A
N/A
0
0
1
2.0 Hz
4.0 Hz
N/A
N/A
0
1
0
1.0 Hz
2.0 Hz
4.0 Hz
N/A
0
1
1
0.5 Hz
1.0 Hz
2.0 Hz
4.0 Hz
1
0
0
0.25 Hz
0.5 Hz
1.0 Hz
2.0 Hz
1
0
1
N/A
0.25 Hz
0.5 Hz
1.0 Hz
1
1
0
N/A
N/A
0.25 Hz
0.5 Hz
1
1
1
N/A
N/A
N/A
0.25 Hz
Voltage generator and contrast control
LCD supply source
The LCD power supply source comes from either the internal stepup converter, or from
an external voltage applied on the VLCD pin. The internal or external voltage source can be
selected using VSEL in LCD_CR. In case of external source selected, the internal boost
circuit (stepup converter) is disabled to reduce power consumption.
When the stepup converter is selected as VLCD source, the VLCD value can be chosen
among a wide set of values from VLCDmin to VLCDmax by means of CC[2:0] (contrast control)
in LCD_FCR (see Section 19.6.2). New values of VLCD takes effect every beginning of
a new frame.
When external power source is selected as VLCD source, the VLCD voltage must be chosen
in the range of VLCDmin to VLCDmax (see datasheets). The contrast can then be controlled by
programming a dead time between frames (see Deadtime).
LCD intermediate voltages
The LCD intermediate voltage levels are generated through an internal resistor divider
network as shown in Figure 82.
The LCD voltage generator issues intermediate voltage levels between VSS and VLCD:
•
1/3 VLCD and 2/3 VLCD in case of 1/3 bias
•
1/4 VLCD, 2/4 VLCD and 3/4 VLCD in case of 1/4 bias
RM0503 Rev 2
447/1325
461
Liquid crystal display controller (LCD)
•
RM0503
only 1/2 VLCD in case of 1/2 bias.
LCD drive selection
Two resistive networks, one with low-value resistors (RL), and one with high-value resistors
(RH) are respectively used to increase the current during transitions, and to reduce power
consumption in static state.
The EN switch follows the rules described below (see Figure 82):
•
If LCDEN is set in LCD_CR, the EN switch is closed.
•
When clearing LCDEN in LCD_CR, the EN switch is open at the end of the even frame
in order to avoid a medium voltage level different from 0 considering the entire frame
odd plus even.
PON[2:0] (pulse on duration) in LCD_FCR configures the time during which RL is
enabledthrough the HD (high drive) switch when the levels of the common and segment
lines change (see Figure 82). A short drive time leads to lower power consumption, but
displays with high internal resistance may need a longer drive time to achieve satisfactory
contrast.
Figure 82. LCD voltage control
HD
EN
VLCD
3 RL
3 RH
3/4 x VLCD
BUFEN
BUFEN
VLCDRail3
RL
BUFEN
RH
2/3 x VLCD
BUFEN
2 RL
BUFEN
2 RH
VLCDRail2
1/2 x VLCD
2 RL
BUFEN
2 RH
1/3 x VLCD
BUFEN
RH
RL
BUFEN
VLCDRail3
1/4 x VLCD
BUFEN
3 RL
3 RH
BIAS[1]
STATIC
VSS
MS33445V2
1. RLN and RHN are the low value resistance network and the high value resistance network, respectively.
The RLN divider can be always switched on using HD in LCD_FCR (see Section 19.6.2).
448/1325
RM0503 Rev 2
RM0503
Liquid crystal display controller (LCD)
The HD switch follows the rules described below:
•
If HD and PON[2:0] are reset in LCD_FCR, the HD switch is open.
•
If HD is reset in LCD_FCR, and PON[2:0] in LCD_FCR are different from 00, the HD
switch is closed during the number of pulses defined in PON[2:0].
•
If HD = 1 in LCD_FCR, then HD switch is always closed.
After LCDEN is activated, RDY is set in LCD_SR to indicate that voltage levels are stable
and the LCD controller can start to work.
Buffered mode
When voltage output buffers are enabled by setting BUFEN in LCD_CR, the LCD driving
capability is improved as buffers prevent the LCD capacitive loads from loading the resistor
bridge unacceptably and interfering with its voltage generation. As a result, intermediate
voltage levels are more stable, which improves RMS voltage applied to the LCD pixels.
In buffer mode, intermediate voltages are generated by the high value resistor bridge RHN to
reduce power consumption. The low value resistor bridge RLN is automatically disabled
whatever HD or PON[2:0] configuration.
Buffers can be used independently of the VLCD supply source (internal or external), but they
can only be enabled or disabled when the LCD controller is not activated.
Deadtime
In addition to using CC[2:0], the contrast can be controlled by programming a dead time
between each frame. During the dead time, the COM and SEG values are put to VSS.
DEAD[2:0] in LCD_FCR can be used to program a time of up to eight phase periods.
This dead time reduces the contrast without modifying the frame rate.
Figure 83. Deadtime
Odd frame
Even frame
Dead time
Odd frame
Even frame
MS33448V1
19.3.6
Double-buffer memory
Using its double-buffer memory, the LCD controller ensures the coherency of the displayed
information without having to use interrupts to control the LCD_RAM modification.
The application software can access the first buffer level (LCD_RAM) through the APB
interface. Once it has modified the LCD_RAM, it sets UDR in LCD_SR. This UDR flag
(update display request) requests the updated information to be moved into the second
buffer level (LCD_DISPLAY).
RM0503 Rev 2
449/1325
461
Liquid crystal display controller (LCD)
RM0503
This operation is done synchronously with the frame (at the beginning of the next frame).
Until the update is completed, the LCD_RAM is write protected, and the UDR flag stays
high. Once the update is completed, another flag (UDD, update display done) is set and
generates an interrupt if UDDIE is set in LCD_FCR.
The time it takes to update LCD_DISPLAY is, in the worst case, one odd and
one even frame.
The update does not occur (UDR = 1 and UDD = 0) until the display is enabled (LCDEN = 1)
19.3.7
COM and SEG multiplexing
Output pins versus duty modes
The output pins consists of:
•
SEG[51:0]
•
COM[3:0]
Depending on the duty configuration, the COM and SEG output pins can have different
functions:
450/1325
•
In static, 1/2, 1/3, and 1/4 duty modes, there are up to 52 SEG pins and respectively 1,
2, 3, and 4 COM pins
•
In 1/8 duty mode (DUTY[2:0] = 100), COM[7:4] outputs are available on SEG[51:48].
This allows reducing the number of available segments.
RM0503 Rev 2
RM0503
19.3.8
Liquid crystal display controller (LCD)
Flowchart
Figure 84. Flowchart example
START
INIT
- Enable the GPIO port clocks
- Configure the LCD GPIO pins as alternate functions
- Configure LCD controller according to the display to be driven
- Load the initial data to be displayed into
LCD_RAM and set the UDR in LCD_SR
- Program the desired frame rate (PS and DIV in LCD_FCR)
- Program the contrast (CC in LCD_FCR)
Enable the display (LCDEN in LCD_CR)
Adjust contrast?
Yes
Change PS, DIV, CC, PON,
DEAD, or HD in LCD_FCR
No
Yes
Modify data?
UDR = 1?
Yes
No
Modify the LCD_RAM
Set UDR in LCD_SR
No
Change blink?
Yes
Change BLINK or BLINKF
in LCD_FCR
No
Disable LCD?
Yes
Disable the display (LCDEN in LCD_CR)
No
ENS = 0?
Yes
END
MS33450V1
RM0503 Rev 2
451/1325
461
Liquid crystal display controller (LCD)
19.4
RM0503
LCD low-power modes
The LCD controller can be displayed in Stop mode, or can be fully disabled to reduce power
consumption.
19.5
LCD interrupts
The table below gives the list of LCD interrupt requests.
Table 101. LCD interrupt requests
Interrupt event
Event flag
Event flag
Interrupt clearing method
Interrupt enable
control bit
Start of frame (SOF)
SOF
Write SOFC = 1
SOFIE
Update display done (UDD)
UDD
Write UDDC = 1
UDDIE
Start of frame (SOF)
The LCD start of frame interrupt is executed if SOFIE (start of frame interrupt enable) is set
in LCD_FCR. SOF is cleared by writing SOFC to 1 in LCD_CLR when executing the
corresponding interrupt handling vector.
Update display done (UDD)
The LCD update display interrupt is executed if UDDIE (update display done interrupt
enable) is set in LCD_FCR. UDD is cleared by writing th UDDC to 1 in LCD_CLR when
executing the corresponding interrupt handling vector.
Depending on the product implementation, all these interrupts events can either share
the same interrupt vector (LCD global interrupt), or be grouped into two interrupt vectors
(LCD SOF interrupt and LCD UDD interrupt). Refer to the for details.
To enable the LCD interrupts, the following sequence is required:
452/1325
1.
Configure and enable the LCD IRQ channel in the NVIC.
2.
Configure the LCD to generate interrupts.
RM0503 Rev 2
RM0503
Liquid crystal display controller (LCD)
19.6
LCD registers
These registers are accessed by words (32-bit).
19.6.1
LCD control register (LCD_CR)
Address offset: 0x00
Reset value: 0x0000 0000
VSEL, MUX_SEG, BIAS, DUTY, and BUFEN bitfields are write-protected when the LCD is
enabled
(ENS =1 in LCD_SR).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
VSEL
LCDEN
rw
rw
Res.
Res.
Res.
Res.
Res.
Res.
Res.
MUX_S
BUFEN
EG
rw
rw
BIAS[1:0]
rw
rw
DUTY[2:0]
rw
rw
rw
Bits 31:9 Reserved, must be kept at reset value.
Bit 8 BUFEN: Voltage output buffer enable
This bit is used to enable/disable the voltage output buffer for higher driving capability.
0: Output buffer disabled
1: Output buffer enabled
Bit 7 MUX_SEG: Mux segment enable
This bit is used to enable SEG pin remapping. Four SEG pins can be multiplexed
with SEG[31:28]. See Section 19.3.7.
0: SEG pin multiplexing disabled
1: SEG[31:28] multiplexed with SEG[43:40]
Bits 6:5 BIAS[1:0]: Bias selector
These bits determine the bias used. Value 11 is forbidden.
00: Bias 1/4
01: Bias 1/2
10: Bias 1/3
11: Reserved
Bits 4:2 DUTY[2:0]: Duty selection
These bits determine the duty cycle. Values 101, 110 and 111 are forbidden.
000: Static duty
001: 1/2 duty
010: 1/3 duty
011: 1/4 duty
100: 1/8 duty
Others: Reserved
Bit 1 VSEL: Voltage source selection
This bit determines the voltage source for the LCD.
0: Internal source (voltage stepup converter)
1: External source (VLCD pin)
RM0503 Rev 2
453/1325
461
Liquid crystal display controller (LCD)
RM0503
Bit 0 LCDEN: LCD controller enable
This bit is set by software to enable the LCD controller/driver. It is cleared by software to turn
off the LCD at the beginning of the next frame. When the LCD is disabled, all COM and SEG
pins are driven to VSS.
0: LCD controller disabled
1: LCD controller enabled
19.6.2
LCD frame control register (LCD_FCR)
Address offset: 0x04
Reset value: 0x0000 0000
This register can be updated any time, but the new values are applied only at the beginning
of the next frame (except for UDDIE, SOFIE that affect the device behavior immediately).
The new value of CC[2:0] is also applied immediately, but its effect on the device is delayed
at the beginning of the next frame by the voltage generator.
Reading this register gives the last value written in the register, and not the configuration
used to display the current frame.
When BUFEN is set in LCD_CR, the low resistor divider network is automatically disabled
whatever HD or PON[2:0] configuration.
31
30
29
28
27
26
Res.
Res.
Res.
Res.
Res.
Res.
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
UDDIE
Res.
SOFIE
HD
rw
rw
rw
rw
rw
rw
rw
rw
BLINKF[2:0]
rw
rw
25
23
22
21
PS[3:0]
CC[2:0]
rw
24
19
18
17
DIV[3:0]
DEAD[2:0]
rw
20
PON[2:0]
rw
rw
16
BLINK[1:0]
rw
Bits 31:26 Reserved, must be kept at reset value.
Bits 25:22 PS[3:0]: PS 16-bit prescaler
These bits are written by software to define the division factor of the PS 16-bit prescaler.
ck_ps = LCDCLK/(2PS[3:0]). See Section 19.3.2.
0000: ck_ps = LCDCLK
0001: ck_ps = LCDCLK/2
0002: ck_ps = LCDCLK/4
...
1111: ck_ps = LCDCLK/32768
Bits 21:18 DIV[3:0]: DIV clock divider
These bits are written by software to define the division factor of the DIV divider
(see Section 19.3.2.)
0000: ck_div = ck_ps/16
0001: ck_div = ck_ps/17
0002: ck_div = ck_ps/18
...
1111: ck_div = ck_ps/31
454/1325
RM0503 Rev 2
RM0503
Liquid crystal display controller (LCD)
Bits 17:16 BLINK[1:0]: Blink mode selection
00: Blink disabled
01: Blink enabled on SEG[0], COM[0] (1 pixel)
10: Blink enabled on SEG[0], all COMs (up to 8 pixels depending on the programmed duty)
11: Blink enabled on all SEGs and all COMs (all pixels)
Bits 15:13 BLINKF[2:0]: Blink frequency selection
000: fLCD/8
001: fLCD/16
010: fLCD/32
011: fLCD/64
100: fLCD/128
101: fLCD/256
110: fLCD/512
111: fLCD/1024
Bits 12:10 CC[2:0]: Contrast control
These bits specify one of the VLCD maximum voltages (independent of VDD). It ranges
from 2.60 V to 3.51V.
000: VLCD0
001: VLCD1
010: VLCD2
011: VLCD3
100: VLCD4
101: VLCD5
110: VLCD6
111: VLCD7
Note: Refer to the datasheet for the VLCDx values.
Bits 9:7 DEAD[2:0]: Dead time duration
These bits are written by software to configure the length of the dead time between frames.
During the dead time the COM and SEG voltage levels are held at 0 V to reduce the contrast
without modifying the frame rate.
000: No dead time
001: 1 phase period dead time
010: 2 phase period dead time
......
111: 7 phase period dead time
RM0503 Rev 2
455/1325
461
Liquid crystal display controller (LCD)
RM0503
Bits 6:4 PON[2:0]: Pulse ON duration
These bits are written by software to define the pulse duration in terms of ck_ps pulses.
A short pulse leads to lower power consumption, but displays with high internal resistance
may need a longer pulse to achieve satisfactory contrast.
Note that the pulse is never longer than one half prescaled LCD clock period.
000: 0
001: 1/ck_ps
010: 2/ck_ps
011: 3/ck_ps
100: 4/ck_ps
101: 5/ck_ps
110: 6/ck_ps
111: 7/ck_ps
PON duration example with LCDCLK = 32.768 kHz and PS=0x03:
000: 0 µs
001: 244 µs
010: 488 µs
011: 782 µs
100: 976 µs
101: 1.22 ms
110: 1.46 ms
111: 1.71 ms
Bit 3 UDDIE: Update display done interrupt enable
This bit is set and cleared by software.
0: LCD update display done interrupt disabled
1: LCD update display done interrupt enabled
Bit 2 Reserved, must be kept at reset value.
Bit 1 SOFIE: Start of frame interrupt enable
This bit is set and cleared by software.
0: LCD start-of-frame interrupt disabled
1: LCD start-of-frame interrupt enabled
Bit 0 HD: High drive enable
This bit is written by software to enable a low resistance divider. Displays with high internal
resistance may need a longer drive time to achieve satisfactory contrast. This bit is useful in
this case if some additional power consumption can be tolerated.
0: Permanent high drive disabled
1: Permanent high drive enabled. When HD = 1, PON[2:0] must be programmed to 001.
19.6.3
LCD status register (LCD_SR)
Address offset: 0x08
Reset value: 0x0000 0020
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
FCRSF
RDY
UDD
UDR
SOF
ENS
r
r
r
rs
r
r
456/1325
RM0503 Rev 2
RM0503
Liquid crystal display controller (LCD)
Bits 31:6 Reserved, must be kept at reset value.
Bit 5 FCRSF: LCD frame control register synchronization flag
This bit is set by hardware each time the LCD_FCR register is updated in the LCDCLK
domain. It is cleared by hardware when writing to the LCD_FCR register.
0: LCD frame control register not yet synchronized
1: LCD frame control register synchronized
Bit 4 RDY: Ready flag
This bit is set and cleared by hardware. It indicates the status of the stepup converter.
0: Not ready
1: Stepup converter enabled and ready to provide the correct voltage
Bit 3 UDD: Update display done
This bit is set by hardware. It is cleared by writing 1 to UDDC in LCD_CLR. The bit set has
priority over the clear.
0: No event
1: Update display request done. A UDD interrupt is generated if UDDIE = 1 in LCD_FCR.
Note: If the device is in Stop mode (PCLK not provided), UDD does not generate an interrupt
even if UDDIE = 1. If the display is not enabled, the UDD interrupt never occurs.
Bit 2 UDR: Update display request
Each time software modifies the LCD_RAM, it must set this bit to transfer the updated data
to the second level buffer. This bit stays set until the end of the update. During this time,
the LCD_RAM is write protected.
0: No effect
1: Update display request
Note: When the display is disabled, the update is performed for all LCD_DISPLAY locations.
When the display is enabled, the update is performed only for locations for which
commons are active (depending on DUTY). For example if DUTY = 1/2,
only the LCD_DISPLAY of COM0 and COM1 are updated.
Writing 0 on this bit or writing 1 when it is already 1 has no effect. This bit can be
cleared by hardware only. It can be cleared only when LCDEN = 1
Bit 1 SOF: Start-of-frame flag
This bit is set by hardware at the beginning of a new frame, at the same time as the display
data is updated. It is cleared by writing a 1 to SOFC in LCD_CLR. The bit clear has priority
over the set.
0: No event
1: Start-of-frame event occurred. An LCD SOF interrupt is generated if SOFIE is set.
Bit 0 ENS: LCD enabled status
This bit is set and cleared by hardware. It indicates the LCD controller status.
0: LCD controller disabled
1: LCD controller enabled
Note: This bit is set immediately when LCDEN in LCD_CR goes from 0 to 1. On deactivation,
it reflects the real LCD status. It becomes 0 at the end of the last displayed frame.
RM0503 Rev 2
457/1325
461
Liquid crystal display controller (LCD)
19.6.4
RM0503
LCD clear register (LCD_CLR)
Address offset: 0x0C
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
UDDC
Res.
SOFC
Res.
w
w
Bits 31:4 Reserved, must be kept at reset value.
Bit 3 UDDC: Update display done clear
This bit is written by software to clear UDD in LCD_SR.
0: No effect
1: Clear UDD flag.
Bit 2 Reserved, must be kept at reset value.
Bit 1 SOFC: Start-of-frame flag clear
This bit is written by software to clear SOF in LCD_SR.
0: No effect
1: Clear SOF flag.
Bit 0 Reserved, must be kept at reset value.
19.6.5
LCD display memory (LCD_RAMx)
Address offset: 0x14 + 0x4 * x, (x = 0, 2, 4, 6, 8, 10, 12, 14)
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
SEGMENT_DATA[31:16]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
SEGMENT_DATA[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:0 SEGMENT_DATA[31:0]:
Each bit corresponds to one pixel of the LCD display.
0: Pixel inactive
1: Pixel active
458/1325
RM0503 Rev 2
RM0503
Liquid crystal display controller (LCD)
19.6.6
LCD display memory (LCD_RAMx)
Address offset: 0x14 + 0x4 * x, (x = 1, 3, 5, 7)
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
19
18
17
16
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
SEGMENT_DATA[51:48]
SEGMENT_DATA[47:32]
rw
rw
Bits 31:20 Reserved, must be kept at reset value.
Bits 19:0 SEGMENT_DATA[51:32]:
Each bit corresponds to one pixel of the LCD display.
0: Pixel inactive
1: Pixel active
19.6.7
LCD display memory (LCD_RAMx)
Address offset: 0x14 + 0x4 * x, (x = 9, 11, 13, 15)
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
SEGMENT_DATA[47:32]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 SEGMENT_DATA[47:32]:
Each bit corresponds to one pixel of the LCD display.
0: Pixel inactive
1: Pixel active
19.6.8
LCD register map
RM0503 Rev 2
0
0
0
0
0
0
VSEL
BIAS[1:0]
0
DUTY
[2:0]
LCDEN
MUX_SEG.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
BUFEN
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
LCD_CR
Res.
0x00
Register
name
Res.
Offset
Table 102. LCD register map and reset values
0
0
459/1325
461
460/1325
S26
S25
S24
S23
S22
S21
S20
S19
S18
S17
S16
S15
S14
S13
S12
S11
S10
S09
S08
S07
S06
S05
S04
S03
S02
S01
S00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
S47
S46
S45
S44
S43
S42
S41
S40
S39
S38
S37
S36
S35
S34
S33
S32
0x38
S27
LCD_RAM
(COM4)
Res.
0x34
S09
S08
S07
S06
S05
S04
S03
S02
S01
S00
0
0
0
0
0
0
0
0
0
0
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
S32
S10
0
S33
S11
0
S34
S12
0
S35
S13
0
S36
S14
0
S37
S15
0
S38
S16
0
S39
S17
0
S40
S18
0
S41
S19
0
S42
S20
0
S43
S21
0
S44
S22
0
S45
S23
0
S46
S24
0
S47
S25
0
S48
S26
0
S49
S27
0
Res.
S09
S08
S07
S06
S05
S04
S03
S02
S01
S00
0
0
0
0
0
0
0
0
0
0
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
S32
S10
0
S33
S11
0
S34
S12
0
S35
S13
0
S36
S14
0
S37
S15
0
S38
S16
0
S39
S17
0
S40
S18
0
S41
S19
0
S42
S20
0
S43
S21
0
S44
S22
0
S45
S23
0
S46
S24
0
S47
S25
0
S48
S26
0
S49
S27
0
S50
S28
0
S51
S29
0
Res.
S10
S09
S08
S07
S06
S05
S04
S03
S02
S01
S00
0
0
0
0
0
0
0
0
0
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
S32
S11
0
S33
S12
0
S34
S13
0
S35
S14
0
S36
S15
0
S37
S16
0
S38
S17
0
S39
S18
0
S40
S19
0
S41
S20
0
S42
S21
0
S43
S22
0
S44
S23
0
S45
S24
0
S46
S25
0
S47
S26
0
S48
S27
0
S49
S28
0
S50
S29
0
S51
S30
0
Res.
S11
S10
S09
S08
S07
S06
S05
S04
S03
S02
S01
S00
0
0
0
0
0
0
0
0
0
0
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
S32
S12
0
S33
S13
0
S34
S14
0
S35
S15
0
S36
S16
0
S37
S17
0
S38
S18
0
S39
S19
0
S40
S20
0
S41
S21
0
S42
S22
0
S43
S23
0
S44
S24
0
S45
S25
0
S46
S26
0
S47
S27
0
S48
S28
0
S49
S29
0
S50
S30
0
S51
S31
0
Res.
RM0503 Rev 2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
UDR
SOF
ENS
1
0
0
0
0
0
Res.
SOFC
BLINKF
[2:0]
BLINK[1:0]
Reset value
0
SOFIE
HD
Res.
UDDIE
PON
[2:0]
Res.
RDY
Reset value
UDD
0
Res.
0
UDDC
0
FCRSF
0
Res.
0
Res.
Res.
Res.
Res.
Res.
DEAD
[2:0]
Res.
0
Res.
Res.
0
Res.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
CC[2:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
LCD_FCR
DIV[3:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
S50
S28
S31
0
Res.
Register
name
PS[3:0]
S51
S29
0
Res.
0x30
0
Res.
LCD_RAM
(COM3)
S28
0x2C
S29
0x28
Res.
LCD_RAM
(COM2)
Res.
0x24
S30
0x20
S31
LCD_RAM
(COM1)
Res.
0x1C
Res.
0x18
S30
LCD_RAM
(COM0)
S31
0x14
Res.
LCD_CLR
Res.
0x0C
S30
LCD_SR
S31
0x08
Res.
0x04
Res.
Offset
Liquid crystal display controller (LCD)
RM0503
Table 102. LCD register map and reset values (continued)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
S29
S28
S27
S26
S25
S24
S23
S22
S21
S20
S19
S18
S17
S16
S15
S14
S13
S12
S11
S10
S09
S08
S07
S06
S05
S04
S03
S02
S01
S00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
S47
S46
S45
S44
S43
S42
S41
S40
S39
S38
S37
S36
S35
S34
S33
S32
LCD_RAM
(COM7)
Res.
0x4C
S14
S13
S12
S11
S10
S09
S08
S07
S06
S05
S04
S03
S02
S01
S00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RM0503 Rev 2
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
S32
S15
0
S33
S16
0
S34
S17
0
S35
S18
0
S36
S19
0
S37
S20
0
S38
S21
0
S39
S22
0
S40
S23
0
S41
S24
0
S42
S25
0
S43
S26
0
S44
S27
0
S45
S28
0
S46
S29
0
S47
S30
0x48
S31
LCD_RAM
(COM6)
Res.
0x44
Res.
S15
S14
S13
S12
S11
S10
S09
S08
S07
S06
S05
S04
S03
S02
S01
S00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
S32
S16
0
S33
S17
0
S34
S18
0
S35
S19
0
S36
S20
0
S37
S21
0
S38
S22
0
S39
S23
0
S40
S24
0
S41
S25
0
S42
S26
0
S43
S27
0
S44
S28
0
S45
S29
0
S46
S30
0
S47
S31
0
Res.
0x40
S30
LCD_RAM
(COM5)
S31
0x3C
Res.
0x50
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Register
name
Res.
Offset
RM0503
Liquid crystal display controller (LCD)
Table 102. LCD register map and reset values (continued)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Refer to Section 2.2 for the register boundary addresses table.
461/1325
461
Touch sensing controller (TSC)
RM0503
20
Touch sensing controller (TSC)
20.1
Introduction
The touch sensing controller provides a simple solution for adding capacitive sensing
functionality to any application. Capacitive sensing technology is able to detect finger
presence near an electrode that is protected from direct touch by a dielectric (for example
glass, plastic). The capacitive variation introduced by the finger (or any conductive object) is
measured using a proven implementation based on a surface charge transfer acquisition
principle.
The touch sensing controller is fully supported by the STMTouch touch sensing firmware
library, which is free to use and allows touch sensing functionality to be implemented reliably
in the end application.
20.2
TSC main features
The touch sensing controller has the following main features:
Note:
462/1325
•
Proven and robust surface charge transfer acquisition principle
•
Supports up to 21 capacitive sensing channels
•
Up to 7 capacitive sensing channels can be acquired in parallel offering a very good
response time
•
Spread spectrum feature to improve system robustness in noisy environments
•
Full hardware management of the charge transfer acquisition sequence
•
Programmable charge transfer frequency
•
Programmable sampling capacitor I/O pin
•
Programmable channel I/O pin
•
Programmable max count value to avoid long acquisition when a channel is faulty
•
Dedicated end of acquisition and max count error flags with interrupt capability
•
One sampling capacitor for up to 3 capacitive sensing channels to reduce the system
components
•
Compatible with proximity, touchkey, linear and rotary touch sensor implementation
•
Designed to operate with STMTouch touch sensing firmware library
The number of capacitive sensing channels is dependent on the size of the packages and
subject to I/O availability.
RM0503 Rev 2
RM0503
20.3
Touch sensing controller (TSC)
TSC implementation
Table 103. TSC implementation
TSC features
STM32U031xx
STM32U0x3xx
Number of analog I/O groups
6(1)
7
Number of channels
18
21
1. Only Gx, x = 1 to 6 applies for this category of devices. G7 related information does not apply and
corresponding bits are reserved.
RM0503 Rev 2
463/1325
483
Touch sensing controller (TSC)
RM0503
20.4
TSC functional description
20.4.1
TSC block diagram
The block diagram of the touch sensing controller is shown in Figure 85.
Figure 85. TSC block diagram
SYNC
Pulse generator
fHCLK
G1_IO1
Clock
prescalers
G1_IO2
G1_IO3
Spread spectrum
G1_IO4
G2_IO1
G2_IO2
Group counters
I/O control
logic
G2_IO3
G2_IO4
TSC_IOG1CR
TSC_IOG2CR
Gx_IO1
Gx_IO2
TSC_IOGxCR
Gx_IO3
Gx_IO4
MS30929V1
20.4.2
Surface charge transfer acquisition overview
The surface charge transfer acquisition is a proven, robust and efficient way to measure a
capacitance. It uses a minimum number of external components to operate with a single
ended electrode type. This acquisition is designed around an analog I/O group composed of
up to four GPIOs (see Figure 86). Several analog I/O groups are available to allow the
acquisition of several capacitive sensing channels simultaneously and to support a larger
number of capacitive sensing channels. Within a same analog I/O group, the acquisition of
the capacitive sensing channels is sequential.
One of the GPIOs is dedicated to the sampling capacitor CS. Only one sampling capacitor
I/O per analog I/O group must be enabled at a time.
The remaining GPIOs are dedicated to the electrodes and are commonly called channels.
For some specific needs (such as proximity detection), it is possible to simultaneously
enable more than one channel per analog I/O group.
464/1325
RM0503 Rev 2
RM0503
Touch sensing controller (TSC)
Figure 86. Surface charge transfer analog I/O group structure
Analog
I/O group
Electrode 1
VSENSOR
RS1
Gx_IO1
CX1
Gx_IO2
CS
VCS
Electrode 2
VSENSOR
RS2
CX2
Electrode 3
VSENSOR
Gx_IO3
RS3
Gx_IO4
CX3
MSv30930V3
Note:
Gx_IOy where x is the analog I/O group number and y the GPIO number within the selected
group.
The surface charge transfer acquisition principle consists of charging an electrode
capacitance (CX) and transferring a part of the accumulated charge into a sampling
capacitor (CS). This sequence is repeated until the voltage across CS reaches a given
threshold (VIH in our case). The number of charge transfers required to reach the threshold
is a direct representation of the size of the electrode capacitance.
Table 104 details the charge transfer acquisition sequence of the capacitive sensing
channel 1. States 3 to 7 are repeated until the voltage across CS reaches the given
threshold. The same sequence applies to the acquisition of the other channels. The
electrode serial resistor RS improves the ESD immunity of the solution.
RM0503 Rev 2
465/1325
483
Touch sensing controller (TSC)
RM0503
Table 104. Acquisition sequence summary
State
Gx_IO1
(channel)
Gx_IO2
(sampling)
#1
Input floating
with analog
switch closed
Output opendrain low with
analog switch
closed
#2
#3
Note:
Gx_IO4
(channel)
Output pushpull high
State description
Input floating with analog switch Discharge all CX and
CS
closed
Input floating
#4
#5
Gx_IO3
(channel)
Dead time
Input floating
Charge CX1
Input floating
Input floating with analog switch
closed
Dead time
Charge transfer from
CX1 to CS
Input floating
#6
Input floating
Dead time
#7
Input floating
Measure CS voltage
Gx_IOy where x is the analog I/O group number and y the GPIO number within the selected
group.
The voltage variation over the time on the sampling capacitor CS is detailed below (refer to
Figure 86 for VSENSOR and VCS definition):
Figure 87. Sampling capacitor voltage variation
VSENSOR
VCS
VDD
VIH
S1
S2
t
MSv71405V1
466/1325
RM0503 Rev 2
RM0503
20.4.3
Touch sensing controller (TSC)
Reset and clocks
The TSC clock source is the AHB clock (HCLK). Two programmable prescalers are used to
generate the pulse generator and the spread spectrum internal clocks:
•
The pulse generator clock (PGCLK) is defined using the PGPSC[2:0] bits of the
TSC_CR register
•
The spread spectrum clock (SSCLK) is defined using the SSPSC bit of the TSC_CR
register
The reset and clock controller (RCC) provides dedicated bits to enable the touch sensing
controller clock and to reset this peripheral. For more information, refer to Section 5: Reset
and clock control (RCC).
20.4.4
Charge transfer acquisition sequence
An example of a charge transfer acquisition sequence is detailed in Figure 88.
Figure 88. Charge transfer acquisition sequence
Charge transfer frequency
CLK_AHB
1
CX
HiZ
0
1
CS
HiZ
CS reading
Pulse low
state
Dead time state
Dead time state
Pulse high
state
Spread spectrum state
Pulse low
state (charge
transfer from
CX to CS)
CS reading
Pulse high
state
(charge of CX)
Dead time state
Discharge
CX and CS
Dead time state
State
Dead time state
0
t
MSv30932V3
For higher flexibility, the charge transfer frequency is fully configurable. Both the pulse high
state (charge of CX) and the pulse low state (transfer of charge from CX to CS) duration can
be defined using the CTPH[3:0] and CTPL[3:0] bits in the TSC_CR register. The standard
range for the pulse high and low states duration is 500 ns to 2 µs. To ensure a correct
measurement of the electrode capacitance, the pulse high state duration must be set to
ensure that CX is always fully charged.
A dead time where both the sampling capacitor I/O and the channel I/O are in input floating
state is inserted between the pulse high and low states to ensure an optimum charge
transfer acquisition sequence. This state duration is 1 period of HCLK.
At the end of the pulse high state and if the spread spectrum feature is enabled, a variable
number of periods of the SSCLK clock are added.
RM0503 Rev 2
467/1325
483
Touch sensing controller (TSC)
RM0503
The reading of the sampling capacitor I/O, to determine if the voltage across CS has
reached the given threshold, is performed at the end of the pulse low state.
Note:
The following TSC control register configurations are forbidden:
•
•
20.4.5
bits PGPSC are set to 000 and bits CTPL are set to 0001
bits PGPSC are set to 001 and bits CTPL are set to 0000
Spread spectrum feature
The spread spectrum feature generates a variation of the charge transfer frequency. This is
done to improve the robustness of the charge transfer acquisition in noisy environments and
also to reduce the induced emission. The maximum frequency variation is in the range of
10% to 50% of the nominal charge transfer period. For instance, for a nominal charge
transfer frequency of 250 kHz (4 µs), the typical spread spectrum deviation is 10% (400 ns)
which leads to a minimum charge transfer frequency of ~227 kHz.
In practice, the spread spectrum consists of adding a variable number of SSCLK periods to
the pulse high state using the principle shown below:
Figure 89. Spread spectrum variation principle
Deviation value
(SSD +1)
3
2
1
0
n-1 n
n+1
Number of pulses
MS30933V1
The table below details the maximum frequency deviation with different HCLK settings:
Table 105. Spread spectrum deviation versus AHB clock frequency
fHCLK
Spread spectrum step
Maximum spread spectrum deviation
48 MHz
20.8 ns
5333.3 ns
The spread spectrum feature can be disabled/enabled using the SSE bit in the TSC_CR
register. The frequency deviation is also configurable to accommodate the device HCLK
clock frequency and the selected charge transfer frequency through the SSPSC and
SSD[6:0] bits in the TSC_CR register.
468/1325
RM0503 Rev 2
RM0503
20.4.6
Touch sensing controller (TSC)
Max count error
The max count error prevents long acquisition times resulting from a faulty capacitive
sensing channel. It consists of specifying a maximum count value for the analog I/O group
counters. This maximum count value is specified using the MCV[2:0] bits in the TSC_CR
register. As soon as an acquisition group counter reaches this maximum value, the ongoing
acquisition is stopped and the end of acquisition (EOAF bit) and max count error (MCEF bit)
flags are both set. An interrupt can also be generated if the corresponding end of acquisition
(EOAIE bit) or/and max count error (MCEIE bit) interrupt enable bits are set.
20.4.7
Sampling capacitor I/O and channel I/O mode selection
To allow the GPIOs to be controlled by the touch sensing controller, the corresponding
alternate function must be enabled through the standard GPIO registers and the GPIOxAFR
registers.
The GPIOs modes controlled by the TSC are defined using the TSC_IOSCR and
TSC_IOCCR register.
When there is no ongoing acquisition, all the I/Os controlled by the touch sensing controller
are in default state. While an acquisition is ongoing, only unused I/Os (neither defined as
sampling capacitor I/O nor as channel I/O) are in default state. The IODEF bit in the
TSC_CR register defines the configuration of the I/Os which are in default state. The table
below summarizes the configuration of the I/O depending on its mode.
Table 106. I/O state depending on its mode and IODEF bit value
IODEF bit
Acquisition
status
Unused I/O
mode
Channel I/O
mode
Sampling
capacitor I/O
mode
0
(output push-pull low)
No
Output push-pull
low
Output push-pull
low
Output push-pull
low
0
(output push-pull low)
Ongoing
Output push-pull
low
-
-
1
(input floating)
No
Input floating
Input floating
Input floating
1
(input floating)
Ongoing
Input floating
-
-
Unused I/O mode
An unused I/O corresponds to a GPIO controlled by the TSC peripheral but not defined as
an electrode I/O nor as a sampling capacitor I/O.
Sampling capacitor I/O mode
To allow the control of the sampling capacitor I/O by the TSC peripheral, the corresponding
GPIO must be first set to alternate output open drain mode and then the corresponding
Gx_IOy bit in the TSC_IOSCR register must be set.
Only one sampling capacitor per analog I/O group must be enabled at a time.
Channel I/O mode
RM0503 Rev 2
469/1325
483
Touch sensing controller (TSC)
RM0503
To allow the control of the channel I/O by the TSC peripheral, the corresponding GPIO must
be first set to alternate output push-pull mode and the corresponding Gx_IOy bit in the
TSC_IOCCR register must be set.
For proximity detection where a higher equivalent electrode surface is required or to speedup the acquisition process, it is possible to enable and simultaneously acquire several
channels belonging to the same analog I/O group.
Note:
During the acquisition phase and even if the TSC peripheral alternate function is not
enabled, as soon as the TSC_IOSCR or TSC_IOCCR bit is set, the corresponding GPIO
analog switch is automatically controlled by the touch sensing controller.
20.4.8
Acquisition mode
The touch sensing controller offers two acquisition modes:
•
Normal acquisition mode: the acquisition starts as soon as the START bit in the
TSC_CR register is set.
•
Synchronized acquisition mode: the acquisition is enabled by setting the START bit in
the TSC_CR register but only starts upon the detection of a falling edge or a rising
edge and high level on the SYNC input pin. This mode is useful for synchronizing the
capacitive sensing channels acquisition with an external signal without additional CPU
load.
The GxE bits in the TSC_IOGCSR registers specify which analog I/O groups are enabled
(corresponding counter is counting). The CS voltage of a disabled analog I/O group is not
monitored and this group does not participate in the triggering of the end of acquisition flag.
However, if the disabled analog I/O group contains some channels, they are pulsed.
When the CS voltage of an enabled analog I/O group reaches the given threshold, the
corresponding GxS bit of the TSC_IOGCSR register is set. When the acquisition of all
enabled analog I/O groups is complete (all GxS bits of all enabled analog I/O groups are
set), the EOAF flag in the TSC_ISR register is set. An interrupt request is generated if the
EOAIE bit in the TSC_IER register is set.
In the case that a max count error is detected, the ongoing acquisition is stopped and both
the EOAF and MCEF flags in the TSC_ISR register are set. Interrupt requests can be
generated for both events if the corresponding bits (EOAIE and MCEIE bits of the TSCIER
register) are set. Note that when the max count error is detected the remaining GxS bits in
the enabled analog I/O groups are not set.
To clear the interrupt flags, the corresponding EOAIC and MCEIC bits in the TSC_ICR
register must be set.
The analog I/O group counters are cleared when a new acquisition is started. They are
updated with the number of charge transfer cycles generated on the corresponding
channel(s) upon the completion of the acquisition.
20.4.9
I/O hysteresis and analog switch control
In order to offer a higher flexibility, the touch sensing controller is able to take the control of
the Schmitt trigger hysteresis and analog switch of each Gx_IOy. This control is available
whatever the I/O control mode is (controlled by standard GPIO registers or other
peripherals) assuming that the touch sensing controller is enabled. This may be useful to
perform a different acquisition sequence or for other purposes.
470/1325
RM0503 Rev 2
RM0503
Touch sensing controller (TSC)
In order to improve the system immunity, the Schmitt trigger hysteresis of the GPIOs
controlled by the TSC must be disabled by resetting the corresponding Gx_IOy bit in the
TSC_IOHCR register.
20.5
TSC low-power modes
Table 107. Effect of low-power modes on TSC
Mode
Description
Sleep
No effect. Peripheral interrupts cause the device to exit Sleep mode.
Low power run
No effect.
Low power sleep No effect. Peripheral interrupts cause the device to exit Low-power sleep mode.
Stop 0 / Stop 1
Stop 2
Standby
Shutdown
20.5.1
Peripheral registers content is kept.
Powered-down. The peripheral must be reinitialized after exiting Standby or
Shutdown mode.
Comparator usage overview
This low-power mode requires that the GPIO dedicated to the sampling capacitor CS has
both the TSC alternate function (TSC_Gx_IOy) and the COMP alternate function
(COMPx_INP) available, see product datasheet.
In this case, the TSC peripheral has the possibility to use the microcontroller internal
comparator to achieve lower power consumption.
The method uses the same principle as the surface charge transfer acquisition that is the
acquisition of the different sensors is automatically stopped when the voltage on the
sampling capacitor reaches a certain threshold.
RM0503 Rev 2
471/1325
483
Touch sensing controller (TSC)
RM0503
Figure 90. Surface charge transfer with comparator analog I/O group structure
Analog I/O
group
Comparator
(COMP)
Electrode 1
RS1
VSENSOR
Gx_IO1
System
configuration
controller
(SYSCFG)
Touch
sensing
controller
(TSC)
CX1
COMPx INP
+
Gx_IO2
COMPx INM
CS
VCS
COMPx
TSC
controller
-
Electrode 2
COMPx_INM_SEL
RS2
Gx_IO3
COMPx_INM I/Os
SYSCFG_
TSCCR
VREFINT
VSENSOR
CX2
3/4 VREFINT
1/2 VREFINT
1/4 VREFINT
Electrode 3
RS3
VSENSOR
Gx_IO4
CX3
MSv71404V1
Unlike charge transfer acquisition (where the threshold is fixed = VIH), here the threshold is
programmable. The sampling capacitor is internally redirected to the comparator input in
order to offer a programmable voltage threshold value VCOMP based on VREFINT. The
possible configurations are about 0.3, 0.6, 0.9 or 1.2 V (corresponding to 1/4VREFINT,
1/2VREFINT, 3/4VREFINT or VREFINT).
VREFINT is the bandgap voltage (~1.2 V).
By reducing the voltage threshold, the acquisition time is shortened which in turn reduces
the power consumption.
The selection of the threshold value is a compromise between sensor acquisition time (the
lowest the threshold the best) and sensor sensitivity (the highest the threshold the best).
Figure 91 below compares the normal mode and the comparator mode (see Figure 90 for
VSENSOR and VCS definition).
The SYSCFG_TSCCR register should be set appropriately in order to configure the MUX
allowing the use of the comparator mode instead of the usual TSC mode (see device
reference manual).
472/1325
RM0503 Rev 2
RM0503
Touch sensing controller (TSC)
Figure 91. Sensor voltage variation for both normal and comparator mode
VSENSOR
VCS
VDD
VIH
S1
S2
t
TSC normal operation
VSENSOR
VCS
VDD
VIH
VCOMP
S1
S2
t
TSC with comparator mode
MSv71403V1
Using the internal comparator, the acquisition time is consequently reduced. This implies
that the number of counts needed to reach the threshold is also reduced, thus, the TSC
peripheral achieves lower power consumption.
The COMPx_INM_SEL and COMPx_INP_SEL bitfields used to configure the comparator
are available in Section 17.6.1: Comparator 1 control and status register (COMP1_CSR)
and Section 17.6.2: Comparator 2 control and status register (COMP2_CSR).
RM0503 Rev 2
473/1325
483
Touch sensing controller (TSC)
20.6
RM0503
TSC interrupts
Table 108. Interrupt control bits
Interrupt event
Enable
control bit
Event flag
Clear flag
bit
Exit the
Sleep mode
Exit the
Stop mode
Exit the
Standby mode
End of acquisition
EOAIE
EOAIF
EOAIC
Yes
No
No
Max count error
MCEIE
MCEIF
MCEIC
Yes
No
No
20.7
TSC registers
Refer to Section 1.2 on page 51 of the reference manual for a list of abbreviations used in
register descriptions.
The peripheral registers can be accessed by words (32-bit).
20.7.1
TSC control register (TSC_CR)
Address offset: 0x00
Reset value: 0x0000 0000
31
30
29
28
27
CTPH[3:0]
26
25
24
23
22
21
CTPL[3:0]
20
19
18
17
SSD[6:0]
16
SSE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
IODEF
SYNC
POL
AM
START
TSCE
rw
rw
rw
rw
rw
SSPSC
rw
474/1325
PGPSC[2:0]
rw
rw
rw
MCV[2:0]
rw
RM0503 Rev 2
rw
rw
RM0503
Touch sensing controller (TSC)
Bits 31:28 CTPH[3:0]: Charge transfer pulse high
These bits are set and cleared by software. They define the duration of the high state of the
charge transfer pulse (charge of CX).
0000: 1x tPGCLK
0001: 2x tPGCLK
...
1111: 16x tPGCLK
Note: These bits must not be modified when an acquisition is ongoing.
Bits 27:24 CTPL[3:0]: Charge transfer pulse low
These bits are set and cleared by software. They define the duration of the low state of the
charge transfer pulse (transfer of charge from CX to CS).
0000: 1x tPGCLK
0001: 2x tPGCLK
...
1111: 16x tPGCLK
Note: These bits must not be modified when an acquisition is ongoing.
Note: Some configurations are forbidden. Refer to the Section 20.4.4: Charge transfer
acquisition sequence for details.
Bits 23:17 SSD[6:0]: Spread spectrum deviation
These bits are set and cleared by software. They define the spread spectrum deviation which
consists in adding a variable number of periods of the SSCLK clock to the charge transfer
pulse high state.
0000000: 1x tSSCLK
0000001: 2x tSSCLK
...
1111111: 128x tSSCLK
Note: These bits must not be modified when an acquisition is ongoing.
Bit 16 SSE: Spread spectrum enable
This bit is set and cleared by software to enable/disable the spread spectrum feature.
0: Spread spectrum disabled
1: Spread spectrum enabled
Note: This bit must not be modified when an acquisition is ongoing.
Bit 15 SSPSC: Spread spectrum prescaler
This bit is set and cleared by software. It selects the AHB clock divider used to generate the
spread spectrum clock (SSCLK).
0: fHCLK
1: fHCLK /2
Note: This bit must not be modified when an acquisition is ongoing.
RM0503 Rev 2
475/1325
483
Touch sensing controller (TSC)
RM0503
Bits 14:12 PGPSC[2:0]: Pulse generator prescaler
These bits are set and cleared by software.They select the AHB clock divider used to
generate the pulse generator clock (PGCLK).
000: fHCLK
001: fHCLK /2
010: fHCLK /4
011: fHCLK /8
100: fHCLK /16
101: fHCLK /32
110: fHCLK /64
111: fHCLK /128
Note: These bits must not be modified when an acquisition is ongoing.
Note: Some configurations are forbidden. Refer to the Section 20.4.4: Charge transfer
acquisition sequence for details.
Bits 11:8 Reserved, must be kept at reset value.
Bits 7:5 MCV[2:0]: Max count value
These bits are set and cleared by software. They define the maximum number of charge
transfer pulses that can be generated before a max count error is generated.
000: 255
001: 511
010: 1023
011: 2047
100: 4095
101: 8191
110: 16383
111: reserved
Note: These bits must not be modified when an acquisition is ongoing.
Bit 4 IODEF: I/O Default mode
This bit is set and cleared by software. It defines the configuration of all the TSC I/Os when
there is no ongoing acquisition. When there is an ongoing acquisition, it defines the
configuration of all unused I/Os (not defined as sampling capacitor I/O or as channel I/O).
0: I/Os are forced to output push-pull low
1: I/Os are in input floating
Note: This bit must not be modified when an acquisition is ongoing.
Bit 3 SYNCPOL: Synchronization pin polarity
This bit is set and cleared by software to select the polarity of the synchronization input pin.
0: Falling edge only
1: Rising edge and high level
476/1325
RM0503 Rev 2
RM0503
Touch sensing controller (TSC)
Bit 2 AM: Acquisition mode
This bit is set and cleared by software to select the acquisition mode.
0: Normal acquisition mode (acquisition starts as soon as START bit is set)
1: Synchronized acquisition mode (acquisition starts if START bit is set and when the
selected signal is detected on the SYNC input pin)
Note: This bit must not be modified when an acquisition is ongoing.
Bit 1 START: Start a new acquisition
This bit is set by software to start a new acquisition. It is cleared by hardware as soon as the
acquisition is complete or by software to cancel the ongoing acquisition.
0: Acquisition not started
1: Start a new acquisition
Bit 0 TSCE: Touch sensing controller enable
This bit is set and cleared by software to enable/disable the touch sensing controller.
0: Touch sensing controller disabled
1: Touch sensing controller enabled
Note: When the touch sensing controller is disabled, TSC registers settings have no effect.
20.7.2
TSC interrupt enable register (TSC_IER)
Address offset: 0x04
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
MCEIE
EOAIE
rw
rw
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 MCEIE: Max count error interrupt enable
This bit is set and cleared by software to enable/disable the max count error interrupt.
0: Max count error interrupt disabled
1: Max count error interrupt enabled
Bit 0 EOAIE: End of acquisition interrupt enable
This bit is set and cleared by software to enable/disable the end of acquisition interrupt.
0: End of acquisition interrupt disabled
1: End of acquisition interrupt enabled
RM0503 Rev 2
477/1325
483
Touch sensing controller (TSC)
20.7.3
RM0503
TSC interrupt clear register (TSC_ICR)
Address offset: 0x08
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
MCEIC EOAIC
rw
rw
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 MCEIC: Max count error interrupt clear
This bit is set by software to clear the max count error flag and it is cleared by hardware
when the flag is reset. Writing a 0 has no effect.
0: No effect
1: Clears the corresponding MCEF of the TSC_ISR register
Bit 0 EOAIC: End of acquisition interrupt clear
This bit is set by software to clear the end of acquisition flag and it is cleared by hardware
when the flag is reset. Writing a 0 has no effect.
0: No effect
1: Clears the corresponding EOAF of the TSC_ISR register
20.7.4
TSC interrupt status register (TSC_ISR)
Address offset: 0x0C
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
MCEF
EOAF
r
r
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 MCEF: Max count error flag
This bit is set by hardware as soon as an analog I/O group counter reaches the max count
value specified. It is cleared by software writing 1 to the bit MCEIC of the TSC_ICR register.
0: No max count error (MCE) detected
1: Max count error (MCE) detected
Bit 0 EOAF: End of acquisition flag
This bit is set by hardware when the acquisition of all enabled group is complete (all GxS bits
of all enabled analog I/O groups are set or when a max count error is detected). It is cleared
by software writing 1 to the bit EOAIC of the TSC_ICR register.
0: Acquisition is ongoing or not started
1: Acquisition is complete
478/1325
RM0503 Rev 2
RM0503
Touch sensing controller (TSC)
20.7.5
TSC I/O hysteresis control register (TSC_IOHCR)
Address offset: 0x10
Reset value: 0xFFFF FFFF
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
27
26
25
24
23
22
21
20
19
18
17
16
G7_IO4 G7_IO3 G7_IO2 G7_IO1 G6_IO4 G6_IO3 G6_IO2 G6_IO1 G5_IO4 G5_IO3 G5_IO2 G5_IO1
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
11
10
9
8
7
6
5
4
3
2
1
0
G4_IO4 G4_IO3 G4_IO2 G4_IO1 G3_IO4 G3_IO3 G3_IO2 G3_IO1 G2_IO4 G2_IO3 G2_IO2 G2_IO1 G1_IO4 G1_IO3 G1_IO2 G1_IO1
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:28 Reserved, must be kept at reset value.
Bits 27:0 Gx_IOy: Gx_IOy Schmitt trigger hysteresis mode
These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger
hysteresis.
0: Gx_IOy Schmitt trigger hysteresis disabled
1: Gx_IOy Schmitt trigger hysteresis enabled
Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is
(even if controlled by standard GPIO registers).
20.7.6
TSC I/O analog switch control register
(TSC_IOASCR)
Address offset: 0x18
Reset value: 0x0000 0000
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
27
26
25
24
23
22
21
20
19
18
17
16
G7_IO4 G7_IO3 G7_IO2 G7_IO1 G6_IO4 G6_IO3 G6_IO2 G6_IO1 G5_IO4 G5_IO3 G5_IO2 G5_IO1
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
11
10
9
8
7
6
5
4
3
2
1
0
G4_IO4 G4_IO3 G4_IO2 G4_IO1 G3_IO4 G3_IO3 G3_IO2 G3_IO1 G2_IO4 G2_IO3 G2_IO2 G2_IO1 G1_IO4 G1_IO3 G1_IO2 G1_IO1
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:28 Reserved, must be kept at reset value.
Bits 27:0 Gx_IOy: Gx_IOy analog switch enable
These bits are set and cleared by software to enable/disable the Gx_IOy analog switch.
0: Gx_IOy analog switch disabled (opened)
1: Gx_IOy analog switch enabled (closed)
Note: These bits control the I/O analog switch whatever the I/O control mode is (even if
controlled by standard GPIO registers).
RM0503 Rev 2
479/1325
483
Touch sensing controller (TSC)
20.7.7
RM0503
TSC I/O sampling control register (TSC_IOSCR)
Address offset: 0x20
Reset value: 0x0000 0000
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
27
26
25
24
23
22
21
20
19
18
17
16
G7_IO4 G7_IO3 G7_IO2 G7_IO1 G6_IO4 G6_IO3 G6_IO2 G6_IO1 G5_IO4 G5_IO3 G5_IO2 G5_IO1
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
11
10
9
8
7
6
5
4
3
2
1
0
G4_IO4 G4_IO3 G4_IO2 G4_IO1 G3_IO4 G3_IO3 G3_IO2 G3_IO1 G2_IO4 G2_IO3 G2_IO2 G2_IO1 G1_IO4 G1_IO3 G1_IO2 G1_IO1
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:28 Reserved, must be kept at reset value.
Bits 27:0 Gx_IOy: Gx_IOy sampling mode
These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor
I/O. Only one I/O per analog I/O group must be defined as sampling capacitor.
0: Gx_IOy unused
1: Gx_IOy used as sampling capacitor
Note: These bits must not be modified when an acquisition is ongoing.
During the acquisition phase and even if the TSC peripheral alternate function is not
enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch
is automatically controlled by the touch sensing controller.
20.7.8
TSC I/O channel control register (TSC_IOCCR)
Address offset: 0x28
Reset value: 0x0000 0000
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
27
26
25
24
23
22
21
20
19
18
17
16
G7_IO4 G7_IO3 G7_IO2 G7_IO1 G6_IO4 G6_IO3 G6_IO2 G6_IO1 G5_IO4 G5_IO3 G5_IO2 G5_IO1
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
11
10
9
8
7
6
5
4
3
2
1
0
G4_IO4 G4_IO3 G4_IO2 G4_IO1 G3_IO4 G3_IO3 G3_IO2 G3_IO1 G2_IO4 G2_IO3 G2_IO2 G2_IO1 G1_IO4 G1_IO3 G1_IO2 G1_IO1
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:28 Reserved, must be kept at reset value.
Bits 27:0 Gx_IOy: Gx_IOy channel mode
These bits are set and cleared by software to configure the Gx_IOy as a channel I/O.
0: Gx_IOy unused
1: Gx_IOy used as channel
Note: These bits must not be modified when an acquisition is ongoing.
During the acquisition phase and even if the TSC peripheral alternate function is not
enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch
is automatically controlled by the touch sensing controller.
480/1325
RM0503 Rev 2
RM0503
Touch sensing controller (TSC)
20.7.9
TSC I/O group control status register (TSC_IOGCSR)
Address offset: 0x30
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
G7S
G6S
G5S
G4S
G3S
G2S
G1S
r
r
r
r
r
r
r
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
G7E
G6E
G5E
G4E
G3E
G2E
G1E
rw
rw
rw
rw
rw
rw
rw
Bits 31:23 Reserved, must be kept at reset value.
Bits 22:16 GxS: Analog I/O group x status
These bits are set by hardware when the acquisition on the corresponding enabled analog
I/O group x is complete. They are cleared by hardware when a new acquisition is started.
0: Acquisition on analog I/O group x is ongoing or not started
1: Acquisition on analog I/O group x is complete
Note: When a max count error is detected the remaining GxS bits of the enabled analog I/O
groups are not set.
Bits 15:7 Reserved, must be kept at reset value.
Bits 6:0 GxE: Analog I/O group x enable
These bits are set and cleared by software to enable/disable the acquisition (counter is
counting) on the corresponding analog I/O group x.
0: Acquisition on analog I/O group x disabled
1: Acquisition on analog I/O group x enabled
20.7.10
TSC I/O group x counter register (TSC_IOGxCR)
x represents the analog I/O group number.
Address offset: 0x30 + 0x04 * x, (x = 1 to 7)
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
r
r
r
r
r
r
CNT[13:0]
r
r
r
r
r
r
r
r
Bits 31:14 Reserved, must be kept at reset value.
Bits 13:0 CNT[13:0]: Counter value
These bits represent the number of charge transfer cycles generated on the analog I/O
group x to complete its acquisition (voltage across CS has reached the threshold).
RM0503 Rev 2
481/1325
483
0x0038
482/1325
TSC_IOG2CR
Reset value
RM0503 Rev 2
Res.
Res.
Res.
Res.
G7E
G5_IO2
G5_IO1
G4_IO4
G4_IO3
G4_IO2
G4_IO1
G3_IO4
G3_IO3
G3_IO2
G3_IO1
G2_IO4
G2_IO3
G2_IO2
G2_IO1
G1_IO4
G1_IO3
G1_IO2
G1_IO1
G5_IO4
G5_IO3
G5_IO2
G5_IO1
G4_IO4
G4_IO3
G4_IO2
G4_IO1
G3_IO4
G3_IO3
G3_IO2
G3_IO1
G2_IO4
G2_IO3
G2_IO2
G2_IO1
G1_IO4
G1_IO3
G1_IO2
G1_IO1
G6_IO2
G6_IO1
G5_IO4
G5_IO3
G5_IO2
G5_IO1
G4_IO4
G4_IO3
G4_IO2
G4_IO1
G3_IO4
G3_IO3
G3_IO2
G3_IO1
G2_IO4
G2_IO3
G2_IO2
G2_IO1
G1_IO4
G1_IO3
G1_IO2
G1_IO1
G6_IO3
G6_IO2
G6_IO1
G5_IO4
G5_IO3
G5_IO2
G5_IO1
G4_IO4
G4_IO3
G4_IO2
Reset value
G4_IO1
0
0
G3_IO4
G3_IO3
G3_IO2
G3_IO1
G2_IO4
G2_IO3
G2_IO2
G2_IO1
G1_IO4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CNT[13:0]
CNT[13:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
G1_IO3
G1_IO2
G1_IO1
Reset value
Reset value
EOAIC
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
TSCE
0
0
0
EOAIE
AM
Res.
START
Res.
0
Res.
Res.
IODEF
Res.
Res.
Res.
Res.
Res.
SYNCPOL
Res.
Res.
Res.
Res.
PGPSC[2:0]
0
MCEIE
Reset value
EOAF
Res.
Res.
0
MCEIC
Res.
0
Res.
Res.
0
MCEF
Res.
TSC_IER
Res.
0
Res.
0
MCV
[2:0]
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
SSE
SSPSC
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
G1E
Res.
G5_IO3
G6_IO1
G6_IO3
G6_IO4
Res.
Res.
0
G2E
Res.
G5_IO4
G6_IO2
G6_IO4
G7_IO1
Res.
Res.
0
G3E
Res.
G6_IO1
G6_IO3
G7_IO1
G7_IO2
Res.
Res.
Res.
Res.
Reset value
G4E
Res.
G6_IO2
G6_IO4
G7_IO2
G7_IO3
Res.
Res.
Res.
Res.
Res.
CTPL[3:0]
G5E
Res.
G6_IO3
G7_IO1
G7_IO3
G7_IO4
Res.
Res.
Res.
Res.
CTPH[3:0]
G6E
Res.
Res.
Res.
G1S
0
Res.
G2S
0
Res.
0x002C
Res.
G3S
0
Res.
G6_IO4
G7_IO2
G7_IO4
Res.
Res.
Res.
Res.
TSC_CR
SSD[6:0]
Res.
G4S
0
Res.
G7_IO1
0x0024
Res.
G5S
0
Res.
G7_IO2
G7_IO3
0x001C
Res.
G6S
0
Res.
G7_IO3
G7_IO4
Res.
Res.
Res.
Res.
0x0014
Res.
Res.
Res.
G7S
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
G7_IO4
Reset value
Res.
Res.
Res.
Reset value
Res.
Res.
Reset value
Res.
TSC_IOG1CR
Res.
Reset value
Res.
0x0034
TSC_IOGCSR
Res.
0x0030
TSC_IOCCR
Res.
0x0028
TSC_IOSCR
Res.
0x0020
TSC_IOASCR
Res.
0x0018
TSC_IOHCR
Res.
0x0010
TSC_ISR
Res.
0x000C
TSC_ICR
Res.
0x0008
Res.
0x0004
Res.
0x0000
Res.
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Register
name
Res.
20.7.11
Res.
Touch sensing controller (TSC)
RM0503
TSC register map
Table 109. TSC register map and reset values
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Reserved
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reserved
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reserved
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reserved
RM0503
Touch sensing controller (TSC)
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
TSC_IOG3CR
Res.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x003C
Register
name
Res.
Offset
Res.
Table 109. TSC register map and reset values (continued)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CNT[13:0]
0
Reset value
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
TSC_IOG7CR
0
CNT[13:0]
0
Reset value
0x004C
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
TSC_IOG6CR
0
CNT[13:0]
0
Reset value
0x0048
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
TSC_IOG5CR
0
CNT[13:0]
0
Reset value
0x0044
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
TSC_IOG4CR
Res.
Reset value
0x0040
CNT[13:0]
0
0
0
0
0
0
0
0
Refer to Section 2.2 on page 55 for the register boundary addresses.
RM0503 Rev 2
483/1325
483
True random number generator (RNG)
RM0503
21
True random number generator (RNG)
21.1
Introduction
The RNG is a true random number generator that provides full entropy outputs to the
application as 32-bit samples. It is composed of a live entropy source (analog) and an
internal conditioning component.
The RNG is a NIST SP 800-90B compliant entropy source that can be used to construct a
nondeterministic random bit generator (NDRBG).
The RNG true random number generator can be certified NIST SP800-90B. It can also be
tested using the German BSI statistical tests of AIS-31 (T0 to T8).
21.2
484/1325
RNG main features
•
The RNG delivers 32-bit true random numbers, produced by an analog entropy source
conditioned by a NIST SP800-90B approved conditioning stage.
•
It can be used as the entropy source to construct a nondeterministic random bit
generator (NDRBG).
•
In the NIST configuration, it produces four 32-bit random samples every 412 AHB clock
cycles if fAHB < fthreshold (256 RNG clock cycles otherwise).
•
It embeds startup and NIST SP800-90B approved continuous health tests (repetition
count and adaptive proportion tests), associated with specific error management
•
It can be disabled to reduce power consumption, or enabled with an automatic low
power mode (default configuration).
•
It has an AMBA® AHB slave peripheral, accessible through 32-bit word single
accesses only (else an AHB bus error is generated, and the write accesses are
ignored).
RM0503 Rev 2
RM0503
True random number generator (RNG)
21.3
RNG functional description
21.3.1
RNG block diagram
Figure 92 shows the RNG block diagram.
Figure 92. RNG block diagram
True RNG
Banked Registers
4x32-bit
FIFO
RNG_CR
32-bit AHB bus
rng_hclk
CONDRST
RNG_DR
AHB
interface
Alarms
RNG_SR
Fault detection
Clock checker
Health tests
AHB clock domain
1-bit
Post-processing (optional)
DIV
rng_clk
Conditioning logic
128-bit data output
rng_it
Sampling (x N) + XOR
RNG clock domain
rng_itamp_out
en_osc
Analog
Analog ... Analog
noise
noise
noise
source 1 source 2
source N
Analog noise source
MSv42098V3
21.3.2
RNG internal signals
Table 110 describes a list of useful-to-know internal signals available at the RNG level, not
at the STM32 product level (on pads).
Table 110. RNG internal input/output signals
Signal name
Signal type
rng_it
Digital output
RNG global interrupt request
rng_hclk
Digital input
AHB clock
rng_clk
Digital input
RNG dedicated clock, asynchronous to rng_hclk
digital output
RNG internal tamper event signal to TAMP (XORed),
triggered when an unexpected hardware fault
occurs. When this signal is triggered, RNG stops
delivering random samples, requiring a reset and a
new initialization to be usable again.
rng_itamp_out
Description
RM0503 Rev 2
485/1325
501
True random number generator (RNG)
21.3.3
RM0503
Random number generation
The true random number generator (RNG) delivers truly random data through its AHB
interface at deterministic intervals.
Within its boundary RNG integrates all the required NIST components depicted on
Figure 93. Those components are an analog noise source, a digitization stage, a
conditioning algorithm, a health monitoring block and two interfaces that are used to interact
with the entropy source: GetEntropy and HealthTest.
Figure 93. NIST SP800-90B entropy source model
Error
message
(HealthTest)
Heath
tests
Output
(GetEntropy)
Conditioning
(optional)
Raw data
Post-processing
(optional)
Digitization
Noise Source
Entropy source
MSv44200V3
The components pictured above are detailed hereafter.
Noise source
The noise source is the component that contains the non-deterministic, entropy-providing
activity that is ultimately responsible for the uncertainty associated with the bitstring output
by the entropy source. This noise source provides 1-bit samples. It is composed of:
•
Multiple analog noise sources (x6), each based on three XORed free-running ring
oscillator outputs. It is possible to disable those analog oscillators to save power, as
described in Section 21.3.8: RNG low-power use. Multiple oscillators are also disabled
for the configuration A (see Table 113: RNG configurations).
•
The XORing of all the noise sources into a single analog output.
•
A sampling stage of this output clocked by a dedicated clock input (rng_clk with
integrated divider), delivering a 1-bit raw data output.
This noise source sampling is independent to the AHB interface clock frequency (rng_hclk),
with a possibility for the software to decrease the sampling frequency by using the
integrated divider.
Note:
486/1325
In Section 21.6: RNG entropy source validation the recommended RNG clock frequencies
and associated divider value are given.
RM0503 Rev 2
RM0503
True random number generator (RNG)
Post processing
In the NIST configuration no post-processing is applied to the sampled noise source. In nonNIST configuration B (as defined in Section 21.6.2) a normalization debiasing is applied,
that is half of the bits are taken from the sampled noise source, half of the bits are taken
from the inverted sampled noise source.
Conditioning
The conditioning component in the RNG is a deterministic function that increases the
entropy rate of the resulting fixed-length bitstrings output (128-bit). The NIST SP800-90B
target is full entropy on the output (128-bit).
The times required between two random number generations, and between the RNG
initialization and availability of first sample are described in Section 21.5: RNG processing
time.
Output buffer
A data output buffer can store up to four 32-bit words that have been output from the
conditioning component. When four words have been read from the output FIFO through
the RNG_DR register, the content of the 128-bit conditioning output register is pushed into
the output FIFO, and a new conditioning round is automatically started. Four new words are
added to the conditioning output register after a number of clock cycles specified in
Section 21.5: RNG processing time.
Whenever a random number is available through the RNG_DR register, the DRDY flag
changes from 0 to 1. This flag remains high until the output buffer becomes empty after
reading four words from the RNG_DR register.
Note:
When interrupts are enabled an interrupt is generated when this data ready flag transitions
from 0 to 1. Interrupt is then cleared automatically by the RNG as explained above.
RM0503 Rev 2
487/1325
501
True random number generator (RNG)
RM0503
Health checks
This component ensures that the entire entropy source (with its noise source) starts then
operates as expected, obtaining assurance that failures are caught quickly and with a high
probability and reliability.
The RNG implements the following health check features in accordance with NIST
SP800-90B. The described thresholds correspond to the value recommended for register
RNG_HTCR (configuration A in Section 21.6.2).
1.
2.
3.
4.
Startup health tests, performed after reset and before the first use of the RNG as
entropy source:
–
Repetition count test, flagging an error when the noise source has provided more
than 42 consecutive bits at a constant value (0 or 1).
–
Adaptive proportion test running on a window of 1024 consecutive bits: the RNG
verifies that the first bit on the outputs of the noise source is not repeated more
than 711 times.
–
Known-answer tests, to verify the conditioning stage.
Continuous health tests, running indefinitely on the outputs of the noise source:
–
Repetition count test, similar to the one running in startup tests.
–
Adaptive proportion test, similar to the one running in startup tests.
Vendor specific continuous tests
–
Transition count test, flagging an error when the noise source has delivered more
than 32 consecutive occurrences of 2-bit patterns (01 or 10).
–
Real-time “too slow” sampling clock detector, flagging an error when one RNG
clock cycle (before divider) is smaller than AHB clock cycle divided by 32.
On-demand test of digitized noise source (raw data)
–
Supported by restarting the entropy source and rerunning the startup tests (see
software reset sequence in Section 21.3.4: RNG initialization). Other kinds of
on-demand testing (software based) are not supported.
The CECS and SECS status bits in the RNG_SR register indicate when an error condition is
detected, as detailed in Section 21.3.7: Error management.
Note:
An interrupt can be generated when an error is detected.
Above the health test thresholds are modified by changing the value in the RNG_HTCR
register. See Section 21.6: RNG entropy source validation for details.
488/1325
RM0503 Rev 2
RM0503
21.3.4
True random number generator (RNG)
RNG initialization
The RNG simplified state machine is pictured on Figure 94.
After enabling the RNG (RNGEN = 1 in RNG_CR), the following chain of events occurs:
1.
The analog noise source is enabled, and by default the RNG waits 16 cycles of RNG
clock cycles (before divider) before starting to sample the analog output and filling the
128-bit conditioning shift register.
2.
The conditioning hardware initializes, automatically triggering startup behavior test on
the raw data samples and known-answer tests.
3.
When startup health tests are completed. During this time, three 128-bit noise source
samples are used.
4.
The conditioning stage internal input data buffer is filled again with 128-bit and a
number of conditioning rounds defined by the RNG configuration (NIST or non-NIST) is
performed. The output buffer is then filled with the post processing result.
5.
The output buffer is refilled automatically according to the RNG usage.
The associated initialization time can be found in Section 21.5: RNG processing time.
Figure 94. RNG initialization overview
1
Wait for noise
source
Software reset
2
Software reset
Start-up heath tests
Error state
start-up test(s)
not OK
3
Conditioning keys
init
continuous test(s)
not OK
4
Generate samples
5
MSv44204V2
RM0503 Rev 2
489/1325
501
True random number generator (RNG)
RM0503
Figure 94 also highlights a possible software reset sequence, implemented by:
1.
Writing bits RNGEN = 0 and CONDRST = 1 in the RNG_CR register with the same
RNG configuration and a new CLKDIV if needed.
2.
Then writing RNGEN = 1 and CONDRST = 0 in the RNG_CR register.
3.
Wait for random number to be ready, after initialization completes.
Note:
When the RNG peripheral is reset through RCC (hardware reset), the RNG configuration for
optimal randomness is lost in the RNG registers. Software reset with CONFIGLOCK set
preserves the RNG configuration.
21.3.5
RNG operation
Normal operations
To run the RNG using interrupts, the following steps are recommended:
1.
2.
Consult Section 21.6: RNG entropy source validation and verify if a specific RNG
configuration is required for the application.
–
If it is the case, write in the RNG_CR register the bit CONDRST = 1 together with
the correct RNG configuration. Then perform a second write to the RNG_CR
register with the bit CONDRST = 0, the interrupt enable bit IE = 1 and the RNG
enable bit RNGEN = 1.
–
If it is not the case perform a write to the RNG_CR register with the interrupt
enable bit IE = 1 and the RNG enable bit RNGEN = 1.
An interrupt is now generated when a random number is ready or when an error
occurs. Therefore, at each interrupt, check that:
–
No error occurred. The SEIS and CEIS bits must be set to 0 in the RNG_SR
register.
–
A random number is ready. The DRDY bit must be set to 1 in the RNG_SR
register.
–
If the above two conditions are true the content of the RNG_DR register can be
read up to four consecutive times. If valid data is available in the conditioning
output buffer, four additional words can be read by the application (in this case the
DRDY bit is still high). If one or both of the above conditions are false, the
RNG_DR register must not be read. If an error occurred, the error recovery
sequence described in Section 21.3.7 must be used.
To run the RNG in polling mode following steps are recommended:
1.
2.
3.
490/1325
Consult Section 21.6: RNG entropy source validation and verify if a specific RNG
configuration is required for the application.
–
If it is the case write in the RNG_CR register the bit CONDRST = 1 together with
the correction RNG configuration. Then perform a second write to the RNG_CR
register with the bit CONDRST = 0 and the RNG enable bit RNGEN = 1.
–
If it is not the case only enable the RNG by setting the RNGEN bit to 1 in the
RNG_CR register.
Read the RNG_SR register and check that:
–
No error occurred (the SEIS and CEIS bits must be set to 0)
–
A random number is ready (the DRDY bit must be set to 1)
If above conditions are true read the content of the RNG_DR register up to four
consecutive times. If valid data is available in the conditioning output buffer four
RM0503 Rev 2
RM0503
True random number generator (RNG)
additional words can be read by the application (in this case the DRDY bit is still high).
If one or both of the above conditions are false, the RNG_DR register must not be read.
If an error occurred, the error recovery sequence described in Section 21.3.7 must be
used.
Note:
When data is not ready (DRDY = 0) RNG_DR returns zero.
It is recommended to always verify that RNG_DR is different from zero. Because when it is
the case a seed error occurred between RNG_SR polling and RND_DR output reading (rare
event).
If the random number generation period is a concern to the application and if NIST
compliance is not required it is possible to select a faster RNG configuration by using the
RNG configuration “B”, described in Section 21.6: RNG entropy source validation. The gain
in random number generation speed is summarized in Section 21.5: RNG processing time.
Low-power operations
If the power consumption is a concern to the application, low-power strategies can be used,
as described in Section 21.3.8: RNG low-power use.
Software post-processing
No specific software post-processing/conditioning is expected to meet the AIS-31 or NIST
SP800-90B approvals.
Built-in health check functions are described in Section 21.3.3: Random number generation.
21.3.6
RNG clocking
The RNG runs on two different clocks: the AHB bus clock and a dedicated RNG clock.
The AHB clock is used to clock the AHB banked registers and conditioning component. The
RNG clock, coupled with a programmable divider (see CLKDIV bitfield in the RNG_CR
register) is used for noise source sampling. Recommended clock configurations are detailed
in Section 21.6: RNG entropy source validation.
Note:
When the CED bit in the RNG_CR register is set to 0, the RNG clock frequency before the
internal divider must be higher than the AHB clock frequency divided by 32, otherwise the
clock checker always flags a clock error (CECS = 1 in the RNG_SR register).
See Section 21.3.1: RNG block diagram for details (AHB and RNG clock domains).
21.3.7
Error management
In parallel to random number generation a health check block verifies the correct noise
source behavior and the frequency of the RNG source clock as detailed in this section.
Associated error state is also described.
Clock error detection
When the clock error detection is enabled (CED = 0) and if the RNG clock frequency is too
low, the RNG sets to 1 both the CEIS and CECS bits to indicate that a clock error occurred.
In this case, the application must check that the RNG clock is configured correctly (see
Section 21.3.6: RNG clocking) and then it must clear the CEIS bit interrupt flag. The CECS
bit is automatically cleared when the clocking condition is normal.
RM0503 Rev 2
491/1325
501
True random number generator (RNG)
Note:
RM0503
The clock error has no impact on generated random numbers that is the application can still
read the RNG_DR register.
CEIS is set only when CECS is set to 1 by RNG.
Noise source error detection
When a noise source (or seed) error occurs, the RNG stops generating random numbers
and sets to 1 both SEIS and SECS bits to indicate that a seed error occurred. If a value is
available in the RNG_DR register, it must not be used as it may not have enough entropy.
The following sequence must be used to fully recover from a seed error:
Note:
1.
Software reset by writing CONDRST at 1 and at 0 (see bitfield description for details).
This step is needed only if SECS is set. Indeed, when SEIS is set and SECS is cleared
it means RNG performed the reset automatically (auto-reset). In this case application
must clear the SEIS bit interrupt flag.
2.
If SECS was set in step 1 (no auto-reset) wait for CONDRST to be cleared in the
RNG_CR register, then confirm that SEIS is cleared in the RNG_SR register.
Otherwise, just clear the SEIS bit in the RNG_SR register.
3.
If SECS was set in step 1 (no auto-reset), wait for SECS to be cleared by RNG. The
random number generation is now back to normal.
After a seed error RNG restarts generating random numbers when SECS is cleared.
When the application sets the ARDIS bit in the RNG_CR register, the auto-reset is disabled.
CONDRST must be used in step 1.
RNG tamper errors
When an unexpected error is found by the RNG an internal tamper event is triggered in the
TAMP peripheral, and the RNG stops delivering random data.
When this event occurs, the secure application needs to reset the RNG peripheral either
using the central reset management or the global SoC reset. Then a proper initialization of
the RNG is required, again.
21.3.8
RNG low-power use
If power consumption is a concern, the RNG can be disabled as soon as the DRDY bit is set
to 1 by setting the RNGEN bit to 0 in the RNG_CR register. As the post-processing logic and
the output buffer remain operational while RNGEN = 0 following features are available to
the software:
•
If there are valid words in the output buffer four random numbers can still be read from
the RNG_DR register.
•
If there are valid bits in the conditioning output internal register four additional random
numbers can be still be read from the RNG_DR register. If it is not the case RNG must
be reenabled by the application until the expected new noise source bits threshold is
reached (128-bit in NIST mode) and a complete conditioning round is done.
Four new random words are then available only if the expected number of conditioning
round is reached (two if NISTC = 0). The overall time can be found in Section 21.5:
RNG processing time on page 494.
When disabling the RNG the user deactivates all the analog seed generators, whose power
consumption is given in the datasheet electrical characteristics section. The user also gates
492/1325
RM0503 Rev 2
RM0503
True random number generator (RNG)
all the logic clocked by the RNG clock. Note that this strategy is adding latency before a
random sample is available on the RNG_DR register, because of the RNG initialization time.
If the RNG block is disabled during initialization (that is well before the DRDY bit rises for the
first time), the initialization sequence resumes from where it was stopped when RNGEN bit
is set to 1, unless the application resets the conditioning logic using CONDRST bit in the
RNG_CR register.
When the application wants to disable the RNG clock it is recommended to wait two RNG
kernel clock cycles between clearing the RNGEN bit and disabling the RNG kernel clock
using the RCC.
Also, when application needs to enter a power mode where RNG is de-activated, it is
recommended to wait two RNG kernel clock cycles between clearing the RNGEN bit and
entering the low power mode using the PWR.
In the two cases above, to avoid unexpected consumption when RNG analog oscillators
stay active, application can set the bit 13 in RNG_CR register. Setting this bit adds some
marginal power consumption while RNGEN bit is set (RNG activated).
Note:
The power modes where RNG is deactivated (that is retained or not available) can be found
in the PWR section.
21.4
RNG interrupts
In the RNG an interrupt can be produced on the following events:
•
Data ready flag
•
Seed error, see Section 21.3.7: Error management
•
Clock error, see Section 21.3.7: Error management
Dedicated interrupt enable control bits are available as shown in Table 111.
Table 111. RNG interrupt requests
Interrupt acronym
RNG
Interrupt event
Event flag
Enable control bit
Interrupt clear method
Data ready flag
DRDY
IE
None (automatic)
Seed error flag
SEIS
IE
Write CONDRST to 1 then to 0
unless ARDIS is cleared (see
Section 21.3.7: Error
management)
Clock error flag
CEIS
IE
Write 0 to CEIS
The user can enable or disable the above interrupt sources individually by changing the
mask bits or the general interrupt control bit IE in the RNG_CR register. The status of the
individual interrupt sources can be read from the RNG_SR register.
Note:
Interrupts are generated only when RNG is enabled.
RM0503 Rev 2
493/1325
501
True random number generator (RNG)
21.5
RM0503
RNG processing time
In recommended configuration A or C described in Table 113, the time between two sets of
four 32-bit data is either:
•
203 x N AHB cycles if fAHB < fthreshold (conditioning stage is limiting), or
•
128 x N RNG cycles fAHB ≥ fthreshold (noise source stage is limiting).
With fthreshold = 1.6 x fRNG, for instance 77 MHz if fRNG= 48 MHz. Value N is defined in
Section 21.6: RNG entropy source validation.
Note:
When CLKDIV is different from zero, fRNG must take into account the internal divider ratio.
If configuration B is selected the performance figures become:
•
203 AHB cycles if fAHB < fthreshold or
•
32 RNG cycles fAHB ≥ fthreshold
with fthreshold = 6.5 x fRNG.
Initialization time
More time is needed for the first set of random numbers after the device exits reset (see
Section 1.3.4: RNG initialization). Table below gives details on how to compute the time
spent in each initialization step.
Table 112. RNG initialization times
Initialization step
Configuration A or C, reset value
Configuraton B
Wait for noise
source, then startup
health tests
Max( (wait_noise(1) + 11 + 1024 x CLKDIV)
RNG_cycles, 13 x 203 AHB_cycles)
Max(16 + 1035 RNG_cycles,
13 x 203 AHB_cycles)
Conditioning keys
initialization
Max((1+2xN) x 128 x CLKDIV) RNG_cycles
Max (3 x 32 RNG_cycles + 203 AHB_cycles,
+ 203 AHB_cycles, (128 x CLKDIV)
32 RNG_cycles + 4 x 203 AHB_cycles)
RNG_cycles + (2xN+2) x 203 AHB_cycles)
1. 192 RNG_cycles (configuration A or C), 16 RNG_cycles (reset value)
As an example, if AHB clock= 54 MHz and RNG clock= 48 MHz then the initialization time is
around 79 μs in the configuration C (CLKDIV=1, N=2) and 66 μs in the configuration B.
21.6
RNG entropy source validation
21.6.1
Introduction
In order to assess the amount of entropy available from the RNG, STMicroelectronics has
tested the peripheral using the German BSI AIS-31 statistical tests (T0 to T8), and NIST
SP800-90B test suite.
494/1325
RM0503 Rev 2
RM0503
21.6.2
True random number generator (RNG)
Validation conditions
STMicroelectronics has tested the RNG true random number generator in the following
conditions:
•
RNG clock rng_clk = 48 MHz
•
RNG configurations are described in Table 113. Note that only configuration A can be
certified NIST SP800-90B. Refer to Table 114 to select the best configuration for the
application.
•
Configuration C can be used when configuration A is not flagged as certified.
Table 113. RNG configurations
RNG_CR bits
Configuration
NISTC
bit
RNG_
CONFIG1
[5:0]
CLKDIV
[3:0]
RNG_
CONFIG2
[2:0](1)
RNG_
CONFIG3
[3:0](2)
Loop
number
CED
(N)
bit
RNG_
HTCR
register
RNG_
NCSR
register
A
Refer to NIST compliant RNG configuration table in AN4230 available from www.st.com.
This application note also indicates if this configuration is part of an existing NIST SP800-90B
Entropy Certificate listed on https://csrc.nist.gov/projects/cryptographic-module-validationprogram.
B
1
0x18
C
0
0x0F
0x0(3)
0x0
0x0
0
1
0x0
0xD
0
2
0x0000
AAC7(4)
default
default
1. 0x1 value is recommended instead of 0x0 for RNG_CONFIG2[2:0], when RNG power consumption is critical. See the end
of Section 21.3.8: RNG low-power use for details.
2. RNG_CONFIG3[1:0] defines the loop number N: 0x0 corresponds to N=1, 0x1 to N=2, 0x2 to N=3, 0x3 to N=4
3. The noise source sampling must be 48 MHz or less. Hence, if the RNG clock is different from 48 MHz, this value of CLKDIV
must be adapted. See the CLKDIV bitfield description in Section 21.7.1 for details.
4. This value can be fixed in the RNG driver (it doesn’t depend on the STM32 family).
Table 114. Configuration selection
Section criteria
Config A
Config B
Config C
Suitable to generate NIST
compliant cryptographic keys
Yes
Entropy(1)
Certified
Good
Very good
Speed(2)
Baseline
Faster
Baseline
No
1. For configurations B and C entropy is verified using AIS-31 test suite (T0 to T8).
2. When speed is not enough for application a NIST compliant DRBG can be used to increase throughput.
For details on data collection and the running of statistical test suites refer to “STM32
microcontrollers random number generation validation using NIST statistical test suite”
application note (AN4230) available from www.st.com.
RM0503 Rev 2
495/1325
501
True random number generator (RNG)
21.7
RM0503
RNG registers
The RNG is associated with a control register, a data register and a status register.
21.7.1
RNG control register (RNG_CR)
Address offset: 0x000
Reset value: 0x0080 0D00
31
30
CONFI COND
GLOCK RST
rs
rw
15
14
29
28
27
26
Res.
Res.
Res.
Res.
13
RNG_CONFIG2[2:0]
rw
rw
rw
12
11
NISTC
rw
10
25
24
rw
22
21
20
19
RNG_CONFIG1[5:0]
rw
rw
9
8
RNG_CONFIG3[3:0]
rw
23
rw
rw
rw
rw
18
17
16
CLKDIV[3:0]
rw
rw
rw
rw
rw
rw
7
6
5
4
3
2
1
0
ARDIS
Res.
CED
Res.
IE
RNGEN
Res.
Res.
rw
rw
rw
rw
Bit 31 CONFIGLOCK: RNG Config lock
0: Writes to the RNG_NSCR, RNG_HTCR and RNG_CR configuration bits [29:4] are
allowed.
1: Writes to the RNG_NSCR, RNG_HTCR and RNG_CR configuration bits [29:4] are
ignored until the next RNG reset.
Once set, this bit can only be cleared when RNG is reset (set once bit).
Bit 30 CONDRST: Conditioning soft reset
Write 1 and then write 0 to reset the conditioning logic, clear all the FIFOs and start a new
RNG initialization process, with RNG_SR cleared. Registers RNG_CR, RNG_NSCR and
RNG_HTCR are not changed by CONDRST.
This bit must be set to 1 in the same access that set any configuration bits [29:4]. In other
words, when CONDRST bit is set to 1 correct configuration in bits [29:4] must also be
written.
When CONDRST is set to 0 by the software, its value goes to 0 when the reset process is
done. It takes about 2 AHB clock cycles + 2 RNG clock cycles.
Bits 29:26 Reserved, must be kept at reset value.
Bits 25:20 RNG_CONFIG1[5:0]: RNG configuration 1
Reserved to the RNG configuration (bitfield 1). Must be initialized using the recommended
value documented in Section 21.6: RNG entropy source validation.
Writing any bit of RNG_CONFIG1 is taken into account only if the CONDRST bit is set to 1 in
the same access, while CONFIGLOCK remains at 0. Writing to this bit is ignored if
CONFIGLOCK = 1.
Bits 19:16 CLKDIV[3:0]: Clock divider factor
This value used to configure an internal programmable divider (from 1 to 16) acting on the
incoming RNG clock. These bits can be written only when the core is disabled (RNGEN = 0).
0x0: internal RNG clock after divider is similar to incoming RNG clock.
0x1: two RNG clock cycles per internal RNG clock.
0x2: 22 (= 4) RNG clock cycles per internal RNG clock.
...
0xF: 215 RNG clock cycles per internal clock (for example. an incoming 48 MHz RNG clock
becomes a 1.5 kHz internal RNG clock)
Writing these bits is taken into account only if the CONDRST bit is set to 1 in the same
access, while CONFIGLOCK remains at 0. Writing to this bit is ignored if CONFIGLOCK = 1.
496/1325
RM0503 Rev 2
RM0503
True random number generator (RNG)
Bits 15:13 RNG_CONFIG2[2:0]: RNG configuration 2
Reserved to the RNG configuration (bitfield 2). Bit 13 can be set when RNG power
consumption is critical. See Section 21.3.8: RNG low-power use. Refer to the
RNG_CONFIG1 bitfield for details.
Bit 12 NISTC: NIST custom
0: Hardware default values for NIST compliant RNG. In this configuration per 128-bit output
two conditioning loops are performed and 256 bits of noise source are used.
1: Custom values for NIST compliant RNG. See Section 21.6: RNG entropy source
validation for recommended configuration.
Writing this bit is taken into account only if CONDRST bit is set to 1 in the same access,
while CONFIGLOCK remains at 0. Writing to this bit is ignored if CONFIGLOCK = 1.
Bits 11:8 RNG_CONFIG3[3:0]: RNG configuration 3
Reserved to the RNG configuration (bitfield 3). Refer to RNG_CONFIG1 bitfield for details.
If the NISTC bit is cleared in this register RNG_CONFIG3 bitfield values are ignored by
RNG.
Bit 7 ARDIS: Auto reset disable
Set this bit to deactivate the auto-reset feature.
0:">