STMicroelectronics STM32WLE5CC Reference Manual

RM0461
Reference manual
STM32WLEx advanced Arm®-based 32-bit MCUs
with sub-GHz radio solution
Introduction
This document is addressed to application developers. It provides complete information on
how to use the STM32WLEx microcontrollers memory and peripherals.
STM32WLEx MCUs with integrated sub-GHz radio operating in the 150 - 960 MHz ISM
band, belong to a family of microcontrollers with different memory sizes, packages and
peripherals.
For ordering information, mechanical and electrical device characteristics, refer to the
corresponding datasheets.
For information on the Arm® Cortex®-M4 core, refer to the corresponding Arm® Technical
Reference Manuals available on http://infocenter.arm.com.
STM32WLEx microcontrollers include ST state-of-the-art patented technology.
Related documents
• STM32WLE5xx STM32WLE4xx datasheet (DS13105)
For information on the device errata with respect to the datasheet and reference manual,
refer to the STM32WLE5xx STM32WLE4xx errata sheet (ES0506).
December 2024
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Contents
1
2
Documentation conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
1.1
General information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
1.2
List of abbreviations for registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
1.3
Register reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
1.4
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
1.5
Availability of peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Memory and bus architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
2.1
3
2.1.1
S0: CPU I-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
2.1.2
S1: CPU D-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
2.1.3
S2: CPU S-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
2.1.4
S4, S5: DMA-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
2.2
Boot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
2.3
SRAM erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
2.4
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
2.4.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
2.4.2
Memory map and register boundary addresses . . . . . . . . . . . . . . . . . . 63
2.4.3
CPU bit banding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Embedded flash memory (FLASH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.1
FLASH introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.2
FLASH main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.3
FLASH functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.4
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System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.3.1
Flash memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.3.2
Empty check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.3.3
Error code correction (ECC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
3.3.4
Read access latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
3.3.5
Adaptive real-time memory accelerator (ART Accelerator) . . . . . . . . . . 72
3.3.6
Flash program and erase operations . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
3.3.7
Flash main memory erase sequences . . . . . . . . . . . . . . . . . . . . . . . . . . 76
3.3.8
Flash main memory programming sequences . . . . . . . . . . . . . . . . . . . . 77
FLASH option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
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3.4.1
Option bytes description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
3.4.2
Option bytes programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Flash memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
3.5.1
Readout protection (RDP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
3.5.2
Proprietary code readout protection (PCROP) . . . . . . . . . . . . . . . . . . . 88
3.5.3
Write protection (WRP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
3.5.4
Security (ESE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
3.5.5
CPU boot lock chain of trust . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
3.6
FLASH program erase suspension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
3.7
FLASH interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
3.8
FLASH registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
3.8.1
FLASH access control register (FLASH_ACR) . . . . . . . . . . . . . . . . . . . 92
3.8.2
FLASH key register (FLASH_KEYR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
3.8.3
FLASH option key register (FLASH_OPTKEYR) . . . . . . . . . . . . . . . . . . 93
3.8.4
FLASH status register (FLASH_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
3.8.5
FLASH control register (FLASH_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . 96
3.8.6
FLASH ECC register (FLASH_ECCR) . . . . . . . . . . . . . . . . . . . . . . . . . 97
3.8.7
FLASH option register (FLASH_OPTR) . . . . . . . . . . . . . . . . . . . . . . . . 98
3.8.8
FLASH PCROP zone A start address register
(FLASH_PCROP1ASR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
3.8.9
FLASH PCROP zone A end address register
(FLASH_PCROP1AER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
3.8.10
FLASH WRP area A address register (FLASH_WRP1AR) . . . . . . . . . 101
3.8.11
FLASH WRP area B address register (FLASH_WRP1BR) . . . . . . . . . 102
3.8.12
FLASH PCROP zone B start address register
(FLASH_PCROP1BSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
3.8.13
FLASH PCROP zone B end address register
(FLASH_PCROP1BER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
3.8.14
FLASH register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Sub-GHz radio (SUBGHZ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
4.1
Sub-GHz radio introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
4.2
Sub-GHz radio main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
4.3
Sub-GHz radio functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
4.3.1
General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
4.3.2
Sub-GHz radio signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
4.3.3
Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
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4.4
4.5
4.6
4.7
4.8
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4.3.4
Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
4.3.5
RF-PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
4.3.6
Intermediate frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Sub-GHz radio clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
4.4.1
Internal oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
4.4.2
HSE32 reference clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Sub-GHz radio modems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
4.5.1
LoRa modem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
4.5.2
LoRa framing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
4.5.3
FSK modem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
4.5.4
MSK modem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
4.5.5
Generic framing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
4.5.6
BPSK modem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
4.5.7
BPSK framing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Sub-GHz radio data buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
4.6.1
Receive data buffer operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
4.6.2
Transmit data buffer operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Sub-GHz radio operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
4.7.1
Startup mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
4.7.2
Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
4.7.3
Calibration mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
4.7.4
Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
4.7.5
Frequency synthesis mode (FS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
4.7.6
Transmit mode (TX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
4.7.7
Receive mode (RX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
4.7.8
Active mode switching time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Sub-GHz radio SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
4.8.1
Sub-GHz radio command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
4.8.2
Register and buffer access commands . . . . . . . . . . . . . . . . . . . . . . . . 127
4.8.3
Operating mode commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
4.8.4
Sub-GHz radio configuration commands . . . . . . . . . . . . . . . . . . . . . . . 134
4.8.5
Communication status information commands . . . . . . . . . . . . . . . . . . 145
4.8.6
IRQ interrupt commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
4.8.7
Miscellaneous commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
4.8.8
Set_TcxoMode command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
4.8.9
Sub-GHz radio commands overview . . . . . . . . . . . . . . . . . . . . . . . . . . 154
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4.9
4.10
Sub-GHz radio application configuration . . . . . . . . . . . . . . . . . . . . . . . . 156
4.9.1
Basic sequence for LoRa, (G)MSK and (G)FSK transmit operation . . 156
4.9.2
Basic sequence for LoRa and (G)FSK receive operation . . . . . . . . . . 157
4.9.3
Basic sequence for BPSK transmit operation . . . . . . . . . . . . . . . . . . . 158
Sub-GHz radio registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
4.10.1
Sub-GHz radio ramp-up MSB register (SUBGHZ_RAM_RAMPUPH) 158
4.10.2
Sub-GHz radio ramp-up LSB register (SUBGHZ_RAM_RAMPUPL) . 159
4.10.3
Sub-GHz radio ramp-down MSB register
(SUBGHZ_RAM_RAMPDNH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
4.10.4
Sub-GHz radio ramp-down LSB register
(SUBGHZ_RAM_RAMPDNL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
4.10.5
Sub-GHz radio frame limit MSB register
(SUBGHZ_RAM_FRAMELIMH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
4.10.6
Sub-GHz radio frame limit LSB register
(SUBGHZ_RAM_FRAMELIML) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
4.10.7
Sub-GHz radio generic bit synchronization register
(SUBGHZ_GBSYNCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
4.10.8
Sub-GHz radio generic CFO MSB register (SUBGHZ_GCFORH) . . . 160
4.10.9
Sub-GHz radio generic CFO LSB register (SUBGHZ_GCFORL) . . . . 161
4.10.10 Sub-GHz radio generic packet control 1 register
(SUBGHZ_GPKTCTL1R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
4.10.11 Sub-GHz radio generic packet control 1A register
(SUBGHZ_GPKTCTL1AR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
4.10.12 Sub-GHz radio generic whitening LSB register
(SUBGHZ_GWHITEINIRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
4.10.13 Sub-GHz radio generic payload length register
(SUBGHZ_GRTXPLDLEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
4.10.14 Sub-GHz radio generic CRC initial MSB register
(SUBGHZ_GCRCINIRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
4.10.15 Sub-GHz radio generic CRC initial LSB register
(SUBGHZ_GCRCINIRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
4.10.16 Sub-GHz radio generic CRC polynomial MSB register
(SUBGHZ_GCRCPOLRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
4.10.17 Sub-GHz radio generic CRC polynomial LSB register
(SUBGHZ_GCRCPOLRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
4.10.18 Sub-GHz radio generic synchronization word control register 0
(SUBGHZ_GSYNCR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
4.10.19 Sub-GHz radio generic synchronization word control register 1
(SUBGHZ_GSYNCR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
4.10.20 Sub-GHz radio generic synchronization word control register 2
(SUBGHZ_GSYNCR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
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4.10.21 Sub-GHz radio generic synchronization word control register 3
(SUBGHZ_GSYNCR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
4.10.22 Sub-GHz radio generic synchronization word control register 4
(SUBGHZ_GSYNCR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
4.10.23 Sub-GHz radio generic synchronization word control register 5
(SUBGHZ_GSYNCR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
4.10.24 Sub-GHz radio generic synchronization word control register 6
(SUBGHZ_GSYNCR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
4.10.25 Sub-GHz radio generic synchronization word control register 7
(SUBGHZ_GSYNCR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
4.10.26 Sub-GHz radio generic node address register
(SUBGHZ_GNODEADR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
4.10.27 Sub-GHz radio generic broadcast address register
(SUBGHZ_GBCASTADDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
4.10.28 Sub-GHz radio generic AFC register (SUBGHZ_GAFCR) . . . . . . . . . 166
4.10.29 Sub-GHz radio LoRa payload length register
(SUBGHZ_LPLDLENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
4.10.30 Sub-GHz radio synchro timeout register
(SUBGHZ_LSYNCTIMEOUTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
4.10.31 Sub-GHz radio LoRa IQ polarity MSB register (SUBGHZ_LIQPOLR) 167
4.10.32 Sub-GHz radio LoRa IQ polarity LSB register (SUBGHZ_LIQPOLR) . 167
4.10.33 Sub-GHz radio LoRa synchronization word MSB register
(SUBGHZ_LSYNCRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
4.10.34 Sub-GHz radio LoRa synchronization word LSB register
(SUBGHZ_LSYNCRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
4.10.35 Sub-GHz radio Tx address pointer register (SUBGHZ_TXADRPTR) . 168
4.10.36 Sub-GHz radio Rx address pointer register
(SUBGHZ_RXADRPTRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
4.10.37 Sub-GHz radio bandwidth select register (SUBGHZ_BWSELR) . . . . . 169
4.10.38 Sub-GHz radio random number register 3 (SUBGHZ_RNGR3) . . . . . 169
4.10.39 Sub-GHz radio random number register 2 (SUBGHZ_RNGR2) . . . . . 169
4.10.40 Sub-GHz radio random number register 1 (SUBGHZ_RNGR1) . . . . . 169
4.10.41 Sub-GHz radio random number register 0 (SUBGHZ_RNGR0) . . . . . 170
4.10.42 Sub-GHz radio SD resolution register (SUBGHZ_SDCFG0R) . . . . . . 170
4.10.43 Sub-GHz radio AGC RSSI control register
(SUBGHZ_AGCRSSICTL0R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
4.10.44 Sub-GHz radio receiver gain control register (SUBGHZ_RXGAINCR) 170
4.10.45 Sub-GHz radio AGC reset configuration register
(SUBGHZ_AGCGFORSTCFGR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
4.10.46 Sub-GHz radio AGC reset power threshold register
(SUBGHZ_AGCGFORSTPOWTHR) . . . . . . . . . . . . . . . . . . . . . . . . . . 171
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4.10.47 Sub-GHz radio Tx clamp register (SUBGHZ_TXCLAMPR) . . . . . . . . . 171
4.10.48 Sub-GHz radio disable LNA register (REG_ANA_LNA) . . . . . . . . . . . 172
4.10.49 Sub-GHz radio disable mixer register (REG_ANA_MIXER) . . . . . . . . 172
4.10.50 Sub-GHz radio PA over current protection register
(SUBGHZ_PAOCPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
4.10.51 Sub-GHz radio RTC control register (SUBGHZ_RTCCTLR) . . . . . . . . 172
4.10.52 Sub-GHz radio RTC period MSB register (SUBGHZ_RTCPRDR2) . . 173
4.10.53 Sub-GHz radio RTC period mid-byte register
(SUBGHZ_RTCPRDR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
4.10.54 Sub-GHz radio RTC period LSB register (SUBGHZ_RTCPRDR0) . . . 173
4.10.55 Sub-GHz radio HSE32 OSC_IN capacitor trim register
(SUBGHZ_HSEINTRIMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
4.10.56 Sub-GHz radio HSE32 OSC_OUT capacitor trim register
(SUBGHZ_HSEOUTTRIMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
4.10.57 Sub-GHz radio SMPS control 0 register (SUBGHZ_SMPSC0R) . . . . 175
4.10.58 Sub-GHz radio power control register (SUBGHZ_PCR) . . . . . . . . . . . 175
4.10.59 Sub-GHz radio regulator drive control register
(SUBGHZ_REGDRVCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
4.10.60 Sub-GHz radio SMPS control 2 register (SUBGHZ_SMPSC2R) . . . . 176
4.10.61 Sub-GHz radio register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
5
Power control (PWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
5.1
5.2
Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
5.1.1
Independent analog peripherals supply . . . . . . . . . . . . . . . . . . . . . . . . 182
5.1.2
Battery backup domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
5.1.3
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
5.1.4
Dynamic voltage scaling management . . . . . . . . . . . . . . . . . . . . . . . . 184
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
5.2.1
Power-on reset (POR)/power-down reset (PDR)
/Brownout reset (BOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
5.2.2
Programmable voltage detector (PVD) . . . . . . . . . . . . . . . . . . . . . . . . 186
5.2.3
Peripheral voltage monitoring (PVM) . . . . . . . . . . . . . . . . . . . . . . . . . . 187
5.2.4
Radio end of life (EOL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
5.3
Radio busy management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
5.4
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
5.4.1
Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
5.4.2
Low-power run mode (LPRun) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
5.4.3
Enter low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
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5.5
6
Exit low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
5.4.5
Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
5.4.6
Low-power sleep mode (LPSleep) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
5.4.7
Stop 0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
5.4.8
Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
5.4.9
Stop 2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
5.4.10
Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
5.4.11
Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
5.4.12
Auto-wake-up from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . 208
PWR registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
5.5.1
PWR control register 1 (PWR_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . 209
5.5.2
PWR control register 2 (PWR_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 211
5.5.3
PWR control register 3 (PWR_CR3) . . . . . . . . . . . . . . . . . . . . . . . . . . 211
5.5.4
PWR control register 4 (PWR_CR4) . . . . . . . . . . . . . . . . . . . . . . . . . . 213
5.5.5
PWR status register 1 (PWR_SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
5.5.6
Power status register 2 (PWR_SR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 215
5.5.7
PWR status clear register (PWR_SCR) . . . . . . . . . . . . . . . . . . . . . . . . 217
5.5.8
PWR control register 5 (PWR_CR5) . . . . . . . . . . . . . . . . . . . . . . . . . . 217
5.5.9
PWR port A pull-up control register (PWR_PUCRA) . . . . . . . . . . . . . . 218
5.5.10
PWR port A pull-down control register (PWR_PDCRA) . . . . . . . . . . . . 219
5.5.11
PWR port B pull-up control register (PWR_PUCRB) . . . . . . . . . . . . . . 219
5.5.12
PWR port B pull-down control register (PWR_PDCRB) . . . . . . . . . . . 220
5.5.13
PWR port C pull-up control register (PWR_PUCRC) . . . . . . . . . . . . . 220
5.5.14
PWR port C pull-down control register (PWR_PDCRC) . . . . . . . . . . . 221
5.5.15
PWR port H pull-up control register (PWR_PUCRH) . . . . . . . . . . . . . 221
5.5.16
PWR port H pull-down control register (PWR_PDCRH) . . . . . . . . . . . 222
5.5.17
PWR extended status and status clear register (PWR_EXTSCR) . . . 222
5.5.18
PWR sub-GHz SPI control register (PWR_SUBGHZSPICR) . . . . . . . 223
5.5.19
PWR register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Reset and clock control (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
6.1
8/1290
5.4.4
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
6.1.1
Power reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
6.1.2
System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
6.1.3
Backup domain reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
6.1.4
Sub-GHz radio reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
6.1.5
PKA SRAM reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
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Contents
6.2
Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
6.2.1
HSE32 clock with trimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
6.2.2
HSI16 clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
6.2.3
MSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
6.2.4
PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
6.2.5
LSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
6.2.6
LSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
6.2.7
Clock source stabilization time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
6.2.8
System clock (SYSCLK) selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
6.2.9
Clock source frequency versus voltage scaling . . . . . . . . . . . . . . . . . . 238
6.2.10
Clock security system on HSE32 (CSS) . . . . . . . . . . . . . . . . . . . . . . . 238
6.2.11
Clock security system on LSE (LSECSS) . . . . . . . . . . . . . . . . . . . . . . 238
6.2.12
SPI2S2 clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
6.2.13
Sub-GHz radio SPI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
6.2.14
ADC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
6.2.15
RTC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
6.2.16
Timer clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
6.2.17
Watchdog clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
6.2.18
True RNG clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
6.2.19
Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
6.2.20
Internal/external clock measurement with TIM16/TIM17 . . . . . . . . . . . 242
6.2.21
Peripheral clocks enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
6.3
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
6.4
RCC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
6.4.1
RCC clock control register (RCC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . 246
6.4.2
RCC internal clock sources calibration register (RCC_ICSCR) . . . . . . 249
6.4.3
RCC clock configuration register (RCC_CFGR) . . . . . . . . . . . . . . . . . 250
6.4.4
RCC PLL configuration register (RCC_PLLCFGR) . . . . . . . . . . . . . . . 253
6.4.5
RCC clock interrupt enable register (RCC_CIER) . . . . . . . . . . . . . . . . 256
6.4.6
RCC clock interrupt flag register (RCC_CIFR) . . . . . . . . . . . . . . . . . . 257
6.4.7
RCC clock interrupt clear register (RCC_CICR) . . . . . . . . . . . . . . . . . 258
6.4.8
RCC AHB1 peripheral reset register (RCC_AHB1RSTR) . . . . . . . . . . 259
6.4.9
RCC AHB2 peripheral reset register (RCC_AHB2RSTR) . . . . . . . . . . 260
6.4.10
RCC AHB3 peripheral reset register (RCC_AHB3RSTR) . . . . . . . . . . 261
6.4.11
RCC APB1 peripheral reset register 1 (RCC_APB1RSTR1) . . . . . . . . 261
6.4.12
RCC APB1 peripheral reset register 2 (RCC_APB1RSTR2) . . . . . . . . 263
6.4.13
RCC APB2 peripheral reset register (RCC_APB2RSTR) . . . . . . . . . . 263
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6.4.14
RCC APB3 peripheral reset register (RCC_APB3RSTR) . . . . . . . . . . 264
6.4.15
RCC AHB1 peripheral clock enable register (RCC_AHB1ENR) . . . . . 265
6.4.16
RCC AHB2 peripheral clock enable register (RCC_AHB2ENR) . . . . . 266
6.4.17
RCC AHB3 peripheral clock enable register (RCC_AHB3ENR) . . . . . 266
6.4.18
RCC APB1 peripheral clock enable register 1 (RCC_APB1ENR1) . . . 267
6.4.19
RCC APB1 peripheral clock enable register 2 (RCC_APB1ENR2) . . . 269
6.4.20
RCC APB2 peripheral clock enable register (RCC_APB2ENR) . . . . . 270
6.4.21
RCC APB3 peripheral clock enable register (RCC_APB3ENR) . . . . . 271
6.4.22
RCC AHB1 peripheral clock enable in Sleep mode register
(RCC_AHB1SMENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
6.4.23
RCC AHB2 peripheral clock enable in Sleep mode register
(RCC_AHB2SMENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
6.4.24
RCC AHB3 peripheral clock enable in Sleep and Stop mode register
(RCC_AHB3SMENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
6.4.25
RCC APB1 peripheral clock enable in Sleep mode register 1
(RCC_APB1SMENR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
6.4.26
RCC APB1 peripheral clock enable in Sleep mode register 2
(RCC_APB1SMENR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
6.4.27
RCC APB2 peripheral clock enable in Sleep mode register
(RCC_APB2SMENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
6.4.28
RCC APB3 peripheral clock enable in Sleep mode register
(RCC_APB3SMENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
6.4.29
RCC peripherals independent clock configuration register
(RCC_CCIPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
6.4.30
RCC backup domain control register (RCC_BDCR) . . . . . . . . . . . . . . 280
6.4.31
RCC control/status register (RCC_CSR) . . . . . . . . . . . . . . . . . . . . . . . 282
6.4.32
RCC extended clock recovery register (RCC_EXTCFGR) . . . . . . . . . 285
6.4.33
RCC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Hardware semaphore (HSEM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
7.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
7.2
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
7.3
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
7.3.1
HSEM block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
7.3.2
HSEM internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
7.3.3
HSEM lock procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
7.3.4
HSEM write/read/read lock register address . . . . . . . . . . . . . . . . . . . . 293
7.3.5
HSEM unlock procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
7.3.6
HSEM MASTERID semaphore clear . . . . . . . . . . . . . . . . . . . . . . . . . . 294
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7.4
8
7.3.7
HSEM interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
7.3.8
AHB bus master ID verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
HSEM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
7.4.1
HSEM register semaphore x (HSEM_Rx) . . . . . . . . . . . . . . . . . . . . . . 297
7.4.2
HSEM read lock register semaphore x (HSEM_RLRx) . . . . . . . . . . . . 298
7.4.3
HSEM interrupt enable register (HSEM_IER) . . . . . . . . . . . . . . . . . . . 299
7.4.4
HSEM interrupt clear register (HSEM_ICR) . . . . . . . . . . . . . . . . . . . . 299
7.4.5
HSEM interrupt status register (HSEM_ISR) . . . . . . . . . . . . . . . . . . . . 299
7.4.6
HSEM interrupt status register (HSEM_MISR) . . . . . . . . . . . . . . . . . . 300
7.4.7
HSEM clear register (HSEM_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
7.4.8
HSEM clear semaphore key register (HSEM_KEYR) . . . . . . . . . . . . . 301
7.4.9
HSEM register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
General-purpose I/Os (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
8.1
GPIO introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
8.2
GPIO main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
8.3
GPIO functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
8.4
8.3.1
General purpose I/O (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
8.3.2
I/O pin alternate function multiplexer and mapping . . . . . . . . . . . . . . . 306
8.3.3
I/O port control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
8.3.4
I/O port data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
8.3.5
I/O data bitwise handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
8.3.6
GPIO locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
8.3.7
I/O alternate function input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
8.3.8
External interrupt/wake-up lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
8.3.9
Input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
8.3.10
Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
8.3.11
Alternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
8.3.12
Analog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
8.3.13
Using the LSE oscillator pins as GPIOs . . . . . . . . . . . . . . . . . . . . . . . 311
8.3.14
Using the GPIO pins in the RTC supply domain . . . . . . . . . . . . . . . . . 311
8.3.15
Using PH3 as GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
GPIO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
8.4.1
GPIOx mode register (GPIOx_MODER) (x = A to B) . . . . . . . . . . . . . . 312
8.4.2
GPIOx output type register (GPIOx_OTYPER) (x = A to B) . . . . . . . . . 312
8.4.3
GPIOx output speed register (GPIOx_OSPEEDR) (x = A to B) . . . . . . 313
8.4.4
GPIOx pull-up/pull-down register (GPIOx_PUPDR) (x = A to B) . . . . . 313
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8.4.5
GPIOx input data register (GPIOx_IDR) (x = A to B) . . . . . . . . . . . . . . 314
8.4.6
GPIOx output data register (GPIOx_ODR) (x = A to B) . . . . . . . . . . . . 314
8.4.7
GPIOx bit set/reset register (GPIOx_BSRR) (x = A to B) . . . . . . . . . . . 315
8.4.8
GPIOx configuration lock register (GPIOx_LCKR) (x = A to B) . . . . . . 315
8.4.9
GPIOx alternate function low register (GPIOx_AFRL) (x = A to B) . . . 316
8.4.10
GPIOx alternate function high register (GPIOx_AFRH) (x = A to B) . . 317
8.4.11
GPIOx bit reset register (GPIOx_BRR) (x = A to B) . . . . . . . . . . . . . . . 317
8.4.12
GPIOC mode register (GPIOC_MODER) . . . . . . . . . . . . . . . . . . . . . . 318
8.4.13
GPIOC output type register (GPIOC_OTYPER) . . . . . . . . . . . . . . . . . 318
8.4.14
GPIOC output speed register (GPIOC_OSPEEDR) . . . . . . . . . . . . . . 319
8.4.15
GPIOC pull-up/pull-down register (GPIOC_PUPDR) . . . . . . . . . . . . . 320
8.4.16
GPIOC input data register (GPIOC_IDR) . . . . . . . . . . . . . . . . . . . . . . 320
8.4.17
GPIOC output data register (GPIOC_ODR) . . . . . . . . . . . . . . . . . . . . 321
8.4.18
GPIOC bit set/reset register (GPIOC_BSRR) . . . . . . . . . . . . . . . . . . . 321
8.4.19
GPIOC configuration lock register (GPIOC_LCKR) . . . . . . . . . . . . . . . 322
8.4.20
GPIOC alternate function low register (GPIOC_AFRL) . . . . . . . . . . . . 323
8.4.21
GPIOC alternate function high register (GPIOC_AFRH) . . . . . . . . . . . 324
8.4.22
GPIOC bit reset register (GPIOC_BRR) . . . . . . . . . . . . . . . . . . . . . . . 324
8.4.23
GPIOH mode register (GPIOH_MODER) . . . . . . . . . . . . . . . . . . . . . . 325
8.4.24
GPIO H output type register (GPIOH_OTYPER) . . . . . . . . . . . . . . . . . 325
8.4.25
GPIOH output speed register (GPIOH_OSPEEDR) . . . . . . . . . . . . . . 326
8.4.26
GPIOH pull-up/pull-down register (GPIOH_PUPDR) . . . . . . . . . . . . . 326
8.4.27
GPIOH input data register (GPIOH_IDR) . . . . . . . . . . . . . . . . . . . . . . 327
8.4.28
GPIOH output data register (GPIOH_ODR) . . . . . . . . . . . . . . . . . . . . 327
8.4.29
GPIO H bit set/reset register (GPIOH_BSRR) . . . . . . . . . . . . . . . . . . . 327
8.4.30
GPIOH configuration lock register (GPIOH_LCKR) . . . . . . . . . . . . . . . 328
8.4.31
GPIOH alternate function low register (GPIOH_AFRL) . . . . . . . . . . . . 329
8.4.32
GPIOH bit reset register (GPIOH_BRR) . . . . . . . . . . . . . . . . . . . . . . . 330
8.4.33
GPIOA register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
8.4.34
GPIOB register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
8.4.35
GPIOC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
8.4.36
GPIOH register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
System configuration controller (SYSCFG) . . . . . . . . . . . . . . . . . . . . 334
9.1
SYSCFG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334
9.2
SYSCFG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334
9.2.1
12/1290
SYSCFG memory remap register (SYSCFG_MEMRMP) . . . . . . . . . . 334
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9.2.2
SYSCFG configuration register 1 (SYSCFG_CFGR1) . . . . . . . . . . . . 335
9.2.3
SYSCFG external interrupt configuration register 1
(SYSCFG_EXTICR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
9.2.4
SYSCFG external interrupt configuration register 2
(SYSCFG_EXTICR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
9.2.5
SYSCFG external interrupt configuration register 3
(SYSCFG_EXTICR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
9.2.6
SYSCFG external interrupt configuration register 4
(SYSCFG_EXTICR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
9.2.7
SYSCFG SRAM control and status register (SYSCFG_SCSR) . . . . . 340
9.2.8
SYSCFG configuration register 2 (SYSCFG_CFGR2) . . . . . . . . . . . . 340
9.2.9
SYSCFG SRAM2 write protection register (SYSCFG_SWPR) . . . . . . 341
9.2.10
SYSCFG SRAM2 key register (SYSCFG_SKR) . . . . . . . . . . . . . . . . . 342
9.2.11
SYSCFG radio debug control register (SYSCFG_RFDCR) . . . . . . . . 342
9.2.12
SYSCFG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
Peripherals interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
10.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
10.2
Connection summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
10.3
Interconnection details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
10.3.1
From timer (TIM1/TIM2/TIM17) to timer (TIM1/TIM2) . . . . . . . . . . . . . 345
10.3.2
From timer (LPTIM1/LPTIM2) to timer (LPTIM3) . . . . . . . . . . . . . . . . . 346
10.3.3
From timer (TIM1/TIM2) and GPIO pin EXTI to ADC/DAC . . . . . . . . . 346
10.3.4
From timer (LPTIM1/LPTIM2) to DAC . . . . . . . . . . . . . . . . . . . . . . . . . 347
10.3.5
From ADC to timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
10.3.6
From HSE32, LSE, LSI, MSI, MCO, RTC to timers
(TIM2/TIM16/TIM17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
10.3.7
From RTC, TAMP, COMP1, COMP2 to low-power timers
(LPTIM1/LPTIM2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
10.3.8
From timer (TIM1/TIM2) to comparators (COMP1/COMP2) . . . . . . . . 348
10.3.9
From internal analog to ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
10.3.10 From comparators (COMP1/COMP2) to timers
(TIM1/TIM2/TIM16/TIM17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
10.3.11 From system errors to timers (TIM1/TIM16/TIM17) . . . . . . . . . . . . . . . 350
10.3.12 From timers (TIM16/TIM17) to IRTIM . . . . . . . . . . . . . . . . . . . . . . . . . 350
10.3.13 From timer (LPTIM1/LPTIM2/LPTIM3/GPIO pin EXTI)
to DMAMUX1 trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
10.3.14 From timer (LPTIM3) to sub-GHz radio SPI NSS . . . . . . . . . . . . . . . . 351
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Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . 352
11.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
11.2
DMA main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
11.3
DMA implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
11.4
12
DMA1 and DMA2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
11.3.2
DMA request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
DMA functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354
11.4.1
DMA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354
11.4.2
DMA pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
11.4.3
DMA transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
11.4.4
DMA arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356
11.4.5
DMA channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356
11.4.6
DMA data width, alignment and endianness . . . . . . . . . . . . . . . . . . . . 361
11.4.7
DMA error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
11.5
DMA interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
11.6
DMA registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
11.6.1
DMA interrupt status register (DMA_ISR) . . . . . . . . . . . . . . . . . . . . . . 363
11.6.2
DMA interrupt flag clear register (DMA_IFCR) . . . . . . . . . . . . . . . . . . 366
11.6.3
DMA channel x configuration register (DMA_CCRx) . . . . . . . . . . . . . . 367
11.6.4
DMA channel x number of data to transfer register (DMA_CNDTRx) . 371
11.6.5
DMA channel x peripheral address register (DMA_CPARx) . . . . . . . . 371
11.6.6
DMA channel x memory address register (DMA_CMARx) . . . . . . . . . 372
11.6.7
DMA register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
DMA request multiplexer (DMAMUX) . . . . . . . . . . . . . . . . . . . . . . . . . 375
12.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
12.2
DMAMUX main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
12.3
DMAMUX implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
12.4
14/1290
11.3.1
12.3.1
DMAMUX1 instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
12.3.2
DMAMUX1 mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
DMAMUX functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
12.4.1
DMAMUX block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
12.4.2
DMAMUX signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
12.4.3
DMAMUX channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
12.4.4
DMAMUX privileged / unprivileged channels . . . . . . . . . . . . . . . . . . . . 380
12.4.5
DMAMUX request line multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
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12.4.6
13
14
DMAMUX request generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384
12.5
DMAMUX interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
12.6
DMAMUX registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
12.6.1
DMAMUX request line multiplexer channel x configuration register
(DMAMUX_CxCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
12.6.2
DMAMUX request line multiplexer interrupt channel status register
(DMAMUX_CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
12.6.3
DMAMUX request line multiplexer interrupt channel clear flag register
(DMAMUX_CCFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
12.6.4
DMAMUX request generator channel x configuration register
(DMAMUX_RGxCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388
12.6.5
DMAMUX request generator interrupt status register
(DMAMUX_RGSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
12.6.6
DMAMUX request generator interrupt clear flag register
(DMAMUX_RGCFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
12.6.7
DMAMUX register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . 393
13.1
NVIC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
13.2
Interrupt and exception vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
Extended interrupts and event controller (EXTI) . . . . . . . . . . . . . . . . 396
14.1
EXTI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396
14.2
EXTI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396
14.3
EXTI connections between peripherals and CPU . . . . . . . . . . . . . . . . . 398
14.3.1
14.4
EXTI wake-up interrupt list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
EXTI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
14.4.1
EXTI configurable event input wake-up . . . . . . . . . . . . . . . . . . . . . . . . 400
14.4.2
EXTI direct event input wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
14.5
EXTI functional behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
14.6
EXTI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
14.6.1
EXTI rising trigger selection register (EXTI_RTSR1) . . . . . . . . . . . . . . 403
14.6.2
EXTI falling trigger selection register (EXTI_FTSR1) . . . . . . . . . . . . . 404
14.6.3
EXTI software interrupt event register (EXTI_SWIER1) . . . . . . . . . . . 405
14.6.4
EXTI pending register (EXTI_PR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
14.6.5
EXTI rising trigger selection register (EXTI_RTSR2) . . . . . . . . . . . . . . 407
14.6.6
EXTI falling trigger selection register (EXTI_FTSR2) . . . . . . . . . . . . . 408
14.6.7
EXTI software interrupt event register (EXTI_SWIER2) . . . . . . . . . . . 408
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14.6.8
EXTI pending register (EXTI_PR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 409
14.6.9
EXTI interrupt mask register (EXTI_IMR1) . . . . . . . . . . . . . . . . . . . . . 409
14.6.10 EXTI event mask register (EXTI_EMR1) . . . . . . . . . . . . . . . . . . . . . . . 410
14.6.11 EXTI interrupt mask register (EXTI_IMR2) . . . . . . . . . . . . . . . . . . . . . 411
14.6.12 EXTI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
15
Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . 413
15.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413
15.2
CRC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413
15.3
CRC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
15.4
16
15.3.1
CRC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
15.3.2
CRC internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
15.3.3
CRC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
CRC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416
15.4.1
CRC data register (CRC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416
15.4.2
CRC independent data register (CRC_IDR) . . . . . . . . . . . . . . . . . . . . 416
15.4.3
CRC control register (CRC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
15.4.4
CRC initial value (CRC_INIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
15.4.5
CRC polynomial (CRC_POL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
15.4.6
CRC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419
Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420
16.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420
16.2
ADC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421
16.3
ADC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
16.3.1
ADC pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
16.3.2
ADC voltage regulator (ADVREGEN) . . . . . . . . . . . . . . . . . . . . . . . . . 423
16.3.3
Calibration (ADCAL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424
16.3.4
ADC on-off control (ADEN, ADDIS, ADRDY) . . . . . . . . . . . . . . . . . . . . 426
16.3.5
ADC clock (CKMODE, PRESC[3:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . 427
16.3.6
ADC connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429
16.3.7
Configuring the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430
16.3.8
Channel selection (CHSEL, SCANDIR, CHSELRMOD) . . . . . . . . . . . 430
16.3.9
Programmable sampling time (SMPx[2:0]) . . . . . . . . . . . . . . . . . . . . . 431
16.3.10 Single conversion mode (CONT = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . 432
16.3.11 Continuous conversion mode (CONT = 1) . . . . . . . . . . . . . . . . . . . . . . 432
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16.3.12 Starting conversions (ADSTART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
16.3.13 Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434
16.3.14 Stopping an ongoing conversion (ADSTP) . . . . . . . . . . . . . . . . . . . . . 435
16.4
16.5
16.6
16.7
16.8
16.9
Conversion on external trigger and trigger polarity (EXTSEL, EXTEN) . 435
16.4.1
Discontinuous mode (DISCEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436
16.4.2
Programmable resolution (RES) - Fast conversion mode . . . . . . . . . . 436
16.4.3
End of conversion, end of sampling phase (EOC, EOSMP flags) . . . . 437
16.4.4
End of conversion sequence (EOS flag) . . . . . . . . . . . . . . . . . . . . . . . 437
16.4.5
Example timing diagrams (single/continuous modes
hardware/software triggers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438
16.4.6
Low frequency trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440
Data management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440
16.5.1
Data register and data alignment (ADC_DR, ALIGN) . . . . . . . . . . . . . 440
16.5.2
ADC overrun (OVR, OVRMOD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440
16.5.3
Managing a sequence of data converted without using the DMA . . . . 442
16.5.4
Managing converted data without using the DMA without overrun . . . 442
16.5.5
Managing converted data using the DMA . . . . . . . . . . . . . . . . . . . . . . 442
Low-power features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443
16.6.1
Wait mode conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443
16.6.2
Auto-off mode (AUTOFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444
Analog window watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445
16.7.1
Description of analog watchdog 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446
16.7.2
Description of analog watchdog 2 and 3 . . . . . . . . . . . . . . . . . . . . . . . 447
16.7.3
ADC_AWDx_OUT output signal generation . . . . . . . . . . . . . . . . . . . . 447
16.7.4
Analog watchdog threshold control . . . . . . . . . . . . . . . . . . . . . . . . . . . 449
Oversampler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450
16.8.1
ADC operating modes supported when oversampling . . . . . . . . . . . . 451
16.8.2
Analog watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452
16.8.3
Triggered mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452
Temperature sensor and internal reference voltage . . . . . . . . . . . . . . . . 452
16.10 Battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
16.11 ADC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456
16.12 ADC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457
16.12.1 ADC interrupt and status register (ADC_ISR) . . . . . . . . . . . . . . . . . . . 457
16.12.2 ADC interrupt enable register (ADC_IER) . . . . . . . . . . . . . . . . . . . . . . 458
16.12.3 ADC control register (ADC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460
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16.12.4 ADC configuration register 1 (ADC_CFGR1) . . . . . . . . . . . . . . . . . . . 462
16.12.5 ADC configuration register 2 (ADC_CFGR2) . . . . . . . . . . . . . . . . . . . 465
16.12.6 ADC sampling time register (ADC_SMPR) . . . . . . . . . . . . . . . . . . . . . 467
16.12.7 ADC watchdog threshold register (ADC_AWD1TR) . . . . . . . . . . . . . . 468
16.12.8 ADC watchdog threshold register (ADC_AWD2TR) . . . . . . . . . . . . . . 468
16.12.9 ADC channel selection register (ADC_CHSELR) . . . . . . . . . . . . . . . . 468
16.12.10 ADC channel selection register [alternate] (ADC_CHSELR) . . . . . . . . 469
16.12.11 ADC watchdog threshold register (ADC_AWD3TR) . . . . . . . . . . . . . . 471
16.12.12 ADC data register (ADC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472
16.12.13 ADC analog watchdog 2 configuration register (ADC_AWD2CR) . . . . 472
16.12.14 ADC Analog Watchdog 3 Configuration register (ADC_AWD3CR) . . . 473
16.12.15 ADC calibration factor (ADC_CALFACT) . . . . . . . . . . . . . . . . . . . . . . . 473
16.12.16 ADC common configuration register (ADC_CCR) . . . . . . . . . . . . . . . . 474
16.13 ADC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475
17
Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478
17.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478
17.2
DAC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478
17.3
DAC implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479
17.4
DAC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479
17.4.1
DAC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479
17.4.2
DAC pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480
17.4.3
DAC channel enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481
17.4.4
DAC data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481
17.4.5
DAC conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482
17.4.6
DAC output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482
17.4.7
DAC trigger selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482
17.4.8
DMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483
17.4.9
Noise generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483
17.4.10 Triangle-wave generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485
17.4.11
DAC channel modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486
17.4.12 DAC channel buffer calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489
17.4.13 DAC channel conversion modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490
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17.5
DAC in low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491
17.6
DAC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492
17.7
DAC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492
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17.7.1
DAC control register (DAC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492
17.7.2
DAC software trigger register (DAC_SWTRGR) . . . . . . . . . . . . . . . . . 494
17.7.3
DAC channel1 12-bit right-aligned data holding register
(DAC_DHR12R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494
17.7.4
DAC channel1 12-bit left aligned data holding register
(DAC_DHR12L1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495
17.7.5
DAC channel1 8-bit right aligned data holding register
(DAC_DHR8R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495
17.7.6
DAC channel1 data output register (DAC_DOR1) . . . . . . . . . . . . . . . . 496
17.7.7
DAC status register (DAC_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496
17.7.8
DAC calibration control register (DAC_CCR) . . . . . . . . . . . . . . . . . . . 497
17.7.9
DAC mode control register (DAC_MCR) . . . . . . . . . . . . . . . . . . . . . . . 497
17.7.10 DAC channel1 sample and hold sample time register
(DAC_SHSR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498
17.7.11 DAC sample and hold time register (DAC_SHHR) . . . . . . . . . . . . . . . 498
17.7.12 DAC sample and hold refresh time register (DAC_SHRR) . . . . . . . . . 499
17.7.13 DAC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500
18
19
Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . 502
18.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502
18.2
VREFBUF functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502
18.3
VREFBUF registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503
18.3.1
VREFBUF control and status register (VREFBUF_CSR) . . . . . . . . . . 503
18.3.2
VREFBUF calibration control register (VREFBUF_CCR) . . . . . . . . . . 504
18.3.3
VREFBUF register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504
Comparator (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505
19.1
COMP introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505
19.2
COMP main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505
19.3
COMP functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506
19.3.1
COMP block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506
19.3.2
COMP pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506
19.3.3
COMP reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508
19.3.4
Comparator LOCK mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508
19.3.5
Window comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508
19.3.6
Hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509
19.3.7
Comparator output blanking function . . . . . . . . . . . . . . . . . . . . . . . . . . 510
19.3.8
COMP power and speed modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510
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19.4
COMP low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .511
19.5
COMP interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .511
19.6
COMP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512
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COMP1 control and status register (COMP1_CSR) . . . . . . . . . . . . . . 512
19.6.2
COMP2 control and status register (COMP2_CSR) . . . . . . . . . . . . . . 514
19.6.3
COMP register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516
True random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . 517
20.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517
20.2
RNG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517
20.3
RNG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518
20.3.1
RNG block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518
20.3.2
RNG internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518
20.3.3
Random number generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518
20.3.4
RNG initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521
20.3.5
RNG operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522
20.3.6
RNG clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524
20.3.7
Error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524
20.3.8
RNG low-power use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525
20.4
RNG interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525
20.5
RNG processing time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526
20.6
RNG entropy source validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526
20.7
21
19.6.1
20.6.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526
20.6.2
Validation conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526
20.6.3
Data collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527
RNG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527
20.7.1
RNG control register (RNG_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527
20.7.2
RNG status register (RNG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529
20.7.3
RNG data register (RNG_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530
20.7.4
RNG health test control register (RNG_HTCR) . . . . . . . . . . . . . . . . . . 531
20.7.5
RNG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531
AES hardware accelerator (AES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532
21.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532
21.2
AES main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532
21.3
AES implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532
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21.4
AES functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533
21.4.1
AES block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533
21.4.2
AES internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533
21.4.3
AES cryptographic core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533
21.4.4
AES procedure to perform a cipher operation . . . . . . . . . . . . . . . . . . . 539
21.4.5
AES decryption round key preparation . . . . . . . . . . . . . . . . . . . . . . . . 542
21.4.6
AES ciphertext stealing and data padding . . . . . . . . . . . . . . . . . . . . . . 542
21.4.7
AES task suspend and resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543
21.4.8
AES basic chaining modes (ECB, CBC) . . . . . . . . . . . . . . . . . . . . . . . 543
21.4.9
AES counter (CTR) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548
21.4.10 AES Galois/counter mode (GCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550
21.4.11 AES Galois message authentication code (GMAC) . . . . . . . . . . . . . . 555
21.4.12 AES counter with CBC-MAC (CCM) . . . . . . . . . . . . . . . . . . . . . . . . . . 557
21.4.13 AES data registers and data swapping . . . . . . . . . . . . . . . . . . . . . . . . 562
21.4.14 AES key registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564
21.4.15 AES initialization vector registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564
21.4.16 AES DMA interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565
21.4.17 AES error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566
21.5
AES interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567
21.6
AES processing latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567
21.7
AES registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568
21.7.1
AES control register (AES_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568
21.7.2
AES status register (AES_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570
21.7.3
AES data input register (AES_DINR) . . . . . . . . . . . . . . . . . . . . . . . . . 572
21.7.4
AES data output register (AES_DOUTR) . . . . . . . . . . . . . . . . . . . . . . 572
21.7.5
AES key register 0 (AES_KEYR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573
21.7.6
AES key register 1 (AES_KEYR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573
21.7.7
AES key register 2 (AES_KEYR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574
21.7.8
AES key register 3 (AES_KEYR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574
21.7.9
AES initialization vector register 0 (AES_IVR0) . . . . . . . . . . . . . . . . . . 574
21.7.10 AES initialization vector register 1 (AES_IVR1) . . . . . . . . . . . . . . . . . . 575
21.7.11 AES initialization vector register 2 (AES_IVR2) . . . . . . . . . . . . . . . . . . 575
21.7.12 AES initialization vector register 3 (AES_IVR3) . . . . . . . . . . . . . . . . . . 575
21.7.13 AES key register 4 (AES_KEYR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576
21.7.14 AES key register 5 (AES_KEYR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576
21.7.15 AES key register 6 (AES_KEYR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576
21.7.16 AES key register 7 (AES_KEYR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577
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21.7.17 AES suspend registers (AES_SUSPxR) . . . . . . . . . . . . . . . . . . . . . . . 577
21.7.18 AES register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578
22
Public key accelerator (PKA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580
22.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580
22.2
PKA main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580
22.3
PKA functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580
22.4
22.3.1
PKA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580
22.3.2
PKA internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581
22.3.3
PKA reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581
22.3.4
PKA public key acceleration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581
22.3.5
Typical applications for PKA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583
22.3.6
PKA procedure to perform an operation . . . . . . . . . . . . . . . . . . . . . . . 585
22.3.7
PKA error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586
PKA operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586
22.4.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586
22.4.2
Montgomery parameter computation . . . . . . . . . . . . . . . . . . . . . . . . . . 587
22.4.3
Modular addition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588
22.4.4
Modular subtraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588
22.4.5
Modular and Montgomery multiplication . . . . . . . . . . . . . . . . . . . . . . . 588
22.4.6
Modular exponentiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589
22.4.7
Modular inversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590
22.4.8
Modular reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591
22.4.9
Arithmetic addition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591
22.4.10 Arithmetic subtraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591
22.4.11 Arithmetic multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592
22.4.12 Arithmetic comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592
22.4.13 RSA CRT exponentiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592
22.4.14 Point on elliptic curve Fp check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593
22.4.15 ECC Fp scalar multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594
22.4.16 ECDSA sign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595
22.4.17 ECDSA verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597
22.5
22.6
22/1290
Example of configurations and processing times . . . . . . . . . . . . . . . . . . 598
22.5.1
Supported elliptic curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598
22.5.2
Computation times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600
PKA interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601
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22.7
23
PKA registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602
22.7.1
PKA control register (PKA_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602
22.7.2
PKA status register (PKA_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603
22.7.3
PKA clear flag register (PKA_CLRFR) . . . . . . . . . . . . . . . . . . . . . . . . . 604
22.7.4
PKA RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604
22.7.5
PKA register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605
Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606
23.1
TIM1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606
23.2
TIM1 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607
23.3
TIM1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609
23.3.1
Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609
23.3.2
Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611
23.3.3
Repetition counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 622
23.3.4
External trigger input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624
23.3.5
Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625
23.3.6
Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629
23.3.7
Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631
23.3.8
PWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632
23.3.9
Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633
23.3.10 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634
23.3.11 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635
23.3.12 Asymmetric PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638
23.3.13 Combined PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639
23.3.14 Combined 3-phase PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640
23.3.15 Complementary outputs and dead-time insertion . . . . . . . . . . . . . . . . 641
23.3.16 Using the break function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643
23.3.17 Bidirectional break inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649
23.3.18 Clearing the OCxREF signal on an external event . . . . . . . . . . . . . . . 651
23.3.19 6-step PWM generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652
23.3.20 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653
23.3.21 Retriggerable one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654
23.3.22 Encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655
23.3.23 UIF bit remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657
23.3.24 Timer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658
23.3.25 Interfacing with Hall sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658
23.3.26 Timer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661
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23.3.27 ADC synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665
23.3.28 DMA burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665
23.3.29 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666
23.4
TIM1 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667
23.4.1
TIM1 control register 1 (TIM1_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . 667
23.4.2
TIM1 control register 2 (TIM1_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 668
23.4.3
TIM1 slave mode control register
(TIM1_SMCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671
23.4.4
TIM1 DMA/interrupt enable register
(TIM1_DIER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673
23.4.5
TIM1 status register (TIM1_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675
23.4.6
TIM1 event generation register (TIM1_EGR) . . . . . . . . . . . . . . . . . . . 677
23.4.7
TIM1 capture/compare mode register 1 (TIM1_CCMR1) . . . . . . . . . . 678
23.4.8
TIM1 capture/compare mode register 1 [alternate]
(TIM1_CCMR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 679
23.4.9
TIM1 capture/compare mode register 2 (TIM1_CCMR2) . . . . . . . . . . 682
23.4.10 TIM1 capture/compare mode register 2 [alternate]
(TIM1_CCMR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683
23.4.11 TIM1 capture/compare enable register
(TIM1_CCER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685
23.4.12 TIM1 counter (TIM1_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688
23.4.13 TIM1 prescaler (TIM1_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688
23.4.14 TIM1 auto-reload register (TIM1_ARR) . . . . . . . . . . . . . . . . . . . . . . . . 688
23.4.15 TIM1 repetition counter register (TIM1_RCR) . . . . . . . . . . . . . . . . . . . 689
23.4.16 TIM1 capture/compare register 1
(TIM1_CCR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689
23.4.17 TIM1 capture/compare register 2
(TIM1_CCR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690
23.4.18 TIM1 capture/compare register 3
(TIM1_CCR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690
23.4.19 TIM1 capture/compare register 4
(TIM1_CCR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691
23.4.20 TIM1 break and dead-time register
(TIM1_BDTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691
23.4.21 TIM1 DMA control register
(TIM1_DCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695
23.4.22 TIM1 DMA address for full transfer
(TIM1_DMAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 696
23.4.23 TIM1 option register 1 (TIM1_OR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 697
23.4.24 TIM1 capture/compare mode register 3
(TIM1_CCMR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 697
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23.4.25 TIM1 capture/compare register 5
(TIM1_CCR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 698
23.4.26 TIM1 capture/compare register 6
(TIM1_CCR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699
23.4.27 TIM1 alternate function option register 1 (TIM1_AF1) . . . . . . . . . . . . . 700
23.4.28 TIM1 Alternate function register 2 (TIM1_AF2) . . . . . . . . . . . . . . . . . . 701
23.4.29 TIM1 timer input selection register (TIM1_TISEL) . . . . . . . . . . . . . . . . 703
23.4.30 TIM1 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704
24
General-purpose timer (TIM2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 707
24.1
TIM2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 707
24.2
TIM2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 707
24.3
TIM2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709
24.3.1
Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709
24.3.2
Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711
24.3.3
Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721
24.3.4
Capture/Compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725
24.3.5
Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 727
24.3.6
PWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728
24.3.7
Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 729
24.3.8
Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 729
24.3.9
PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 730
24.3.10 Asymmetric PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 734
24.3.11 Combined PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 734
24.3.12 Clearing the OCxREF signal on an external event . . . . . . . . . . . . . . . 735
24.3.13 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737
24.3.14 Retriggerable one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738
24.3.15 Encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739
24.3.16 UIF bit remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741
24.3.17 Timer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741
24.3.18 Timers and external trigger synchronization . . . . . . . . . . . . . . . . . . . . 742
24.3.19 Timer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745
24.3.20 DMA burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750
24.3.21 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751
24.4
TIM2 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752
24.4.1
TIM2 control register 1 (TIM2_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . 752
24.4.2
TIM2 control register 2 (TIM2_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 753
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24.4.3
TIM2 slave mode control register (TIM2_SMCR) . . . . . . . . . . . . . . . . 755
24.4.4
TIM2 DMA/Interrupt enable register (TIM2_DIER) . . . . . . . . . . . . . . . 758
24.4.5
TIM2 status register (TIM2_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759
24.4.6
TIM2 event generation register (TIM2_EGR) . . . . . . . . . . . . . . . . . . . 761
24.4.7
TIM2 capture/compare mode register 1 (TIM2_CCMR1) . . . . . . . . . . 762
24.4.8
TIM2 capture/compare mode register 1 [alternate] (TIM2_CCMR1) . . 764
24.4.9
TIM2 capture/compare mode register 2 (TIM2_CCMR2) . . . . . . . . . . 766
24.4.10 TIM2 capture/compare mode register 2 [alternate] (TIM2_CCMR2) . . 767
24.4.11 TIM2 capture/compare enable register
(TIM2_CCER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 768
24.4.12 TIM2 counter (TIM2_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 769
24.4.13 TIM2 counter [alternate] (TIM2_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . 770
24.4.14 TIM2 prescaler (TIM2_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770
24.4.15 TIM2 auto-reload register (TIM2_ARR) . . . . . . . . . . . . . . . . . . . . . . . . 771
24.4.16 TIM2 capture/compare register 1 (TIM2_CCR1) . . . . . . . . . . . . . . . . . 771
24.4.17 TIM2 capture/compare register 2 (TIM2_CCR2) . . . . . . . . . . . . . . . . . 771
24.4.18 TIM2 capture/compare register 3 (TIM2_CCR3) . . . . . . . . . . . . . . . . . 772
24.4.19 TIM2 capture/compare register 4 (TIM2_CCR4) . . . . . . . . . . . . . . . . . 772
24.4.20 TIM2 DMA control register (TIM2_DCR) . . . . . . . . . . . . . . . . . . . . . . . 773
24.4.21 TIM2 DMA address for full transfer (TIM2_DMAR) . . . . . . . . . . . . . . . 774
24.4.22 TIM2 option register 1 (TIM2_OR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 774
24.4.23 TIM2 alternate function option register 1 (TIM2_AF1) . . . . . . . . . . . . . 774
24.4.24 TIM2 timer input selection register (TIM2_TISEL) . . . . . . . . . . . . . . . . 775
24.4.25 TIMx register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776
25
26/1290
General-purpose timers (TIM16/TIM17) . . . . . . . . . . . . . . . . . . . . . . . . 779
25.1
TIM16/TIM17 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779
25.2
TIM16/TIM17 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779
25.3
TIM16/TIM17 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781
25.3.1
Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781
25.3.2
Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 783
25.3.3
Repetition counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787
25.3.4
Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 788
25.3.5
Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 790
25.3.6
Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 792
25.3.7
Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793
25.3.8
Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793
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Contents
25.3.9
PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 795
25.3.10 Complementary outputs and dead-time insertion . . . . . . . . . . . . . . . . 796
25.3.11 Using the break function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 798
25.3.12 Bidirectional break inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 801
25.3.13 6-step PWM generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 802
25.3.14 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804
25.3.15 UIF bit remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 805
25.3.16 Slave mode – combined reset + trigger mode . . . . . . . . . . . . . . . . . . . 805
25.3.17 DMA burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 805
25.3.18 Using timer output as trigger for other timers (TIM16/TIM17) . . . . . . . 806
25.3.19 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807
25.4
TIM16/TIM17 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 808
25.4.1
TIMx control register 1 (TIMx_CR1)(x = 16 to 17) . . . . . . . . . . . . . . . . 808
25.4.2
TIMx control register 2 (TIMx_CR2)(x = 16 to 17) . . . . . . . . . . . . . . . . 809
25.4.3
TIMx DMA/interrupt enable register (TIMx_DIER)(x = 16 to 17) . . . . . 810
25.4.4
TIMx status register (TIMx_SR)(x = 16 to 17) . . . . . . . . . . . . . . . . . . . 811
25.4.5
TIMx event generation register (TIMx_EGR)(x = 16 to 17) . . . . . . . . . 812
25.4.6
TIMx capture/compare mode register 1
(TIMx_CCMR1)(x = 16 to 17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 813
25.4.7
TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 16 to 17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814
25.4.8
TIMx capture/compare enable register (TIMx_CCER)(x = 16 to 17) . . 816
25.4.9
TIMx counter (TIMx_CNT)(x = 16 to 17) . . . . . . . . . . . . . . . . . . . . . . . 818
25.4.10 TIMx prescaler (TIMx_PSC)(x = 16 to 17) . . . . . . . . . . . . . . . . . . . . . . 819
25.4.11 TIMx auto-reload register (TIMx_ARR)(x = 16 to 17) . . . . . . . . . . . . . 819
25.4.12 TIMx repetition counter register (TIMx_RCR)(x = 16 to 17) . . . . . . . . . 820
25.4.13 TIMx capture/compare register 1 (TIMx_CCR1)(x = 16 to 17) . . . . . . 820
25.4.14 TIMx break and dead-time register (TIMx_BDTR)(x = 16 to 17) . . . . . 821
25.4.15 TIMx DMA control register (TIMx_DCR)(x = 16 to 17) . . . . . . . . . . . . . 823
25.4.16 TIMx DMA address for full transfer (TIMx_DMAR)(x = 16 to 17) . . . . . 824
25.4.17 TIM16 option register 1 (TIM16_OR1) . . . . . . . . . . . . . . . . . . . . . . . . . 825
25.4.18 TIM16 alternate function register 1 (TIM16_AF1) . . . . . . . . . . . . . . . . 825
25.4.19 TIM16 input selection register (TIM16_TISEL) . . . . . . . . . . . . . . . . . . 826
25.4.20 TIM17 option register 1 (TIM17_OR1) . . . . . . . . . . . . . . . . . . . . . . . . . 827
25.4.21 TIM17 alternate function register 1 (TIM17_AF1) . . . . . . . . . . . . . . . . 827
25.4.22 TIM17 input selection register (TIM17_TISEL) . . . . . . . . . . . . . . . . . . 828
25.4.23 TIM16/TIM17 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829
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26
RM0461
Low-power timer (LPTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 831
26.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 831
26.2
LPTIM main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 831
26.3
LPTIM implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 831
26.4
LPTIM functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 832
26.4.1
LPTIM block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 832
26.4.2
LPTIM pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 832
26.4.3
LPTIM input and trigger mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 833
26.4.4
LPTIM reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 835
26.4.5
Glitch filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 835
26.4.6
Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 836
26.4.7
Trigger multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 836
26.4.8
Operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 837
26.4.9
Timeout function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 839
26.4.10 Waveform generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 839
26.4.11 Register update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 840
26.4.12 Counter mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 841
26.4.13 Timer enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 841
26.4.14 Timer counter reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 842
26.4.15 Encoder mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 842
26.4.16 Repetition counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 844
26.4.17 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 845
26.5
LPTIM low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846
26.6
LPTIM interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846
26.7
LPTIM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 847
26.7.1
LPTIM interrupt and status register (LPTIM_ISR) . . . . . . . . . . . . . . . . 847
26.7.2
LPTIM interrupt clear register (LPTIM_ICR) . . . . . . . . . . . . . . . . . . . . 848
26.7.3
LPTIM interrupt enable register (LPTIM_IER) . . . . . . . . . . . . . . . . . . . 849
26.7.4
LPTIM configuration register (LPTIM_CFGR) . . . . . . . . . . . . . . . . . . . 850
26.7.5
LPTIM control register (LPTIM_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . 853
26.7.6
LPTIM compare register (LPTIM_CMP) . . . . . . . . . . . . . . . . . . . . . . . 854
26.7.7
LPTIM autoreload register (LPTIM_ARR) . . . . . . . . . . . . . . . . . . . . . . 854
26.7.8
LPTIM counter register (LPTIM_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . 855
26.7.9
LPTIM1 option register (LPTIM1_OR) . . . . . . . . . . . . . . . . . . . . . . . . . 855
26.7.10 LPTIM2 option register (LPTIM2_OR) . . . . . . . . . . . . . . . . . . . . . . . . . 856
26.7.11 LPTIM3 option register (LPTIM3_OR) . . . . . . . . . . . . . . . . . . . . . . . . . 856
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26.7.12 LPTIM repetition register (LPTIM_RCR) . . . . . . . . . . . . . . . . . . . . . . . 857
26.7.13 LPTIM register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 857
27
Infrared interface (IRTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 859
28
Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 860
28.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 860
28.2
IWDG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 860
28.3
IWDG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 860
28.4
29
28.3.1
IWDG block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 860
28.3.2
Window option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 861
28.3.3
Hardware watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 862
28.3.4
Low-power freeze . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 862
28.3.5
Register access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 862
28.3.6
Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 862
IWDG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 863
28.4.1
IWDG key register (IWDG_KR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 863
28.4.2
IWDG prescaler register (IWDG_PR) . . . . . . . . . . . . . . . . . . . . . . . . . 864
28.4.3
IWDG reload register (IWDG_RLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 865
28.4.4
IWDG status register (IWDG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 866
28.4.5
IWDG window register (IWDG_WINR) . . . . . . . . . . . . . . . . . . . . . . . . 867
28.4.6
IWDG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 868
System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . 869
29.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 869
29.2
WWDG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 869
29.3
WWDG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 869
29.3.1
WWDG block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 870
29.3.2
WWDG internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 870
29.3.3
Enabling the watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 870
29.3.4
Controlling the down-counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 870
29.3.5
How to program the watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . . 871
29.3.6
Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 872
29.4
WWDG interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 872
29.5
WWDG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 872
29.5.1
WWDG control register (WWDG_CR) . . . . . . . . . . . . . . . . . . . . . . . . . 873
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29.5.2
WWDG configuration register (WWDG_CFR) . . . . . . . . . . . . . . . . . . . 873
29.5.3
WWDG status register (WWDG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . 874
29.5.4
WWDG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 874
Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 875
30.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 875
30.2
RTC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 875
30.3
RTC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 876
30.3.1
RTC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 876
30.3.2
RTC pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 877
30.3.3
GPIOs controlled by the RTC and TAMP . . . . . . . . . . . . . . . . . . . . . . . 878
30.3.4
Clock and prescalers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 880
30.3.5
Real-time clock and calendar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 882
30.3.6
Calendar ultra-low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 882
30.3.7
Programmable alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 882
30.3.8
Periodic auto-wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 883
30.3.9
RTC initialization and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 884
30.3.10 Reading the calendar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 886
30.3.11 Resetting the RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 887
30.3.12 RTC synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 887
30.3.13 RTC reference clock detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 888
30.3.14 RTC smooth digital calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 889
30.3.15 Timestamp function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 891
30.3.16 Calibration clock output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 892
30.3.17 Tamper and alarm output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 892
30/1290
30.4
RTC low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 893
30.5
RTC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 894
30.6
RTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 895
30.6.1
RTC time register (RTC_TR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 895
30.6.2
RTC date register (RTC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 896
30.6.3
RTC sub second register (RTC_SSR) . . . . . . . . . . . . . . . . . . . . . . . . . 897
30.6.4
RTC initialization control and status register (RTC_ICSR) . . . . . . . . . 897
30.6.5
RTC prescaler register (RTC_PRER) . . . . . . . . . . . . . . . . . . . . . . . . . 899
30.6.6
RTC wake-up timer register (RTC_WUTR) . . . . . . . . . . . . . . . . . . . . . 900
30.6.7
RTC control register (RTC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900
30.6.8
RTC write protection register (RTC_WPR) . . . . . . . . . . . . . . . . . . . . . 904
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Contents
30.6.9
RTC calibration register (RTC_CALR) . . . . . . . . . . . . . . . . . . . . . . . . . 904
30.6.10 RTC shift control register (RTC_SHIFTR) . . . . . . . . . . . . . . . . . . . . . . 905
30.6.11 RTC timestamp time register (RTC_TSTR) . . . . . . . . . . . . . . . . . . . . . 906
30.6.12 RTC timestamp date register (RTC_TSDR) . . . . . . . . . . . . . . . . . . . . 907
30.6.13 RTC timestamp sub second register (RTC_TSSSR) . . . . . . . . . . . . . . 907
30.6.14 RTC alarm A register (RTC_ALRMAR) . . . . . . . . . . . . . . . . . . . . . . . . 908
30.6.15 RTC alarm A sub second register (RTC_ALRMASSR) . . . . . . . . . . . . 909
30.6.16 RTC alarm B register (RTC_ALRMBR) . . . . . . . . . . . . . . . . . . . . . . . . 910
30.6.17 RTC alarm B sub second register (RTC_ALRMBSSR) . . . . . . . . . . . . 911
30.6.18 RTC status register (RTC_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 912
30.6.19 RTC masked interrupt status register (RTC_MISR) . . . . . . . . . . . . . . 913
30.6.20 RTC status clear register (RTC_SCR) . . . . . . . . . . . . . . . . . . . . . . . . . 914
30.6.21 RTC alarm A binary mode register (RTC_ALRABINR) . . . . . . . . . . . . 915
30.6.22 RTC alarm B binary mode register (RTC_ALRBBINR) . . . . . . . . . . . . 915
30.6.23 RTC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 916
31
Tamper and backup registers (TAMP) . . . . . . . . . . . . . . . . . . . . . . . . . 918
31.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 918
31.2
TAMP main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 918
31.3
TAMP functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 919
31.3.1
TAMP block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 919
31.3.2
TAMP pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 920
31.3.3
TAMP register write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 921
31.3.4
Tamper detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 921
31.4
TAMP low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 923
31.5
TAMP interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 923
31.6
TAMP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 924
31.6.1
TAMP control register 1 (TAMP_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . 924
31.6.2
TAMP control register 2 (TAMP_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . 925
31.6.3
TAMP control register 3 (TAMP_CR3) . . . . . . . . . . . . . . . . . . . . . . . . . 926
31.6.4
TAMP filter control register (TAMP_FLTCR) . . . . . . . . . . . . . . . . . . . . 927
31.6.5
TAMP interrupt enable register (TAMP_IER) . . . . . . . . . . . . . . . . . . . . 928
31.6.6
TAMP status register (TAMP_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 929
31.6.7
TAMP masked interrupt status register (TAMP_MISR) . . . . . . . . . . . . 930
31.6.8
TAMP status clear register (TAMP_SCR) . . . . . . . . . . . . . . . . . . . . . . 931
31.6.9
TAMP monotonic counter register (TAMP_COUNTR) . . . . . . . . . . . . . 933
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31.6.10 TAMP backup x register (TAMP_BKPxR) . . . . . . . . . . . . . . . . . . . . . . 933
31.6.11 TAMP register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 934
32
Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . 935
32.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 935
32.2
I2C main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 935
32.3
I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 936
32.4
I2C functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 936
32.4.1
I2C block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 937
32.4.2
I2C pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 937
32.4.3
I2C clock requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 938
32.4.4
I2C mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 938
32.4.5
I2C initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 939
32.4.6
I2C reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 943
32.4.7
I2C data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 944
32.4.8
I2C target mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 946
32.4.9
I2C controller mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 955
32.4.10 I2C_TIMINGR register configuration examples . . . . . . . . . . . . . . . . . . 966
32.4.11 SMBus specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 968
32.4.12 SMBus initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 970
32.4.13 SMBus I2C_TIMEOUTR register configuration examples . . . . . . . . . . 972
32.4.14 SMBus target mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 973
32.4.15 SMBus controller mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 976
32.4.16 Wake-up from Stop mode on address match . . . . . . . . . . . . . . . . . . . 979
32.4.17 Error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 980
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32.5
I2C in low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 982
32.6
I2C interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 982
32.7
I2C DMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 983
32.7.1
Transmission using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 983
32.7.2
Reception using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 983
32.8
I2C debug modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 984
32.9
I2C registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 984
32.9.1
I2C control register 1 (I2C_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 984
32.9.2
I2C control register 2 (I2C_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 987
32.9.3
I2C own address 1 register (I2C_OAR1) . . . . . . . . . . . . . . . . . . . . . . . 989
32.9.4
I2C own address 2 register (I2C_OAR2) . . . . . . . . . . . . . . . . . . . . . . . 990
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32.9.5
I2C timing register (I2C_TIMINGR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 991
32.9.6
I2C timeout register (I2C_TIMEOUTR) . . . . . . . . . . . . . . . . . . . . . . . . 992
32.9.7
I2C interrupt and status register (I2C_ISR) . . . . . . . . . . . . . . . . . . . . . 993
32.9.8
I2C interrupt clear register (I2C_ICR) . . . . . . . . . . . . . . . . . . . . . . . . . 995
32.9.9
I2C PEC register (I2C_PECR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 996
32.9.10 I2C receive data register (I2C_RXDR) . . . . . . . . . . . . . . . . . . . . . . . . 996
32.9.11 I2C transmit data register (I2C_TXDR) . . . . . . . . . . . . . . . . . . . . . . . . 997
32.9.12 I2C register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 998
33
Universal synchronous/asynchronous receiver
transmitter (USART/UART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 999
33.1
USART introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 999
33.2
USART main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000
33.3
USART extended features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1001
33.4
USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1001
33.5
USART functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1002
33.5.1
USART block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1002
33.5.2
USART signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1003
33.5.3
USART character description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1004
33.5.4
USART FIFOs and thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1006
33.5.5
USART transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1006
33.5.6
USART receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1010
33.5.7
USART baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1017
33.5.8
Tolerance of the USART receiver to clock deviation . . . . . . . . . . . . . 1018
33.5.9
USART auto baud rate detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1020
33.5.10 USART multiprocessor communication . . . . . . . . . . . . . . . . . . . . . . . 1022
33.5.11 USART Modbus communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1024
33.5.12 USART parity control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1025
33.5.13 USART LIN (local interconnection network) mode . . . . . . . . . . . . . . 1026
33.5.14 USART synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1028
33.5.15 USART single-wire half-duplex communication . . . . . . . . . . . . . . . . . 1032
33.5.16 USART receiver timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1032
33.5.17 USART smartcard mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1033
33.5.18 USART IrDA SIR ENDEC block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1037
33.5.19 Continuous communication using USART and DMA . . . . . . . . . . . . . 1040
33.5.20 RS232 hardware flow control and RS485 Driver Enable . . . . . . . . . . 1042
33.5.21 USART low-power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1045
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33.6
USART in low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1048
33.7
USART interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1049
33.8
USART registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1050
33.8.1
USART control register 1 (USART_CR1) . . . . . . . . . . . . . . . . . . . . . 1050
33.8.2
USART control register 1 [alternate] (USART_CR1) . . . . . . . . . . . . . 1053
33.8.3
USART control register 2 (USART_CR2) . . . . . . . . . . . . . . . . . . . . . 1057
33.8.4
USART control register 3 (USART_CR3) . . . . . . . . . . . . . . . . . . . . . 1061
33.8.5
USART baud rate register (USART_BRR) . . . . . . . . . . . . . . . . . . . . 1065
33.8.6
USART guard time and prescaler register (USART_GTPR) . . . . . . . 1065
33.8.7
USART receiver timeout register (USART_RTOR) . . . . . . . . . . . . . . 1066
33.8.8
USART request register (USART_RQR) . . . . . . . . . . . . . . . . . . . . . . 1067
33.8.9
USART interrupt and status register (USART_ISR) . . . . . . . . . . . . . 1068
33.8.10 USART interrupt and status register [alternate] (USART_ISR) . . . . . 1074
33.8.11 USART interrupt flag clear register (USART_ICR) . . . . . . . . . . . . . . 1079
33.8.12 USART receive data register (USART_RDR) . . . . . . . . . . . . . . . . . . 1081
33.8.13 USART transmit data register (USART_TDR) . . . . . . . . . . . . . . . . . . 1081
33.8.14 USART prescaler register (USART_PRESC) . . . . . . . . . . . . . . . . . . 1082
33.8.15 USART register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1083
34
Low-power universal asynchronous receiver
transmitter (LPUART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1085
34.1
LPUART introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1085
34.2
LPUART main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1086
34.3
LPUART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1087
34.4
LPUART functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1088
34.4.1
LPUART block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1088
34.4.2
LPUART signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1089
34.4.3
LPUART character description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1090
34.4.4
LPUART FIFOs and thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1091
34.4.5
LPUART transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1092
34.4.6
LPUART receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1095
34.4.7
LPUART baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1099
34.4.8
Tolerance of the LPUART receiver to clock deviation . . . . . . . . . . . . 1100
34.4.9
LPUART multiprocessor communication . . . . . . . . . . . . . . . . . . . . . . 1101
34.4.10 LPUART parity control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1103
34.4.11 LPUART single-wire half-duplex communication . . . . . . . . . . . . . . . . 1104
34.4.12 Continuous communication using DMA and LPUART . . . . . . . . . . . . 1104
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34.4.13 RS232 hardware flow control and RS485 Driver Enable . . . . . . . . . . 1107
34.4.14 LPUART low-power management . . . . . . . . . . . . . . . . . . . . . . . . . . . 1109
34.5
LPUART in low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1112
34.6
LPUART interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1113
34.7
LPUART registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1114
34.7.1
LPUART control register 1 (LPUART_CR1) . . . . . . . . . . . . . . . . . . . 1114
34.7.2
LPUART control register 1 [alternate] (LPUART_CR1) . . . . . . . . . . . 1117
34.7.3
LPUART control register 2 (LPUART_CR2) . . . . . . . . . . . . . . . . . . . 1120
34.7.4
LPUART control register 3 (LPUART_CR3) . . . . . . . . . . . . . . . . . . . 1122
34.7.5
LPUART baud rate register (LPUART_BRR) . . . . . . . . . . . . . . . . . . 1125
34.7.6
LPUART request register (LPUART_RQR) . . . . . . . . . . . . . . . . . . . . 1125
34.7.7
LPUART interrupt and status register (LPUART_ISR) . . . . . . . . . . . 1126
34.7.8
LPUART interrupt and status register [alternate] (LPUART_ISR) . . . 1130
34.7.9
LPUART interrupt flag clear register (LPUART_ICR) . . . . . . . . . . . . 1133
34.7.10 LPUART receive data register (LPUART_RDR) . . . . . . . . . . . . . . . . 1134
34.7.11 LPUART transmit data register (LPUART_TDR) . . . . . . . . . . . . . . . . 1134
34.7.12 LPUART prescaler register (LPUART_PRESC) . . . . . . . . . . . . . . . . 1135
34.7.13 LPUART register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1136
35
Serial peripheral interface / integrated interchip sound (SPI/I2S) . 1138
35.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1138
35.2
SPI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1138
35.3
I2S main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1139
35.4
SPI/I2S implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1139
35.5
SPI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1140
35.5.1
General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1140
35.5.2
Communications between one master and one slave . . . . . . . . . . . . 1141
35.5.3
Standard multislave communication . . . . . . . . . . . . . . . . . . . . . . . . . 1143
35.5.4
Multimaster communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1144
35.5.5
Slave select (NSS) pin management . . . . . . . . . . . . . . . . . . . . . . . . . 1145
35.5.6
Communication formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1146
35.5.7
Configuration of SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1148
35.5.8
Procedure for enabling SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1149
35.5.9
Data transmission and reception procedures . . . . . . . . . . . . . . . . . . 1149
35.5.10 SPI status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1159
35.5.11 SPI error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1160
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35.5.12 NSS pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1161
35.5.13 TI mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1161
35.5.14 CRC calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1162
35.6
SPI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1164
35.7
I2S functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1165
35.7.1
I2S general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1165
35.7.2
Supported audio protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1166
35.7.3
Start-up description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1173
35.7.4
Clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1175
35.7.5
I2S master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1178
35.7.6
I2S slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1179
35.7.7
I2S status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1181
35.7.8
I2S error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1182
35.7.9
DMA features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1183
35.8
I2S interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1183
35.9
SPI and I2S registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1184
35.9.1
SPI control register 1 (SPIx_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1184
35.9.2
SPI control register 2 (SPIx_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1186
35.9.3
SPI status register (SPIx_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1188
35.9.4
SPI data register (SPIx_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1190
35.9.5
SPI CRC polynomial register (SPIx_CRCPR) . . . . . . . . . . . . . . . . . . 1190
35.9.6
SPI Rx CRC register (SPIx_RXCRCR) . . . . . . . . . . . . . . . . . . . . . . . 1190
35.9.7
SPI Tx CRC register (SPIx_TXCRCR) . . . . . . . . . . . . . . . . . . . . . . . 1191
35.9.8
SPIx_I2S configuration register (SPIx_I2SCFGR) . . . . . . . . . . . . . . . 1191
35.9.9
SPIx_I2S prescaler register (SPIx_I2SPR) . . . . . . . . . . . . . . . . . . . . 1193
35.9.10 SPI/I2S register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1195
36
36/1290
Debug support (DBG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1196
36.1
DBG introduction and main features . . . . . . . . . . . . . . . . . . . . . . . . . . .1196
36.2
DBG use cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1196
36.3
DBG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1197
36.3.1
DBG block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1197
36.3.2
DBG pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1197
36.3.3
DBG reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1197
36.3.4
DBG power domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1198
36.3.5
DBG low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1198
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36.4
36.3.6
Serial-wire and JTAG debug port . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1198
36.3.7
JTAG debug port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1199
36.3.8
Serial-wire debug port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1202
Debug port (DP) registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1203
36.4.1
DP identification register (DP_DPIDR) . . . . . . . . . . . . . . . . . . . . . . . 1205
36.4.2
DP abort register (DP_ABORTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1205
36.4.3
DP control and status register (DP_CTRLSTATR) . . . . . . . . . . . . . . 1206
36.4.4
DP data link control register (DP_DLCR) . . . . . . . . . . . . . . . . . . . . . . 1208
36.4.5
DP target identification register (DP_TARGETIDR) . . . . . . . . . . . . . . 1209
36.4.6
DP data link protocol identification register (DP_DLPIDR) . . . . . . . . 1209
36.4.7
DP resend register (DP_RESENDR) . . . . . . . . . . . . . . . . . . . . . . . . . 1210
36.4.8
DP access port select register (DP_SELECTR) . . . . . . . . . . . . . . . . 1210
36.4.9
DP read buffer register (DP_BUFFR) . . . . . . . . . . . . . . . . . . . . . . . . 1211
36.4.10 DP target identification register (DP_TARGETSELR) . . . . . . . . . . . . 1211
36.4.11 DP register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . 1212
36.5
36.6
Access port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1213
36.5.1
AP control/status word register (AP_CSWR) . . . . . . . . . . . . . . . . . . . 1217
36.5.2
AP transfer address register (AP_TAR) . . . . . . . . . . . . . . . . . . . . . . . 1218
36.5.3
AP data read/write register (AP_DRWR) . . . . . . . . . . . . . . . . . . . . . . 1218
36.5.4
AP banked data registers x (AP_BDxR) . . . . . . . . . . . . . . . . . . . . . . 1219
36.5.5
AP base address register (AP_BASER) . . . . . . . . . . . . . . . . . . . . . . 1219
36.5.6
AP identification register (AP_IDR) . . . . . . . . . . . . . . . . . . . . . . . . . . 1220
36.5.7
AP register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . 1220
Data watchpoint and trace unit (DWT) . . . . . . . . . . . . . . . . . . . . . . . . . 1221
36.6.1
DWT control register (DWT_CTRLR) . . . . . . . . . . . . . . . . . . . . . . . . 1222
36.6.2
DWT cycle count register (DWT_CYCCNTR) . . . . . . . . . . . . . . . . . . 1224
36.6.3
DWT CPI count register (DWT_CPICNTR) . . . . . . . . . . . . . . . . . . . . 1224
36.6.4
DWT exception count register (DWT_EXCCNTR) . . . . . . . . . . . . . . . 1224
36.6.5
DWT sleep count register (DWT_SLPCNTR) . . . . . . . . . . . . . . . . . . 1225
36.6.6
DWT LSU count register (DWT_LSUCNTR) . . . . . . . . . . . . . . . . . . . 1225
36.6.7
DWT fold count register (DWT_FOLDCNTR) . . . . . . . . . . . . . . . . . . 1225
36.6.8
DWT program counter sample register (DWT_PCSR) . . . . . . . . . . . 1226
36.6.9
DWT comparator register x (DWT_COMPxR) . . . . . . . . . . . . . . . . . . 1226
36.6.10 DWT mask register x (DWT_MASKxR) . . . . . . . . . . . . . . . . . . . . . . . 1226
36.6.11 DWT function register x (DWT_FUNCTxR) . . . . . . . . . . . . . . . . . . . . 1227
36.6.12 DWT CoreSight peripheral identity register 4 (DWT_PIDR4) . . . . . . 1228
36.6.13 DWT CoreSight peripheral identity register 0 (DWT_PIDR0) . . . . . . 1228
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36.6.14 DWT CoreSight peripheral identity register 1 (DWT_PIDR1) . . . . . . 1229
36.6.15 DWT CoreSight peripheral identity register 2 (DWT_PIDR2) . . . . . . 1229
36.6.16 DWT CoreSight peripheral identity register 3 (DWT_PIDR3) . . . . . . 1230
36.6.17 DWT CoreSight component identity register 0 (DWT_CIDR0) . . . . . 1230
36.6.18 DWT CoreSight peripheral identity register 1 (DWT_CIDR1) . . . . . . 1230
36.6.19 DWT CoreSight component identity register 2 (DWT_CIDR2) . . . . . 1231
36.6.20 DWT CoreSight component identity register 3 (DWT_CIDR3) . . . . . 1231
36.6.21 DWT register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1232
36.7
ROM table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1234
36.7.1
ROM memory type register (ROM_MEMTYPER) . . . . . . . . . . . . . . . 1235
36.7.2
ROM CoreSight peripheral identity register 4 (ROM_PIDR4) . . . . . . 1236
36.7.3
ROM CoreSight peripheral identity register 0 (ROM_PIDR0) . . . . . . 1236
36.7.4
ROM CoreSight peripheral identity register 1 (ROM_PIDR1) . . . . . . 1237
36.7.5
ROM CoreSight peripheral identity register 2 (ROM_PIDR2) . . . . . . 1237
36.7.6
ROM CoreSight peripheral identity register 3 (ROM_PIDR3) . . . . . . 1238
36.7.7
ROM CoreSight component identity register 0 (ROM_CIDR0) . . . . . 1238
36.7.8
ROM CoreSight peripheral identity register 1 (ROM_CIDR1) . . . . . . 1239
36.7.9
ROM CoreSight component identity register 2 (ROM_CIDR2) . . . . . 1239
36.7.10 ROM CoreSight component identity register 3 (ROM_CIDR3) . . . . . 1240
36.7.11 ROM table register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1240
36.8
Breakpoint unit (FPB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1241
36.8.1
FPB control register (FPB_CTRLR) . . . . . . . . . . . . . . . . . . . . . . . . . . 1241
36.8.2
FPB remap register (FPB_REMAPR) . . . . . . . . . . . . . . . . . . . . . . . . 1242
36.8.3
FPB comparator register x (FPB_COMPxR) . . . . . . . . . . . . . . . . . . . 1242
36.8.4
FPB CoreSight peripheral identity register 4 (FPB_PIDR4) . . . . . . . 1243
36.8.5
FPB CoreSight peripheral identity register 0 (FPB_PIDR0) . . . . . . . 1244
36.8.6
FPB CoreSight peripheral identity register 1 (FPB_PIDR1) . . . . . . . 1244
36.8.7
FPB CoreSight peripheral identity register 2 (FPB_PIDR2) . . . . . . . 1245
36.8.8
FPB CoreSight peripheral identity register 3 (FPB_PIDR3) . . . . . . . 1245
36.8.9
FPB CoreSight component identity register 0 (FPB_CIDR0) . . . . . . 1246
36.8.10 FPB CoreSight peripheral identity register 1 (FPB_CIDR1) . . . . . . . 1246
36.8.11 FPB CoreSight component identity register 2 (FPB_CIDR2) . . . . . . 1247
36.8.12 FPB CoreSight component identity register 3 (FPB_CIDR3) . . . . . . 1247
36.8.13 FPB register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1247
36.9
38/1290
Instrumentation trace macrocell (ITM) . . . . . . . . . . . . . . . . . . . . . . . . . 1249
36.9.1
ITM stimulus register x (ITM_STIMRx) . . . . . . . . . . . . . . . . . . . . . . . 1249
36.9.2
ITM trace enable register (ITM_TER) . . . . . . . . . . . . . . . . . . . . . . . . 1250
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Contents
36.9.3
ITM trace privilege register (ITM_TPR) . . . . . . . . . . . . . . . . . . . . . . . 1250
36.9.4
ITM trace control register (ITM_TCR) . . . . . . . . . . . . . . . . . . . . . . . . 1251
36.9.5
ITM CoreSight peripheral identity register 4 (ITM_PIDR4) . . . . . . . . 1252
36.9.6
ITM CoreSight peripheral identity register 0 (ITM_PIDR0) . . . . . . . . 1252
36.9.7
ITM CoreSight peripheral identity register 1 (ITM_PIDR1) . . . . . . . . 1253
36.9.8
ITM CoreSight peripheral identity register 2 (ITM_PIDR2) . . . . . . . . 1253
36.9.9
ITM CoreSight peripheral identity register 3 (ITM_PIDR3) . . . . . . . . 1254
36.9.10 ITM CoreSight component identity register 0 (ITM_CIDR0) . . . . . . . 1254
36.9.11 ITM CoreSight peripheral identity register 1 (ITM_CIDR1) . . . . . . . . 1255
36.9.12 ITM CoreSight component identity register 2 (ITM_CIDR2) . . . . . . . 1255
36.9.13 ITM CoreSight component identity register 3 (ITM_CIDR3) . . . . . . . 1256
36.9.14 ITM register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1256
36.10 Trace port interface unit (TPIU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1257
36.10.1 TPIU supported port size register (TPIU_SSPSR) . . . . . . . . . . . . . . 1258
36.10.2 TPIU current port size register (TPIU_CSPSR) . . . . . . . . . . . . . . . . . 1258
36.10.3 TPIU asynchronous clock prescaler register (TPIU_ACPR) . . . . . . . 1258
36.10.4 TPIU selected pin protocol register (TPIU_SPPR) . . . . . . . . . . . . . . 1259
36.10.5 TPIU formatter and flush status register (TPIU_FFSR) . . . . . . . . . . . 1259
36.10.6 TPIU formatter and flush control register (TPIU_FFCR) . . . . . . . . . . 1260
36.10.7 TPIU formatter synchronization counter register (TPIU_FSCR) . . . . 1261
36.10.8 TPIU claim tag set register (TPIU_CLAIMSETR) . . . . . . . . . . . . . . . 1261
36.10.9 TPIU claim tag clear register (TPIU_CLAIMCLR) . . . . . . . . . . . . . . . 1262
36.10.10 TPIU device configuration register (TPIU_DEVIDR) . . . . . . . . . . . . . 1262
36.10.11 TPIU device type identifier register (TPIU_DEVTYPER) . . . . . . . . . . 1263
36.10.12 TPIU CoreSight peripheral identity register 4 (TPIU_PIDR4) . . . . . . 1263
36.10.13 TPIU CoreSight peripheral identity register 0 (TPIU_PIDR0) . . . . . . 1264
36.10.14 TPIU CoreSight peripheral identity register 1 (TPIU_PIDR1) . . . . . . 1264
36.10.15 TPIU CoreSight peripheral identity register 2 (TPIU_PIDR2) . . . . . . 1265
36.10.16 TPIU CoreSight peripheral identity register 3 (TPIU_PIDR3) . . . . . . 1265
36.10.17 TPIU CoreSight component identity register 0 (TPIU_CIDR0) . . . . . 1266
36.10.18 TPIU CoreSight peripheral identity register 1 (TPIU_CIDR1) . . . . . . 1266
36.10.19 TPIU CoreSight component identity register 2 (TPIU_CIDR2) . . . . . 1267
36.10.20 TPIU CoreSight component identity register 3 (TPIU_CIDR3) . . . . . 1267
36.10.21 TPIU register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1267
36.11 Microcontroller debug unit (DBGMCU) . . . . . . . . . . . . . . . . . . . . . . . . . 1269
36.11.1 DBGMCU identity code register (DBGMCU_IDCODER) . . . . . . . . . . 1270
36.11.2 DBGMCU configuration register (DBGMCU_CR) . . . . . . . . . . . . . . . 1270
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36.11.3 DBGMCU APB1 peripheral freeze register 1
(DBGMCU_APB1FZR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1271
36.11.4 DBGMCU APB1 peripheral freeze register 2
(DBGMCU_APB1FZR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1272
36.11.5 DBGMCU APB2 peripheral freeze register
(DBGMCU_APB2FZR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1272
36.11.6 DBGMCU register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1273
36.12 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1274
37
Device electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1275
37.1
Device electronic signature registers . . . . . . . . . . . . . . . . . . . . . . . . . . 1275
37.1.1
Unique device ID register (UID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1275
37.1.2
FLASH size data register (FLASHSIZE) . . . . . . . . . . . . . . . . . . . . . . 1276
37.1.3
Package data register (PKG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1277
37.1.4
IEEE 64-bit unique device ID register (UID64) . . . . . . . . . . . . . . . . . 1277
38
Important security notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1279
39
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1280
40/1290
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List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Table 49.
Table 50.
Device boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
SRAM erase conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Memory map and peripheral register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . 64
Flash memory - Single bank organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Number of wait states according to flash clock (HCLK3) frequency . . . . . . . . . . . . . . . . . . 72
Page erase overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Mass erase overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Errors in page-based row programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Option bytes organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Option loading control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Flash memory readout protection status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
RDP regression from level 1 to level 0 and memory erase. . . . . . . . . . . . . . . . . . . . . . . . . 87
Access status versus protection level and execution modes . . . . . . . . . . . . . . . . . . . . . . . 87
Flash interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Flash interface register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Sub-GHz internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Sub-GHz radio transmit high output power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
FSK mode intermediate frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
LoRa mode intermediate frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Spreading factor, chips/symbol and LoRa SNR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
LoRa bandwidth setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Coding rate and overhead ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Operation mode transition BUSY switching time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
PA optimal setting and operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Recommended CAD configuration settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
IRQ bit mapping and definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Image calibration for ISM bands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Command format Set_TcxoMode() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
RegTcxoTrim and Timeout bytes definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Sub-GHz radio SPI commands overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
SUBGHZ register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
PVM features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Low-power mode summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Functionalities depending on system operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
MCU and sub-GHz radio operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
LPRun . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
CPU wakeup versus system operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
LPSleep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Stop 0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Stop 2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
PWR register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Clock source stabilization times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Clock source frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
RM0461 Rev 10
41/1290
46
List of tables
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Table 83.
Table 84.
Table 85.
Table 86.
Table 87.
Table 88.
Table 89.
Table 90.
Table 91.
Table 92.
Table 93.
Table 94.
Table 95.
Table 96.
Table 97.
Table 98.
Table 99.
Table 100.
Table 101.
Table 102.
42/1290
RM0461
SPI2S2 I2S clock PLL configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Sub-GHz radio SPI clock configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Peripheral clock enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Low-power debug configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
RCC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
HSEM internal input/output signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Authorized AHB bus master ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
HSEM register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
Port bit configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
GPIOA register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
GPIOB register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
GPIOC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
GPIOH register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
SYSCFG register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
STM32WLEx peripherals interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
DMA1 and DMA2 implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
DMA internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
Programmable data width and endian behavior (when PINC = MINC = 1) . . . . . . . . . . . 361
DMA interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
DMA register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
DMAMUX instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
DMAMUX1: assignment of multiplexer inputs to resources . . . . . . . . . . . . . . . . . . . . . . . 377
DMAMUX1: assignment of trigger inputs to resources . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
DMAMUX1: assignment of synchronization inputs to resources . . . . . . . . . . . . . . . . . . . 378
DMAMUX signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
DMAMUX interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
DMAMUX register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
Vector table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
EXTI pin overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
EVG pin overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
Wake-up interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
EXTI event input configurations and register control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
Masking functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
EXTI register map sections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
EXTI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
CRC internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
CRC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419
ADC input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
ADC internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
External triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
Latency between trigger and start of conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428
Configuring the trigger polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435
tSAR timings depending on resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437
Analog watchdog comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446
Analog watchdog 1 channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446
Maximum output results vs N and M. Grayed values indicates truncation . . . . . . . . . . . . 451
ADC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456
ADC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475
DAC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479
DAC input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480
DAC internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480
DAC interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480
RM0461 Rev 10
RM0461
Table 103.
Table 104.
Table 105.
Table 106.
Table 107.
Table 108.
Table 109.
Table 110.
Table 111.
Table 112.
Table 113.
Table 114.
Table 115.
Table 116.
Table 117.
Table 118.
Table 119.
Table 120.
Table 121.
Table 122.
Table 123.
Table 124.
Table 125.
Table 126.
Table 127.
Table 128.
Table 129.
Table 130.
Table 131.
Table 132.
Table 133.
Table 134.
Table 135.
Table 136.
Table 137.
Table 138.
Table 139.
Table 140.
Table 141.
Table 142.
Table 143.
Table 144.
Table 145.
Table 146.
Table 147.
Table 148.
Table 149.
Table 150.
Table 151.
Table 152.
Table 153.
Table 154.
List of tables
Sample and refresh timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487
Channel output modes summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488
Effect of low-power modes on DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491
DAC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492
DAC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500
VREF buffer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502
VREFBUF register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504
COMP1 input plus assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506
COMP1 input minus assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507
COMP2 input plus assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507
COMP2 input minus assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507
Comparator behavior in the low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511
Interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511
COMP register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516
RNG internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518
RNG interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525
RNG configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526
Configuration selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527
RNG register map and reset map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531
AES internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533
CTR mode initialization vector definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549
GCM last block definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551
Initialization of AES_IVRx registers in GCM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552
Initialization of AES_IVRx registers in CCM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559
Key endianness in AES_KEYRx registers (128- or 256-bit key length) . . . . . . . . . . . . . . 564
AES interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567
Processing latency for ECB, CBC and CTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567
Processing latency for GCM and CCM (in clock cycles). . . . . . . . . . . . . . . . . . . . . . . . . . 568
AES register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578
Internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581
PKA integer arithmetic functions list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582
PKA prime field (Fp) elliptic curve functions list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582
Montgomery parameter computation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587
Modular addition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588
Modular subtraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588
Montgomery multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589
Modular exponentiation (normal mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590
Modular exponentiation (fast mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590
Modular inversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590
Modular reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591
Arithmetic addition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591
Arithmetic subtraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591
Arithmetic multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592
Arithmetic comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592
CRT exponentiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593
Point on elliptic curve Fp check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594
ECC Fp scalar multiplication. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594
ECC Fp scalar multiplication (Fast Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595
ECDSA sign - Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596
ECDSA sign - Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596
Extended ECDSA sign (extra outputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597
ECDSA verification (inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597
RM0461 Rev 10
43/1290
46
List of tables
Table 155.
Table 156.
Table 157.
Table 158.
Table 159.
Table 160.
Table 161.
Table 162.
Table 163.
Table 164.
Table 165.
Table 166.
Table 167.
Table 168.
Table 169.
Table 170.
Table 171.
Table 172.
Table 173.
Table 174.
Table 175.
Table 176.
Table 177.
Table 178.
Table 179.
Table 180.
Table 181.
Table 182.
Table 183.
Table 184.
Table 185.
Table 186.
Table 187.
Table 188.
Table 189.
Table 190.
Table 191.
Table 192.
Table 193.
Table 194.
Table 195.
Table 196.
Table 197.
Table 198.
Table 199.
Table 200.
Table 201.
Table 202.
Table 203.
Table 204.
Table 205.
44/1290
RM0461
ECDSA verification (outputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597
Family of supported curves for ECC operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598
Modular exponentiation computation times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600
ECC scalar multiplication computation times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600
ECDSA signature average computation times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600
ECDSA verification average computation times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601
Point on elliptic curve Fp check average computation times . . . . . . . . . . . . . . . . . . . . . . 601
Montgomery parameters average computation times. . . . . . . . . . . . . . . . . . . . . . . . . . . . 601
PKA interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601
PKA register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605
Behavior of timer outputs versus BRK/BRK2 inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648
Break protection disarming conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650
Counting direction versus encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656
TIM1 internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673
Output control bits for complementary OCx and OCxN channels with break feature . . . . 687
TIM1 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704
Counting direction versus encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 740
TIM2 internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758
Output control bit for standard OCx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 769
TIM2 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776
Break protection disarming conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 801
Output control bits for complementary OCx and OCxN channels with break feature
(TIM16/17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 818
TIM16/TIM17 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829
STM32WLEx LPTIM features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 831
LPTIM input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 832
LPTIM internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 833
LPTIM1 external trigger connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 833
LPTIM2 external trigger connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 833
LPTIM3 external trigger connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 834
LPTIM1 input 1 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 834
LPTIM1 input 2 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 834
LPTIM2 input 1 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 834
LPTIM3 input 1 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 834
Prescaler division ratios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 836
Encoder counting scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 843
Effect of low-power modes on the LPTIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846
Interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846
LPTIM register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 857
IWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 868
WWDG internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 870
WWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 874
RTC input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 877
RTC internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 877
RTC interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 878
PC13 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 878
RTC_OUT mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 880
Effect of low-power modes on RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 893
RTC pins functionality over modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 893
Interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 894
RTC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 916
TAMP input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 920
RM0461 Rev 10
RM0461
Table 206.
Table 207.
Table 208.
Table 209.
Table 210.
Table 211.
Table 212.
Table 213.
Table 214.
Table 215.
Table 216.
Table 217.
Table 218.
Table 219.
Table 220.
Table 221.
Table 222.
Table 223.
Table 224.
Table 225.
Table 226.
Table 227.
Table 228.
Table 229.
Table 230.
Table 231.
Table 232.
Table 233.
Table 234.
Table 235.
Table 236.
Table 237.
Table 238.
Table 239.
Table 240.
Table 241.
Table 242.
Table 243.
Table 245.
Table 246.
Table 247.
Table 248.
Table 249.
Table 250.
Table 251.
Table 252.
Table 253.
Table 254.
Table 255.
Table 256.
Table 257.
Table 258.
List of tables
TAMP internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 920
TAMP interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 920
Effect of low-power modes on TAMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 923
Interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 923
TAMP register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 934
I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 936
I2C input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 937
I2C internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 938
Comparison of analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 940
I²C-bus and SMBus specification data setup and hold times . . . . . . . . . . . . . . . . . . . . . . 942
I2C configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 946
I²C-bus and SMBus specification clock timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 957
Timing settings for fI2CCLK of 8 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 967
Timing settings for fI2CCLK of 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 967
SMBus timeout specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 969
SMBus with PEC configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 971
TIMEOUTA[11:0] for maximum tTIMEOUT of 25 ms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 972
TIMEOUTB[11:0] for maximum tLOW:SEXT and tLOW:MEXT of 8 ms . . . . . . . . . . . . . . . . . 972
TIMEOUTA[11:0] for maximum tIDLE of 50 µs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 972
Effect of low-power modes to I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 982
I2C interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 982
I2C register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 998
USART / LPUART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1001
USART/UART input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1004
USART internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1004
Noise detection from sampled data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1016
Tolerance of the USART receiver when BRR [3:0] = 0000. . . . . . . . . . . . . . . . . . . . . . . 1019
Tolerance of the USART receiver when BRR[3:0] is different from 0000 . . . . . . . . . . . . 1020
USART frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1025
Effect of low-power modes on the USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1048
USART interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1049
USART register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1083
USART / LPUART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1087
LPUART input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1089
LPUART internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1089
Error calculation for programmed baud rates at lpuart_ker_ck_pres = 32.768 kHz . . . . 1099
Error calculation for programmed baud rates at fCK = 100 MHz . . . . . . . . . . . . . . . . . . 1100
Tolerance of the LPUART receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1101
Effect of low-power modes on the LPUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1112
LPUART interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1113
LPUART register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1136
STM32WLEx SPI and SPI/I2S implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1139
SPI interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1164
Audio-frequency precision using 48 MHz clock derived from HSE. . . . . . . . . . . . . . . . . 1177
I2S interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1183
SPI/I2S register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1195
JTAG/Serial-wire debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1197
Single-wire trace port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1197
JTAG-DP data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1201
Packet request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1202
ACK response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1203
Data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1203
RM0461 Rev 10
45/1290
46
List of tables
Table 259.
Table 260.
Table 261.
Table 262.
Table 263.
Table 264.
Table 265.
Table 266.
Table 267.
Table 268.
Table 269.
Table 270.
46/1290
RM0461
Debug port registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1204
DP register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1212
MEM-AP registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1214
AP register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1220
DWT register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1232
ROM table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1234
ROM table register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1240
FPB register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1247
ITM register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1256
TPIU register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1267
DBGMCU register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1273
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1280
RM0461 Rev 10
RM0461
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Sequential 16 bits instructions execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Changing the RDP level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Sub-GHz radio system block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
High output power PA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Low output power PA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
LoRa packet frames format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Generic packet frames format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Sub-GHz RAM data buffer operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Sub-GHz radio operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Sub-GHz radio BUSY timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Receiver listening mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Supply configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Brownout reset waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
PVD thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
EOL thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Radio busy management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Simplified diagram of the reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
HSE32 clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
HSE32 TCXO control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
LSE clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Frequency measurement with TIM16 in capture mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Frequency measurement with TIM17 in capture mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 242
HSEM block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Procedure state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Interrupt state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
Basic structure of a standard I/O port bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
Basic structure of a 5V-tolerant I/O port bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
Input floating/pull-up/pull-down configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
Alternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
High impedance analog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
DMA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354
DMAMUX block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
Synchronization mode of the DMAMUX request line multiplexer channel . . . . . . . . . . . . 382
Event generation of the DMA request line multiplexer channel . . . . . . . . . . . . . . . . . . . . 383
EXTI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
Configurable event trigger logic CPU wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
Direct event trigger logic CPU wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
CRC calculation unit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
ADC calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
Calibration factor forcing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
Enabling/disabling the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426
ADC clock scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427
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Figure 49. ADC connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429
Figure 50. Analog-to-digital conversion time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434
Figure 51. ADC conversion timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434
Figure 52. Stopping an ongoing conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435
Figure 53. Single conversions of a sequence, software trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438
Figure 54. Continuous conversion of a sequence, software trigger . . . . . . . . . . . . . . . . . . . . . . . . . . 438
Figure 55. Single conversions of a sequence, hardware trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
Figure 56. Continuous conversions of a sequence, hardware trigger . . . . . . . . . . . . . . . . . . . . . . . . 439
Figure 57. Data alignment and resolution (oversampling disabled: OVSE = 0). . . . . . . . . . . . . . . . . 440
Figure 58. Example of overrun (OVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441
Figure 59. Wait mode conversion (continuous mode, software trigger). . . . . . . . . . . . . . . . . . . . . . . 444
Figure 60. Behavior with WAIT = 0, AUTOFF = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445
Figure 61. Behavior with WAIT = 1, AUTOFF = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445
Figure 62. Analog watchdog guarded area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446
Figure 63. ADC_AWDx_OUT signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448
Figure 64. ADC_AWDx_OUT signal generation (AWDx flag not cleared by software) . . . . . . . . . . . 448
Figure 65. ADC_AWDx_OUT signal generation (on a single channel) . . . . . . . . . . . . . . . . . . . . . . . 449
Figure 66. Analog watchdog threshold update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449
Figure 67. 20-bit to 16-bit result truncation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450
Figure 68. Numerical example with 5-bit shift and rounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450
Figure 69. Triggered oversampling mode (TOVS bit = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452
Figure 70. Temperature sensor and VREFINT channel block diagram . . . . . . . . . . . . . . . . . . . . . . 453
Figure 71. VBAT channel block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
Figure 72. DAC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479
Figure 73. Data registers in single DAC channel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481
Figure 74. Timing diagram for conversion with trigger disabled TEN = 0 . . . . . . . . . . . . . . . . . . . . . 482
Figure 75. DAC LFSR register calculation algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484
Figure 76. DAC conversion (SW trigger enabled) with LFSR wave generation. . . . . . . . . . . . . . . . . 484
Figure 77. DAC triangle wave generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485
Figure 78. DAC conversion (SW trigger enabled) with triangle wave generation . . . . . . . . . . . . . . . 485
Figure 79. DAC sample and hold mode phase diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488
Figure 80. Comparator block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506
Figure 81. Window mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509
Figure 82. Comparator hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509
Figure 83. Comparator output blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510
Figure 84. RNG block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518
Figure 85. NIST SP800-90B entropy source model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519
Figure 86. RNG initialization overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522
Figure 87. AES block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533
Figure 88. ECB encryption and decryption principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535
Figure 89. CBC encryption and decryption principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
Figure 90. CTR encryption and decryption principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537
Figure 91. GCM encryption and authentication principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538
Figure 92. GMAC authentication principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538
Figure 93. CCM encryption and authentication principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539
Figure 94. Example of suspend mode management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543
Figure 95. ECB encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544
Figure 96. ECB decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544
Figure 97. CBC encryption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545
Figure 98. CBC decryption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545
Figure 99. ECB/CBC encryption (Mode 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546
Figure 100. ECB/CBC decryption (Mode 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547
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Figure 101. Message construction in CTR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548
Figure 102. CTR encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549
Figure 103. CTR decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549
Figure 104. Message construction in GCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551
Figure 105. GCM authenticated encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552
Figure 106. Message construction in GMAC mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556
Figure 107. GMAC authentication mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556
Figure 108. Message construction in CCM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557
Figure 109. CCM mode authenticated encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559
Figure 110. 128-bit block construction with respect to data swap . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563
Figure 111. DMA transfer of a 128-bit data block during input phase . . . . . . . . . . . . . . . . . . . . . . . . . 565
Figure 112. DMA transfer of a 128-bit data block during output phase . . . . . . . . . . . . . . . . . . . . . . . . 566
Figure 113. PKA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581
Figure 114. Advanced-control timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608
Figure 115. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 610
Figure 116. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 610
Figure 117. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612
Figure 118. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612
Figure 119. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613
Figure 120. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613
Figure 121. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . . 614
Figure 122. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . . . . . 614
Figure 123. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616
Figure 124. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616
Figure 125. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617
Figure 126. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617
Figure 127. Counter timing diagram, update event when repetition counter is not used . . . . . . . . . . . 618
Figure 128. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . . . . . . . . . . . 619
Figure 129. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 620
Figure 130. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . . 620
Figure 131. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621
Figure 132. Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . . . . . . . . . 621
Figure 133. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . . . . . . . . . . 622
Figure 134. Update rate examples depending on mode and TIMx_RCR register settings . . . . . . . . . 623
Figure 135. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624
Figure 136. TIM1 ETR input circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624
Figure 137. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 625
Figure 138. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626
Figure 139. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627
Figure 140. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627
Figure 141. Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628
Figure 142. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 629
Figure 143. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629
Figure 144. Output stage of capture/compare channel (channel 1, idem ch. 2 and 3) . . . . . . . . . . . . 630
Figure 145. Output stage of capture/compare channel (channel 4). . . . . . . . . . . . . . . . . . . . . . . . . . . 630
Figure 146. Output stage of capture/compare channel (channel 5, idem ch. 6) . . . . . . . . . . . . . . . . . 631
Figure 147. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633
Figure 148. Output compare mode, toggle on OC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635
Figure 149. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636
Figure 150. Center-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637
Figure 151. Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . . . . . . . . . . . . . . . 639
Figure 152. Combined PWM mode on channel 1 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640
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Figure 153. 3-phase combined PWM signals with multiple trigger pulses per period . . . . . . . . . . . . . 641
Figure 154. Complementary output with dead-time insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642
Figure 155. Dead-time waveforms with delay greater than the negative pulse . . . . . . . . . . . . . . . . . . 642
Figure 156. Dead-time waveforms with delay greater than the positive pulse. . . . . . . . . . . . . . . . . . . 643
Figure 157. Break and Break2 circuitry overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645
Figure 158. Various output behavior in response to a break event on BRK (OSSI = 1) . . . . . . . . . . . 647
Figure 159. PWM output state following BRK and BRK2 pins assertion (OSSI=1) . . . . . . . . . . . . . . . 648
Figure 160. PWM output state following BRK assertion (OSSI=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 649
Figure 161. Output redirection (BRK2 request not represented) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650
Figure 162. Clearing TIMx OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651
Figure 163. 6-step generation, COM example (OSSR=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652
Figure 164. Example of one pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653
Figure 165. Retriggerable one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655
Figure 166. Example of counter operation in encoder interface mode. . . . . . . . . . . . . . . . . . . . . . . . . 656
Figure 167. Example of encoder interface mode with TI1FP1 polarity inverted. . . . . . . . . . . . . . . . . . 657
Figure 168. Measuring time interval between edges on 3 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658
Figure 169. Example of Hall sensor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 660
Figure 170. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661
Figure 171. Control circuit in Gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 662
Figure 172. Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663
Figure 173. Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . 664
Figure 174. General-purpose timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708
Figure 175. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 710
Figure 176. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 710
Figure 177. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711
Figure 178. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712
Figure 179. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712
Figure 180. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713
Figure 181. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded). . . . . 713
Figure 182. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . . . . . 714
Figure 183. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715
Figure 184. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715
Figure 185. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 716
Figure 186. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 716
Figure 187. Counter timing diagram, Update event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717
Figure 188. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . . . . . . . . . . . . 718
Figure 189. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719
Figure 190. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . . 719
Figure 191. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720
Figure 192. Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . . . . . . . . . 720
Figure 193. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . . . . . . . . . . 721
Figure 194. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 722
Figure 195. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722
Figure 196. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723
Figure 197. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724
Figure 198. Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725
Figure 199. Capture/Compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . 725
Figure 200. Capture/Compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726
Figure 201. Output stage of Capture/Compare channel (channel 1) . . . . . . . . . . . . . . . . . . . . . . . . . . 726
Figure 202. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728
Figure 203. Output compare mode, toggle on OC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 730
Figure 204. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731
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Figure 205. Center-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 733
Figure 206. Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . . . . . . . . . . . . . . . 734
Figure 207. Combined PWM mode on channels 1 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735
Figure 208. Clearing TIMx OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736
Figure 209. Example of one-pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737
Figure 210. Retriggerable one-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739
Figure 211. Example of counter operation in encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . 740
Figure 212. Example of encoder interface mode with TI1FP1 polarity inverted . . . . . . . . . . . . . . . . . 741
Figure 213. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742
Figure 214. Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743
Figure 215. Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744
Figure 216. Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . 745
Figure 217. Master/Slave timer example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746
Figure 218. Master/slave connection example with 1 channel only timers . . . . . . . . . . . . . . . . . . . . . 746
Figure 219. Gating TIM2 with OC1REF of TIM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747
Figure 220. Gating TIM2 with Enable of TIM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 748
Figure 221. Triggering TIM2 with update of TIM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749
Figure 222. Triggering TIM2 with Enable of TIM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749
Figure 223. TIM16/TIM17 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 780
Figure 224. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 782
Figure 225. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 782
Figure 226. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 784
Figure 227. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 784
Figure 228. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 785
Figure 229. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 785
Figure 230. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not
preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 786
Figure 231. Counter timing diagram, update event when ARPE=1 (TIMx_ARR
preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 786
Figure 232. Update rate examples depending on mode and TIMx_RCR register settings . . . . . . . . . 788
Figure 233. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 789
Figure 234. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 789
Figure 235. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 790
Figure 236. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 791
Figure 237. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 791
Figure 238. Output stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 792
Figure 239. Output compare mode, toggle on OC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 795
Figure 240. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 796
Figure 241. Complementary output with dead-time insertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 797
Figure 242. Dead-time waveforms with delay greater than the negative pulse. . . . . . . . . . . . . . . . . . 797
Figure 243. Dead-time waveforms with delay greater than the positive pulse. . . . . . . . . . . . . . . . . . . 798
Figure 244. Output behavior in response to a break . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800
Figure 245. Output redirection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 802
Figure 246. 6-step generation, COM example (OSSR=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803
Figure 247. Example of one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804
Figure 248. Low-power timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 832
Figure 249. Glitch filter timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 836
Figure 250. LPTIM output waveform, single-counting mode configuration
when repetition register content is different than zero (with PRELOAD = 1) . . . . . . . . . . 837
Figure 251. LPTIM output waveform, single-counting mode configuration
and Set-once mode activated (WAVE bit is set) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 838
Figure 252. LPTIM output waveform, Continuous counting mode configuration . . . . . . . . . . . . . . . . . 838
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Figure 253. Waveform generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 840
Figure 254. Encoder mode counting sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 844
Figure 255. Continuous counting mode when repetition register LPTIM_RCR
different from zero (with PRELOAD = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 845
Figure 256. IRTIM internal hardware connections with TIM16 and TIM17
. . . . . . . . . . . . . . . . . . . 859
Figure 257. Independent watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 860
Figure 258. Watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 870
Figure 259. Window watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 871
Figure 260. RTC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 876
Figure 261. TAMP block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 919
Figure 262. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 937
Figure 263. I²C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 939
Figure 264. Setup and hold timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 941
Figure 265. I2C initialization flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 943
Figure 266. Data reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 944
Figure 267. Data transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 945
Figure 268. Target initialization flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 948
Figure 269. Transfer sequence flow for I2C target transmitter, NOSTRETCH = 0 . . . . . . . . . . . . . . . 950
Figure 270. Transfer sequence flow for I2C target transmitter, NOSTRETCH = 1 . . . . . . . . . . . . . . . 951
Figure 271. Transfer bus diagrams for I2C target transmitter (mandatory events only) . . . . . . . . . . . 952
Figure 272. Transfer sequence flow for I2C target receiver, NOSTRETCH = 0 . . . . . . . . . . . . . . . . . 953
Figure 273. Transfer sequence flow for I2C target receiver, NOSTRETCH = 1 . . . . . . . . . . . . . . . . . 954
Figure 274. Transfer bus diagrams for I2C target receiver
(mandatory events only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 954
Figure 275. Controller clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 956
Figure 276. Controller initialization flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 958
Figure 277. 10-bit address read access with HEAD10R = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 958
Figure 278. 10-bit address read access with HEAD10R = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 959
Figure 279. Transfer sequence flow for I2C controller transmitter, N ≤ 255 bytes. . . . . . . . . . . . . . . . 960
Figure 280. Transfer sequence flow for I2C controller transmitter, N > 255 bytes. . . . . . . . . . . . . . . . 961
Figure 281. Transfer bus diagrams for I2C controller transmitter
(mandatory events only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 962
Figure 282. Transfer sequence flow for I2C controller receiver, N ≤ 255 bytes . . . . . . . . . . . . . . . . . 964
Figure 283. Transfer sequence flow for I2C controller receiver, N > 255 bytes. . . . . . . . . . . . . . . . . . 965
Figure 284. Transfer bus diagrams for I2C controller receiver
(mandatory events only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 966
Figure 285. Timeout intervals for tLOW:SEXT, tLOW:MEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 970
Figure 286. Transfer sequence flow for SMBus target transmitter N bytes + PEC . . . . . . . . . . . . . . . 973
Figure 287. Transfer bus diagram for SMBus target transmitter (SBC = 1). . . . . . . . . . . . . . . . . . . . . 974
Figure 288. Transfer sequence flow for SMBus target receiver N bytes + PEC . . . . . . . . . . . . . . . . . 975
Figure 289. Bus transfer diagrams for SMBus target receiver (SBC = 1) . . . . . . . . . . . . . . . . . . . . . . 976
Figure 290. Bus transfer diagrams for SMBus controller transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . 977
Figure 291. Bus transfer diagrams for SMBus controller receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . 979
Figure 292. USART block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1002
Figure 293. Word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1005
Figure 294. Configurable stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1007
Figure 295. TC/TXE behavior when transmitting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1010
Figure 296. Start bit detection when oversampling by 16 or 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1011
Figure 297. usart_ker_ck clock divider block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1014
Figure 298. Data sampling when oversampling by 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1015
Figure 299. Data sampling when oversampling by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1016
Figure 300. Mute mode using Idle line detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1023
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Figure 301. Mute mode using address mark detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1024
Figure 302. Break detection in LIN mode (11-bit break length - LBDL bit is set) . . . . . . . . . . . . . . . . 1027
Figure 303. Break detection in LIN mode vs. Framing error detection. . . . . . . . . . . . . . . . . . . . . . . . 1028
Figure 304. USART example of synchronous master transmission. . . . . . . . . . . . . . . . . . . . . . . . . . 1029
Figure 305. USART data clock timing diagram in synchronous master mode
(M bits = 00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1029
Figure 306. USART data clock timing diagram in synchronous master mode
(M bits = 01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1030
Figure 307. USART data clock timing diagram in synchronous slave mode
(M bits = 00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1031
Figure 308. ISO 7816-3 asynchronous protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1033
Figure 309. Parity error detection using the 1.5 stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1035
Figure 310. IrDA SIR ENDEC block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1039
Figure 311. IrDA data modulation (3/16) - normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1039
Figure 312. Transmission using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1041
Figure 313. Reception using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1042
Figure 314. Hardware flow control between 2 USARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1042
Figure 315. RS232 RTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1043
Figure 316. RS232 CTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1044
Figure 317. Wake-up event verified (wake-up event = address match, FIFO disabled) . . . . . . . . . . 1047
Figure 318. Wake-up event not verified (wake-up event = address match,
FIFO disabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1047
Figure 319. LPUART block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1088
Figure 320. LPUART word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1091
Figure 321. Configurable stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1093
Figure 322. TC/TXE behavior when transmitting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1095
Figure 323. lpuart_ker_ck clock divider block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1098
Figure 324. Mute mode using Idle line detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1102
Figure 325. Mute mode using address mark detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1103
Figure 326. Transmission using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1105
Figure 327. Reception using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1106
Figure 328. Hardware flow control between 2 LPUARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1107
Figure 329. RS232 RTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1107
Figure 330. RS232 CTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1108
Figure 331. Wake-up event verified (wake-up event = address match,
FIFO disabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1111
Figure 332. Wake-up event not verified (wake-up event = address match,
FIFO disabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1111
Figure 333. SPI block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1140
Figure 334. Full-duplex single master/ single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1141
Figure 335. Half-duplex single master/ single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1142
Figure 336. Simplex single master/single slave application (master in transmit-only/
slave in receive-only mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1143
Figure 337. Master and three independent slaves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1144
Figure 338. Multimaster application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1145
Figure 339. Hardware/software slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1146
Figure 340. Data clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1147
Figure 341. Data alignment when data length is not equal to 8-bit or 16-bit . . . . . . . . . . . . . . . . . . . 1148
Figure 342. Packing data in FIFO for transmission and reception . . . . . . . . . . . . . . . . . . . . . . . . . . . 1152
Figure 343. Master full-duplex communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1155
Figure 344. Slave full-duplex communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1156
Figure 345. Master full-duplex communication with CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1157
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Figure 346. Master full-duplex communication in packed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1158
Figure 347. NSSP pulse generation in Motorola SPI master mode . . . . . . . . . . . . . . . . . . . . . . . . . . 1161
Figure 348. TI mode transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1162
Figure 349. I2S block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1165
Figure 350. I2S Philips protocol waveforms (16/32-bit full accuracy). . . . . . . . . . . . . . . . . . . . . . . . . 1167
Figure 351. I2S Philips standard waveforms (24-bit frame) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1167
Figure 352. Transmitting 0x8EAA33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1168
Figure 353. Receiving 0x8EAA33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1168
Figure 354. I2S Philips standard (16-bit extended to 32-bit packet frame) . . . . . . . . . . . . . . . . . . . . 1168
Figure 355. Example of 16-bit data frame extended to 32-bit channel frame . . . . . . . . . . . . . . . . . . 1168
Figure 356. MSB Justified 16-bit or 32-bit full-accuracy length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1169
Figure 357. MSB justified 24-bit frame length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1169
Figure 358. MSB justified 16-bit extended to 32-bit packet frame . . . . . . . . . . . . . . . . . . . . . . . . . . . 1170
Figure 359. LSB justified 16-bit or 32-bit full-accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1170
Figure 360. LSB justified 24-bit frame length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1170
Figure 361. Operations required to transmit 0x3478AE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1171
Figure 362. Operations required to receive 0x3478AE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1171
Figure 363. LSB justified 16-bit extended to 32-bit packet frame . . . . . . . . . . . . . . . . . . . . . . . . . . . 1171
Figure 364. Example of 16-bit data frame extended to 32-bit channel frame . . . . . . . . . . . . . . . . . . 1172
Figure 365. PCM standard waveforms (16-bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1172
Figure 366. PCM standard waveforms (16-bit extended to 32-bit packet frame). . . . . . . . . . . . . . . . 1173
Figure 367. Start sequence in master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1174
Figure 368. Audio sampling frequency definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1175
Figure 369. I2S clock generator architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1175
Figure 370. Block diagram of debug support infrastructure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1197
Figure 371. JTAG TAP state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1200
Figure 372. Debug and access port connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1213
Figure 373. Debugger connection to debug components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1216
Figure 374. CPU CoreSight topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1235
Figure 375. TPIU architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1257
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1
Documentation conventions
1.1
General information
The STM32WLEx devices embed an Arm®(a) Cortex®-M4 with DSP.
1.2
List of abbreviations for registers
The following abbreviations(b) are used in register descriptions:
read/write (rw)
Software can read and write to this bit.
read-only (r)
Software can only read this bit.
write-only (w)
Software can only write to this bit. Reading this bit returns the reset value.
read/clear write0 (rc_w0)
Software can read as well as clear this bit by writing 0. Writing 1 has no
effect on the bit value.
read/clear write1 (rc_w1)
Software can read as well as clear this bit by writing 1. Writing 0 has no
effect on the bit value.
read/clear write (rc_w)
Software can read as well as clear this bit by writing to the register. The
value written to this bit is not important.
read/clear by read (rc_r)
Software can read this bit. Reading this bit automatically clears it to 0.
Writing this bit has no effect on the bit value.
read/set by read (rs_r)
Software can read this bit. Reading this bit automatically sets it to 1.
Writing this bit has no effect on the bit value.
read/set (rs)
Software can read as well as set this bit. Writing 0 has no effect on the bit
value.
read/write once (rwo)
Software can only write once to this bit and can also read it at any time.
Only a reset can return the bit to its reset value.
toggle (t)
The software can toggle this bit by writing 1. Writing 0 has no effect.
read-only write trigger (rt_w1) Software can read this bit. Writing 1 triggers an event but has no effect on
the bit value.
Reserved (Res.)
1.3
Reserved bit, must be kept at reset value.
Register reset value
Bits (binary notation) or bits nibbles (hexadecimal notation) of which the reset value is
undefined are marked as X.
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
b. This is an exhaustive list of all abbreviations applicable to STMicroelectronics microcontrollers, some of
them may not be used in the current document.
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Bits (binary notation) or bits nibbles (hexadecimal notation) of which the reset value is
unmodified are marked as U.
1.4
Glossary
This section gives a brief definition of acronyms and abbreviations used in this document:
•
1.5
Word: data of 32-bit length.
•
Half-word: data of 16-bit length.
•
Byte: data of 8-bit length.
•
Option bytes: device configuration bits stored in the flash memory.
•
AHB: advanced high-performance bus.
Availability of peripherals
For availability of peripherals and their number across all devices, refer to the particular
device datasheet.
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Memory and bus architecture
Memory and bus architecture
The following definition is used in this section:
•
2.1
CPU = Arm Cortex-M4 with MPU and DSP
System architecture
The main system consists of a 32-bit multilayer AHB bus matrix that interconnects the
following masters and slaves:
•
•
Five masters:
–
CPU core I-bus
–
CPU core D-bus
–
CPU core S-bus
–
DMA1
–
DMA2
Eight slaves:
–
Internal flash memory on the CPU Code bus
–
Internal flash memory on CPU DCode bus
–
Internal SRAM1 (up to 32 Kbytes, size depending on the device, refer to the
datasheet)
–
Internal SRAM2 (up to 32 Kbytes, size depending on the device, refer to the
datasheet)
–
AHB1 peripherals including AHB to APB bridges and APB peripherals (connected
to APB1 and APB2)
–
AHB2 peripherals
–
AHB3 peripherals including AHB to APB bridges and APB peripherals (connected
to APB3)
The bus matrix provides access from a master to a slave, enabling concurrent access and
efficient operation even when several high-speed peripherals work simultaneously.
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This architecture is shown in the figure below.
Figure 1. System architecture
CPU
Arm
Cortex-M4
S0
S1
S2
DMA1
DMA2
S4
S5
M0 M1
Flash
memory
arbiter
FLASH
M3
SRAM1
M4
SRAM2
M5
AHB1
M6
AHB2
M7
AHB3
when remapped
Bus matrix
MSv60753V1
2.1.1
S0: CPU I-bus
This bus connects the instruction bus of the CPU core to the bus matrix. This bus is used by
the core to fetch instructions. The targets of this bus are the internal flash memory,
SRAM1and SRAM2.
2.1.2
S1: CPU D-bus
This bus connects the data bus of the CPU core to the bus matrix. This bus is used by the
core for literal load and debug access. The targets of this bus are the internal flash memory,
SRAM1 and SRAM2.
2.1.3
S2: CPU S-bus
This bus connects the system bus of the CPU core to the bus matrix. This bus is used by the
core to access data located in a peripheral or SRAM area. The targets of this bus are the
SRAM1, SRAM2, the AHB1 peripherals including the APB1 and APB2 peripherals, the
AHB2 peripherals and the AHB3 peripherals including the APB3.
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2.1.4
S4, S5: DMA-bus
These buses connect the AHB master interface of the DMAs to the bus matrix.The targets of
this bus are the internal flash memory, SRAM1, SRAM2 the AHB1 peripherals including the
APB1 and APB2 peripherals, the AHB2 peripherals and the AHB3 peripherals including the
APB3 peripherals.
AHB/APB bridges
The two bridges AHB to APB1 and AHB to ABP2 provide full synchronous connections
between the AHB1 and the two APB buses, allowing flexible selection of the peripheral
frequency.
The bridge AHB to APB3 provides full synchronous connections between the AHB and the
APB bus, allowing flexible selection of the frequency between the AHB and peripherals.
Refer to Section 2.4.2: Memory map and register boundary addresses for the address
mapping of the peripherals connected to this bridge.
After each device reset, all peripheral clocks are disabled, except for the SRAM1/2 and the
flash memory interface. Before using a peripheral, its clock must be enabled in the
RCC_AHBxENR and RCC_APBxENR registers.
Note:
When a 16- or 8-bit access is performed on an APB register, the access is transformed into
a 32-bit access: the bridge duplicates the 16- or 8-bit data to feed the 32-bit vector.
2.2
Boot configuration
Three different CPU boot modes can be selected through the BOOT0 pin and nBOOT1 bit
in the user options.
Boot is furthermore conditioned by the CPU boot lock enable and the user flash memory
empty check, as shown in the table below.
Table 1. Device boot mode
x
1
0
1
1
x
0
User Flash empty
1
Valid options
0
BOOT_LOCK
nSWBOOT0
option
x
PH3/BOOT0
nBOOT0 option
nBOOT1 option
Boot mode selection
CPU aliasing space
Hold
x
No
SRAM1 boot
x
Hold
0
SRAM1 boot
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Table 1. Device boot mode (continued)
1
x
1
0
x
x
1
0
x
Valid options
BOOT_LOCK
0
1
0
1
1
x
CPU aliasing space
0
User Flash boot
1
System Flash boot
System Flash boot
x
x
0
User Flash empty
x
nSWBOOT0
option
PH3/BOOT0
nBOOT0 option
nBOOT1 option
Boot mode selection
0
0
Yes
SRAM1 boot
User Flash boot
0
User Flash boot
1
System Flash boot
System Flash boot
x
x
SRAM1 boot
1
User Flash boot
Values on BOOT0 and BOOT1 are latched after a reset. It is up to the user to provide the
correct value for the required boot mode.
BOOT0 and BOOT1 are also re-sampled when exiting Standby mode. Consequently they
must be kept in the required boot mode. After the startup delay, the CPU fetches the top-ofstack from address 0x0000 0000, then starts code execution from the boot memory at
0x0000 0004.
Depending on the selected boot mode, main flash memory, system flash memory and
SRAM1 are accessible as follows:
•
Boot from main flash memory
The main flash memory is aliased in the CPU boot memory space at address 0x0000
0000 and is also still accessible from its physical address 0x0800 0000. In other words,
the flash memory contents can be accessed starting from address 0x0000 0000 or
0x0800 0000.
•
Boot from system flash memory
The system flash memory is aliased in the CPU boot memory space at address 0x0000
0000 and is also still accessible from its physical address 0x1FFF 0000.
•
Boot from SRAM memory
The SRAM memory is aliased in the CPU boot memory space at address 0x0000 0000
and is also still accessible from its physical address 0x2000 0000.
CPU SRAM physical remap
Following CPU boot, the application software can modify the memory map at address
0x0000 0000. This modification is performed by programming the SYSCFG memory remap
register (SYSCFG_MEMRMP) in the SYSCFG controller.
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The following memories can be remapped:
•
Main flash memory
•
System flash memory
•
SRAM memory
Embedded bootloader
The embedded bootloader is located in the system flash memory, programmed by
STMicroelectronics during production. It is used to program the flash memory using one of
the following device interfaces:
•
USART1 on pins PA9 and PA10
•
USART2 on pins PA2 and PA3
•
SPI1 on pins PA4, PA5, PA6 and PA7
•
SPI2S2 on pins PB12, PB13, PB14 and PB15
The embedded bootloader runs on the CPU and can be used to load content in memory
areas.
2.3
SRAM erase
SRAM1, SRAM2 and PKA SRAM provide an SRAM erase feature.
These SRAMs are erased under the conditions detailed in the table below.
Table 2. SRAM erase conditions
Condition
SRAM1(1)
SRAM2(1)
PKA SRAM(2)
System reset(3) (user option SRAM_RST = 1)
Retained
Retained
Hardware erased
System reset (user option SRAM_RST = 0)
Hardware erased
Hardware erased
Hardware erased
OBL with invalid user options
Hardware erased
Hardware erased
Hardware erased
RDP regression from 1 to 0, on OPTSTRT.
Hardware erased(4)
Hardware erased
Hardware erased
Retained
Hardware erased
Hardware erased
Retained
Hardware erased
Retained
Tamper
(5)
SYSCFG_SCSR SRAM2ER
1. An ongoing SRAM1 or SRAM2 erase can be monitored by SYSCFG_SCSR.SRAMBSY flag.
2. An ongoing PKA SRAM erase can be monitored by SYSCFG_SCSR.PKASRAMBSY flag.
3. POR, NRST, and wake-up from Standby.
4. For more details, see Table 12: RDP regression from level 1 to level 0 and memory erase.
5. To be able to debug without SRAM erase on tamper, especially ITAM6 debug access, the tamper erase must be disabled in
the TAMP by firmware.
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2.4
Memory organization
2.4.1
Introduction
Program memory, data memory, registers and I/O ports are organized within the same linear
4-Gbyte address space.
The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word
is considered the word’s least significant byte and the highest numbered byte the most
significant.
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2.4.2
Memory map and register boundary addresses
Figure 2. Memory map
0xFFFF FFFF
0x5801 FFFF
CPU
internal
peripherals
APB3
0x5801 0000
AHB3
0x5800 0000
0xE000 0000
AHB2
0x4800 0000
AHB1
0x4802 0000
APB2
0x4001 0000
APB1
0x4000 0000
0x2000 FFFF
SRAM2
0x2000 8000
SRAM1
0x2000 0000
Peripherals
Reserved
Option bytes
0x4000 0000
0x1FFF 7800
0x1FFF 7400
0x1FFF 7000
SRAM
Reserved
OTP area
System Flash
Reserved
0x2000 0000
0x1000 7FFF
0x1000 0000
SRAM2
Reserved
0x0803 FFFF
CODE
Flash
0x0800 0000
0x0000 0000
0x0003 FFFF
Reserved
0x0000 0000
Reserved
CPU
Flash, system
memory or
SRAM1,
depending on
BOOT
configuration
MSv60755V1
Any memory area not allocated to on-chip memories and peripherals is considered
“Reserved”.
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The table below details the boundary addresses of peripherals available in the device.
Table 3. Memory map and peripheral register boundary addresses
Bus
APB3
Boundary address
Size
(bytes)
Peripheral
0x5801 0400 - 0x5801 FFFF
-
Reserved
0x5801 0000 - 0x5801 03FF
1K
SUBGHZSPI
0x5800 4400 - 0x5800 FFFF
-
Reserved
-
0x5800 4000 - 0x5800 43FF
1K
FLASH
Section 3.8.14: FLASH register map
0x5800 3400 - 0x5800 3FFF
0x5800 2400 - 0x5800 33FF
AHB2
AHB1
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Section 35.9.10: SPI/I2S register map
PKA continue
8K
PKA RAM
0x5800 2000 - 0x5800 23FF
AHB3
Peripheral register map
Section 22.7.5: PKA register map
PKA
0x5800 1C00 - 0x5800 1FFF
-
Reserved
-
0x5800 1800 - 0x5800 1BFF
1K
AES
Section 21.7.18: AES register map
0x5800 1400 - 0x5800 17FF
1K
HSEM
Section 7.4.9: HSEM register map
0x5800 1000 - 0x5800 13FF
1K
True RNG
Section 20.7.5: RNG register map
0x5800 0C00 - 0x5800 0FFF
-
Reserved
-
0x5800 0800 - 0x5800 0BFF
1K
EXTI
Section 14.6.12: EXTI register map
0x5800 0400 - 0x5800 07FF
1K
PWR
Section 5.5.19: PWR register map
0x5800 0000 - 0x5800 03FF
1K
RCC
Section 6.4.33: RCC register map
0x4800 2000 - 0x57FF FFFF
-
Reserved
-
0x4800 1C00 - 0x4800 1FFF
Section 8.4.36: GPIOH register map
0x4800 0C00 - 0x4800 1BFF
Reserved
0x4800 0800 - 0x4800 0BFF
8K
GPIO
Section 8.4.35: GPIOC register map
0x4800 0400 - 0x4800 07FF
Section 8.4.34: GPIOB register map
0x4800 0000 - 0x4800 03FF
Section 8.4.33: GPIOA register map
0x4260 0000 - 0x47FF FFFF
-
Reserved
0x4240 0000 - 0x425F FFFF
2048 K
AHB1 bit banding -
0x4220 0000 - 0x423F FFFF
2048 K
APB2 bit banding -
0x4200 0000 - 0x421F FFFF
2048 K
APB1 bit banding -
0x4002 3400 - 0x41FF FFFF
-
Reserved
0x4002 3000 - 0x4002 33FF
1K
CRC
0x4002 0C00 - 0x4002 2FFF
-
Reserved
-
0x4002 0800 - 0x4002 0BFF
1K
DMAMUX1
Section 12.6.7: DMAMUX register map
0x4002 0400 - 0x4002 07FF
1K
DMA2
Section 11.6.7: DMA register map
0x4002 0000 - 0x4002 03FF
1K
DMA1
Section 11.6.7: DMA register map
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Section 15.4.6: CRC register map
RM0461
Table 3. Memory map and peripheral register boundary addresses (continued)
Bus
APB2
Boundary address
Size
(bytes)
Peripheral
0x4001 4C00 - 0x4001 FFFF
-
Reserved
0x4001 4800 - 0x4001 4BFF
1K
TIM17
Section 25.4.23: TIM16/TIM17 register
map
0x4001 4400 - 0x4001 47FF
1K
TIM16
Section 25.4.23: TIM16/TIM17 register
map
0x4001 3C00 - 0x4001 43FF
-
Reserved
-
0x4001 3800 - 0x4001 3BFF
1K
USART1
Section 33.8.15: USART register map
0x4001 3400 - 0x4001 37FF
-
Reserved
-
0x4001 3000 - 0x4001 33FF
1K
SPI1
Section 35.9.10: SPI/I2S register map
0x4001 2C00 - 0x4001 2FFF
1K
TIM1
Section 23.4.30: TIM1 register map
0x4001 2800 - 0x4001 2BFF
-
Reserved
0x4001 2400 - 0x4001 27FF
1K
ADC
0x4001 0400 - 0x4001 23FF
-
Reserved
-
COMP
Section 19.6.3: COMP register map
0x4001 0200 - 0x4001 03FF
0x4001 0100 - 0x4001 01FF
0x4001 0030 - 0x4001 00FF
0x4001 0000 - 0x4001 002F
1K
Peripheral register map
-
Section 16.13: ADC register map
SYSCFG continue Section 9.2.12: SYSCFG register map
VREFBUF
Section 18.3.3: VREFBUF register map
SYSCFG
Section 9.2.12: SYSCFG register map
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Table 3. Memory map and peripheral register boundary addresses (continued)
Bus
APB1
-
Boundary address
Size
(bytes)
Peripheral
0x4000 B400 - 0x4000 FFFF
-
Reserved
0x4000 B000 - 0x4000 B3FF
1K
TAMP
0x4000 9C00 - 0x4000 AFFF
-
Reserved
-
0x4000 9800 - 0x4000 9BFF
1K
LPTIM3
Section 26.7.13: LPTIM register map
0x4000 9400 - 0x4000 97FF
1K
LPTIM2
Section 26.7.13: LPTIM register map
0x4000 8400 - 0x4000 93FF
-
Reserved
-
0x4000 8000 - 0x4000 83FF
1K
LPUART1
Section 34.7.13: LPUART register map
0x4000 7C00 - 0x4000 7FFF
1K
LPTIM1
Section 26.7.13: LPTIM register map
0x4000 7800 - 0x4000 7BFF
-
Reserved
-
0x4000 7400 - 0x4000 77FF
1K
DAC
0x4000 6000 - 0x4000 73FF
-
Reserved
0x4000 5C00 - 0x4000 5FFF
1K
I2C3
Section 32.9.12: I2C register map
0x4000 5800 - 0x4000 5BFF
1K
I2C2
Section 32.9.12: I2C register map
0x4000 5400 - 0x4000 57FF
1K
I2C1
Section 32.9.12: I2C register map
0x4000 4800 - 0x4000 53FF
-
Reserved
-
0x4000 4400 - 0x4000 47FF
1K
USART2
Section 33.8.15: USART register map
0x4000 3C00 - 0x4000 43FF
-
Reserved
-
0x4000 3800 - 0x4000 3BFF
1K
SPI2S2
Section 35.9.10: SPI/I2S register map
0x4000 3400 - 0x4000 37FF
-
Reserved
-
0x4000 3000 - 0x4000 33FF
1K
IWDG
Section 28.4.6: IWDG register map
0x4000 2C00 - 0x4000 2FFF
1K
WWDG
Section 29.5.4: WWDG register map
0x4000 2800 - 0x4000 2BFF
1K
RTC
Section 30.6.23: RTC register map
0x4000 0400 - 0x4000 27FF
-
Reserved
0x4000 0000 - 0x4000 03FF
1K
TIM2
0x2220 0000 - 0x3FFF FFFF
-
Reserved
-
1024 K
SRAM2 bit
banding
-
1024 K
(1)
SRAM1 bit
banding
-
0x2001 0000 - 0x21FF FFFF
-
Reserved
-
0x2000 8000 - 0x2000 FFFF
32 K(1)
SRAM2
-
0x2000 0000 - 0x2000 7FFF
32 K
(1)
SRAM1
-
0x1FFF 8080 - 0x1FFF FFFF
-
Reserved
-
0x2210 0000 - 0x221F FFFF
AHB3
0x2200 0000 - 0x220F FFFF
AHB3
-
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Section 31.6.11: TAMP register map
Section 17.7.13: DAC register map
-
Section 24.4.25: TIMx register map
RM0461
Table 3. Memory map and peripheral register boundary addresses (continued)
Boundary address
Size
(bytes)
0x1FFF 7800 - 0x1FFF 7FFF
2K
0x1FFF 7400 - 0x1FFF 77FF
1K
Flash Engi
-
0x1FFF 7000 - 0x1FFF 73FF
1K
Flash OTP
-
0x1FFF 0000 - 0x1FFF 6FFF
28 K
Flash RSS and
bootloader
-
0x1000 8000 - 0x1FFE FFFF
-
Reserved
-
AHB3
0x1000 0000 - 0x1000 7FFF
32 K(1)
SRAM2
-
-
0x0804 0000 - 0x0FFF FFFF
-
Reserved
-
AHB3
0x0800 0000 - 0x0803 FFFF
256 K(1)
User flash
-
-
0x0004 0000 - 0x07FF FFFF
-
Reserved
-
0x0000 0000 - 0x0003 FFFF
256 K(1)
CPU boot area
-
Bus
AHB3
-
BOOT
(2)
Peripheral
Peripheral register map
Flash user options Section 3.8.14: FLASH register map
1. Size depending on the device. Refer to the datasheet for more details.
2. Bus depends on the selected CPU boot area.
2.4.3
CPU bit banding
The CPU map includes two bit-band regions. These regions map each word in an alias
region of memory to a bit in a bit-band region of memory. Writing to a word in the alias
region has the same effect as a read-modify-write operation on the targeted bit in the bitband region.
The AHB1, APB1, APB2 peripheral registers and the SRAM1 and SRAM2 are mapped to a
bit-band region, so that single bit-band write and read operations are allowed. The
operations are only available for CPU accesses and not form other bus masters (such as
DMA).
The peripheral bit-band alias is located from address 0x4200 0000 to 0x425F FFFF.
The SRAM bit-band alias is located from address 0x2200 0000 to 0x221F FFFF.
A mapping formula shows how to reference each word in the alias region to a corresponding
bit in the bit-band region.
The mapping formula is the following:
bit_word_addr = bit_band_base + (byte_offset * 32) + (bit_number * 4)
where:
•
bit_word_addr is the address of the word in the alias memory region that maps to the
targeted bit.
•
bit_band_base is the starting address of the alias region.
•
byte_offset is the number of the byte in the bit_band region that contains the targeted
bit.
•
bit_number is the bit position (0-7) of the targeted bit.
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Example
The following example shows how to map bit [2] of the byte located at SRAM1 address
0x2000 0300 to the alias region. The formula is then:
0x2200 6008 = 0x2200 0000 + 0x0300 * 32 + 2 * 4
Writing to address 0x2200 6008 has the same effect as a read-modify-write operation on bit
[2] of the byte at SRAM1 address 0x2000 0300.
Reading address 0x2200 6008 returns the value 0x01 or 0x00 of bit [2] of the byte at
SRAM1 address 0x2000 0300.
For more information on bit-band, refer to the Cortex-M4 programming manual.
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3
Embedded flash memory (FLASH)
3.1
FLASH introduction
The flash memory interface manages the CPU AHB ICode and DCode accesses to the flash
memory. It implements the access, the erase and program flash memory operations, and
the read and write protection.
The flash memory interface accelerates code execution with a system of instruction prefetch
and cache lines.
3.2
FLASH main features
•
Up to 256 Kbytes of flash memory single bank architecture
•
Memory organization: 1 bank
–
Main memory: up to 256 Kbytes
–
Page size: 2 Kbytes
•
72-bit wide data read (64 bits plus 8 ECC bits)
•
72-bit wide data write (64 bits plus 8 ECC bits)
•
Page erase (2 Kbytes) and mass erase
Flash memory interface features:
•
Flash memory read operations
•
Flash memory program/erase operations
•
Readout protection activated by option (RDP)
•
2 write protection areas selected by option (WRP)
•
2 proprietary code readout protection area selected by option (PCROP)
•
Flash empty check
•
Program and erase suspension feature
•
Prefetch on CPU ICODE
•
CPU instruction cache: 32 cache lines of 4 x 64 bits on ICode (1-Kbyte RAM)
•
CPU data cache: 8 cache lines of 4 x 64 bits on DCode (256-byte RAM)
•
Error code correction (ECC): 8 bits for 64-bit
•
Option byte loader
3.3
FLASH functional description
3.3.1
Flash memory organization
The flash memory is organized as 72-bit wide memory cells (64 bits plus 8 ECC bits) that
can be used for storing both code and data constants.
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The flash memory is organized as follows:
•
A main memory block containing 128 pages of 2 Kbytes, each page with eight rows of
256 bytes.
•
An information block containing:
–
System memory, from which the CPU boots in system memory boot mode
This area is reserved and contains the bootloader used to reprogram the flash
memory through one of the following interfaces: USART1, USART2, I2C1, I2C2,
I2C3, SPI1, SPI2S2. It is programmed by STMicroelectronics when the device is
manufactured and protected against spurious write/erase operations. For further
details, refer to AN2606 “STM32 microcontroller system memory boot mode”.
–
1-Kbyte (128 double-word) OTP (one-time programmable) for user data
The OTP data cannot be erased and can be written only once. If only one bit is at
0, the entire double-word (64 bits) cannot be written anymore, even with the value
0x0000 0000 0000 0000.
–
Option bytes for user configuration
The memory organization is based on a main area and an information block, as shown in
the table below.
Table 4. Flash memory - Single bank organization
Area
Main memory
Information block
3.3.2
Addresses
Size (Kbytes)
Name
0x0800 0000 - 0x0800 07FF
2
Page 0
0x0800 0800 - 0x0800 0FFF
2
Page 1
0x0800 1000 - 0x0800 17FF
2
Page 2
0x0800 1800 - 0x0800 1FFF
2
Page 3
...
...
...
0x0803 F000 - 0x0803 F7FF
2
Page 126
0x0803 F800 - 0x0803 FFFF
2
Page 127
0x1FFF 0000 - 0x1FFF 6FFF
28
System memory
0x1FFF 7000 - 0x1FFF 73FF
1
OTP area
0x1FFF 7800 - 0x1FFF 7FFF
2
Option bytes
Empty check
During the OBL phase, after loading all options, the flash memory interface checks whether
the first location of the main memory is programmed. The result of this check, in conjunction
with the BOOT0 and BOOT1 information, is used to determine where the system must boot
from. It prevents the system to boot from the flash main memory area when, for example, no
user code is programmed.
The flash main memory empty check status can be read from the EMPTY bit in the
FLASH_ACR register. Software can modify the flash main memory empty status by writing
to the EMPTY bit.
The internal empty check flag (EMPTY bit in FLASH_ACR) is implemented to allow easy
programming of virgin devices by the bootloader. This flag is used when the BOOT0 pin
defines the main flash memory as target boot area. When this flag is set, the device is
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considered as empty and the system memory (bootloader) is selected instead of the main
flash memory as a boot area, to allow the user to program the flash memory. Therefore,
some of the GPIOs are reconfigured from the high-Z state. Refer to the application note
AN2606 for more details concerning the bootloader and GPIO configuration in system
memory boot mode. This feature can be disabled by configuring the option bytes to force a
boot from the main flash memory (nSWBOOT0 = 0, nBOOT0 = 1).
This empty check flag is updated only during the loading of option bytes: it is set when the
content of the address 0x08000 0000 is read as 0xFFFF FFFF, otherwise it is cleared. A
power reset or setting of OBL_LAUNCH bit in FLASH_CR is needed to clear this flag after
programming of a virgin device to execute user code after a system reset. The EMPTY bit
can also directly be written by software.
3.3.3
Error code correction (ECC)
Data in flash memory words are 72-bit wide: eight bits are added per each double-word
(64 bits).
The ECC mechanism supports the following modes:
•
one error detection and correction
•
two errors detection
When one error is detected and corrected, the flag ECCC (ECC correction) is set in
FLASH_ECCR. If ECCCIE is set, an interrupt is generated.
When two errors are detected, the flag ECCD (ECC detection) is set in FLASH_ECCR. In
this case, an NMI is generated.
When an ECC error is detected, the address of the failing double-word is saved in
ADDR_ECC[16:0] in FLASH_ECCR. ADDR_ECC[2:0] bits are always cleared. The bus-ID
of the CPU accessing the address is saved in CPUID[2:0].
While ECCC or ECCD is set, FLASH_ECCR is not updated if a new ECC error occurs.
FLASH_ECCR is updated only when ECC flags are cleared.
Note:
For virgin data (0xFF FFFF FFFF FFFF FFFF), one error is detected and corrected, but the
two errors detection mode is not supported.
When an ECC error is reported, a new read at the failing address may not generate an ECC
error if the data is still present in the current buffer, even if ECCC and ECCD are cleared. If
this is not the desired behavior, the user must reset the cache.
3.3.4
Read access latency
To correctly read data from the flash memory, the number of wait states (LATENCY[2:0])
must be correctly programmed in FLASH_ACR according to the frequency of the flash
memory clock (HCLK3) and the internal voltage range of the device (VCORE). Refer to
Section 5.1.4: Dynamic voltage scaling management.
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Table 5 shows the correspondence between wait states and frequency of the memory clock.
Table 5. Number of wait states according to flash clock (HCLK3) frequency
HCLK3 (MHz)
Wait states (WS)
(access)
VCORE range 1
VCORE range 2
0 WS (1 HCLK cycle)
≤ 18
≤6
1 WS (2 HCLK cycles)
≤ 36
≤ 12
2 WS (3 HCLK cycles)
≤ 48
≤ 16
After power-on reset and wake-up from Standby, the HCLK3 clock frequency is 4 MHz in
range 1 and 0 wait state (WS) is configured in FLASH_ACR.
When changing the frequency of the flash memory clock or the VCORE range, the software
sequences detailed below must be applied in order to tune the number of wait states
needed to access the flash memory:
Increase the CPU frequency
1.
Program the new number of wait states to the LATENCY[2:0] bits in FLASH_ACR.
2.
Check that the new number of wait states is taken into account to access the flash
memory by reading back the LATENCY[2:0] bits in FLASH_ACR, and wait until the new
programmed number is read.
3.
Modify the system cock source by writing the SW[1:0] bits in RCC_CFGR.
4.
If needed, modify the CPU clock prescaler by writing the SHDHPRE[3:0] bits in
RCC_EXTCFGR.
5.
Optionally, check that the new system clock source or/and the new flash memory clock
prescaler value is/are taken into account by reading the clock source status (SWS(1:0]
bits) in RCC_CFGR, or/and the AHB prescaler value (SHDHPREF bit) in
RCC_EXTCFGR.
Decrease the CPU frequency
3.3.5
1.
Modify the system clock source by writing the SW[1:0] bits in RCC_CFGR.
2.
If needed, modify the flash memory clock prescaler by writing the SHDHPRE[3:0] bits
in RCC_EXTCFGR.
3.
Check that the new system clock source or/and the new flash memory clock prescaler
value is/are taken into account by reading the clock source status (SWS[1:0] bits) in
RCC_CFGR, or/and the AHB prescaler value (SHDHPREF bit) in RCC_EXTCFGR.
Wait until the new programmed system clock source or/and new flash memory clock
prescaler value is/are read.
4.
Program the new number of wait states to the LATENCY[2:0] bits in FLASH_ACR.
5.
Optionally, check that the new number of wait states is used to access the flash
memory by reading back the LATENCY[2:0] bits in FLASH_ACR.
Adaptive real-time memory accelerator (ART Accelerator)
The proprietary adaptive real-time (ART) memory accelerator is optimized for STM32
industry-standard Arm Cortex-M4 with DSP processors. It balances the inherent
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performance advantage of the Cortex-M4 with DSP over flash memory technologies, which
normally require the processor to wait for the flash memory at higher operating frequencies.
To release the processor full performance, the accelerator implements an instruction
prefetch queue and branch cache that increases program execution speed from the 64-bit
flash memory. Based on CoreMark® benchmark, the performance achieved thanks to the
ART Accelerator is equivalent to 0 wait state program execution from the flash memory at a
CPU frequency up to 48 MHz.
Instruction prefetch
The CPU fetches the instruction over the ICode bus and the literal pool (constant/data) over
the DCode bus. The prefetch block aims at increasing the efficiency of ICode bus accesses.
Each flash memory read operation provides 64 bits from either two instructions of 32 bits or
four instructions of 16 bits according to the program launched. This 64-bit current instruction
line is saved in a current buffer. In case of sequential code, at least two CPU cycles are
needed to execute the previous read instruction line. Prefetch on the CPU ICode bus can
be used to read the next sequential instruction line from the flash memory while the current
instruction line is being requested by the CPU.
Prefetch is enabled by setting PRFTEN in FLASH_ACR. This feature is useful if at least one
wait state is needed to access the flash memory.
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The figure below shows the execution of sequential 16-bit instructions with and without
prefetch when three wait states are needed to access the flash memory.
Figure 3. Sequential 16 bits instructions execution
@
1
WAIT
F
1
@
2
D
1
E
1
F
2
D
2
E
2
@
3
F
3
D
3
E
3
@
4
F
4
D
4
WITHOUT PREFETCH
@
5
E
4
F
5
WAIT
D
5
E
5
F
6
D
6
E
6
@
7
F
7
D
7
@
8
F
8
@
6
Read ins 1, 2, 3, 4
@
1
WAIT
@
2
F
1
ins 1 ins 2 ins 3 ins 4
fetch fetch fetch fetch
ins 5 ins 6 ins 7 ins 8
fetch fetch fetch fetch
Gives ins 1, 2, 3, 4
Gives ins 5, 6, 7, 8
Read ins 5, 6, 7, 8
D
1
E
1
F
2
D
2
E
2
@
3
F
3
D
3
E
3
@
4
F
4
D
4
E
4
@
5
F
5
D
5
E
5
@
6
F
6
D
6
E
6
@
7
F
7
D
7
@
8
F
8
WITH PREFETCH
ins 1 ins 2 ins 3 ins 4 ins 5 ins 6 ins 7 ins 8
fetch fetch fetch fetch fetch fetch fetch fetch
Read ins 1, 2, 3, 4
Gives ins 1, 2, 3, 4
Gives ins 5, 6, 7, 8
Read ins 5, 6, 7, 8
Cortex-M4 pipeline
@
6
F
6
D
6
E
6
AHB protocol
@: address requested
F: Fetch stage
D: Decode stage
E: Execute stage
Read ins 9, 10, ...
MS33467V1
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When the code is not sequential (branch), the instruction may not be present in the currently
used instruction line or in the prefetched instruction line. In this case (miss), the penalty in
terms of number of cycles is at least equal to the number of wait states.
If a loop is present in the current buffer, no new access is performed.
CPU instruction cache memory (I-Cache)
To limit the CPU time lost due to jumps, it is possible to retain 32 lines of 4 x 64 bits
(1 Kbyte) in an instruction cache memory.This feature is enabled for the CPU by setting the
instruction cache enable (ICEN) bit in FLASH_ACR. Each time a miss occurs (requested
data not present in the currently used instruction line, in the prefetched instruction line or in
the instruction cache memory), the line read is copied into the instruction cache memory. If
some data contained in the instruction cache memory are requested by the CPU, they are
provided without inserting any delay. Once all the instruction cache memory lines have been
filled, the LRU (least recently used) policy is used to determine the line to replace in the
instruction memory cache. This feature is particularly useful in case of code containing
loops.
The instruction cache memory is enabled after system reset.
CPU data cache memory (D-Cache)
CPU literal pools are fetched from the flash memory through the DCode bus during the
execution stage of the CPU pipeline. Each CPU DCode bus read access fetches 64 bits that
are saved in a current buffer. The CPU pipeline is consequently stalled until the requested
literal pool is provided. To limit the time lost due to literal pools, accesses through the AHB
data bus DCode have priority over accesses through the AHB instruction bus ICode.
If some literal pools are frequently used, the CPU data cache memory can be enabled by
setting the data cache enable (DCEN) bit in FLASH_ACR. This feature works like the
instruction cache memory but the retained data size is limited to eight lines of 4 x 64 bits
(256 bytes).
The data cache memory is enabled after system reset.
Note:
The D-Cache is active only when data is requested by the CPU (not by DMAs).
Data in option bytes block are not cacheable.
3.3.6
Flash program and erase operations
The embedded flash memory can be programmed using in-circuit programming or inapplication programming.
The in-circuit programming (ICP) method is used to update the entire contents of the flash
memory using the JTAG, SWD protocol or the supported interfaces by the system
bootloader, to load the user application for the CPU, into the microcontroller. ICP offers
quick and efficient design iterations and eliminates unnecessary package handling or
socketing of devices.
In contrast to the ICP method, in-application programming (IAP) can use any
communication interface supported by the microcontroller (such as I/Os, UART, I2C or SPI)
to download programming data into memory. IAP allows the user to re-program the flash
memory while the application is running. Nevertheless, part of the application must have
been previously programmed in the flash memory using ICP.
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The contents of the flash memory are not guaranteed if a device reset occurs during a flash
memory operation.
During a program/erase operation to the flash memory, any attempt to read the memory
stalls the bus. The read operation proceeds correctly once the program/erase operation is
completed.
Unlocking the flash memory
After a reset, write is not allowed in FLASH_CR to protect the flash memory against
possible unwanted operations (for example, electric disturbances).
The following sequence is used to unlock these registers:
1.
Write KEY1 = 0x4567 0123 in FLASH_KEYR.
2.
Write KEY2 = 0xCDEF 89AB in FLASH_KEYR.
Any wrong sequence locks up FLASH_CR until the next system reset. In the case of a
wrong key sequence, a bus error is detected and a hard fault interrupt is generated.
FLASH_CR can be locked again by software by setting the LOCK bit.
Note:
FLASH_CR cannot be written when BSY is set in FLASH_SR. Any attempt to write to this
register with BSY set causes the AHB bus to stall until BSY is cleared.
3.3.7
Flash main memory erase sequences
Erase can be performed by page (page erase) or on the whole memory (mass erase). Mass
erase does not affect the information block (system flash memory, OTP, and option bytes).
Flash memory page erase
A page erase only starts when allowed by PESD in FLASH_SR.
When a page is protected by PCROP or WRP, it is not erased.
Table 6. Page erase overview
PCROP
WRP
No
No
No
Yes
Yes
No
Yes
Yes
PCROP_RDP
x
Comment
WRPERR
Page is erased
No
Page erase aborted (no page erase started)
Yes
CPU bus error
No
To erase a 2-Kbyte page, follow the steps detailed below:
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1.
Check that no flash memory operation is ongoing by checking BSY in FLASH_SR.
2.
Check that flash program and erase operation is allowed by checking PESD in
FLASH_SR.
3.
Check and clear all error programming flags due to a previous programming. If not,
PGSERR is set.
4.
Set PER and select the page to erase (PNB[6:0]) in FLASH_CR.
5.
Set STRT in FLASH_CR.
6.
Wait for BSY to be cleared in FLASH_SR.
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The internal oscillator HSI16 (16 MHz) is enabled automatically when the STRT bit is set,
and disabled automatically when the STRT bit is cleared, except if the HSI16 is previously
enabled with HSION in the RCC_CR register.
Flash mass erase
When PCROP or WRP is enabled, any flash memory mass erase is aborted and no erase
started.
Table 7. Mass erase overview
PCROP
WRP
No
No
No
Yes
Yes
No
Yes
Yes
PCROP_RDP
x
Comment
WRPERR
Memory is erased.
No
Erase aborted (no erase started)
Yes
CPU bus error
No
To perform a mass erase, follow the steps detailed below:
1.
Check that no flash memory operation is ongoing by checking BSY in FLASH_SR.
2.
Check and clear all error programming flags due to a previous programming. If not,
PGSERR is set.
3.
Set MER in FLASH_CR.
4.
Set STRT in FLASH_CR
5.
Wait for BSY to be cleared in FLASH_SR.
Note:
The internal oscillator HSI16 (16 MHz) is enabled automatically when the STRT bit is set,
and disabled automatically when the STRT bit is cleared, except if the HSI16 is previously
enabled with HSION in the RCC_CR register.
3.3.8
Flash main memory programming sequences
The flash memory is programmed with 72 bits at a time (a double-word of 64 bits plus 8 bits
ECC).
Programming in a previously programmed double-word is only allowed when programming
an all 0 value. It is not allowed to program any other value in a previously programmed
double-word. Any attempt sets PROGERR flag in FLASH_SR, except when programming
an already programmed double-word with an all 0 value.
It is only possible to program a double-word (2 x 32-bit data), otherwise:
•
Any attempt to write a byte (8 bits) or half-word (16 bits) sets SIZERR in FLASH_SR.
•
Any attempt to write a double-word that is not aligned with a double-word address sets
the PGAERR flag in FLASH_SR.
Standard programming
The flash memory programming sequence in standard mode is as follows:
1.
Check that no flash main memory operation is ongoing by checking BSY in
FLASH_SR.
2.
Check that flash program and erase operation is allowed by checking PESD in
FLASH_SR.
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3.
Check and clear all error programming flags due to a previous programming. If not,
PGSERR is set.
4.
Set PG in FLASH_CR.
5.
Perform the data write operation at the desired memory address, inside the main
memory block or OTP area. Only double-word (64 bits) can be programmed.
a)
Write a first word in an address aligned with double-word
b)
Write the second word (see the note below)
Note: When the flash memory interface received a good sequence (a double-word),
programming is automatically launched and the BSY bit is set. The internal oscillator
HSI16 (16 MHz) is enabled automatically when the PG bit is set, and disabled
automatically when the PG bit is cleared, except if the HSI16 is previously enabled
with HSION in the RCC_CR register.
If the user needs to program only one word, double-word must be completed with the
erase value 0xFFFF FFFF to launch automatically the programming.
ECC is calculated from the double-word to program.
For correct operation, the firmware must guarantee that the flash page access
protection is not changed during the programming sequence. This is between the first
and second word write.
6.
Wait until BSY is cleared in FLASH_SR.
7.
Check that EOP is set in FLASH_SR (meaning the programming operation
succeeded), and clear it by software.
8.
Clear PG in FLASH_SR if there no more programming request.
Fast programming
This mode allows a row to be programmed, 32 double-words (256 bytes), and the page
programming time to be reduced by eliminating the need for verifying the flash memory
locations before they are programmed and to avoid rising and falling time of high voltage for
each double-word. During fast programming, the flash clock frequency (HCLK3) must be at
least 8 MHz.
Fast row programming must be performed by executing firmware from SRAM and disabling
interrupts when not relocating the CPU interrupt vector table. A read access form the CPU
requesting row programming causes a bus error. A read from any other source (such as the
DMA) is stalled until the row programming is finished (standard double-word programming
does not cause a bus error to the requesting CPU but stalls any read until standard
programming is finished).
Only the main memory can be programmed in Fast programming mode.
The flash main memory programming sequence in Fast programming mode is described
below:
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1.
Perform a mass erase. If not, PGSERR is set.
2.
Check that no flash main memory operation is ongoing by checking BSY bit
FLASH_SR.
3.
Check that flash memory program and erase operation is allowed by checking PESD in
FLASH_SR.
4.
Check and clear all error programming flag due to a previous programming.
5.
Set FSTPG in FLASH_CR.
6.
Write the 32 double-words to program a row (256 bytes).
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Note:
Embedded flash memory (FLASH)
7.
Wait until BSY is cleared in FLASH_SR.
8.
Check that the EOP flag is set in FLASH_SR(meaning the programming operation
succeeded), and clear it by software.
9.
Clear FSTPG in FLASH_SR if there are no more programming requests.
When attempting to write in Fast programming mode while a read operation is ongoing, the
programming is aborted without any system notification (no error flag is set).
When the flash memory interface receives the first double-word, programming is
automatically launched. The BSY bit is set when the high voltage is applied for the first
double-word, and it is cleared when the last double-word is programmed or in case of error.
The internal oscillator HSI16 (16 MHz) is enabled automatically when FSTPG is set, and
disabled automatically when the FSTPG bit is cleared, except if the HSI16 is previously
enabled with HSION in the RCC_CR register.
The 32 double-word must be written successively. The high voltage is kept on the flash
memory for all the programming. Maximum time between two double-words write requests
is the time programming (~ 20 µs). If a second double-word arrives after this time
programming, fast programming is interrupted and MISSERR is set.
High voltage must not exceed 8 ms for a full row between two erases. This is guaranteed by
the sequence of 32 double-words successively written with a clock system greater or equal
to 8 MHz. An internal time-out counter counts 7 ms when Fast programming is set and stops
the programming when time-out is over. In this case FASTERR is set.
If an error occurs, high voltage is stopped and next double-word to programmed is not
programmed. Anyway, all previous double-words have been properly programmed.
Programming errors signaled by flags
Several kind of errors can be detected. In case of error, the flash operation (programming or
erasing) is aborted.
•
PROGERR: programming error
In standard programming, PROGERR is set if the word to write, with a different value
than all zero, is not previously erased (except if the value to program is all zero).
If any other error occurs (such as SIZERR, PAGERR, PGSERR, WRPERR),
PROGRERR may not be set even if there is a word re-programming without erase
error.
•
SIZERR: size programming error
In standard programming or in fast programming: only double-word can be
programmed and only 32-bit data can be written. SIZERR is set if a byte or an
half-word is written.
•
PGAERR: alignment programming error
PGAERR is set if one of the following conditions occurs:
•
–
In standard programming, the first word to be programmed is not aligned with a
double-word address, or the second word does not belong to the same doubleword address.
–
In fast programming, the data to program does not belong to the same row than
the previous programmed double-words, or the address to program is not greater
than the previous one.
PGSERR: programming sequence error
PGSERR is set if one of the following conditions occurs:
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–
In the standard programming sequence or the fast programming sequence, a data
is written when PG and FSTPG are cleared.
–
In the standard programming sequence or the fast programming sequence, MER
and PER are not cleared when PG or FSTPG is set.
–
In the fast programming sequence, the mass erase is not performed before setting
the FSTPG bit.
–
In the mass erase sequence, PG, FSTPG, and PER are not cleared when MER is
set, when the security of the flash allows a mass erase. A non-secure mass erase
request on a secure flash memory does not set a PGSERR. An illegal access
event is generated instead.
–
In the page erase sequence, PG, FSTPG and MER are not cleared when PER is
set, when the security of the page allows access. When the security of this page
does not allow access, no PGSERR is set but an illegal access event is generated
instead.
–
PGSERR is set also if PROGERR, SIZERR, PGAERR, WRPERR, MISSERR,
FASTERR or PGSERR is set due to a previous programming error.
–
In the fast programming sequence, if the page containing the row to be
programmed has not been erased by the last page erase action (If a mass erase
has been done, it is allowed to program rows on higher order pages but not on
lower order)
WRPERR: write protection error
WRPERR is set if one of the following conditions occurs:
•
–
Attempt to program or erase in a write protected area (WRP) or in a PCROP area,
when the security of the area allows access. When the security of this area does
not allow access, no WRPERR is set but an illegal access event is generated
instead.
–
Attempt to perform a mass erase when one page or more is protected by WRP or
PCROP, when the security of the flash allows a mass erase. A non-secure mass
erase request on a secure flash memory does not set a WRPERR. An illegal
access event is generated instead.
–
The debug features are connected or the boot is executed from SRAM or from
system flash memory when the readout protection (RDP) is set to level 1.
–
Attempt to modify the option bytes when the readout protection (RDP) is set to
Level 2
MISSERR: fast programming data miss error
In fast programming, all the data must be written successively. MISSERR is set if the
previous data programming is finished and the next data to program is not written yet.
•
FASTERR: fast programming error
In fast programming, FASTERR is set if one of the following conditions occurs:
–
When FSTPG bit is set for more than 7 µs (generating a time-out detection).
–
When the row fast programming is interrupted by a MISSERR, PGAERR,
WRPERR or SIZERR.
If an error occurs during a program or erase operation, one of the following error flags is set
in FLASH_SR:
80/1290
•
PROGERR, SIZERR, PGAERR, PGSERR, MISSERR (program error flags)
•
WRPERR (protection error flag)
RM0461 Rev 10
RM0461
Embedded flash memory (FLASH)
In this case, if the error interrupt enable bit ERRIE is set in FLASH_CR, an interrupt is
generated and the operation error flag OPERR is set in FLASH_SR.
Note:
If several successive errors are detected (for example, in case of DMA transfer to the flash
memory), the error flags cannot be cleared until the end of the successive write request.
PGSERR and PGAERR in a page-based row programming
In case of fast programming, the table below describes how PGAERR and PGSERR are
handled.
Table 8. Errors in page-based row programming
Last page/row
page [x]/row [y]
Current page/row
MER active
PPER active
page [x] / row [x-n]
PGAERR
PGAERR
page [x-n] / row [any]
PGAERR & PGSERR
PGAERR & PGSERR
page [x+n] / row [any]
No error
PGSERR
After a system reset, no MER or PER is performed. Any programming attempt causes a
PGAERR and a PGSERR.
Programming errors causing a bus error
The error conditions listed below do not generate an error flag but a bus error instead:
•
AHB write to any page when RDP level 1 and boot is performed from the system flash
memory or SRAM1
•
AHB write when the flash memory is powered down
•
Read or write from the flash memory through the debugger
•
Read from the flash memory when fast row programming is ongoing, for the source
which requested the fast row programming
•
New programming request when the previous one is not finished
•
FLASH_CR register write between the two accesses of a double-word programming
•
FLASH_CR register write when PESD is active (set)
•
Write a wrong key in FLASH_KEYR or FLASH_OPTKEYR register
•
Any subsequent write to FLASH_KEYR or FLASH_OPTKEYR after unlocking the
respective feature
Programming and caches
If a flash memory write access impacts data in the data cache, the flash memory write
access modifies the data in the memory and in the cache.
If an erase operation in the flash memory also concerns data in the data cache or instruction
cache, the user must ensure that these data are rewritten before they are accessed during
code execution. Upon an erase operation, the cache content is invalidated.
Note:
The ICACHE and DCACHE must be flushed only when disabled (ICEN or DCEN = 0).
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Embedded flash memory (FLASH)
RM0461
3.4
FLASH option bytes
3.4.1
Option bytes description
The option bytes can be read from the memory locations listed in the table below or from the
following option byte registers:
•
FLASH option register (FLASH_OPTR)
•
FLASH PCROP zone A start address register (FLASH_PCROP1ASR)
•
FLASH PCROP zone A end address register (FLASH_PCROP1AER)
•
FLASH PCROP zone B start address register (FLASH_PCROP1BSR)
•
FLASH PCROP zone B end address register (FLASH_PCROP1BER)
•
FLASH WRP area A address register (FLASH_WRP1AR)
•
FLASH WRP area B address register (FLASH_WRP1BR)
Res.
Res.
nBOOT0
nSWBOOT0
SRAM_RST
SRAM2PAR
nBOOT1
Res.
Res.
Res.
WWDG_SW
IWDG_STDBY
IWDG_STOP
IWDG_SW
Res.
nRST_SHDW
nRST_STDBY
nRST_STOP
ESE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res. Res. Res. Res.
Res. Res. Res. Res.
Res. Res. Res. Res.
Res. Res. Res. Res.
Res. Res. Res. Res.
Res. Res. Res. Res.
Res. Res. Res. Res.
WRP1A_END[6:0]
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res. Res. Res.
Res. Res. Res. Res.
Res. Res. Res. Res.
Res. Res. Res. Res.
Res. Res. Res. Res.
Res. Res. Res. Res.
Res. Res. Res. Res.
Res. Res. Res. Res.
Res. Res.
Res. Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
WRP1A_STRT[6:0]
WRP1B_STRT[6:0]
PCROP1B_STRT[7:0]
OPTVAL[31:0]
0x1FFF 7FF8
1. The upper 32 bits of the double-word address contain the inverted data from the lower 32 bits.
3.4.2
Option bytes programming
After a reset, the options related bits in FLASH_CR are write-protected. To run any
operation on the option bytes page, the option lock bit OPTLOCK in FLASH_CR must be
cleared.
82/1290
RM0461 Rev 10
Res.
Res.
Res.
Res.
Res.
Res.
PCROP1B_END[7:0]
Res.
WRP1B_END[6:0]
BOR_LEV[2:0]
BOOT_LOCK
to
0x1FFF 7FF0
Res.
0x1FFF 7838
Res.
0x1FFF 7830
Res. Res. Res. Res.
0x1FFF 7828
PCROP1A_END[7:0]
Res.
0x1FFF 7820
Res.
0x1FFF 7818
Res.
0x1FFF 7810
PCROP1A_STRT[7:0]
PCROP_RDP
0x1FFF 7808
RDP[7:0]
Res. Res. Res. Res.
0x1FFF 7800
Res.
Address(1)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 9. Option bytes organization
RM0461
Embedded flash memory (FLASH)
The following sequence is used to unlock the FLASH_CR and flash memory option
registers:
1.
Unlock FLASH_CR with the LOCK clearing sequence (refer to Unlocking the flash
memory).
2.
Write OPTKEY1 = 0x0819 2A3B in FLASH_OPTKEYR
3.
Write OPTKEY2 = 0x4C5D 6E7F in FLASH_OPTKEYR
Any wrong sequence locks up the flash option register until the next system reset. In the
case of a wrong key sequence, a bus error is detected and a hard fault interrupt is
generated.
The user options can be protected against unwanted erase/program operations by setting
the OPTLOCK bit by software.
Note:
If LOCK is set by software, OPTLOCK is automatically set as well.
Modify user options
The option bytes are programmed differently from a main memory user address.
To modify the user options value, follow the procedure below:
Note:
1.
Clear OPTLOCK option lock bit with the clearing sequence described above
2.
Write the desired options value in the options registers.
3.
Check that no flash memory operation is ongoing by checking the BSY bit in
FLASH_SR.
4.
Check that flash program and erase operation is allowed by checking the PESD bit in
FLASH_SR.
5.
Set the options start bit OPTSTRT in FLASH_CR.
6.
Wait for the BSY bit to be cleared.
Any modification of the value of one option is automatically performed by erasing user
option bytes pages first, and then programming all the option bytes with the values
contained in the flash option registers.
Warning:
On RDP regression from level 1 to level 0, starting the option
programming by the OPTSTRT bit causes the flash memory,
SRAM1 and SRAM2 to be erased. All device software in all
memories is erased. A subsequent OBL_LAUNCH must be
started by an external tool or a POR must be performed to
restart the device and reload the options.
Option byte loading
After the BSY bit is cleared, all new options are updated into the flash memory but not
applied to the system. A read from the option registers still returns the last loaded option
byte values. The new options have effect on the system only after they are loaded.
Option bytes loading is performed in the following two cases:
•
when OBL_LAUNCH bit is set in FLASH_CR
•
after a power reset (BOR reset or exit from Standby/Shutdown modes)
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Embedded flash memory (FLASH)
RM0461
Option byte loader performs a read of the options block and stores the data into internal
option registers. These internal registers configure the system and can be read by software.
Setting OBL_LAUNCH generates a reset so the option byte loading is performed under
system reset.
Each option bit has also its complement in the same double-word. During option loading, a
verification of the option bit and its complement allows the correct loading to be checked.
During option byte loading, the options are read by double-word. ECC on option words is
not taken into account during OBL but only during direct software read of option area.
If the word and its complement are matching, the option word/byte is copied into the option
register.
If the comparison between the word and its complement fails, a status bit OPTVERR is set.
Mismatch values are forced into the option registers as follows:
•
For USR OPT option, the value of mismatch is all options at ‘1’, except for BOR_LEV
that is “000” (lowest threshold).
•
For WRP option, the value of mismatch is the default value “No protection”.
•
For RDP option, the value of mismatch is the default value “Level 1”.
•
For PCROP, the value of mismatch is “all memory protected”.
•
For BOOT_LOCK option, the value of mismatch is “CPU boot lock disabled”
•
For OPTVAL option, the value of mismatch is “not valid”. OPTVAL is a check word
programmed at the last user option address. It is used to check if all user options have
been programmed during an OPTSTART. If the user option program sequence has not
terminated completely, OPTVAL is not be programmed and OPTNV is set.
If the OPTVAL option indicates “not valid”, SRAM1, SRAM2, and PKA SRAM memories are
erased.
Table 10. Option loading control
OPTVERR OPTNV
Description
0
0
Options correctly loaded and OPTVAL is “Valid”.
Device is non-secure.
0
1
Does not occur
1
0
OPTVAL option is correctly loaded as “Valid” but some or all other options and engineering
bits are corrupted: mismatch values are loaded.
– When secure option is loaded correctly, security is applied according to the loaded secure
option values.
– When secure option is corrupted, security is applied on the full memory as indicated by the
loaded mismatch value.
1
1
Some or all options and engineering bits are corrupted: mismatch values are loaded.
OPTVAL is correctly loaded as “not Valid”.
Security applied on full memories irrespective of the loaded secure option values.
On system reset rising, internal option registers are copied into the following option registers
that can be read and written by software:
84/1290
•
FLASH_OPTR
•
FLASH_PCROP1xSR (x = A or B)
RM0461 Rev 10
RM0461
Embedded flash memory (FLASH)
•
FLASH_PCROP1xER (x = A or B)
•
FLASH_WRP1xR (x = A or B)
These registers are also used to modify the options. If these registers are not modified by
the user, they reflect the options states of the system. See Modify user options for more
details.
3.5
Flash memory protection
The main flash memory can be protected against external accesses with the readout
protection (RDP). The pages can also be protected against unwanted write (WRP) due to
loss of program counter context. The write protection WRP granularity is 2 Kbytes.
Apart from the RDP and WRP, the flash memory can also be protected against read and
write from third parties (PCROP). The PCROP granularity is 1 Kbyte.
3.5.1
Readout protection (RDP)
The readout protection is activated by setting the RDP option byte and performing an option
byte programming with OPTSTRT followed by a OBL_LAUNCH, POR or wake-up from
Standby or Shutdown mode. The readout protection protects the main flash memory, the
option bytes, the backup registers (TAMP_BKPxR in TAMP) and SRAM2.
There is no exception while the debugger is connected.
There are three levels of readout protection from no protection (level 0) to maximum
protection or no debug (level 2).
The flash memory is protected when the RDP option byte and its complement contain the
pair of values shown in the table below.
Table 11. Flash memory readout protection status
RDP byte value
RDP complement value
RDP level
0xAA
0x55
Level 0
Any value except 0xAA or 0xCC
Any value (not necessarily
complementary), except 0x55 and 0x33
Level 1 (default)
0xCC
0x33
Level 2
The system memory area is read accessible whatever the protection level. It is never
accessible for program/erase operation.
Level 0: no protection
Read, program and erase operations into the main flash memory area are possible. The
option bytes, SRAM2 and backup registers are also accessible by all operations.
RM0461 Rev 10
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Embedded flash memory (FLASH)
RM0461
Level 1: readout protection
This is the default protection level when the RDP option byte is erased. It is defined as well
when the RDP value is at any value different from 0xAA and 0xCC, or even if the
complement is not correct.
•
User mode
The code executing in user mode (Boot flash) can access the main flash memory,
option bytes, SRAM2 and backup registers with all operations.
•
Debug, boot RAM and bootloader and SFI/RSS modes
In debug mode or when the code is running from boot RAM or bootloader or SFI/RSS,
the main flash memory, backup registers (RTC_BKPxR in the RTC) and SRAM2 are
totally inaccessible. In these modes, a read or write access to the flash memory
generates a bus error and a hard fault interrupt.
Caution:
In case the level 1 is configured and no PCROP areas are defined, it is mandatory to set
PCROP_RDP bit to 1 (full mass erase when the RDP level is decreased from level 1 to
level 0). In case the level 1 is configured and a PCROP area is defined, if the user code
needs to be protected by RDP but not by PCROP, it must not be placed in a page containing
a PCROP area.
Level 2: no debug
In this level, the protection level 1 is guaranteed. In addition, the CPU debug port, the boot
from RAM (boot RAM mode) and the boot from system memory (bootloader mode) are no
more available. In user execution mode (boot FLASH mode), all operations are allowed on
the main flash memory. On the contrary, only read and secure write operations can be
performed on the option bytes.
Note:
The debug feature is also disabled under reset.
STMicroelectronics is not able to perform analysis on defective parts on which the level 2
protection has been set.
Change the readout protection level
It is easy to move from level 0 to level 1 by changing the value of the RDP byte to any value
(except 0xCC). By programming the 0xCC value in the RDP byte, it is possible to go to
level 2 directly from level 0 or from level 1. Once in level 2 it is no more possible to modify
the readout protection level.
When the RDP is reprogrammed to the value 0xAA to move from level 1 to level 0, a mass
erase of the main flash memory is performed if PCROP_RDP is set in
FLASH_PCROP1AER. Backup registers (RTC_BKPxR in the RTC), SRAM1, SRAM2 and
PKA SRAM are also erased. The user options except PCROP protection are set to their
previous values copied from FLASH_OPTR, FLASH_WRP1xR (x= A or B). PCROP is
disabled. The OTP area is not affected by mass erase and remains unchanged.
If the bit PCROP_RDP is cleared in FLASH_PCROP1AER, the full mass erase is replaced
by a partial mass erase that is successive page erases, except for the pages protected by
PCROP. This is done in order to keep the PCROP code. Only when the flash memory is
erased, options are re-programmed with their previous values. This is also true for
FLASH_PCROP1xSR and FLASH_PCROP1xER registers (x= A or B).
86/1290
RM0461 Rev 10
RM0461
Embedded flash memory (FLASH)
Table 12. RDP regression from level 1 to level 0 and memory erase
PCROP
PCROP_RDP
None
x
Comment
Flash, SRAM1, SRAM2, PKA SRAM and backup registers mass erase
1
Flash multiple page erase of all non-PCROP pages
SRAM1, SRAM2, PKA SRAM and backup registers erased (PCROP flash pages
conserved)
Partial
0
Complete
Flash, SRAM1, SRAM2 and backup registers conserved. PKA SRAM erase.
Note:
Full or partial mass erase is performed only when level 1 is active and level 0 is requested.
When the protection level is increased (0→1, 1→2, 0→2), there is no mass erase.
To validate the protection level change, the option bytes must be reloaded through the
OBL_LAUNCH bit in FLASH_CR, or a POR, or wake-up from Standby or Shutdown mode.
Figure 4. Changing the RDP level
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KƚŚĞƌƐŽƉƚŝŽŶƐŵŽĚŝĨŝĞĚ
Level 1
5'30xAA
5'30xCC
default
tƌŝƚĞŽƉƚŝŽŶƐŝŶĐůƵĚŝŶŐ
ZWтϬdžĂŶĚZWтϬdž
Write options including
RDP = 0xCC
Level 2
RDP = 0xCC
Write options including
RDP = 0xAA
Level 0
RDP = 0xAA
tƌŝƚĞŽƉƚŝŽŶƐŝŶĐůƵĚŝŶŐ
RDP сϬdž
ZWсϬdž
Other;ƐͿŽƉƚŝŽŶ;ƐͿŵŽĚŝĨŝĞĚ
Options write (RDP level identical) includes:
- Options page erase
- New options program
Options write (RDP level increase) includes:
- Options page erase
- New options program
Options write (RDP level decrease) includes:
- Full mass erase or partial mass erase to not erase PCROP pages if PCROP_RDP is cleared
- Backup registers and CCM SRAM erase
- Options page erase
- New options program
MSv60766V1
Table 13. Access status versus protection level and execution modes
Area
Main flash
memory
User execution (BootFromFlash)
Protection
level
Debug/ BootFromRam/
BootFromLoader/|BootFromSFI
/RSS
Read
Write
Erase
Read
Write
Erase
1
Yes
Yes
Yes
No
No
No(4)
2
Yes
Yes
Yes
N/A(1)
N/A(1)
N/A(1)
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Embedded flash memory (FLASH)
RM0461
Table 13. Access status versus protection level and execution modes (continued)
User execution (BootFromFlash)
Protection
level
Area
System
memory(2)
Option bytes
Backup
registers
SRAM2
Debug/ BootFromRam/
BootFromLoader/|BootFromSFI
/RSS
Read
Write
Erase
Read
Write
Erase
1
Yes
No
No
Yes
No
No
2
Yes
No
No
N/A(1)
N/A(1)
N/A(1)
1
Yes
Yes(3)
Yes
Yes
Yes(3)
Yes
(1)
N/A(1)
2
Yes
No
No
N/A
N/A(1)
1
Yes
Yes
N/A
No
No
No(4)
N/A(1)
N/A(1)
2
Yes
Yes
N/A
N/A(1)
1
Yes
Yes
N/A
No
No
No(5)
2
Yes
Yes
N/A
N/A(1)
N/A(1)
N/A(1)
1. When the protection level 2 is active, the debug port, the boot from RAM and the boot from system memory are disabled.
2. The system memory is only read-accessible, whatever the protection level (0, 1 or 2) and execution mode.
3. The Flash non secure main memory is erased when the RDP option byte is programmed from level 1 to level 0.
4. The backup registers are erased when RDP changes from level 1 to level 0.
5. SRAM1, SRAM2 and PKA SRAM are erased when RDP changes from level 1 to level 0.
3.5.2
Proprietary code readout protection (PCROP)
Two parts of the flash memory can be protected against read and write from third parties.
The protected area is execute-only: it can only be reached by the STM32 CPU with an
instruction code, while all other accesses (DMA, debug and CPU data read, write and
erase) are strictly prohibited. The PCROP areas have a 1-Kbyte granularity. An additional
option bit (PCROP_RDP) defines if the PCROP area is erased or not when the RDP
protection is changed from level 1 to level 0 (refer to Change the readout protection level).
Each PCROP area is defined by a start page offset and an end page offset into the flash
memory. These offsets are defined in the PCROP address registers (FLASH_PCROP1ASR,
FLASH_PCROP1AER), FLASH_PCROP1BSR and FLASH_PCROP1BER).
A PCROP area is defined from the address:
Flash memory base address + [PCROP1x_STRT x 0x400] (included) to the address
Flash memory base address + [(PCROP1x_END+1) x 0x400] (excluded).
The minimum PCROP area size is two PCROP pages (2 Kbytes)
PCROP1x_END = PCROP1x_STRT + 1.
When PCROP1x_END = PCROP1x_STRT, the full flash memory is PCROP protected.
For example, to protect by PCROP from the address 0x0801 2F80 (included) to the address
0x0801 D004 (included), if boot in flash is selected, one of the FLASH_PCROP1xSR and
FLASH_PCROP1xER registers (x =A or B) must be programmed with:
•
PCROP1x_STRT = 0x4B (PCROP area first address 0x0801 2C00)
•
PCROP1x_END = 0x74 (PCROP area last address 0x0801 D3FF)
Any data read access performed through a PCROP protected area triggers the RDERR flag
error.
88/1290
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RM0461
Embedded flash memory (FLASH)
Any PCROP protected address is also write protected and any write access to one of these
addresses triggers WRPERR.
Any PCROP area is also erase protected. Consequently, any erase to a page in this zone is
impossible (including the page containing the start address and the end address of this
zone). Moreover, a software mass erase cannot be performed if one zone is PCROP
protected.
In the previous example, due to erase by page, all pages from page 0x4B to 0x74 are
protected. In case of page erase, all addresses from 0x0801 2C00 to 0x0801 D3FF cannot
be erased.
Deactivation of PCROP can only occurs when the RDP is changing from level 1 to level 0. If
the user options modification tries to clear PCROP or to decrease the PCROP areas, the
options programming is launched but PCROP areas stays unchanged. On the contrary, it is
possible to increase the PCROP areas.
When option bit PCROP_RDP is cleared and when the RDP is changing from level 1 to
level 0, the full mass erase is replaced by a partial mass erase to preserve the PCROP area
(refer to Change the readout protection level). In this case, PCROP1x_STRT and
PCROP1x_END (x =A or B) are not erased.
Table 14: PCROP protection
PCROP registers values (x = A or B)
PCROP protection area
PCROP1x_STRT = PCROP1x_END
No PCROP1x, unprotected
PCROP1x_STRT > PCROP1x_END
No PCROP1x, unprotected
PCROP1x_STRT < PCROP1x_END
Pages from PCROP1x_STRT to PCROP1x_END are protected
Note:
It is recommended to align PCROP areas with the page granularity when using
PCROP_RDP, or to leave free the rest of the page where PCROP zones starts or ends.
3.5.3
Write protection (WRP)
The user area in the flash memory can be protected against unwanted write operations. Two
write-protected (WRP) areas can be defined, with 2-Kbyte granularity page. Each area is
defined by a start page offset and an end page offset related to the physical flash memory
base address. These offsets are defined in the WRP address registers FLASH_WRP1AR
and FLASH_WRP1BR.
The WRP “x” area (x = A, B) is defined from the address:
Flash memory Base address + [WRP1x_STRT x 0x800] (included) to the address:
Flash memory Base address + [(WRP1x_END+1) x 0x800] (excluded).
The minimum WRP area size is one WRP 2_Kbyte page, WRP1x_END = WRP1x_STRT.
For example, to protect by WRP from the address 0x0801 2000 (included) to the address
0x0801 9FFF (included), if boot in flash is selected, FLASH_WRP1AR register must be
programmed with:
•
WRP1A_STRT = 0x24
•
WRP1A_END = 0x33
RM0461 Rev 10
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Embedded flash memory (FLASH)
RM0461
WRP1B_STRT and WRP1B_END in FLASH_WRP1BR can be used instead (area “B” in
flash memory).
When WRP is active, it cannot be erased or programmed. Consequently, a software mass
erase cannot be performed if one area is write-protected.
If an erase/program operation to a write-protected part of the flash memory is attempted, the
write protection error flag (WRPERR) is set in FLASH_SR. This flag is also set for any write
access to on the following area:
Note:
•
OTP area
•
part of the flash memory that can never be written like the ICP
•
PCROP area
When the flash memory readout protection level is selected (RDP level1), it is not possible
to program or erase the memory if the CPU debug features are connected (JTAG or single
wire) or boot code is being executed from RAM or system flash, even if WRP is not
activated. Any attempt generates an hard fault (BusFault).
Table 15: WRP protection
WRPx registers values (x = A or B)
WRP protection area
WRP1x_STRT = WRP1x_END
Page WRP1x is protected
WRP1x_STRT > WRP1x_END
No WRP, unprotected
WRP1x_STRT < WRP1x_END
Pages from WRP1x_STRT to WRP1x_END are protected
Note:
To validate the WRP options, the option bytes must be reloaded through the OBL_LAUNCH
bit in FLASH_CR.
3.5.4
Security (ESE)
When OPTVAL option indicates “not valid” or the comparison between the user options
word and its complement fails (indicated in OPTVERR), the Flash memory is secured and
SRAM1, SRAM2 and PKA SRAM memories are erased. The CPU is no longer able to
execute firmware from the Flash memory. When booting in SRAM1, the CPU debug is
enabled. In this case, any CPU firmware can be downloaded in SRAM or JTAG can be used
to perform an RDP regression from level1 to level 0 with ESE = 0.This restores valid option
bytes and erases all user Flash memory, SRAM1, SRAM2 and PKA SRAM content.
3.5.5
CPU boot lock chain of trust
The BOOT_LOCK forces the CPU to boot from the user flash memory, regardless of what is
selected by BOOT0 and BOOT1. When BOOT_LOCK is enabled and BOOT0/BOOT1
select anything different than the user flash memory boot, the system boots anyway from
the user flash memory. System boot via BOOT0/BOOT1 from SRAM1 or bootloader is no
longer possible.
It is still possible to boot the CPU according to the software selected remap by MEM_MODE
bits in SYSCFG memory remap register (SYSCFG_MEMRMP) from SRAM1 or bootloader.
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3.6
Embedded flash memory (FLASH)
FLASH program erase suspension
Flash program and erase operation can be suspended by setting the PES bit in
FLASH_ACR. This feature is useful when executing time critical sections by a CPU. It
makes possible to suspend any new program or erase operation from being started,
preventing CPU instruction and data fetches from being blocked.
When PES bit is set, the following occurs:
•
Any ongoing program or erase operation is completed.
The maximum latency for a flash program erase suspension is the maximum time for
one program or erase operation to complete (see product datasheets for more
information on the flash program and erase timing).
•
All new requested program and erase operations is not started but suspended.
PESD bit in FLASH_SRis setas soon as PES is set, no matter if a program/erase is
currently suspended. This allows a CPU to test PESD prior to requesting a program or
an erase operation.
When PES bit is reset to 0, a suspended program or erase operation is started: the PESD
bit is cleared.
3.7
FLASH interrupts
Table 16. Flash interrupt requests
Interrupt event
Event flag
Event flag/interrupt
clearing method
Interrupt enable
control bit
EOP(1)
Write EOP=1
EOPIE
Operation error
(2)
OPERR
Write OPERR=1
ERRIE
Readout protection error
RDERR
Write RDERR=1
RDERRIE
Write protection error
WRPERR
Write WRPERR=1
N/A
Size error
SIZERR
Write SIZERR=1
N/A
Programming sequential error
PROGERR
Write PROGERR=1
N/A
Programming alignment error
PGAERR
Write PGAERR=1
N/A
Programming sequence error
PGSERR
Write PGSERR=1
N/A
Data miss during fast programming error
MISSERR
Write MISSERR=1
N/A
Fast programming error
FASTERR
Write FASTERR=1
N/A
ECC error correction
ECCC
Write ECCC=1
ECCCIE
ECC double-error (NMI)
ECCD
Write ECCD=1
N/A
End of operation
1. EOP is set only if EOPIE is set.
2. OPERR is set only if ERRIE is set.
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Embedded flash memory (FLASH)
RM0461
3.8
FLASH registers
3.8.1
FLASH access control register (FLASH_ACR)
Address offset: 0x000
Reset value: 0x0000 0600
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
EMPTY
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
PES
Res.
Res.
DCEN
ICEN
PRFTEN
Res.
Res.
Res.
Res.
Res.
rw
rw
rw
rw
rw
DCRST ICRST
rw
rw
0
LATENCY[2:0]
rw
rw
rw
Bits 31:17 Reserved, must be kept at reset value.
Bit 16 EMPTY: Flash user area empty
When read, this bit indicates whether the first location of the user flash is erased or has a
programmed value.
0: Read: user flash programmed
1: Read: user flash empty
Bit 15 PES: CPU program/erase suspend request
0: Flash program and erase operations granted
1: Any new flash program and erase operation is suspended until this bit is cleared. The
PESD bit in FLASH_SR is set when PES bit in FLASH_ACRis set.
Bits 14:13 Reserved, must be kept at reset value.
Bit 12 DCRST: CPU data cache reset
0: CPU data cache not reset
1: CPU data cache reset
This bit can be written only when the data cache is disabled.
Bit 11 ICRST: CPU instruction cache reset
0: CPU instruction cache not reset
1: CPU instruction cache reset
This bit can be written only when the instruction cache is disabled.
Bit 10 DCEN: CPU data cache enable
0: CPU data cache disabled
1: CPU data cache enabled
Bit 9 ICEN: CPU instruction cache enable
0: CPU instruction cache disabled
1: CPU instruction cache enabled
Bit 8 PRFTEN: CPU prefetch enable
0: CPU prefetch disabled
1: CPU prefetch enabled
Bits 7:3 Reserved, must be kept at reset value.
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Embedded flash memory (FLASH)
Bits 2:0 LATENCY[2:0]: Latency
These bits represent the ratio of the flash HCLK clock period to the flash memory access
time.
000: Zero wait state
001: One wait state
010: Two wait states
Others: reserved
3.8.2
FLASH key register (FLASH_KEYR)
Address offset: 0x008
Reset value: 0x0000 0000
s
31
30
29
28
27
26
25
24
w
w
w
w
w
w
w
w
15
14
13
12
11
10
9
8
23
22
21
20
19
18
17
16
w
w
w
w
w
w
w
w
7
6
5
4
3
2
1
0
w
w
w
w
w
w
w
KEY[31:16]
KEY[15:0]
w
w
w
w
w
w
w
w
w
Bits 31:0 KEY[31:0]: Flash key
The following values must be written consecutively to unlock FLASH_CR, thus enabling
programming/erasing operations:
KEY1: 0x4567 0123
KEY2: 0xCDEF 89AB
3.8.3
FLASH option key register (FLASH_OPTKEYR)
Address offset: 0x00C
Reset value: 0x0000 0000
s
31
30
29
28
27
26
25
24
w
w
w
w
w
w
w
w
15
14
13
12
11
10
9
8
23
22
21
20
19
18
17
16
w
w
w
w
w
w
w
w
7
6
5
4
3
2
1
0
w
w
w
w
w
w
w
OPTKEY[31:16]
OPTKEY[15:0]
w
w
w
w
w
w
w
w
w
Bits 31:0 OPTKEY[31:0]: Option byte key lower bits
The following values must be written consecutively to unlock the flash memory option
registers, enabling option byte programming/erasing operations:
KEY1: 0x0819 2A3B
KEY2: 0x4C5D 6E7F
3.8.4
FLASH status register (FLASH_SR)
Address offset: 0x010
Reset value: 0x000X 0000
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Embedded flash memory (FLASH)
RM0461
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PESD
CFGBSY
Res.
BSY
r
r
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OPTVERR
RDERR
OPTNV
Res.
Res.
Res.
FASTERR
MISSERR
PGSERR
SIZERR
PGAERR
WRPERR
PROGERR
Res.
OPERR
r
15
EOP
rc_w1
rc_w1
r
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
Bits 31:20 Reserved, must be kept at reset value.
Bit 19 PESD: Program/erase operation suspended
This bit is set and reset by hardware.
Set when PES bit in FLASH_ACR is set.
Cleared when PES bitin FLASH_ACRis cleared.
When set, new program or erase operations are not started.
Bit 18 CFGBSY: Program or erase configuration busy
This bit is set and reset by hardware (set when first word is sent and reset when program
operation completes or is interrupted by an error).
When set, the program and erase settings in PG, PNB[6:0], PER, and MER bits in
FLASH_CR are used (busy) and cannot be changed (a programming or erase operation is
ongoing).
When reset, the program and erase settings in PG, PNB[6:0], PER, and MER bits in
FLASH_CR can be modified.
Bit 17 Reserved, must be kept at reset value.
Bit 16 BSY: Busy
This bit indicates that a flash operation requested in FLASH_CR is in progress. This bit is set
at the beginning of a flash operation and reset when the operation finishes or when an error
occurs.
Bit 15 OPTVERR: Option and engineering bits loading validity error
Set by hardware when the options and engineering bits read may not be the one configured
by the user or production. If options and engineering bits are not properly loaded, OPTVERR
is set again after each system reset. Option bytes that fail loading are forced to a safe value
(see Section 3.4.2: Option bytes programming).
This bit is cleared by writing 1.
Bit 14 RDERR: PCROP read error
Set by hardware when an address to be read through the D-bus belongs to a read protected
area of the flash memory (PCROP protection). An interrupt is generated if RDERRIE is set in
FLASH_CR.
This bit is cleared by writing 1.
Bit 13 OPTNV: User option OPTVAL indication
This bit is set and reset by hardware.
0: The OBL user option OPTVAL indicates “valid” (user option program sequence has not
terminated completely).
1: The OBL user option OPTVAL indicates “not valid” (OPTVAL check word has been
erroneously read).
Bits 12:10 Reserved, must be kept at reset value.
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Embedded flash memory (FLASH)
Bit 9 FASTERR: Fast programming error
Set by hardware when a fast programming sequence (activated by FSTPG) is interrupted
due to an error (alignment, size, write protection or data miss). The corresponding status bit
(PGAERR, SIZERR, WRPERR or MISSERR) is set at the same time.
This bit is cleared by writing 1.
Bit 8 MISSERR: Fast programming data miss error
In Fast programming mode, 32 double-words (256 bytes) must be sent to the flash memory
successively and the new data must be sent to the logic control before the current data is
fully programmed.
This bit is set by hardware when the new data is not present in time and cleared by writing 1.
Bit 7 PGSERR: Programming sequence error
This bit is set by hardware when a write access to the flash memory is performed by the
code, while PG or FSTPG have not been set previously. This bit is also set by hardware
when PROGERR, SIZERR, PGAERR, WRPERR, MISSERR or FASTERR is set due to a
previous programming error.
This bit is cleared by writing 1.
Bit 6 SIZERR: Size error
This bit is set by hardware when the size of the access is a byte or half-word during a
program or a fast program sequence. Only double-word programming is allowed
(consequently: word access).
This bit is cleared by writing 1.
Bit 5 PGAERR: Programming alignment error
This bit is set by hardware when the data to program cannot be contained in the same
double-word (64 bits) flash memory in case of standard programming, or if there is a change
of page during fast programming.
This bit is cleared by writing 1.
Bit 4 WRPERR: Write protection error
This bit is set by hardware when an address to be erased/programmed belongs to a writeprotected part (by WRP, PCROP or RDP level 1) of the flash memory.
This bit is cleared by writing 1.
Bit 3 PROGERR: Programming error
This bit is set by hardware when a double-word address to be programmed contains a value
different from 0xFFFF FFFF FFFF FFFF before programming, except if the data to write is
0x0000 0000 0000 0000.
This bit is cleared by writing 1.
Bit 2 Reserved, must be kept at reset value.
Bit 1 OPERR: Operation error
This bit is set by hardware when a flash memory operation (program/erase) completes
unsuccessfully. This bit is set only if error interrupts are enabled (ERRIE = 1).
This bit is cleared by writing 1.
Bit 0 EOP: End of operation
This bit is set by hardware when one or more flash memory operation (program/erase)
completes successfully. This bit is set only if the end of operation interrupts are enabled
(EOPIE = 1).
This bit is cleared by writing 1.
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Embedded flash memory (FLASH)
3.8.5
RM0461
FLASH control register (FLASH_CR)
Address offset: 0x014
Reset value: 0xC000 0000
Access: no wait state when no flash memory operation is ongoing. Word, half-word and byte
access.
This register cannot be modified when CFGBSY is set in FLASH_SR.
When PESD is cleared in FLASH_SR, the register write access is stalled until the CFGBSY
bit is cleared.
When PESD is set in FLASH_SR and a program or an erase operation is ongoing, the
register write access causes a bus error.
When PESD is set in FLASH_SR but there is no ongoing programming or erase operation,
the register write access is completed, but the requested operation is suspended.
BSY/CFGBSY is set and remains 1 until suspend is deactivated by clearing the PES bits in
FALSH_ACR. Consequently PESD goes back to 0 and the suspended operation completes.
31
30
LOCK
OPT
LOCK
29
28
27
26
Res.
Res.
OBL_
LAUNCH
RD
ERRIE
25
24
ERRIE
EOPIE
rs
rs
rc_w1
rw
rw
rw
15
14
13
12
11
10
9
8
Res.
Res.
Res.
Res.
Res.
Res.
23
22
21
20
19
Res.
Res.
Res.
Res.
Res.
7
6
5
4
3
PNB[6:0]
rw
rw
rw
rw
rw
rw
rw
18
17
16
FSTPG
OPT
STRT
STRT
rw
rs
rs
2
1
0
MER
PER
PG
rw
rw
rw
Bit 31 LOCK: FLASH_CR lock
This bit can only be set by software. When set, the FLASH_CR register is locked. This bit is
cleared by hardware after detecting the unlock sequence.
In case of an unsuccessful unlock operation, this bit remains set until the next system reset.
Bit 30 OPTLOCK: Options lock
This bit can only be set by software. When set, all bits concerning user option in FLASH_CR
and so option page are locked. This bit is cleared by hardware after detecting the option
unlock sequence. The LOCK bit must be cleared before doing the unlock sequence for
OPTLOCK bit.
In case of an unsuccessful option unlock operation, this bit remains set until the next reset.
Bits 29:28 Reserved, must be kept at reset value.
Bit 27 OBL_LAUNCH: forces the option byte loading
When set to 1, this bit forces the option byte reloading. This bit is cleared only when the
option byte loading is complete. It cannot be written if OPTLOCK is set.
0: Option byte loading completed
1: Option byte loading requested
Bit 26 RDERRIE: PCROP read error interrupt enable
This bit enables the interrupt generation when the RDERR bit in FLASH_SR is set to 1.
0: PCROP read error interrupt disabled
1: PCROP read error interrupt enabled
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Embedded flash memory (FLASH)
Bit 25 ERRIE: error interrupt enable
This bit enables the interrupt generation when the OPERR bit in FLASH_SR is set to 1.
0: OPERR error interrupt disabled
1: OPERR error interrupt enabled
Bit 24 EOPIE: end of operation interrupt enable
This bit enables the interrupt generation when the EOP bit in FLASH_SR is set to 1.
0: EOP Interrupt disabled
1: EOP Interrupt enabled
Bits 23:19 Reserved, must be kept at reset value.
Bit 18 FSTPG: fast programming
0: Fast programming disabled
1: Fast programming enabled
Bit 17 OPTSTRT: options modification start
When set, this bit triggers an options programming operation. When RDP level is regressed
from level 1 to level 0, this bit also launches a flash memory, SRAM1 and SRAM2 erase.
This bit is set only by software and cleared when BSY is cleared in FLASH_SR.
Bit 16 STRT: start
When set, this bit triggers an erase operation. If MER and PER are reset and STRT is set, an
unpredictable behavior may occur without generating any error flag. This condition is
forbidden.
This bit is set only by software and cleared when BSY is cleared in FLASH_SR.
Bits 15:10 Reserved, must be kept at reset value.
Bits 9:3 PNB[6:0]: page number selection
These bits select the 2-Kbyte page to erase.
0x00: page 0
0x01: page 1
...
0x3F: page 63
Bit 2 MER: mass erase
When set, this bit triggers the mass erase (all user pages).
Bit 1 PER: page erase
0: page erase disabled
1: page erase enabled
Bit 0 PG: programming
0: Flash programming disabled
1: Flash programming enabled
3.8.6
FLASH ECC register (FLASH_ECCR)
Address offset: 0x018
Reset value: 0x0000 0000
Access: no wait state when no flash memory operation is ongoing. Word, half-word and byte
access.
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RM0461
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
ECCD
ECCC
Res.
Res.
Res.
Res.
Res.
ECCCIE
Res.
Res.
Res.
SYSF_ECC
Res.
Res.
Res.
ADDR_ECC[16]
rc_w1
rc_w1
15
14
rw
13
12
11
10
9
8
r
7
6
r
5
4
3
2
1
0
r
r
r
r
r
r
ADDR_ECC[15:0]
r
r
r
r
r
r
r
r
r
r
Bit 31 ECCD: ECC detection
Set by hardware when two ECC errors have been detected. When this bit is set, a NMI is
generated.
This bit is cleared by writing 1.
Bit 30 ECCC: ECC correction
Set by hardware when one ECC error has been detected and corrected. An interrupt is
generated if ECCIE is set.
This bit is cleared by writing 1.
Bits 29:25 Reserved, must be kept at reset value.
Bit 24 ECCCIE: ECC correction interrupt enable
0: ECCC interrupt disabled
1: ECCC interrupt enabled
Bits 23:21 Reserved, must be kept at reset value.
Bit 20 SYSF_ECC: system flash memory ECC fail
This bit indicates that the ECC error correction or double ECC error detection is located in
the system flash memory.
Bits 19:17 Reserved, must be kept at reset value.
Bits 16:0 ADDR_ECC[16:0]: ECC fail double-word address
This bit indicates that double-word address is concerned by the ECC error correction or
causes the double ECC error detection.
3.8.7
FLASH option register (FLASH_OPTR)
Address offset: 0x020
Reset value: 0x3FFF F0AA
Default reset value from ST production is given. Subsequently, 0bXX11 XXXX X111 XXXX
1XXX XXXX XXXX XXXX, the option bits are loaded with user values from the flash
memory at reset release.
Access: no wait state when no flash memory operation is ongoing. Word, half-word and byte
access.
This register can only be written by the CPU in RDP level 0 or RDP level 1.
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Embedded flash memory (FLASH)
26
25
24
23
22
21
20
Res.
BOOT_
LOCK
Res.
Res.
Res.
Res.
Res.
rw
15
Res.
14
13
12
nBOOT1
27
SRAM2_PE
28
SRAM_RST
29
nSWBOOT0
30
nBOOT0
31
rw
rw
rw
rw
rw
11
10
9
8
7
nRST_ nRST_ nRST_
SHDW STDBY STOP
rw
rw
rw
BOR_LEV[2:0]
rw
rw
6
5
ESE
rw
rw
19
18
17
16
WWDG IWDG_ IWDG_ IWDG_
_SW STDBY STOP
SW
4
rw
rw
rw
rw
3
2
1
0
rw
rw
rw
RDP[7:0]
rw
rw
rw
rw
rw
Bit 31 Reserved, must be kept at reset value.
Bit 30 BOOT_LOCK: CPU boot lock enable option bit
This bit may be set by software at any time, but a write to clear is only taken into account in
one of the following conditions:
- when staying in RDP level 0
- when regressing RDP level from 1 to 0
0: CPU boot lock disabled
1: CPU boot lock enabled
Bits 29:28 Reserved, must be kept at reset value.
Bit 27 nBOOT0: nBOOT0 option bit
If nSWBOOT0 bit selects BOOT0 to be taken from option bit nBOOT0, then this bit,
together with option nBOOT1, selects the boot modes (from the user flash memory, SRAM1
or system flash memory). Refer to Section 2.2: Boot configuration.
0: nBOOT0 = 0
1: nBOOT0 = 1
Bit 26 nSWBOOT0: software BOOT0 selection
0: BOOT0 taken from the option bit nBOOT0
1: BOOT0 taken from PH3/BOOT0 pin
Bit 25 SRAM_RST: SRAM1 and SRAM2 erase when system reset
0: SRAM1 and SRAM2 erased when a system reset occurs
1: SRAM1 and SRAM2 not erased when a system reset occurs
Note: PKA SRAM is always erased on any system.
Bit 24 SRAM2_PE: SRAM2 parity check enable
0: SRAM2 parity check enabled
1: SRAM2 parity check disable
Bit 23 nBOOT1: boot configuration
Together with the BOOT0 pin or option bit nBOOT0 (depending on nSWBOOT0 option bit
configuration), this bit selects boot mode from the user flash memory, SRAM or system
flash memory. Refer to Section 2.2: Boot configuration.
Bits 22:20 Reserved, must be kept at reset value.
Bit 19 WWDG_SW: window watchdog selection
0: Hardware window watchdog
1: Software window watchdog
Bit 18 IWDG_STDBY: independent watchdog counter freeze in Standby mode
0: Independent watchdog counter frozen in Standby mode
1: Independent watchdog counter running in Standby mode
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RM0461
Bit 17 IWDG_STOP: independent watchdog counter freeze in Stop mode
0: Independent watchdog counter frozen in Stop mode
1: Independent watchdog counter running in Stop mode
Bit 16 IWDG_SW: independent watchdog selection
0: Hardware independent watchdog
1: Software independent watchdog
Bit 15 Reserved, must be kept at reset value.
Bit 14 nRST_SHDW: reset generation in Shutdown mode
0: Reset generated when entering the Shutdown mode
1: No reset generated when entering the Shutdown mode
Bit 13 nRST_STDBY: reset generation in Standby mode
0: Reset generated when entering the Standby mode
1: No reset generated when entering the Standby mode
Bit 12 nRST_STOP: reset generation in Stop mode
0: Reset generated when entering the Stop mode
1: No reset generated when entering the Stop mode
Bits 11:9 BOR_LEV[2:0]: BOR reset Level
These bits contain the VDD supply level threshold that activates/releases the reset.
000: BOR level 0. Reset level threshold is ~ 1.7 V
001: BOR level 1. Reset level threshold is ~ 2.0 V
010: BOR level 2. Reset level threshold is ~ 2.2 V
011: BOR level 3. Reset level threshold is ~ 2.5 V
100: BOR level 4. Reset level threshold is ~ 2.8 V
Bit 8 ESE: system security enable flag
When read, this bit indicates whether the system security is enabled, meaning a not valid
option byte has been loaded. Writing 0 to this bit and regressing the RDP from level 1 to
level 0 disables the security.
0: Security disabled
1: Security enabled
Bits 7:0 RDP[7:0]: readout protection level
0xAA: Level 0, readout protection not active
0xCC: Level 2, chip readout protection active
Others: Level 1, memories readout protection active
Note: Take care about PCROP_RDP configuration in level 1. Refer to Level 1: readout
protection for more details.
3.8.8
FLASH PCROP zone A start address register
(FLASH_PCROP1ASR)
Address offset: 0x024
Reset value: 0xFFFF FFFF
Default reset value from ST production is given. Subsequently, 0b1111 1111 1111 1111 1111
1111 XXXX XXXX, the option bits are loaded with user values from the flash memory at
reset release.
Access: no wait state when no flash memory operation is ongoing. Word, half-word access.
This register can only be written by the CPU in RDP level 0 or RDP level 1.
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Embedded flash memory (FLASH)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
7
6
5
4
3
2
1
0
rw
rw
rw
15
14
13
12
11
10
9
8
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PCROP1A_STRT[7:0]
rw
rw
rw
rw
rw
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 PCROP1A_STRT[7:0]: PCROP1A area start offset
PCROP1A_STRT contains the first 1-Kbyte page of the PCROP1A area.
3.8.9
FLASH PCROP zone A end address register
(FLASH_PCROP1AER)
Address offset: 0x028
Reset value: 0xFFFF FF00
Default reset value from ST production is given. Subsequently, 0bX111 1111 1111 1111 1111
1111 XXXX XXXX, the option bits are loaded with user values from flash memory at reset
release.
Access: no wait state when no flash memory operation is ongoing. Word, half-word access.
PCROP_RDP bit can be accessed with byte access
This register can only be written by the CPU in RDP level 0 or RDP level 1.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
PCROP
_RDP
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
7
6
5
4
3
2
1
0
rw
rw
rw
rs
15
14
13
12
11
10
9
8
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PCROP1A_END[7:0]
rw
rw
rw
rw
rw
Bit 31 PCROP_RDP: PCROP area preserved when RDP level decreased
This bit is set only. It is reset after a full mass erase due to a change of RDP from level 1 to
level 0.
0: PCROP area not erased when the RDP level is decreased from level 1 to level 0
1: PCROP area erased when the RDP level is decreased from level 1 to level 0 (full mass
erase)
Bits 30:8 Reserved, must be kept at reset value.
Bits 7:0 PCROP1A_END[7:0]: PCROP1A area end offset
PCROP1A_END contains the last 1-Kbyte page of the PCROP1A area.
3.8.10
FLASH WRP area A address register (FLASH_WRP1AR)
Address offset: 0x02C
Reset value: 0xFF80 FFFF
RM0461 Rev 10
101/1290
105
Embedded flash memory (FLASH)
RM0461
Default reset value from ST production is given as.0b1111 1111 1XXX XXXX 1111 1111
1XXX XXXX, the option bits are loaded with user values from the flash memory at reset
release.
Access: no wait state when no flash memory operation is ongoing. Word, half-word and byte
access.
This register can only be written by the CPU in RDP level 0 or RDP level 1.
31
30
29
28
27
26
25
24
23
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
22
21
20
19
18
17
16
WRP1A_END[6:0]
rw
rw
rw
rw
rw
rw
rw
6
5
4
3
2
1
0
rw
rw
WRP1A_STRT[6:0]
rw
rw
rw
rw
rw
Bits 31:23 Reserved, must be kept at reset value.
Bits 22:16 WRP1A_END[6:0]: WRP area A end offset
Contains the last 2-Kbyte page of the WRP area A.
Bits 15:7 Reserved, must be kept at reset value.
Bits 6:0 WRP1A_STRT[6:0]: WRP area A start offset
Contains the first 2-Kbyte page of the WRP area A.
3.8.11
FLASH WRP area B address register (FLASH_WRP1BR)
Address offset: 0x030
Reset value: 0xFF80 FFFF
Default reset value from ST production is given as 0b1111 1111 1XXX XXXX 1111 1111
1XXX XXXX, the option bits are loaded with user values from flash memory at reset release.
Access: no wait state when no flash memory operation is ongoing. Word, half-word and byte
access.
This register can only be written by the CPU in RDP level 0 or RDP level 1.
31
30
29
28
27
26
25
24
23
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
22
21
20
19
16
rw
rw
rw
rw
rw
rw
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
WRP1B_STRT[6:0]
rw
Bits 22:16 WRP1B_END[6:0]: WRP area B end offset
WRPB1_END contains the last 2-Kbyte page of the WRP area B.
Bits 15:7 Reserved, must be kept at reset value.
Bits 6:0 WRP1B_STRT[6:0]: WRP area B start offset
WRPB1_END contains the first 2-Kbyte page of the WRP area B.
RM0461 Rev 10
17
rw
Bits 31:23 Reserved, must be kept at reset value.
102/1290
18
WRP1B_END[6:0]
rw
RM0461
Embedded flash memory (FLASH)
3.8.12
FLASH PCROP zone B start address register
(FLASH_PCROP1BSR)
Address offset: 0x034
Reset value: 0xFFFF FFFF
Default reset value from ST production is given. Subsequently, 0b1111 1111 1111 1111 1111
1111 XXXX XXXX, the option bits are loaded with user values from the flash memory at
reset release.
Access: no wait state when no flash memory operation is ongoing. Word and half-word
access.
This register can only be written by the CPU in RDP level 0 or RDP level 1.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
rw
rw
rw
rw
rw
rw
PCROP1B_STRT[7:0]
rw
rw
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 PCROP1B_STRT[7:0]: PCROP1B area start offset
Contains the first 1-Kbyte page of the PCROP1B area.
3.8.13
FLASH PCROP zone B end address register
(FLASH_PCROP1BER)
Address offset: 0x038
Reset value: 0xFFFF FF00
Default reset value from ST production is given. Subsequently, 0b1111 1111 1111 1111 1111
1111 XXXX XXXX, the option bits are loaded with user values from the flash memory at
reset release.
Access: no wait state when no flash memory operation is ongoing. Word and half-word
access.
This register can only be written by the CPU in RDP level 0 or RDP level 1.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
7
6
5
4
3
2
1
0
rw
rw
rw
15
14
13
12
11
10
9
8
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PCROP1B_END[7:0]
rw
rw
rw
rw
rw
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 PCROP1B_END[7:0]: PCROP1B area end offset
Contains the first 1-Kbyte page of the PCROP1B area.
RM0461 Rev 10
103/1290
105
0x030
104/1290
FLASH_
WRP1BR
Reset value
0
0
0
0
0
WRP1B_END[6:0]
0
RM0461 Rev 10
0
Res.
0
0
Res.
Res.
0
0
0
0
0
0
0
.ESE
0
Res.
0
Reset value
Res.
Res.
0
Res.
0
Res.
Res.
1
0
0
Res.
Res.
0
0
0
0
0
0
0
0
0
0
0
0
0
FLASH_SR
Res.
Res.
Res.
PESD
Res.
Res.
Res.
FASTERR
MISSERR
PGSERR
SIZERR
X
0
0
0
0
Res.
Res.
Res.
0
Res.
0
OPTNV
0
Res.
0
0
Res.
nRST_STOP
1
Res.
0
0
Res.
nRST_STDBY
1
Res.
0
RDERR
0
OPTVERR
0
Res.
0
Res.
0
X
Res.
Res.
1
Res.
0
X
Res.
Res.
Res.
nRST_SHDW
BOR_LEV
[2:0]
Res.
0
Res.
0
0
1
1
0
0
0
ADDR_ECC[16:0]
0
RDP[7:0]
0
1
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
1
0
1
0
1
1
EOP
0
0
0
0
PG
0
PER
1
Res.
OPERR
ICEN
PRFTEN
1
MER
DCEN
0
Res.
Res.
Res.
Res.
Res.
ICRST
0
PROGERR
WRPERR
PNB[6:0]
PGAERR
PES
Res.
Res.
EMPTY
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DCRST
0
Res.
0
0
Res.
0
Res.
0
Res.
KEYR[31:0]
Res.
0
0
Res.
STRT
0
Res.
BSY
OPTSTRT
0
Res.
0
Res.
FLASH_KEYR
Res.
WRP1A_END[6:0]
Res.
Res.
0
IWDG_SW
1
Res.
0
CFGBSY
0
Res.
0
Res.
Reserved.
Res.
0
0
Res.
IWDG_STOP
1
Res.
Res.
Res.
Res.
FSTPG
Res.
Res.
SYSF_ECC
Res.
0
Res.
Reserved
Res.
0
Res.
IWDG_STDBY
1
Res.
Res.
Res.
WWDG_SW
Res.
Res.
Res.
Res.
Res.
ECCCIE
Res.
EOPIE
Res.
0
Res.
FLASH_
OPTKEYR
0
Res.
0
0
0
Res.
0
0
Res.
Res.
0
0
Res.
Res.
ERRIE
Res.
0
Res.
Reset value
Reset value
Res.
Reset value
Res.
Reset value
0
Res.
1
0
Res.
nBOOT1
1
Res.
SRAM2_PE
1
Res.
RDERRIE
0
Res.
.nSWBOOT0
SRAM_RST
1
Res.
0
0
Res.
.nBOOT0
1
Res.
Res.
OBL_LAUNCH
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
BOOT_LOCK
0
Res.
FLASH_
WRP1AR
0
Res.
1
0
Res.
Reset value
Res.
0
0
Res.
0x02C
FLASH_
PCROP1AER
0
Res.
0x028
FLASH_
PCROP1ASR
Res.
0x024
Res.
0
0
Res.
0
Res.
OPTLOCK
Reset value
Res.
FLASH_ECCR
Res.
Reset value
Res.
1
Res.
1
FLASH_OPTR
Res.
0x010
0
Res.
0x00C
0
Res.
Reset value
Res.
0x004
Res.
FLASH_ACR
Res.
LOCK
0x020
Reset value
ECCC
0x018
FLASH_CR
ECCD
0x014
Res.
0x008
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Register
name
Res.
0x000
PCROP_RDP.
Offset
Res.
3.8.14
Res.
Embedded flash memory (FLASH)
RM0461
FLASH register map
Table 17. Flash interface register map and reset values
1
1
0
1
1
LATENCY
[2:0]
0
0
0
0
0
0
0
OPTKEY[31:0]
0
0
0
PCROP1A_STRT[7:0]
1
0
1
1
1
0
1
1
1
PCROP1A_END[7:0]
0
WRP1A_STRT[6:0]
1
WRP1B_STRT[6:0]
1
RM0461
Embedded flash memory (FLASH)
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
FLASH_
PCROP1BSR
Res.
0x034
Register
name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Offset
Res.
Table 17. Flash interface register map and reset values (continued)
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
1
Res.
0x038
FLASH_
PCROP1BER
Res.
Reset value
PCROP1B_STRT[7:0]
1
1
1
1
1
1
1
PCROP1B_END[7:0]
0
0
0
0
0
0
0
0
Refer to Section 2.4 for the register boundary addresses.
RM0461 Rev 10
105/1290
105
Sub-GHz radio (SUBGHZ)
RM0461
4
Sub-GHz radio (SUBGHZ)
4.1
Sub-GHz radio introduction
The sub-GHz radio is an ultra-low-power sub-GHz radio operating in the 150 - 960 MHz ISM
band. LoRa® and (G)FSK modulation in transmit and receive, and BPSK/(G)MSK
in transmit only, allow an optimal trade-off between range, data rate and power
consumption. This sub-GHz radio is compliant with the LoRaWAN® specification v1.0 and
radio regulations including ETSI EN 300 220, EN 300 113, EN 301 166, FCC CFR 47 part
15, 24, 90, 101 and the ARIB STD-T30, T-67, T-108.
Features related to the LoRa modulation are only available on STM32WLE5xx devices, that
support LoRa.
The sub-GHz radio consists of:
4.2
•
an analog front end transceiver, capable of outputting + 15 dBm maximum power on
the RFO_LP pin and + 22 dBm maximum power on the RFO_HP pin
•
a digital modem bank providing the following modulation schemes:
–
LoRa Rx/Tx with bandwidth (BW) from 7.8 - 500 kHz, spreading factor (SF)
5 - 12, bit rate (BR) from 0.013 to 17.4 Kbit/s (real bitrate)
–
FSK and GFSK Rx/Tx with BR from 0.6 to 300 Kbit/s
–
(G)MSK Tx with BR from 0.1 to 10 Kbit/s
–
BPSK Tx with bitrate for 100 and 600 bit/s
•
a digital control comprising all data processing and sub-GHz radio configuration control
•
a high-speed clock generation
Sub-GHz radio main features
The main features of the sub-GHz radio are listed below:
•
Half-duplex 150 - 960 MHz ISM sub-GHz radio transceiver supporting:
–
LoRa modulation
–
(G)FSK modulation
–
(G)MSK Tx modulation
–
BPSK Tx modulation
•
Programmable output power up to + 22 dBm
•
Low-IF architecture, mixing the RF receive signal with a signal tone located in the
negative frequency
flo = - frf + fif where flo is the local RF-PLL oscillator frequency, frf is the wanted receive
signal and fif is the intermediate frequency
•
106/1290
Automatic I/Q calibration to improve image rejection
RM0461 Rev 10
RM0461
Sub-GHz radio (SUBGHZ)
4.3
Sub-GHz radio functional description
4.3.1
General description
The sub-GHz radio provides an internal processing unit to handle communication with the
system CPU. Communication is handled by commands sent over the SPI interface, and a
set of interrupts is used to signal events. BUSY information signals operation activity and is
used to indicate when the sub-GHz radio commands cannot be received.
The block diagram of the sub-GHz radio system is shown in the figure below.
Figure 5. Sub-GHz radio system block diagram
VDDPA
Sub-GHz radio
VR_PA
SUBGHZSPI
FSK
modem
RFO_HP
BUSY
RFO_LP
RFI_P
Interrups
Radio
control
Sub-GHz
RF frontend
RFI_N
LoRa
modem
PB0_VDDTCXO
Data
and
control
HSEON
HSEBYPPWR
(note)
OSC_IN
HSERDY
OSC_OUT
HSE32
hse32
MSv62615V1
Note: LoRa modem is only available on STM32WLE5xx devices.
4.3.2
Sub-GHz radio signals
Table 18 gives the list of sub-GHz radio signals.
Table 18. Sub-GHz internal input/output signals
Signal name
Signal type
RFO_HP
RF output
Transmit high-power PA output
RFO_LP
RF output
Transmit low-power PA output
RFI_P
RF input
Receiver differential P input
RFI_N
RF input
Receiver differential N input
OSC_IN
Analog input
HSE32 oscillator input
OSC_OUT
Analog output
HSE32 oscillator output
VDDPA
Supply
Input supply for PA regulator
VR_PA
Supply
Regulated PA supply output
PB0_VDDTCXO
Supply
Regulated TCXO supply output
hse32
Digital output
HSE32 clock signal to CPU
HSEON
Digital input
Enable HSE32 clock for CPU usage
HSEBYPPWR
Digital input
Enable VDDTCXO regulator control
RM0461 Rev 10
Description
107/1290
178
Sub-GHz radio (SUBGHZ)
RM0461
Table 18. Sub-GHz internal input/output signals (continued)
4.3.3
Signal name
Signal type
Description
HSERDY
Digital output
HSE32 clock ready indication
SUBGHZSPI
Digital in/output
Sub-GHz radio SPI interface
BUSY
Digital output
BUSY signal
Interrupts
Digital output
IRQ interrupts
Transmitter
The transmit chain comprises the modulated output from the modem, that directly
modulates the RF-PLL. An optional pre-filtering of the bit stream can be enabled to reduce
the power in the adjacent channel also dependent on the selected modulation scheme. The
modulated signal from the RF-PLL directly drives the high-power PA (HP PA) or low-power
PA (LP PA).
Transmitter high output power
Transmit high output power up to + 22 dBm, is supported through the RFO_HP RF pin. The
HP PA can be supplied from the PA regulator (REG PA) up to 3.1 V.
For this, the REG PA must be supplied directly from VDD (on VDDSMPS pin), as shown in
Figure 6.
Figure 6. High output power PA
SMPS mode
LDO mode
VDD
VDD
VDDSMPS (1.8 to 3.6V)
VDDSMPS (1.8 to 3.6V)
VLXSMPS
VLXSMPS
LDO/SMPS
LDO/SMPS
VFBSMPS (1.55V)
VFBSMPS (1.55V)
VDD
VDD
VDDPA
VDDPA
VR_PA (up to 3.1V)
REG
PA
VR_PA (up to 3.1V)
REG
PA
RFO_HP
HP PA
RFO_HP
HP PA
Note: Use of the SMPS is optional. When SMPS is not used, the BOM can be reduced by removing the coil
between VLXSMPS and VFBSMPS pins.
108/1290
RM0461 Rev 10
MSv62616V2
RM0461
Sub-GHz radio (SUBGHZ)
Table 19 gives the maximum transmit output power versus the VDDPA supply level.
Table 19. Sub-GHz radio transmit high output power
VDDPA supply (V)
Transmit output power (dBm)
3.3
+ 22
2.7
+ 20
2.4
+ 19
1.8
+ 16
Transmitter low output power
The transmit low output power up to + 15 dBm, is supported through the RFO_LP pin. The
LP PA can be supplied from the PA regulator (REG PA) up to 1.35 V. For this, the REG PA
must be supplied from the regulated VFBSMPS supply at 1.55 V, as shown in the figure
below.
The output power range is programmable in 32 steps of ~1 dB. The power amplifier ramping
timing is also programmable.This allows adaptation to meet radio regulation requirements.
Figure 7. Low output power PA
LDO mode
SMPS mode
VDD
VDD
VDDSMPS (1.8 to 3.6V)
VDDSMPS (1.8 to 3.6V)
VLXSMPS
VLXSMPS
LDO/SMPS
LDO/SMPS
VFBSMPS (1.55V)
VFBSMPS (1.55V)
VDDPA
VDDPA
VR_PA (up to 1.35V)
REG
PA
VR_PA (up to 1.35V)
REG
PA
RFO_LP
RFO_LP
LP PA
LP PA
Note: Use of the SMPS is optional. When SMPS is not used, the BOM can be reduced by removing the coil
between VLXSMPS and VFBSMPS pins.
4.3.4
MSv62617V2
Receiver
The receive chain comprises a differential low-noise amplifier (LNA), a down-converter to
low-IF by mixer operation in quadrature configuration. The I and Q signals are low pass
filtered and a Ʃ∆ ADC converts them into the digital domain. In the digital modem, the
signals are decimated, further down converted and channel filtered. The demodulation is
done according to the selected modulation scheme.
The down mixing to low-IF is done by mixing the receive signal with the local RF-PLL
located in the negative frequency, where -flo = -frf + fif. (where flo is the local RF-PLL
RM0461 Rev 10
109/1290
178
Sub-GHz radio (SUBGHZ)
RM0461
frequency, frf is the received signal and fif is the intermediate frequency). The wanted signal
is located at frf = flo + fif.
The receiver features automatic I and Q calibration, that improves image rejection. The
calibration is done automatically at startup before using the receiver, and can be requested
by command (see Image calibration for specific frequency bands for more details).
The receiver supports LoRa and (G)FSK modulations.
4.3.5
RF-PLL
The RF-PLL is used as the frequency synthesizer for the generation of the local oscillator
frequency (flo) for both transmit and receive chains. The RF-PLL uses auto calibration and
uses the 32 MHz HSE32 reference. The sub-GHz radio covers all continuous frequencies in
the range between 150 to 960 MHz.
4.3.6
Intermediate frequencies
The sub-GHz radio receiver operates mostly in low-IF configuration, except for specific highbandwidth settings.
Table 20. FSK mode intermediate frequencies
110/1290
Setting name
Bandwidth (kHz)
RX_BW_467
467.0
RX_BW_234
234.3
RX_BW_117
117.3
RX_BW_58
58.6
RX_BW_29
29.3
RX_BW_14
14.6
RX_BW_7
7.3
RX_BW_373
373.6
RX_BW_187
187.2
RX_BW_93
93.8
RX_BW_46
46.9
RX_BW_23
23.4
RX_BW_11
11.7
RX_BW_5
5.8
RX_BW_312
312.0
RX_BW_156
156.2
RX_BW_78
78.2
RX_BW_39
39.0
RX_BW_19
19.5
RX_BW_9
9.7
RX_BW_4
4.8
RM0461 Rev 10
fif (kHz)
250
200
167
RM0461
Sub-GHz radio (SUBGHZ)
Table 21. LoRa mode intermediate frequencies
Setting name
Bandwidth [kHz]
fif [kHz]
LORA_BW_500
500
0
LORA_BW_250
250
LORA_BW_125
125
LORA_BW_62
62.5
LORA_BW_41
41.67
167
LORA_BW_31
31.25
250
LORA_BW_20
20.83
167
LORA_BW_15
15.63
250
LORA_BW_10
10.42
167
LORA_BW_7
7.81
250
4.4
Sub-GHz radio clocks
4.4.1
Internal oscillators
250
The following sub-GHz radio dedicated internal RC oscillators are available:
•
•
64 kHz RC oscillator
–
optionally used during the sub-GHz radio Sleep mode to wake up the transceiver
when performing periodic or duty cycled operations
–
used by the sub-GHz radio RTC for time based events
13 MHz RC oscillator, enabled for all sub-GHz radio SPI communication
The frequency of each sub-GHz radio internal oscillators is calibrated using the HSE32
clock at every sub-GHz radio transition from Deep-Sleep or Sleep-to-Standby, and after a
sub-GHz radio reset. The calibration can also be done on demand by the command
Calibrate().
4.4.2
HSE32 reference clock
The high-precision 32 MHz frequency needed for the sub-GHz radio transmission and
reception is taken from HSE32. The HSE32 clock can also be used by the MCU. The use of
an external crystal (XTAL) or a temperature compensated crystal oscillator (TCXO) are
supported. The used clock source is configured in the RCC (see Section 6.2.1: HSE32 clock
with trimming for more details).
When using the HSE32 with a XTAL, the load capacitors are provided by the integrated
capacitor banks that can be trimmed. The trimming is provided by SUBGHZ_HSEINTRIMR
and SUBGHZ_HSEOUTRIMR registers. The load capacitances on OSC_IN and OSC_OUT
can be trimmed separately. Software trimming must be applied after the sub-GHz radio
entered Standby with HSE32 mode.
The TCXO regulator, integrated in the sub-GHz radio, can be used to supply an external
temperature compensated crystal oscillator (TCXO). The regulated VDDTCXO supply level is
controlled through set_TcxoMode()command.
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The sub-GHz radio, depending on the transmit output power (max + 22 dBm), can heat up
the device. The heating depends on the used transmit output power and the device
package. Careful PCB design using thermal heat dissipation techniques must be applied to
avoid heat transfer to the HSE32 reference clock source. For the HSE32 frequency drift
requirements related to the sub-GHz radio, see Section 4.5.1.
4.5
Sub-GHz radio modems
The following modems are provided enabling the respective modulation and associated
framing.
•
LoRa with the LoRa framing
•
FSK and MSK with a generic framing
•
BPSK with a BPSK framing
The modems and frame types are set by Set_PacketType()command. The current used
modem and frame type can be obtained by Get_PacketType()command.
Once the modem and frame to be used are selected, modulation and packet parameters
can be defined by Set_ModulationParams() and Set_PacketParams() commands.
The LoRa and (G)FSK(a) modems support both transmission and reception.
The (G)MSK and BPSK modems only supports transmission.
The framing determines how the bit stream is translated in packets and how data is stored in
the data buffers. It performs operations such as whitening and CRC handling. The framing is
configured using Set_PacketParams()command.
4.5.1
LoRa modem
The LoRa modem uses spread spectrum modulation and forward error correction
techniques to increase the range and reliability of sub-GHz radio communication. The LoRa
modem provides improved co-channel rejection.
The LoRa modulation can be optimized for a given application by
Set_ModulationParams()command, allowing a trade off between link budget,
interference immunity, spectral occupation and nominal data rate.
The following parameters can be optimized:
•
spreading factor (SF)
•
modulation bandwidth (BW)
•
error coding rate (CR)
•
low data rate optimization (LDRO)
The LoRa symbol rate (Rs) is defined as Rs = BW / 2SF
The transmitted signal is a constant envelope signal. Equivalently, one chip is sent per
second per Hz of bandwidth.
a. The (G)FSK modem can be used for (G)MSK modulation in Tx and Rx when setting the frequency
deviation to a quarter of the bit rate.
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Spreading factor (SF)
The LoRa spread spectrum modulation is performed by representing each data bit of the
packet payload by multiple chips of information. The rate at which the spread information is
sent, is referred to as the symbol rate (Rs). The ratio between the nominal data rate and the
chip rate is the spreading factor (SF). It represents the number of symbols per data bit.
The spreading factor must be known in advance on both transmit and receive side of the
link.
The resulting signal to noise ratio (SNR) required at the receiver input, is influenced by the
spreading factor. This allows the increase of the receiver sensitivity, and so increase the link
budget and range.
A higher spreading factor provides a better receiver sensitivity, more link budget and longer
range at the expense of a longer transmission time (see the table below).
Table 22. Spreading factor, chips/symbol and LoRa SNR
Spreading factor (SF)
5
6(1)
7(2)
8
9
10
11
12
2SF (chips/symbol)
32
64
128
256
512
1024
2048
4096
LoRa demodulator SNR (dB)
- 2.5
-5
-7
- 9.5
- 12
- 14.5
- 17
- 19
1. The SF6 is not backward compatible with earlier LoRa devices.
2. Default value.
For SF5 and SF6, due to the higher symbol rate, the minimum preamble length needed to
ensure correct detection and demodulation of the received signal is 12 symbols.
Bandwidth (BW)
An increase in signal bandwidth allows the use of a higher effective data rate and reduces
the transmission time at the expense of a reduced sensitivity, less link budget and shorter
range. The LoRa modem operates at a programmable bandwidth (BW) around a
programmable RF frequency (frf).
There are country dependent regulatory constraints on the permitted occupied bandwidth.
The LoRa signal bandwidth refers to the double side bandwidth (DSB). The bandwidth
selection range is given in the table below.
Table 23. LoRa bandwidth setting
LoRa BW setting
0
8
1
9
2
10
3
4
5(1)
6(1)
Bandwidth (kHz)
7.81
10.42
15.63
20.83
31.25
41.67
62.5
125
250
500
1. Bandwidth not available below a 400 MHz RF frequency.
Forward error correction coding rate (CR)
The sub-GHz radio communication reliability can be improved by performing forward error
correction. This is particularly efficient in the presence of interference. The coding rate can
be changed in response to channel condition. The coding rate information is included in the
packet header for use by the receiver.
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A higher coding rate provides better immunity to interference at the expense of longer
transmission time. In normal conditions and factor of 4 / 5 provides the best trade off. In
case of strong interference, a higher coding rate may be used.
The coding rate and overhead ratio is given in the table below.
Table 24. Coding rate and overhead ratio
0(1)
1
2(2)
3
4
Coding rate (data bits/total coded bits)
4/4
4/5
4/6
4/7
4/8
Overhead ratio
1
1.25
1.5
1.75
2
CR setting
1. No forward error correction.
2. Default value.
Low data rate optimization (LDRO)
For low data rates (typically high SF or low BW) and very long payloads (may last several
seconds), the low data rate optimization (LDRO) can be enabled. This reduces the number
of bits per symbol to the given SF minus 2, to allow the receiver to have a better tracking of
the LoRa receive signal. Depending on the payload length, the low data rate optimization is
usually recommended when the LoRa symbol time is equal or above 16.38 ms.
When using LoRa modulation, the total frequency drift over the packet time must be kept
lower than Freq_drift_max:
Freq_drift_max = BW / (3 x 2SF)
When possible, enabling the low data rate optimization (Set_ModulationParams()
command), relaxes the total frequency drift over the packet time by 16:
Freq_drift_optimise_max = 16 x Freq_drift_max
4.5.2
LoRa framing
The following types of LoRa packet formats are available:
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explicit header mode packet: includes a short header that contains information about
the number of payload bytes, coding rate and presence of CRC.
•
implicit header mode packet (no header)
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The LoRa packet frames are illustrated in Figure 8.
Figure 8. LoRa packet frames format
Explicit packet frame
n preamble symbols
n header symbols
Preamble
Header + CRC
CR = 4/8
Payload
CRC
CR defined by coding rate
SF defined by spreading factor
Implicit packet frame
n preamble symbols
Preamble
Payload
CRC
CR defined by coding rate
SF defined by spreading factor
MSv62618V1
The LoRa packet frames start with a preamble that is used to synchronize the receiver with
the received signal. By default, the packet is configured with a 12-symbol-long preamble
sequence. The preamble length is programmable by Set_PacketParams() command.
This allows the transmission of near arbitrarily long preamble sequences.
The receiver undertakes a preamble detection process that periodically restarts. For this
reason, the preamble length at receiving side must be configured identical to the one at
transmitting side. When the preamble length is not known at receiving side or when it varies,
the maximum preamble length must be programmed at receiving side.
In the explicit packet format, the preamble is followed by a header with CRC, then followed
by the payload and payload CRC.
In the implicit packet format, the preamble is directly followed by the payload and payload
CRC.
The payload is a variable length field that contains the user data coded at the coding rate,
either as specified in the explicit header or in the sub-GHz configuration when using implicit
mode, by Set_PacketParams() and Set_ModulationParams() commands.
The payload can be followed by an optional payload CRC.
Explicit header mode
The default operation mode is the explicit header mode, where the header provides
information on the payload. The header is transmitted using maximum forward error
correction coding rate 4/8. It is protected by its own header CRC to allow the receiver to
discard a packet up on receiving an invalid header.
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Implicit header mode
In certain operation modes where the payload coding rate and CRC presence are fixed or
known in advance, it can be advantageous to reduce transmission time by invoking implicit
header mode. In this mode, the header is not present in the packet frame. The payload
length, forward error correction coding rate and presence of the payload CRC must be
configured on both sides of the sub-GHz radio link.
LoRa time-on-air
The total transmission time of packet can be calculated as follows:
TotalTimeOnAir = (PreambleSymbols + NbSymbolPayload + 4.25 + 8) x (2SF/ BW)
where PreambleSymbols is the number of preamble symbols programmed in
Set_PacketParams(PbLength).
The number of payload symbols can be calculated as follows:
NbSymbolPayload = CEILING(NbSymbolPayloadFrac,4 + CR)
where CEILING is the function that rounds up to the integer multiple of (4 + CR) immediately
superior to the fractional first parameter.
The number of payload fractional symbols in Explicit mode can be calculated as follows:
NbSymbolPayloadFrac = ((PL x 8 + CRC x 16 - 4 x (SF - 7)) x (4 + CR)) / (4 x SF)
The number of payload fractional symbols in Implicit mode can be calculated as follows:
NbSymbolPayloadFrac = ((PL x 8 + CRC x 16 - 4 x (SF - 2)) x (4 + CR)) / (4 x SF)
where:
•
CRC = 0 (no CRC) or 1 (16-bit CRC)
•
CR = 0 to 4
•
PL = 1 to 255, user data payload length in number of bytes
•
SF = 7 to 12 spreading factor
LoRa data rates “raw data rate” and “real data rate” are defined as:
RawBitRate = ((SF x BW) / 2SF) x (4 / (4 + CR))
RealBitRate = (PayloadLength x 8) / TotalTimeOnAir
Channel activity detection (CAD)
The channel activity detection is used to detect the presence of a LoRa signal, by detecting
a LoRa preamble or data symbols.
Once in channel activity detection mode, the band is scanned for a determined duration as
set in Set_CadParams() command. If LoRa symbols are detected during this period, the
channel activity detected IRQ is set.
The time needed to perform the channel activity detection depend on the LoRa modulation
settings. For a given SF / BW, the typical CAD detection time can be selected to be 1, 2, 4,
8, or 16 symbols. The CAD duration time is further more extended with half a symbol.
4.5.3
FSK modem
The FSK modem provides a 2-FSK modulation over a range of data rates from 0.6 Kbit/s up
to 300 Kbit/s. In receive mode, the bandwidth is automatically adjusted to match the
selected data rate. In transmit mode, the frequency deviation is selected via the modulation
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index. An optional Gaussian filter can be used. All modulation parameters are set using
Set_ModulationParams() command.
The bit rate (or equivalent chip) is referenced to the HSE32 frequency and controlled by the
BR parameter, defined as follows:
BR = 32 x HSE32FREQ / BitRate where HSE32FREQ = 32 MHz
FSK modulation is performed inside the RF-PLL bandwidth, by changing the fractional
divider. The high resolution of the RF-PLL allows very narrow frequency deviation. The
frequency deviation parameter Fdev, is one of the parameters in
Set_ModulationParams(). Fdev is defined as follows:
Fdev= Fdev[Hz] / FreqStep where FreqStep = HSE32FREQ / 225
To ensure correct modulation, the following limit applies: (Fdev + BR/2) < BW.
The bandwidth must be chosen so that:
BW[DSB] > BR + 2 x frequency deviation + frequency error
where frequency error = 2 x HSE32FREQ error
The FSK modem offers several pulse shape options in the PulseShape parameter.
4.5.4
MSK modem
The MSK modem provides a 2-MSK modulation over a range of data rates from 0.1 Kbit/s
up to 10 Kbit/s. This MSK modulation is only available in transmit mode. The modulation
index is automatically adjusted to 0.5. An optional Gaussian filter can be used. All
modulation parameters are set using Set_ModulationParams() command.
The bit rate (or equivalent chip) is referenced to the HSE32 frequency and controlled by the
BR parameter, defined as follows:
BR = HSE32FREQ / BitRate where HSE32FREQ = 32 MHz
4.5.5
Generic framing
The generic packet framing is used with the FSK and MSK modems.
The generic packet provides a conventional packet format for applications in proprietary
NRZ coded, long range, low-energy communication links. The generic packet framing can
be configured by Set_PacketParams() command and allows whitening based on pseudo
random number generation, CRC operations and packet acknowledgment.
The following types of generic packet formats are available:
•
Variable length packet: including a short header (named length) that contains
information about the number of payload bytes
•
Fixed length packet: no header
In both packet formats, the payload length is limited to 254 when the address filtering is
activated.
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The generic packet frames are illustrated in Figure 9.
Figure 9. Generic packet frames format
Variable length generic packet frame
Preamble
Syncword
Length Address
0 to 1 byte
0 to 8 bytes
Payload
CRC
0 to 2 bytes
0 to 255 bytes
CRC check
Whitening
Fixed length generic packet frame
Syncword
8 to 65535 bits
0 to 8 bytes
Address
Payload
0 to 1 byte
0 to 255 bytes
CRC
0 to 2 bytes
CRC check
Whitening
MSv62620V4
Preamble
1. The payload length can be extended beyond 255 bytes. Refer to Section 4.6: Sub-GHz radio data buffer
for more details.
The generic packet frames start with a preamble that is used to synchronize the receiver
with the received signal. The preamble length is programmable by Set_PacketParams()
command.
The receiver undertakes a preamble detection process that periodically restarts. For this
reason, the preamble length at the receiving side must be configured identical to the one of
the transmitting side. When the preamble length is not known at receiving side or when it
can vary, the maximum preamble length must be programmed at receiving side.
The preamble is followed by a syncword field with programmable length in
Set_PacketParams() command.
The address is optional and can be used for a unicast when several devices share the same
syncword.
In the variable length generic packet format, the syncword is followed by the length of the
payload (If the Address field is present then Length must include this additional byte),
followed by the payload and payload CRC.
In the fixed length generic packet format, the syncword is directly followed by the payload
and payload CRC.
The payload is a variable length field that contains the user data either as specified in the
variable length generic packet or in the sub-GHz radio configuration when using fixed length
generic packet by Set_PacketParams().
The payload can be followed by an optional payload CRC with programmable length in
Set_PacketParams() command.
Endianness of the frame is MSB first.
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Variable length generic packet mode
When the packet is of uncertain or variable length, the information on the payload length
must be transmitted within the packet. For this, a header with the payload length information
is transmitted after the syncword.
Fixed length generic packet mode
In certain operation modes where the payload length is fixed or known in advance, it may be
advantageous to reduce transmission time by invoking fixed length generic packet mode. In
this mode, the header is not present in the packet frame and the payload length must be
configured on both sides of the sub-GHz radio link.
Node or broadcast address
The node or broadcast address are not considered part of the payload. They are added
automatically when enabled by Set_PacketParams() command. Adding these fields
allows the user to perform additional packet filtering at the header level.
Whitening
Whitening is based on a 9-bit LFSR and used to whiten the payload and, when present, the
header and CRC. Whitening limits a sequence of consecutive 1 or 0 bit to nine. The
whitening polynomial is x9 + x5 + 1, and can be initialized with the whitening initial value in
WHITEINI[8:0].
CRC
CRC computation can be configured for polynomial and initial value, and allows inversion.
Configuration is done through Set_PacketParams() command.
The flexible CRC configuration allows any standard CRC or proprietary CRC to be
generated and checked, for example:
•
•
4.5.6
IBM CRC configuration
–
CRC polynomial 0x8005
–
CRC initial value 0xFFFF
–
2-byte length CRC
CCIT CRC configuration
–
CRC polynomial 0x1021
–
CRC initial value 0x1D0F
–
2-byte length inverted CRC
BPSK modem
The BPSK modem provides a BPSK modulation for data rates of 100 and 600 bit/s. BPSK
modulation is only available in transmit mode. The modulation offers a raise-cosine pulse
shape filter with a BT of 0.5. The BPSK modulator can be changed into DBPSK modulation
by some host pre-processing on the data to be transmitted.
All modulation parameters are set by Set_ModulationParams() command.
The bit rate (or equivalent chip) is controlled by Br parameter, defined as follows:
Br = HSE32FREQ / BitRate where HSE32FREQ = 32 MHz.
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BPSK framing
The BPSK packet framing is used with the BPSK modem. The BPSK packet framing can be
configured by Set_PacketParams() command and allows the total frame length
definition. The full packet (preamble, synch word, device id to CRC) must be provided in the
transmit data buffer.
4.6
Sub-GHz radio data buffer
The sub-GHz radio uses a 256-byte RAM data buffer that is accessible by the CPU through
the SUBGHZSPI interface in all sub-GHz radio operating modes except Sleep and
Deep-Sleep. The RAM data buffer is cleared in Deep-Sleep mode, optionally retained in
Sleep mode and always retained in all other modes. In Sleep and Deep-Sleep modes, the
TxBaseAddr and RxBaseAddr values are lost. In order to retrieve data after Sleep mode
retention, the default values must be used (TxBaseAddr = 0x80 and RxBaseAddr = 0x00),
or RxPayloadLength and RxBufferPointer must be stored in the CPU memory.
On die revision Y and later, the PayloadLength can be updated during transmission. This
capability allows the support of long packets.
On previous die revisions, the PayloadLength is fixed (latched in the radio) after a SetTx()
command.
The RAM data buffers are fully configurable. They allow access to the transmit data buffer
and the last receive data buffer. The RAM data buffer organization is depicted in the figure
below.
Figure 10. Sub-GHz RAM data buffer operation
CPU side
Sub-GHz radio side
address 0xFF
RAM data
buffer
TxBaseAddr + RTxPayloadLength
TxBufferPointer
Transmit
data buffer
Write_Buffer()
TxBaseAddr
Receive
data buffer
Last received
payload
Read_Buffer()
RxBufferPointer + RTxPayloadLength
RxBufferPointer
RxBaseAddr
address 0x00
MSv62621V3
The RAM data buffer is accessed by Write_Buffer() and Read_Buffer()commands.
The offset parameter defines the address in the SRAM data buffer. To read the first byte
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from the receive data buffer, the offset must be set to the RxBufferPointer value. To write to
the first byte in the transmit data buffer, the offset must be set to the TxBaseAddr value.
The RAM data buffer has a circular nature: any address increment exceeding 0xFF wraps
around to address 0x00.
4.6.1
Receive data buffer operation
In receive mode, RxBaseAddr, configured through Set_BufferBaseAddress(),
determines the receive buffer offset in the sub-GHz radio RAM. RxBaseAddr can be set
anywhere within the RAM data buffer. If needed, the whole 256-byte RAM data buffer can
be used.
For the first received packet, RxBufferPointer is set to RxBaseAddr. The first byte of the first
received packet payload data is written at the RxBufferPointer address. The last byte of the
received packet payload data is written at the address determined by RxBufferPointer +
RxPayloadLength. RxBufferPointer and RxPayloadLength can be read by
Get_RxBufferStatus() command.
In single receive and listening modes, RxBufferPointer is automatically initialized to
RxBaseAddr for each new reception when the sub-GHz radio enters RX mode.
In continuous receive mode, RxBufferPointer is continuously incremented from the position
at which it was left by the previous received packet. In this mode, subsequent received
packets are stored continuous in the RAM data buffer.
Caution:
If the amount of received data exceeds the defined receive buffer size, other data in the
RAM are overwritten.
Receive data are written to the receive data buffer regardless of the received CRC status.
When the received CRC fails, post processing on the incorrectly received data can still be
performed by the CPU.
Caution:
When the received packet length exceeds the area allocated to the receive data buffer, it
may overwrite the transmit data buffer area in the RAM data buffer.
4.6.2
Transmit data buffer operation
In transmit mode, TxBaseAddr determines the transmit buffer offset in the sub-GHz radio
RAM. For each transmission, when the sub-GHz radio enters TX mode, TxBufferPointer is
automatically initialized to TxBaseAddr. Each time a payload byte is transmitted,
TxBufferPointer is incremented until all bytes, according the PayloadLength set by the
Set_PacketParams() command, are transmitted.
4.7
Sub-GHz radio operating modes
After a sub-GHz radio reset, a startup phase is initiated. As BUSY is active during this
phase, commands cannot be accepted. When supply and clock are available to the subGHz radio, BUSY is deactivated and the CPU can take control.
The sub-GHz radio provides the following operating modes:
•
Sleep mode
–
Deep-Sleep: all sub-GHz radio clocks are turned off and data memory is lost
–
RC 13 MHz clock turned off
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•
•
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–
RC 64 kHz and timers can be kept running (optional)
–
Optional registers and data memory retained
Calibration mode
–
intermediate mode between Deep-Sleep or Sleep, and Standby
–
used to calibrate the sub-GHz radio RC 64 kHz, sub-GHz radio RC 13 MHz, RFPLL, RF-ADC and image
Standby mode
–
sub-GHz radio clocked by its internal RC 13 MHz clock
–
HSE32 clock can be kept running (optional)
–
data memory retained
Active mode (FS, TX, RX)
–
Frequency synthesis (FS) mode: RF-PLL switched on
–
Transmit (TX) mode: the power amplifier (PA) ramped and data transmitted from
the data buffer according the selected modulation scheme
–
Receive (RX) mode: sub-GHz radio looking for incoming data packets
The sub-GHz radio operating modes are shown in the figure below.
Figure 11. Sub-GHz radio operating modes
POR and reset
Startup
Set_Sleep()
Sleep
NSS or RF-RTC (cold)
Calibration
Calibration done
NSS or RF-RTC (warm)
Standby
RxTimeout,
RxDone,
Set_Standby()
Set_Standby()
TxTimeout,
TxDone
Set_Fs()
Set_Rx()
Set_Tx()
Set_Fs()
Set_Tx()
FS
Set_Fs()
Set_Rx()
Set_Rx()
Set_Tx()
RX
TX
Set_Rx()
Set_Tx()
Active
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4.7.1
Sub-GHz radio (SUBGHZ)
Startup mode
At POR or after a sub-GHz radio reset, the Startup mode is entered. BUSY is set. When
internal supply and clocks become available, the sub-GHz radio enters Sleep mode.
4.7.2
Sleep mode
In Sleep mode, only the sub-GHz radio startup and Sleep control is operational and the
configuration is lost. BUSY is set. Optionally, configuration registers and memories may be
kept in retention. The RC 64 kHz and sub-GHz RTC may be kept running.
The Sleep mode provides the following sub-mode and options:
•
Deep-Sleep mode: all sub-GHz radio function off, controlled by set_Sleep()
command
•
Sleep with the sub-GHz radio RC 64 kHz kept on: configuration registers can be
retained as configured by Set_Sleep() command
•
Sleep with the data RAM retained, controlled by Set_Sleep() command
Following a POR sub-GHz radio reset, the Deep-Sleep mode is entered from Startup mode.
Sleep mode can be entered from Standby mode by Set_Sleep() command.
Caution:
After Set_Sleep() command, the sub-GHz radio cannot receive any SPI commands. The
user must guarantee that the sub-GHz radio SPI NSS is not set low during 500 μs.
Exit Sleep mode can be done:
•
on a firmware request via the sub-GHz radio SPI NSS signal (keeping sub-GHz radio
SPI NSS low for at least 20 μs)
•
on a request from the sub-GHz radio RTC timer generating an end-of-count event
(corresponding to duty cycled operation)
When the sub-GHz radio configuration registers are retained, a warm start is performed
when exiting Sleep mode. During a warm start, the configuration registers are restored with
their retained value an the Calibration state is skipped.
4.7.3
Calibration mode
On a cold start, when transitioning from Deep-Sleep or Sleep mode to Standby mode, the
intermediate Calibration mode is entered. In Calibration mode, BUSY is set to indicate that
the sub-GHz radio is busy and cannot accept any SPI command.
The calibration phase consists of the following operations:
•
sub-GHz radio RC 64 kHz frequency calibration
•
sub-GHz radio RC 13 MHz frequency calibration
•
RF-PLL modulation path calibration
•
RF-ADC calibration
•
image calibration
The total calibration time is 1.6 ms. All calibration results are stored in data RAM.
When the data RAM is retained in Sleep mode, the sub-GHz radio retrieves the calibration
data and then transitions to Standby mode without repeating the calibration phase.
Once the calibration is finished, BUSY is deactivated and the sub-GHz radio enters Standby
with RC 13 MHz mode.
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When in Standby mode, the calibration of different blocks can be requested by
Calibrate() command.
Image calibration for specific frequency bands
The image calibration is performed as part of the calibration process, by default in the band
902 - 928 MHz. The image calibration can furthermore be requested in any band by
CalibrateImage() command.
Image calibration must be redone when the RF frequency is changed significantly and when
the temperature changes more than 20 °C.
4.7.4
Standby mode
The Standby mode is entered from the Calibration mode and can furthermore be entered by
Set_Standby() command.
In Standby mode, BUSY is cleared. The software must configure the sub-GHz radio for FS,
TX, RX or Sleep mode. By default, in Standby mode, the sub-GHz radio is clocked by the
sub-GHz RC 13 MHz. For time critical applications, HSE32 can be turned on. The use of RC
13 MHz or HSE32 is selected by Set_Standby() command.
If the SMPS is used during the sub-GHz transmission or reception, SMPS must be enabled
in the Standby with RC 13 MHz mode. The SMPS is selected by Set_RegulatorMode()
command. When selected, the SMPS is enabled automatically when entering the Standby
with HSE32 mode. If the SMPS has been enabled by the CPU with PWR_CR5.SMPSEN,
the SMPS remains enabled in all sub-GHz radio operating modes including transmission
and reception.
4.7.5
Frequency synthesis mode (FS)
When entering FS mode, BUSY is set. In FS mode, the RF-PLL is activated. Once RF-PLL
is locked, BUSY goes low. The sub-GHz radio may be requested to enter this mode by
Set_Fs().
Due to the low-IF architecture, the transmit and receive RF-PLL frequencies are different.
The receive RF-PLL frequency is equal to the transmit frequency minus the intermediate
frequency offset.
4.7.6
Transmit mode (TX)
The TX mode can be requested to be entered from Standby mode. In this case, the subGHz radio enters first FS mode to lock the RF-PLL, and subsequently TX mode.
In TX mode after ramping-up the power amplifier (PA), data from the data buffer is
transmitted. The sub-GHz radio operates in one of the following transmit modes:
•
single transmit mode
•
single transmit with timeout mode: timeout used as safety, when the transmit is aborted
or does not succeed. The timeout informs the software of such events.
The sub-GHz radio returns automatically to Standby mode after the last data bit of the
packet is transmitted or after the timeout expires.
TX mode entry is requested by Set_Tx() command.
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When entering TX mode, BUSY is set. In TX mode, BUSY is cleared when the PA ramped
up and preamble transmission starts.
PA ramping
The PA ramping time can be selected while setting the output power, by Set_TxParams().
4.7.7
Receive mode (RX)
The RX mode can be requested to be entered from Standby mode. In this case, the subGHz radio enters first FS mode to lock the RF-PLL, and subsequently RX mode.
In RX mode, LNA, RF-PLL and selected modem are enabled. The receive mode provides
the following operating modes:
•
Continuous mode: The sub-GHz radio remains in RX mode and waits for incoming
packets reception until the software terminates RX mode.
•
Single mode: The sub-GHz radio remains in RX mode until a packet reception and
enters automatically Standby mode after.
•
Single with timeout mode: The sub-GHz radio remains in RX mode until a packet
reception or until the timeout expires, and enters automatically Standby mode after.
•
Listening mode: The sub-GHz radio repeatedly switches between RX single with
timeout mode and Sleep mode, until an IRQ is triggered.
RX mode entry is requested by Set_Rx() command.
When entering RX mode, BUSY is set. In RX mode, BUSY is cleared when the receiver is
ready to receive data.
The receiver provides a power-saving mode at the expense of reduced sensitivity. The
receiver power-saving mode is controlled by the SUBGHZ_RXGAINR register.
4.7.8
Active mode switching time
At each transaction with the sub-GHz radio (register read/write operation or mode
switching), BUSY is set during the transaction and while the sub-GHz radio is processing
the command. BUSY is cleared once the command processing is finished or reached a
stable operating mode, and the sub-GHz radio is ready to receive a new command.
All write commands activate BUSY. For read commands, BUSY remains low.
Switching time (tSWMODE) is defined as the time to process the command or reach a stable
operating mode, starting from the sub-GHz radio SPI NSS rising edge, ending the SPI
command transaction, until BUSY goes inactive. There is a small delay (tSW) between the
sub-GHz radio SPI NSS rising edge, ending the SPI command transaction, and when BUSY
is set. The maximum time for tSW is 600 ns.
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BUSY timing is shown in the figure below.
Figure 12. Sub-GHz radio BUSY timing
BUSY
NSS
SPI
Opcode
Param 1
Param n
Write command
tSW
tSWMODE
MSv64330V1
For the different mode transitions, typical busy timing values are given in the table below.
Table 25. Operation mode transition BUSY switching time
Mode transition
SPI command (sub-GHz radio event)
tSWMODE
typical (μs)
Sleep-to-Standby (no data retention)
SPI NSS low 20 μs
3500
Sleep-to-Standby (with data
retention)
SPI NSS low 20 μs (RTC end-of-count)
340
Standby-to-Standby with HSE32
Set_Standby()
31
Standby (HSE32 off)-to-FS
Set_Fs()
50
Standby (HSE32 off)-to-TX(2)
all Set_Tx()
126
Standby (HSE32 off)-to-RX(3)
Set_Rx(), Set_Cad()
83
Standby (HSE32 on)-to-FS(1)
Set_Fs()
40
Standby (HSE32 on)-to-TX(2)
all Set_Tx()
105
Set_Rx(), Set_Cad()
62
FS-to-TX
all Set_Tx()
76
FS-to-RX(3)
Set_Rx(), Set_Cad()
41
(1)
Standby (HSE32 on)-to-RX
(3)
(2)
1. When entering FS mode, BUSY is cleared to 0 when RF-PLL is locked.
2. When entering TX mode, BUSY is cleared to 0 when the PA ramps up and the transmission of
preamble starts.
3. When entering RX mode, BUSY is cleared to 0 when the receiver is ready to receive data.
4.8
Sub-GHz radio SPI interface
The sub-GHz radio SPI slave interface gives access to the sub-GHz radio configuration,
registers and buffer memory, through SPI commands. It is connected to the SUBGHZSPI
master interface peripheral on the CPU bus matrix.
For a write access, an opcode byte is sent followed by sending the command parameter
bytes.
For a read access, an opcode byte is sent followed by receiving data bytes.
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For each access, the sub-GHz radio SPI NSS goes low at the start of the transfer and is set
high at the end, after all bytes have been transfered.
The following transaction types are supported:
•
configuration transaction: provides the CPU with a direct access to control registers.
Used to write or read sub-GHz radio configuration registers or buffer memory.
•
command transaction: requires more complex, non-atomic operations such as packet
transmission and reception or operating mode changes
BUSY is used to indicate the status of the sub-GHz radio and its ability (or not) to receive a
SPI transaction. Prior to issuing a new SPI transaction, the CPU must check the BUSY
status to make sure a new transaction can be received by the sub-GHz radio.
4.8.1
Sub-GHz radio command structure
The SPI command structure consists of an opcode and parameters when writing data to the
sub-GHz radio, and consists of a status when reading data.
In case of a write command that does not require any parameters, the CPU sent only an
opcode over the sub-GHz radio SPI interface.
In case of a write command that requires parameters, the opcode is followed immediately by
the parameter bytes. All parameters must be sent before the sub-GHz radio SPI NSS rising
edge, that terminates the command.
In case of a read command, the opcode is followed immediately by the status bytes. All
status must be received before the sub-GHz radio SPI NSS rising edge, that terminates the
command.
Command structure values are given in the table below.
Table 26. Command structure
Command type
4.8.2
Byte 0
Byte 1:n
Write command without parameter
Opcode
Not applicable
Write command with parameters
Opcode
Parameters
Read command
Opcode
data
Register and buffer access commands
Write_Register() command
Write_Register(Addr, Data0, Data1, to Datan) allows a block of bytes to be
written in a contiguous memory area, starting from the specified address. The address is
auto incremented after each byte.
0
1
Opcode
w
byte 0
bytes 2:1
2
Addr[15:0]
w
w
3
...
n+3
Data0[7:0]
...
Datan[7:0]
w
w
w
bits 7:0 Opcode: 0x0D
bits 15:0 Addr[15:0]: first write address
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byte 3
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bits 7:0 Data0[7:0]: data to write to first address
...
byte n+3
...
bits 7:0 Datan[7:0]: data to write to address + n (n = number of bytes to write)
Read_Register() command
Read_Register(Addr, Status, Data0, Data1, to Datan) allows a block of
bytes to be read in a contiguous memory area starting from the specified address. The
address is auto incremented after each byte.
0
1
2
Opcode
Addr]15:0]
w
w
byte 0
bytes 2:1
w
3
4
...
n+4
Status[7:0]
Data0[7:0]
...
Datan[7:0]
r
r
r
r
bits 7:0 Opcode: 0x1D
bits 15:0 Addr[15:0]: first read address
byte 3
bits 7:0 Status[7:0]: see Get_Status() command
byte 4
bits 7:0 Data0[7:0]: data read from first address
...
byte n+4
...
bits 7:0 Datan[7:0]: data read from address + n (n = number of bytes to read)
Write_Buffer() command
Write_Buffer(Offset, Data0, Data1, to Datan) allows transmit packet payload
data to be written to a contiguous data memory area, starting from the specified offset. The
offset is auto incremented after each byte. When the offset exceeds the value 255, it is
wrapped around to 0 (providing a 256-byte circular buffer).
0
1
2
...
n+2
Opcode
Offset[7:0]
Data0[7:0]
...
Datan[7:0]
w
w
w
w
w
byte 0
bits 7:0 Opcode: 0x0E
byte 1
bits 7:0 Offset[7:0]: first write address offset
byte 2
bits 7:0 Data0[7:0]: data to write to offset address
...
byte n+2
...
bits 7:0 Datan[7:0]: data to write to offset address + n (n = number of bytes to write)
Read_Buffer() command
Read_Buffer(Offset, Status, Data0, Data1, to Datan) allows receive packet
payload data to be read from a contiguous data memory area, starting from the specified
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offset. The offset is auto incremented after each byte. When the offset exceeds the value
255, it is wrapped around to 0 (providing a 256 byte circular buffer).
0
1
2
3
...
n+3
Opcode
Offset[7:0]
Status[7:0]
Data0[7:0]
...
Datan[7:0]
w
w
r
r
r
r
byte 0
bits 7:0 Opcode: 0x1E
byte 1
bits 7:0 Offset[7:0]: first read address offset
byte 2
bits 7:0 Status[7:0]: see Get_Status() command
byte 3
bits 7:0 Data0[7:0]: data read from offset address
...
byte n+3
4.8.3
...
bits 7:0 Datan[7:0]: data read from offset address + n (n = number of bytes to read)
Operating mode commands
Set_Sleep() command
Set_Sleep(SleepCfg) is used to set the sub-GHz radio in Sleep mode. This command is
only accepted in Standby mode. The SleepCfg parameter allows some optional functions to
be maintained in Sleep mode.
0
1
Opcode
SleepCfg
w
w
byte 0
bits 7:0 Opcode: 0x84
byte 1
bits 7:3 Reserved, must be kept at reset value.
bit 2 SleepCfg_Start: Sub-GHz radio startup selection
0: cold startup when exiting Sleep mode, configuration registers reset
1: warm startup when exiting Sleep mode, configuration registers kept in
retention
Note: Only the configuration of the activated modem, before going to Sleep
mode, is retained. The configuration of the other modes is lost and must
be re-configured when exiting Sleep mode.
bit 1 Reserved, must be kept at reset value.
bit 0 SleepCfg_RTCEn: Sub-GHz radio RTC wake-up enable
0: Sub-GHz radio RTC wake-up disabled
1: Sub-GHz radio RTC wake-up enabled
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Set_Standby() command
Set_Standby(StandbyCfg) is used to set the sub-GHz radio in Standby mode. The
StandbyCfg parameter allows some optional functions to be selected in Standby mode.
0
1
Opcode
StandbyCfg
w
w
byte 0
bits 7:0 Opcode: 0x80
byte 1
bits 7:1 Reserved, must be kept at reset value.
bit 0 StandbyCfg_StandbyClk: set clock in Standby mode
0: RC 13 MHz used in Standby mode
1: HSE32 used in Standby mode (Standby with HSE32)
Set_Fs() command
Set_Fs() is used to set the sub-GHz radio in FS mode. This command allows the RF-PLL
test.
0
Opcode
w
byte 0
bits 7:0 Opcode: 0xC1
The RF-PLL frequency must be set by Set_RfFrequency() command prior sending
Set_Fs().
Set_Tx() command
Set_Tx(Timeout) is used to set the sub-GHz radio in TX mode.
0
1
Opcode
bytes 3:1
3
Timeout[23:0]
w
byte 0
2
w
w
w
bits 7:0 Opcode: 0x83
bits 23:0 Timeout[23:0]: Transmit packet timeout
0x000000: Timeout disabled
0x000001 - 0xFFFFFF: Timeout enabled, resolution 15.625 μs
Time-out duration is computed as follows:
Time-out duration = Timeout x 15.625 μs (maximum time-out duration = 262.14 s)
When Set_Tx(Timeout) is sent in Standby or Receive mode, the sub-GHz radio passes
through the FS mode (no need to send Set_Fs()). In this case, the RF-PLL frequency
must be set by Set_RfFrequency() prior sending Set_Tx(Timeout).
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Set_Rx() command
Set_Rx(Timeout) is used to set the sub-GHz radio in Receive mode.
0
1
Opcode
w
byte 0
bytes 3:1
2
3
Timeout[23:0]
w
w
w
bits 7:0 Opcode: 0x82
bits 23:0 Timeout[23:0]: Transmit packet timeout
0x000000: timeout disabled
0x000001 - 0xFFFFFE: timeout enabled, single packet receive mode,
resolution 15.625 μs
0xFFFFFF: timeout disabled, continuous receive mode
Time-out duration is computed by the following formula:
Time-out duration = Timeout x 15.625 μs (maximum Time-out duration = 262.14 s)
When Set_Rx(Timeout) is sent in Standby mode or Transmit mode, the sub-GHz radio
passes through the FS mode (no need to send Set_Fs()). In this case, the RF-PLL
frequency must be set by Set_RfFrequency() prior sending Set_Rx(Timeout).
Set_StopRxTimerOnPreamble() command
Set_StopRxTimerOnPreamble(RxTimeoutStop) allows the selection of the receiver
event on which the receiver timeout timer (in Set_Rx()), is stopped.
0
1
Opcode
RxTimeoutStop
w
w
byte 0
bits 7:0 Opcode: 0x9F
byte 1
bits 7:1 Reserved, must be kept at reset value.
bit 0 RxTimeoutStop: receiver timeout timer stop event selection
0: receive timeout stopped on synchronization word detection in generic
packet mode or header detection in LoRa packet mode
1: receive timeout stopped on preamble detection
Caution:
When the receiver timeout is selected to be stopped on preamble detection, the sub-GHz
radio remains in Receive mode until a packet is received. A false preamble detection may
cause the sub-GHz radio to remain in Receive mode for an unexpected long period, until
stopped by a mode configuration command.
Set_RxDutyCycle() command
Set_RxDutyCycle(RxPeriod, SleepPeriod) is used to set the sub-GHz radio
receiver in listening mode, regularly looking for new packets. This command must be sent in
Standby mode. This command is only functional with FSK and LoRa packet type.
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The following steps are performed:
1.
Save sub-GHz radio configuration.
2.
Enter Receive mode and listen for a preamble for the specified RxPeriod period.
3.
Upon the detection of a preamble, the RxPeriod timeout is stopped and restarted with
the value 2 x RxPeriod +SleepPeriod. During this new period, the sub-GHz radio looks
for the detection of a synchronization word when in (G)FSK modulation mode, or a
header when in LoRa modulation mode.
4.
If no packet is received during the listen period defined by 2 x RxPeriod + SleepPeriod,
the Sleep mode is entered for a duration of SleepPeriod. At the end of the receive
period, the sub-GHz radio takes some time to save the context before starting the sleep
period.
5.
After the sleep period, a new listening period is automatically started. The sub-GHz
radio restores the sub-GHz radio configuration and continuous with step 2.
The listening mode is terminated in one of the following cases:
•
if a packet is received during the listening period: the sub-GHz radio issues a RxDone
interrupt and enters Standby mode.
•
if SetStandby() is sent during the listening period or after the sub-GHz has been
requested to exit Sleep mode by sub-GHz radio SPI NSS
0
1
Opcode
w
byte 0
2
3
4
RxPeriod[23:0]
w
w
5
6
SleepPeriod[23:0]
w
w
w
w
bits 7:0 Opcode: 0x94
bytes 3:1
bits 23:0 RxPeriod[23:0]: Receive duration
0x000000: Receiver duration disabled, receiver remaining active until a
packet is detected
0x000001 - 0xFFFFFF: Receive duration, resolution 15.625 μs
bytes 6:4
bits 23:0 SleepPeriod[23:0]: Sleep duration, resolution 15.625 μ
Receive period duration is computed as follows:
Receive period duration = RxPeriod x 15.625 μs (max receiver duration = 262.14 s)
Sleep period duration is computed by the following formula:
Sleep period duration = SleepPeriod x 15.625 us (max sleep duration = 262.14 s)
For correct operation, the following must be respected:
•
(G)FSK modulation: Tpreamble + Tsyncword < 2 x RxPeriod + SleepPeriod
•
LoRa modulation: Tpreamble + Theader < 2 x RxPeriod + SleepPeriod
Figure 13. Receiver listening mode timing
RxPeriod
2 x RxPeriod + SleepPeriod
Sub-GHz radio
mode
Sleep
Standby and SF
RX
Save
context
Sleep
Preamble detection
MSv62623V1
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Set_Cad() command
Set_Cad() is used to detect the channel activity and can only be used with LoRa packet
types. The channel activity detection (CAD) is a specific LoRa operation mode, where the
sub-GHz radio searches for a LoRa radio signal. After the search is completed, the Standby
mode is automatically entered, CAD is done and IRQ is generated. When a LoRa radio
signal is detected, the CAD detected IRQ is also generated.
0
Opcode
w
byte 0
bits 7:0 Opcode: 0xC5
The length of the search must be configured with Set_CadParams() prior sending
Set_Cad().
Set_TxContinuousWave() command
Set_TxContinuousWave() is a test command to generate a continuous transmit tone at
the RF-PLL frequency. The sub-GHz radio remains in continuous transmit tone mode until a
mode configuration command is received.
0
Opcode
w
byte 0
bits 7:0 Opcode: 0xD1
Set_TxContinuousPreamble() command
Set_TxContinuousPreamble() is a test command to generate an infinite preamble at
the RF-PLL frequency.
The preamble is an alternating 0s and 1s sequence in generic (G)FSK and (G)MSK
modulations. The preamble is symbol 0 in LoRa modulation.
The sub-GHz radio remains in infinite preamble mode until a mode configuration command
is received.
0
Opcode
w
byte 0
bits 7:0 Opcode: 0xD2
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4.8.4
RM0461
Sub-GHz radio configuration commands
Set_PacketType() command
Set_PacketType(PktType) allows the selection of packet frame format. This command
must be the first command of a sub-GHz radio configuration sequence.
Changing from one sub-GHz radio configuration to another is done using
Set_PacketType(). The parameters from the previous sub-GHz radio configuration are
lost. The switch from one configuration mode to another is only accepted in Standby mode.
0
1
Opcode
PktType
w
w
byte 0
bits 7:0 Opcode: 0x8A.
byte 1
bits 7:2 Reserved, must be kept at reset value.
bits 1:0 PktType[1:0]: Packet type definition
0: FSK generic packet type
1: LoRa packet type
2: BPSK packet type
3: MSK generic packet type
Other: reserved
Get_PacketType() command
Get_PacketType(Status, PktType) returns information on the selected packet frame
format.
Changing from one sub-GHz radio configuration to another is done using
Set_PacketType(). The parameters from the previous sub-GHz radio configuration are
lost. The switch from one configuration mode to another is only accepted in Standby mode.
0
1
2
Opcode
Status[7:0]
PktType
w
r
r
byte 0
bits 7:0 Opcode: 0x11
byte 1
bits 7:0 Status[7:0]: see Get_Status() command
byte 2
bits 7:2 Reserved, must be kept at reset value.
bits 1:0 PktType[1:0]: Packet type definition
0: FSK generic packet type
1: LoRa packet type
2: BPSK packet type
3: MSK generic packet type
Others: reserved
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Set_RfFrequency() command
Set_RfFrequency(RfFreq) is used to lock the RF-PLL frequency to the transmit and
receive frequency.
0
1
2
Opcode
w
byte 0
bytes 4:1
3
4
w
w
RfFreq[31:0]
w
w
bits 7:0 Opcode: 0x86
bits 31:0 RfFreq[31:0]: RF frequency
RF-PLL frequency = 32e6 x RFfreq / 225
Set_TxParams() command
Set_TxParams(Power, RampTime) is used to set the transmit output power and the PA
ramp-up time.
0
1
2
Opcode
Power[7:0]
RampTime[7:0]
w
w
w
byte 0
bits 7:0 Opcode: 0x8E
byte 1
bits 7:0 Power[7:0]: Output power setting
LP PA selected in Set_PaConfig()
0x0E:+ 14 dB
...
0x00: 0 dB
...
0xEF: - 17 dB
Others: reserved
HP PA selected in Set_PaConfig()
0x16:+ 22 dB
...
0x00: 0 dB
...
0xF7: - 9 dB
Others: reserved
byte 2
bits 7:0 RampTime[7:0]: PA ramp time for FSK, MSK and LoRa modulation
0x00: 10 μs
0x01: 20 μs
0x02; 40 μs
0x03: 80 μs
0x04: 200 μs
0x05: 800 μs
0x06: 1700 μs
0x07: 3400 μs
Others: reserved
Note: In BPSK mode, the ramping time is specific and RampTime[7:0] is not
used.
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Set_PaConfig() command
Set_PaConfig(PaDutyCycle, HpMax, PaSel, 0x01) is used to customize the
maximum output power and PA efficiency.
0
1
2
3
4
Opcode
PaDutyCycle[2:0]
HpMax[2:0]
PaSel
0x01
w
w
w
w
w
byte 0
bits 7:0 Opcode: 0x95
byte 1
bits 7:3 Reserved, must be kept at reset value.
bits 2:0 PaDutyCycle[2:0]: PA duty cycle (conduit angle) control
Duty cycle = 0.2 + 0.04 x PaDutyCycle[2:0] (see Table 27 for settings)
Caution: The following restrictions must be observed to avoid over-stress on
the PA:
- LP PA mode with synthesis frequency >400 MHz, PaDutyCycle
must be < 0x7.
- LP PA mode with synthesis frequency < 400 MHz, PaDutyCycle
must be < 0x4.
- HP PA mode, PaDutyCycle must be < 0x4.
byte 2
bits 2:0 HpMax[2:0]: HP PA output power (see Table 27 for settings)
bits 7:3 Reserved, must be kept at reset value.
byte 3
bits 7:1 Reserved, must be kept at reset value.
bit 0 PaSel: PA selection.
0: HP PA selected
1: LP PA selected (default)
byte 4
bits 7:0 0x01
PA optimal settings given in the table below must be used to maximize the PA efficiency for
the maximum targeted output power. Matching network determination must be done using
these settings (see the application note AN5457 for more details).
Table 27. PA optimal setting and operating modes
Set_PaConfig()
Output power
(dBm)
PA mode
PaDutyCycle
[2:0]
HpMax[2:0]
PaSel
Power
0x7
0x0
1
0x0E
0x4
0x0
1
0x0E
+ 10
0x1
0x0
1
0x0D
+ 22
0x4
0x7
0
0x16
0x3
0x5
0
0x16
0x2
0x3
0
0x16
0x2
0x2
0
0x16
+ 15
+ 14
+ 20
+ 17
+ 14
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LP
HP
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Sub-GHz radio (SUBGHZ)
Set_TxRxFallbackMode() command
Set_TxRxFallbackMode(FallbackMode) defines the operating mode to enter after a
successful packet transmission or packet reception.
0
1
Opcode
FallbackMode[7:0]
w
w
byte 0
bits 7:0 Opcode: 0x93
byte 1
bits 7:0 FallbackMode[7:0]: Fall-back mode after successful packet transmission or
packet reception
0x20: Standby mode entry (default)
0x30: Standby with HSE32 enabled mode entry
0x40: FS mode entry
Others: reserved
Set_CadParams() command
0
1
2
3
4
Opcode
NbCadSymbol[2:0]
CadDetPeak[7:0]
CadDetMin[7:0]
CadExitMode
Set_CadParams(NbCadSymbol,CadDetPeak,CadDetMin,CadExtiMode,Timeout)
allows the CAD configuration for LoRa packet types.
w
w
w
w
w
byte 0
bits 7:0 Opcode: 0x88
byte 1
bits 7:3 Reserved, must be kept at reset value.
5
6
7
Timeout[23:0]
w
w
w
bits 2:0 NbCadSymbol[2:0]: Number of symbols used for CAD scan
0x0: 1 symbol
0x1: 2 symbols
0x2: 4 symbols
0x3: 8 symbols
0x4: 16 symbols
Others: reserved
byte 2
bits 7:0 CadDetPeak[7:0]: Used with CadDetMin[7:0] to correlate the LoRa symbol
See Table 28.
byte 3
bits 7:0 CadDetMin[7:0]: Used with CadDetPeak[7:0] to correlate the LoRa symbol
see Table 28.
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byte 4
RM0461
bits 7:1 Reserved, must be kept at reset value.
Bit 0 CadExitMode: defines the sub-GHz radio operating mode to enter after CAD
scan is finished
0: Standby with RC 13 MHz mode entry after CAD, whatever is detected
during the CAD scan
1: Standby with RC 13 MHz mode after CAD if no LoRa symbol is detected
during the CAD scan
if a LoRa symbol is detected, the sub-GHz radio stays in Receive mode until a
packet is received or until the CAD timeout is reached.
bytes 7:5
bits 23:0 Timeout[23:0]: CAD timeout = Timeout[23:0] x 15.625 μs
The CAD timeout is only used when a symbol is detected and
CadExitMode = 1 (stay in Receive mode after a LoRa symbol detection).
0x000000 - 0xFFFFFF: timeout, resolution 15.625 μs
The correct values selected in the table below must be carefully tested to ensure a good
detection at sensitivity level and to limit the number of false detections.
Table 28. Recommended CAD configuration settings
Spreading factor
cadDetMin
cadDetPeak
cadSymbolNum
22
2 symbols
SF7
SF8
SF9
23
10
SF10
24
SF11
25
SF12
28
4 symbols
Set_BufferBaseAddress() command
Set_BufferBaseAddress(TxBaseAddr, RxBaseAddr) sets the data buffer base
address for the packet handling in TX and RX.
0
1
2
Opcode
TxBaseAddr[7:0]
RxBaseAddr[7:0]
w
w
w
byte 0
bits 7:0 Opcode: 0x8F
byte 1
bits 7:0 TxBaseAddr[7:0]: Tx base address offset relative to the sub-GHz RAM base
address
byte 2
bits 7:0 RxBaseAddr[7:0]: Rx base address offset relative to the sub-GHz RAM base
address
(G)FSK Set_ModulationParams() command
Set_ModulationParams(Br, PulseShape, Bw, Fdev) is used to configure the
(G)FSK modulation parameters for the sub-GHz radio. Depending on the selected packet
138/1290
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Sub-GHz radio (SUBGHZ)
type in Set_PacketType() sent prior to this function, the parameters for generic packets
are interpreted as follows:
Br and Fdev are used for the transmission and reception.
•
Bw is used only for reception.
•
PulseShape represents the Gaussian filter that can be used to filter the modulation
stream at the transmitter.
0
1
Opcode
w
byte 0
bytes 3:1
byte 4
2
3
Br[23:0]
w
w
w
4
5
PulseShape[7:0]
•
Bw[7:0]
w
w
6
7
8
Fdev[23:0]
w
w
w
bits 7:0 Opcode: 0x8B
bits 23:0 Br[23:0]: Bit rate
0x000000: reserved
0x000001 - 0xFFFFFF: Br = 32 x 32 MHz / bit rate
bit 7:0 PulseShape[7:0]: Pulse shape
0x00: no filter applied
0x08:Gaussian BT 0.3
0x09: Gaussian BT 0.5
0x0A: Gaussian BT 0.7
0x0B: Gaussian BT 1.0
Others: no filter applied
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Sub-GHz radio (SUBGHZ)
bytes5
bytes 8:6
RM0461
bit 7:0 Bw[7:0]: Bandwidth
0x1F: BW4 4.8 kHz DSB
0x17: BW5 5.8 kHz DSB
0x0F: BW7 7.3 kHz DSB
0x1E: BW9 9.7 kHz DSB
0x16: BW11 11.7 kHz DSB
0x0E: BW14 14.6 kHz DSB
0x1D: BW19 19.5 kHz DSB
0x15: BW23 23.4 kHz DSB
0x0D: BW29 29.3 kHz DSB
0x1C: BW39 39.0 kHz DSB
0x14: BW46 46.9 kHz DSB
0x0C: BW58 58.6 kHz DSB
0x1B: BW78 78.2 kHz DSB
0x13: BW93 93.8 kHz DSB
0x0B: BW117 117.3 kHz DSB
0x1A: BW156 156.2 kHz DSB
0x12: BW187 187.2 kHz DSB
0x0A: BW234 234.3 kHz DSB
0x19: BW312 312.0 kHz DSB
0x11: BW373 373.6 kHz DSB
0x09: BW467 467.0 kHz DSB
Others: reserved
bit 23:0 Fdev[23:0]: Frequency deviation
0x000000 - 0xFFFFFF: Fdev = Frequency deviation x 225 / 32 MHz
LoRa Set_ModulationParams() command
Set_ModulationParams(Sf, Bw, Cr, Ldro) is used to configure the LoRa
modulation parameters for the sub-GHz radio. Depending on the selected packet type in
Set_PacketType() sent prior to this function, the parameters for LoRa are interpreted as
below.
0
1
2
3
4
Opcode
Sf[3:0]
Bw[7:0]
Cr[2:0]
Ldro
w
w
w
w
w
byte 0
bits 7:0 Opcode: 0x8B
byte 1
bits 7:4 Reserved, must be kept at reset value.
bits 3:0 Sf[3:0]: Spreading factor
0x5: Spreading factor 5
0x6: Spreading factor 6
0x7: Spreading factor 7
0x8: Spreading factor 8
0x9: Spreading factor 9
0xA: Spreading factor 10
0xB: Spreading factor 11
0xC: Spreading factor 12
Others: reserved
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RM0461
Sub-GHz radio (SUBGHZ)
byte 2
bits 7:0 Bw[7:0]: Bandwidth
0x00: bandwidth 7 (7.81 kHz)
0x08: bandwidth 10 (10.42 kHz)
0x01: bandwidth 15 (15.63 kHz)
0x09: bandwidth 20 (20.83 kHz)
0x02: bandwidth 31 (31.25 kHz)
0x0A: bandwidth 41 (41.67 kHz)
0x03: bandwidth 62 (62.50 kHz)
0x04: bandwidth 125 (125 kHz)
0x05: bandwidth 250 (250 kHz)
0x06: bandwidth 500 (500 kHz)
Others: reserved
byte 3
bits 7:3 Reserved, must be kept at reset value.
bits 2:0 Cr[2:0]: Forward error correction coding rate
0x0: no forward error correction coding rate 4/4
0x1: forward error correction coding rate 4/5
0x2: forward error correction coding rate 4/6
0x3:forward error correction coding rate 4/7
0x4: forward error correction coding rate 4/8
Others: reserved
byte 4
bits 7:1 Reserved, must be kept at reset value.
bit 0 Ldro: low data rate optimization enable
0: low data rate optimization disabled
1: low data rate optimization enabled
BPSK Set_ModulationParams() command
Set_ModulationParams(Br, PulseShape) is used to configure the BPSK modulation
parameters for the sub-GHz radio. Depending on the selected packet type in
Set_PacketType() sent prior to this function, the parameters for BPSK packets are
interpreted as follows:
•
For BPSK packet type, the BitRate is used for the transmission.
•
PulseShape represents the Gaussian filter that can be used to filter the modulation
stream at the transmitter.
0
1
2
Opcode
w
byte 0
bytes 3:1
byte 4
3
Br[23:0]
w
w
4
PulseShape[7:0]
w
w
bits 7:0 Opcode: 0x8B
bits 23:0 Br[23:0]: bit rate
0x000000: reserved
0x000001 - 0xFFFFFF: Br = 32 x 32 MHz / bit rate
0x1A0AAA: 600 bit/s
0x9C4000: 100 bit/s
bits 7:0 PulseShape[7:0]: Pulse shape
0x16: Gaussian BT 0.5
Others: reserved
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Sub-GHz radio (SUBGHZ)
RM0461
Generic Set_PacketParams() command
5
6
7
8
9
PktType
Whitening
w
w
w
w
w
w
w
w
w
byte 0
bits 7:0 Opcode: 0x8C.
bytes 2:1
byte 3
w
4
CrcType[2:0]
PbLength[15:0]
3
PayloadLength[7:0]
2
AddrComp[1:0]
Opcode
1
SyncWordLength[6:0]
0
PbDetLength[2:0]
Set_PacketParams(PbLength,PbDetLength,SynchWordLength,AddrComp,
PktType,PayloadLength,CrcType,Whitening) is used to configure the packet
handling for the sub-GHz radio. When the generic packet is selected with packet type in
Set_PacketType() sent prior to this function, the parameters are interpreted as below.
bits 15:0 PbLength[15:0]: Preamble length in number of symbols
0x0000: reserved
0x0001 - 0xFFFF: 1 to 65535 symbols
bits 7:3 Reserved, must be kept at reset value.
bits 2:0 PbDetLength[2:0]: Preamble detection length in number of bit symbols
0x0: preamble detection disabled
0x4: 8-bit preamble detection
0x5: 16-bit preamble detection
0x6: 24-bit preamble detection
0x7: 32-bit preamble detection
Others: reserved
byte 4
bit 7 Reserved, must be kept at reset value.
bits: 6:0 SyncWordLength[6:0]: Synchronization word length in number of bit symbols
0x00 - 0x40: 0 to 64-bit synchronization word (synchronization word data
defined in SUBGHZ_GSYNCR[0:7])
Others: reserved
byte 5
bits 7:2 Reserved, must be kept at reset value.
bits: 1:0 AddrComp[1:0]: Address comparison/filtering
0x0: address comparison/filtering disabled
0x1: address comparison/filtering on node address
0x2: address comparison/filtering on node and broadcast addresses
Others: reserved
byte 6
bits 7:1 Reserved, must be kept at reset value.
bit 0 PktType: Packet type definition
0: Fixed payload length and header field not added to packet
1: Variable payload length and header field added to packet
byte 7
142/1290
bits 7:0 PayloadLength[7:0]: Payload length in number of bytes
0x00- 0xFF: 0 to 255 bytes
RM0461 Rev 10
RM0461
Sub-GHz radio (SUBGHZ)
byte 8
bits 7:3 Reserved, must be kept at reset value.
bits 2:0 CrcType[2:0]: CRC type definition
The CRC initialization value is provided in SUBGHZ_GCRCINIRL and
SUBGHZ_GCRCINIRH. The polynomial is defined in
SUBGHZ_GCRCPOLRL and SUBGHZ_GCRCPOLRH.
0x0: 1-byte CRC
0x1: no CRC
0x2: 2-byte CRC
0x4: 1-byte inverted CRC
0x6: 2-byte inverted CRC
Others: reserved
byte 9
bits 7:1 Reserved, must be kept at reset value.
bit 0 Whitening: Whitening enable
The whitening initial value is provided in WHITEINI[8:0].
0: Whitening disabled
1: Whitening enabled
LoRa Set_PacketParams() command
0
Opcode
w
byte 0
bytes 2:1
byte 3
1
2
PbLength[15:0]
w
w
3
4
5
6
HeaderType
PayloadLength[7:0]
Set_PacketParams(PbLength, HeaderType, PayloadLength, CrcType,
InvertIQ) is used to configure the packet handling for the sub-GHz radio. Depending on
the selected packet type in Set_PacketType() sent prior to this function, the parameters
are interpreted as below.
CrcType
InvertIQ
w
w
w
w
bits 7:0 Opcode: 0x8C.
bits 15:0 PbLength[15:0]: Preamble length in number of symbols
0x0000: reserved
0x0001 - 0xFFFF: 1 to 65535 symbols
bits 7:1 Reserved, must be kept at reset value.
bit 0 HeaderType: Header type definition
0: explicit header for variable length payload
1: implicit header for fixed length payload
byte 4
bits 7:0 PayloadLength[7:0]: Payload length in number of bytes
0x00- 0xFF: 0 to 255 bytes
byte 5
bits 7:1 Reserved, must be kept at reset value.
bit 0 CrcType CRC enable
0: CRC disabled
1: CRC enabled
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Sub-GHz radio (SUBGHZ)
byte 6
RM0461
bits 7:1 Reserved, must be kept at reset value.
bit 0 InvertIQ: IQ setup
0: standard IQ setup
1: inverted IQ setup
BPSK Set_PacketParams() command
Set_PacketParams(PayloadLength) is used to configure the packet handling for the
sub-GHz radio. When the BPSK packet is selected with packet type in
Set_PacketType() sent prior to this function, the parameters are interpreted as below.
0
1
Opcode
PayloadLength[7:0]
w
w
byte 0
bits 7:0 Opcode: 0x8C.
byte 1
bits 7:0 PayloadLength[7:0]: BPSK packet (payload) length, including preamble, synch
word, device id and CRC, in number of bytes
0x00- 0xFF: 0 to 255 bytes
LoRa Set_LoRaSymbTimeout() command
Set_LoRaSymbTimeout(SymbNum) is used to configure the number of LoRa symbols to
be received before starting the reception of a LoRa packet.
Note:
144/1290
0
1
Opcode
SymbNum[7:0]
w
w
byte 0
bits 7:0 Opcode: 0xA0.
byte 1
bits 7:0 SymbNum[7:0]: Number of LoRa symbols before timeout IRQ is generated if
end of preamble has not been detected
0x0: No detection of end of preamble
Others: When setting SymbNum to a value ≠ 0, the modem counts the number
of received chirp after the first LoRa chirp is detected. The modem checks that
the end of preamble is detected before the SymbNum number of LoRa symbol
is obtained after the first chirp is detected. If this is not the case, a timeout
is generated.
In LoRa packet type, when entering the Receive mode and SymbNum[7:0] = 0x0, the
modem locks as soon as a single LoRa symbol is detected. This may lead to a false
detection. To avoid false detections, the number of LoRa symbols to be detected can be
increased.
RM0461 Rev 10
RM0461
4.8.5
Sub-GHz radio (SUBGHZ)
Communication status information commands
Get_Status() command
Get_Status(Status) can be issued at any time.
byte 0
0
1
Opcode
Status[7:0]
w
r
bits 7:0 Opcode: 0xC0
byte 1
bit 7 Reserved, must be kept at reset value.
bits 6:4 Status_Mode[2:0] sub-GHz radio operating mode
0x2: Standby mode with RC 13 MHz
0x3: Standby mode with HSE32
0x4: FS mode
0x5: RX mode
0x6: TX mode
Others: reserved
bits 3:1 Status_CmdStatus[2:0]: Command status
0x2: data available to host (packet received successfully and data can be
retrieved)
0x3:command time out (command took too long to complete triggering a subGHz radio watchdog timeout)
0x4:command processing error (invalid opcode or incorrect number of
parameters)
0x5:command execution failure (command successfully received but cannot
be executed at this time, requested operating mode cannot be entered or
requested data cannot be sent)
0x6: transmit command completed (current packet transmission completed)
Others: reserved
bit 0 Reserved, must be kept at reset value.
Get_RxBufferStatus() command
Get_RxBufferStatus(Status, RxPayloadLength, RxBufferPointer) returns
the sub-GHz radio status, the length of the last received packet (RxPayloadLength) and the
buffer address of the first received payload byte (RxBufferPointer).
0
1
2
3
Opcode
Status[7:0]
RxPayloadLength[7:0]
RxBufferPointer[7:0]
w
r
r
r
byte 0
bits 7:0 Opcode: 0x13.
byte 1
bits 7:0 Status[7:0]: see Get_Status() command.
byte 2
bits 7:0 RxPayloadLenght[7:0]: indicate the number of bytes received in the last
received packet
byte 3
bits 7:0 RxBufferPointer[7:0]: indicates the offset in the RAM data buffer where the first
byte of the last received packet is stored
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Sub-GHz radio (SUBGHZ)
RM0461
(G)FSK Get_PacketStatus() command
Get_PacketStatus(Status, RxStatus, RssiSync, RssiAvg) returns information
on the last received packet. Depending on the selected packet type in Set_PacketType()
sent prior to this function, the parameters for generic packets are interpreted as below.
0
1
2
3
4
Opcode
Status[7:0]
RxStatus[7:0]
RssiSync[7:0]
RssiAvg[7:0]
w
r
r
r
r
byte 0
bits 7:0 Opcode: 0x14
byte 1
bits 7:0 Status[7:0]: see Get_Status() command
byte 2
bit 7 RxStatus_PreambleErr: Set when a preamble error occurred
bit 6 RxStatus_SyncErr: Set when a synchronization error occurred
bit 5 RxStatus_AdrsErr: Set when an address error occurred
bit 4 RxStatus_CrcErr: Set when a crc error occurred
bit 3 RxStatus_LengthErr: Set when a length error occurred
bit 2 RxStatus_AbortErr: Set when an abort error occurred
bit 1 RxStatus_PktReceived: Set when a packet is received
bit 0 RxStatus_PktSent: Set when a packet has been sent
byte 3
bits 7:0 RssiSync[7:0]: RSSI level when the synchronization address is detected
Signal power = -RssiSync / 2 (in dBm)
byte 4
bits 7:0 RssiAvg[7:0]: Average RSSI level over the received packet
Signal power = -RssiAvg / 2 (in dBm)
LoRa Get_PacketStatus() command
Get_PacketStatus(Status, RssiPkt, SnrPkt, SignalRssiPkt) returns
information on the last received packet. Depending on the selected packet type in
Set_PacketType() sent prior to this function, the parameters for LoRa packets are
interpreted as below.
146/1290
0
1
2
3
4
Opcode
Status[7;0]
RssiPkt[7:0]
SnrPkt[7:0]
SignalRssiPkt
w
r
r
r
r
byte 0
bits 7:0 Opcode: 0x14
byte 1
bits 7:0 Status[7:0]: see Get_Status() command
byte 2
bits 7:0 RssiPkt[7:0]: Average RSSI level over the received packet
Signal power = - RssiPkt / 2 (in dBm)
byte 3
bits 7:0 SnrPkt[7:0]: Estimation of SNR over the received packet
SNR = SnrPkt / 4 (in dB)
byte 4
bits 7:0 SignalRssiPkt[7:0]: Estimation of RSSI level of the LoRa signal after
despreading
Signal power = - SignalRssiPkt / 2 (in dBm)
RM0461 Rev 10
RM0461
Sub-GHz radio (SUBGHZ)
Get_RssiInst() command
Get_RssiInst(Status, RssiInst) returns the instantaneous signal strength while in
RX mode.
0
1
2
Opcode
Status[7:0]
RssiInst[7:0]
w
r
r
byte 0
bits 7:0 Opcode: 0x15
byte 1
bits 7:0 Status[7:0]: see Get_Status() command
byte 2
bits 7:0 RssiInst[7:0]: instantaneous RSSI level at the reception time
Signal power = - RssiInst / 2 (in dBm)
(G)FSK Get_Stats() command
Get_Stats(Status, NbPktReceived, NbPktCrcError, NpPktLengthError)
returns statistics information on the last received packet. Depending on the selected packet
type in Set_PacketType() sent prior to this function, the parameters for generic packets
are interpreted as below.
0
1
Opcode
Status[7:0]
w
r
2
3
NbPktReceived[15:0]
r
r
4
5
NbPktCrcError[15:0]
r
byte 0
bits 7:0 Opcode: 0x10
byte 1
bits 7:0 Status[7:0]: see Get_Status() command
r
6
7
NbPktLengthError[15:0]
r
r
bytes 3:2
bits 15:0 NbPktReceived[15:0]: Number of packets received
bytes 5:4
bits 15:0 NbPktCrcError[15:0]: Number of packets received with a payload CRC error
bytes 7:6
bits 15:0 NbPktLengthError[15:0]: Number of packets received with a payload length
error
LoRa Get_Stats() command
Get_Stats(Status, NbPktReceived, NbPktCrcError, NpPktHeaderError)
returns statistics information on the last received packet. Depending on the selected packet
type in Set_PacketType() sent prior to this function, the parameters for LoRa packets
are interpreted as below.
0
1
Opcode
Status[7:0]
w
r
2
3
NbPktReceived[15:0]
r
r
4
5
NbPktCrcError[15:0]
r
byte 0
bits 7:0 Opcode: 0x10
byte 1
bits 7:0 Status[7:0]: see Get_Status() command
r
6
7
NbPktHeaderError[15:0]
r
r
bytes 3:2
bits 15:0 NbPktReceived[15:0]: Number of packets received
bytes 5:4
bits 15:0 NbPktCrcError[15:0]: Number of packets received with a payload CRC error.
RM0461 Rev 10
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Sub-GHz radio (SUBGHZ)
bytes 7:6
RM0461
bits 15:0 NbPktHeaderError[15:0]: Number of packets received with a header CRC
error
Reset_Stats() command
Reset_Stats(0x00,0x00,0x00,0x00,0x00,0x00) resets the received packet
statistics as reported in Get_Stats() (NbPktReceived, NbPktCrcError, NbPktlengthError
and NbPktHeaderError).
4.8.6
0
1
2
3
4
5
6
Opcode
0x00
0x00
0x00
0x00
0x00
0x00
w
w
w
w
w
w
w
byte 0
bits 7:0 Opcode: 0x0
byte 1
bits 7:0 0x0
byte 2
bits 7:0 0x0
byte 3
bits 7:0 0x0
byte 4
bits 7:0 0x0
byte 5
bits 7:0 0x0
byte 6
bits 7:0 0x0
IRQ interrupt commands
There are three IRQ interrupts that can be mapped to several sub-GHz radio interrupt
sources. The source of an interrupt is determined by reading the device status. Interrupts
are cleared using Clr_IrqStatus().
There are 10 possible interrupt sources used depending on the packet type and operating
mode. Each of these interrupt sources can be enabled or masked and mapped on any of the
IRQ interrupts.
A set of commands is used to configure and control the IRQ sources and interrupt
generation
Table 29. IRQ bit mapping and definition
Bit
Source
Description
Packet type
Operation
0
TxDone
Packet transmission finished
LoRa and GFSK
Tx
1
RxDone
Packet reception finished
LoRa and GFSK
Rx
2
PreambleDetected
Preamble detected
LoRa and GFSK
Rx
3
SyncDetected
Synchronization word valid
GFSK
Rx
4
HeaderValid
Header valid
LoRa
Rx
5
HeaderErr
Header CRC error
LoRa
Rx
Err
preamble, syncword, address,
CRC or length error
GFSK
Rx
CrcErr
CRC error
LoRa
Rx
6
148/1290
RM0461 Rev 10
RM0461
Sub-GHz radio (SUBGHZ)
Table 29. IRQ bit mapping and definition (continued)
Bit
Source
Description
Packet type
Operation
7
CadDone
Channel activity detection finished
LoRa
Cad
8
CadDetected
Channel activity detected
LoRa
Cad
9
Timeout
RX or TX timeout
LoRa and GFSK
Rx and Tx
15:10
Not applicable
Reserved
Not applicable
Cfg_DioIrq() command
Cfg_DioIrq(IrqMask, Irq1Mask, Irq2Mask, Irq3Mask) allows interrupts to be
masked and mapped on the IRQ lines.
0
1
Opcode
2
3
4
5
6
7
8
IrqMask[15:0]
Irq1Mask[15:0]
Irq2Mask[15:0]
Irq3Mask[15:0]
w
w
w
w
w
byte 0
bits 7:0 Opcode: 0x08
w
w
w
bytes 2:1
bits 15:0 IrqMask[15:0]: Global interrupt enable
See Table 29 for interrupt bit map definition. For each bit:
0: IRQ disabled
1: IRQ enabled
bytes 4:3
bits 15:0 Irq1Mask[15:0]: IRQ1 line Interrupt enable
0: interrupt on IRQ1 line disable
1: interrupt on IRQ1 line enabled
bytes 6:5
bits 15:0 Irq2Mask[15:0]: IRQ2 line Interrupt enable
0: interrupt on IRQ2 line disable
1: interrupt on IRQ2 line enabled
bytes 8:7
bits 15:0 Irq3Mask[15:0]: IRQ3 line Interrupt enable
0: interrupt on IRQ3 line disable
1: interrupt on IRQ3 line enabled
w
Get_IrqStatus() command
Get_IrqStatus(Status, IrqStatus) returns the IRQ status.
0
1
Opcode
Status[7:0]
w
r
2
IrqStatus[15:0]
r
byte 0
bits 7:0 Opcode: 0x12
byte 1
bits 7:0 Status[7:0]: see Get_Status() command
bytes 3:2
3
r
bits 15:0 IrqStatus[15:0]: interrupt pending status information
See Table 29 for interrupt bit map definition. For each bit:
0: IRQ not pending
1: IRQ pending
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Sub-GHz radio (SUBGHZ)
RM0461
Clr_IrqStatus() command
Clr_IrqStatus(ClrIrq) clears the IRQ status flags (IrqStatus[15:0]).
0
1
Opcode
w
byte 0
bytes 2:1
4.8.7
2
ClrIrq[15:0]
w
w
bits 7:0 Opcode: 0x02
bits 15:0 ClrIrq[15:0]: Clear interrupt status
See Table 29 for interrupt bit map definition. For each bit:
0: no action
1: IRQ pending status flag cleared
Miscellaneous commands
Calibrate() command
Calibrate(CalibCfg) allows one or several blocks to be calibrated at any time when in
Standby mode. The blocks to calibrate are defined by CalibCfg parameter. When the
calibration is ongoing, BUSY is set. A falling edge on BUSY indicates the end of all enabled
calibrations.
byte 0
150/1290
0
1
Opcode
CalibCfg[7:0]
w
w
bits 7:0 Opcode: 0x89
RM0461 Rev 10
RM0461
Sub-GHz radio (SUBGHZ)
byte 1
bit 7 Reserved, must be kept at reset value.
bit 6 CalibCfg_Image: Image calibration
0: Image calibration disabled
1: Image calibration enabled
bit 5 CalibCfg_AdcBulkP: RF-ADC bulk P calibration
0: RF-ADC bulk P calibration disabled
1: RF-ADC bulk P calibration enabled
bit 4 CalibCfg_AdcBulkN: RF-ADC bulk N calibration
0: RF-ADC bulk N calibration disabled
1: RF-ADC bulk N calibration enabled
bit 3 CalibCfg_AdcPulse: RF-ADC pulse calibration
0: RF-ADC pulse calibration disabled
1: RF-ADC pulse calibration enabled
bit 2 CalibCfg_Pll: RF-PLL calibration
0: RF-PLL calibration disabled
1: RF-PLL calibration enabled
bit 1 CalibCfg_RC13M: Sub-GHz radio RC 13 MHz calibration
0: Sub-GHz radio RC 13 MHz calibration disabled
1: Sub-GHz radio RC 13 MHz calibration enabled
bit 0 CalibCfg_RC64K: Sub-GHz radio RC 64 kHz calibration
0: Sub-GHz radio RC 64 kHz calibration disabled
1: Sub-GHz radio RC 64 kHz calibration enabled
CalibrateImage() command
CalibrateImage(CalFreq1, CalFreq2) allows the image to be calibrated at given
frequencies, at any time when in Standby mode. The calibration frequencies are defined by
CalFreq1 and CalFreq2. When the calibration is ongoing, BUSY is set. A falling edge on
BUSY indicates the end of calibration. Once performed, the calibration is valid for all
frequencies between the two selected calibration frequencies. Any ISM band can be
covered by selecting the applicable frequency for CalFreq1 and CalFreq2
Table 30. Image calibration for ISM bands
ISM band [MHz]
CallFreq1
CallFreq2
430 - 440
0x6B
0x6F
470 - 510
0x75
0x81
779 - 787
0xC1
0xC5
863 - 870
0xD7
0xDB
902 - 928
0xE1 (default)
0xE9 (default)
By default, the image calibration is made in the band 902 - 928 MHz. Nevertheless it is
possible to request a new calibration at other frequencies.
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RM0461
0
1
2
Opcode
CalFreq1[7:0]
CalFreq2[7:0]
w
w
w
byte 0
bits 7:0 Opcode: 0x98
byte 1
bits 7:0 CalFreq1[7:0]: Lower frequency of the band to calibrate (see Table 30)
byte 2
bits 7:0 CalFreq2[7:0]: Higher frequency of the band to calibrate (see Table 30)
The calibration frequencies are computed as follows:
Calibrationfreq = CalFreq * 4 MHz where CalFreq1 < CalFreq2
Example: 0x6B = 428 MHz.
When CalFreq1 = CalFreq2, the image calibration is done at a single frequency.
For frequencies between CalFreq1 and CalFreq2, the calibration coefficient is linearly
interpolated from the values obtained during the image calibration at CalFreq1 and
CalFreq2.
For frequencies < CalFreq1, the coefficient obtained during the image calibration at
CalFreq1 is used.
For frequencies > CalFreq2, the coefficient obtained during the image calibration at
CalFreq2 is used.
Set_RegulatorMode() command
Set_RegulatorMode(RegMode) allows the sub-GHz radio supply operation mode
selection, between LDO mode (default) and SMPS mode, when in Standby with HSE32 and
Active modes.
0
1
Opcode
RegMode
w
w
byte 0
bits 7:0 Opcode: 0x96
byte 1
bits 7:1 Reserved, must be kept at reset value.
bit 0 RegMode: Regulator mode selection when sub-GHz radio is active
0: LDO mode
1: SMPS mode used in Standby with HSE32, FS, RX and TX modes
Note:
For the different CPU operating modes, the LDO or SMPS mode is controlled by the
SMPSEN bit inPWR control register 5 (PWR_CR5). When the sub-GHz radio or CPU
selects the SMPS mode, the LDO mode selection is discarded.
Get_Error() command
Get_Error(Status, OpError) returns the sub-GHz radio operational errors.
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0
1
Opcode
Status[7:0]
w
r
RM0461 Rev 10
2
3
OpError[15:0]
r
r
RM0461
Sub-GHz radio (SUBGHZ)
byte 0
bits 7:0 Opcode: 0x17
byte 1
bits 7:0 Status[7:0]: see Get_Status() command
bytes 3:2
bits 15:9 Reserved, must be kept at reset value.
bit 8 OpError_PaRampError: PA ramping failed
bit 7 Reserved, must be kept at reset value.
bit 6 OpError_PllLockError: RF-PLL locking failed
bit 5 OpError_XoscStartError: HSE32 clock startup failed
bit 4 OpError_ImageCalibrationError: Image calibration failed
bit 3 OpError_AdcCalibrationError: RF-ADC calibration failed
bit 2 OpError_PllCalibrationError: RF-PLL calibration failed
bit 1 OpError_RC13MCalibrationError: Sub-GHz radio RC 13 MHz oscillator
calibration failed
bit 0 OpError_RC64KCalibrationError: Sub-GHz radio RC 64 kHz oscillator
calibration failed
Clr_Error() command
Clr_Error(0x00) clears all recorded sub-GHz radio errors, as reported in Get_Error()
(RC64KCalibrationError, RC13MCalibrationError, PllCalibrationError, AdcCalibrationError,
ImageCalibrationError, XscoStartError, PllLockError and PaRampError).
4.8.8
0
1
Opcode
0x00
w
w
byte 0
bits 7:0 Opcode: 0x07
byte 1
bits 7:0 0x00
Set_TcxoMode command
Set_TcxoMode(RegTcxoTrim,Timeout) is used to configure the TCXO and HSE32
ready timeout.
Table 31. Command format Set_TcxoMode()
Byte 0
Byte 1
Byte 2-4
Opcode = 0x97
RegTcxoTrim[2:0]
Timeout[23:0]
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RM0461
The definition of RegTcxoTrim and Timeout bytes is given in the table below.
Table 32. RegTcxoTrim and Timeout bytes definition
Byte 1 [7:3]
Byte 1 RegTcxoTrim[2:0(1)] (V)
Byte 2-4 [23:0] timeout
0x0 = 1.6
0x000000 = timeout disabled
0x1 = 1.7
Other = timeout enabled(2)
0x2 = 1.8
-
0x3 = 2.2
-
0x4 = 2.4
-
0x5 = 2.7
-
0x6 = 3.0
-
0x7 = 3.3
-
Reserved
1. To use VDDTCXO, the VDDRF supply must be at least + 200 mV higher than the selected
RegTcxoTrim voltage level.
2. Maximum time the system waits for the HSE32 clock to be ready, before HSEStartErr is set.
The time-out duration is computed by the following formula:
Time-out duration = Timeout x 15.625 μs (maximum time-out duration = 262.14 s)
4.8.9
Sub-GHz radio commands overview
The sub-GHz radio commands are mapped as 8-bit addressable SPI commands, as
described in the table below:
Table 33. Sub-GHz radio SPI commands overview
Command
Opcode
CalibratImage()
0x98
CalFreq1, CalFreq2
Calibrate()
0x89
CalibCfg
Cfg_DioIrq()
0x08
IrqMask, Irq1Mask, Irq2Mask, Irq3Mask
Clr_Error()
0x07
0x00
Clr_IrqStatus()
0x02
ClrIrq
Get_Error()
0x17
Status, OpError
Get_IrqStatus()
0x12
Status, IrqStatus
FSK
Get_PacketStatus()
LoRa
0x14
Parameters
Status, RxStatus, RssiSync, RssiAvg
Status. RssiPkt, SnrPkt, SignalRssiPkt
Get_PacketType()
0x11
Status, PktType
Get_RssiInst()
0x15
Status, RssiInst
Get_RxBufferStatus()
0x13
Status, RxPayloadLength, RxBufferPointer
FSK
Get_Stats()
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0x10
Status, NbPktReceived, NbPktCrcError, NbPktLengthError
Status, NbPktReceived, NbPktCrcError, NbPktHeaderError
RM0461 Rev 10
RM0461
Sub-GHz radio (SUBGHZ)
Table 33. Sub-GHz radio SPI commands overview (continued)
Command
Opcode
Get_Status()
0xC0
Status
Read_Buffer()
0x1E
Offset, Status, Data0, Data1, ..., Datan
Read_Register()
0x1D
Addr, Status, Data0, Data1, ..., Datan
Reset_Stats()
0x00
0x00, 0x00, 0x00, 0x00, 0x00, 0x00
Set_BufferBaseAddress()
0x8F
TxBaseAddr, RxBaseAddr
Set_Cad()
0xC5
-
Set_CadParams()
0x88
NbCadSymbol, CadDetPeak, CadDetMin, CadExitMode,
Timeout
Set_Fs()
0xC1
-
Set_LoRaSymbTimeout()
0xA0
SymbNum
FSK
LoRa
Set_ModulationParams()
Br, PulseShape, Bw, Fdev
0x8B
BPSK
LoRa
PaDutyCycle, HpMax, HpSel, 0x01
PbLength, PdDetLength, SyncWordLength, AddrComp,
PktType, PayloadLength, CrcType, Whitening
Generic
Set_PacketParams()
Sf, Bw, Cr, Ldro
Br, PulseShape
0x95
Set_PaConfig()
Parameters
0x8C
BPSK
PbLength, HeaderType, PayloadLength, CrcType, InvertIQ
PayloadLength
Set_PacketType()
0x8A
PktType
Set_RegulatorMode()
0x96
RegMode
Set_RfFrequency()
0x86
RfFreq
Set_Rx()
0x82
Timeout
Set_RxDutyCycle()
0x94
RxPeriod, SleepPeriod
Set_TxRxFallbackMode()
0x93
FallbackMode
Set_Sleep()
0x84
SleepCfg
Set_Standby()
0x80
StandbyCfg
Set_StopRxTimerOnPreamble()
0x9F
RxTimeoutStop
Set_TcxoMode()
0x97
RegTcxoTrim, Timeout
Set_Tx()
0x83
Timeout
Set_TxContinuousWave()
0xD1
-
Set_TxContinuousPreamble()
0xD2
-
Set_TxParams()
0x8E
Power, RampTime
Write_Buffer()
0x0E
Offset, Data0, Data1, ..., Datan
Write_Register()
0x0D
Addr, Data0, Data1, ..., Datan
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4.9
RM0461
Sub-GHz radio application configuration
The sub-GHz radio is controlled via the SPI command interface. The following sections
describe the basic sequence for some sub-GHz radio operations.
After releasing the sub-GHz radio reset and waking it up with sub-GHz radio SPI NSS, the
sub-GHz radio automatically performs a calibration and enters Standby mode. When the
sub-GHz radio is already active, the Standby mode can be requested by Set_Standby().
Once BUSY goes low, the sub-GHz radio can be set in Active mode.
4.9.1
Basic sequence for LoRa, (G)MSK and (G)FSK transmit operation
The sub-GHz radio can be set in LoRa, (G)MSK or (G)FSK transmit operation mode with
the following steps:
1.
Define the location of the transmit payload data in the data buffer, with
Set_BufferBaseAddress().
2.
Write the payload data to the transmit data buffer with Write_Buffer().
3.
Select the packet type (generic or LoRa) with Set_PacketType().
4.
Define the frame format with Set_PacketParams().
5.
Define synchronization word in the associated packet type SUBGHZ_xSYNCR(n) with
Write_Register().
6.
Define the RF frequency with Set_RfFrequency().
7.
Define the PA configuration with Set_PaConfig().
8.
Define the PA output power and ramping with Set_TxParams().
9.
Define the modulation parameters with Set_ModulationParams().
10. Enable TxDone and timeout interrupts by configuring IRQ with Cfg_DioIrq().
11. Start the transmission by setting the sub-GHz radio in TX mode with Set_Tx(). After
the transmission is finished, the sub-GHz radio enters automatically the Standby mode.
12. Wait for sub-GHz radio IRQ interrupt and read interrupt status with
Get_IrqStatus():
a)
On a TxDone interrupt, the packet is successfully sent
b)
On a timeout interrupt, the transmission is timeout.
13. Clear interrupt with Clr_IrqStatus().
14. Optionally, send a Set_Sleep() command to force the sub-GHz radio in Sleep mode.
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4.9.2
Sub-GHz radio (SUBGHZ)
Basic sequence for LoRa and (G)FSK receive operation
The sub-GHz radio can be set in LoRa or (G)FSK receive operation mode with the following
steps:
1.
Define the location where the received payload data must be stored in the data buffer,
with Set_BufferBaseAddress().
2.
Select the packet type (generic or LoRa) with Set_PacketType().
3.
Define the frame format with Set_PacketParams().
4.
Define synchronization word in the associated packet type SUBGHZ_xSYNCR(n) with
Write_Register().
5.
Define the RF frequency with Set_RfFrequency().
6.
Define the modulation parameters with Set_ModulationParams().
7.
Enable RxDone and timeout interrupts by configuring IRQ with Cfg_DioIrq().
8.
9.
Start the receiver by setting the sub-GHz radio in RX mode with Set_Rx():
–
When in continuous receiver mode, the sub-GHz radio remains in RX mode to
look for packets until stopped with Set_Standby().
–
In single mode (with or without timeout), when the reception is finished, the
sub-GHz radio enters automatically the Standby mode.
–
In listening mode, the sub-GHz radio repeatedly switches between RX single with
timeout mode and Sleep mode.
Wait for sub-GHz radio IRQ interrupt and read the interrupt status with
Get_IrqStatus():
a)
On a RxDone interrupt, a packet is received:
–
Check received packet error status (header error, crc error) with
Get_IrqStatus().
–
When a valid packet is received, read the receive start buffer pointer and received
payload length with Get_RxBufferStatus().
–
Read the received payload data from the receive data buffer with
Read_Buffer().
b)
On a timeout interrupt, the reception is timed out.
10. Clear interrupts with Clr_IrqStatus().
11. Optionally, send a Set_Sleep() command to force the sub-GHz radio in Sleep mode.
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4.9.3
RM0461
Basic sequence for BPSK transmit operation
The sub-GHz radio can be set in BPSK transmit operation mode by the following steps:
1.
Define the location of the transmit payload data in the data buffer, with
Set_BufferBaseAddress()
2.
Write the packet data (synchronization word, payload data) to the transmit data buffer
with Write_Buffer().
3.
Select the packet type (BPSK) with Set_PacketType().
4.
Define the frame format with Set_PacketParams().
5.
Define the RF frequency with Set_RfFrequency().
6.
Define the PA configuration with Set_PaConfig().
7.
Define the PA output power and ramping with Set_TxParams().
8.
Define the modulation parameters with Set_ModulationParams().
9.
Enable TxDone and Timeout interrupts by configuring IRQ with Cfg_DioIrq().
10. Start the transmission by setting the sub-GHz radio in TX mode with Set_Tx(). After
the transmission is finished, the sub-GHz radio enters automatically the Standby mode.
11. Wait for sub-GHz radio IRQ interrupt and read interrupt status with
Get_IrqStatus():
a)
On a TxDone interrupt, the packet is successfully sent.
b)
On a timeout interrupt, the transmission is timed out.
12. Clear interrupt with Clr_IrqStatus().
13. Optionally, send a Set_Sleep() command to force the sub-GHz radio in Sleep mode.
4.10
Sub-GHz radio registers
The sub-GHz radio peripheral registers can be accessed by sub-GHz radio command
Write_Register() and Read_Register().
4.10.1
Sub-GHz radio ramp-up MSB register (SUBGHZ_RAM_RAMPUPH)
Address offset: 0x0F0
Reset value: 0x00
7
6
5
4
rw
rw
rw
rw
3
2
1
0
rw
rw
rw
rw
RAMPUP[15:8]
Bits 7:0 RAMPUP[15:8]: Ramp-up MSB bits
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4.10.2
Sub-GHz radio (SUBGHZ)
Sub-GHz radio ramp-up LSB register (SUBGHZ_RAM_RAMPUPL)
Address offset: 0x0F1
Reset value: 0x00
7
6
5
4
3
2
1
0
rw
rw
rw
rw
3
2
1
0
rw
rw
rw
rw
3
2
1
0
rw
rw
rw
rw
2
1
0
rw
rw
rw
RAMPUP[7:0]
rw
rw
rw
rw
Bits 7:0 RAMPUP[7:0]: Ramp-up LSB bits
4.10.3
Sub-GHz radio ramp-down MSB register
(SUBGHZ_RAM_RAMPDNH)
Address offset: 0x0F2
Reset value: 0x00
7
6
5
4
rw
rw
rw
rw
RAMPDN[15:8]
Bits 7:0 RAMPDN[15:8]: Ramp-down MSB bits
4.10.4
Sub-GHz radio ramp-down LSB register
(SUBGHZ_RAM_RAMPDNL)
Address offset: 0x0F3
Reset value: 0x00
7
6
5
4
RAMPDN[7:0]
rw
rw
rw
rw
Bits 7:0 RAMPDN[7:0]: Ramp-down LSB bits
4.10.5
Sub-GHz radio frame limit MSB register
(SUBGHZ_RAM_FRAMELIMH)
Address offset: 0x0F4
Reset value: 0x00
7
6
5
4
3
FRAMELIMH[15:8]
rw
rw
rw
rw
rw
Bits 7:0 FRAMELIMH[15:8]: frame limit MSB bits
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4.10.6
RM0461
Sub-GHz radio frame limit LSB register
(SUBGHZ_RAM_FRAMELIML)
Address offset: 0x0F5
Reset value: 0x00
7
6
5
4
3
2
1
0
rw
rw
rw
rw
FRAMELIML[7:0]
rw
rw
rw
rw
Bits 7:0 FRAMELIML[7:0]: frame limit LSB bits
4.10.7
Sub-GHz radio generic bit synchronization register
(SUBGHZ_GBSYNCR)
Address offset: 0x6AC
Reset value: 0x00
This register must be cleared to 0x00 when using packet types other than LoRa.
7
6
5
4
3
2
1
0
Res.
SBITSYNCEN
RXDINV
BITSYNCDIS
Res.
Res.
Res.
Res.
rw
rw
rw
Bit 7 Reserved, must be kept at reset value.
Bit 6 SBITSYNCEN: LoRa simple bit synchronization enable
This bit must be cleared to 0 when using generic packet and BPSK type.
0: simple bit synchronization disabled
1: simple bit synchronization enabled
Bit 5 RXDINV: LoRa receive data inversion
This bit must be cleared to 0 when using generic packet and BPSK type.
0: receive data not inverted
1: receive data inverted
Bit 4 BITSYNCDIS: LoRa normal bit synchronization enable
This bit must be cleared to 0 when using generic packet and BPSK type.
0: normal bit synchronization enabled
1: normal bit synchronization disabled
Bits 3:0 Reserved, must be kept at reset value.
4.10.8
Sub-GHz radio generic CFO MSB register (SUBGHZ_GCFORH)
Address offset: 0x6B0
Reset value: 0x00
7
6
5
4
Res
Res
Res
Res
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2
r
r
1
0
DEMOD_CFO[3:0]
RM0461 Rev 10
r
r
RM0461
Sub-GHz radio (SUBGHZ)
Bits 7:4 Reserved, must be kept at reset value.
Bits 3:0 DEMOD_CFO[3:0]: actual frequency error from normalized value (MSB bits)
4.10.9
Sub-GHz radio generic CFO LSB register (SUBGHZ_GCFORL)
Address offset: 0x6B1
Reset value: 0x00
7
6
5
4
3
2
1
0
r
r
r
DEMOD_CFO[7:0]
r
r
r
r
r
Bits 7:0 DEMOD_CFO[7:0]: actual frequency error from normalized value (LSB bits)
4.10.10
Sub-GHz radio generic packet control 1 register
(SUBGHZ_GPKTCTL1R)
Address offset: 0x06B4
Reset value: 0x04
This register must be cleared to 0x00 when using packet types other than LoRa.
7
6
5
4
3
2
Res
Res
Res
Res
Res
PBDETON
1
0
PBDETLEN[1:0]
rw
rw
rw
Bits 7:3 Reserved, must be kept at reset value.
Bit 2 PBDETON: Preamble detection enable
Bits 1:0 PBDETLEN: Receiver preamble detection length
0b00: 8-bit preamble detection
0b01: 16-bit preamble detection
0b10: 24-bit preamble detection
0b11: 32-bit preamble detection
4.10.11
Sub-GHz radio generic packet control 1A register
(SUBGHZ_GPKTCTL1AR)
Address offset: 0x6B8
Reset value: 0x21
7
6
5
4
Res.
Res.
SYNCDETEN
CONTTX
rw
rw
3
2
INFSEQSEL[1:0]
rw
1
0
INFSQEQEN
WHITEINI[8]
rw
rw
rw
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 SYNCDETEN: Generic packet synchronization word detection enable
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RM0461
Bit 4 CONTTX: Generic packet continuous transmit enable
Bits 3:2 INFSEQSEL[1:0]: Generic packet infinite sequence selection
00: preamble 0x5555
01: all zero 0x0000
10: all one 0xFFFF
11: PRBS9
Bit 1 INFSQEQEN: Generic packet infinite sequence enable
Bit 0 WHITEINI[8]: Generic packet whitening initial value MSB bit [8]
4.10.12
Sub-GHz radio generic whitening LSB register
(SUBGHZ_GWHITEINIRL)
Address offset: 0x6B9
Reset value: 0x00
7
6
5
4
3
2
1
0
rw
rw
rw
rw
2
1
0
rw
rw
rw
WHITEINI[7:0]
rw
rw
rw
rw
Bits 7:0 WHITEINI[7:0]: Generic packet whitening initial value LSB bits [7:0]
4.10.13
Sub-GHz radio generic payload length register
(SUBGHZ_GRTXPLDLEN)
Address offset: 0x6BB
Reset value: 0x0F
7
6
5
4
3
RTXPLDLEN[7:0]
rw
rw
rw
rw
rw
Bits 7:0 RTXPLDLEN[7:0]: Payload length FIFO match value in Rx and Tx
4.10.14
Sub-GHz radio generic CRC initial MSB register
(SUBGHZ_GCRCINIRH)
Address offset: 0x6BC
Reset value: 0x1D
7
6
5
4
rw
rw
rw
rw
3
2
1
0
rw
rw
rw
rw
CRCINI[15:8]
Bits 7:0 CRCINI[15:8]: Generic packet CRC initial polynomial MSB bits [15:8]
These bits are used for CRC initialization.
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4.10.15
Sub-GHz radio (SUBGHZ)
Sub-GHz radio generic CRC initial LSB register
(SUBGHZ_GCRCINIRL)
Address offset: 0x6BD
Reset value: 0x0F
7
6
5
4
3
2
1
0
rw
rw
rw
rw
CRCINI[7:0]
rw
rw
rw
rw
Bits 7:0 CRCINI[7:0]: Generic packet CRC initial polynomial LSB bits [7:0]
These bits are used for CRC initialization.
4.10.16
Sub-GHz radio generic CRC polynomial MSB register
(SUBGHZ_GCRCPOLRH)
Address offset: 0x6BE
Reset value: 0x10
7
6
5
4
3
2
1
0
rw
rw
rw
rw
CRCPOL[15:8]
rw
rw
rw
rw
Bits 7:0 CRCPOL[15:8]: Generic packet CRC polynomial MSB bits [15:8]
These bits are used for CRC initialization.
4.10.17
Sub-GHz radio generic CRC polynomial LSB register
(SUBGHZ_GCRCPOLRL)
Address offset: 0x6BF
Reset value: 0x21
7
6
5
4
3
2
1
0
rw
rw
rw
rw
CRCPOLI[7:0]
rw
rw
rw
rw
Bits 7:0 CRCPOLI[7:0]: Generic packet CRC initial polynomial LSB bits [7:0]
These bits are used for CRC initialization.
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4.10.18
RM0461
Sub-GHz radio generic synchronization word control register 0
(SUBGHZ_GSYNCR0)
Address offset: 0x6C0
Reset value: 0x97
7
6
5
4
3
2
1
0
rw
rw
rw
SYNCWORD[63:56]
rw
rw
rw
rw
rw
Bits 7:0 SYNCWORD[63:56]: Eight byte of generic packet synchronization word
4.10.19
Sub-GHz radio generic synchronization word control register 1
(SUBGHZ_GSYNCR1)
Address offset: 0x6C1
Reset value: 0x23
7
6
5
4
3
2
1
0
rw
rw
rw
SYNCWORD[55:48]
rw
rw
rw
rw
rw
Bits 7:0 SYNCWORD[55:48]: Seventh byte of generic packet synchronization word
4.10.20
Sub-GHz radio generic synchronization word control register 2
(SUBGHZ_GSYNCR2)
Address offset: 0x6C2
Reset value: 0x52
7
6
5
4
3
2
1
0
rw
rw
rw
SYNCWORD[47:40]
rw
rw
rw
rw
rw
Bits 7:0 SYNCWORD[47:40]: Sixth byte of generic packet synchronization word
4.10.21
Sub-GHz radio generic synchronization word control register 3
(SUBGHZ_GSYNCR3)
Address offset: 0x6C3
Reset value: 0x25
7
6
5
4
rw
rw
rw
rw
3
2
1
0
rw
rw
rw
SYNCWORD[39:32]
rw
Bits 7:0 SYNCWORD[39:32]: Fifth byte of generic packet synchronization word
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4.10.22
Sub-GHz radio (SUBGHZ)
Sub-GHz radio generic synchronization word control register 4
(SUBGHZ_GSYNCR4)
Address offset: 0x6C4
Reset value: 0x56
7
6
5
4
3
2
1
0
rw
rw
rw
SYNCWORD[31:24]
rw
rw
rw
rw
rw
Bits 7:0 SYNCWORD[31:24] Fourth byte of generic packet synchronization word
4.10.23
Sub-GHz radio generic synchronization word control register 5
(SUBGHZ_GSYNCR5)
Address offset: 0x6C5
Reset value: 0x53
7
6
5
4
3
2
1
0
rw
rw
rw
SYNCWORD[23:16]
rw
rw
rw
rw
rw
Bits 7:0 SYNCWORD[23:16]: Third byte of generic packet synchronization word
4.10.24
Sub-GHz radio generic synchronization word control register 6
(SUBGHZ_GSYNCR6)
Address offset: 0x6C6
Reset value: 0x65
7
6
5
4
3
2
1
0
rw
rw
rw
SYNCWORD[15:8]
rw
rw
rw
rw
rw
Bits 7:0 SYNCWORD[15:8]: Second byte of generic packet synchronization word
4.10.25
Sub-GHz radio generic synchronization word control register 7
(SUBGHZ_GSYNCR7)
Address offset: 0x6C7
Reset value: 0x64
7
6
5
4
rw
rw
rw
rw
3
2
1
0
rw
rw
rw
SYNCWORD[7:0]
rw
Bits 7:0 SYNCWORD[7:0]: First byte of generic packet synchronization word
RM0461 Rev 10
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Sub-GHz radio (SUBGHZ)
4.10.26
RM0461
Sub-GHz radio generic node address register
(SUBGHZ_GNODEADR)
Address offset: 0x6CD
Reset value: 0x00
7
6
5
4
3
2
1
0
rw
rw
rw
rw
NODEADD[7:0]
rw
rw
rw
rw
Bits 7:0 NODEADD[7:0]: Node address used in FSK mode register
4.10.27
Sub-GHz radio generic broadcast address register
(SUBGHZ_GBCASTADDR)
Address offset: 0x6CE
Reset value: 0x00
7
6
5
4
3
2
1
0
rw
rw
rw
rw
BCASTADD[7:0]
rw
rw
rw
rw
Bits 7:0 BCASTADD[7:0]: Broadcast address used in FSK mode register
4.10.28
Sub-GHz radio generic AFC register (SUBGHZ_GAFCR)
Address offset: 0x6D1
Reset value: 0x18
7
6
5
4
3
2
1
0
rw
rw
rw
rw
3
2
1
0
rw
rw
rw
rw
AFC[7:0]
rw
rw
rw
rw
Bits 7:0 AFC[7:0]: Automatic frequency control register
4.10.29
Sub-GHz radio LoRa payload length register
(SUBGHZ_LPLDLENR)
Address offset: 0x702
Reset value: 0x00
7
6
5
4
PLDLEN[7:0]
rw
rw
rw
rw
Bits 7:0 PLDLEN[7:0]: Payload length in number of bytes, in case of LoRa fixed header
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RM0461
4.10.30
Sub-GHz radio (SUBGHZ)
Sub-GHz radio synchro timeout register
(SUBGHZ_LSYNCTIMEOUTR)
Address offset: 0x706
Reset value: 0x00
7
6
5
4
3
2
1
0
r
r
r
SYNCTIMEOUT[7:0]
r
r
r
r
r
Bits 7:0 SYNCTIMEOUT[7:0]: TimeoutValue = synchtimeout[7:3]*2^(2*synchtimeout[2:0]+1)
If a detection has not occurred by TimeoutValue, it goes back to Standby mode, or restart
synch in continuous receive mode
Bits 7:3 synchtimeout(7:3) mantissa part
Bits 2:0 synchtimeout(2:0) exponent part
4.10.31
Sub-GHz radio LoRa IQ polarity MSB register (SUBGHZ_LIQPOLR)
Address offset: 0x735
Reset value: 0x00
7
6
5
4
3
2
1
0
Res
Res
Res
Res
Res
Res
Res
Res
Bits 7:0 Reserved, must be kept at reset value.
4.10.32
Sub-GHz radio LoRa IQ polarity LSB register (SUBGHZ_LIQPOLR)
Address offset: 0x736
Reset value: 0x00
7
6
5
4
3
2
1
0
Res
Res
Res
Res
Res
Res
Res
Res
Bits 7:0 Reserved, must be kept at reset value.
4.10.33
Sub-GHz radio LoRa synchronization word MSB register
(SUBGHZ_LSYNCRH)
Address offset: 0x740
Reset value: 0x14
7
6
5
4
rw
rw
rw
rw
3
2
1
0
rw
rw
rw
SYNCWORD[15:8]
rw
RM0461 Rev 10
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Sub-GHz radio (SUBGHZ)
RM0461
Bits 7:0 SYNCWORD[15:8]: LoRa synchronization word MSB bits [15:8]
0x14: LoRa private network
0x34: LoRa public network
Others: reserved
4.10.34
Sub-GHz radio LoRa synchronization word LSB register
(SUBGHZ_LSYNCRL)
Address offset: 0x741
Reset value: 0x24
7
6
5
4
3
2
1
0
rw
rw
rw
SYNCWORD[7:0]
rw
rw
rw
rw
rw
Bits 7:0 SYNCWORD[7:0]: LoRa synchronization word LSB bits [7:0]
0x24: LoRa private network
0x44: LoRa public network
Others: reserved
4.10.35
Sub-GHz radio Tx address pointer register (SUBGHZ_TXADRPTR)
Address offset: 0x0802
Reset value: 0x00
7
6
5
4
3
2
1
0
rw
rw
rw
rw
3
2
1
0
rw
rw
rw
rw
PTR[7:0]
rw
rw
rw
rw
Bits 7:0 PTR[7:0]: TX buffer address pointer
4.10.36
Sub-GHz radio Rx address pointer register
(SUBGHZ_RXADRPTRR)
Address offset: 0x0803
Reset value: 0x00
7
6
5
4
PTR[7:0]
rw
rw
rw
rw
Bits 7:0 PTR[7:0]: RX buffer address pointer
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RM0461
4.10.37
Sub-GHz radio (SUBGHZ)
Sub-GHz radio bandwidth select register (SUBGHZ_BWSELR)
Address offset: 0x807
Reset value: 0x00
7
6
5
4
Res
Res
Res
CHBWMANT[1:0]
3
r
2
1
0
CHBWEXPO[2:0]
r
r
r
r
Bits 7:5 Reserved, must be kept at reset value.
Bits 4:3 CHBWMANT[1:0]: Channel bandwidth mantissa
Bits 2:0 CHBWEXP[2:0]: Channel bandwidth exponent
4.10.38
Sub-GHz radio random number register 3 (SUBGHZ_RNGR3)
Address offset: 0x819
Reset value: 0x00
7
6
5
4
r
r
r
r
3
2
1
0
r
r
r
r
RNDATA[31:24]
Bits 7:0 RNDATA[31:24]: Random number data bits [31:24]
4.10.39
Sub-GHz radio random number register 2 (SUBGHZ_RNGR2)
Address offset: 0x81A
Reset value: 0x00
7
6
5
4
3
2
1
0
r
r
r
r
RNDATA[23:16]
r
r
r
r
Bits 7:0 RNDATA[23:16]: Random number data bits [23:16]
4.10.40
Sub-GHz radio random number register 1 (SUBGHZ_RNGR1)
Address offset: 0x81B
Reset value: 0x00
7
6
5
4
3
2
1
0
r
r
r
r
RNDATA[15:8]
r
r
r
r
Bits 7:0 RNDATA[15:8]: Random number data bits [15:8]
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Sub-GHz radio (SUBGHZ)
4.10.41
RM0461
Sub-GHz radio random number register 0 (SUBGHZ_RNGR0)
Address offset: 0x81C
Reset value: 0x00
7
6
5
4
3
2
1
0
r
r
r
r
RNDATA[7:0]
r
r
r
r
Bits 7:0 RNDATA[7:0]: Random number data bits [7:0]
4.10.42
Sub-GHz radio SD resolution register (SUBGHZ_SDCFG0R)
Address offset: 0x889
Reset value: 0x00
7
6
5
4
3
2
1
0
rw
rw
rw
rw
3
2
1
0
rw
rw
rw
rw
SD[7:0]
rw
rw
rw
rw
Bits 7:0 SD[7:0]: Radio SD resolution
4.10.43
Sub-GHz radio AGC RSSI control register
(SUBGHZ_AGCRSSICTL0R)
Address offset: 0x89B
Reset value: 0x00
7
6
5
4
CALDATA[7:0]
rw
rw
rw
rw
Bits 7:0 CALDATA[7:0]: AGC RSSI control
4.10.44
Sub-GHz radio receiver gain control register (SUBGHZ_RXGAINCR)
Address offset: 0x8AC
Reset value: 0x94
7
6
5
4
3
2
1
SENSI_ADJUST[5:0]
rw
rw
rw
rw
rw
Bits 7:2 SENSI_ADJUST[5:0]: Sensitivity Floor of AGC
This bitfield must be kept at 0x25.
170/1290
0
PMODE[1:0]
RM0461 Rev 10
rw
rw
rw
RM0461
Sub-GHz radio (SUBGHZ)
Bits 1:0 PMODE[1:0]: Receiver power mode selection between normal mode and power saving mode
00: power saving mode (reduced sensitivity)
01: boost mode level1 active (improves sensitivity at detriment of power consumption)
10: boost mode level2 active (improves a set further sensitivity at detriment of power
consumption)
Others: boost mode (best receiver sensitivity)
4.10.45
Sub-GHz radio AGC reset configuration register
(SUBGHZ_AGCGFORSTCFGR)
Address offset: 0x8B8
Reset value: 0x14
7
6
5
4
3
2
1
0
rw
rw
rw
rw
EN[7:0]
rw
rw
rw
rw
Bits 7:0 EN[7:0]: Enable the reset generation for frequency-offset estimation
4.10.46
Sub-GHz radio AGC reset power threshold register
(SUBGHZ_AGCGFORSTPOWTHR)
Address offset: 0x8B9
Reset value: 0x0A
7
6
5
4
3
2
1
0
rw
rw
rw
rw
PWRTHR[7:0]
rw
rw
rw
rw
Bits 7:0 PWRTHR[7:0]: Power threshold reset for frequency-offset estimation
4.10.47
Sub-GHz radio Tx clamp register (SUBGHZ_TXCLAMPR)
Address offset: 0x8D8
Reset value: 0x00
7
6
5
4
3
2
1
0
Res
Res
Res
Res
Res
Res
Res
Res
Bits 7:0 Reserved, must be kept at reset value.
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Sub-GHz radio (SUBGHZ)
4.10.48
RM0461
Sub-GHz radio disable LNA register (REG_ANA_LNA)
Address offset: 0x8E2
Reset value: 0x00
7
6
5
4
3
2
1
0
Res
Res
Res
Res
Res
Res
Res
Res
Bits 7:0 Reserved, must be kept at reset value.
4.10.49
Sub-GHz radio disable mixer register (REG_ANA_MIXER)
Address offset: 0x8E5
Reset value: 0x00
7
6
5
4
3
2
1
0
Res
Res
Res
Res
Res
Res
Res
Res
2
1
0
rw
rw
rw
Bits 7:0 Reserved, must be kept at reset value.
4.10.50
Sub-GHz radio PA over current protection register
(SUBGHZ_PAOCPR)
Address offset: 0x8E7
Reset value: 0x18
7
6
Res.
Res.
5
4
3
OCP[5:0]
rw
rw
rw
Bits 7:6 Reserved, must be kept at reset value.
Bits 5:0 OCP[5:0]: Power amplifier over current protection level
0x18: maximum 60 mA current for LP PA mode
0x38: maximum 140mA current for HP PA mode.
Others: reserved
4.10.51
Sub-GHz radio RTC control register (SUBGHZ_RTCCTLR)
Address offset: 0x902
Reset value: 0x00
7
6
5
4
3
2
1
0
Res
Res
Res
Res
Res
Res
Res
RTCEN
rw
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RM0461
Sub-GHz radio (SUBGHZ)
Bits 7:1 Reserved, must be kept at reset value.
Bit 0 RTCEN: Writing 1 restarts the radio RTC.
4.10.52
Sub-GHz radio RTC period MSB register (SUBGHZ_RTCPRDR2)
Address offset: 0x906
Reset value: 0x00
7
6
5
4
3
2
1
0
rw
rw
rw
rw
3
2
1
0
rw
rw
rw
rw
RTCPRD[31:16]
rw
rw
rw
rw
Bits 7:0 RTCPRD[31:16]: Updates radio RTC period (MSB)
4.10.53
Sub-GHz radio RTC period mid-byte register
(SUBGHZ_RTCPRDR1)
Address offset: 0x907
Reset value: 0x00
7
6
5
4
RTCPRD[15:8]
rw
rw
rw
rw
Bits 7:0 RTCPRD[15:8]: Updates radio RTC period (mid-byte)
4.10.54
Sub-GHz radio RTC period LSB register (SUBGHZ_RTCPRDR0)
Address offset: 0x908
Reset value: 0x00
7
6
5
4
3
2
1
0
rw
rw
rw
rw
RTCPRD[7:0]
rw
rw
rw
rw
Bits 7:0 RTCPRD[7:0]: Updates radio RTC period (LSB)
RM0461 Rev 10
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Sub-GHz radio (SUBGHZ)
4.10.55
RM0461
Sub-GHz radio HSE32 OSC_IN capacitor trim register
(SUBGHZ_HSEINTRIMR)
Address offset: 0x911
Reset value: 0x12
This register is retained in Sleep mode, but lost in Deep-Sleep mode.
7
6
Res.
Res.
5
4
3
2
1
0
rw
rw
rw
TRIM[5:0]
rw
rw
rw
Bits 7:6 Reserved, must be kept at reset value.
Bits 5:0 TRIM[5:0]: HSE32 XTAL mode OSC_IN load capacitor trimming
Load capacitor trimming step size ~0.47 pf.
0x00: minimum value ~11.3 pF
...
0x12 value ~20.3 pF (default)
...
0x2F: maximum capacitor value ~33.4 pF
Others: reserved
4.10.56
Sub-GHz radio HSE32 OSC_OUT capacitor trim register
(SUBGHZ_HSEOUTTRIMR)
Address offset: 0x912
Reset value: 0x12
This register is retained in Sleep mode, but lost in Deep-Sleep mode.
7
6
Res.
Res.
5
4
3
rw
rw
rw
2
1
0
rw
rw
rw
TRIM[5:0]
Bits 7:6 Reserved, must be kept at reset value.
Bits 5:0 TRIM[5:0]: HSE32 XTAL mode OSC_OUT load capacitor trimming
Load capacitor trimming step size ~0.47 pf.
0x00: minimum value ~11.3 pF
...
0x12 value ~20.3 pF (default)
...
0x2F: maximum capacitor value ~33.4 pF
Others: reserved
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RM0461
4.10.57
Sub-GHz radio (SUBGHZ)
Sub-GHz radio SMPS control 0 register (SUBGHZ_SMPSC0R)
Address offset: 0x916
Reset value: 0x00
7
6
5
4
3
2
1
0
Res.
CLKDE
Res.
Res.
Res.
Res.
Res.
Res.
rw
Bit 7 Reserved, must be kept at reset value.
Bit 6 CLKDE: SMPS clock detection enable
SMPS clock detection must be enabled before enabling the SMPS, if the application uses an
external HSE clock source (not coming from XO or TCXO but from another device).
0: SMPS clock detection disabled
1: SMPS clock detection enabled
Bits 5:0 Reserved, must be kept at reset value.
4.10.58
Sub-GHz radio power control register (SUBGHZ_PCR)
Address offset: 0x91A
Reset value: 0x50
This register is retained in Sleep mode but lost in Deep-Sleep mode.
7
6
Res.
CLE
rw
5
4
CLV[1:0]
rw
3
2
1
0
Res.
Res.
Res.
Res.
rw
Bit 7 Reserved, must be kept at reset value.
Bit 6 CLE: Power-supply current limiter enable
0: power-supply current limiter disabled (unlimited current)
1: power-supply current limiter enabled (current limited according to CLV[1:0])
Bits 5:4 CLV[1:0]: Power-supply current limiter value
When the power-supply current limiter is enabled by CLEN, these bits define the maximum
current limiting level.
0x0: power-supply current limiting level 25 mA
0x1: power-supply current limiting level 50 mA (default)
0x2: power-supply current limiting level 100 mA
0x3: power-supply current limiting level 200 mA
Bits 3:0 Reserved, must be kept at reset value.
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Sub-GHz radio (SUBGHZ)
4.10.59
RM0461
Sub-GHz radio regulator drive control register
(SUBGHZ_REGDRVCR)
Address offset: 0x91F
Reset value: 0x08
This register is retained in Sleep mode but lost in Deep-Sleep mode.
7
6
5
4
Res
Res
Res
Res
3
2
1
TRIM[2:0
rw
0
EN
rw
rw
rw
Bits 7:4 Reserved, must be kept at reset value.
Bits 3:1 TRIM[2:0]: Regulator drive trimming
000: 1.22
001: 1.24
010: 1.26
011: 1.28
100: 1.30(default)
101: 1.32
110: 1.34
Bit 0 EN: Regulator drive enable
4.10.60
Sub-GHz radio SMPS control 2 register (SUBGHZ_SMPSC2R)
Address offset: 0x923
Reset value: 0x06
This register is retained in Sleep mode but lost in Deep-Sleep mode.
7
6
5
4
3
Res
Res
Res
Res
Res
2
rw
Bits 7:3 Reserved, must be kept at reset value.
Bits 2:1 DRV[1:0]: SMPS maximum drive capability.
0x0: 20 mA
0x1: 40 mA
0x2: 60 mA
0x3: 100 mA (default)
Bit 0 Reserved, must be kept at reset value.
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RM0461 Rev 10
1
DRV[1:0]
0
Res
rw
RM0461
4.10.61
Sub-GHz radio (SUBGHZ)
Sub-GHz radio register map
7
6
5
4
3
2
1
0
SUBGHZ_GBSYNCR
Res.
RXDINV
BITSYNCDIS
Res.
Res.
Res.
Res.
0
0
0
INFSQEQSEL[1:0]
Reset value
SUBGHZ_GPKTCTL1AR
Reserved
Res.
Res.
Reset value
0x6B9
0x6BC
0x6BD
0x6BE
0x6BF
0x6C0
0x6C1
0x6C2
0x6C3
0x6C4
0x6C5
0x6C6
0x6C7
0x6C80x73C
0x740
0x741
0x7420x818
CONTTX
1
0
SUBGHZ_GWHITEINIRL
Reset value
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
1
0
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
1
0
0
0
0
0
0
1
1
0
1
1
1
0
0
0
1
1
1
0
0
1
0
0
0
1
0
1
1
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
0
1
0
0
1
0
0
SYNCWORD[7:0]
0
1
1
0
0
Reserved
SUBGHZ_LSYNCRH
SYNCWORD[15:8]
0
0
0
SUBGHZ_LSYNCRL
Reset value
0
0
Reserved
Reset value
1
SYNCWORD[15:8]
SUBGHZ_GSYNCR7
Reset value
1
SYNCWORD[23:16]
SUBGHZ_GSYNCR6
Reset value
0
SYNCWORD[31:24]
SUBGHZ_GSYNCR5
Reset value
1
SYNCWORD[39:32]
SUBGHZ_GSYNCR4
Reset value
1
SYNCWORD[47:40]
SUBGHZ_GSYNCR3
Reset value
0
SYNCWORD[55:48]
SUBGHZ_GSYNCR2
Reset value
0
SYNCWORD[63:56]
SUBGHZ_GSYNCR1
Reset value
0
CRCPOL[7:0]
SUBGHZ_GSYNCR0
Reset value
0
CRCPOL[15:8]
SUBGHZ_GCRCPOLRL
Reset value
1
CRCINI[7:0]
SUBGHZ_GCRCPOLRH
Reset value
0
CRCINI[15:8]
SUBGHZ_GCRCINIRL
Reset value
0
WHITEINI[7:0]
SUBGHZ_GCRCINIRH
Reset value
0
WHITEINI[8]
0x6B8
Reserved
INFSSQEQEN
0x6AC0x6B4
SYNCDETEN
0x6AC
Register name
SBITSYNCEN
Table 34. SUBGHZ register map and reset values
Offset
1
0
SYNCWORD[7:0]
0
0
1
Reserved
0
0
Reserved
RM0461 Rev 10
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Sub-GHz radio (SUBGHZ)
RM0461
Table 34. SUBGHZ register map and reset values (continued)
Offset
0x819
0x81A
0x81B
0x81C
0x89B
0x8200x8AB
0x8AC
0x8B00x8E6
0x8E7
0x8E8 0x910
0x911
0x912
0x9130x915
0x916
0x9170x919
0x91A
0x91B0x920
0x91F
0x923
Register name
7
6
5
4
SUBGHZ_RNGR3
Reset value
0
0
0
0
0
0
0
SUBGHZ_RNGR2
Reset value
0
0
Reset value
0
0
0
0
SUBGHZ_AGCRSSIC0R
Res.
MODE
MC
0
0
SUBGHZ_RNGR0
0
0
0
0
0
0
0
0
0
0
0
0
Res.
Res.
0
0
1
0
0
0
0
0
0
1
0
0
0
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PMODE[1:0]
Reserved
Res.
Res.
OCP[5:0]
0
1
1
Reserved
Res.
Res.
Res.
Res.
Reset value
TRIM[5:0]
0
Reset value
1
0
TRIM[5:0]
0
1
Reserved
Reserved
Res.
Reset value
CLKDE
Res.
Res.
0
Reserved
Reserved
Res.
Reset value
CLE
1
CLV[1:0]
0
Reserved
Res.
1
Reserved
Res.
Res.
Res.
Res.
Reset value
TRIM[2:0]
1
Res.
Res.
Res.
Res.
Reset value
0
Res.
RM0461 Rev 10
EN
0
DRV[1:0]
1
Refer to Section 2.4 for the register boundary addresses.
178/1290
0
0
1
Reserved
SUBGHZ_SMPSC2R
0
SENSI_ADJUST[5:0].
1
Reset value
SUBGHZ_REGDRVTSTR
0
0
Reserved
SUBGHZ_PCR
0
Reserved
SUBGHZ_RXGAINCR
SUBGHZ_SMPSC0R
0
LENGTH[2:0]
Reserved
SUBGHZ_HSEOUTTRIMR
0
RNDATA[7:0]
Reset value
SUBGHZ_HSEINTRIMR
1
RNDATA[15:8]
0
SUBGHZ_PAOCPR
0
0
0
Reset value
2
RNDATA[23:16]
SUBGHZ_RNGR1
Reset value
3
RNDATA[31:24]
0
Res.
1
RM0461
5
5.1
Power control (PWR)
Power control (PWR)
Power supplies
The STM32WLEx devices require a VDD operating voltage supply between 1.71 V and
3.6 V. Several independent supplies (VDDSMPS, VFBSMPS, VDDA, VDDRF) can be provided for
specific peripherals:
•
VDD = 1.71 V to 3.6 V
VDD is the external power supply for the I/Os, the system analog blocks such as reset,
power management, internal clocks and low-power regulator. It is provided externally
through VDD pins.
•
VDDSMPS = 1.71 V to 3.6 V
VDDSMPS is the external power supply for the SMPS step-down converter. It is provided
externally through VDDSMPS supply pin and must be connected to the same supply as
VDD.
•
VFBSMPS = 1.55 V
VFBSMPS is the external power supply for the main system regulator. It is provided
externally through VFBSMPS pin and is supplied through the SMPS step-down
converter.
•
VDDA = 0 V to 3.6 V (DAC/COMPs minimum voltage is 1.62 V, ADC minimum voltage is
1.8 V and VREFBUF minimum voltage is 2.4 V).
VDDA is the external analog power supply for A/D converters, D/A converters, voltage
reference buffer, and comparators. The VDDA voltage level is independent from the VDD
voltage (see power-up and power-down limitations below) and must preferably be
connected to VDD when these peripherals are not used.
•
VDDRF = 1.71 V to 3.6 V
VDDRF is the external power supply for the radio. It is provided externally through the
VDDRF pin and must be connected to the same supply as VDD.
•
VDDRF1V5 = 1.45 V to 1.62 V
VDDRF1V5 is the external power supply for the radio. It is provided externally through
the VDDRF1V5 pin.
•
VBAT = 1.55 V to 3.6 V
VBAT is the power supply for RTC, TAMP, external clock 32 kHz oscillator and backup
registers (through power switch) when VDD is not present.
•
VREF-, VREF+
VREF+ is the input reference voltage for ADC. It is also the output of the internal voltage
reference buffer when enabled.
–
When VDDA < 2 V, VREF+ must be equal to VDDA.
–
When VDDA ≥ 2 V, VREF+ must be between 2 V and VDDA.
VREF+ can be grounded when ADC is not active. The internal voltage reference buffer
supports the following output voltages, configured with VRS bit in the VREFBUF_CSR
register:
–
VREF+ around 2.048 V: this requires VDDA ≥ 2.4 V.
–
VREF+ around 2.5 V: this requires VDDA ≥ 2.8 V.
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VREF+ pin is not available on all packages. When not available, this pin is internally
bonded to VDDA. When VREF+ is double-bonded with VDDA in a package, the
internal voltage reference buffer is not available and must be kept disabled (refer to the
datasheet for pinout descriptions).
During power up and power down, the following power sequence is required:
1.
When VDD < 1 V other power supplies (VDDA) must remain below VDD + 300 mV.
During power down, VDD can temporarily become lower then other supplies only if the
energy provided to the device remains below 1 mJ. This allows external decoupling
capacitors to be discharged with different time constants during this transient phase.
2.
When VDD > 1 V, all other power supplies (VDDA) become independent.
An embedded linear voltage regulator is used to supply the internal digital power VCORE.
VCORE is the power supply for digital peripherals, SRAM1 and SRAM2. The flash memory is
supplied by VCORE and VDD. VCORE is split in two parts: VDDO part and an interruptible part
VDDI.
Figure 14. Power supply overview
VSW
VBAT
VDD
POR
FW mode
en
VDDSMPS
LDO/SMPS
VLXSMPS
mode
VFBSMPS
VDDRF1V5
LPR
MR
RFLDO
VLP
VMAIN
VBKP
VDDO
VRF
VDDI
MSv50973V2
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The different supply configurations are shown in the figure below.
Figure 15. Supply configurations
VDD
VDD
VDDSMPS
VDDSMPS
VLXSMPS
VLXSMPS
LDO/SMPS
VFBSMPS
VDDRF1V5
LDO/SMPS
VFBSMPS
VDDRF1V5
RF
LDO
MR
LPR
LDO/SMPS supply
RF
LDO
MR
LPR
LDO supply
MSv50974V1
The LDO or SMPS step-down converter operating mode can be configured by one of the
following:
•
by the MCU using the SMPSEN setting in PWR control register 5 (PWR_CR5), that
depends upon the MCU system operating mode (Run, Stop, Standby or Shutdown).
•
by the sub-GHz radio using Set_RegulatorMode() command and the sub-GHz
radio operating mode (Sleep, Calibrate, Standby, Standby with HSE32 or Active).
After any POR and NRST reset, the LDO mode is selected. The SMPS selection has priority
over LDO selection.
While the sub-GHz radio is in Standby with HSE32 or in Active mode, the supply mode is
not altered until the sub-GHz radio enters Standby or Sleep mode. The sub-GHz radio
activity may add a delay for entering the MCU software requested supply mode.
The LDO or SMPS supply mode can be checked with the SMPSRDY flag in Power status
register 2 (PWR_SR2).
Note:
When the radio is active, the supply mode is not changed until after the radio activity is
finished.
During Stop 1, Stop 2 and Standby modes, when the sub-GHz radio is not active, the LDO
or SMPS step-down converter is switched off. When exiting low-power modes (except
Shutdown), the SMPS step-down converter is set by hardware to the mode selected by the
SMPSEN bit in PWR control register 5 (PWR_CR5). SMPSEN is retained in Stop and
Standby modes.
Independently from the MCU software selected supply operating mode, the sub-GHz radio
allows the supply mode selection while the sub-GHz radio is active (thanks to the sub-GHz
radio Set_RegulatorMode()command). For more details, see Relation between MCU
and sub-GHz radio operating modes.
The maximum load current delivered by the SMPS can be selected by the sub- GHz radio
SUBGHZ_SMPSC2R register. For more details see Section 4: Sub-GHz radio (SUBGHZ).
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The inrush current of the LDO and SMPS step-down converter can be controlled via the
sub- GHz radio SUBGHZ_PCR register. This information is retained in all but the sub-GHz
radio Deep-Sleep mode. For more details see Section 4: Sub-GHz radio (SUBGHZ).
The SMPS needs a clock to be functional. If for any reason this clock stops, the device may
be destroyed. It can be the case if the HSE is provided by an external clock source
(Figure 22: HSE32 clock sources), with the risk that this clock disappears while the SMPS is
enabled. To avoid this situation, a clock detection is used to, in case of a clock failure, switch
off the SMPS and enable the LDO. The SMPS clock detection is enabled by the sub-GHz
radio SUBGHZ_SMPSC0R.CLKDE. By default, the SMPS clock detection is disabled and
must be enabled before enabling the SMPS. For more details, see Section 4: Sub-GHz
radio (SUBGHZ).
5.1.1
Independent analog peripherals supply
To improve the ADC conversion accuracy and to extend the supply flexibility, the analog
peripherals have an independent power supply that can be separately filtered and shielded
from noise on the PCB.
The analog peripherals voltage supply input is available on a separate VDDA pin.
An isolated supply ground connection is provided on VSSA pin.
The VDDA supply voltage can be different from VDD. The presence of VDDA must be checked
before enabling any of the analog peripherals supplied by VDDA (A/D converter,
comparators, voltage reference buffer).
The VDDA supply can be monitored by the peripheral voltage monitoring, and compared with
a threshold (1.65 V for PVM3). See Section 5.2.3: Peripheral voltage monitoring (PVM) for
more details.
When a single supply is used, VDDA can be externally connected to VDD through the
external filtering circuit in order to ensure a noise-free VDDA reference voltage.
ADC reference voltage
To ensure a better accuracy on low-voltage inputs and outputs, the user can connect a
separate reference voltage lower than VDDA, to VREF+. VREF+ is the highest voltage,
represented by the full scale value, for an analog input (ADC) signal.
VREF+ can be provided either by an external reference of by an internal buffered voltage
reference (VREFBUF).
The internal voltage reference is enabled by setting the ENVR bit in the VREFBUF control
and status register (VREFBUF_CSR). The voltage reference is set to 2.5 V when the VRS
bit is set and to 2.048 V when the VRS bit is cleared. The internal voltage reference can also
provide the voltage to external components through VREF+ pin. Refer to the device
datasheet and to Voltage reference buffer (VREFBUF) for further information.
5.1.2
Battery backup domain
To retain the content of the backup registers and supply the RTC and TAMP functions when
VDD is turned off, the VBAT pin can be connected to an optional backup voltage supplied by
a battery or by another source.
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The VBAT pin powers RTC, TAMP, the LSE oscillator and the PC13 to PC15 I/Os, allowing
RTC and TAMP to operate even when the main power supply is turned off. The switch to the
VBAT supply is controlled by the power-down reset embedded in the reset block.
Warning:
During tRSTTEMPO (temporization at VDD startup) or after a PDR
is detected, the power switch between VBAT and VDD remains
connected to VBAT.
During the startup phase, if VDD is established in less than
tRSTTEMPO (refer to the datasheet for the value of tRSTTEMPO)
and VDD > VBAT + 0.6 V, a current can be injected into VBAT
through an internal diode connected between VDD and the
power switch (VBAT).
If the power supply/battery connected to the VBAT pin cannot
support this current injection, it is strongly recommended to
connect an external low-drop diode between this power
supply and the VBAT pin.
If no external battery is used in the application, it is recommended to connect VBAT
externally to VDD with a 100 nF external ceramic decoupling capacitor.
When the backup domain is supplied by VDD (analog switch connected to VDD), the
following pins are available:
Note:
•
PC13, PC14 and PC15, that can be used as GPIO pins
•
PC13, PC14 and PC15, that can be configured by RTC, TAMP or LSE (refer to
Section 30: Real-time clock (RTC) and Section 31: Tamper and backup registers
(TAMP))
•
PA0/TAMP_IN2 and PB3/TAMP_IN3 when they are configured by the TAMP as tamper
pins
Due to the fact that the analog switch can transfer only a limited amount of current (3 mA),
the use of GPIO PC13 to PC15 in output mode is restricted: the speed must be limited to
2 MHz with a maximum load of 30 pF and these I/Os must not be used as current source
(e.g. to drive a LED).
When the backup domain is supplied by VBAT (analog switch connected to VBAT because
VDD is not present), the following functions are available:
•
PC13, PC14 and PC15 can be controlled only by RTC, TAMP or LSE (refer to
Section 30: Real-time clock (RTC) and Section 31: Tamper and backup registers
(TAMP))
•
PA0/TAMP_IN2 and PB3/TAMP_IN3, when they are configured by the TAMP as
tamper pins
Backup domain access
After a system reset, the backup domain (RTC and TAMP backup registers) is protected
against possible unwanted write accesses. The DBP bit must be set in the PWR control
register 1 (PWR_CR1) to enable access to the backup domain
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VBAT battery charging
When VDD is present, It is possible to charge the external battery on VBAT through an
internal resistance.
The VBAT charging is done either through a 5 kΩ resistor or through a 1.5 kΩ resistor,
depending on the VBRS bit value in the PWR control register 4 (PWR_CR4).
The battery charging is enabled by setting VBE bit in the PWR control register 4
(PWR_CR4), and automatically disabled in VBAT mode.
5.1.3
Voltage regulator
Two embedded linear voltage regulators supply all the digital circuitries, except for the
Standby circuitry and the backup domain. The main regulator (MR) output voltage (VCORE)
can be programmed by software to two different power ranges (range 1 and range 2) to
optimize the consumption depending on the system maximum operating frequency (refer to
Section 6.2.9: Clock source frequency versus voltage scaling and to Section 3.3.4: Read
access latency.
The voltage regulators are always enabled after a reset. Depending on the application
modes, the VCORE supply is provided either by the main regulator or by the low-power
regulator (LPR), as detailed below:
5.1.4
•
In Run, Sleep and Stop 0 modes, both regulators are enabled and the main regulator
(MR) supplies full power to the VCORE domain (core, memories and digital peripherals).
•
In LPRun and LPSleep modes, the main regulator (MR) is off and the low-power
regulator (LPR) supplies reduced power to the VCORE domain, preserving the contents
of the registers and internal SRAM1 and SRAM2.
•
In Stop 1 and Stop 2 modes, the main regulator (MR) is off and the low-power regulator
(LPR) supplies low power to the all or part of the VCORE domain, preserving the
contents of all or part of the registers and of internal SRAM1 and SRAM2.
•
In Standby modes with SRAM2 content preserved (RRS bit set in the PWR control
register 3 (PWR_CR3)), the main regulator (MR) is off and the low-power regulator
(LPR) provides the supply to SRAM2 only. The core and digital peripherals (except
Standby circuitry and backup domain), SRAM1 is powered off.
•
In Standby mode, both regulators (MR and LPR) are powered off. The contents of the
registers and of SRAM1 and SRAM2 is lost except for the Standby circuitry and the
backup domain.
•
In Shutdown mode, both regulators are powered off. When exiting from Shutdown
mode, a power-on reset is generated. Consequently, the contents of the registers and
of both SRAM1 and SRAM2 is lost, except for the backup domain.
Dynamic voltage scaling management
The dynamic voltage scaling is a power management technique that consists in increasing
or decreasing the voltage used for the digital peripherals (VCORE), according to the
application performance and power consumption needs.
Dynamic voltage scaling to increase VCORE is known as “overvolting”. It is used to improve
the device performance.
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Dynamic voltage scaling to decrease VCORE is known as “undervolting”. It is used to save
power, particularly in laptop and other mobile devices where the energy comes from a
battery and is thus limited.
•
range 1: high-performance range
The main regulator provides a typical output voltage at 1.2 V. The system clock
frequency can be up to 64 MHz. The flash memory access time for read access is
minimum. Write and erase operations are possible.
•
range 2: low-power range
The main regulator provides a typical output voltage at 1.0 V. The system clock
frequency can be up to 16 MHz.The flash memory access time for a read access is
increased as compared to range 1. Write and erase operations are possible.
Voltage scaling is selected through the VOS bit in the PWR control register 1 (PWR_CR1).
The sequence to go from range 1 to range 2 is the following:
1.
Reduce the system frequency to a value lower or equal to 16 MHz.
2.
Adjust number of wait states according to new frequency target in range 2 (LATENCY
bits in the FLASH_ACR).
3.
Select range 2 with the VOS bits in the PWR control register 1 (PWR_CR1).
The sequence to go from range 2 to range 1 is detailed below:
1.
Select range 1 in the VOS bits in the PWR control register 1 (PWR_CR1).
2.
Wait until the VOSF flag is cleared in the Power status register 2 (PWR_SR2).
3.
Adjust number of wait states according new frequency target in range 1 (LATENCY bits
in the FLASH_ACR).
4.
Increase the system frequency.
5.2
Power supply supervisor
5.2.1
Power-on reset (POR)/power-down reset (PDR)
/Brownout reset (BOR)
The device has an integrated power-on reset/power-down reset, coupled with a Brownout
reset circuitry.
Five BOR thresholds can be selected through option bytes.
BOR0 level cannot be disabled. Other BOR levels can be enabled by user option. When
enabled, BOR is active in all power modes except in Shutdown.
Reset mode
During power-on, BOR keeps the device under reset until the supply voltage VDD reaches
the specified VBORx threshold. When VDD drops below the selected threshold, a device
reset is generated. When VDD is above the VBORx upper limit, the device reset is released
and the system can start.
For more details on the Brownout reset thresholds, refer to the electrical characteristics
section in the datasheet.
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Figure 16. Brownout reset waveform
VDD
BORHrise
hysteresis
BORHfall
t
nPwr
MS44480V1
1. The reset temporization tRSTTEMPO is present only for the BOR lowest threshold (VBOR0).
5.2.2
Programmable voltage detector (PVD)
The PVD can be used to monitor VDD by comparing it to a threshold selected by the
PLS[2:0] bits in the PWR control register 2 (PWR_CR2).
PVD can also be used to monitor a voltage level on the PVD_IN pin. In this case the voltage
level on PVD_IN is compared to the internal VREFINT level.
PVD is enabled by setting the PVDE bit.
A PVDO flag is available in the Power status register 2 (PWR_SR2) to indicate if VDD or the
voltage level on PVD_IN is higher or lower than the PVD threshold. This event is internally
connected to the EXTI line 16 and can generate an interrupt if enabled through the EXTI
registers.
The PVD output interrupt can be generated when VDD or voltage level on PVD_IN drops
below the PVD threshold and/or when VDD or voltage level on PVD_IN rises above the PVD
threshold depending on EXTI line 16 rising/falling edge configuration. As an example, the
service routine can perform emergency shutdown tasks.
The PVD can be configured to monitor the VDD supply level needed for the sub-GHz radio
operation. For this, the PVD must select its lowest level and PVD and the wake-up must be
enabled in EWPVD. Only a voltage drop below the PVD level generates a wake-up event.
BOR0 level cannot be disabled. The other BOR levels can be enabled by user option. When
enabled, BOR is active in all power modes except in Shutdown.
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Figure 17. PVD thresholds
VDD, or
PVD_IN
PVDrise
hysteresis
PVDfall
t
PVDO
PVDE
SW enable
PDR reset
MS44481V1
5.2.3
Peripheral voltage monitoring (PVM)
Only VDD is monitored by default as it is the only supply required for all system-related
functions. The other supplies (such as VDDA) can be independent from VDD and can be
monitored by the peripheral voltage monitoring (PVM).
Each PVMx is a comparator between a fixed threshold VPVMx and the selected power
supply. PVMOx flags indicate if the independent power supply is higher or lower than the
PVMx threshold. The PVMOx flag is cleared when the supply voltage is above the PVMx
threshold and is set when the supply voltage is below the PVMx threshold.
Each PVM output is connected to an EXTI line and can generate an interrupt if enabled
through the EXTI registers. The PVMx output interrupt is generated when the independent
power supply drops below the PVMx threshold and/or when it rises above the PVMx
threshold, depending on EXTI line rising/falling edge configuration.
Each PVM can remain active in Stop 0, Stop 1 and Stop 2 modes, and the PVM interrupt
can wake up from the Stop modes.
Table 35. PVM features
PVM
Power supply
PVM threshold
EXTI line
PVM1
Not used
-
-
PVM2
Not used
-
-
PVM3
VDDA
VPVM3 (around 1.65 V)
34
PVM4
Not used
-
-
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The independent supply VDDA is not considered as present by default and a logical and
electrical isolation is applied to ignore any information coming from the peripherals supplied
by these dedicated supplies:
•
If VDDA is shorted externally to VDD, the application must assume that VDDA is available
without enabling any peripheral voltage monitoring.
•
If VDDA is independent from VDD, the peripheral voltage monitoring (PVM) can be
enabled to confirm whether the VDDA supply is present or not.
The following sequence must be applied before using any of these analog peripherals:
ADC, DAC, comparators or voltage reference buffer:
1.
If VDDA is independent from VDD:
a)
2.
5.2.4
Enable PVM3 by setting PVME3 bit in the PWR control register 2 (PWR_CR2).
b)
Wait for the PVM3 wake-up time.
c)
Wait until PVMO3 is cleared in the Power status register 2 (PWR_SR2).
d)
Disable the PVM3 for consumption saving (optional).
Enable the analog peripheral. This automatically removes the VDDA isolation.
Radio end of life (EOL)
The radio end-of-life monitor provides information on the VDD supply when it is too low to
operate the sub-GHz radio. When reaching the EOL level, the software must stop all radio
activities in a safe way.
The EOL is enabled by setting the RFEOLEN bit.
The RFEOLF flag is available in Power status register 2 (PWR_SR2) to indicate if VDD
voltage level is below the EOL threshold.
The EOL is only generated when the sub-GHz radio is in Calibrate, Standby or Active mode.
Figure 18. EOL thresholds
VDD
VEOLH
hysteresis
VEOLL
t
RFEOLF
5.3
MSv62619V1
Radio busy management
For correct software handling of the radio busy signal RFBUSY, additional busy control are
included in the PWR controller. This generates a busy mask RFBUSYMS status based on
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the SUBGHZSPI_NSS activity, and masks the RFBUSYS status low time (not busy) after an
SPI command transfer (see the figure below).
Figure 19. Radio busy management
POR
SUBGHZSPI_DATA
SUBGHZSPI_NSS
RFBUSY/RFBUSYS
RFBUSYMS
minimum RFBUSYSM delay
EXTI RFBUSY interrupt (Stop, Run)
WRFBUSYF wakeup (from Standby)
MSv50975V1
At reset, the radio is busy (as signaled by the RFBUSY signal). At this time, the RFBUSYMS
signal provides the same information. Subsequently the radio is woken up by a falling edge
on SUBGHZSPI_NSS. Once the radio is ready to receive a command, RFBUSYS and
RFBUSYMS go low. After reset, the RFBUSYS or RFBUSYMS status can be used to check
that the radio is ready.
For any subsequent command, as soon as the SUBGHZSPI_NSS goes low, the
RFBUSYMS status is set to signal busy radio. RFBUSYMS remains high for at least the
minimum RFBUSYMS delay after the SUBGHZSPI_NSS is set high, or as long as the
RFBUSY signal remains high:
•
When transferring a command with an expected radio busy indication the RFBUSYMS
status must be used to detect the radio busy state.
•
When transferring a command without any expected radio busy indication, there is no
need for checking any busy status. Anew command can be sent even when
RFBUSYMS status indicates busy radio.
When the SUBGHZSPI_NSS is selected to be driven by the LPTIM3_OUT in
PWR_CR1.SUBGHZSPINSSSEL, the RFBYSYMS status is disabled and must not be used
by software.
When in Standby mode, the CPU can be woken up through a WRFBUSYF wake-up flag
when enabled by EWRFBUSY in Section 5.5.3: PWR control register 3 (PWR_CR3).
When in Stop or Run mode, a CPU can be woken up and interrupted by the EXTI
configurable event on the RFBUSY signal, see Section 14.3.1: EXTI wake-up interrupt list.
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Low-power modes
By default, the microcontroller is in Run mode after a system or a power reset. Low-power
modes are available to save power when the CPU does not need to be kept running, for
example when it is waiting for an external event. The user must select the mode giving the
best compromise between consumption, startup time and available wake-up sources.
These low-power modes are detailed below:
•
Sleep mode: CPU clock off, all peripherals including CPU core peripherals (among
them NVIC, SysTick) can run and wake up the CPU when an interrupt or an event
occurs.
•
Low-power run mode (LPRun): when the system clock frequency is reduced below
2 MHz. The code is executed from the SRAM or from the flash memory. The regulator
is in low-power mode to minimize the operating current.
•
Low-power sleep mode (LPSleep): entered from the LPRun mode.
•
Stop 0 mode, and Stop 1 mode: the content of SRAM1, SRAM2 and of all registers is
retained. All clocks in the VCORE domain are stopped. PLL, MSI, HSI16 and HSE32 are
disabled. LSI and LSE can be kept running.
RTC can remain active (Stop mode with RTC, Stop mode without RTC). The sub-GHz
radio may remain active independently from the CPU.
Some peripherals with the wake-up capability can enable HSI16 RC during the Stop
mode to detect their wake-up condition.
Stop 1 offers the largest number of active peripherals and wake-up sources, a smaller
wake-up time but a higher consumption compared with Stop 2.
In Stop 0 mode, the main regulator remains on, resulting in the fastest wake-up time
but with much higher consumption. The active peripherals and wake-up sources are
the same as in Stop 1 mode that uses the low-power regulator.
The system clock, when exiting Stop 0 or Stop 1 mode, can be either MSI up to 48 MHz
or HSI16, depending on the software configuration.
•
Stop 2 mode: part of the VCORE domain is powered off. Only SRAM1, SRAM2, CPU
and some peripherals preserve their contents (see Table 37: Functionalities depending
on system operating mode).
All clocks in the VCORE domain are stopped. PLL, MSI, HSI16 and HSE32 are disabled.
LSI and LSE can be kept running.
RTC can remain active (Stop 2 mode with RTC, Stop 2 mode without RTC). The subGHz radio may also remain active independent from the CPU.
Some peripherals with the wake-up capability can enable HSI16 RC during the Stop 2
mode to detect their wake-up condition (see Table 37: Functionalities depending on
system operating mode).
The system clock when exiting from Stop 2 mode, can be either MSI up to 48 MHz or
HSI16, depending on the software configuration.
•
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Standby mode: VCORE domain is powered off. However, it is possible to preserve the
SRAM2 content as detailed below:
–
Standby mode with SRAM2 retention when the RRS bit is set in the PWR control
register 3 (PWR_CR3). In this case, SRAM2 is supplied by the low-power
regulator.
–
Standby mode when the RRS bit is cleared in the PWR control register 3
(PWR_CR3). In this case the main regulator and the low-power regulator are
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powered off.
All clocks in the VCORE domain are stopped. PLL, MSI, HSI16 and HSE32 are disabled.
LSI and LSE can be kept running.
Th RTC can remain active (Standby mode with RTC, Standby mode without RTC). The
sub-GHz radio and the PVD may also remain active when enabled independent from
the CPU. In Standby mode, the PVD selects its lowest level.
The system clock, when exiting Standby modes, is MSI at 4 MHz.
•
Shutdown mode: VCORE domain is powered off. All clocks in the VCORE domain are
stopped. PLL, MSI, HSI16, LSI and HSE32 are disabled. LSE can be kept running. The
system clock when exiting the Shutdown mode, is MSI at 4 MHz. In this mode, the
supply voltage monitoring is disabled and the product behavior is not guaranteed in
case of a power voltage drop.
In addition, the power consumption in Run mode can be reduced by slowing down the
system clocks, and/or by gating the clocks to the APB and AHB peripherals when they are
unused.
The system operation mode depends on the CPU sub-system operating mode. The system
only enters a low-power mode when the CPU allows it to do so.
The system low-power mode to enter depends on the allowed mode selected by the CPU in
LPMS[2:0] bits in PWR control register 1 (PWR_CR1).
Table 36. Low-power mode summary
Mode name
Entry
WFI or return
Sleep
(Sleep-now or from ISR
Sleep-on-exit) WFE
Wake-up
system clock
Wake-up
source(1)
Any interrupt
Wake-up event
LPRun
Set LPR bit
Clear LPR bit
Any interrupt
LPSleep
Set LPR bit +
WFI or return
from ISR
Set LPR bit +
WFE
Wake-up event
Effect on clocks
Voltage
regulators
MR
LPR
CPU clock OFF
Same as before
entering Sleep mode No effect on other clocks
or analog clock sources
ON
ON
Same as LPRun
clock
None
OFF
ON
Same as before
entering LPSleep
mode
CPU clock OFF
No effect on other clocks
or analog clock sources
OFF
ON
OFF
ON
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Table 36. Low-power mode summary (continued)
Mode name
Wake-up
source(1)
Entry
Wake-up
system clock
Voltage
regulators
Effect on clocks
MR
LPMS = 0b000 +
SLEEPDEEP bit
+ WFI or return
from ISR or WFE
Stop 0
Stop 1
Stop 2
(with I2C3,
LPUART1,
LPTIM1,
SRAM1,
SRAM2)
ON
LPMS = 0b001 + Any EXTI line
SLEEPDEEP bit (configured in the
EXTI registers).
+ WFI or return
from ISR or WFE Specific
peripherals
events
LPMS = 0b010+
SLEEPDEEP bit
+ WFI or return
from ISR or WFE
HSI16 when
STOPWUCK = 1 in
RCC_CFGR.
MSI with the
frequency before
entering the Stop
mode when
STOPWUCK = 0.
All clocks OFF
except HSI16, LSI and
LSE
ON
OFF
LPMS = 0b011+
Wake-up PVD,
Set RRS bit +
Standby (with
SLEEPDEEP bit RFIRQ, wake-up
SRAM2)
RFBUSY, WKUP
+ WFI or return
from ISR or WFE pin edge, RTC
and TAMP event, MSI 4 MHz
LPMS = 0b011 + LSECSS,
Clear RRS bit + external reset in
SLEEPDEEP bit NRST pin,
Standby
+ WFI or return
IWDG reset
from ISR or WFE
Shutdown
LPR
WKUP pin edge,
LPMS = 0b1xx +
RTC and TAMP
SLEEPDEEP bit
event, external
+ WFI or return
reset in NRST
from ISR or WFE
pin
All clocks OFF
except LSI and LSE
OFF OFF
All clocks OFF
except LSE
MSI 4 MHz
OFF OFF
1. Refer to Table 37: Functionalities depending on system operating mode.
Table 37. Functionalities depending on system operating mode(1)
Wake-up capability
-
Wake-up capability
-
Wake-up capability
-
CPU
Y
-
Y
-
R
-
R
-
R
-
-
-
-
-
-
Radio-system (sub-GHz)
O
O
O
O
O
O
O
O
O
O
O
O
-
-
-
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VBAT
-
Peripheral
Wake-up capability
-
Wake-up capability
Shutdo
LPSleep
Standby
LPRun
Stop 2
Sleep
Stop 1
Run
Stop 0
RM0461
Power control (PWR)
Table 37. Functionalities depending on system operating mode(1) (continued)
R
-
R
-
Wake-up capability
-
-
Shutdo
Wake-up capability
R
-
Standby
Wake-up capability
-
Wake-up capability
Wake-up capability
-
Stop 2
-
R
-
R
Flash memory
(up to 256 Kbytes)
Y
O(2) O(3)
Flash memory interface
Y
Y
Y
Y
R
-
R
-
R
-
-
-
-
-
-
SRAM1
Y
(2)
O
Y
O(2)
R
-
R
-
R
-
-
-
-
-
-
SRAM2
Y
O(2)
Y
O(2)
R
-
R
-
R
-
O(4)
-
-
-
-
Backup registers
Y
Y
Y
Y
R
-
R
-
R
-
R
-
R
-
R
Brownout reset (BOR)
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
-
-
-
Programmable voltage
detector (PVD)
O
O
O
O
O
O
O
O
O
O
O(5) O(5)
-
-
-
Peripheral voltage monitor
(PVM3)
O
O
O
O
O
O
O
O
O
O
-
-
-
-
-
DMAx (x = 1, 2)
O
O
O
O
R
-
R
-
-
-
-
-
-
-
-
DMAMUX1
O
O
O
O
R
-
R
-
-
-
-
-
-
-
-
Peripheral
High-speed internal (HSI16)
O
-
(3)
R
O(2)
VBAT
Sleep
LPSleep
Stop 1
Run
LPRun
Stop 0
O
O
O
O(6)
-
O(6)
-
O(6)
-
-
-
-
-
-
(7)
O(7)
O(7)
-
O(7)
-
O(7)
-
O(7)
-
-
-
-
High-speed external (HSE32)
O
O
O
Low-speed internal (LSI)
O
O
O
O
O
-
O
-
O
-
O
-
-
-
-
Low-speed external (LSE)
O
O
O
O
O
-
O
-
O
-
O
-
O
-
O
Multi-speed internal (MSI)
O
O
O
O
O
-
O
-
O
-
-
-
-
-
-
Clock security system (CSS)
O
O
O
O
R
-
R
-
-
-
-
-
-
-
-
Clock security system on LSE
O
O
O
O
O
O
O
O
O
O
O
O
-
-
-
RTC/auto wake-up
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Number of TAMP tamper pins
3
3
3
3
3
O
3
O
3
O
3
O
3
O
3
O
O
(8)
(8)
O
(8)
(8)
-
-
-
-
-
-
-
(8)
O
(8)
(8)
O
(8)
O
(8)
-
-
-
-
-
USARTx (x= 1, 2)
O
O
O
O
(8)
O
O
O
Low-power UART (LPUART1)
O
O
O
O
O
I2Cx (x = 1, 2)
O
O
O
O
O(9) O(9) O(9) O(9)
-
-
-
-
-
-
-
(9)
O(9)
O(9)
O(9)
O(9)
O(9)
-
-
-
-
-
I2C3
O
O
O
O
O
SPI1
O
O
O
O
R
-
R
-
-
-
-
-
-
-
-
SUBGHZSPI
O
O
O
O
R
-
R
-
-
-
-
-
-
-
-
SPI2S2
O
O
O
O
R
-
R
-
-
-
-
-
-
-
-
ADC
O
O
O
O
R
-
R
-
-
-
-
-
-
-
-
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Table 37. Functionalities depending on system operating mode(1) (continued)
Wake-up capability
-
Wake-up capability
-
Wake-up capability
-
DAC
O
O
O
O
R
-
R
-
-
-
-
-
-
-
-
VREFBUF
O
O
O
O
O
-
O
-
R
-
-
-
-
-
-
COMPx (x = 1, 2)
O
O
O
O
O
O
O
O
O
O
-
-
-
-
-
Temperature sensor
O
O
O
O
R
-
R
-
-
-
-
-
-
-
-
Timers (TIMx) x = 1, 2, 16, 17)
O
O
O
O
R
-
R
-
-
-
-
-
-
-
-
LPTIM1
O
O
O
O
O
O
O
O
O
O
-
-
-
-
-
LPTIMx (x = 2, 3)
O
O
O
O
O
O
O
O
-
-
-
-
-
-
-
Independent watchdog
(IWDG)
O
O
O
O
O
O
O
O
O
O
O
O
-
-
-
Window watchdog (WWDG)
O
O
O
O
R
-
R
-
R
-
-
-
-
-
-
SysTick timer
O
O
O
O
R
-
R
-
R
-
-
-
-
-
-
VBAT
-
Peripheral
Wake-up capability
-
Wake-up capability
Shutdo
LPSleep
Standby
LPRun
Stop 2
Sleep
Stop 1
Run
Stop 0
True random number
generator (RNG)
(10)
O
O(1
0)
R
R
R
-
R
-
-
-
-
-
-
-
-
AES hardware accelerator
O
O
O
O
R
-
R
-
-
-
-
-
-
-
-
PKA hardware accelerator
O
O
O
O
R
-
R
-
-
-
-
-
-
-
-
CRC calculation unit
O
O
O
O
R
-
R
-
R
-
-
-
-
-
-
HSEM
O
R
O
R
R
-
R
-
-
-
-
-
-
-
-
EXTI
O
O
O
O
R
O
R
O
R
O
-
-
-
-
-
O
R(11)
GPIOs
O
O
O
O
O
O
O
O
O
3
3
pin (13) pin
s
s(1
(12)
2)
1. Legend: Y = Yes (enable). O = Optional (disable by default and can be enabled by software). R = data retained.
- = Not available. Gray cells indicate wake-up capability.
2. The SRAM clock can be gated on or off.
3. Flash memory can be placed in power-down mode.
4. The SRAM2 content can optionally be retained when the PWR_CR3.RRS bit is set.
5. Only when the sub-GHz radio is active.
6. Some peripherals with wake-up from Stop capability can request HSI16 to be enabled. In this case, HSI16 is woken up by
the peripheral, and only feeds the peripheral that requested it. HSI16 is automatically put off when the peripheral does not
need it anymore.
7. HSE32 can be used by sub-GHz radio system.
8. UART reception is functional in Stop 0 and 1 modes. LPUART1 reception is functional is Stop 0, 1, and 2 modes. LPUART1
generates a wake-up interrupt on Start address match or received frame event.
9. I2Cx (x= 1, 2) address detection is functional in Stop 0 and 1 modes. I2C3 address detection is functional in Stop 0, 1, and
2 modes. I2C3 generates a wake-up interrupt in case of address match.
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10. Voltage scaling range 1 only.
11. I/Os can be configured with internal pull-up, pull-down or floating in Standby mode.
12. The I/Os with wake-up from Standby/Shutdown capability are PA0, PC13 and PB3.
13. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode, but the configuration is lost when
exiting the Shutdown mode.
Relation between MCU and sub-GHz radio operating modes
The CPU and sub-GHz radio have their own operating modes, as defined in the table below.
Table 38. MCU and sub-GHz radio operating modes
CPU operating
mode
Sub-GHz radio operating
mode(1)
Sleep, Calibration, Standby, Active LDO or SMPS regulator active, MCU running in main
(FS, TX, RX)(2)
regulator (MR) mode.
Run, Sleep
Deep-Sleep
LPRun, LPSleep
Sleep, Calibration, Standby, Active LDO or SMPS regulator active, MCU running in low power
(FS, TX, RX)
regulator (LPR) mode.
Deep-Sleep
Stop 1 and Stop 2
LDO and SMPS regulator off, MCU using low power
regulator (LPR) mode.
Sleep, Calibration, Standby, Active LDO or SMPS regulator active, MCU using low power
(FS, TX, RX)
regulator (LPR) mode.
Deep-Sleep
Shutdown
LDO and SMPS regulator off, MCU running in low power
regulator (LPR) mode.
Sleep, Calibration, Standby, Active LDO or SMPS regulator active, MCU running in main
regulator (MR) mode.
(FS, TX, RX)(2)
Stop 0
Standby
Description
LDO and SMPS regulator off, MCU regulator off or on in low
power (LPR) mode(3).
Sleep, Calibration, Standby, Active LDO or SMPS regulator active, MCU regulator off or on in
(FS, TX, RX)
low power (LPR) mode(3).
Deep-Sleep(4)
LDO and SMPS regulator off, MCU regulator off
1. For more details on sub-GHz radio operating modes, see Section 4: Sub-GHz radio (SUBGHZ).
2. In the MCU Run, Sleep and Stop 0 modes, the sub-GHz radio is prevented from entering Deep-Sleep mode.
3. When retaining SRAM2 in Standby mode, the MCU uses the low-power regulator (LPR) mode.
4. When the CPU is in Shutdown mode, the sub-GHz radio cannot be activated and is forced in Deep-Sleep mode.
Debug mode
By default, the debug connection is lost if the application puts the MCU in Stop 0, Stop 1,
Stop 2, Standby or Shutdown mode while the debug features are used. This is because the
CPU core is no longer clocked.
However, by setting some configuration bits in the DBGMCU_CR register, the software can
be debugged even when using the low-power modes extensively. For more details, refer to
Section 36.3.6: Serial-wire and JTAG debug port.
In Stop 0 and 1 modes, the EXTI CDBGPWRUPREQ wake-up event can be used to restart
the CPU clock by the debugger. For more details, refer to Section 14.3.1: EXTI wake-up
interrupt list.
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5.4.1
RM0461
Run mode
Slowing down system clocks
In Run mode, the speed of the system clocks (SYSCLK, HCLK, PCLK) can be reduced by
programming the prescaler registers. These prescalers can also be used to slow down the
peripherals before entering the Sleep mode.
For more details, refer to RCC clock configuration register (RCC_CFGR).
Peripheral clock gating
In Run mode, HCLK and PCLK for individual peripherals and memories can be stopped at
any time to reduce the power consumption.
In Sleep mode, to further reduce the power consumption, the peripheral clocks can be
disabled prior to executing the WFI or WFE instructions.
The peripheral clock gating is controlled by the RCC_AHBxENR and RCC_APBxENR
registers.
Disabling the peripherals clocks in Sleep mode can be performed automatically by resetting
the corresponding bits in the RCC_AHBxSMENR and RCC_APBxSMENR registers.
5.4.2
Low-power run mode (LPRun)
To further reduce the consumption when the system is in Run mode, the regulator can be
configured in low-power mode. In this mode, the HCLK bus frequency must not exceed
2 MHz. HPRE and SHDHPRE must be used to divide the SYSCLK frequency (or MSI not
exceeding 2 MHz must be used) before entering LPRun mode.
Warning:
In LPRun mode, HSE32 cannot be used and must be disabled
before entering LPRun mode.
In LPRun mode HSI16 can be used as kernel clock for peripherals and PLL must be
disabled.
The device only enters LPRun mode once the low-power regulator is ready. The REGLPS
bit can be used to check that the low-power regulator is ready. The REGLPF bit must be
used to know if the device is in LPRun mode.
Refer to the product datasheet for more details on voltage regulator and peripherals
operating conditions.
I/O states in LPRun mode
In LPRun mode, all I/O pins keep the same state as in Run mode.
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Enter LPRun mode
To enter the LPRun mode, proceed as follows (refer to Table 39):
1.
Jump into the SRAM and power down the flash memory by setting the FPDR bit in the
Section 5.5.1: PWR control register 1 (PWR_CR1) (optional).
2.
Disable HSE32 clock.
3.
Decrease the HCLK clock frequencies below 2 MHz.
4.
Force the regulator in low-power mode by setting the LPR bit in the PWR control
register 1 (PWR_CR1).
Exit LPRun mode
To exit the LPRun mode, proceed as follows (refer to Table 39):
1.
Force the regulator in main mode by clearing the LPR bit in the PWR control register 1
(PWR_CR1).
2.
Wait until REGLPF bit is cleared in the Power status register 2 (PWR_SR2).
3.
Increase the HCLK clock frequency (enable HSE32 clock when needed).
Table 39. LPRun
LPRun mode
Description
Mode entry
Decrease the system clock frequency below 2 MHz. LPR = 1.
Mode exit
LPR = 0. Wait until REGLPF = 0. Increase the system clock frequency.
Wake-up latency Regulator wake-up time from low-power mode
5.4.3
Enter low-power mode
The MCU enters low-power mode following one of these events:
•
when MCU executes the WFI (wait for interrupt)
•
when MCU executes WFE (wait for event) instructions
•
on return from ISR when the SLEEPONEXIT bit in the CPU system control register is
set
Low-power mode is only be entered if no interrupt or event is pending.
5.4.4
Exit low-power mode
From Sleep and Stop modes, the CPU exits low-power mode depending on the way the
mode was entered, as detailed below:
•
If the WFI instruction or return from ISR was used to enter the low-power mode, any
peripheral interrupt acknowledged by the NVIC can wake up the device.
•
If the WFE instruction is used to enter the low-power mode, the CPU exits the
low-power mode as soon as an event occurs. The wake-up event can be generated
either by an NVIC IRQ interrupt or by an event.
–
Wake-up generated by an NVIC IRQ with SEVONPEND = 0 in the CPU system
control register, enabling an interrupt in the peripheral control register and
in the NVIC)
When the CPU resumes from WFE, the peripheral interrupt pending bit and the
NVIC peripheral IRQ channel pending bit (in the NVIC interrupt clear pending
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RM0461
register) must be cleared. Only NVIC interrupts with sufficient priority wake up and
interrupt the CPU.
–
Wake-up generated by an NVIC IRQ with SEVONPEND = 1 in the CPU system
control register, enabling an interrupt in the peripheral control register and
optionally in the NVIC
When the CPU resumes from WFE, the peripheral interrupt pending bit and when
enabled the NVIC peripheral IRQ channel pending bit (in the NVIC interrupt clear
pending register) must be cleared. All NVIC interrupts wake up the CPU, even the
disabled ones. Only enabled NVIC interrupts with sufficient priority wake up and
interrupt the CPU.
–
Wake-up generated by an event, configuring an EXTI line in event mode
When the CPU resumes from WFE, it is not necessary to clear the EXTI
peripheral interrupt pending bit or the NVIC IRQ channel pending bit as the
pending bits corresponding to the event line is not set. It may be necessary to
clear the interrupt flag in the peripheral.
From Standby and Shutdown modes, the CPU exits low-power mode through an external
reset (NRST pin), an IWDG reset, a sub-GHz radio IRQ, a PVD event, an edge on the subGHz radio busy signal, a edge on one of the enabled WKUPx pins, an RTC and TAMP
event, or a radio event (for Standby only).
After waking up from Standby or Shutdown mode, the program execution restarts in the
same way as after a reset (boot pin sampling, option bytes loading, reset vector is fetched).
The system mode when it wakes up from low-power mode can be determined from the
C1STOPF, C1STOP2F and C1SBF bits in the PWR extended status and status clear
register (PWR_EXTSCR).
Table 40. CPU wakeup versus system operating mode
Stop
Standby
N/A
5.4.5
C1STOP2F
Run
C1STOPF
System
mode
C1SBF
CPU
0
0
0
Kept running
0
1
0
Wakeup from Stop 0 or 1
0
0
1
Wakeup from Stop 2
1
0
0
Wakeup from Standby
Others
CPU wakeup
Not valid, does not occur
Sleep mode
I/O states in Sleep mode
In Sleep mode, all I/O pins keep the same state as in Run mode.
Enter Sleep mode
The Sleep mode is entered from Run mode according to Enter low-power mode, when the
SLEEPDEEP bit in the CPU system control register is cleared (see Table 41).
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Exit Sleep mode
The MCU exits the Sleep mode (see Table 41) as indicated in Exit low-power mode.
Table 41. Sleep mode
Sleep mode
Description
WFI (wait for interrupt) or WFE (wait for event) while:
– SLEEPDEEP = 0
– No interrupt (for WFI) or event (for WFE) is pending
Refer to the Cortex system control register.
Mode entry
On return from ISR while:
– SLEEPDEEP = 0 and
– SLEEPONEXIT = 1
– No interrupt is pending
Refer to the Cortex system control register.
If WFI or return from ISR was used for entry
Interrupt: refer to Table 78: Vector table
Mode exit
If WFE was used for entry and SEVONPEND = 0:
Wake-up event: refer to Table 81: Wake-up interrupts
If WFE was used for entry and SEVONPEND = 1:
Interrupt even when disabled in NVIC: refer to Table 78: Vector table or
wake-up event: refer to Table 81: Wake-up interrupts
Wake-up latency
5.4.6
None
Low-power sleep mode (LPSleep)
Refer to the product datasheet for more details on voltage regulator and peripherals
operating conditions.
I/O states in LPSleep mode
In LPSleep mode, all I/O pins keep the same state as in Run mode.
Enter LPSleep mode
The LPSleep mode is entered from LPRun mode as described in Section 5.4.3: Enter lowpower mode, when the SLEEPDEEP bit in the Cortex system control register is clear.
Refer to Table 42 for details on how to enter the LPSleep mode.
Exit LPSleep mode
The LPSleep mode is exited as described in Section 5.4.4: Exit low-power mode. When
exiting the LPSleep mode by issuing an interrupt or an event, the MCU is in LPRun mode.
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The table below details how to exit the LPSleep mode.
Table 42. LPSleep
LPSleep mode
Description
LPSleep mode is entered from the LPRun mode.
WFI (wait for interrupt) or WFE (wait for event) while:
– SLEEPDEEP = 0
– No interrupt (for WFI) or event (for WFE) is pending
Refer to the Cortex system control register.
Mode entry
Mode exit
Wake-up latency
5.4.7
LPSleep mode is entered from the LPRun mode.
On return from ISR while:
– SLEEPDEEP = 0 and
– SLEEPONEXIT = 1
– No interrupt is pending
Refer to the Cortex system control register.
If WFI or return from ISR was used for entry
Interrupt: refer to Table 78: Vector table
If WFE was used for entry and SEVONPEND = 0:
Wake-up event: refer to Table 81: Wake-up interrupts
If WFE was used for entry and SEVONPEND = 1:
Interrupt even when disabled in NVIC: refer to Table 78: Vector table
Wake-up event: refer to Table 81: Wake-up interrupts
After exiting the LPSleep mode, the MCU is in LPRun mode.
None
Stop 0 mode
The Stop 0 mode is based on the CPU Deep-Sleep mode combined with the peripheral
clock gating. The voltage regulator is configured in main regulator mode. In Stop 0 mode, all
clocks in the VCORE domain are stopped.PLL, MSI, HSI16 and HSE32 oscillators are
disabled. Some peripherals with the wake-up capability (I2Cx (x = 1, 3), USARTx (x = 1, 2)
and LPUART1) can switch on HSI16 to receive a frame, and switch off HSI16 after receiving
the frame if it is not a wake-up frame. In this case, the HSI16 clock is propagated only to the
peripheral requesting it.
SRAM1, SRAM2 and register contents are preserved.
The BOR is always available in Stop 0 mode. The consumption is increased when
thresholds higher than VBOR0 are used.
The BOR and PDR can be activated to sample periodically the supply voltage. This option
enabled by setting the ULPEN bit of the PWR_CR3 register allows decreasing the current
consumption in this mode, but any drop of the voltage below the operating conditions
between two active periods of the supply detector results in a non-generation of PDR reset.
I/O states in Stop 0 mode
In the Stop 0 mode, all I/O pins keep the same state as in the Run mode.
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Enter Stop 0 mode
The Stop 0 mode is entered according Section 5.4.3, when the SLEEPDEEP bit in the
Cortex system control register is set (see Table 43).
If flash memory programming is ongoing, the Stop 0 mode entry is delayed until the
operation is completed.
If an access to the APB domain is ongoing, the Stop 0 mode entry is delayed until the APB
access is finished.
In Stop 0 mode, the following features can be selected by programming individual control
bits:
•
Independent watchdog (IWDG): the IWDG is started by writing to its key register or by
hardware option. Once started, it cannot be stopped except by a reset. See
Section 28.3: IWDG functional description.
•
Real-time clock (RTC): this is configured by the RTCEN bit in the RCC backup domain
control register (RCC_BDCR).
•
Internal RC oscillator (LSI): this is configured by the LSIxON bit in the RCC
control/status register (RCC_CSR).
•
External 32.768 kHz oscillator (LSE): this is configured by the LSEON bit in the RCC
backup domain control register (RCC_BDCR).
•
Sub-GHz radio activity, as programmed, see Section 4: Sub-GHz radio (SUBGHZ).
•
PVD detection configured in PWR control register 3 (PWR_CR3).
Several peripherals can be used in Stop 0 mode and can add consumption if they are
enabled and clocked by LSI or LSE: LPTIMx (x = 1, 2, 3), I2Cx (x = 1, 2, 3),
USARTx (x = 1, 2), LPUART1.
In Stop 0 mode, when HSIKERON is enabled, the wake-up capabilities of some peripherals
are also available when clocked by HSI16: I2Cx (x = 1, 2, 3), USARTx (x = 1, 2) or
LPUART1.
The comparators can be used in Stop 0 mode, PVM3 and PVD as well. If they are not
needed, they must be disabled by software to save their power consumption.
ADC, temperature sensor and VREFBUF buffer can consume power during the Stop 0
mode, unless they are disabled before entering this mode.
Exit Stop 0 mode
The Stop 0 mode is exited according to what is indicated in Section 5.4.4 (see Table 43 for
details).
When exiting Stop 0 mode by issuing an interrupt or a wake-up event, the HSI16 oscillator is
selected as system clock if the bit STOPWUCK is set in RCC clock configuration register
(RCC_CFGR). The MSI oscillator is selected as system clock if the bit STOPWUCK is
cleared. The wake-up time is shorter when HSI16 is selected as wake-up system clock. The
MSI selection enables a wake-up at higher frequency, up to 48 MHz.
When the voltage regulator operates in low-power mode, an additional startup delay is
incurred when waking up from Stop 0 mode with HSI16. By keeping the internal regulator on
during Stop 0 mode, the consumption is higher but the startup time is reduced.
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When exiting the Stop 0 mode, the MCU is either in Run mode (range 1 or range 2
depending on VOS bit in PWR control register 1 (PWR_CR1)) or in LPRun mode if the bit
LPR is set in the same register.
Table 43. Stop 0 mode
Stop 0
Description
WFI (wait for interrupt) or WFE (wait for event) while:
– SLEEPDEEP bit is set in Cortex system control register
– No interrupt (for WFI) or event (for WFE) is pending
– LPMS = 0b000 in PWR_CR1
Mode entry
On return from ISR while:
– SLEEPDEEP bit is set in Cortex system control register
– SLEEPONEXIT = 1
– No interrupt is pending
– LPMS = 0b000 in PWR_CR1
Note: To enter Stop 0 mode, all EXTI line pending bits (in EXTI pending register
(EXTI_PR1)), and the peripheral flags generating wake-up interrupts must
be cleared. Otherwise, the Stop 0 mode entry procedure is ignored and
program execution continues.
Mode exit
If WFI or return from ISR was used for entry
Any EXTI line configured in Interrupt mode (the corresponding EXTI interrupt
vector must be enabled in the NVIC). The interrupt source can be external
interrupts or peripherals with wake-up capability. Refer to Table 78: Vector table.
If WFE was used for entry and SEVONPEND = 0:
Any EXTI line configured in event mode. Refer to Table 81: Wake-up interrupts.
If WFE was used for entry and SEVONPEND = 1:
Any EXTI line configured in Interrupt mode (even if the corresponding EXTI
interrupt vector is disabled in the NVIC). The interrupt source can be external
interrupts or peripherals with wake-up capability. Refer toTable 78: Vector table.
Wake-up event: refer to Table 81: Wake-up interrupts.
Wake-up latency
5.4.8
Longest wake-up time between: MSI or HSI16 wake-up time and flash memory
wake-up time from Stop 0 mode.
Stop 1 mode
The Stop 1 mode is the same as Stop 0 mode except that the main regulator is off, and only
the low-power regulator is on. Stop 1 mode can be entered from Run mode and from LPRun
mode. The device only enters Stop 1 mode once the low-power regulator is ready. The
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REGLPS bit can be used to check that the low-power regulator is ready (see the table
below).
Table 44. Stop 1 mode
Stop 1
Description
WFI (wait for interrupt) or WFE (wait for event) while:
– SLEEPDEEP bit is set in Cortex system control register
– No interrupt (for WFI) or event (for WFE) is pending
– LPMS = 0b001 in PWR_CR1
Mode entry
On return from ISR while:
– SLEEPDEEP bit is set in Cortex system control register
– SLEEPONEXIT = 1
– No interrupt is pending
– LPMS = 0b001 in PWR_CR1
Note: To enter Stop 1 mode, all EXTI line pending bits (in EXTI pending register
(EXTI_PR1)), and the peripheral flags generating wake-up interrupts must
be cleared. Otherwise, the Stop 1 mode entry procedure is ignored and
program execution continues.
Mode exit
If WFI or return from ISR was used for entry
Any EXTI line configured in Interrupt mode (the corresponding EXTI interrupt
vector must be enabled in the NVIC). The interrupt source can be external
interrupts or peripherals with wake-up capability. Refer to Table 78: Vector
table.
If WFE was used for entry and SEVONPEND = 0:
Any EXTI line configured in event mode. Refer to Section 14.4.1: EXTI
configurable event input wake-up.
If WFE was used for entry and SEVONPEND = 1:
Any EXTI line configured in Interrupt mode (even if the corresponding EXTI
interrupt vector is disabled in the NVIC). The interrupt source can be external
interrupts or peripherals with wake-up capability. Refer to Table 78: Vector
table.
Wake-up event: refer to Table 81: Wake-up interrupts
Wake-up latency
5.4.9
Longest wake-up time between: MSI or HSI16 wake-up time and regulator wakeup time from low-power mode + flash memory wake-up time from Stop 1 mode.
Stop 2 mode
The Stop 2 mode is based on the CPU Deep-Sleep mode combined with peripheral clock
gating and partial power down of the VCORE domain. In Stop 2 mode, all clocks in the VCORE
domain are stopped. PLL, MSI, HSI16 and HSE32 oscillators are disabled. Some of the
logic is powered down except for the CPU and some peripherals with wake-up capability
(I2C3, LPTIM1 and LPUART1), that can switch on the HSI16 to receive a frame, and switch
off HSI16 after receiving the frame if it is not a wake-up frame. In this case, the HSI16 clock
is propagated only to the peripheral requesting it. The Stop 2 mode uses the low-power
regulator, hence the device only enters Stop 2 mode once the low-power regulator is ready.
The REGLPS bit can be used to check that the low-power regulator is ready.
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SRAM1, SRAM2, PWR, flash memory interface, RCC, EXTI, IWDG, WWDG, GPIO, CRC,
SYSCFG, RTC and TAMP contents and registers in the backup domain are also preserved.
The content of all other peripherals is reset and must be reprogrammed.
The BOR is always available in Stop 2 mode. The consumption is increased when
thresholds higher than VBOR0 are used.
The BOR and PDR can be activated to sample periodically the supply voltage. This option
enabled by setting the ULPEN bit of the PWR_CR3 register allows the current consumption
to be decreased in this mode, but any drop of the voltage below the operating conditions
between two active periods of the supply detector, results in a non-generation of PDR reset.
Note:
The comparators, LPUART1 and LPTIM1 outputs are forced to low speed
(OSPEEDy = 0b00) during the Standby mode.
I/O states in Stop 2 mode
In Stop 2 mode, all I/O pins keep the same state as in the Run mode.
Enter Stop 2 mode
The Stop 2 mode is entered as described in Section 5.4.3, when the SLEEPDEEP bit in the
Cortex system control register is set (see Table 45).
Stop 2 mode can only be entered from Run mode. It is not possible to enter Stop 2 mode
from the LPRun mode.
If flash memory programming is ongoing, the Stop 2 mode entry is delayed until the memory
access is finished.
If an access to the APB domain is ongoing, The Stop 2 mode entry is delayed until the APB
access is finished.
Several peripherals can be used in Stop 2 mode and can add consumption if they are
enabled and clocked by LSI or LSE: LPTIM1, I2C3 and LPUART1.
In Stop 2 mode, when HSIKERON is enabled, the wake-up capabilities of some peripherals
are also available when clocked by HSI16: I2C3 or LPUART1.
The comparators can be used in Stop 2 mode, PVM3 and PVD as well. If they are not
needed, they must be disabled by software to save their power consumption.
ADC, temperature sensor and VREFBUF buffer can consume power during Stop 2 mode,
unless they are disabled before entering this mode.
All the peripherals that cannot be used in Stop 2 mode are powered down.
Exit Stop 2 mode
The Stop 2 mode is exited according Section 5.4.4 (see Table 45).
When exiting Stop 2 mode by issuing an interrupt or a wake-up event, the HSI16 oscillator is
selected as system clock if the bit STOPWUCK is set in RCC clock configuration register
(RCC_CFGR). The MSI oscillator is selected as system clock if the bit STOPWUCK is
cleared. The wake-up time is shorter when HSI16 is selected as wake-up system clock. The
MSI selection allows a wake-up at higher frequency, up to 48 MHz,
The STOP2F status flag in the PWR control register 3 (PWR_CR3) indicates that the MCU
was in Stop 2 mode. All non retained registers are reset after wake-up from Stop 2. When
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exiting the Stop 2 mode, the MCU is in Run mode (range 1 or range 2 depending on VOS bit
in PWR_CR1).
Table 45. Stop 2 mode
Stop 2
Description
WFI (wait for interrupt) or WFE (wait for event) while:
– SLEEPDEEP bit is set in Cortex system control register
– No interrupt (for WFI) or event (for WFE) is pending
– LPMS = 0b010 in PWR_CR1
Mode entry
On return from ISR while:
– SLEEPDEEP bit is set in Cortex system control register
– SLEEPONEXIT = 1
– No interrupt is pending
– LPMS = 0b010 in PWR_CR1
Note: To enter Stop 2 mode, all EXTI line pending bits in EXTI pending register
(EXTI_PR1), and EXTI pending register (EXTI_PR2)), and the peripheral
flags generating wake-up interrupts must be cleared. Otherwise, the
Standby mode entry procedure is ignored and program execution
continues.
5.4.10
Mode exit
Any EXTI line configured in Interrupt mode or event mode (regardless if the
corresponding EXTI interrupt vector is enabled in the NVIC). The interrupt source
can be external interrupts or peripherals with wake-up capability. Refer to Table 78:
Vector table.
Wake-up
latency
Longest wake-up time between: MSI or HSI16 wake-up time and regulator wakeup time from Low-power mode + flash wake-up time from Stop 2 mode.
Standby mode
The Standby mode allows the lowest power consumption to be achieved with BOR. It is
based on the CPU Deep-Sleep mode, with the voltage regulators disabled (except when
SRAM2 content is preserved). PLL, HSI16, MSI and HSE32 oscillators are also switched
off.
SRAM1 and register contents are lost except for registers in the backup domain and
Standby circuitry (see Figure 14). SRAM2 content can be preserved if the bit RRS is set in
the PWR control register 3 (PWR_CR3). In this case the low-power regulator is enabled and
provides the supply to SRAM2 only. When the SRAM2 retention is enabled the device only
enters Standby mode once the low-power regulator is ready. The REGLPS bit can be used
to check that the low-power regulator is ready. Immediately exiting from Standby mode with
SRAM2 retention may be delayed until the low-power regulator is ready.
BOR is always available in Standby modes. The consumption is increased when thresholds
higher than VBOR0 are used.
BOR and PDR can be activated to sample periodically the supply voltage. This option
enabled by setting the ULPEN bit of the PWR_CR3 register allows the current consumption
to be decreased in this mode, but any drop of the voltage below the operating conditions
between two active periods of the supply detector results in a non-generation of PDR reset.
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I/O states in Standby mode
In Standby mode, the I/Os can be configured either with a pull-up (refer to PWR_PUCRx
registers (x = A, B, C, H)), or with a pull-down (refer to PWR_PDCRx registers (x = A, B, C,
H)), or can be kept in analog state.
The RTC output on PC13 only is functional in Standby mode. PC14 and PC15 used for LSE
are also functional. Three wake-up pins (WKUPx, x = 1, 2, 3) and the three TAMP tampers
are available.
The sub-GHz radio is functional and PVD can be enabled.
Enter Standby mode
The Standby mode is entered according Section 5.4.3, when the SLEEPDEEP bit in the
Cortex system control register is set (see Table 46 for details).
In Standby mode, the following features can be selected by programming individual control
bits:
•
Independent watchdog (IWDG): the IWDG is started by writing to its key register or by
hardware option. Once started it cannot be stopped except by a reset. See
Section 28.3: IWDG functional description.
•
Real-time clock (RTC): this is configured by the RTCEN bit in the backup domain
control register (RCC_BDCR)
•
Internal RC oscillator (LSI): this is configured by the LSIxON bit in the control/status
register (RCC_CSR).
•
External 32.768 kHz oscillator (LSE): this is configured by the LSEON bit in the backup
domain control register (RCC_BDCR)
•
Sub-GHz radio activity, as programmed, see Section 4: Sub-GHz radio (SUBGHZ).
•
PVD detection configured in PWR control register 3 (PWR_CR3).
Exit Standby mode
The Standby mode is exited according to Section 5.4.4. The SBF status flags (CnSBF) in
the PWR extended status and status clear register (PWR_EXTSCR) indicate that the MCU
was in Standby mode. All registers are reset after wake-up from Standby except for PWR
extended status and status clear register (PWR_EXTSCR).
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Refer to the table below for more details on how to exit Standby mode.
Table 46. Standby mode
Standby
Description
WFI (wait for interrupt) or WFE (wait for event) while:
– SLEEPDEEP bit is set in Cortex system control register
– No interrupt (for WFI) or event (for WFE) is pending
– LPMS = 0b011 in PWR_CR1
– WUFx bits are cleared in power status register 1 (PWR_SR1)
Mode entry
Mode exit
On return from ISR while:
– SLEEPDEEP bit is set in Cortex system control register
– SLEEPONEXIT = 1
– No interrupt is pending
– LPMS = 0b011 in PWR_CR1
– Radio IRQ is cleared in the sub-GHz radio.
– WPVDF, WRFBUSY and WUFx bits are cleared in power status register 1
(PWR_SR1)
– RTC flag corresponding to the chosen wake-up source (RTC Alarm A, RTC
Alarm B, RTC wake-up, synchronous binary counter or timestamp flags) is
cleared
– TAMP flags ITAMPxF and TAMPxF are cleared.
PVD event, RFIRQ interrupt, RFBUSY wake-up event, WKUPx pin edge, RTC
and TAMP event, external reset in NRST pin, IWDG reset, BOR reset
Wake-up latency Reset phase
5.4.11
Shutdown mode
The lowest power consumption can be reached in Shutdown mode. It is based on the
Deep-Sleep mode, with the voltage regulator disabled. The VCORE domain is consequently
powered off. PLL, HSI16, MSI, LSI and HSE32 oscillators are also switched off.
SRAM1, SRAM2 and registers contents are lost except for registers in the backup domain.
BOR is not available in Shutdown mode. No power voltage monitoring is possible in this
mode, therefore the switch to the backup domain is not supported.
I/O states in Shutdown mode
In Shutdown mode, the I/Os can be configured either with a pull-up (refer to PWR_PUCRx
registers (x = A, B, C, H), or with a pull-down (refer to PWR_PDCRx registers (x = A, B, C,
H)), or can be kept in analog state. However this configuration is lost when exiting the
Shutdown mode due to the power-on reset.
The RTC output on PC13 only is functional in Shutdown mode. PC14 and PC15 used for
LSE are also functional. Three wake-up pins (WKUPx, x = 1, 2, 3) and the three TAMP
tampers are available.
Enter Shutdown mode
The Shutdown mode is entered according Section 5.4.3, when the SLEEPDEEP bit in the
Cortex system control register is set (see Table 47 for details).
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In Shutdown mode, the following features can be selected by programming individual
control bits:
•
Caution:
Real-time clock (RTC): this is configured by the RTCEN bit in the backup domain
control register (RCC_BDCR).
In case of VDD power-down, the RTC content is lost.
•
External 32.768 kHz oscillator (LSE): this is configured by the LSEON bit in the backup
domain control register (RCC_BDCR)
Exit Shutdown mode
The Shutdown mode is exited according Section 5.4.4. A power-on reset occurs when
exiting from Shutdown mode. All registers (except for the ones in the backup domain) are
reset after wake-up from Shutdown.
Refer to the table below for more details on how to exit Shutdown mode.
Table 47. Shutdown mode
Shutdown mode
Description
WFI (wait for interrupt) or WFE (wait for event) while:
– SLEEPDEEP bit is set in Cortex system control register
– No interrupt (for WFI) or event (for WFE) is pending
– LPMS = 0b1xx in PWR_CR1
– WUFx bits are cleared in power status register 1 (PWR_SR1)
Mode entry
5.4.12
On return from ISR while:
– SLEEPDEEP bit is set in Cortex system control register
– SLEEPONEXT = 1
– No interrupt is pending
– LPMS = 0b1xx in PWR_CR1
– Radio IRQ is cleared in the sub-GHz radio.
– WPVDF, WRFBUSY and WUFx bits are cleared in power status register 1
(PWR_SR1)
– The RTC flag corresponding to the chosen wake-up source (RTC Alarm A,
RTC Alarm B, RTC wake-up, synchronous binary counter or timestamp
flags) is cleared
– TAMP flags ITAMPxF and TAMPxF are cleared.
Mode exit
WKUPx pin edge, RTC and TAMP event, external reset in NRST pin
Wake-up latency
Reset phase
Auto-wake-up from low-power mode
The RTC can be used to wake up the MCU from low-power mode without depending on an
external interrupt (auto-wake-up mode). The RTC provides a programmable time base for
waking up from Stop (0, 1 or 2) or Standby mode at regular intervals. For this purpose, the
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following alternative RTC clock sources can be selected by programming the RTCSEL[1:0]
bits in the RCC backup domain control register (RCC_BDCR):
•
Low-power 32.768 kHz external crystal oscillator (LSE OSC)
This clock source provides a precise time base with very low-power consumption.
•
Low-power internal RC oscillator (LSI)
This clock source has the advantage of saving the cost of the 32.768 kHz crystal. This
internal RC oscillator is designed to add minimum power consumption.
To wake up from Stop mode with an RTC alarm event, it is necessary to:
•
Configure the EXTI line 18 to be sensitive to rising edge.
•
Configure the RTC to generate the RTC alarm.
To wake up from Standby mode, there is no need to configure the EXTI line 18.
To wake up from Stop mode with an RTC wake-up event, it is necessary to:
•
Configure the EXTI line 20 to be sensitive to rising edge.
•
Configure the RTC to generate the RTC alarm.
To wake up from Standby mode, there is no need to configure the EXTI line 20.
5.5
PWR registers
The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).
5.5.1
PWR control register 1 (PWR_CR1)
This register is reset after wake-up from Standby mode, except for bit field LPMS[2:0].
Access: additional APB cycles are used to access this register versus those used for a
standard APB access (three for a write and two for a read).
Address offset: 0x000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
LPR
Res.
Res.
Res.
VOS[1:0]
DBP
Res.
Res.
FPDS
FPDR
SUBGHZSPINSSSEL
Reset value: 0x0000 0200
rw
rw
rw
rw
rw
rw
rw
LPMS[2:0]
rw
rw
rw
Bits 31:15 Reserved, must be kept at reset value.
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Bit 14 LPR: LPRun
When this bit is set, the supply mode is switched from main regulator mode (MR) to lowpower regulator mode (LPR).
Note: Stop 2 mode cannot be entered when LPR bit is set. Stop 1 is entered instead.
Bits 13:11 Reserved, must be kept at reset value.
Bits 10:9 VOS[1:0]: Voltage scaling range selection
Previous voltage range change must be completed before chaining voltage range again.
0b00: Cannot be written (forbidden by hardware)
0b01: Range 1
0b10: Range 2
0b11: Cannot be written (forbidden by hardware)
Bit 8 DBP: Disable backup domain write protection
In reset state, the RTC and backup registers are protected against parasitic write access.
This bit must be set to enable write access to these registers.
0: Access to RTC and backup registers disabled
1: Access to RTC and backup registers enabled
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 FPDS: Flash memory power-down mode during LPSleep
This bit selects whether the flash memory is in Power-down mode or Idle mode when the
CPU is in Sleep mode. flash memory is only set in power-down mode when the system is in
LPSleep mode.
0: Flash memory in Idle mode when system is in LPSleep mode
1: Flash memory in Power-down mode when system is in LPSleep mode
Bit 4 FPDR: Flash memory power-down mode during LPRun
This bit can only be written to 1 after unlocking this register bit, by first writing (code 0xC1B0)
into this register (when writing the code, the register bits are not updated). Selects whether
the flash memory is in power-down mode or Idle mode when in LPRun mode. (flash memory
can only be in power-down mode when code is executed from SRAM). Flash memory is only
set in power-down mode when the system is in LPRun mode.
0: Flash memory in Idle mode when system is in LPRun mode
1: Flash memory in Power-down mode when system is in LPRun mode
Bit 3 SUBGHZSPINSSSEL: sub-GHz SPI NSS source select
This bit is set and cleared by software.
0: sub-GHz SPI NSS signal driven from PWR_SUBGHZSPICR.NSS (RFBUSYMS
functionality enabled)
1: sub-GHz SPI NSS signal driven from LPTIM3_OUT (RFBUSYMS functionality disabled)
Bits 2:0 LPMS[2:0]: Low-power mode selection
These bits are not reset when exiting Standby mode.
These bits select the low-power mode allowed when CPU enters the Deep -Sleep mode.
000: Stop 0 mode
001: Stop 1 mode
010: Stop 2 mode
011: Standby mode
1xx: Shutdown mode
Note: If LPR bit is set, Stop 2 mode cannot be selected and Stop 1 mode must be entered
instead of Stop 2.
In Standby mode, SRAM2 is preserved, depending on RRS bit configuration in
PWR_CR3.
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5.5.2
PWR control register 2 (PWR_CR2)
This register is reset when exiting the Standby mode.
Address offset: 0x004
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
3
2
1
15
14
13
12
11
10
9
8
7
6
5
4
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PVME3
Res.
Res.
rw
PLS[2:0]
rw
rw
0
PVDE
rw
rw
Bits 31:7 Reserved, must be kept at reset value.
Bit 6 PVME3: Peripheral voltage monitoring 3 enable: VDDA versus 1.62 V
0: PVM3 (VDDA monitoring versus 1.62 V threshold) disable.
1: PVM3 (VDDA monitoring versus 1.62 V threshold) enable.
Bits 5:4 Reserved, must be kept at reset value.
Bits 3:1 PLS[2:0]: Programmable voltage detector level selection.
These bits select the voltage threshold detected by the programmable voltage detector:
000: VPVD0 around 2.0 V
001: VPVD1 around 2.2 V
010: VPVD2 around 2.4 V
011: VPVD3 around 2.5 V
100: VPVD4 around 2.6 V
101: VPVD5 around 2.8 V
110: VPVD6 around 2.9 V
111: External input analog voltage PVD_IN (compared internally to VREFINT)
Note: These bits are write-protected when the bit PVDL (PVD Lock) is set in the
SYSCFG_CBR register.
These bits are reset only by a system reset.
Bit 0 PVDE: Programmable voltage detector enable
0: Programmable voltage detector disabled
1: Programmable voltage detector enabled
Note: This bit is write-protected when the bit PVDL (PVD Lock) is set in the SYSCFG_CBR
register.
This bit is reset only by a system reset.
5.5.3
PWR control register 3 (PWR_CR3)
This register is not reset when exiting Standby modes.
Access: additional APB cycles are needed to access this register versus those needed for a
standard APB access (three for a write and two for a read).
Address offset: 0x008
Reset value: 0x0000 8000
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31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
EIWUL
Res.
Res.
EWRFBUSY
APC
RRS
EWPVD
ULPEN
Res.
Res.
Res.
Res.
EWUP3
EWUP2
EWUP1
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EWRFIRQ
Power control (PWR)
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:16 Reserved, must be kept at reset value.
Bit 15 EIWUL: internal wake-up line for CPU enable
0: Internal wake-up line interrupt to CPU disabled
1: Internal wake-up line interrupt to CPU enabled
Bit 14 Reserved, must be kept at reset value.
Bit 13 EWRFIRQ: radio IRQ[2:0] wake-up for CPU enable
When this bit is set, the radio IRQ[2:0] is enabled and triggers a wake-up from Standby event
to CPU.
Bit 12 Reserved, must be kept at reset value.
Bit 11 EWRFBUSY: radio busy wake-up from Standby for CPU enable
When this bit is set, the radio busy is enabled and triggers a wake-up from Standby event to
CPUwhen a rising or a falling edge occurs. The active edge is configured via the
WRFBUSYP bit in the PWR control register 4 (PWR_CR4).
Bit 10 APC: Apply pull-up and pull-down configuration from CPU
When this bit is set, the I/O pull-up and pull-down configurations defined in the PWR_PUCRx
and PWR_PDCRx registers are applied. When this bit is cleared, the PWR_PUCRx and
PWR_PDCRx registers are not applied to the I/Os.
Bit 9 RRS: SRAM2 retention in Standby mode
0: SRAM2 powered off in Standby mode (SRAM2 content lost)
1: SRAM2 powered by the low-power regulator in Standby mode (SRAM2 content kept)
Bit 8 EWPVD: PVD and wake-up for CPU enable (when sub-GHz radio in active state)
This bit is set and reset by software.
When this bit is set, the PVD is enabled while the sub-GHz radio is active and triggers an
interrupt and wake-up from Stop, Standby event to CPU, when the voltage level drops below
the PVD threshold level.
0: PVD not enabled by the sub-GHz radio active state
1: PVD enabled while the sub-GHz radio is active
Bit 7 ULPEN: Ultra-low-power enable
Enable/disable periodical sampling of supply voltage in Stop and Standby modes for
detecting condition of PDR and BOR reset.
0: Disable (the supply voltage is monitored continuously)
1: Enable, when set, the supply voltage is sampled for PDR/BOR reset condition only
periodically and not continuously, in order to save power. The sampling period is typically
12 ms, but is strongly linked to the temperature (the period decreases when the temperature
increases).
Caution: When enabled and if the supply voltage drops below the minimum operating
condition between two supply voltage samples, the reset condition is missed and no
reset is generated.
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RM0461
Power control (PWR)
Bits 6:3 Reserved, must be kept at reset value.
Bit 2 EWUP3: Wake-up pin WKUP3 for CPUenable
When this bit is set, the external wake-up pin WKUP3 is enabled and triggers an interrupt
and wake-up from Stop, Standby or Shutdown event when a rising or a falling edge occurs to
CPU. The active edge is configured via the WP3 bit in the PWR control register 4
(PWR_CR4).
Bit 1 EWUP2: Wake-up pin WKUP2 for CPUenable
When this bit is set, the external wake-up pin WKUP2 is enabled and triggers an interrupt
and wake-up from Stop, Standby or Shutdown event when a rising or a falling edge occurs to
CPU. The active edge is configured via the WP2 bit in the PWR control register 4
(PWR_CR4).
Bit 0 EWUP1: Wake-up pin WKUP1 for CPU enable
When this bit is set, the external wake-up pin WKUP1 is enabled and triggers an interrupt
and wake-up from Stop, Standby or Shutdown event when a rising or a falling edge occurs to
CPU. The active edge is configured via the WP1 bit in the PWR control register 4
(PWR_CR4).
5.5.4
PWR control register 4 (PWR_CR4)
This register is not reset when exiting Standby modes.
Access: additional APB cycles are needed to access this register versus those needed for a
standard APB access (three for a write and two for a read).
Address offset: 0x00C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
WRFBUSYP
Reset value: 0x0000 0000
Res.
VBRS
VBE
Res.
Res.
Res.
Res.
Res.
WP3
WP2
WP1
rw
rw
rw
rw
rw
rw
Bits 31:12 Reserved, must be kept at reset value.
Bit 11 WRFBUSYP: Wake-up radio busy polarity
This bit defines the polarity used for an event detection on radio busy signal.
0: Detection on high level (rising edge)
1: Detection on low level (falling edge)
Bit 10 Reserved, must be kept at reset value.
Bit 9 VBRS: VBAT battery charging resistor selection
0: VBAT charging through a 5 kΩ resistor
1: VBAT charging through a 1.5 kΩ resistor
Bit 8 VBE: VBAT battery charging enable
0: VBAT battery charging disabled
1: VBAT battery charging enabled
RM0461 Rev 10
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Power control (PWR)
RM0461
Bits 7:3 Reserved, must be kept at reset value.
Bit 2 WP3: Wake-up pin WKUP3 polarity
This bit defines the polarity used for an event detection on external wake-up pin, WKUP3
0: Detection on high level (rising edge)
1: Detection on low level (falling edge)
Bit 1 WP2: Wake-up pin WKUP2 polarity
This bit defines the polarity used for an event detection on external wake-up pin, WKUP2
0: Detection on high level (rising edge)
1: Detection on low level (falling edge)
Bit 0 WP1: Wake-up pin WKUP1 polarity
This bit defines the polarity used for an event detection on external wake-up pin, WKUP1
0: Detection on high level (rising edge)
1: Detection on low level (falling edge)
5.5.5
PWR status register 1 (PWR_SR1)
This register is not reset when exiting Standby modes.
Access: two additional APB cycles are needed to read this register versus a standard APB
read.
Address offset: 0x010
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
WUFI
Res.
Res.
Res.
WRFBUSYF
Res.
Res.
WPVDF
Reset value: 0x0000 0000
Res.
Res.
Res.
Res.
Res.
WUF3
WUF2
WUF1
r
r
r
r
r
r
Bits 31:16 Reserved, must be kept at reset value.
Bit 15 WUFI: Internal wake-up interrupt flag
This bit is set when a wake-up is detected on the internal wake-up line. It is cleared when all
internal wake-up sources are cleared.
Bits 14:12 Reserved, must be kept at reset value.
Bit 11 WRFBUSYF: Radio busy wake-up flag
This bit is set when a wake-up event is detected on radio busy. It is cleared by writing ‘1’ in
the CWRFBUSYF bit of the PWR_SCR register.
Bits 10:9 Reserved, must be kept at reset value.
Bit 8 WPVDF: Wake-up PVD flag
This bit is set when a wake-up event is detected on PVD. It is cleared by writing ‘1’ in the
CWPVDF bit of the PWR_SCR register.
Bits 7:3 Reserved, must be kept at reset value.
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RM0461
Power control (PWR)
Bit 2 WUF3: Wake-up flag 3
This bit is set when a wake-up event is detected on wake-up pin, WKUP3. It is cleared by
writing 1 in the CWUF3 bit of the PWR status clear register (PWR_SCR).
Bit 1 WUF2: Wake-up flag 2
This bit is set when a wake-up event is detected on wake-up pin, WKUP2. It is cleared by
writing 1 in the CWUF2 bit of the PWR status clear register (PWR_SCR).
Bit 0 WUF1: Wake-up flag 1
This bit is set when a wake-up event is detected on wake-up pin, WKUP1. It is cleared by
writing 1 in the CWUF1 bit of the PWR status clear register (PWR_SCR).
5.5.6
Power status register 2 (PWR_SR2)
This register is partially reset when exiting Standby/Shutdown modes.
Address offset: 0x014
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
PVMO3
Res.
Res.
PVDO
VOSF
REGLPF
REGLPS
FLASHRDY
REGMRS
RFEOLF
LDORDY
SMPSRDY
RFBUSYMS
RFBUSYS
Reset value: 0x0000 0000
Res.
r
r
r
r
r
r
r
r
r
r
r
r
Bits 31:15 Reserved, must be kept at reset value.
Bit 14 PVMO3: Peripheral voltage monitoring output: VDDA versus 1.62 V
0: VDDA voltage above PVM3 threshold (around 1.62 V)
1: VDDA voltage below PVM3 threshold (around 1.62 V)
Note: PVMO3 is cleared when PVM3 is disabled (PVME3 = 0). After enabling PVM3, the
PVM3 output is valid after the PVM3 wake-up time.
Bits 13:12 Reserved, must be kept at reset value.
Bit 11 PVDO: Programmable voltage detector output
0: VDD or voltage level on PVD_IN above the selected PVD threshold
1: VDD or voltage level on PVD_IN below the selected PVD threshold
Bit 10 VOSF: Voltage scaling flag
A delay is required for the internal regulator to be ready after the voltage scaling has been
changed. VOSF indicates that the regulator reached the voltage level defined with VOS bits
of the PWR control register 1 (PWR_CR1).
0: regulator ready in the selected voltage range
1: regulator output voltage changed to the required voltage level
RM0461 Rev 10
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Power control (PWR)
RM0461
Bit 9 REGLPF: low-power regulator flag
This bit is set by hardware when the MCU is in LPRun mode. When the MCU exits from the
LPRun mode, this bit remains at 1 until the main regulator is ready. A polling on this bit must
be done before increasing the product frequency.
This bit is cleared by hardware when the main regulator is ready.
0: main regulator (MR) ready and used
1: low-power regulator (LPR) used
Bit 8 REGLPS: low-power regulator started (ready)
This bit provides the information whether the low-power regulator is ready after a power-on
reset or a Standby/Shutdown. If the Standby mode is entered while REGLPS bit is still
cleared (“backup” SRAM2 disabled), the wake-up time from Standby mode may be
increased.
0: LPR not ready
1: LPR ready
Bit 7 FLASHRDY: Flash memory ready
This bit is set by hardware when the flash memory can be accessed by software after a
software controlled flash power down (in LPRun mode). This bit is cleared by hardware when
the flash memory is powered down.
0: Flash memory not ready to be accessed
1: Flash memory ready to be accessed
Bit 6 REGMRS: Main regulator status
This bit is set by hardware when the main regulator is supplied by the LDO or SMPS when
enabled. When this bit is cleared the main regulator is directly supplied from VDD.
0: main regulator supplied directly from VDD
1: main regulator supplied through LDO or SMPS
Bit 5 RFEOLF: Radio end-of-life flag
When enabled by RFEOLEBN, this bit indicates that the supply voltage reached the radio
end-of-life operating low level.
0: Supply voltage below radio end-of-life operating low level
1: Supply voltage above radio end-of-life operating low level
Bit 4 LDORDY: LDO ready flag
This bit indicates that the LDO is ready.
0: LDO not ready or off
1: LDO ready
Bit 3 SMPSRDY: SMPS ready flag
This bit indicates that the SMPS step-down converter is ready.
0: SMPS step-down converter not ready or off
1: SMPS step-down converter ready
Bit 2 RFBUSYMS: Radio busy masked signal status
This bit indicates the actual status of the radio busy masked signal.
0: radio busy masked signal low (not busy)
1: radio busy masked signal high (busy)
Bit 1 RFBUSYS: Radio busy signal status
This bit indicates the actual status of the radio busy signal.
0: radio busy signal low (not busy)
1: radio busy signal high (busy)
Bit 0 Reserved, must be kept at reset value.
216/1290
RM0461 Rev 10
RM0461
Power control (PWR)
5.5.7
PWR status clear register (PWR_SCR)
Access: three additional APB cycles are needed to write this register versus a standard APB
write.
Address offset: 0x018
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
CWRFBUSYF
Res.
Res.
CWPVDF
Res.
Res.
Res.
Res.
Res.
CWUF3
CWUF2
CWUF1
Reset value: 0x0000 0000
w
w
w
w
w
Bits 31:12 Reserved, must be kept at reset value.
Bit 11 CWRFBUSYF: Clear wake-up radio busy flag
Setting this bit clears the WRFBUSYF flag in the PWR_SR1. This bit is always read 0.
Bits 10:9 Reserved, must be kept at reset value.
Bit 8 CWPVDF: Clear wake-up PVD interrupt flag
Setting this bit clears the WPVDF flag in the PWR_SR1. This bit is always read as 0.
Bits 7:3 Reserved, must be kept at reset value.
Bit 2 CWUF3: Clear wake-up flag 3
Setting this bit clears the WUF3 flag in the PWR_SR1 register. This bit is always read as 0.
Bit 1 CWUF2: Clear wake-up flag 2
Setting this bit clears the WUF2 flag in the PWR_SR1 register. This bit is always read as 0.
Bit 0 CWUF1: Clear wake-up flag 1
Setting this bit clears the WUF1 flag in the PWR_SR1 register. This bit is always read as 0.
5.5.8
PWR control register 5 (PWR_CR5)
This register is not reset when exiting Standby modes.
Access: three additional APB cycles are needed to write this register versus a standard APB
write.
Address offset: 0x01C
Reset value: 0x0000 0000
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31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RFEOLEN
RM0461
SMPSEN
Power control (PWR)
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
rw
rw
Bits 31:16 Reserved, must be kept at reset value.
Bit 15 SMPSEN: SMPS step-down converter enable
This bit enables the SMPS step-down converter.
0: SMPS step-down converter SMPS mode disabled (LDO mode enabled)
1: SMPS step-down converter SMPS mode enabled
Caution: Before enabling the SMPS, the SMPS clock detection must be enabled
in SUBGHZ_SMPSC0R.CLKDE, if the application uses an external HSE clock
source (not coming from XO or TCXO but from another device).
Bit 14 RFEOLEN: sub-GHz radio end-of-life detector enable
0: Radio end-of-life detector disabled
1: Radio end-of-life detector enabled
Bits 13:0 Reserved, must be kept at reset value.
5.5.9
PWR port A pull-up control register (PWR_PUCRA)
This register is not reset when exiting Standby modes.
Access: additional APB cycles are needed to access this register versus those needed for a
standard APB access (three for a write and two for a read).
Address offset: 0x020
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PU15
PU14
PU13
PU12
PU11
PU10
PU9
PU8
PU7
PU6
PU5
PU4
PU3
PU2
PU1
PU0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 PU[15:0]: Port PA[y] pull-up bit y (y = 0 to 15)
When set, each bit activates the pull-up on PA[y] when both APC bits are set in PWR control
register 3 (PWR_CR3). The pull-up is not activated if the corresponding PA[y] bit is also set.
218/1290
RM0461 Rev 10
RM0461
Power control (PWR)
5.5.10
PWR port A pull-down control register (PWR_PDCRA)
This register is not reset when exiting Standby modes.
Access: additional APB cycles are needed to access this register versus those needed for a
standard APB access (three for a write and two for a read).
Address offset: 0x024
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PD15
PD14
PD13
PD12
PD11
PD10
PD9
PD8
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 PD[15:0]: Port PA[y] pull-down (y = 0 to 15)
When set, each bit activates the pull-down on PA[y] when both APC bits are set in PWR
control register 3 (PWR_CR3).
5.5.11
PWR port B pull-up control register (PWR_PUCRB)
This register is not reset when exiting Standby modes.
Access: additional APB cycles are needed to access this register versus those needed for a
standard APB access (three for a write and two for a read).
Address offset: 0x028
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PU15
PU14
PU13
PU12
PU11
PU10
PU9
PU8
PU7
PU6
PU5
PU4
PU3
PU2
PU1
PU0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 PU[15:0]: Port PB[y] pull-up (y = 0 to 15)
When set, each bit activates the pull-up on PB[y] when both APC bits are set in PWR control
register 3 (PWR_CR3). The pull-up is not activated if the corresponding PB[y] bit is also set.
RM0461 Rev 10
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Power control (PWR)
5.5.12
RM0461
PWR port B pull-down control register (PWR_PDCRB)
This register is not reset when exiting Standby modes.
Access: additional APB cycles are needed to access this register versus those needed for a
standard APB access (three for a write and two for a read).
Address offset: 0x02C
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PD15
PD14
PD13
PD12
PD11
PD10
PD9
PD8
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 PD[15:0]: Port PB[y] pull-down (y = 0 to 15)
When set, each bit activates the pull-down on PB[y] when both APC bits are set in PWR
control register 3 (PWR_CR3).
5.5.13
PWR port C pull-up control register (PWR_PUCRC)
This register is not reset when exiting Standby modes.
Access: additional APB cycles are needed to access this register versus those needed for a
standard APB access (three for a write and two for a read).
Address offset: 0x030
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PU15
PU14
PU13
Res.
Res.
Res.
Res.
Res.
Res.
PU6
PU5
PU4
PU3
PU2
PU1
PU0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:13 PU[15:13]: Port PC[y] pull-up (y = 13 to 15)
When set, each bit activates the pull-up on PC[y] when both APC bits are set in PWR control
register 3 (PWR_CR3). The pull-up is not activated if the corresponding PC[y] bit is also set.
Bits 12:7 Reserved, must be kept at reset value.
Bits 6:0 PU[6:0]: Port PC[y] pull-up (y = 0 to 6)
When set, each bit activates the pull-up on PC[y] when both APC bits are set in PWR control
register 3 (PWR_CR3). The pull-up is not activated if the corresponding PC[y] bit is also set.
220/1290
RM0461 Rev 10
RM0461
Power control (PWR)
5.5.14
PWR port C pull-down control register (PWR_PDCRC)
This register is not reset when exiting Standby modes.
Access: additional APB cycles are needed to access this register versus those needed for a
standard APB access (three for a write and two for a read).
Address offset: 0x034
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PD15
PD14
PD13
Res.
Res.
Res.
Res.
Res.
Res.
PD6
PD5
PD4
PD3
PD2
PD1
PD0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:13 PD[15:13]: Port PC[y] pull-down (y = 13 to 15)
When set, each bit activates the pull-down on PC[y] when both APC bits are set in PWR
control register 3 (PWR_CR3).
Bits 12:7 Reserved, must be kept at reset value.
Bits 6:0 PD[6:0]: Port PC[y] pull-down bit y (y = 0 to 6)
When set, each bit activates the pull-down on PC[y] when both APC bits are set in .
5.5.15
PWR port H pull-up control register (PWR_PUCRH)
This register is not reset when exiting Standby modes and with PWRRST bit in the
RCC_APB1RSTR1 register.
Access: additional APB cycles are needed to access this register versus those needed for a
standard APB access (three for a write and two for a read).
Address offset: 0x058
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PU3
Res.
Res.
Res.
rw
Bits 31:4 Reserved, must be kept at reset value.
Bit 3 PU3: Port PH[3] pull-up
When set, this bit activates the pull-up on PH[3] when both APC bit are set in PWR control
register 3 (PWR_CR3). The pull-up is not activated if the corresponding PH[3] bit is also set.
Bits 2:0 Reserved, must be kept at reset value.
RM0461 Rev 10
221/1290
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Power control (PWR)
5.5.16
RM0461
PWR port H pull-down control register (PWR_PDCRH)
This register is not reset when exiting Standby modes and with PWRRST bit in the
RCC_APB1RSTR1 register.
Access: additional APB cycles are needed to access this register versus those needed for a
standard APB access (three for a write and two for a read).
Address offset: 0x05C
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PD3
Res.
Res.
Res.
rw
Bits 31:4 Reserved, must be kept at reset value.
Bit 3 PD3: Port PH[3] pull-down
When set, this bit activates the pull-down on PH[3] when both APC bits are set in PWR
control register 3 (PWR_CR3).
Bits 2:0 Reserved, must be kept at reset value.
5.5.17
PWR extended status and status clear register (PWR_EXTSCR)
Access: three additional APB cycles are needed to write this register versus a standard APB
write.
Address offset: 0x088
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
C1DS
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
C1CSS
F
r
C1STO C1STO
C1SBF
PF
P2F
r
r
r
Bits 31:15 Reserved, must be kept at reset value.
Bit 14 C1DS: CPU Deep-Sleep mode
This bit is set by hardware when CPU enters Deep-Sleep mode.
0: CPU is running or in sleep
1: CPU is in Deep-Sleep
Bits 13:11 Reserved, must be kept at reset value.
222/1290
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RM0461
Power control (PWR)
Bit 10 C1STOPF: System Stop 0, 1 flag for CPU (all core states retained)
This bit is set by hardware and cleared only by any reset or by setting C1CSSF bit.
0: System has not been in Stop 0 or 1 mode
1: System has been in Stop 0 or 1 mode.
Bit 9 C1STOP2F: System Stop 2 flag for CPU (partial core states retained)
This bit is set by hardware and cleared only by any reset or by setting C1CSSF bit.
0: System has not been in Stop 2 mode
1: System has been in Stop 2 mode.
Bit 8 C1SBF: System Standby flag for CPU (no core states retained)
This bit is set by hardware and cleared only by a POR reset or by setting C1CSSF bit.
0: System has not been in Standby mode
1: System has been in Standby mode.
Bits 7:1 Reserved, must be kept at reset value.
Bit 0 C1CSSF: Clear CPU Stop Standby flags
Setting this bit clears the C1STOPF and C1SBF bits.
5.5.18
PWR sub-GHz SPI control register (PWR_SUBGHZSPICR)
Address offset: 0x090
Reset value: 0x0000 8000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NSS
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
rw
Bits 31:16 Reserved, must be kept at reset value.
Bit 15 NSS: sub-GHz SPI NSS control
This bit is set and cleared by software and is used to control the sub-GHz SPI NSS level from
software.
0: sub-GHz SPI NSS signal at level low
1: sub-GHz SPI NSS signal is at level high
Bits 14:0 Reserved, must be kept at reset value.
RM0461 Rev 10
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RM0461 Rev 10
PD14
PD13
PD12
PD11
PD10
PD9
PD8
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PU13
PU12
PU11
PU10
PU9
PU8
PU7
PU6
PU5
PU4
PU3
PU2
PU1
PU0
Reset value
PU14
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PU13
PU12
PU11
PU10
PU9
PU8
PU7
PU6
PU5
PU4
PU3
PU2
PU1
PU0
RFEOLEN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PU14
Reset value
SMPSEN
Reset value
PU15
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
0
Reset value
REGLPS
FLASHRDY
REGMRS
RFEOLF
LDORDY
SMPSRDY
RFBUSYMS
RFBUSYS
0
0
0
0
0
0
0
0
0
0
CWPVDF
Res.
Res.
Res.
Res.
Res.
CWUF3
CWUF2
CWUF1
Res.
APC
RRS
EWPVD
ULPEN
0
0
0
WRFBUSYP
Res.
Res.
0
0
0
0
0
0
WUF2
WUF1
0
WUF3
WP3
WP2
WP1
Res.
Res.
Res.
Res.
FPDR
SUBGHZSPINSSSEL
0
0
0
0
0
Res.
PLS [2:0]
PVDE
0
0
0
0
EWUP3
EWUP2
EWUP1
Res.
0
Res.
Res.
Res.
FPDS
PVME3
DBP
VOS [1:0]
Res.
Res.
Res.
LPR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
LPMS
[2:0]
Res.
Res.
0
Res.
Res.
Res.
Res.
Reset value
Res.
Res.
Res.
0
Res.
VBE
1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
0
WPVDF
0
VBRS
Res.
EWRFBUSY
0
Res.
0
Res.
Res.
WRFBUSYF
EWRFIRQ
Res.
EIWUL
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
REGLPF
0
Res.
0
VOSF
0
Res.
Res.
0
PVDO
Res.
Reset value
CWRFBUSYF
Res.
Res.
Res.
WUFI
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
1
Res.
Reset value
PVMO3
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
PD15
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
PU15
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PWR_PDCRA
Res.
0x024
PWR_PUCRA
Res.
0x020
PWR_CR5
Res.
0x01C
PWR_SCR
Res.
0x018
PWR_SR2
Res.
0x014
PWR_SR1
Res.
0x010
PWR_CR4
Res.
0x00C
PWR_CR3
Res.
0x008
PWR_CR2
Res.
0x004
PWR_CR1
Res.
0x000
Res.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Offset Register name
Res.
5.5.19
Res.
Power control (PWR)
RM0461
PWR register map
Table 48. PWR register map and reset values
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x090
PWR_
SUBGHZSPICR
Reset value
RM0461 Rev 10
0
Res.
Res.
Res.
Res.
Reset value
Res.
Res.
Res.
C1CSSF
PD3
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
C1SBF
0
Res.
C1STOP2F
0
Res.
Res.
C1STOPF
0
Res.
Res.
Res.
PD5
PD4
PD3
PD2
PD1
PD0
0
0
0
0
0
0
Res.
Res.
PU3
Res.
Res.
Res.
PD6
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PD13
0
Res.
PD14
0
Res.
PD5
PD4
PD3
PD2
PD1
PD0
0
0
0
0
0
0
0
0
0
Res.
Res.
Res.
Res.
Res.
PU0
PD6
0
PU1
PD7
0
PU2
PD8
0
PU3
PD9
0
PU4
PD11
PD10
0
PU5
PD12
0
PU6
PD13
0
Res.
PU13
PD14
PU14
0
Res.
Res.
Res.
0
Res.
Res.
C1DS
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PD15
PU15
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Reset value
Res.
PD15
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
NSS
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PWR_EXTSCR
Res.
0x088
PWR_PDCRH
Res.
0x05C
PWR_PUCRH
Res.
0x058
PWR_PDCRC
Res.
0x034
PWR_PUCRC
Res.
0x030
PWR_PDCRB
Res.
0x02C
Res.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Offset Register name
Res.
RM0461
Power control (PWR)
Table 48. PWR register map and reset values (continued)
0
0
0
0
0
0
0
0
0
1
Refer to Section 2.4 for the register boundary addresses.
225/1290
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Reset and clock control (RCC)
RM0461
6
Reset and clock control (RCC)
6.1
Reset
There are three types of reset, defined as system reset, power reset and backup domain
reset.
6.1.1
Power reset
A power reset is generated when one of the following events occurs:
•
a Brownout reset (BOR)
•
when exiting from Standby mode
•
when exiting from Shutdown mode
A Brownout reset, including power-on or power-down reset (POR/PDR), sets all registers to
their reset values except the backup domain.
When exiting Standby mode, all registers in the VCORE domain are set to their reset value.
Registers outside the VCORE domain (RTC, WKUP, IWDG and Standby/Shutdown modes
control) are not impacted.
When exiting Shutdown mode, a Brownout reset is generated, resetting all registers except
those in the backup domain.
6.1.2
System reset
A system reset sets all registers to their reset values unless otherwise specified in the
register description.
A system reset is generated when one of the following events occurs:
•
a low level on the NRST pin (external reset)
•
window watchdog event (WWDG reset)
•
independent watchdog event (IWDG reset)
•
a software reset (SW reset) (see Software reset)
•
low-power mode security reset (see Low-power mode security reset)
•
option byte loader reset (see Option byte loader reset)
•
a Brownout reset
•
an illegal sub-GHz radio access (sub-GHz radio protocol error reset) (only valid for non
LoRa devices, STM32WLE4xx)
The reset source can be identified by checking the reset flags in the control/status register,
RCC_CSR (see Section 6.4.31: RCC control/status register (RCC_CSR)).
These sources act on the NRST pin, that is always kept low during the delay phase. The
CPU RESET service routine vector is selected via the BOOT0 and BOOT1.
The system reset signal provided to the device is output on the NRST pin. The pulse
generator guarantees a minimum reset pulse duration of 20 µs for each internal reset
source. In case of an external reset, the reset pulse is generated while the NRST pin is
asserted low.
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RM0461
Reset and clock control (RCC)
In case on an internal reset, the internal pull-up RPU is deactivated in order to save the
power consumption through the pull-up resistor.
Figure 20. Simplified diagram of the reset circuit
VDD
RPU
System reset
External
reset NRST
Filter
WWDG reset
IWDG reset
Pulse
generator
(min 20 ȝs)
Radio protocol error reset(1)
CPU software reset
Low-power manager reset
Option byte loader reset
BOR reset
1) The sub-GHz radio protocol error reset is available in non LoRa devices only, STM32WLE4xx.
MSv62603V1
Software reset
The SYSRESETREQ bit in CPU application interrupt and reset control register may be set
to force a software reset on the device (refer to the programming manual STM32 Cortex®M4 MCUs and MPUs (PM0214)).
Low-power mode security reset
To prevent that critical applications mistakenly enter a low-power mode, two low-power
mode security resets are available.
If enabled in option bytes, the resets are generated in the following conditions:
•
Entering Standby mode: this type of reset is enabled by resetting nRST_STDBY bit in
user option bytes. In this case, whenever a Standby mode entry sequence is
successfully executed, the device is reset instead of entering Standby mode.
•
Entering Stop mode: this type of reset is enabled by resetting nRST_STOP bit in user
option bytes. In this case, whenever a Stop mode entry sequence is successfully
executed, the device is reset instead of entering Stop mode.
•
Entering Shutdown mode: this type of reset is enabled by resetting nRST_SHDW bit in
user option bytes. In this case, whenever a Shutdown mode entry sequence is
successfully executed, the device is reset instead of entering Shutdown mode.
For further information on the user option bytes, refer to Section 3.4.1: Option bytes
description.
Option byte loader reset
The option byte loader reset is generated when the OBL_LAUNCH bit is set in the
FLASH_CR register. This bit is used to launch the option byte loading by software.
6.1.3
Backup domain reset
The backup domain has two specific resets.
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Reset and clock control (RCC)
RM0461
A backup domain reset is generated when one of the following events occurs:
•
a software reset, triggered by setting the BDRST bit in the RCC backup domain control
register (RCC_BDCR)
•
VDD or VBAT power on, if both supplies have previously been powered off
A backup domain reset only affects the LSE oscillator, the RTC, the backup registers and
the RCC backup domain control register.
6.1.4
Sub-GHz radio reset
The sub-GHz radio can be reset by the RFRST register bit. A sub-GHz radio reset status
flag is provided in the RFRSTF register bit. The sub-GHz radio must not be accessed as
long as the reset status flag RFRSTF indicates sub-GHz radio in reset.
The sub-GHz radio is also reset when entering Shutdown mode.
6.1.5
PKA SRAM reset
The PKA SRAM is erased by hardware on any power reset and system reset. The status of
the PKA SRAM erase operation can be monitored in SYSCFG_SCSR.PKASRAMBSY flag
register bit.
6.2
Clocks
The following different clock sources can be used to drive the system clock (SYSCLK):
•
HSI16 (high-speed internal) 16 MHz RC oscillator clock
•
MSI (multi-speed internal) RC oscillator clock from 100 kHz to 48 MHz
•
HSE32 (high-speed external) 32 MHz oscillator clock, with trimming capacitors.
•
PLL clock
The MSI is used as system clock source after startup from reset, configured at 4 MHz.
The devices have the following additional clock sources:
•
LSI: 32 kHz low-speed internal RC that may drive the independent watchdog and
optionally the RTC used for auto-wake-up from Stop and Standby modes.
•
LSE: 32.768 kHz low-speed external crystal that optionally drives the RTC used for
auto-wake-up from Stop, Standby and Shutdown modes, or the real-time clock
(RTCCLK).
Each clock source can be switched on or off independently when it is not used, to optimize
power consumption.
Several prescalers can be used to configure the AHB frequencies (HCLK3/PCLK3, HCLK1),
the high-speed APB2 (PCLK2) and the low-speed APB1 (PCLK1) domains. The maximum
frequency of the AHB (HCLK3, HCLK1), the PCLK1 and the PCLK2 domains is 48 MHz.
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RM0461
Reset and clock control (RCC)
Most peripheral clocks are derived from their bus clock (HCLK, PCLK) except the following:
•
•
The clock used for true RNG, is derived (selected by software) from one of the following
sources:
–
PLL VCO (PLLQCLK) (only available in Run mode)
–
MSI (only available in Run mode)
–
LSI clock
–
LSE clock
The ADC clock is derived (selected by software) from one of the following sources:
–
system clock (SYSCLK) (only available in Run mode)
–
HSI16 clock (only available in Run mode)
–
PLL VCO (PLLPCLK) (only available in Run mode)
•
The DAC uses the LSI clock in sample and hold mode
•
The (LP)U(S)ARTs clocks are derived (selected by software) from one of the following
sources:
–
system clock (SYSCLK) (only available in Run mode)
–
HSI16 clock (available in Run and Stop modes)
–
LSE clock (available in Run and Stop modes)
–
APB clock (PCLK depending on which APB the U(S)ART is mapped) (available in
CRun and CSleep when also enabled in (LP)U(S)ARTxSMEN.)
The wake-up from Stop mode is supported only when the clock is HSI16 or LSE.
•
The I2Cs clocks are derived (selected by software) from one of the following sources:
–
system clock (SYSCLK) (only available in Run mode)
–
HSI16 clock (available in Run and Stop modes)
–
APB clock (PCLK depending on which APB the I2C is mapped) (available in CRun
and CSleep when also enabled in I2CxSMEN.)
The wake-up from Stop mode is supported only when the clock is HSI16.
•
•
The SPI2S2 I2S clock is derived (selected by software) from one of the following
sources:
–
HSI16 clock (only available in Run mode)
–
PLL VCO (PLLQCLK) (only available in Run mode)
–
external input I2S_CK (available in Run and Stop modes)
–
The SPI2S2 clock in SPI mode is provided by PCLK1 clock.
–
I2S mode is selected through register SPIx_I2SCFGR I2SMOD field
The low-power timers (LPTIMx) clock is derived (selected by software) from one of the
following sources:
–
LSI clock (available in Run and Stop modes)
–
LSE clock (available in Run and Stop modes)
–
HSI16 clock (only available in Run mode)
–
APB clock (PCLK depending on which APB the LPTIMx is mapped) (available in
Run and CStop when enabled in LPTIMxSMEN.)
–
external clock mapped on LPTIMx_IN1 (available in Run and Stop modes)
The functionality in Stop mode (including wake-up) is supported only when the clock is
LSI or LSE, or in external clock mode.
RM0461 Rev 10
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Reset and clock control (RCC)
•
RM0461
The RTC clock is derived (selected by software) from one of the following sources:
–
LSE clock
–
LSI clock
–
HSE32 clock divided by 32
The functionality in Stop mode (including wake-up) is supported only when the clock is
LSI or LSE.
•
The IWDG clock is always the LSI clock.
The RCC feeds the CPU system timer (SysTick) external clock with the AHB clock (HCLK1)
divided by eight. The SysTick can work either with this clock or directly with the CPU clock
(HCLK1), configurable in the SysTick control and status register.
FCLK1 acts as CPU free-running clock. For more details, refer to the programming manual
STM32 Cortex®-M4 MCUs and MPUs programming manual (PM0214).
Figure 21. Clock tree
LSIPRE
/1,128
LSI RCC 32 kHz
to IWDG
LSCO
OSC32_OUT
LSI
LSE OSC
32.768 kHz
LSE
to RTC
OSC32_IN
LSE CSS
LSI
LSE
CPU
HPRE
/1,2,...,512
/32
HSE32
HCLK1
to CPU, AHB1, AHB2
to CPU FCLK
SYSCLK
MCO
/8
PLLRCLK
/1 - 16
PLLQCLK
APB1
to APB1
PCLK1
PPRE1
/1,2,4,8,16
x1 or to APB1 TIMx
x2
SYS clock
source
control
PLLPCLK
HSI16
PLLRCLK
APB2
to APB2
PCLK2
PPRE2
/1,2,4,8,16
x1 or to APB2 TIMx
x2
MSI
OSC_OUT
OSC_IN
to CPU system timer
HSE32 OSC
32 MHz
MSI
SYSCLK
HSE CSS
HSE32 HSEPRE
/1,2
HSI16 RC
16 MHz
HSI16
MSI RC
100 kHz - 48 MHz
MSI
AHB3
SHDHPRE
/1,2,...,512
HCLK3
to AHB3, Flash, SRAM1, SRAM2
PCLK3
to APB3
HSI16
/M
to RF
PCLKn
PCLKn
HSI16
HSI16
SYSCLK
SYSCLK
PLL
x
N
to ADC
HSI16
/P
PLLPCLK
/Q
PLLQCLK
/R
PLLRCLK
to USART1
to USART2
to LPUART1
HSI16
I2S_CKIN
to SPI2S2
LSE
to LPTIM1
to LPTIM2
to LPTIM3
LSE
LSE
LSI
LSI
PCLKn
to RNG
MSI
SYSCLK
HSI16
LSI
DAC
to I2C1
to I2C2
to I2C3
MSv62605V3
1. For full details about the internal and external clock source characteristics, refer to the electrical characteristics section in
the device datasheet.
2. The ADC clock can additionally be derived from the AHB clock of the ADC bus interface, divided by a programmable factor
(1, 2 or 4). When the programmable factor is 1, the AHB prescaler must be equal to 1.
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6.2.1
Reset and clock control (RCC)
HSE32 clock with trimming
The HSE32 32 MHz external oscillator has the advantage of producing a very accurate rate
on the main clock. The HSE32 furthermore provides on-chip trimming capability.
The high-speed external clock signal (HSE32) can be generated from the following clock
sources:
•
HSE32 external crystal
•
HSE32 external clock
–
external clock source
–
external TCXO
The clock source must be placed as close as possible to the oscillator pins in order to
minimize output distortion and startup stabilization time.
HSE32 is controlled from the CPU and from the sub-GHz radio (see Section 4: Sub-GHz
radio (SUBGHZ)).
HSE32 can be switched on and off using the HSEON bit in the RCC clock control register
(RCC_CR). The HSE32 clock sources can be either an external crystal (XTAL) or an
external source including a temperature compensated crystal oscillator (TCXO). HSE32
must be enabled with the HSEON bit when used for the CPU.
The stability of the XTAL HSE32 clock may be impacted by the sub-GHz radio, depending
on the transmit output power (max +22 dBm), heating up the device. Heating depends on
the used transmit output power and the device package. Careful PCB design using thermal
heat dissipation techniques must be applied to avoid heat transfer to the HSE32 reference
clock source. For the HSE32 frequency drift requirements related to the sub-GHz radio, see
Section 4.5.1: LoRa modem.
The HSERDY flag in the RCC clock control register (RCC_CR) indicates if the HSE32
oscillator is stable or not. At startup, the clock is not released until this bit is set by hardware.
An interrupt can be generated if enabled in the RCC clock interrupt enable register
(RCC_CIER).
The sub-GHz radio enables HSE32 autonomously for its own purpose, independently of the
HSEON bit.
Warning:
The HSE32 cannot be used in LPRun mode.
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Figure 22. HSE32 clock sources
Clock source
Hardware configuration
tunable load
capacitors
CLOUT
CLIN
Crystal
OSC_IN
OSC_OUT
OSC_OUT
OSC_IN
External
Not
connected
External
clock source
CLIN
VDDTCXO
TCXO
C
C
TCXO
R
OSC_IN
OSC_OUT
Not connected
Note: Force SUBGHZ_HSEINTRIMR = 0x00
to get CLIN= 11.3 pF.
MSv62606V2
External crystal (HSE32 crystal)
The associated hardware configuration is shown in Figure 22. Refer to the electrical
characteristics section of the datasheet for more details.
Frequency trimming
When using HSE32 with external crystal, the load capacitors are provided by the integrated
capacitor banks, that can be trimmed. The HSE32 load capacitor trimming allows a
compensation of device manufacturing process variations, used crystal and PCB design.
The HSE32 frequency can be tuned in the application via the sub-GHz radio registers
SUBGHZ_HSEINTRIMR and SUBGHZ_HSEOUTRIMR. For more information see
Section 4.4: Sub-GHz radio clocks.
The HSE32 frequency can be measured by outputting the HSE32 clock on the MCO when
in Run mode.
External source (HSE32 TXCO)
In this mode, an external TXCO clock source must be provided. This external source
frequency must be 32 MHz. This mode is selected by setting the HSEBYPPWR and
HSEON bits in the RCC clock control register (RCC_CR). The external clock signal (refer to
the datasheet) must drive the following pins (see Figure 22: HSE32 clock sources):
•
OSC_IN and OSC_OUT pins: OSC_IN pin must be driven, while the OSC_OUT pin
must be left not connected.
The TCXO supply can be provided by the device on PB0/VDDTCXO. The VDDTCXO supply
is also enabled with the HSEBYPPWR bit in RCC clock control register (RCC_CR) before
enabling the HSE32 oscillator. VDDTCXO supply level and TCXO clock startup timeout can
be configured through the sub-GHz radio Set_TcxoMode() command (see Section 4:
Sub-GHz radio (SUBGHZ) for more details).
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Figure 23. HSE32 TCXO control
VDDRF
LDO
TCXO
PB0 GPIO
HSEBYPPWR
HSERDY
HSEclk
PB0-VDDTCXO
0
VDD TCXO
HSEON
Radio control
1
OSC
Control
tcxoon
oscon
OSC
HSE32
en CLIN
OSC_IN
TCXO
R
CLK
OSC_OUT NC
RDY
Control
clk
Note: Force SUBGHZ_HSEINTRIMR = 0x00
to get CLIN= 11.3 pF.
MSv62607V2
The control of the HSE32 external TCXO can be done in the following ways:
•
powered by VDDTCXO:
–
Set the voltage level inside the sub-GHz radio by using the Set_TcxoMode()
command, before enabling the VDDTCXO regulator.
–
Set the HSEBYPPWR bit to 1 to use the VDDTCXO regulator.
–
Enable the HSE32 use with external TCXO in Run mode for the CPU with the
HSEON bit.The availability of the clock can be checked with the HSERDY bit.
–
Enable the HSE32 use with TXCXO for the sub-GHz radio with the sub-GHz radio
Set_TcxoMode() command when in sub-GHz radio Standby mode. It is
recommended to issue a sub-GHz radio calibration command once the HSE32
clock is available.
When the CPUis in one of the low-power modes (Stop, Standby, or Shutdown) and the subGHz radio is in Sleep, the HSE32 clock including the TCXO is disabled.
6.2.2
HSI16 clock
The HSI16 clock signal is generated from an internal 16 MHz Oscillator.
The HSI16 oscillator has the advantage of providing a clock source at low cost. It also has a
faster startup time than the HSE32 crystal oscillator however, even with calibration the
frequency is less accurate than an external crystal oscillator or ceramic resonator.
The HSI16 clock can be selected as system clock after wake-up from Stop modes (Stop 0,
Stop 1 or Stop 2). Refer to Section 6.3. It can also be used as a backup clock source
(auxiliary clock) if the HSE32 crystal oscillator fails. Refer to Section 6.2.10.
Calibration
The RC oscillator frequencies can vary from one chip to another due to manufacturing
process variations. This is why each device is factory calibrated by ST for 1 % accuracy at
TA = 25 °C.
After a reset, the factory calibration value is loaded in the HSICAL[7:0] bits in the RCC
internal clock sources calibration register (RCC_ICSCR).
If the application is subject to voltage or temperature variations, this may affect the RC
oscillator speed. The HSI16 frequency can be trimmed in the application using the
HSITRIM[6:0] bits in the RCC internal clock sources calibration register (RCC_ICSCR).
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For more details on how to measure the HSI16 frequency variation, refer to Section 6.2.20.
The HSIRDY flag in the RCC clock control register (RCC_CR) indicates if the HSI16 RC is
stable or not. At startup, the HSI16 RC output clock is not released until this bit is set by
hardware.
The HSI16 RC can be switched on and off using the HSION bit in the RCC clock control
register (RCC_CR).
The HSI16 signal can also be used as a backup source (Auxiliary clock) if the HSE32 crystal
oscillator fails. Refer to Section 6.2.10.
6.2.3
MSI clock
The MSI clock signal is generated from an internal RC oscillator. Its frequency range can be
adjusted by software using the MSIRANGE[3:0] bits in the RCC clock control register
(RCC_CR). The following frequency ranges are available: 100 kHz, 200 kHz, 400 kHz,
800 kHz, 1 MHz, 2 MHz, 4 MHz (default value), 8 MHz, 16 MHz, 24 MHz, 32 MHz and
48 MHz. To use the MSI range, it must be selected by MSIRGSEL.
The MSI clock is used as system clock after restart from reset, wake-up from Standby and
Shutdown low-power modes. After restart from Reset and Shutdown, the MSI frequency is
set to its default value 4 MHz (see Section 6.3). When wake-up from Standby, MSI can be
adjusted by software using the MSISRANGE[3:0] bits in the RCC control/status register
(RCC_CSR). The following frequency ranges are available: 1MHz, 2 MHz, 4 MHz (default
value) and 8 MHz.
The MSI clock can be selected as system clock after a wake-up from Stop mode (Stop 0,
Stop 1, or Stop 2, see Section 6.3). It can also be used as a backup clock source (auxiliary
clock for the CPU) if the HSE32 crystal oscillator fails (see Section 6.2.10).
The MSI RC oscillator provides a low-power clock source. In addition, when used in PLLmode with the LSE, it also provides a very accurate clock source that can be used to feed
the PLL to run the system at the maximum speed 48 MHz.
The MSIRDY flag in the RCC clock control register (RCC_CR) indicates whether the MSI
RC is stable or not. At startup, the MSI RC output clock is not released until this bit is set by
hardware. The MSI RC can be switched on and off by using the MSION bit in the RCC clock
control register (RCC_CR).
Hardware auto calibration with LSE (PLL-mode)
When a 32.768 kHz external oscillator is present in the application, it is possible to configure
the MSI in a PLL-mode by setting the MSIPLLEN bit in the RCC clock control register
(RCC_CR). When configured in PLL-mode, MSI automatically calibrates itself thanks to the
LSE. This mode is available for all MSI frequency ranges.
Software calibration
The MSI RC oscillator frequency can vary from one chip to another due to manufacturing
process variations. This is why each device is factory calibrated by ST for 1 % accuracy at
an ambient temperature TA = 25 °C. After reset, the factory calibration value is loaded in the
MSICAL[7:0] bits in the RCC internal clock sources calibration register (RCC_ICSCR). If the
application is subject to voltage or temperature variations, this may affect the RC oscillator
speed. The MSI frequency can be trimmed in the application using the MSITRIM[7:0] bits in
the RCC internal clock sources calibration register (RCC_ICSCR). For more details on how
to measure the MSI frequency variation, refer to Section 6.2.20.
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6.2.4
Reset and clock control (RCC)
PLL
The device embeds one PLL. The PLL provides up to three independent outputs. The
internal PLL can be used to multiply the HSI16, HSE32 or MSI output clock frequency. The
PLL input frequency must be between 2.66 and 16 MHz. The selected clock source is
divided by a programmable factor PLLM from 1 to 8 to provide a clock frequency in the
requested input range. Refer to Figure 21 and RCC PLL configuration register
(RCC_PLLCFGR).
The PLL configuration (selection of the input clock and multiplication factor) must be done
before enabling the PLL. Once the PLL is enabled, these parameters cannot be changed.
To modify the PLL configuration, proceed as follows:
1.
Disable the PLL by setting PLLON to 0 in the RCC clock control register (RCC_CR).
2.
Wait until PLLRDY is cleared. The PLL is now fully stopped.
3.
Change the desired parameter.
4.
Enable the PLL again by setting PLLON to 1.
5.
Enable the desired PLL outputs by configuring PLLPEN, PLLQEN, PLLREN in the
RCC PLL configuration register (RCC_PLLCFGR).
An interrupt can be generated when the PLL is ready, if enabled in the RCC clock interrupt
enable register (RCC_CIER).
The PLLQCLK and PLLRCLK output frequency must not exceed 48 MHz. The PLLPCLK
output frequency must not exceed 62 MHz.
The enable bits of the PLL output clock (PLLPEN, PLLQEN, PLLREN) can be modified at
any time without stopping the PLL. PLLREN cannot be cleared if PLLRCLK is used as
system clock.
6.2.5
LSE clock
The LSE crystal is a 32.768 kHz low-speed external crystal or ceramic resonator. It provides
a low-power but highly accurate clock source to the real-time clock peripheral (RTC) for
clock/calendar or other timing functions.
The resonator and the load capacitors must be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. The loading
capacitance values must be adjusted according to the selected oscillator.
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Figure 24. LSE clock sources
Clock source
Hardware configuration
OSC32_IN
Crystal/
ceramic
resonators
OSC32_OUT
CL2
CL1
Load
capacitors
OSC32_OUT
OSC32_IN
External
External
clock source
GPIO
MSv62608V1
The LSE crystal is switched on and off using the LSEON bit in the RCC backup domain
control register (RCC_BDCR). The crystal oscillator driving strength can be changed at
runtime using the LSEDRV[1:0] bits in the RCC backup domain control register
(RCC_BDCR) to obtain the best compromise between robustness and short start-up time
on one side and low-power-consumption on the other side. The LSE drive can be decreased
to the lower drive capability (LSEDRV = 0) when the LSE is on. However, once LSEDRV is
selected, the drive capability can not be increased if LSEON = 1.
The LSERDY flag in the RCC backup domain control register (RCC_BDCR) indicates
whether the LSE crystal is stable or not. At startup, the LSE crystal output clock signal is not
released until this bit is set by hardware. An interrupt can be generated if enabled in the
RCC clock interrupt enable register (RCC_CIER).
When enabled and ready the LSE clock can directly be used by the RTC. To be able to use
the clocks by other peripherals (LPTIMx, TIMx, USARTx, LPUARTx, system LSCO, MCO,
MSI PLL mode), the LSE system clock must be enabled with the LSESYSEN bit in the RCC
backup domain control register (RCC_BDCR). When the LSE clock is ready and LSECSS is
enabled, the LSE clock is used by the LSECSS and is available on the LSCO. A
LSESYSRDY flag is provided in the RCC backup domain control register (RCC_BDCR) to
indicate when LSE system clock is ready (due clock synchronization) after having been
enabled by the LSESYSEN.
External source (LSE bypass)
In this mode, an external clock source must be provided. It can have a frequency of up to
1 MHz. This mode is selected by setting the LSEBYP and LSEON bits in the RCC backup
domain control register (RCC_BDCR). The external clock signal (square, sinus or triangle)
with ~50 % duty cycle must drive the OSC32_IN pin while the OSC32_OUT pin can be used
as GPIO (see Figure 24).
6.2.6
LSI clock
The LSI RC acts as a low-power clock source that can be kept running in Stop and Standby
modes for the independent watchdog (IWDG) and RTC. The clock frequency is ~32 kHz or
can be divided by 128 (~250 Hz) using LSIPRE. For more details, refer to the electrical
characteristics section of the datasheets.
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The LSI RC can be switched on and off using the LSION bit in the RCC control/status
register (RCC_CSR).
The LSIRDY flag in the RCC control/status register (RCC_CSR) indicates if the LSI
oscillator is stable or not. At startup, the clock is not released until this bit is set by hardware.
An interrupt can be generated if enabled in the RCC clock interrupt enable register
(RCC_CIER).
6.2.7
Clock source stabilization time
The different clock sources require a stabilization time, during which no clock is forwarded to
the system (see the table below).
Table 49. Clock source stabilization times
Clock source
MSI
Refer to the device datasheet.
HSI
Refer to the device datasheet.
HSE
Refer to the device datasheet.
LSI
LSE
6.2.8
Stabilization time
2 cycles (~85 μs LSIPRE = 0)
2 cycles (~2 ms LSIPRE = 1)
4096 cycles (125 ms)
System clock (SYSCLK) selection
The following clock sources can be used to drive the system clock (SYSCLK):
•
MSI oscillator
•
HSI16 oscillator
•
HSE32 oscillator (either 32 MHz or divided by 2 for 16 MHz)
•
PLLRCLK
The system clock maximum frequency in range 1 is 48 MHz. After a system reset, the MSI
oscillator, at 4 MHz, is selected as system clock. When a clock source is used directly or
through the PLL as a system clock, it is not possible to stop it.
A switch from one clock source to another occurs only if the target clock source is ready
(clock stable after startup delay or PLL locked). If a clock source that is not yet ready is
selected, the switch occurs when the clock source becomes ready. Status bits in the RCC
internal clock sources calibration register (RCC_ICSCR) indicate which clock(s) is (are)
ready and which clock is currently used as a system clock.
When waking up from Standby mode, the MSI at 4 MHz is selected as system clock.
In range 2, the system clock must not exceed 16 MHz.
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Clock source frequency versus voltage scaling
The following table gives the different clock source frequencies depending on the product
voltage range.
Table 50. Clock source frequency
Product voltage
range
Clock frequency
MSI
HSI16
HSE32
PLL
Range 1
48 MHz
16 MHz
32 MHz
PLLRCLK = PLLQCLK = 48 MHz
PLLPCLK = 62 MHz
(VCO max = 344 MHz)
Range 2
16 MHz
16 MHz
32 MHz(1)
PLLRCLK = PLLQCLK = 16 MHz
PLLPCLK = 21 MHz
(VCO max = 128 MHz)
1. The HSEPRE must be set to divide by two.
6.2.10
Clock security system on HSE32 (CSS)
The clock security system can be activated by software. In this case, the clock detector is
enabled after the HSE32 oscillator startup delay, and disabled when this oscillator is
stopped.
If a failure is detected on the HSE32 clock, the HSE32 oscillator is automatically disabled. A
clock failure event is sent to the break input of the advanced-control timers (TIM1 and
TIM16/17) and a HSE32 CSS interrupt is generated to inform the software about the failure,
allowing the MCU to perform rescue operations. The HSE32 CSS interrupt is linked to the
CPU NMI (non-maskable interrupt) exception vector.
Note:
Once the HSE32 CSS is enabled and if the HSE32 clock fails, the HSE32 CSS interrupt
occurs and a NMI is automatically generated. The NMI is executed indefinitely unless the
CSSF pending bit is cleared. As a consequence, in the NMI ISR (interrupt service routine),
the user must clear the HSE CSS interrupt by setting the CSSC bit in the RCC clock
interrupt clear register (RCC_CICR).
If the HSE32 oscillator is used directly or indirectly as the system clock (indirectly meaning
HSE32 is used as PLL input clock and the PLL clock is used as system clock), a detected
failure causes a switch of the system clock to the MSI or the HSI16 oscillator depending on
the STOPWUCK configuration in the RCC clock configuration register (RCC_CFGR), and
the disabling of the HSE32 oscillator. If the HSE32 clock (divided or not) is the clock entry of
the PLL used as system clock when the failure occurs, the PLL is disabled too.
6.2.11
Clock security system on LSE (LSECSS)
A CSS on LSE can be activated by software writing the LSECSSON bit in the RCC backup
domain control register (RCC_BDCR). This bit can be disabled only by a hardware reset or
RTC software reset, or after a failure detection on LSE. LSECSSON must be written after
LSE and LSI are enabled (LSEON and LSION) and ready (LSERDY and LSIRDY set by
hardware), and after the RTC clock has been selected by RTCSEL. The LSI clock is
automatically enabled.The LSE must not be disabled with the LSEON bit when LSECSS is
enabled with the LSECSSON bit.
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The CSS on LSE is working in all modes except VBAT. It is working also under system reset
(excluding power on reset). If a failure is detected on the external 32 kHz oscillator, the LSE
clock is no longer supplied to the RTC but no hardware action is made to the registers. If the
MSI was in PLL-mode, this mode is disabled.
In Standby mode, a wake-up is generated. In other modes an interrupt can be sent to wakeup the software (see RCC clock interrupt enable register (RCC_CIER), RCC clock interrupt
flag register (RCC_CIFR), RCC clock interrupt clear register (RCC_CICR)).
The software must then disable the LSECSSON bit, stop the defective 32 kHz oscillator
(disabling LSEON), and change the RTC clock source (no clock or LSI or HSE32, with
RTCSEL), or take any required action to secure the application.
6.2.12
SPI2S2 clock
The SPI2S2 I2S clock is derived from the HSI16 clock, PLL output, or from the external
I2S_CLK signal. It can reach 48 MHz.
The serial audio interface requires either a frequency close to 49.152 MHz or 11.2896 MHz.
The 49.152 MHz aims to derive audio sampling frequencies of 192 kHz, 96 kHz, 48 kHz,
32 kHz, 16 kHz and 8 kHz. While 11.2896 MHz targets audio sampling frequencies of
44.1 kHz, 22.05 kHz and 11.025 kHz. The targeted worts case accuracy must be 0.05 %.
Possible clock configurations are given in the table below.
Table 51. SPI2S2 I2S clock PLL configurations
Clock source
6.2.13
M
PLLN
PLLQ
MSI (4 MHz)
1
4
7
HSE32 (32 MHz)
7
43
4
HSI16 (16 MHz)
2
43
7
MSI (4 MHz)
1
79
28
HSE32 (32 MHz)
3
18
17
HSI16 (16 MHz)
1
12
17
I2C clock frequency
49.14286 MHz (-0.019%)
11.28571 MHz (0.034%)
11.29412 MHz (0.040%)
Sub-GHz radio SPI clock
The sub-GHz radio SPI clock is derived from the PCLK3 clock. The SUBGHZSPI_SCK
frequency is obtained by PCLK3 divided by two. The SUBGHZSPI_SCK clock maximum
speed must not exceed 16 MHz.
Table 52. Sub-GHz radio SPI clock configurations
PCLK3 [MHz]
SUBGHZSPI_SCK clock maximum speed
48
PCLK / 4(1) = 12 MHz
32
PCLK / 2(1) = 16 MHz
1. As controlled by SUBGHZSPI_CR1 BR baud rate control.
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ADC clock
The ADC clock is derived from the system clock, from the HSI16 clock, or from the PLL
output. The ADC clock can reach 35 MHz and can be divided by the following prescalers
values: 1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128 or 256 by configuring the ADC_CCR register. It
is asynchronous to the AHB clock. Alternatively, the ADC clock can be derived from the AHB
clock of the ADC bus interface, divided by a programmable factor (1, 2 or 4). This
programmable factor is configured using the CKMODE bit fields in the ADC_CCR register.
If the programmed factor is 1, the AHB prescaler must be set to 1.
6.2.15
RTC clock
The RTCCLK clock source can be either the HSE32 divided by 32, the LSE or the LSI clock.
RTCCLK is selected by programming the RTCSEL[1:0] bits in the RCC backup domain
control register (RCC_BDCR). This selection cannot be modified without resetting the
backup domain. The system must always be configured so as to get a PCLK frequency
greater then or equal to the RTCCLK frequency for a proper operation of the RTC.
The LSE clock is in the backup domain, whereas the HSE32 and LSI clocks are not, with the
following consequences:
•
If LSE is selected as RTC clock, the RTC continues to work even if the VDD supply is
switched off, provided the VBAT supply is maintained.
•
If LSI is selected as the RTC clock, the RTC state is not guaranteed if the VDD supply is
powered off.
•
If the HSE32 clock divided by a prescaler is used as the RTC clock, the RTC state is
not guaranteed if the VDD supply is powered off or if the internal voltage regulator is
powered off (removing power from the VCORE domain).
When the RTC clock is LSE or LSI, the RTC remains clocked and functional under system
reset.
6.2.16
Timer clock
The timer clock frequencies are automatically defined by hardware.
The following cases are possible:
6.2.17
•
If the APB prescaler (PPREx) selects the PCLKx clock to be HCLK1 not divided, the
timer clock frequencies are set to the HCLK1 frequency (timer clock = HCLK1).
•
If the APB prescaler (PPREx) selects the PCLKx clock to be HCLK1 divided by n, the
timer clock frequencies are set to HCLK1 divided by (n / 2) (timer clock = 2 x PCLKx).
Watchdog clock
If the independent watchdog (IWDG) is started by an hardware option or a software access,
the LSI clock is forced on.
If the LSI oscillator is disabled when starting the IWDG, the LSI oscillator is forced on. After
the LSI oscillator temporization, the clock is provided to the IWDG.
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6.2.18
Reset and clock control (RCC)
True RNG clock
The true random number generator (RNG) seed clock is derived from the MSI, from the PLL
output or from the LSE or LSI clock. It can reach 48 MHz and can be divided by a prescalers
values by configuring the true RNG register. It is asynchronous to the AHB clock.
6.2.19
Clock-out capability
•
MCO
The microcontroller clock output (MCO) capability allows the clock to be output onto the
external MCO pin. One of the following clock signals can be selected as the MCO
clock:
–
SYSCLK
–
MSI
–
HSI16 (only available when enabled by HSION)
–
HSE32
–
PLLRCLK
–
LSI
–
LSE
–
PLLPCLK
–
PLLQCLK
The selection is controlled by the MCOSEL[3:0] bits in the RCC clock configuration
register (RCC_CFGR). The selected clock can be divided with the MCOPRE[2:0] bits in
the RCC clock configuration register (RCC_CFGR).
The clock on MCO is only available in Run modes and is not available in Stop, Standby
and Shutdown modes.
•
LSCO
Another output (LSCO) allows one of the following low-speed clocks to be output onto
the external LSCO pin:
–
LSI
–
LSE
The selection is controlled by the LSCOSEL bit and enabled with the LSCOEN bit in
the RCC backup domain control register (RCC_BDCR).
The clock on LSCO is available in Run, Stop, and Standby and Shutdown modes.
The configuration registers of the corresponding GPIO port must be programmed in
alternate function mode.
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Internal/external clock measurement with TIM16/TIM17
The frequency of all on-board clock sources can be indirectly measured by mean of the
TIM16 or TIM17 channel 1 input capture, as shown in Figure 25 and Figure 26.
Figure 25. Frequency measurement with TIM16 in capture mode
TIM16
TI1_RMP[1:0]
GPIO
TI1
LSI
LSE
RTC wakeup interrupt
MS33434V1
The TIM16 input capture channel can be a GPIO line or an internal clock of the MCU. This
selection is performed through the TI1_RMP[1:0] bits in the TIM16_OR register. The
possibilities are listed below:
•
TIM16 channel1 is connected to the GPIO (refer to the alternate function mapping in
the device datasheets).
•
TIM16 channel1 is connected to the LSI clock.
•
TIM16 channel1 is connected to the LSE clock.
•
TIM16 channel1 is connected to the RTC wake-up interrupt signal. In this case the RTC
interrupt must be enabled.
Figure 26. Frequency measurement with TIM17 in capture mode
TIM17
TI1_RMP[1:0]
GPIO
TI1
MSI
HSE/32
MCO
MS33435V1
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The TIM17 input capture channel can be a GPIO line or an internal clock of the MCU. This
selection is performed through the TI1_RMP[1:0] bits in the TIM17_OR register. The
possibilities are listed below:
•
TIM17 channel1 is connected to the GPIO (refer to the alternate function mapping in
the device datasheets).
•
TIM17 channel1 is connected to the MSI Clock.
•
TIM17 channel1 is connected to the HSE32/32 Clock.
•
TIM17 channel1 is connected to the microcontroller clock output (MCO). This selection
is controlled by the MCOSEL[3:0] bits in the RCC clock configuration register
(RCC_CFGR).
Calibration of the HSI16 and the MSI
For TIM16, the primary purpose of connecting the LSE to the channel 1 input capture is to
be able to precisely measure the HSI16 and MSI system clocks (for this, HSI16 or MSI must
be used as the system clock source). The number of HSI16 (MSI, respectively) clock counts
between consecutive edges of the LSE signal, provides a measure of the internal clock
period. Taking advantage of the high precision of LSE crystals (typically a few tens of ppms),
it is possible to determine the internal clock frequency with the same resolution and to trim
the source to compensate for manufacturing-process- and/or temperature- and voltagerelated frequency deviations.
The MSI and HSI16 oscillator both have dedicated user-accessible calibration bits for this
purpose.
The basic concept consists in providing a relative measurement (the HSI16/LSE ratio): the
precision is therefore closely related to the ratio between the two clock sources. The higher
the ratio is, the better the measurement is.
If LSE is not available, HSE32/32 is the better option in order to reach the most precise
calibration possible.
It is however not possible to have a good enough resolution when the MSI clock is low
(typically below 1 MHz). In this case, the following is recommended:
•
Accumulate the results of several captures in a row.
•
Use the timer input capture prescaler (up to one capture every eight periods).
•
Use the RTC wake-up interrupt signal (when the RTC is clocked by the LSE) as the
input for the channel 1 input capture. This improves the measurement precision. For
this purpose the RTC wake-up interrupt must be enabled.
Calibration of the LSI
The LSI calibration follows the same pattern than the HSI16, but changing the reference
clock. It is necessary to connect the LSI clock to the TIM16 channel 1 input capture. Then
the HSE32 must be defined as system clock source. The number of HSE32 clock counts
between consecutive edges of the LSI signal provides a measure of the internal low-speed
clock period.
The basic concept consists in providing a relative measurement (the HSE32 / LSI ratio): the
precision is therefore closely related to the ratio between the two clock sources. The higher
the ratio is, the better the measurement is.
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Peripheral clocks enable
Most peripheral bus and kernel clocks can be individually enabled.The RCC_AHBxENR and
RCC_APBxENRy registers enable peripheral clocks. The peripheral clocks follow the CPU
state and the system state (see the table below). The RTC kernel clock is enabled by the
RTCEN bit and does not depend on the CPU state nor the system state.
Peripheral bus clock activity during the CPU Sleep mode is controlled by the xxxxSMEN bit
of the RCC_AHBxSMENR and RCC_APBxSMENRy registers.The peripheral bus clock
during Sleep mode follows the CPU state (see the table below).
Table 53. Peripheral clock enable
xxxEN xxxSMEN
0
x
0
1
1
x
x
System mode
Bus clock
Kernel clock(1)
Any
Stopped
Stopped
Run
Clocked
Clocked
Sleep
Stopped
Clocked
Sleep
Clocked
Clocked
Clocked when from HSI16, LSI, or LSE
Stop
Stopped
Stopped when from bus clock, SYSCLK,
PLL clocks, or MSI clocks
Standby or
Shutdown
Stopped
Stopped
1. Only the I2C, LPTIM, USART, LPUART, True RNG, ADC and SPI2S2 peripherals have a kernel clock
controlled by xxxEN and xxxSMEN. The RTC has a kernel clock controlled by RTCEN and does not
depend on xxxEN and xxxSMEN.
When the peripheral bus clock is not active, read or write accesses to the peripheral
registers are not supported.
When the peripheral kernel clock is not active, the peripheral functionality is stopped.
The enable bits have a synchronization mechanism to create a glitch free clock for the
peripheral. After the enable bit is set, there is a two clock cycles delay before the clock is
active in the peripheral.
Caution:
Just after enabling a clock for a peripheral, the software must wait for a delay before
accessing the peripheral registers.
6.3
Low-power modes
AHB and APB peripheral clocks, including DMA clock, can be disabled by software.
Sleep and LPSleep modes stop the CPU clock. The memory interface clocks (flash memory
and SRAM1/2 interfaces) can be stopped during Sleep mode by software using the
SRAMxSMEN bits. The AHB to APB bridge clocks are disabled by hardware during Sleep
mode when all the clocks of the peripherals connected to them are disabled in the
peripheral SMEN bits.
Stop modes (Stop 0, Stop 1 and Stop 2) stop most clocks in the VCORE domain and disable
the PLLs, the MSI and the HSE32 oscillators. HSI16 may be kept running when requested
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by the peripheral (USART1, USART2, LPUART1, I2C1, I2C2 or I2C3) that allows the wakeup from Stop modes.
All U(S)ARTs, LPUARTs and I2Cs have the capability to enable the HSI16 oscillator even
when the MCU is in Stop mode (if HSI16 is selected as clock source for that peripheral).
All U(S)ARTs, LPUARTs and LPTIMs can also be driven by the LSE oscillator when the
system is in Stop mode (if LSE is selected as clock source for that peripheral) and the LSE
oscillator is enabled (LSEON). In that case, LSE remains always on in Stop mode (no
capability to turn on the LSE oscillator).
All LPTIMs can also be driven by the LSI oscillator when the system is in Stop mode (if LSI
is selected as clock source for that peripheral) and the LSI oscillator is enabled (LSION).
Standby and Shutdown modes stop all clocks in the VCORE domain and disable the PLL, the
HSI16, the MSI and the HSE32 oscillators.
The low-power modes can be overridden for debugging the CPU by setting the
DBG_SLEEP, DBG_STOP or DBG_STANDBY bits in the DBGMCU_CR register. In
addition, the EXTI CDBGPWRUPREQ events can be used to allow debugging the CPU in
Stop modes (see the table below).
Table 54. Low-power debug configurations
CDBGPWRUPREQ
DBGMCU
Debug
Mode
CPU
DBG_STANDBY
DBG_STOP
DBG_SLEEP
CPU
Sleep
x(1)
x
x
x
Enabled
Stop 0
and
Stop 1
Disabled
Disabled
Disabled
Enabled
x
Stop 0,
Stop 1
and
Stop 2
x
Standby
x
Enabled
x
Enabled
Disabled
Enabled
x
Enabled
x
Disabled
Enabled
1. x = Don’t care.
When leaving the Stop modes (Stop 0, Stop 1 or Stop 2), the system clock is either MSI or
HSI16, depending on the software configuration of the STOPWUCK bit in the RCC clock
configuration register (RCC_CFGR). The frequency (range and user trim) of the MSI
oscillator is the one configured before entering Stop mode. The user trim of HSI16 is kept. If
the MSI was in PLL-mode before entering Stop mode, the PLL-mode stabilization time must
be waited for after wake-up, even if LSE was kept on during the Stop mode.
When exiting Standby mode, the system clock is MSI at 4 MHz.
When exiting Shutdown modes, the system clock is MSI. The MSI frequency at wake-up
from Shutdown mode is 4 MHz. The user trim is lost.
If a flash memory programming operation is ongoing, Stop, Standby and Shutdown modes
entry is delayed until the flash memory interface access is finished. If an access to the APB
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domain is ongoing, Stop, Standby and Shutdown modes entry is delayed until the APB
access is finished.
6.4
RCC registers
6.4.1
RCC clock control register (RCC_CR)
Address offset: 0x000
Reset value: 0x0000 0061
Access: no wait state, word, half-word and byte access
31
30
29
28
27
26
25
24
PLLON
Res.
Res.
Res.
Res.
Res.
Res.
PLL
RDY
r
rw
15
14
13
12
11
10
9
8
Res.
Res.
Res.
HSI
KERDY
HSI
ASFS
HSI
RDY
r
rw
r
23
22
21
20
19
Res.
Res.
HSEBY
PPWR
HSE
PRE
CSS
ON
rw
rw
rs
7
6
5
4
3
HSI
HSION
KERON
rw
rw
rw
rw
17
16
Res.
HSE
RDY
HSEON
r
rw
2
1
0
MSI
RDY
MSION
r
rw
MSIRG
MSI
SEL
PLLEN
MSIRANGE[3:0]
rw
18
rw
rs
rw
Bits 31:26 Reserved, must be kept at reset value.
Bit 25 PLLRDY: Main PLL clock ready flag
This bit is set by hardware to indicate that the main PLL is locked.
0: PLL unlocked
1: PLL locked
Bit 24 PLLON: Main PLL enable
This bit is set and cleared by software to enable the main PLL. It is also cleared by hardware
when entering Stop, Standby or Shutdown mode. This bit cannot be reset if the main PLL
clock is used as the system clock.
0: Main PLL off
1: Main PLL on
Bits 23:22 Reserved, must be kept at reset value.
Bit 21 HSEBYPPWR: HSE32 VDDTCXO output on package pin PB0-VDDTCXO enable
This bit is set and cleared by software to control the function on package pin
PB0-VDDTCXO. It can only be written when HSE32 oscillator is disabled
(HSEON = HSERDY = 0).
0: PB0 selected
1: VDDTCXO selected
Bit 20 HSEPRE: HSE32 SYSCLK prescaler
This bit is set and cleared by software to control the division factor of SYSCLK when
selecting HSE32 clock.
0: SYSCLK not divided (HSE32)
1: SYSCLK divided by two (HSE32 / 2)
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Bit 19 CSSON: HSE32 clock security system enable
This bit is set by software to enable the clock security system. When CSSON is set, the
HSE32 lock detector is enabled by hardware when the HSE32 oscillator is ready, and
disabled by hardware if a HSE32 clock failure is detected. This bit is set only and is cleared
by reset.
0: HSE32 CSS off (clock detector off)
1: HSE32 CSS on (clock detector on if the HSE32 oscillator is stable and off if not)
Bit 18 Reserved, must be kept at reset value.
Bit 17 HSERDY: HSE32 clock ready flag
This bit is set and cleared by hardware to indicate that the HSE32 oscillator is stable or not.
0: HSE32 oscillator not ready
1: HSE32 oscillator ready
Note: Once HSEON is cleared, HSERDY goes low after six HSE32 clock cycles.
Bit 16 HSEON: HSE32 clock enable for CPU
This bit is set and cleared by software. It is also cleared by hardware to stop the HSE32
oscillator when entering Stop, Standby or Shutdown mode. This bit cannot be reset if the
HSE32 oscillator is used directly or indirectly as system clock. The HSE32 oscillator must be
disabled before entering LPRun mode.
0: HSE32 oscillator for CPU disabled
1: HSE32 oscillator for CPU enabled
Note: The sub-GHz radio has its own HSE32 oscillator enable in the sub-GHz radio.
Bits 15:13 Reserved, must be kept at reset value.
Bit 12 HSIKERDY: HSI16 kernel clock ready flag for peripherals requests
This bit is set and cleared by hardware to indicate that the HSI16 oscillator is stable or not,
when enabled by HSIKERON or a peripheral kernel clock request. This bit is not set when
HSI16 is enabled by software with HSION setting or by wake-up from Standby.
0: HSI16 oscillator not ready
1: HSI16 oscillator ready
Note: Once HSIKERON is cleared, HSIKERDY goes low after six HSI16 clock cycles.
Bit 11 HSIASFS: HSI16 automatic start from Stop modes
This bit is set and cleared by software. When the system wake-up clock is MSI, this bit is
used to wake-up the HSI16 in parallel to the system wake-up clock.
0: HSI16 not enabled by hardware when exiting Stop modes with MSI as wake-up clock
1: HSI16 enabled by hardware when exiting Stop mode with MSI as wake-up clock
Bit 10 HSIRDY: HSI16 clock ready flag
This bit is set and cleared by hardware to indicate that HSI16 oscillator is stable or not. It is
set only when HSI16 is enabled by software by setting HSION, or by wake-up from Stop
modes and HSIASFS is enabled. After wake-up from Stop modes, this bit is read 1 once the
HSI16 is ready. This bit is not set when HSI16 is enabled by HSIKERON or by a peripheral
request.
0: HSI16 oscillator not ready
1: HSI16 oscillator ready
Note: Once HSION is cleared, HSIRDY goes low after six HSI16 clock cycles.
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Bit 9 HSIKERON: HSI16 enable for peripheral kernel clocks
This bit is set and cleared by software to force HSI16 on even in Stop modes. HSI16 enabled
by HSIKERON can only feed USARTs, LPUARTs and I2Cs peripherals configured with
HSI16 as kernel clock. Keeping HSI16 on in Stop modes avoids slowing down the
communication speed because of the HSI16 startup time. This bit has no effect on HSION
value.
0: No effect on HSI16 oscillator
1: HSI16 oscillator forced on even in Stop modes
Bit 8 HSION: HSI16 clock enable
This bit is set and cleared by software. It is also cleared by hardware to stop the HSI16
oscillator when entering Stop, Standby or Shutdown mode. This bit is set by hardware to
force the HSI16 oscillator on when STOPWUCK = 1 or HSIASFS = 1 when exiting Stop
modes, or in case of HSE32 crystal oscillator failure.
This bit is set by hardware if the HSI16 is used directly or indirectly as system clock. This bit
cannot be reset if the HSI16 oscillator is used directly or indirectly as system clock.
0: HSI16 oscillator off
1: HSI16 oscillator on
Bits 7:4 MSIRANGE[3:0]: MSI clock ranges
These bits are configured by software to choose the frequency range of MSI when
MSIRGSEL = 1. The following frequency ranges available:
0000: Range 0 around 100 kHz
0001: Range 1 around 200 kHz
0010: Range 2 around 400 kHz
0011: Range 3 around 800 kHz
0100: Range 4 around 1 MHz
0101: Range 5 around 2 MHz
0110: Range 6 around 4 MHz (reset value)
0111: Range 7 around 8 MHz
1000: Range 8 around 16 MHz
1001: Range 9 around 24 MHz
1010: Range 10 around 32 MHz
1011: Range 11 around 48 MHz
Others: not allowed (hardware write protection)
Caution: This field can be modified only when MSI is off (MSION = 0) or when MSI is ready
(MSIRDY = 1). This filed must not be modified when MSI is on and when MSI is not
ready (MSION = 1 and MSIRDY = 0).
Bit 3 MSIRGSEL: MSI range control selection
This bit is cleared to 0 on a system reset and when exiting Standby mode. It can be set to 1
by software. Software writing 0 has no effect.
0: MSI frequency range defined by MSISRANGE[3:0] in the RCC_CSR register
1: MSI frequency range defined by MSIRANGE[3:0] in the RCC_CR register
Bit 2 MSIPLLEN: MSI clock PLL enable
This bit is set and cleared by software to enable/disable the PLL part of the MSI clock source.
It must be enabled after LSE is enabled (LSEON = 1) and ready (LSERDY set by
hardware).There is a hardware protection to avoid enabling this bit if LSE is not ready.
This bit is cleared by hardware when LSE is disabled (LSEON = 0) or when the CSS on LSE
detects an LSE failure (refer to RCC_CSR register).
0: MSI PLL off
1: MSI PLL on
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Bit 1 MSIRDY: MSI clock ready flag
This bit is set and cleared by hardware to indicate that the MSI oscillator is stable or not. After
reset, this bit is read 1 once the MSI is ready.
0: MSI oscillator not ready
1: MSI oscillator ready
Note: Once MSION is cleared, MSIRDY goes low after six MSI clock cycles.
Bit 0 MSION: MSI clock enable
This bit is set and cleared by software. It is also cleared by hardware to stop the MSI
oscillator when entering Stop, Standby or Shutdown mode. This bit is set by hardware to
force the MSI oscillator on when exiting Standby or Shutdown mode. It is set by hardware to
force the MSI oscillator on when STOPWUCK = 0 when exiting from Stop modes, or in case
of a HSE32 oscillator failure. This bit is set by hardware when used directly or indirectly as
system clock. It cannot be reset if the MSI oscillator is used directly or indirectly as system
clock.
0: MSI oscillator off
1: MSI oscillator on
6.4.2
RCC internal clock sources calibration register (RCC_ICSCR)
Address offset: 0x004
Reset value: 0x40XX 00XX
The reset value of HSICAL[7:0] and MSICAL[7:0] is factory-programmed.
Access: no wait state, word, half-word and byte access
31
30
29
28
Res.
27
26
25
24
23
22
21
HSITRIM[6:0]
20
19
18
17
16
HSICAL[7:0]
rw
rw
rw
rw
rw
rw
rw
r
r
r
r
r
r
r
r
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
r
r
r
r
r
r
MSITRIM[7:0]
rw
rw
MSICAL[7:0]
r
r
Bit 31 Reserved, must be kept at reset value.
Bits 30:24 HSITRIM[6:0]: HSI16 clock trimming
These bits provide an additional user-programmable trimming value that is added to the
HSICAL[7:0] bits. They can be programmed to adjust to variations in voltage and
temperature that influence the HSI16 frequency.
The default value is 64 that, when added to the HSICAL value, must trim the HSI16 to
16 MHz ± 1 %.
Bits 23:16 HSICAL[7:0]: HSI16 clock calibration
These bits are initialized at startup with the factory-programmed HSI16 calibration trim value.
When HSITRIM is written, HSICAL is updated with the sum of HSITRIM and the factory trim
value.
Bits 15:8 MSITRIM[7:0]: MSI clock trimming
These bits provide an additional user-programmable trimming value that is added to the
MSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature
that influence the frequency of the MSI.
The default value is 0, that, when added to the MSICAL value, must trim the MSI to its mid
frequency.
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Bits 7:0 MSICAL[7:0]: MSI clock calibration
These bits are initialized at startup with the factory-programmed MSI calibration trim value.
When MSITRIM is written, MSICAL is updated with the sum of MSITRIM and the factory trim
value.
Note: Adding a MSITRIM value with the MSB set results in a subtraction.
6.4.3
RCC clock configuration register (RCC_CFGR)
Address offset: 0x008
Reset value: 0x0007 0000
(after POR reset and after wake-up from Standby)
Access: 0 ≤ wait state ≤ 2, word, half-word and byte access
One or two wait states inserted only if the access occurs during clock source switch.
From 0 to 15 wait states inserted if the access occurs when the APB or AHB prescalers
values update is ongoing.
31
30
Res.
29
28
27
MCOPRE[2:0]
26
25
24
MCOSEL[3:0]
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
STOP
WUCK
Res.
rw
PPRE2[2:0]
rw
rw
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
PPRE
2F
PPRE
1F
HPREF
r
r
r
7
6
5
4
3
2
1
0
PPRE1[2:0]
rw
rw
rw
HPRE[3:0]
rw
rw
rw
rw
SWS[1:0]
rw
r
r
SW[1:0]
rw
Bit 31 Reserved, must be kept at reset value.
Bits 30:28 MCOPRE[2:0]: Microcontroller clock output prescaler
These bits are set and cleared by software.
It is highly recommended to change this prescaler before MCO output is enabled.
000: MCO divided by 1
001: MCO divided by 2
010: MCO divided by 4
011: MCO divided by 8
100: MCO divided by 16
Others: not allowed
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Reset and clock control (RCC)
Bits 27:24 MCOSEL[3:0]: Microcontroller clock output selection
These bits are set and cleared by software.
0000: MCO output disabled, no clock on MCO
0001: SYSCLK system clock selected
0010: MSI clock selected.
0011: HSI16 clock selected.
0100: HSE32 clock selected (after stabilization)
0101: Main PLLRCLK clock selected
0110: LSI clock selected
1000: LSE clock selected
1101: Main PLLPCLK clock selected
1110: Main PLLQCLK clock selected
Others: reserved
Note: This clock output may have some truncated cycles at startup, entering and wake-up
from low-power modes, or during MCO clock source switching.
Bits 23:19 Reserved, must be kept at reset value.
Bit 18 PPRE2F: PCLK2 prescaler flag (APB2)
This bit is set and reset by hardware to acknowledge PCLK2 prescaler programming. It is
reset when a new prescaler value is programmed in PPRE2 and set when the programmed
value is actually applied.
0: PCLK2 prescaler value not yet applied
1: PCLK2 prescaler value applied
Bit 17 PPRE1F: PCLK1 prescaler flag (APB1)
This bit is set and reset by hardware to acknowledge PCLK1 prescaler programming. It is
reset when a new prescaler value is programmed in PPRE1 and set when the programmed
value is actually applied.
0: PCLK1 prescaler value not yet applied
1: PCLK1 prescaler value applied
Bit 16 HPREF: HCLK1 prescaler flag (CPU, AHB1, and AHB2)
This bit is set and reset by hardware to acknowledge HCLK1 prescaler programming. It is
reset when a new prescaler value is programmed in HPRE and set when the programmed
value is actually applied.
0: HCLK1 prescaler value not yet applied
1: HCLK1 prescaler value applied
Bit 15 STOPWUCK: Wake-up from Stop and CSS backup clock selection
This bit is set and cleared by software to select the system clock used when exiting Stop
mode. The selected clock is also used as emergency clock for the CSS on HSE32.
0: MSI oscillator selected as wake-up from stop clock and CSS backup clock.
1: HSI16 oscillator selected as wake-up from stop clock and CSS backup clock
Note: Warning: STOPWUCK must not be modified when the HSE32 CSS is enabled by
CSSON in the RCC_CR register and the system clock is HSE32 (SWS = 10) or a
switch on HSE32 is requested (SW = 10).
Bit 14 Reserved, must be kept at reset value.
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Bits 13:11 PPRE2[2:0]: PCLK2 high-speed prescaler (APB2)
These bits are set and cleared by software to control the division factor of the PCLK2 clock
(APB2). The PPRE2F flag can be checked to know if the programmed PPRE2 prescaler
value is applied.
0xx: HCLK1 not divided
100: HCLK1 divided by 2
101: HCLK1 divided by 4
110: HCLK1 divided by 8
111: HCLK1 divided by 16
Bits 10:8 PPRE1[2:0]: PCLK1 low-speed prescaler (APB1)
These bits are set and cleared by software to control the division factor of the PCLK1 clock
(APB1). The PPRE1F flag can be checked to know if the programmed PPRE1 prescaler
value is applied.
0xx: HCLK1 not divided
100: HCLK1 divided by 2
101: HCLK1 divided by 4
110: HCLK1 divided by 8
111: HCLK1 divided by 16
Bits 7:4 HPRE[3:0]: HCLK1 prescaler (CPU, AHB1, and AHB2.)
These bits are set and cleared by software to control the division factor of the HCLK1 clock
(CPU, AHB1, AHB2). The HPREF flag can be checked to know if the programmed HPRE
prescaler value is applied.
0001: SYSCLK divided by 3
0010: SYSCLK divided by 5
0101: SYSCLK divided by 6
0110: SYSCLK divided by 10
0111: SYSCLK divided by 32
1000: SYSCLK divided by 2
1001: SYSCLK divided by 4
1010: SYSCLK divided by 8
1011: SYSCLK divided by 16
1100: SYSCLK divided by 64
1101: SYSCLK divided by 128
1110: SYSCLK divided by 256
1111: SYSCLK divided by 512
Others: SYSCLK not divided
Caution: Depending on the device voltage range, the software must set correctly these bits to
ensure that the system frequency does not exceed the maximum allowed frequency
(for more details, refer to Section 5.1.4: Dynamic voltage scaling management).
After a write operation to these bits and before decreasing the voltage range, the
HPREF bit must be read to be sure that the new value has been taken into account.
Bits 3:2 SWS[1:0]: System clock switch status
These bits are set and cleared by hardware to indicate which clock source is used as system
clock.
00: MSI oscillator used as system clock
01: HSI16 oscillator used as system clock
10: HSE32 used as system clock
11: PLLRCLK used as system clock
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Bits 1:0 SW[1:0]: System clock switch
These bits are set and cleared by software to select system clock source (SYSCLK). They
are configured by hardware to force MSI oscillator selection when exiting Shutdown mode
and Standby mode.
These bits can also be configured by hardware to force MSI or HSI16 oscillator selection
when exiting Stop mode or in case of failure of the HSE32 oscillator, depending on
STOPWUCK value.
00: MSI selected as system clock
01: HSI16 selected as system clock
10: HSE32 selected as system clock
11: PLLRCLK selected as system clock
6.4.4
RCC PLL configuration register (RCC_PLLCFGR)
Address offset: 0x00C
Reset value: 0x2204 0100
Access: no wait state, word, half-word and byte access
This register is used to configure the main PLL clock outputs according to the formulas:
• f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
• f(PLL_P) = f(VCO clock) / PLLP
• f(PLL_Q) = f(VCO clock) / PLLQ
• f(PLL_R) = f(VCO clock) / PLLR
31
30
29
28
27
PLL
REN
PLLR[2:0]
26
25
24
PLL
QEN
PLLQ[2:0]
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
rw
rw
rw
rw
rw
rw
Res.
PLLN[6:0]
rw
23
22
Res.
Res.
7
6
Res.
21
20
18
17
16
PLL
PEN
PLLP[4:0]
rw
rw
rw
rw
rw
rw
5
4
3
2
1
0
Res.
Res.
PLLM[2:0]
rw
19
rw
rw
PLLSRC[1:0]
rw
rw
Bits 31:29 PLLR[2:0]: Main PLL division factor for PLLRCLK
These bits are set and cleared by software to control the frequency of the main PLL output
clock PLLRCLK. This output can be selected as system clock. These bits can be written only
if PLL is disabled.
PLLRCLK output clock frequency = VCO frequency / PLLR with PLLR = 2, 3, 4,... or 8 [VCO
frequency / (N + 1)]
000: reserved
001: PLLR = 2
010: PLLR = 3
011: PLLR = 4
100: PLLR = 5
101: PLLR = 6
110: PLLR = 7
111: PLLR = 8
Note: The software must set these bits correctly not to exceed 48 MHz on this domain in
range 1.
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RM0461
Bit 28 PLLREN: Main PLL PLLRCLK output enable
This bit is set and reset by software to enable the PLLRCLK output of the main PLL. It
cannot be written when PLLRCLK output of the PLL is used as system clock. In order to
save power, when the PLLRCLK output of the PLL is not used, the value of PLLREN must
be 0.
0: PLLRCLK output disabled
1: PLLRCLK output enabled
Bits 27:25 PLLQ[2:0]: Main PLL division factor for PLLQCLK
These bits are set and cleared by software to control the frequency of the main PLL output
clock PLLQCLK. This output can be selected for True RNG clock. These bits can be written
only if PLL is disabled.
PLLQCLK output clock frequency = VCO frequency / PLLQ with PLLQ = 2, 3, 4,... or 8 [VCO
frequency / (N + 1)]
000: reserved
001: PLLQ = 2
010: PLLQ = 3
011: PLLQ = 4
100: PLLQ = 5
101: PLLQ = 6
110: PLLQ = 7
111: PLLQ = 8
Note: The software must set these bits correctly not to exceed 48 MHz on this domain in
range 1.
Bit 24 PLLQEN: Main PLL PLLQCLK output enable
This bit is set and reset by software to enable the PLLQCLK output of the main PLL. In order
to save power, when the PLLQCLK output of the PLL is not used, the value of PLLQEN must
be 0.
0: PLLQCLK output disabled
1: PLLQCLK output enabled
Bits 23:22 Reserved, must be kept at reset value.
Bits 21:17 PLLP[4:0]: Main PLL division factor for PLLPCLK
These bits are set and cleared by software to control the frequency of the main PLL output
clock PLLPCLK. This output can be selected for ADC. These bits can be written only if the
PLL is disabled.
PLLPCLK output clock frequency = VCO frequency / PLLP with PLLP = 2, 3, 4, ...or 32 [VCO
frequency / (N + 1)]
0000: reserved
00001: PLLP = 2
00010: PLLP = 3
00011: PLLP = 4
00100: PLLP = 5
...
11111: PLLP = 32
Caution: The software must set these bits correctly not to exceed 48 MHz on this domain in
range 1.
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Reset and clock control (RCC)
Bit 16 PLLPEN: Main PLL PLLPCLK output enable
This bit is set and reset by software to enable the PLLPCLK output of the main PLL. In order
to save power, when the PLLPCLK output of the PLL is not used, the value of PLLPEN must
be 0.
0: PLLPCLK output disabled
1: PLLPCLK output enabled
Bit 15 Reserved, must be kept at reset value.
Bits 14:8 PLLN[6:0]: Main PLL multiplication factor for VCO
These bits are set and cleared by software to control the multiplication factor of the VCO.
They can be written only when the PLL is disabled.
VCO output frequency = VCO input frequency x PLLN with 6< PLLN < 127
0000000: Reserved must not be used.
...
0000101: Reserved (must not be used)
0000110: PLLN = 6
0000111: PLLN = 7
...
1010101: PLLN = 85
1010110: PLLN = 86
...
1111111: PLLN = 127
Caution: The software must set correctly these bits to assure that the VCO output frequency
is between 96 and 344 MHz.
Bit 7 Reserved, must be kept at reset value.
Bits 6:4 PLLM[2:0]: Division factor for the main PLL input clock
These bits are set and cleared by software to divide the PLL input clock before the VCO.
They can be written only when the PLL is disabled.
VCO input frequency = PLL input clock frequency / PLLM with 1 < PLLM < 8
000: PLLM = 1
001: PLLM = 2
010: PLLM = 3
011: PLLM = 4
100: PLLM = 5
101: PLLM = 6
110: PLLM = 7
111: PLLM = 8
Caution: The software must set these bits correctly to ensure that the VCO input frequency
ranges from 2.66 to 16 MHz.
Bits 3:2 Reserved, must be kept at reset value.
Bits 1:0 PLLSRC[1:0]: Main PLL entry clock source
These bits are set and cleared by software to select PLL clock source. They can be written
only when PLL is disabled. In order to save power, when no PLL is used, the value of
PLLSRC must be 0.
00: No clock sent to PLL
01: MSI clock selected as PLL clock entry
10: HSI16 clock selected as PLL clock entry
11: HSE32 clock selected as PLL clock entry
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6.4.5
RM0461
RCC clock interrupt enable register (RCC_CIER)
Address offset: 0x018
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
LSE
CSSIE
Res.
Res.
Res.
PLL
RDYIE
HSE
RDYIE
HSI
RDYIE
MSI
RDYIE
LSE
RDYIE
LSI
RDYIE
rw
rw
rw
rw
rw
rw
rw
Bits 31:10 Reserved, must be kept at reset value.
Bit 9 LSECSSIE: LSE clock security system interrupt enable
This bit is set and cleared by software to enable/disable interrupt caused by the CSS on
LSE.
0: Clock security interrupt caused by LSE clock failure disabled
1: Clock security interrupt caused by LSE clock failure enabled
Bits 8:6 Reserved, must be kept at reset value.
Bit 5 PLLRDYIE: PLL ready interrupt enable
This bit is set and cleared by software to enable/disable interrupt caused by PLL lock.
0: PLL lock interrupt disabled
1: PLL lock interrupt enabled
Bit 4 HSERDYIE: HSE32 ready interrupt enable
This bit is set and cleared by software to enable/disable interrupt caused by the HSE32
oscillator stabilization.
0: HSE32 ready interrupt disabled
1: HSE32 ready interrupt enabled
Bit 3 HSIRDYIE: HSI16 ready interrupt enable
This bit is set and cleared by software to enable/disable interrupt caused by the HSI16
oscillator stabilization.
0: HSI16 ready interrupt disabled
1: HSI16 ready interrupt enabled
Bit 2 MSIRDYIE: MSI ready interrupt enable
This bit is set and cleared by software to enable/disable interrupt caused by the MSI
oscillator stabilization.
0: MSI ready interrupt disabled
1: MSI ready interrupt enabled
Bit 1 LSERDYIE: LSE ready interrupt enable
This bit is set and cleared by software to enable/disable interrupt caused by the LSE
oscillator stabilization.
0: LSE ready interrupt disabled
1: LSE ready interrupt enabled
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RM0461
Reset and clock control (RCC)
Bit 0 LSIRDYIE: LSI ready interrupt enable
This bit is set and cleared by software to enable/disable interrupt caused by the LSI
oscillator stabilization.
0: LSI ready interrupt disabled
1: LSI ready interrupt enabled
6.4.6
RCC clock interrupt flag register (RCC_CIFR)
Address offset: 0x01C
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
LSE
CSSF
CSSF
Res.
PLL
RDYF
HSE
RDYF
HSI
RDYF
MSI
RDYF
LSE
RDYF
LSI
RDYF
r
r
r
r
r
r
r
r
Res.
Res.
Res.
Res.
Res.
Res.
Bits 31:10 Reserved, must be kept at reset value.
Bit 9 LSECSSF: LSE CSS (clock security system) flag after masking
This bit is set by hardware when LSECSSIE = 1 and a failure is detected in the LSE
oscillator. It is cleared by software setting the LSECSSC bit.
0: No CSS interrupt caused by LSE clock failure
1: CSS interrupt caused by LSE clock failure
Bit 8 CSSF: HSE32 CSS flag
This bit is set by hardware when a failure is detected in the HSE32 oscillator. It is cleared by
software setting the CSSC bit.
0: No clock security interrupt caused by HSE32 clock failure
1: Clock security interrupt caused by HSE32 clock failure
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 PLLRDYF: PLL ready interrupt flag
This bit is set by hardware when the PLL locks and PLLRDYDIE is set. It is cleared by
software setting the PLLRDYC bit.
0: No clock ready interrupt caused by PLL lock
1: Clock ready interrupt caused by PLL lock
Bit 4 HSERDYF: HSE32 ready interrupt flag
This bit is set by hardware when the HSE32 clock becomes stable and HSERDYDIE is set.
It is cleared by software setting the HSERDYC bit.
0: No clock ready interrupt caused by the HSE32 oscillator
1: Clock ready interrupt caused by the HSE32 oscillator
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RM0461
Bit 3 HSIRDYF: HSI16 ready interrupt flag
This bit is set by hardware when the HSI16 clock becomes stable and HSIRDYDIE is set in
a response to setting the HSION in the RCC_CR register. When HSION is not set but the
HSI16 oscillator is enabled by the peripheral through a clock request, this bit is not set and
no interrupt is generated. This bit is cleared by software setting the HSIRDYC bit.
0: No clock ready interrupt caused by the HSI16 oscillator
1: Clock ready interrupt caused by the HSI16 oscillator
Bit 2 MSIRDYF: MSI ready interrupt flag
This bit is set by hardware when the MSI clock becomes stable and MSIRDYDIE is set. It is
cleared by software setting the MSIRDYC bit.
0: No clock ready interrupt caused by the MSI oscillator
1: Clock ready interrupt caused by the MSI oscillator
Bit 1 LSERDYF: LSE ready interrupt flag
This bit is set by hardware when the LSE clock becomes stable and LSERDYDIE is set. It is
cleared by software setting the LSERDYC bit.
0: No clock ready interrupt caused by the LSE oscillator
1: Clock ready interrupt caused by the LSE oscillator
Bit 0 LSIRDYF: LSI ready interrupt flag
This bit is set by hardware when the LSI clock becomes stable and LSIRDYDIE is set. It is
cleared by software setting the LSIRDYC bit.
0: No clock ready interrupt caused by the LSI oscillator
1: Clock ready interrupt caused by the LSI oscillator
6.4.7
RCC clock interrupt clear register (RCC_CICR)
Address offset: 0x020
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
LSE
CSSC
CSSC
Res.
Res.
PLL
RDYC
HSE
RDYC
HSI
RDYC
MSI
RDYC
LSE
RDYC
LSI
RDYC
w
w
w
w
w
w
w
w
Bits 31:10 Reserved, must be kept at reset value.
Bit 9 LSECSSC: LSE CSS flag clear
This bit is set by software to clear the LSECSSF flag.
0: No effect
1: LSECSSF flag cleared
Bit 8 CSSC: HSE32 CSS flag clear
This bit is set by software to clear the HSE32 CSSF flag.
0: No effect
1: HSE32 CSSF flag cleared
Bits 7:6 Reserved, must be kept at reset value.
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RM0461
Reset and clock control (RCC)
Bit 5 PLLRDYC: PLL ready interrupt clear
This bit is set by software to clear the PLLRDYF flag.
0: No effect
1: PLLRDYF flag cleared
Bit 4 HSERDYC: HSE32 ready interrupt clear
This bit is set by software to clear the HSERDYF flag.
0: No effect
1: HSERDYF flag cleared
Bit 3 HSIRDYC: HSI16 ready interrupt clear
This bit is set software to clear the HSIRDYF flag.
0: No effect
1: HSIRDYF flag cleared
Bit 2 MSIRDYC: MSI ready interrupt clear
This bit is set by software to clear the MSIRDYF flag.
0: No effect
1: MSIRDYF flag cleared
Bit 1 LSERDYC: LSE ready interrupt clear
This bit is set by software to clear the LSERDYF flag.
0: No effect
1: LSERDYF flag cleared
Bit 0 LSIRDYC: LSI ready interrupt clear
This bit is set by software to clear the LSIRDYF flag.
0: No effect
1: LSIRDYF flag cleared
6.4.8
RCC AHB1 peripheral reset register (RCC_AHB1RSTR)
Address offset: 0x028
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
CRC
RST
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DMA
MUX1
RST
DMA2
RST
DMA1
RST
rw
rw
rw
rw
Bits 31:13 Reserved, must be kept at reset value.
Bit 12 CRCRST: CRC reset
This bit is set and cleared by software.
0: No effect
1: CRC reset
Bits 11:3 Reserved, must be kept at reset value.
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Reset and clock control (RCC)
RM0461
Bit 2 DMAMUX1RST: DMAMUX1 reset
This bit is set and cleared by software.
0: No effect
1: DMAMUX1 reset
Bit 1 DMA2RST: DMA2 reset
This bit is set and cleared by software.
0: No effect
1: DMA2 reset
Bit 0 DMA1RST: DMA1 reset
This bit is set and cleared by software.
0: No effect
1: DMA1 reset
6.4.9
RCC AHB2 peripheral reset register (RCC_AHB2RSTR)
Address offset: 0x02C
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
GPIOH
RST
Res.
Res.
Res.
Res.
Res.
Res.
Res.
rw
Bits 31:8 Reserved, must be kept at reset value.
Bit 7 GPIOHRST: IO port H reset
This bit is set and cleared by software.
0: No effect
1: IO port H reset
Bits 6:3 Reserved, must be kept at reset value.
Bit 2 GPIOCRST: IO port C reset
This bit is set and cleared by software.
0: No effect
1: IO port C reset
Bit 1 GPIOBRST: IO port B reset
This bit is set and cleared by software.
0: No effect
1: IO port B reset
Bit 0 GPIOARST: IO port A reset
This bit is set and cleared by software.
0: No effect
1: IO port A reset
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Res.
Res.
Res.
Res.
GPIOC GPIOB GPIOA
RST
RST
RST
rw
rw
rw
RM0461
Reset and clock control (RCC)
6.4.10
RCC AHB3 peripheral reset register (RCC_AHB3RSTR)
Address offset: 0x030
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
31
30
29
28
27
26
25
FLASH
RST
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
Res.
Res.
Res.
Res.
Res.
Res.
24
23
22
21
20
19
18
17
16
HSEM
RST
RNG
RST
AES
RST
PKA
RST
rw
Res.
Res.
Res.
Res.
Res.
rw
rw
rw
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
rw
Bits 31:26 Reserved, must be kept at reset value.
Bit 25 FLASHRST: Flash interface reset
This bit can only be set when the flash memory is in power down. It is set and cleared by
software.
0: No effect
1: Flash memory interface reset
Bits 24:20 Reserved, must be kept at reset value.
Bit 19 HSEMRST: HSEM reset
This bit is set and cleared by software.
0: No effect
1: HSEM reset
Bit 18 RNGRST: True RNG reset
This bit is set and cleared by software.
0: No effect
1: True RNG reset
Bit 17 AESRST: AES hardware accelerator reset
This bit is set and cleared by software.
0: No effect
1: AES reset
Bit 16 PKARST: PKA hardware accelerator reset
This bit is set and cleared by software. PKA reset is disabled when a hardware PKA SRAM
erase is ongoing.
0: No effect
1: PKA reset
Bits 15:0 Reserved, must be kept at reset value.
6.4.11
RCC APB1 peripheral reset register 1 (RCC_APB1RSTR1)
Address offset: 0x038
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
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Reset and clock control (RCC)
RM0461
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
LPTIM1
RST
Res.
DAC
RST
Res.
Res.
Res.
Res.
Res.
I2C3
RST
I2C2
RST
I2C1
RST
Res.
Res.
Res.
USART2
RST
Res.
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
Res.
SPI2S2
RST
rw
rw
Res.
Res.
Res.
Res.
Res.
Res.
Res.
rw
Res.
Res.
Res.
Res.
1
0
Res.
TIM2
RST
rw
Bit 31 LPTIM1RST: Low-power timer 1 reset
This bit is set and cleared by software.
0: No effect
1: LPTIM1 reset
Bit 30 Reserved, must be kept at reset value.
Bit 29 DACRST: DAC reset
This bit is set and cleared by software.
0: No effect
1: DAC reset
Bits 28:24 Reserved, must be kept at reset value.
Bit 23 I2C3RST: I2C3 reset
This bit is set and cleared by software.
0: No effect
1: I2C3 reset
Bit 22 I2C2RST: I2C2 reset
This bit is set and cleared by software.
0: No effect
1: I2C2 reset
Bit 21 I2C1RST: I2C1 reset
This bit is set and cleared by software.
0: No effect
1: I2C1 reset
Bits 20:18 Reserved, must be kept at reset value.
Bit 17 USART2RST: USART2 reset
This bit is set and cleared by software.
0: No effect
1: USART2 reset
Bits 16:15 Reserved, must be kept at reset value.
Bit 14 SPI2S2RST: SPI2S2 reset
This bit is set and cleared by software.
0: No effect
1: SPI2S2 reset
Bits 13:1 Reserved, must be kept at reset value.
Bit 0 TIM2RST: TIM2 timer reset
This bit is set and cleared by software.
0: No effect
1: TIM2 reset
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RM0461 Rev 10
RM0461
Reset and clock control (RCC)
6.4.12
RCC APB1 peripheral reset register 2 (RCC_APB1RSTR2)
Address offset: 0x03C
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
LPTIM3RST
LPTIM2RST
Res.
Res.
Res.
Res.
LPUART1RST
Access: no wait state, word, half-word and byte access
rw
rw
rw
Bits 31:7 Reserved, must be kept at reset value.
Bit 6 LPTIM3RST: Low-power timer 3 reset
This bit is set and cleared by software.
0: No effect
1: LPTIM3 reset
Bit 5 LPTIM2RST: Low-power timer 2 reset
This bit is set and cleared by software.
0: No effect
1: LPTIM2 reset
Bits 4:1 Reserved, must be kept at reset value.
Bit 0 LPUART1RST: Low-power UART 1 reset
This bit is set and cleared by software.
0: No effect
1: LPUART1 reset
6.4.13
RCC APB2 peripheral reset register (RCC_APB2RSTR)
Address offset: 0x040
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TIM17
RST
TIM16
RST
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
USART1
RST
Res.
SPI1
RST
TIM1
RST
Res.
ADC
RST
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
rw
rw
rw
rw
Bits 31:19 Reserved, must be kept at reset value.
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Reset and clock control (RCC)
RM0461
Bit 18 TIM17RST: Timer 17 reset
This bit is set and cleared by software.
0: No effect
1: TIM17 reset
Bit 17 TIM16RST: Timer 16 reset
This bit is set and cleared by software.
0: No effect
1: TIM16 reset
Bits 16:15 Reserved, must be kept at reset value.
Bit 14 USART1RST: USART1 reset
This bit is set and cleared by software.
0: No effect
1: USART1 reset
Bit 13 Reserved, must be kept at reset value.
Bit 12 SPI1RST: SPI1 reset
This bit is set and cleared by software.
0: No effect
1: SPI1 reset
Bit 11 TIM1RST: Timer 1 reset
This bit is set and cleared by software.
0: No effect
1: TIM1 reset
Bit 10 Reserved, must be kept at reset value.
Bit 9 ADCRST: ADC reset
This bit is set and cleared by software.
0: No effect
1: ADC reset
Bits 8:0 Reserved, must be kept at reset value.
6.4.14
RCC APB3 peripheral reset register (RCC_APB3RSTR)
Address offset: 0x044
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
SUBGHZSPIRST
Access: no wait state, word, half-word and byte access
rw
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RM0461
Reset and clock control (RCC)
Bits 31:1 Reserved, must be kept at reset value.
Bit 0 SUBGHZSPIRST: Sub-GHz radio SPI reset
This bit is set and cleared by software.
0: No effect
1: Sub-GHz radio SPI reset
6.4.15
RCC AHB1 peripheral clock enable register (RCC_AHB1ENR)
Address offset: 0x048
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
Note:
When the peripheral clock is not active, the peripheral registers read or write access is not
supported.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
DMA
MUX1
EN
DMA2
EN
DMA1
EN
rw
rw
rw
Res.
Res.
Res.
CRC
EN
Res.
Res.
Res.
Res.
Res.
rw
Res.
Res.
Res.
Bits 31:13 Reserved, must be kept at reset value.
Bit 12 CRCEN: CRC clock enable
This bit is set and cleared by software.
0: CRC clock disabled
1: CRC clock enabled
Bits 11:3 Reserved, must be kept at reset value.
Bit 2 DMAMUX1EN: DMAMUX1 clock enable
This bit is set and cleared by software.
0: DMAMUX1 clock disabled
1: DMAMUX1 clock enabled
Bit 1 DMA2EN: DMA2 clock enable
This bit is set and cleared by software.
0: DMA2 clock disabled
1: DMA2 clock enabled
Bit 0 DMA1EN: DMA1 clock enable
This bit is set and cleared by software.
0: DMA1 clock disabled
1: DMA1 clock enabled
RM0461 Rev 10
265/1290
289
Reset and clock control (RCC)
6.4.16
RM0461
RCC AHB2 peripheral clock enable register (RCC_AHB2ENR)
Address offset: 0x04C
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
Note:
When the peripheral clock is not active, the peripheral registers read or write access is not
supported.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
GPIOH
EN
Res.
Res.
Res.
Res.
rw
GPIOC GPIOB GPIOA
EN
EN
EN
rw
rw
rw
Bits 31:8 Reserved, must be kept at reset value.
Bit 7 GPIOHEN: IO port H clock enable
This bit is set and cleared by software.
0: IO port H clock disabled
1: IO port H clock enabled
Bits 6:3 Reserved, must be kept at reset value.
Bit 2 GPIOCEN: IO port C clock enable
This bit is set and cleared by software.
0: IO port C clock disabled
1: IO port C clock enabled
Bit 1 GPIOBEN: IO port B clock enable
This bit is set and cleared by software.
0: IO port B clock disabled
1: IO port B clock enabled
Bit 0 GPIOAEN: IO port A clock enable
This bit is set and cleared by software.
0: IO port A clock disabled
1: IO port A clock enabled
6.4.17
RCC AHB3 peripheral clock enable register (RCC_AHB3ENR)
Address offset: 0x050
Reset value: 0x0208 0000
Access: no wait state, word, half-word and byte access
Note:
266/1290
When the peripheral clock is not active, the peripheral registers read or write access is not
supported.
RM0461 Rev 10
RM0461
Reset and clock control (RCC)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
FLASH
EN
Res.
Res.
Res.
Res.
Res.
HSEM
EN
RNG
EN
AES
EN
PKA
EN
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
rw
Bits 31:26 Reserved, must be kept at reset value.
Bit 25 FLASHEN: flash memory interface clock enable
This bit can only be cleared when the flash memory is in power down. Set and cleared by
software.
0: Flash interface clock disabled
1: Flash interface clock enabled
Bits 24:20 Reserved, must be kept at reset value.
Bit 19 HSEMEN: HSEM clock enable
This bit is set and cleared by software.
0: HSEM clock disabled
1: HSEM clock enabled
Bit 18 RNGEN: true RNG clocks enable
This bit is set and cleared by software.
0: True RNG bus and kernel clocks disabled
1: True RNG bus and kernel clocks enabled
Bit 17 AESEN: AES accelerator clock enable
This bit is set and cleared by software.
0: AES clock disabled
1: AES clock enabled
Bit 16 PKAEN: PKA accelerator clock enable
This bit is set and cleared by software.
PKA clock is enabled when a hardware PKA SRAM erase is ongoing.
0: PKA clock disabled
1: PKA clock enabled
Bits 15:0 Reserved, must be kept at reset value.
6.4.18
RCC APB1 peripheral clock enable register 1 (RCC_APB1ENR1)
Address offset: 0x058
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
Note:
When the peripheral clock is not active, the peripheral registers read or write access is not
supported.
RM0461 Rev 10
267/1290
289
Reset and clock control (RCC)
RM0461
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
LPTIM1
EN
Res.
DAC
EN
Res.
Res.
Res.
Res.
Res.
I2C3
EN
I2C2
EN
I2C1
EN
Res.
Res.
Res.
USART2
EN
Res.
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
Res.
SPI2S2
EN
rw
rw
rw
Res.
Res.
WWDG RTCAPB
EN
EN
rs
Res.
Res.
Res.
Res.
rw
Res.
Res.
Res.
1
0
Res.
TIM2
EN
rw
Bit 31 LPTIM1EN: Low power timer 1 clocks enable
This bit is set and cleared by software.
0: LPTIM1 bus and kernel clocks disabled
1: LPTIM1 bus and kernel clocks enabled
Bit 30 Reserved, must be kept at reset value.
Bit 29 DACEN: DAC clock enable
This bit is set and cleared by software.
0: DAC clock disabled
1: DAC clock enabled
Bits 28:24 Reserved, must be kept at reset value.
Bit 23 I2C3EN: I2C3 clocks enable
This bit is set and cleared by software.
0: I2C3 bus and kernel clocks disabled
1: I2C3 bus and kernel clocks enabled
Bit 22 I2C2EN: I2C2 clocks enable
This bit is set and cleared by software.
0: I2C2 bus and kernel clocks disabled
1: I2C2 bus and kernel clocks enabled
Bit 21 I2C1EN: I2C1 clocks enable
This bit is set and cleared by software.
0: I2C1 bus and kernel clocks disabled
1: I2C1 bus and kernel clocks enabled
Bits 20:18 Reserved, must be kept at reset value.
Bit 17 USART2EN: USART2 clock enable
This bit is set and cleared by software.
0: USART2 bus and kernel clocks disabled
1: USART2 bus and kernel clocks enabled
Bits 16:15 Reserved, must be kept at reset value.
Bit 14 SPI2S2EN: SPI2S2 clock enable
This bit is set and cleared by software.
0: SPI2S2 clock disabled
1: SPI2S2 clock enabled
Bits 13:12 Reserved, must be kept at reset value.
268/1290
Res.
rw
RM0461 Rev 10
RM0461
Reset and clock control (RCC)
Bit 11 WWDGEN: Window watchdog clock enable
This bit is set by software to enable the window watchdog clock. It is reset by hardware
system reset. This bit is forced to 1 by hardware when the hardware WWDG_SW option is
reset.
0: Window watchdog clock disabled
1: Window watchdog clock enabled
Bit 10 RTCAPBEN: RTC APB bus clock enable
This bit is set and cleared by software.
RTC kernel clock is controlled by RCC_BDCR register bit RTCEN bit.
0: RTC APB bus clock disabled
1: RTC APB bus clock enabled
Bits 9:1 Reserved, must be kept at reset value.
Bit 0 TIM2EN: timer 2 clock enable
This bit is set and cleared by software.
0: TIM2 clock disabled
1: TIM2 clock enabled
6.4.19
RCC APB1 peripheral clock enable register 2 (RCC_APB1ENR2)
Address offset: 0x05C
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
LPTIM2EN
Res.
Res.
Res.
Res.
LPUART1EN
When the peripheral clock is not active, the peripheral registers read or write access is not
supported.
LPTIM3EN
Note:
rw
rw
rw
Bits 31:7 Reserved, must be kept at reset value.
Bit 6 LPTIM3EN: Low-power timer 3 clocks enable
This bit is set and cleared by software.
0: LPTIM3 bus and kernel clocks disabled
1: LPTIM3 bus and kernel clocks enable
Bit 5 LPTIM2EN: Low-power timer 2 clocks enable
Set and cleared by software.
0: LPTIM2 bus and kernel clocks disable
1: LPTIM2 bus and kernel clocks enable
Bits 4:1 Reserved, must be kept at reset value.
RM0461 Rev 10
269/1290
289
Reset and clock control (RCC)
RM0461
Bit 0 LPUART1EN: Low power UART 1 clocks enable
Set and cleared by software.
0: LPUART1 bus and kernel clocks disable
1: LPUART1 bus and kernel clocks enable
6.4.20
RCC APB2 peripheral clock enable register (RCC_APB2ENR)
Address offset: 0x060
Reset value: 0x0000 0000
Access: word, half-word and byte access
Note:
When the peripheral clock is not active, the peripheral registers read or write access is not
supported.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TIM17
EN
TIM16
EN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
USART1
EN
Res.
SPI1
EN
TIM1
EN
Res.
ADC
EN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
rw
rw
rw
rw
Bits 31:19 Reserved, must be kept at reset value.
Bit 18 TIM17EN: Timer 17 clock enable
This bit is set and cleared by software.
0: TIM17 clock disabled
1: TIM17 clock enabled
Bit 17 TIM16EN: Timer 16 clock enable
This bit is set and cleared by software.
0: TIM16 clock disabled
1: TIM16 clock enabled
Bits 16:15 Reserved, must be kept at reset value.
Bit 14 USART1EN: USART1 clocks enable
This bit is set and cleared by software.
0: USART1 bus and kernel clocks disabled
1: USART1 bus and kernel clocks enabled
Bit 13 Reserved, must be kept at reset value.
Bit 12 SPI1EN: SPI1 clock enable
This bit is set and cleared by software.
0: SPI1 clock disabled
1: SPI1 clock enabled
Bit 11 TIM1EN: TIM1 timer clock enable
This bit is set and cleared by software.
0: TIM1 timer clock disabled
1: TIM1P timer clock enabled
Bit 10 Reserved, must be kept at reset value.
270/1290
RM0461 Rev 10
RM0461
Reset and clock control (RCC)
Bit 9 ADCEN: ADC clocks enable
This bit is set and cleared by software.
0: ADC bus and kernel clocks disabled
1: ADC bus and kernel clocks enabled
Bits 8:0 Reserved, must be kept at reset value.
6.4.21
RCC APB3 peripheral clock enable register (RCC_APB3ENR)
Address offset: 0x64
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
When the peripheral clock is not active, the peripheral registers read or write access is not
supported.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
SUBGHZSPIEN
Note:
rw
Bits 31:1 Reserved, must be kept at reset value.
Bit 0 SUBGHZSPIEN: sub-GHz radio SPI clock enable
This bit is set and cleared by software.
0: Sub-GHz radio SPI clock disable
1: Sub-GHz radio SPI clock enable
6.4.22
RCC AHB1 peripheral clock enable in Sleep mode register
(RCC_AHB1SMENR)
Address offset: 0x068
Reset value: 0x0000 1007
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
CRC
SMEN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DMAMUX1
SMEN
DMA2
SMEN
DMA1
SMEN
Access: no wait state, word, half-word and byte access
rw
rw
rw
rw
RM0461 Rev 10
271/1290
289
Reset and clock control (RCC)
RM0461
Bits 31:13 Reserved, must be kept at reset value.
Bit 12 CRCSMEN: CRC clock enable during Sleep mode.
This bit is set and cleared by software.
0: CRC clock disabled by the clock gating during Sleep and Stop modes
1: CRC clock enabled by the clock gating during Sleep mode, disabled during Stop mode.
Bits 11:3 Reserved, must be kept at reset value.
Bit 2 DMAMUX1SMEN: DMAMUX1 clock enable during Sleep mode.
This bit is set and cleared by software.
0: DMAMUX1 clock disabled by the clock gating during Sleep and Stop modes
1: DMAMUX1 clock enabled by the clock gating during Sleep mode, disabled during Stop
mode
Bit 1 DMA2SMEN: DMA2 clock enable during Sleep mode
This bit is set and cleared by software.
0: DMA2 clock disabled by the clock gating during Sleep and Stop modes
1: DMA2 clock enabled by the clock gating during Sleep mode, disabled during Stop mode
Bit 0 DMA1SMEN: DMA1 clock enable during Sleep mode.
This bit is set and cleared by software.
0: DMA1 clock disabled by the clock gating during Sleep and Stop modes
1: DMA1 clock enabled by the clock gating during Sleep mode, disabled during Stop mode.
6.4.23
RCC AHB2 peripheral clock enable in Sleep mode register
(RCC_AHB2SMENR)
Address offset: 0x06C
Reset value: 0x0000 0087
Access: no wait state, word, half-word and byte access
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
GPIOH
SMEN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
rw
Res.
Res.
Res.
Res.
GPIOC GPIOB GPIOA
SMEN SMEN SMEN
rw
rw
rw
Bits 31:8 Reserved, must be kept at reset value.
Bit 7 GPIOHSMEN: IO port H clock enable during Sleep mode.
This bit is set and cleared by software.
0: IO port H clock disabled by the clock gating during Sleep and Stop modes
1: IO port H clock enabled by the clock gating during Sleep mode, disabled during Stop
mode.
Bits 6:3 Reserved, must be kept at reset value.
Bit 2 GPIOCSMEN: IO port C clock enable during Sleep mode.
This bit is set and cleared by software.
0: IO port C clock disabled by the clock gating during Sleep and Stop modes
1: IO port C clock enabled by the clock gating during Sleep mode, disabled during Stop mode
272/1290
RM0461 Rev 10
RM0461
Reset and clock control (RCC)
Bit 1 GPIOBSMEN: IO port B clock enable during Sleep mode.
This bit is set and cleared by software.
0: IO port B clock disabled by the clock gating during Sleep and Stop modes
1: IO port B clock enabled by the clock gating during Sleep mode, disabled during Stop mode
Bit 0 GPIOASMEN: IO port A clock enable during Sleep mode.
This bit is set and cleared by software.
0: IO port A clock disabled by the clock gating during Sleep and Stop modes
1: IO port A clock enabled by the clock gating during Sleep mode, disabled during Stop
mode.
6.4.24
RCC AHB3 peripheral clock enable in Sleep and Stop mode register
(RCC_AHB3SMENR)
Address offset: 0x070
Reset value: 0x0387 0000
Access: no wait state, word, half-word and byte access
31
Res.
30
Res.
29
Res.
28
Res.
27
Res.
26
Res.
25
24
23
FLASH SRAM2 SRAM1
SMEN SMEN SMEN
rw
rw
22
Res.
21
Res.
20
Res.
19
18
17
16
Res.
RNG
SMEN
AES
SMEN
PKA
SMEN
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Bits 31:26 Reserved, must be kept at reset value.
Bit 25 FLASHSMEN: Flash memory interface clock enable during Sleep mode.
This bit is set and cleared by software.
0: Flash memory interface clock disabled by the clock gating during Sleep and Stop modes
1: Flash memory interface clock enabled by the clock gating during Sleep mode, disabled
during Stop mode.
Bit 24 SRAM2SMEN: SRAM2 memory interface clock enable during Sleep mode
This bit is set and cleared by software.
0: SRAM2 clock disabled by the clock gating during Sleep and Stop modes
1: SRAM2 clock enabled by the clock gating during Sleep mode, disabled during Stop mode.
Bit 23 SRAM1SMEN: SRAM1 interface clock enable during Sleep mode.
This bit is set and cleared by software.
0: SRAM1 interface clock disabled by the clock gating during Sleep and Stop modes
1: SRAM1 interface clock enabled by the clock gating during Sleep mode, disabled during
Stop mode
Bits 22:19 Reserved, must be kept at reset value.
Bit 18 RNGSMEN: True RNG clocks enable during Sleep and Stop modes
This bit is set and cleared by software.
0: True RNG bus clock disabled by the clock gating during Sleep and Stop modes
1: True RNG bus clock enabled by the clock gating during Sleep mode, disabled during Stop
mode.
RM0461 Rev 10
273/1290
289
Reset and clock control (RCC)
RM0461
Bit 17 AESSMEN: AES accelerator clock enable during Sleep mode.
This bit is set and cleared by software.
0: AES clock disabled by the clock gating during Sleep and Stop modes
1: AES clock enabled by the clock gating during Sleep mode, disabled during Stop mode
Bit 16 PKASMEN: PKA accelerator clock enable during Sleep mode.
This bit is set and cleared by software.
0: PKA clock disabled by the clock gating during Sleep and Stop modes
1: PKA clock enabled by the clock gating during Sleep mode, disabled during Stop mode
Bits 15:0 Reserved, must be kept at reset value.
6.4.25
RCC APB1 peripheral clock enable in Sleep mode register 1
(RCC_APB1SMENR1)
Address offset: 0x078
Reset value: 0xA0E2 4C01
Access: no wait state, word, half-word and byte access
31
30
29
28
27
26
25
24
23
LPTIM1
SMEN
Res.
DAC
SMEN
Res.
Res.
Res.
Res.
Res.
I2C3
SMEN
rw
rw
rw
14
13
12
11
10
9
8
7
6
Res.
Res.
Res.
Res.
rw
rw
15
Res.
SPI2S2
SMEN
rw
Res.
Res.
RTC
WWDG
APB
SMEN
SMEN
rw
22
21
20
19
18
17
16
Res.
Res.
Res.
USART2
SMEN
Res.
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
TIM2
SMEN
I2C2
I2C1
SMEN SMEN
rw
rw
rw
Bit 31 LPTIM1SMEN: Low power timer 1 clock enable during Sleep and Stop modes
This bit is set and cleared by software.
0: LPTIM1 bus clock disabled by the clock gating during Sleep and Stop modes
1: LPTIM1 bus clock enabled by the clock gating during Sleep mode, disabled during Stop
mode
Bit 30 Reserved, must be kept at reset value.
Bit 29 DACSMEN: DAC clock enable during Sleep and Stop modes
This bit is set and cleared by software.
0: DAC clock disabled by the clock gating during Sleep and Stop modes
1: DAC clock enabled by the clock gating during Sleep mode, disabled during Stop mode
Bits 28:24 Reserved, must be kept at reset value.
Bit 23 I2C3SMEN: I2C3 clock enable during Sleep and Stop modes
This bit is set and cleared by software.
0: I2C3 bus clock disabled by the clock gating during Sleep and Stop modes
1: I2C3 bus clock enabled by the clock gating during Sleep mode, disabled during Stop
mode
274/1290
RM0461 Rev 10
RM0461
Reset and clock control (RCC)
Bit 22 I2C2SMEN: I2C2 clock enable during Sleep and Stop modes
This bit is set and cleared by software.
0: I2C2 bus clock disabled by the clock gating during Sleep and Stop modes
1: I2C2 bus clock enabled by the clock gating during Sleep mode, disabled during Stop
mode
Bit 21 I2C1SMEN: I2C1 clock enable during Sleep and Stop modes
This bit is set and cleared by software.
0: I2C1 bus clock disabled by the clock gating during Sleep and Stop modes
1: I2C1 bus clock enabled by the clock gating during Sleep mode, disabled during Stop
mode
Bits 20:18 Reserved, must be kept at reset value.
Bit 17 USART2SMEN: USART2 clock enable during Sleep and Stop modes
This bit is set and cleared by software.
0: USART2 bus clock disabled by the clock gating during Sleep and Stop modes
1: USART2 bus clock enabled by the clock gating during Sleep mode, disabled during Stop
mode
Bits 16:15 Reserved, must be kept at reset value.
Bit 14 SPI2S2SMEN: SPI2S2 clock enable during Sleep and Stop modes
This bit is set and cleared by software.
0: SPI2S2 clock disabled by the clock gating during Sleep and Stop modes
1: SPI2S2 clock enabled by the clock gating during Sleep mode, disabled during Stop mode
Bits 13:12 Reserved, must be kept at reset value.
Bit 11 WWDGSMEN: Window watchdog clocks enable during Sleep and Stop modes
This bit is set and cleared by software.It is forced to 1 by hardware when the hardware
WWDG_SW option is reset.
0: Window watchdog clock disabled by the clock gating during Sleep and Stop modes
1: Window watchdog clocks enabled by the clock gating during Sleep mode, disabled during
Stop mode
Bit 10 RTCAPBSMEN: RTC APB bus clock enable during Sleep and Stop modes
This bit is set and cleared by software. RTC kernel clock is controlled by the RTCEN bit in
the RCC_BDCR register.
0: RTC APB bus clock disabled during by the clock gating during Sleep and Stop modes
1: RTC APB bus clock enabled during by the clock gating during Sleep mode, disabled
during Stop mode
Bits 9:1 Reserved, must be kept at reset value.
Bit 0 TIM2SMEN: Timer 2 clock enable during Sleep and Stop modes
This bit is set and cleared by software.
0: TIM2 clock disabled by the clock gating during Sleep and Stop modes
1: TIM2 clock enabled by the clock gating during Sleep mode, disabled during Stop mode
6.4.26
RCC APB1 peripheral clock enable in Sleep mode register 2
(RCC_APB1SMENR2)
Address offset: 0x07C
Reset value: 0x0000 0061
Access: no wait state, word, half-word and byte access
RM0461 Rev 10
275/1290
289
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
LPTIM2SMEN
Res.
Res.
Res.
Res.
LPUART1SMEN
RM0461
LPTIM3SMEN
Reset and clock control (RCC)
rw
rw
rw
Bits 31:7 Reserved, must be kept at reset value.
Bit 6 LPTIM3SMEN: Low-power timer 3 clock enable during Sleep and Stop modes
This bit is set and cleared by software.
0: LPTIM3 bus clock disabled by the clock gating during Sleep and Stop modes
1: LPTIM3 bus clock enabled by the clock gating during Sleep mode, disabled during Stop
mode
Bit 5 LPTIM2SMEN: Low power timer 2 clock enable during Sleep and Stop modes
This bit is set and cleared by software.
0: LPTIM2 bus clock disabled by the clock gating during Sleep and Stop modes
1: LPTIM2 bus clock enabled by the clock gating during Sleep mode, disabled during Stop
mode
Bits 4:1 Reserved, must be kept at reset value.
Bit 0 LPUART1SMEN: Low-power UART 1 clock enable during Sleep and Stop modes
This bit is set and cleared by software.
0: LPUART1 bus clock disabled by the clock gating during Sleep and Stop modes
1: LPUART1 bus clock enabled by the clock gating during Sleep mode, disabled during Stop
mode
6.4.27
RCC APB2 peripheral clock enable in Sleep mode register
(RCC_APB2SMENR)
Address offset: 0x080
Reset value: 0x0006 5A00
Access: word, half-word and byte access
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TIM17
SMEN
TIM16
SMEN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
USART1
SMEN
Res.
SPI1
SMEN
TIM1
SMEN
Res.
ADC
SMEN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
rw
rw
rw
rw
Bits 31:19 Reserved, must be kept at reset value.
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Reset and clock control (RCC)
Bit 18 TIM17SMEN: Timer 17 clock enable during Sleep and Stop modes
This bit is set and cleared by software.
0: TIM17 clock disabled by the clock gating during Sleep and Stop modes
1: TIM17 clocks enabled by the clock gating during Sleep mode, disabled during Stop mode
Bit 17 TIM16SMEN: Timer 16 clock enable during Sleep and Stop modes
This bit is set and cleared by software.
0: TIM16 clock disabled by the clock gating during Sleep and Stop modes
1: TIM16 clock enabled by the clock gating during Sleep mode, disabled during Stop mode
Bits 16:15 Reserved, must be kept at reset value.
Bit 14 USART1SMEN: USART1 clock enable during Sleep and Stop modes
This bit is set and cleared by software.
0: USART1 bus clock disabled by the clock gating during Sleep and Stop modes
1: USART1 bus clock enabled by the clock gating during Sleep mode, disabled during Stop
mode
Bit 13 Reserved, must be kept at reset value.
Bit 12 SPI1SMEN: SPI1 clock enable during Sleep and Stop modes
This bit is set and cleared by software.
0: SPI1 clock disabled by the clock gating during Sleep and Stop modes
1: SPI1 clock enabled by the clock gating during Sleep mode, disabled during Stop mode
Bit 11 TIM1SMEN: Timer 1 clock enable during Sleep and Stop modes
This bit is set and cleared by software.
0: TIM1 clocks disabled by the clock gating during Sleep and Stop modes
1: TIM1 clock enabled by the clock gating during Sleep mode, disabled during Stop mode
Bit 10 Reserved, must be kept at reset value.
Bit 9 ADCSMEN: ADC clocks enable during Sleep and Stop modes
This bit is set and cleared by software.
0: ADC bus clock disabled by the clock gating during Sleep and Stop modes
1: ADC bus clock enabled by the clock gating during Sleep mode, disabled during Stop mode
Bits 8:0 Reserved, must be kept at reset value.
6.4.28
RCC APB3 peripheral clock enable in Sleep mode register
(RCC_APB3SMENR)
Address offset: 0x084
Reset value: 0x0000 0001
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
SUBGHZSPI
SMEN
Access: word, half-word and byte access
rw
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Reset and clock control (RCC)
RM0461
Bits 31:1 Reserved, must be kept at reset value.
Bit 0 SUBGHZSPISMEN: Sub-GHz radio SPI clock enable during Sleep and Stop modes
This bit is set and cleared by software.
0: Sub-GHz radio SPI clock disabled by the clock gating during Sleep and Stop modes
1: Sub-GHz radio SPI clock enabled by the clock gating during Sleep mode, disabled during
Stop mode
6.4.29
RCC peripherals independent clock configuration register
(RCC_CCIPR)
Address offset: 0x088
Reset value: 0x0000 0000
Access: no wait states, word, half-word and byte access
31
30
RNGSEL[1:0]
28
27
26
25
24
ADCSEL[1:0]
29
Res.
Res.
Res.
Res.
11
10
9
8
rw
rw
rw
rw
15
14
13
12
I2C2SEL[1:0]
I2C1SEL[1:0]
LPUART1SEL
[1:0]
rw
rw
rw
rw
rw
rw
SPI2S2SEL
[1:0]
rw
23
22
21
20
19
18
LPTIM3SEL[1:0] LPTIM2SEL[1:0] LPTIM1SEL[1:0]
17
16
I2C3SEL[1:0]
rw
rw
rw
rw
rw
rw
rw
rw
7
6
5
4
3
2
1
0
Res.
rw
Res.
Res.
Res.
USART2SEL
[1:0]
USART1SEL
[1:0]
rw
rw
rw
rw
Bits 31:30 RNGSEL[1:0]: RNG clock source selection
These bits are set and cleared by software to select the clock source used by the true RNG.
00: PLL “Q” clock (PLLQCLK) selected
01: LSI clock selected
10: LSE clock selected
11: MSI clock selected
Bits 29:28 ADCSEL[1:0]: ADC clock source selection
These bits are set and cleared by software to select the clock source used by the ADC
interface.
00: No clock selected
01: HSI16 clock selected
10: PLL “P” clock (PLLPCLK) selected
11: System clock (SYSCLK) selected
Bits 27:24 Reserved, must be kept at reset value.
Bits 23:22 LPTIM3SEL[1:0]: Low-power timer 3 clock source selection
These bits are set and cleared by software to select the LPTIM3 clock source.
00: PCLK selected
01: LSI clock selected
10: HSI16 clock selected
11: LSE clock selected
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Reset and clock control (RCC)
Bits 21:20 LPTIM2SEL[1:0]: Low-power timer 2 clock source selection
These bits are set and cleared by software to select the LPTIM2 clock source.
00: PCLK selected
01: LSI clock selected
10: HSI16 clock selected
11: LSE clock selected
Bits 19:18 LPTIM1SEL[1:0]: Low-power timer 1 clock source selection
These bits are set and cleared by software to select the LPTIM1 clock source.
00: PCLK selected
01: LSI clock selected
10: HSI16 clock selected
11: LSE clock selected
Bits 17:16 I2C3SEL[1:0]: I2C3 clock source selection
These bits are set and cleared by software to select the I2C3 clock source.
00: PCLK selected
01: System clock (SYSCLK) selected
10: HSI16 clock selected
11: Reserved
Bits 15:14 I2C2SEL[1:0]: I2C2 clock source selection
These bits are set and cleared by software to select the I2C2 clock source.
00: PCLK selected
01: System clock (SYSCLK) selected
10: HSI16 clock
11: Reserved
Bits 13:12 I2C1SEL[1:0]: I2C1 clock source selection
These bits are set and cleared by software to select the I2C1 clock source.
00: PCLK selected
01: System clock (SYSCLK) selected
10: HSI16 clock selected
11: Reserved
Bits 11:10 LPUART1SEL[1:0]: LPUART1 clock source selection
These bits are set and cleared by software to select the LPUART1 clock source.
00: PCLK selected
01: System clock (SYSCLK) selected
10: HSI16 clock selected
11: LSE clock selected
Bits 9:8 SPI2S2SEL[1:0]: SPI2S2 I2S clock source selection
This bit is set and cleared by software to select the SPI2S2 I2S clock source.
00: Reserved
01: PLL “Q” clock (PLLQCLK) selected
10: HSI16 clock selected
11: External input I2S_CKIN selected
Bits 7:4 Reserved, must be kept at reset value.
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RM0461
Bits 3:2 USART2SEL[1:0]: USART2 clock source selection
This bit is set and cleared by software to select the USART2 clock source.
00: PCLK selected
01: System clock (SYSCLK) selected
10: HSI16 clock selected
11: LSE clock selected
Bits 1:0 USART1SEL[1:0]: USART1 clock source selection
These bits are set and cleared by software to select the USART1 clock source.
00: PCLK selected
01: System clock (SYSCLK) selected
10: HSI16 clock selected
11: LSE clock selected
6.4.30
RCC backup domain control register (RCC_BDCR)
Address offset: 0x090
Reset value: 0x0000 0000
Reset by backup domain reset, except LSCOSEL, LSCOEN and BDRST that are reset only
by backup domain power-on reset but not reset by wake-up from Standby and NRST pad.
Access: 0 ≤ wait state ≤ 3, word, half-word and byte access
Wait states are inserted in case of successive accesses to this register.
Note:
The bits of this register are outside of the VCORE domain. As a result, after Reset, these bits
are write-protected and the DBP bit in the PWR control register 1 (PWR_CR1) must be set
before these bits can be modified. Refer to Section 5.1.2: Battery backup domain for further
information. These bits (except LSCOSEL, LSCOEN and BDRST) are only reset after a
backup domain reset (see Section 6.1.3). Any internal or external reset has no effect on
these bits.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
LSCO
SEL
LSCO
EN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
BDRST
rw
rw
9
8
7
6
5
4
3
2
1
0
LSEDRV[1:0]
LSE
BYP
LSE
RDY
LSEON
rw
rw
r
rw
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
Res.
LSESY
SRDY
RTCEN
Res.
rw
Res.
r
Res.
RTCSEL[1:0]
rw
rw
LSE
LSE
SYSEN CSSD
rw
rw
Bits 31:26 Reserved, must be kept at reset value.
Bit 25 LSCOSEL: Low-speed clock output selection
This bit is set and cleared by software.
0: LSI clock selected
1: LSE clock selected
Bit 24 LSCOEN: Low-speed clock output enable
This bit is set and cleared by software.
0: LSCO disabled
1: LSCO enabled
Bits 23:17 Reserved, must be kept at reset value.
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RM0461 Rev 10
r
LSE
CSSON
rw
rw
RM0461
Reset and clock control (RCC)
Bit 16 BDRST: Backup domain software reset
This bit is set and cleared by software.
0: Reset not activated
1: Entire backup domain reset
Bit 15 RTCEN: RTC kernel clock enable
This bit is set and cleared by software. The RTC APB bus clock is controlled by the
RTCAPBEN bit in the RCC_APB1ENR1 register and the RTCAPBSMEN bit in the
RCC_APB1SMENR1register.
0: RTC kernel clock disabled
1: RTC kernel clock enabled
Bits 14:12 Reserved, must be kept at reset value.
Bit 11 LSESYSRDY: LSE system clock ready
This bit is set and cleared by hardware to indicate when the LSE system clock is ready after
the LSESYSEN bit is set. This bit is only valid when LSEON, LSERDY and LSESYSEN are
set.
0: LSE system clock not ready
1: LSE system clock ready
Bit 10 Reserved, must be kept at reset value.
Bits 9:8 RTCSEL[1:0]: RTC clock source selection
These bits are set by software to select the clock source for the RTC. Once the RTC clock
source is selected, it cannot be changed anymore unless the backup domain is reset, or
unless a failure is detected on LSE (LSECSSD is set). The BDRST bit can be used to reset
them.
These bits cannot be written when LSE clock security is enabled in LSECSSON.
00: No clock
01: LSE oscillator clock selected
10: LSI oscillator clock selected
11: HSE32 oscillator clock divided by 32 selected
Bit 7 LSESYSEN: LSE system clock enable
This bit is set and cleared by software to enabled the LSE as system clock to the USARTx,
LPUARTx, LPTIMx, TIMx, RNG, system LSCO, MCO, MSI PLL mode. The LSE system clock
is only enabled when LSEON and LSERDY are both set.
0: LSE system clock disabled to USARTx, LPUARTx, LPTIMx, TIMx, RNG, system LSCO,
MCO, MSI PLL mode
1: LSE system clock enabled to USARTx, LPUARTx, LPTIMx, TIMx, RNG, system LSCO,
MCO, MSI PLL mode
Note: The LSE clock for the RTC is not impacted by this bit.
Bit 6 LSECSSD: CSS on LSE failure detection
This bit is set by hardware to indicate when a failure is detected by the CSS on the external
32 kHz oscillator (LSE). This bit is only reset by hardware on a BDRST and a POR reset.
0: No failure detected on LSE (32 kHz oscillator)
1: Failure detected on LSE (32 kHz oscillator)
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Reset and clock control (RCC)
RM0461
Bit 5 LSECSSON: CSS on LSE enable
This bit is set by software to enable the CSS on LSE (32 kHz oscillator). LSECSSON must
be enabled after the LSE oscillator is enabled (LSEON bit = 1) and ready (LSERDY flag set
by hardware), and after the RTCSEL bit is selected. This bit automatically enables the LSI
oscillator. Once enabled this bit cannot be disabled, except after a LSE failure detection
(LSECSSD = 1). In that case the software must disable the LSECSSON bit.
0: CSS on LSE off
1: CSS on LSE on
Bits 4:3 LSEDRV[1:0]: LSE oscillator drive capability
These bits are set by software to modulate the LSE oscillator drive capability.
00: Xtal mode lower driving capability
01: Xtal mode medium-low driving capability
10: Xtal mode medium-high driving capability
11: Xtal mode higher driving capability
Note: The oscillator is in Xtal mode when it is not in bypass mode.
Bit 2 LSEBYP: LSE oscillator bypass
This bit is set and cleared by software to bypass the LSE oscillator. It can be written only
when the external 32 kHz oscillator is disabled (LSEON = 0 and LSERDY = 0).
0: LSE oscillator not bypassed
1: LSE oscillator bypassed
Bit 1 LSERDY: LSE oscillator ready
This bit is set and cleared by hardware to indicate when the external 32 kHz oscillator is
stable.
0: LSE oscillator not ready
1: LSE oscillator ready
Note: Once the LSEON bit is cleared, this bit goes low after six LSE clock cycles.
Bit 0 LSEON: LSE oscillator enable
This bit is set and cleared by software.
0: LSE oscillator off
1: LSE oscillator on
Note: The LSE clock is directly forwarded to the RTC. To enable the LSE clock to other
system peripherals (USARTx, LPUARTx, LPTIMx, TIMx, RNG, system LSCO, MCO,
MSI PLL mode), LSE must be enabled with the LSESYSEN bit.
6.4.31
RCC control/status register (RCC_CSR)
Address offset: 0x094
Reset value: 0x0C01 C600
(Reset by NRST pad, except reset flags by POR only, not reset by wake-up from Standby)
Access: 0 ≤ wait state ≤ 3, word, half-word and byte access
Wait states are inserted in case of successive accesses to this register.
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RM0461
Reset and clock control (RCC)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
LPWR
RSTF
WWDG
RSTF
IWDG
RSTF
SFT
RSTF
BOR
RSTF
PIN
RSTF
OBLRS
TF
RFILA
RSTF
RMVF
Res.
Res.
Res.
Res.
Res.
Res.
Res.
6
5
4
3
2
1
0
Res.
LSI
PRE
Res.
LSI
RDY
LSION
r
rw
r
r
r
r
r
r
r
r
rw
15
14
13
12
11
10
9
8
7
RFRST
RF
RSTF
rw
r
Res.
Res.
MSISRANGE[3:0]
rw
rw
rw
Res.
rw
Res.
rw
Res.
Bit 31 LPWRRSTF: Low-power reset flag
This bit is set by hardware when a reset occurs due to illegal Stop, Standby or Shutdown
mode entry. It is cleared by writing to the RMVF bit.
0: No illegal mode reset occurred
1: Illegal mode reset occurred
Bit 30 WWDGRSTF: Window watchdog reset flag
This bit is set by hardware when a window watchdog reset occurs. It is cleared by writing to
the RMVF bit.
0: No window watchdog reset occurred
1: Window watchdog reset occurred
Bit 29 IWDGRSTF: Independent window watchdog reset flag
This bit is set by hardware when an independent watchdog reset domain occurs. It is cleared
by writing to the RMVF bit.
0: No independent watchdog reset occurred
1: Independent watchdog reset occurred
Bit 28 SFTRSTF: Software reset flag
This bit is set by hardware when a software reset occurs. It is cleared by writing to the RMVF
bit.
0: No software reset occurred
1: Software reset occurred
Bit 27 BORRSTF: BOR flag
This bit is set by hardware when a BOR occurs. It is cleared by writing to the RMVF bit.
0: No BOR occurred
1: BOR occurred
Bit 26 PINRSTF: Pin reset flag
This bit is set by hardware when a reset from the NRST pin occurs. It is cleared by writing to
the RMVF bit.
0: No reset from NRST pin occurred
1: Reset from NRST pin occurred
Bit 25 OBLRSTF: Option byte loader reset flag
This bit is set by hardware when a reset from the option byte loading occurs. It is cleared by
writing to the RMVF bit.
0: No reset from option byte loading occurred
1: Reset from option byte loading occurred
Bit 24 RFILARSTF: Sub-GHz radio illegal command flag
This bit is set by hardware when a illegal sub-GHz radio command is sent. It is cleared by
writing to the RMVF bit.
0: No sub-GHz radio illegal command occurred
1: Sub-GHz radio illegal command occurred
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Reset and clock control (RCC)
RM0461
Bit 23 RMVF: Remove reset flag
This bit is set by software to clear the reset flags LPWRRSTF, WWDGRSTF, IWDGRSTF,
SFTRSTF, BORRSTF, PINRSTF, OBLRSTF and RFILARSTF.
0: No effect
1: Reset flags reset
Bits 22:16 Reserved, must be kept at reset value.
Bit 15 RFRST: Sub-GHz radio reset
This bit is set and cleared by software.
0: Sub-GHz radio software reset removed
1: Sub-GHz radio software reset active
Bit 14 RFRSTF: Sub-GHz radio in reset status flag
This bit is set and cleared by hardware.
0: Sub-GHz radio out of reset
1: Sub-GHz radio in reset
Bits 13:12 Reserved, must be kept at reset value.
Bits 11:8 MSISRANGE[3:0]: MSI clock ranges
These bits are configured by software and can be written only when MSIRGSEL = 1 in the
RCC_CR register. They are used to choose the MSI frequency range when exiting Standby
mode and when MSIRGSEL = 0.
0100: Range 4 around 1 MHz
0101: Range 5 around 2 MHz
0110: Range 6 around 4 MHz (reset value)
0111: Range 7 around 8 MHz
Others: Not allowed (hardware write protection)
Bits 7:5 Reserved, must be kept at reset value.
Bit 4 LSIPRE: LSI frequency prescaler
This bit is set and cleared by software. It can be written at any time, however a new value is
only taken into account after a switching off and turning on sequence on LSI by using the
LSION bit.
0: LSI clock not divided (LSI)
1: LSI clock divided by 128 (LSI / 128)
Bits 3:2 Reserved, must be kept at reset value.
Bit 1 LSIRDY: LSI oscillator ready
This bit is set and cleared by hardware to indicate when the LSI oscillator is stable. After the
LSION bit is cleared, this bit goes low after three LSI clock cycles. This bit can be set even if
LSION = 0 if the LSI is requested by the CSS on LSE, by the independent watchdog or by
the RTC.
0: LSI oscillator not ready
1: LSI oscillator ready
Bit 0 LSION: LSI oscillator enable
This bit is set and cleared by software.
0: LSI oscillator off
1: LSI oscillator on
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RM0461
Reset and clock control (RCC)
6.4.32
RCC extended clock recovery register (RCC_EXTCFGR)
Address offset: 0x108
Reset value: 0x0003 0000
Access: no wait state, word, half-word and byte access
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
SHD
HPREF
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
r
SHDHPRE[3:0]
rw
rw
rw
rw
Bits 31:17 Reserved, must be kept at reset value.
Bit 16 SHDHPREF: HCLK3 shared prescaler flag (AHB3, flash, SRAM1, and SRAM2)
This bit is set and cleared by hardware to acknowledge the shared HCLK3 prescaler
programming. It is reset when a new prescaler value is programmed in SHDHPRE[3:0]. This
bit is set when the programmed value is actually applied.
0: HCLK3 prescaler value not yet applied
1: HCLK3 prescaler value applied
Bits 15:4 Reserved, must be kept at reset value.
Bits 3:0 SHDHPRE[3:0]: HCLK3 shared prescaler (AHB3, flash, SRAM1, and SRAM2)
These bits are set and cleared by software to control the division factor of the shared HCLK3
clock. (AHB3, flash, SRAM1 and SRAM2, APB3). The SHDHPREF flag can be checked to
know if the programmed SHDHPRE prescaler value is applied.
0001: SYSCLK divided by 3
0010: SYSCLK divided by 5
0101: SYSCLK divided by 6
0110: SYSCLK divided by 10
0111: SYSCLK divided by 32
1000: SYSCLK divided by 2
1001: SYSCLK divided by 4
1010: SYSCLK divided by 8
1011: SYSCLK divided by 16
1100: SYSCLK divided by 64
1101: SYSCLK divided by 128
1110: SYSCLK divided by 256
1111: SYSCLK divided by 512
Others: SYSCLK not divided
Caution: Depending on the device voltage range, the software must set correctly these bits to
ensure that the system frequency does not exceed the maximum allowed frequency
(refer to Section 5.1.4: Dynamic voltage scaling management). After a write
operation to these bits and before decreasing the voltage range, the SHDHPRE bit
must be read to be sure that the new value is taken into account.
RM0461 Rev 10
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0x02C
286/1290
RCC_
AHB2RSTR
Reset value
RM0461 Rev 10
0
0
LSIRDYC
0
0
0
DMA1RST
0
0
0
0
GPIOARST
LSERDYC
0
DMA2RST
MSIRDYC
HSERDYF
HSIRDYF
MSIRDYF
LSERDYF
LSIRDYF
HSERDYIE
HSIRDYIE
MSIRDYIE
LSERDYIE
LSIRDYIE
0
GPIOBRST
HSIRDYC
0
Res.
0
Res.
Res.
Res.
PLLSRC
[1:0]
PLLM[2:0]
0
x
DMAMUX1RST
HSERDYC
0
Res.
0
PLLRDYIE
0
x
GPIOCRST
0
x
MSIRGSEL
MSIPLLEN
MSIRDY
MSION
MSIRANGE
[3:0]
HSION
0
Res.
0
Res.
0
1
Res.
0
0
PLLRDYF
1
Res.
0
x
PLLRDYC
MSITRIM[7:0]
Res.
PLLN[6:0]
Res.
0
x
1
Res.
0
0
0
Res.
0
Res.
0
0
Res.
0
Res.
0
0
Res.
CSSF
0
Res.
HSIRDY
HSIKERON
0
Res.
CSSC
Reserved
Res.
SW
[1:0]
0
Res.
0
LSECSSIE.
HSIASFS
Res.
HSIKERDY
0
GPIOHRST
Reset value
LSECSSF
Reset value
LSECSSC
Reset value
Res.
0
Res.
SWS
[1:0]
0
Res.
0
Res.
HPRE[3:0]
0
Res.
Res.
PPRE1
[2:0]
0
Res.
Res.
0
Res.
Res.
0
Res.
Res.
Reserved
0
Res.
PPRE2[
2:0]
0
Res.
Res.
Res.
Res.
HSEON
0
Res.
CRCRST
Res.
Res.
0
0
Res.
Reset value
Res.
Res.
PLLPEN
HSICAL[7:0]
Res.
0
0
Res.
0
Res.
1
Res.
HPREF
STOPWUCK
1
Res.
Res.
Res.
0
Res.
Res.
Res.
x
Res.
Res.
0
Res.
HSERDY
Res.
CSSON
0
Res.
PLLP[4:0]
PPRE1F
1
Res.
Res.
x
PPRE2F
HSEPRE
0
Res.
Res.
x
Res.
Res.
Reserved
Res.
1
Res.
Res.
0
Res.
0
x
Res.
Res.
Res.
HSEBYPPWR
0
Res.
Res.
Res.
PLLON
Res.
PLLRDY
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
0
Res.
Res.
Res.
0
Res.
Res.
0
x
Res.
Res.
Res.
x
Res.
Res.
Res.
0
Res.
Res.
Res.
x
Res.
Res.
Res.
HSITRIM[6:0]
Res.
Res.
Res.
x
Res.
Res.
0
Res.
PLLQEN
MCOSEL
[3:0]
Res.
RCC_CR
0
Res.
Res.
Res.
1
Res.
Res.
PLLQ[2:0]
0
Res.
Res.
Res.
Res.
0
0
Res.
Res.
Res.
PLLREN
0
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
MCOPRE
[2:0]
Res.
Register
name
0
Res.
RCC_
AHB1RSTR
Res.
PLLR[2:0]
Reset value
Res.
0x028
0
0
0
Res.
Reserved
0
0
Res.
0x024
1
0
Res.
RCC_CICR
0
Res.
RCC_CIFR
0
Res.
RCC_
PLLCFGR
Res.
RCC_CIER
0
Res.
0x020
0
Res.
0x01C
Reset value
Res.
0x018
1
Res.
0x0100x014
0
Res.
Reset value
Res.
0x00C
RCC_CFGR
Res.
0x008
Res.
Reset value
Res.
RCC_ICSCR
Res.
0x004
Res.
0x000
Res.
Offset
Res.
6.4.33
Res.
Reset and clock control (RCC)
RM0461
RCC register map
Table 55. RCC register map and reset values
0
0
0
1
MSICAL[7:0]
x
x
x
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x058
RCC_
APB1ENR1
Reset value
0
I2C1EN
0
0
0
Reserved
RM0461 Rev 10
1
0
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
WWDGEN
RTCAPBEN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
TIM2EN
Reserved
Res.
0
0
0
Reset value
DMA2EN
DMA1EN
0
0
GPIOAEN
Res.
0
GPIOBEN
0
DMAMUX1EN
0
GPIOCEN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
SUBGHZSPIRST
LPTIM2RST
0
Reset value
LPUART1RST
Res.
Res.
Res.
Res.
LPTIM3RST
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
ADCRST
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
TIM1RST
Res.
Reset value
Res.
GPIOHEN
Res.
Res.
Res.
Res.
SPI1RST
Res.
USART1RST
0
Res.
Res.
Res.
Res.
0
Res.
Res.
Reset value
CRCEN
Res.
Res.
0
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
AESRST
PKARST
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
TIM2RST
Res.
RNGRST
Res.
Reserved
SPI2S2RST
Res.
Res.
USART2RST
Res.
HSEMRST
0
Res.
Res.
Res.
Res.
TIM16RST
Res.
Res.
Res.
Res.
Res.
Res.
FLASHRST.
Res.
Res.
Res.
Res.
0
SPI2S2EN
0
Res.
TIM17RST
0
Res.
Res.
Res.
Res.
Res.
0
Res.
PKAEN
Res.
Res.
I2C1RST
Res.
Res.
I2C2RST
Res.
Res.
I2C3RST
Res.
Res.
Res.
Res.
Res.
Res.
Res.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RCC_
AHB3RSTR
Res.
Register
name
0
Res.
AESEN
Res.
Res.
0
Res.
RNGEN
Res.
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reserved
USART2EN
1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DACRST
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
HSEMEN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
FLASHEN
Res.
Res.
Res.
Res.
Res.
LPTIM1RST
Res.
Res.
0
Res.
I2C2EN
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
I2C3EN
0
Res.
Res.
Res.
Res.
Reset value
Res.
RCC_
AHB3ENR
Res.
RCC_
AHB2ENR
Res.
RCC_
AHB1ENR
Res.
0x054
RCC_
APB3RSTR
Res.
0x050
RCC_
APB1RSTR2
Res.
0x04C
0
DACEN
0x048
Reset value
Res.
0x044
RCC_
APB2RSTR
Res.
0x040
RCC_
APB1RSTR1
Res.
0x03C
Res.
0x038
Res.
0x034
Res.
0x030
Res.
Offset
LPTIM1EN
RM0461
Reset and clock control (RCC)
Table 55. RCC register map and reset values (continued)
0
0
0
0
0
0
0
287/1290
289
0x078
RCC_APB1
SMENR1
Reset value
1
RCC_APB1
SMENR2
288/1290
1
RM0461 Rev 10
1
1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
TIM2SMEN
DMAMUX1SMEN
DMA2SMEN
DMA1SMEN
1
1
GPIOBSMEN
GPIOASMEN
Res.
Res.
Res.
1
GPIOCSMEN
Res.
Res.
Res.
Res.
Res.
Reset value
LPUART1SMEN
Res.
Res.
1
Res.
Res.
Res.
Res.
1
Res.
Res.
Res.
GPIOHSMEN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
SUBGHZSPIEN
ADCEN
Res.
Res.
0
Res.
Res.
Res.
Res.
LPTIM2EN
LPUART1EN
Res.
Res.
Res.
Res.
LPTIM3EN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
TIM1EN
Res.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RCC_
APB1ENR2
Res.
Register
name
0
Res.
LPTIM2SMEN
Res.
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
SPI1EN
Res.
USART1EN
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
RTCAPBSMEN
Res.
CRCSMEN
Res.
Res.
Res.
Res.
TIM16EN
Res.
0
Res.
Res.
Res.
WWDGSMEN
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
TIM17EN
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
1
Res.
Reserved
SPI2S2SMEN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
LPTIM3SMEN
Reset value
Res.
1
Res.
1
Res.
1
Res.
PKASMEN
1
Res.
AESSMEN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
USART2SMEN
RNGSMEN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
Res.
Res.
1
Res.
I2C1SMEN
1
Res.
SRAM1SMEN
1
Res.
FLASHSMEN
SRAM2SMEN
Res.
Res.
Res.
Res.
1
Res.
I2C2SMEN
1
Res.
Res.
Res.
I2C3SMEN
1
Res.
Res.
Res.
Res.
Reset value
Res.
Res.
Res.
Res.
RCC_
AHB3SMENR
DACSMEN
RCC_
AHB2SMENR
Res.
0x070
RCC_
AHB1SMENR
Res.
0x06C
RCC_
APB3ENR
Res.
0x064
Res.
0x068
RCC_
APB2ENR
Res.
0x060
Res.
0x05C
Res.
Offset
Res.
Reserved
LPTIM1SMEN
0x07C
0x074
Res.
Reset and clock control (RCC)
RM0461
Table 55. RCC register map and reset values (continued)
0
0
1
1
1
1
1
1
1
0x108
Reserved
Reserved
RCC_
EXTCFGR
SHDHPREF
0x0980x104
Reset value
RM0461 Rev 10
1
Res.
Reserved
LSECSSD
LSECSSON
LSEDRV[1:0]
LSEBYP
LSERDY
LSEON
0
0
0
0
0
0
0
Res.
Res.
LSIPRE
Res.
Res.
LSIRDY
LSION
RTCSEL[1:0]
USART1SEL
[1:0]
0
USART2SEL
[1:0]
Res.
Res.
Res.
Res.
SPI2S2SEL
[1:0]
Res.
LSESYSEN
0
0
Res.
1
Res.
1
0
Res.
0
0
Res.
0
Res.
MSISRANGE[3:0]
LPUART1SEL
[1:0]
0
0
LSESYSRDY
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
SUBGHZSPISMEN
ADCSMEN
Res.
1
Res.
Res.
Res.
TIM1SMEN
Res.
Res.
Res.
SPI1SMEN
Res.
Res.
USART1SMEN
Res.
Res.
1
Res.
I2C1SEL
[1:0]
0
0
Res.
Res.
Res.
1
Res.
Res.
Res.
0
0
Res.
1
Res.
I2C2SEL
[1:0]
TIM16SMEN
Res.
Res.
TIM17SMEN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
1
Res.
0
Res.
0
RFRSTF
I2C3SEL
[1:0]
0
Res.
RTCEN
0
RFRST
LPTIM1SEL
[1:0]
0
0
Res.
BDRST
LPTIM2SEL
[1:0]
Res.
Res.
Res.
1
Res.
Res.
Res.
Res.
Res.
Res.
Reserved
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RCC_APB2
SMENR
Res.
Register
name
1
Res.
0
Res.
LPTIM3SE
L[1:0]
0
0
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
Res.
0
0
0
Res.
1
Res.
1
0
0
Res.
0
0
Res.
0
0
RMVF
0
LSCOEN
0
LSCOSEL
OBLRSTF
RFILARSTF
Res.
0
Res.
Res.
Reset value
Res.
PINRSTF
Res.
0
Res.
ADCSEL
[1:0]
0
Res.
BORRSTF
Res.
Res.
RNGSEL
[1:0]
Reset value
Res.
Reset value
SFTRSTF
RCC_CSR
IWDGRSTF
RCC_BDCR
Res.
0x094
RCC_CCIPR
0
Res.
0x090
Res.
0x08C
Res.
0x088
RCC_
APB3SMENR
LPWRRSTF
0x084
WWDGRSTF
0x080
Res.
Offset
Res.
RM0461
Reset and clock control (RCC)
Table 55. RCC register map and reset values (continued)
Reset value
1
0
0
0
0
0
0
0
SHDHPRE
[3:0]
0
0
0
0
Refer to Section 2.4 for the register boundary addresses.
289/1290
289
Hardware semaphore (HSEM)
RM0461
7
Hardware semaphore (HSEM)
7.1
Introduction
The hardware semaphore block provides 16 (32-bit) register based semaphores.
The semaphores can be used to ensure synchronization between different processes
running on the core. The HSEM provides a non-blocking mechanism to lock semaphores in
an atomic way. The following functions are provided:
•
•
Semaphore lock, in two ways:
–
2-step lock: by writing MASTERID and PROCID to the semaphore, followed by a
read check
–
1-step lock: by reading the MASTERID from the semaphore
Interrupt generation when a semaphore is unlocked
–
•
Semaphore clear protection
–
•
7.2
Each semaphore may generate an interrupt
A semaphore is only unlocked when MASTERID and PROCID match
Global semaphore clear per MASTERID
Main features
The HSEM includes the following features:
•
•
•
•
•
290/1290
16 (32-bit) semaphores
8-bit PROCID
4-bit MASTERID
One interrupt line
Lock indication
RM0461 Rev 10
RM0461
Hardware semaphore (HSEM)
7.3
Functional description
7.3.1
HSEM block diagram
As shown in Figure 27, the HSEM is based on three sub-blocks:
•
the semaphore block containing the semaphore status and IDs
•
the semaphore interface block providing AHB access to the semaphore via the
HSEM_Rx and HSEM_RLRx registers
•
the interrupt interface block providing control for the interrupts via HSEM_ISR,
HSEM_IER, HSEM_MISR, and HSEM_ICR registers.
Figure 27. HSEM block diagram
32-bit AHB bus
HSEM
Interrupt interface
Semaphore interface
Bus master ID
Semaphore block
Sem_Ints
1
HSEM_R0
HSEM_R1
Semaphore 1
HSEM_MISR
hsem_hclk
HSEM_IER
HSEM_RLR0
1
Sem_Ints
HSEM_ISR
Semaphore 0
hsem_int_it
HSEM_RLR1
Sem_Ints
1
HSEM_Rx
Semaphore x
HSEM_RLRx
HSEM_ICR
MSv41950V3
7.3.2
HSEM internal signals
Table 56. HSEM internal input/output signals
7.3.3
Signal name
Signal type
Description
AHB bus
Digital input/output
BusMasterID
Digital input
AHB bus master ID
hsem_int_it
Digital output
Interrupt line
AHB register access bus
HSEM lock procedures
There are two lock procedures, namely 2-step (write) lock and 1-step (read) lock. The two
procedures can be used concurrently.
RM0461 Rev 10
291/1290
302
Hardware semaphore (HSEM)
RM0461
The semaphore is free when its LOCK bit is 0. In this case, the MASTERID and PROCID
are also 0. When the LOCK bit is 1, the semaphore is locked and the MASTERID indicates
which AHB bus master ID has locked it. The PROCID indicates which process of that AHB
bus master ID has locked the semaphore.
When write locking a semaphore, the written MASTERID must match the AHB bus master
ID , and the PROCID is written by the AHB bus master software process taking the lock.
When read locking the semaphore, the MASTERID is taken from the AHB bus master ID,
and the PROCID is forced to 0 by hardware. There is no PROCID available with read lock.
Figure 28. Procedure state diagram
WRITE (LOCK = 0)
WRITE (MASTERID & PROCID & LOCK = 1)
WRITE (LOCK = 1)
or
or
READ LOCK
WRITE (MASTERID or PROCID)
Lock
Free
Locked
Unlock
READ
WRITE (MASTERID & PROCID & LOCK = 0)
READ
or
READ LOCK
MSv41949V3
2-step (write) lock procedure
The 2-step lock procedure consists in a write to lock the semaphore, followed by a read to
check if the lock has been successful, carried out from the HSEM_Rx register.
•
Write semaphore with PROCID and MASTERID, and LOCK = 1. The MASTERID data
written by software must match the AHB bus master information, that is, a AHB bus
master ID = 1 writes data MASTERID = 1.
Lock is put in place when the semaphore is free at write time.
•
Read-back the semaphore
The software checks the lock status, if PROCID and MASTERID match the written
data, then the lock is confirmed.
•
Else retry (the semaphore has been locked by another process).
A semaphore can only be locked when it is free.
A semaphore can be locked when the PROCID = 0.
Consecutive write attempts with LOCK = 1 to a locked semaphore are ignored.
292/1290
RM0461 Rev 10
RM0461
Hardware semaphore (HSEM)
1-step (read) lock procedure
The 1-step procedure consists in a read to lock and check the semaphore in a single step,
carried out from the HSEM_RLRx register.
•
Read lock semaphore with the AHB bus master MASTERID.
•
If read MASTERID matches and PROCID = 0, then lock is put in place. If MASTERID
matches and PROCID is not 0, this means that another process from the same
MASTERID has locked the semaphore with a 2-step (write) procedure.
•
Else retry (the semaphore has been locked by another process).
A semaphore can only be locked when it is free. When read locking a free semaphore,
PROCID is 0. Read locking a locked semaphore returns the MASTERID and PROCID that
locked it. All read locks, including the first one that locks the semaphore, return the
MASTERID that locks or locked the semaphore.
Note:
The 1-step procedure must not be used when running multiple processes of the same AHB
bus master ID. All processes using the same semaphore read the same status. When only
one process locks the semaphore, each process of that AHB bus master ID reads the
semaphore as locked by itself with the MASTERID.
7.3.4
HSEM write/read/read lock register address
For each semaphore, two AHB register addresses are provided, separated in two banks of
32-bit semaphore registers, spaced by a 0x80 address offset.
In the first register address bank the semaphore can be written (locked/unlocked) and read
through the HSEM_Rx registers.
In the second register address bank the semaphore can be read (locked) through the
HSEM_RLRx registers.
7.3.5
HSEM unlock procedures
Unlocking a semaphore is a protected process, to prevent accidental clearing by a AHB bus
master ID or by a process not having the semaphore lock right. The procedure consists in
writing to the semaphore HSEM_Rx register with the corresponding MASTERID and
PROCID and LOCK = 0. When unlocked, the MASTERID, and the PROCID are all 0.
When unlocked, an interrupt may be generated to signal the event. To this end, the
semaphore interrupt must be enabled.
The unlock procedure consists in a write to the semaphore HSEM_Rx register with
matching MASTERID regardless on how the semaphore has been locked (1- or 2-step).
Note:
•
Write semaphore with PROCID, MASTERID, and LOCK = 0
•
If the written data matches the semaphore PROCID and MASTERID and the AHB bus
master ID , the semaphore is unlocked and an interrupt may be generated when
enabled, else write is ignored, semaphore remains locked and no interrupt is generated
(the semaphore is locked by another process or the written data does not match the
AHB bus master signaling).
Different processes of the AHB bus master ID can write any PROCID value. Preventing
other processes of the AHB bus master ID from unlocking a semaphore must be ensured
by software, handling the PROCID correctly.
RM0461 Rev 10
293/1290
302
Hardware semaphore (HSEM)
7.3.6
RM0461
HSEM MASTERID semaphore clear
All semaphores locked by a MASTERID can be unlocked at once by using the HSEM_CR
register. Write MASTERID and correct KEY value in HSEM_CR. All locked semaphores with
a matching MASTERID are unlocked, and may generate an interrupt when enabled.
An interrupt may be generated for the unlocked semaphore(s). To this end, the semaphore
interrupt must be enabled in the HSEM_IER register.
7.3.7
HSEM interrupts
An interrupt line hsem_int_it allows each semaphore to generate an interrupt.
An interrupt line provides the following features per semaphore:
•
interrupt enable
•
interrupt clear
•
interrupt status
•
masked interrupt status
With the interrupt enable (HSEM_IER) the semaphores affecting the interrupt line can be
enabled. Disabled (masked) semaphore interrupts do not set the masked interrupt status
MISF for that semaphore, and do not generate an interrupt on the interrupt line.
The interrupt clear (HSEM_ICR) clears the interrupt status ISF and masked interrupt status
MISF of the associated semaphore for the interrupt line.
The interrupt status (HSEM_ISR) mirrors the semaphore interrupt status ISF before the
enable.
The masked interrupt status (HSEM_MISR) only mirrors the semaphore enabled interrupt
status MISF on the interrupt line. All masked interrupt status MISF of the enabled
semaphores need to be cleared to clear the interrupt line.
294/1290
RM0461 Rev 10
RM0461
Hardware semaphore (HSEM)
Figure 29. Interrupt state diagram
Semaphore x
locked
WRITE
(MASTERID & PROCID & LOCK = 0)
Interrupt
Semaphore x
Status = 1
No
Interrupt
Semaphore x
Enabled
Yes
Interrupt
Semaphore x
MaskedStatus = 1 & Interrupt x generated
Semaphore x free
MSv41951V3
The procedure to get an interrupt when a semaphore becomes free is described hereafter.
Try to lock semaphore x
•
If the semaphore lock is obtained, no interrupt is needed.
•
If the semaphore lock fails:
•
Clear pending semaphore x interrupt status for the interrupt line in HSEM_ICR.
Re-try to lock the semaphore x again:
–
If the semaphore lock is obtained, no interrupt is needed (semaphore has been
freed between first try to lock and clear semaphore interrupt status).
–
If the semaphore lock fails, enable the semaphore x interrupt in HSEM_IER.
On semaphore x free interrupt, try to lock semaphore x
•
If the semaphore lock is obtained:
Disable the semaphore x interrupt in HSEM_IER.
Clear pending semaphore x interrupt status in HSEM_ICR.
•
If the semaphore x lock fails:
Clear pending semaphore x interrupt status in HSEM_ICR.
Try again to lock the semaphore x:
–
If the semaphore lock is obtained (semaphore has been freed between first try to
lock and semaphore interrupt status clear), disable the semaphore interrupt in
HSEM_IER.
RM0461 Rev 10
295/1290
302
Hardware semaphore (HSEM)
–
RM0461
If the semaphore lock fails, wait for semaphore free interrupt.
Note:
An interrupt does not lock the semaphore. After an interrupt, either the AHB bus master or
the process must still perform the lock procedure to lock the semaphore.
7.3.8
AHB bus master ID verification
The HSEM allows only authorized AHB bus master ID to lock and unlock semaphores.
•
The AHB bus master 2-step lock write access to the semaphore HSEM_Rx register is
checked against the valid bus master ID.
–
•
The AHB bus master 1-step lock read access from the semaphore HSEM_RLRx
register is checked against the valid bus master ID.
–
•
Accesses from unauthorized AHB bus master IDs are discarded and do not lock
the semaphore.
An unauthorized AHB bus master ID read from HSEM_RLRx returns all 0.
The semaphore unlock write access to the HSEM_CR register is checked against the
valid bus master ID. Only the valid bus master ID can write to the HSEM_CR register
and unlock any of the MASTERID semaphores.
–
Accesses from unauthorized AHB bus master IDs are discarded and do not clear
the MASTERID semaphores.
Table 57 details the relation between bus master/processor and MASTERID.
Table 57. Authorized AHB bus master ID
Bus master 0 (CPU)
MASTERID = 4
Note:
296/1290
Accesses from unauthorized AHB bus master IDs to other registers are granted.
RM0461 Rev 10
RM0461
Hardware semaphore (HSEM)
7.4
HSEM registers
Registers must be accessed using word format. Byte and half-word accesses are ignored
and have no effect on the semaphores, they generate a bus error.
7.4.1
HSEM register semaphore x (HSEM_Rx)
Address offset: 0x000 + 0x4 * x (x = 0 to 15)
Reset value: 0x0000 0000
The HSEM_Rx must be used to perform a 2-step write lock, read back, and for unlocking a
semaphore. Only write accesses with authorized AHB bus master ID is granted. Write
accesses with unauthorized AHB bus master IDs are discarded.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
LOCK
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
15
14
13
12
Res.
Res.
Res.
Res.
MASTERID[3:0]
rw
rw
rw
PROCID[7:0]
rw
rw
rw
rw
rw
rw
Bit 31 LOCK: Lock indication
This bit can be written and read by software.
0: On write free semaphore (only when MASTERID and PROCID match), on read
semaphore is free.
1: On write try to lock semaphore, on read semaphore is locked.
Bits 30:13 Reserved, must be kept at reset value.
Bit 12 Reserved, must be kept at reset value.
Bits 11:8 MASTERID[3:0]: Semaphore MASTERID
Written by software
- When the semaphore is free and the LOCK bit is at the same time written to 1 and the
MASTERID matches the AHB bus master ID.
- When the semaphore is unlocked (LOCK written to 0 and AHB bus master ID matched
MASTERID, the MASTERID is cleared to 0.
- When the semaphore is unlocked (LOCK bit written to 0 or AHB bus master ID does not
match MASTERID, the MASTERID is not affected.
- Write when LOCK bit is already 1 (semaphore locked), the MASTERID is not affected.
- An authorized read returns the stored MASTERID value.
Bits 7:0 PROCID[7:0]: Semaphore PROCID
Written by software
-When the semaphore is free and the LOCK is written to 1, and the MASTERID matches the
AHB bus master ID, PROCID is set to the written data.
- When the semaphore is unlocked, LOCK written to 0 and AHB bus master ID matched
MASTERID, the PROCID is cleared to 0.
- When the semaphore is unlocked, LOCK bit written to 0 and AHB bus master ID does not
match MASTERID, the PROCID is not affected.
- Write when LOCK bit is already 1 (semaphore locked), the PROCID is not affected.
- An authorized read returns the stored PROCID value.
RM0461 Rev 10
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302
Hardware semaphore (HSEM)
7.4.2
RM0461
HSEM read lock register semaphore x (HSEM_RLRx)
Address offset: 0x080 + 0x4 * x (x = 0 to 15)
Reset value: 0x0000 0000
Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx must be used to perform
a 1-step read lock. Only read accesses with authorized AHB bus master ID is granted. Read
accesses with unauthorized AHB bus master IDs are discarded and return 0.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
LOCK
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
11
10
9
8
7
6
5
4
3
2
1
0
r
r
r
r
15
14
13
12
Res.
Res.
Res.
Res.
MASTERID[3:0]
r
r
r
PROCID[7:0]
r
r
r
r
r
r
Bit 31 LOCK: Lock indication
This bit is read only by software at this address.
- When the semaphore is free:
A read with a valid AHB bus master ID locks the semaphore and returns 1.
- When the semaphore is locked:
A read with a valid AHB bus master ID returns 1 (the MASTERID and PROCID reflect the
already locked semaphore information).
Bits 30:13 Reserved, must be kept at reset value.
Bit 12 Reserved, must be kept at reset value.
Bits 11:8 MASTERID[3:0]: Semaphore MASTERID
This field is read only by software at this address.
On a read, when the semaphore is free, the hardware sets the MASTERID to the AHB bus
master ID reading the semaphore. The MASTERID of the AHB bus master locking the
semaphore is read.
On a read when the semaphore is locked, this field returns the MASTERID of the AHB bus
master that has locked the semaphore.
Bits 7:0 PROCID[7:0]: Semaphore processor ID
This field is read only by software at this address.
- On a read when the semaphore is free:
A read with a valid AHB bus master ID locks the semaphore and hardware sets the PROCID
to 0.
- When the semaphore is locked:
A read with a valid AHB bus master ID returns the PROCID of the AHB bus master that has
locked the semaphore.
298/1290
RM0461 Rev 10
RM0461
Hardware semaphore (HSEM)
7.4.3
HSEM interrupt enable register (HSEM_IER)
Address offset: 0x100
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
ISE[15:0]
rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 ISE[15:0]: Interrupt semaphore x enable bit (x = 0 to 15)
This bit is read and written by software.
0: Interrupt generation for semaphore x disabled (masked)
1: Interrupt generation for semaphore x enabled (not masked)
7.4.4
HSEM interrupt clear register (HSEM_ICR)
Address offset: 0x104
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
ISC[15:0]
rc_w1
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 ISC[15:0]: Interrupt semaphore x clear bit (x = 0 to 15)
This bit is written by software, and is always read 0.
0: Interrupt semaphore x status ISFx and masked status MISFx not affected.
1: Interrupt semaphore x status ISFx and masked status MISFx cleared.
7.4.5
HSEM interrupt status register (HSEM_ISR)
Address offset: 0x108
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
ISF[15:0]
r
RM0461 Rev 10
299/1290
302
Hardware semaphore (HSEM)
RM0461
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 ISF[15:0]: Interrupt semaphore x status bit before enable (mask) (x = 0 to 15)
This bit is set by hardware, and reset only by software. This bit is cleared by software writing
the corresponding HSEM_ICR bit.
0: Interrupt semaphore x status, no interrupt pending
1: Interrupt semaphore x status, interrupt pending
7.4.6
HSEM interrupt status register (HSEM_MISR)
Address offset: 0x10C
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r
r
r
r
r
r
r
r
r
r
r
r
r
r
MISF[15:0]
r
r
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 MISF[15:0]: Masked interrupt semaphore x status bit after enable (mask) (x = 0 to 15)
This bit is set by hardware and read only by software. This bit is cleared by software writing
the corresponding HSEM_ICR bit. This bit is read as 0 when semaphore x status is masked
in HSEM_IER bit x.
0: interrupt semaphore x status after masking not pending
1: interrupt semaphore x status after masking pending
7.4.7
HSEM clear register (HSEM_CR)
Address offset: 0x140
Reset value: 0x0000 0000
Only write accesses with authorized AHB bus master ID are granted. Write accesses with
unauthorized AHB bus master ID are discarded.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
KEY[15:0]
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
MASTERID[3:0]
w
w
w
w
Bits 31:16 KEY[15:0]: Semaphore clear key
This field can be written by software and is always read 0.
If this key value does not match HSEM_KEYR.KEY, semaphores are not affected.
If this key value matches HSEM_KEYR.KEY, all semaphores matching the MASTERID are
cleared to the free state.
300/1290
RM0461 Rev 10
RM0461
Hardware semaphore (HSEM)
Bits 15:13 Reserved, must be kept at reset value.
Bit 12 Reserved, must be kept at reset value.
Bits 11:8 MASTERID[3:0]: MASTERID of semaphores to be cleared
This field can be written by software and is always read 0.
This field indicates the MASTERID for which the semaphores are cleared when writing the
HSEM_CR.
Bits 7:0 Reserved, must be kept at reset value.
7.4.8
HSEM clear semaphore key register (HSEM_KEYR)
Address offset: 0x144
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
KEY[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Bits 31:16 KEY[15:0]: Semaphore clear key
This field can be written and read by software.
Key value to match when clearing semaphores.
Bits 15:0 Reserved, must be kept at reset value.
RM0461 Rev 10
301/1290
302
Reset value
0x144
Reset value
302/1290
0
0
0
0
0
0
0
0
0
0
0
HSEM_KEYR
0
0
0
0
0
0
0
0
0
RM0461 Rev 10
Reset value
0
KEY[15:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MASTERID[3:
0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
0
0
0
Res.
0
Res.
0
0
Res.
0
0
Res.
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
0
0
Res.
Reset value
0
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
0
Res.
KEY[15:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
HSEM_CR
Res.
Res.
Res.
Res.
Res.
Reset value
Res.
0x140
HSEM_MISR
Res.
0x10C
HSEM_ISR
Res.
0x108
HSEM_ICR
Res.
0x104
...
...
0
HSEM_RLR0
MASTERID
[3:0]
Reset value
0
0
HSEM_RLR1
MASTERID
[3:0]
Reset value
0
HSEM_RLR15
Reset value
0
HSEM_IER
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
LOCK
0
Res.
LOCK
LOCK
Reset value
Res.
HSEM_R15
Res.
0
Res.
Reset value
Res.
HSEM_R1
MASTERID
[3:0]
Res.
0
LOCK
0x100
0
LOCK
0x0BC
Reset value
LOCK
0x084
HSEM_R0
Res.
0x080
Res.
0x03C
Res.
0x004
Res.
0x000
Res.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Offset Register name
Res.
7.4.9
Res.
Hardware semaphore (HSEM)
RM0461
HSEM register map
Table 58. HSEM register map and reset values
MASTERID
[3:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Refer to Section 2.4 on page 62 for the register boundary addresses.
PROCID[7:0]
0
0
0
0
0
MASTERID
[3:0]
0
0
0
0
0
0
MASTERID
[3:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PROCID[7:0]
0
PROCID[7:0]
0
PROCID[7:0]
0
PROCID[7:0]
0
0
0
0
0
0
0
0
0
0
0
PROCID[7:0]
ISE[15:0]
ISC[15:0]
ISF[15:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MISF[15:0]
RM0461
General-purpose I/Os (GPIO)
8
General-purpose I/Os (GPIO)
8.1
GPIO introduction
Each general-purpose I/O port has four 32-bit configuration registers (GPIOx_MODER,
GPIOx_OTYPER, GPIOx_OSPEEDR and GPIOx_PUPDR), two 32-bit data registers
(GPIOx_IDR and GPIOx_ODR) and one 32-bit set/reset register (GPIOx_BSRR).
All GPIOs have a 32-bit locking register (GPIOx_LCKR) and two 32-bit alternate function
selection registers (GPIOx_AFRH and GPIOx_AFRL).
8.2
8.3
GPIO main features
•
Output states: push-pull or open drain + pull-up/down
•
Output data from output data register (GPIOx_ODR) or peripheral (alternate function
output)
•
Speed selection for each I/O
•
Input states: floating, pull-up/down, analog
•
Input data to input data register (GPIOx_IDR) or peripheral (alternate function input)
•
Bit set and reset register (GPIOx_ BSRR) for bitwise write access to GPIOx_ODR
•
Locking mechanism (GPIOx_LCKR) provided to freeze the I/O port configurations
•
Analog function
•
Alternate function selection registers
•
Fast toggle capable of changing every two clock cycles
•
Highly flexible pin multiplexing allowing the use of I/O pins as GPIOs or as one of
several peripheral functions
GPIO functional description
Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each
port bit of GPIO ports can be individually configured by software in several modes listed
below:
•
Input floating
•
Input pull-up
•
Input pull-down
•
Analog
•
Output open-drain with pull-up or pull-down capability
•
Output push-pull with pull-up or pull-down capability
•
Alternate function push-pull with pull-up or pull-down capability
•
Alternate function open-drain with pull-up or pull-down capability
Each I/O port bit is freely programmable, however the I/O port registers must be accessed
as 32-bit words, half-words or bytes.
RM0461 Rev 10
303/1290
333
General-purpose I/Os (GPIO)
RM0461
GPIOx_BSRR and GPIOx_BRR registers allow atomic read/modify accesses to any of the
GPIOx_ODR registers. In this way, there is no risk of an IRQ occurring between the read
and the modify access.
Figure 30 and Figure 31 show the basic structure of a standard and a 5V-tolerant I/O port
bit.
Table 59 gives the possible port bit configurations.
Figure 30. Basic structure of a standard I/O port bit
Analog
To on-chip
peripheral
Input data register
Alternate function input
Output data register
Write
Bit set/reset registers
Read
on/off
VDDIOxVDDIOx
trigger
on/off
Input driver
I/O pin
Output driver
VDDIOx
on/off
P-MOS
Output
control
Pull
down
VSS
Protection
diode
VSS
N-MOS
Read/write
VSS
From on-chip
peripheral
Protection
diode
Pull
up
Alternate function output
Push-pull,
open-drain or
disabled
Analog
MS31476V1
304/1290
RM0461 Rev 10
RM0461
General-purpose I/Os (GPIO)
Figure 31. Basic structure of a 5V-tolerant I/O port bit
To on-chip
peripheral
Alternate function input
Read/write
From on-chip
peripheral
Input data register
VDDIOx VDD_FT
TTL Schmitt
trigger
on/off
Pull
up
(1)
Protection
diode
Input driver
Output data register
Bit set/reset registers
Read
Write
on/off
I/O pin
Output driver
VDDIOx
on/off
P-MOS
Pull
down
VSS
Output
control
Protection
diode
VSS
N-MOS
VSS
Alternate function output
Push-pull,
open-drain or
disabled
1) VDD_FT is specific to 5V-tolerant I/Os and different from VDD.
ai15939e
Table 59. Port bit configurations
MODE(i)[1:0]
01
OTYPER(i)
PUPD(i)[1:0]
I/O configuration(1)
0
00
GP output
PP
0
01
GP output
PP + PU
0
10
GP output
PP + PD
0
11
1
00
GP output
OD
1
01
GP output
OD + PU
1
10
GP output
OD + PD
1
0
10
OSPEED(i)[1:0]
SPEED[1:0]
11
Reserved
Reserved (GP output OD)
00
AF
PP
0
01
AF
PP + PU
0
10
AF
PP + PD
0
11
1
00
AF
OD
1
01
AF
OD + PU
1
10
AF
OD + PD
1
11
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Table 59. Port bit configurations (continued)
MODE(i)[1:0]
00
11
I/O configuration(1)
OTYPER(i)
OSPEED(i)[1:0]
PUPD(i)[1:0]
X
XX
00
Input
Floating
X
XX
01
Input
PU
X
XX
10
Input
PD
X
XX
11
Reserved (input floating)
X
XX
00
X
XX
01
X
XX
10
X
XX
11
Input/output
Analog
Reserved
1. GP = general purpose, PP = push-pull, PU = pull-up, PD = pull-down, OD = open drain, AF = alternate function.
8.3.1
General purpose I/O (GPIO)
During and just after reset, the alternate functions are not active and most of the I/O ports
are configured in analog mode.
The debug pins listed below are in AF pull-up/pull-down after reset:
•
PA15: JTDI in input mode with pull-up
•
PA14: JTCK/SWCLK in input mode with pull-down
•
PA13: JTMS/SWDAT in input mode with pull-up
•
PB4: NJTRST in input mode with pull-up
•
PB3: JTDO in HI-Z mode no pulls.
PH3/BOOT0 is in input mode during the reset until at least the end of the option byte loading
phase (see Section 8.3.15: Using PH3 as GPIO).
When the I/O pin is configured as output, the value written to the output data register
GPIOx_ODR is output on the I/O pin. It is possible to use the output driver in push-pull mode
or open-drain mode (only the low level is driven, high level is HI-Z).
The input data register GPIOx_IDR captures the data present on the I/O pin at every AHB
clock cycle.
All GPIO pins have weak internal pull-up and pull-down resistors, which can be activated or
not depending on the value in the GPIOx_PUPDR register.
8.3.2
I/O pin alternate function multiplexer and mapping
The I/O pins are connected to on-board peripherals/modules through a multiplexer that
allows only one AF peripheral connected to each I/O pin at a time. This avoids conflict
between peripherals available on the same I/O pin.
Each I/O pin has a multiplexer with up to sixteen alternate function inputs (AF0 to AF15),
that can be configured through the registers GPIOx_AFRL (for pin 0 to 7) and GPIOx_AFRH
(for pin 8 to 15):
After reset, the multiplexer selection is alternate function 0 (AF0). I/Os are configured in
alternate function mode through GPIOx_MODER register.
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Specific alternate function assignments for each pin are detailed in the product datasheet.
In addition to this flexible I/O multiplexing architecture, each peripheral has alternate
functions mapped on different I/O pins to optimize the number of peripherals available in
smaller packages.
To use an I/O in a given configuration, the user must proceed as follows:
•
Debug function
After each device reset, these pins are assigned as alternate function pins immediately
usable by the debugger host.
•
GPIO
Configure the desired I/O as output, input or analog in the GPIOx_MODER register.
•
•
Peripheral alternate function
–
Connect the I/O to the desired AFx in the GPIOx_AFRL or GPIOx_AFRH register.
–
Select the type, pull-up/pull-down and output speed via the GPIOx_OTYPER,
GPIOx_PUPDR and GPIOx_OSPEEDR registers, respectively.
–
Configure the desired I/O as an alternate function in the GPIOx_MODER register.
Additional functions
–
For ADC, DAC and COMP, configure the desired I/O in analog mode in the
GPIOx_MODER register and configure the required function in the ADC, DAC and
COMP registers.
–
For the additional functions like RTC, WKUPx and oscillators, configure the
required function in the related RTC, PWR and RCC registers. These functions
have priority over the configuration in the standard GPIO registers.
Refer to the “Alternate function mapping” table in the product datasheet for the detailed
mapping of the alternate function I/O pins.
8.3.3
I/O port control registers
Each of the GPIO ports has four 32-bit memory-mapped control registers (GPIOx_MODER,
GPIOx_OTYPER, GPIOx_OSPEEDR and GPIOx_PUPDR) to configure up to sixteen I/Os.
GPIOx_MODER is used to select the I/O mode (input, output, AF or analog).
GPIOx_OTYPER and GPIOx_OSPEEDR are used to select the output type (push-pull or
open-drain) and speed.
GPIOx_PUPDR is used to select the pull-up/pull-down whatever the I/O direction.
8.3.4
I/O port data registers
Each GPIO has two 16-bit memory-mapped input and output data registers: GPIOx_IDR
and GPIOx_ODR.
GPIOx_ODR stores the data to be output, it is read/write accessible.
Data input through the I/O are stored into GPIOx_IDR, it is a read-only register.
8.3.5
I/O data bitwise handling
The bit set reset register (GPIOx_BSRR) is a 32-bit register that allows the application to set
and reset each individual bit in the output data register (GPIOx_ODR). GPIOx_BSRR has
twice the size of GPIOx_ODR.
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To each bit in GPIOx_ODR correspond two control bits in GPIOx_BSRR, BS(i) and BR(i):
•
When written to 1, BS(i) sets the corresponding ODR(i) bit.
•
When written to 1, BR(i) resets the ODR(i) corresponding bit.
Writing any bit to 0 in GPIOx_BSRR does not have any effect on the corresponding bit in
GPIOx_ODR. If there is an attempt to both set and reset a bit in GPIOx_BSRR, the set
action takes priority.
Using GPIOx_BSRR to change the values of individual bits in GPIOx_ODR is a “one-shot”
effect that does not lock the GPIOx_ODR bits. The GPIOx_ODR bits can always be
accessed directly. GPIOx_BSRR provides a way of performing atomic bitwise handling.
There is no software need to disable interrupts when programming GPIOx_ODR at bit level:
it is possible to modify one or more bits in a single atomic AHB write access.
8.3.6
GPIO locking mechanism
It is possible to freeze the GPIO control registers by applying a specific write sequence to
the GPIOx_LCKR register. Frozen registers are GPIOx_MODER, GPIOx_OTYPER,
GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
To write GPIOx_LCKR, a specific write/read sequence must be applied. When the right
LOCK sequence is applied to bit 16 in this register, the value of LCKR[15:0] is used to lock
the I/Os configuration (during the write sequence, LCKR[15:0] value must be the same).
When the LOCK sequence is applied to a port bit, the value of the port bit can no longer be
modified until the next MCU reset or peripheral reset.
Each GPIOx_LCKR bit freezes the corresponding bit in the control registers
GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL
and GPIOx_AFRH.
The LOCK sequence can only be performed using a word (32-bit long) access to
GPIOx_LCKR due to the fact that GPIOx_LCKR bit 16 must be set at the same time as the
[15:0] bits.
8.3.7
I/O alternate function input/output
Two registers are provided to select one of the alternate function inputs/outputs available for
each I/O: GPIOx_AFRL and GPIOx_AFRH.
With these registers, the user can connect an alternate function to some other pin as
required by the application. This means that a number of possible peripheral functions are
multiplexed on each GPIO. The application can thus select any one of the possible functions
for each I/O.
The AF selection signal being common to the alternate function input and alternate function
output, a single channel is selected for the alternate function input/output of a given I/O.
To know which functions are multiplexed on each GPIO pin, refer to the product datasheet.
8.3.8
External interrupt/wake-up lines
All ports have external interrupt capability.
To use external interrupt lines, the port must be configured in input mode.
Refer to Section 14.4.1: EXTI configurable event input wake-up.
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8.3.9
General-purpose I/Os (GPIO)
Input configuration
When the I/O port is programmed as input, the following occurs:
•
The output buffer is disabled.
•
The Schmitt trigger input is activated.
•
The pull-up and pull-down resistors are activated depending on the value in the
GPIOx_PUPDR register.
•
The data present on the I/O pin are sampled into the input data register every AHB
clock cycle.
•
A read access to the input data register provides the I/O state.
The figure below shows the input configuration of the I/O port bit.
Input data register
Figure 32. Input floating/pull-up/pull-down configurations
Read/write
Output data register
Write
Bit set/reset registers
Read
on
TTL Schmitt
trigger
input driver
VDDIOx VDDIOx
on/off
protection
diode
pull
up
I/O pin
on/off
output driver
pull
down
VSS
protection
diode
VSS
MS31477V1
8.3.10
Output configuration
When the I/O port is programmed as output, the following occurs:
•
The output buffer is enabled:
–
Open drain mode: A 0 in the Output register activates the N-MOS whereas a 1 in
the Output register leaves the port in Hi-Z (the P-MOS is never activated).
–
Push-pull mode: A 0 in the Output register activates the N-MOS whereas a 1 in the
Output register activates the P-MOS.
•
The Schmitt trigger input is activated.
•
The pull-up and pull-down resistors are activated depending on the value in the
GPIOx_PUPDR register.
•
The data present on the I/O pin are sampled into the input data register every AHB
clock cycle.
•
A read access to the input data register gets the I/O state.
•
A read access to the output data register gets the last written value.
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The figure below shows the output configuration of the I/O port bit.
Input data register
Figure 33. Output configuration
Write
Read/write
on
VDDIOx VDDIOx
TTL Schmitt
trigger
on/off
Input driver
Output data register
Bit set/reset registers
Read
pull
up
Output driver
I/O pin
VDDIOx
on/off
P-MOS
Output
control
VSS
protection
diode
N-MOS
Push-pull or
Open-drain
protection
pull
down
diode
VSS
VSS
MS31478V1
8.3.11
Alternate function configuration
When the I/O port is programmed as alternate function, the following occurs:
•
The output buffer can be configured in open-drain or push-pull mode.
•
The output buffer is driven by the signals coming from the peripheral (transmitter
enable and data).
•
The Schmitt trigger input is activated.
•
The weak pull-up and pull-down resistors are activated or not depending on the value
in the GPIOx_PUPDR register.
•
The data present on the I/O pin are sampled into the input data register every AHB
clock cycle.
•
A read access to the input data register gets the I/O state.
The figure below shows the alternate function configuration of the I/O port bit.
Figure 34. Alternate function configuration
Input data register
Alternate function input
To on-chip
peripheral
Read/write
From on-chip
peripheral
on
VDDIOxVDDIOx
TTL Schmitt
trigger
on/off
Pull
up
Input driver
Output data register
Write
Bit set/reset registers
Read
protection
diode
I/O pin
Output driver
on/off
VDD
P-MOS
Output
control
Pull
down
protection
diode
VSS V
SS
N-MOS
VSS
push-pull or
open-drain
Alternate function output
MSv34756V2
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8.3.12
General-purpose I/Os (GPIO)
Analog configuration
When the I/O port is programmed as analog configuration, the following occurs:
•
The output buffer is disabled.
•
The Schmitt trigger input is deactivated, providing zero consumption for every analog
value of the I/O pin. The output of the Schmitt trigger is forced to a constant value (0).
•
The weak pull-up and pull-down resistors are disabled by hardware.
•
Read access to the input data register gets the value 0.
The figure below shows the high-impedance, analog-input configuration of the I/O port bits.
Figure 35. High impedance analog configuration
Input data register
Analog
To on-chip
peripheral
Read/write
From on-chip
peripheral
8.3.13
Output data register
Write
Bit set/reset registers
Read
off
0
VDDIOx
TTL Schmitt
trigger
protection
diode
Input driver
I/O pin
protection
diode
VSS
Analog
MS31480V1
Using the LSE oscillator pins as GPIOs
When the LSE oscillator is switched off (default state after reset), the related oscillator pins
can be used as normal GPIOs.
When the LSE oscillator is switched on (by setting the LSEON bit in the RCC_CSR
register), the oscillator takes the control of its associated pins and the GPIO configuration of
these pins has no effect.
When the oscillator is configured in a user external clock mode, only the OSC32_IN pin is
reserved for clock input and the OSC32_OUT pin can still be used as normal GPIO.
Note:
The HSE32 OSC_IN and OSC_OUT pins are dedicated oscillator pins and cannot be used
as GPIO.
8.3.14
Using the GPIO pins in the RTC supply domain
GPIO functionality of PC13, PC14 and PC15 is lost when the core supply domain is
powered off (device enters Standby mode). In this case, if their GPIO configuration is not
bypassed by the RTC configuration, these pins are set in an analog input mode.
For details about I/O control by the RTC, refer to Section 30: Real-time clock (RTC).
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8.3.15
RM0461
Using PH3 as GPIO
PH3 may be used as boot pin (BOOT0) or as GPIO.
PH3 switches from the input mode to the analog input mode depending on the nSWBOOT0
bit in the user option byte as follows:
8.4
•
After the option byte loading phase if nSWBOOT0 = 1.
•
After reset if nSWBOOT0 = 0.
GPIO registers
This section gives a detailed description of the GPIO registers for GPIOx port,
with x = A to C and x = H.
For a summary of register bits, register address offsets and reset values, refer to Table 60 to
Table 63.
The peripheral registers can be written in word, half word or byte mode.
8.4.1
GPIOx mode register (GPIOx_MODER) (x = A to B)
Address offset: Block A: 0x0000
Address offset: Block B: 0x0400
Reset value: Block A: 0xABFF FFFF
Reset value: Block B: 0xFFFF FEBF
31
30
29
MODE15[1:0]
28
27
26
25
24
23
22
21
20
19
18
17
16
MODE14[1:0]
MODE13[1:0]
MODE12[1:0]
MODE11[1:0]
MODE10[1:0]
MODE9[1:0]
MODE8[1:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MODE7[1:0]
MODE6[1:0]
MODE5[1:0]
MODE4[1:0]
MODE3[1:0]
MODE2[1:0]
MODE1[1:0]
MODE0[1:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:0 MODEy[1:0]: Port Pxy I/O type configuration (y = 15 to 0)
These bits are written by software to configure the I/O mode.
00: Input mode
01: General purpose output mode
10: Alternate function mode
11: Analog mode (reset state)
8.4.2
GPIOx output type register (GPIOx_OTYPER) (x = A to B)
Address offset: Block A: 0x0004
Address offset: Block B: 0x0404
Reset value: 0x0000 0000
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31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OT15
OT14
OT13
OT12
OT11
OT10
OT9
OT8
OT7
OT6
OT5
OT4
OT3
OT2
OT1
OT0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
17
16
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 OTy: Port Pxy output type configuration (y = 15 to 0)
These bits are written by software to configure the I/O output type.
0: Output push-pull (reset state)
1: Output open-drain
8.4.3
GPIOx output speed register (GPIOx_OSPEEDR) (x = A to B)
Address offset: Block A: 0x0008
Address offset: Block B: 0x0408
Reset value: Block A: 0x0C00 0000
Reset value: Block B: 0x0000 00C0
31
30
29
OSPEED15[1:0]
28
OSPEED14[1:0]
27
26
OSPEED13[1:0]
25
24
OSPEED12[1:0]
23
22
OSPEED11[1:0]
21
20
OSPEED10[1:0]
19
18
OSPEED9[1:0]
OSPEED8[1:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OSPEED7[1:0]
rw
rw
OSPEED6[1:0]
rw
rw
OSPEED5[1:0]
rw
rw
OSPEED4[1:0]
OSPEED3[1:0]
OSPEED2[1:0]
rw
rw
rw
rw
rw
rw
OSPEED1[1:0]
rw
rw
OSPEED0[1:0]
rw
rw
Bits 31:0 OSPEEDy[1:0]: Port Pxy output speed configuration (y = 15 to 0)
These bits are written by software to configure the I/O output speed.
00: Low speed
01: Medium speed
10: Fast speed
11: High speed
Note: Refer to the device datasheet for the frequency specifications and the power supply
and load conditions for each speed.
8.4.4
GPIOx pull-up/pull-down register (GPIOx_PUPDR) (x = A to B)
Address offset: Block A: 0x000C
Address offset: Block B: 0x040C
Reset value: Block A: 0x6400 0000
Reset value: Block B: 0x0000 0100
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30
29
28
27
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26
25
24
23
22
21
20
19
18
17
16
PUPD15[1:0]
PUPD14[1:0]
PUPD13[1:0]
PUPD12[1:0]
PUPD11[1:0]
PUPD10[1:0]
PUPD9[1:0]
PUPD8[1:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PUPD7[1:0]
PUPD6[1:0]
PUPD5[1:0]
PUPD4[1:0]
PUPD3[1:0]
PUPD2[1:0]
PUPD1[1:0]
PUPD0[1:0]
rw
rw
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rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:0 PUPDy[1:0]: Port Pxy pull configuration (y = 15 to 0)
These bits are written by software to configure the I/O pull-up or pull-down
00: No pull-up, pull-down
01: Pull-up
10: Pull-down
11: Reserved
8.4.5
GPIOx input data register (GPIOx_IDR) (x = A to B)
Address offset: Block A: 0x0010
Address offset: Block B: 0x0410
Reset value: 0x0000 XXXX
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ID15
ID14
ID13
ID12
ID11
ID10
ID9
ID8
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 IDy: Port Pxy input data bit (y = 15 to 0)
These bits are read-only. They contain the input value of the corresponding I/O port.
8.4.6
GPIOx output data register (GPIOx_ODR) (x = A to B)
Address offset: Block A: 0x0014
Address offset: Block B: 0x0414
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OD15
OD14
OD13
OD12
OD11
OD10
OD9
OD8
OD7
OD6
OD5
OD4
OD3
OD2
OD1
OD0
rw
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rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:16 Reserved, must be kept at reset value.
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Bits 15:0 ODy: Port Pxy output data (y = 15 to 0)
These bits can be read and written by software.
Note: For atomic bit set/reset, OD bits can be individually set and/or reset by writing to the
GPIOx_BSRR and GPIOx_BRR registers.
8.4.7
GPIOx bit set/reset register (GPIOx_BSRR) (x = A to B)
Address offset: Block A: 0x0018
Address offset: Block B: 0x0418
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
BR15
BR14
BR13
BR12
BR11
BR10
BR9
BR8
BR7
BR6
BR5
BR4
BR3
BR2
BR1
BR0
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BS15
BS14
BS13
BS12
BS11
BS10
BS9
BS8
BS7
BS6
BS5
BS4
BS3
BS2
BS1
BS0
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
Bits 31:16 BRy: Port Pxy reset output data bit [15:0] in GPIOx_ODR (y = 15 to 0)
These bits are read clear-write 1. A read to these bits returns the value 0x0000.
0: No action on the corresponding GPIOx_ODR.OD[y] bit
1: Resets the corresponding GPIOx_ODR.OD[y] bit.
Note: If both BSy and BRy are set, BSy has priority.
Bits 15:0 BSy: Port Pxy set output data bit [15:0] in GPIOx_ODR (y = 15 to 0)
These bits are read clear-write 1. A read to these bits returns the value 0x0000.
0: No action on the corresponding GPIOx_ODR.OD[y] bit
1: Sets the corresponding GPIOx_ODR.OD[y] bit.
8.4.8
GPIOx configuration lock register (GPIOx_LCKR) (x = A to B)
Address offset: Block A: 0x001C
Address offset: Block B: 0x041C
Reset value: 0x0000 0000
This register is used to lock the configuration of the port bits when a correct write sequence
is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the
GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the lock
sequence has been applied on a port bit, the value of this port bit can no longer be modified
until the next MCU reset or peripheral reset.
Note:
A specific write sequence is used to write to GPIOx_LCKR. Only word access (32-bit long)
is allowed during this locking sequence.
Each lock bit freezes a specific configuration register (control and alternate function
registers).
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General-purpose I/Os (GPIO)
RM0461
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
LCKK
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LCK15
LCK14
LCK13
LCK12
LCK11
LCK10
LCK9
LCK8
LCK7
LCK6
LCK5
LCK4
LCK3
LCK2
LCK1
LCK0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:17 Reserved, must be kept at reset value.
Bit 16 LCKK: Lock key
This bit can be read any time. It can only be modified using the lock key write sequence.
0: Port configuration lock key not active
1: Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU
reset or peripheral reset.
LOCK key write sequence:
WR LCKR[16] = 1 + LCKR[15:0]
WR LCKR[16] = 0 + LCKR[15:0]
WR LCKR[16] = 1 + LCKR[15:0]
RD LCKR
RD LCKR[16] = 1 (This read operation is optional but it confirms that the lock is active.)
Note: During the LOCK key write sequence, the value of LCK[15:0] must not change.
Any error in the lock sequence aborts the lock.
After the first lock sequence on any bit of the port, any read access on the LCKK bit
returns 1 until the next MCU reset or peripheral reset.
Bits 15:0 LCKy: Port Px[15:0] lock configuration (y = 15 to 0)
These bits are read/write but can only be written when the LCKK bit is 0.
0: Port Pxy configuration not locked
1: Port Pxy configuration locked
8.4.9
GPIOx alternate function low register (GPIOx_AFRL) (x = A to B)
Address offset: Block A: 0x0020
Address offset: Block B: 0x0420
Reset value: 0x0000 0000
31
30
29
28
27
AFSEL7[3:0]
26
25
24
23
AFSEL6[3:0]
22
21
20
19
AFSEL5[3:0]
18
17
16
AFSEL4[3:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
AFSEL3[3:0]
rw
316/1290
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rw
AFSEL2[3:0]
rw
rw
rw
rw
AFSEL1[3:0]
rw
rw
RM0461 Rev 10
rw
rw
AFSEL0[3:0]
rw
rw
rw
rw
rw
RM0461
General-purpose I/Os (GPIO)
Bits 31:0 AFSELy[3:0]: Port Pxy alternate function selection (y = 7 to 0)
These bits are written by software to configure alternate function I/Os
0x0: AF0 selected
0x1: AF1 selected
0x2: AF2 selected
...
0xE: AF14 selected
0xF: AF15 selected
8.4.10
GPIOx alternate function high register (GPIOx_AFRH) (x = A to B)
Address offset: Block A: 0x0024
Address offset: Block B: 0x0424
Reset value: 0x0000 0000
31
30
29
28
27
AFSEL15[3:0]
26
25
24
23
AFSEL14[3:0]
22
21
20
19
AFSEL13[3:0]
18
17
16
AFSEL12[3:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
AFSEL11[3:0]
rw
rw
rw
AFSEL10[3:0]
rw
AFSEL9[3:0]
rw
rw
rw
AFSEL8[3:0]
rw
rw
rw
Bits 31:0 AFSELy[3:0]: Port Pxy alternate function selection (y = 15 to 8)
These bits are written by software to configure alternate function I/Os
0x0: AF0 selected
0x1: AF1 selected
0x2: AF2 selected
...
0xE: AF14 selected
0xF: AF15 selected
8.4.11
GPIOx bit reset register (GPIOx_BRR) (x = A to B)
Address offset: Block A: 0x0028
Address offset: Block B: 0x0428
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BR15
BR14
BR13
BR12
BR11
BR10
BR9
BR8
BR7
BR6
BR5
BR4
BR3
BR2
BR1
BR0
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
Bits 31:16 Reserved, must be kept at reset value.
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General-purpose I/Os (GPIO)
RM0461
Bits 15:0 BRy: Port Pxy reset output data bit [15:0] in GPIOx_ODR (y = 15 to 0)
These bits are read clear-write 1. A read to these bits returns the value 0x0000.
0: No action on the corresponding GPIOx_ODR.OD[y] bit
1: Resets the corresponding GPIOx_ODR.OD[y] bit.
8.4.12
GPIOC mode register (GPIOC_MODER)
Address offset: 0x0800
Reset value: 0xFC00 3FFF
31
30
MODE15[1:0]
29
28
27
26
25
24
23
22
21
20
19
18
17
16
MODE14[1:0]
MODE13[1:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
Res.
Res.
MODE6[1:0]
MODE5[1:0]
MODE4[1:0]
MODE3[1:0]
MODE2[1:0]
MODE1[1:0]
MODE0[1:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:30 MODE15[1:0]: Port PC15 IO type configuration
Bits 29:28 MODE14[1:0]: Port PC14 IO type configuration
Bits 27:26 MODE13[1:0]: Port PC13 IO type configuration
Bits 25:14 Reserved, must be kept at reset value.
Bits 13:12 MODE6[1:0]: Port PC6 IO type configuration
Bits 11:10 MODE5[1:0]: Port PC5 IO type configuration
Bits 9:8 MODE4[1:0]: Port PC4 IO type configuration
Bits 7:6 MODE3[1:0]: Port PC3 IO type configuration
Bits 5:4 MODE2[1:0]: Port PC2 IO type configuration
Bits 3:2 MODE1[1:0]: Port PC1 IO type configuration
Bits 1:0 MODE0[1:0]: Port PC0 IO type configuration
These bits are written by software to configure the I/O mode.
00: Input mode
01: General purpose output mode
10: Alternate function mode
11: Analog mode (reset state)
8.4.13
GPIOC output type register (GPIOC_OTYPER)
Address offset: 0x0804
Reset value: 0x0000 0000
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rw
RM0461
General-purpose I/Os (GPIO)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OT15
OT14
OT13
Res.
Res.
Res.
Res.
Res.
Res.
OT6
OT5
OT4
OT3
OT2
OT1
OT0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:13 OTy: Port PCy output type configuration (y = 15 to 13)
These bits are written by software to configure the I/O output type.
0: Output push-pull (reset state)
1: Output open-drain
Bits 12:7 Reserved, must be kept at reset value.
Bits 6:0 OTy: Port PCy output type configuration (y = 6 to 0)
8.4.14
GPIOC output speed register (GPIOC_OSPEEDR)
Address offset: 0x0808
Reset value: 0x0000 0000
31
30
29
OSPEED15[1:0]
rw
rw
15
14
Res.
Res.
28
OSPEED14[1:0]
rw
rw
13
12
OSPEED6[1:0]
rw
rw
27
26
OSPEED13[1:0]
rw
rw
11
10
OSPEED5[1:0]
rw
rw
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
9
8
7
6
5
4
3
2
1
0
OSPEED4[1:0]
rw
OSPEED3[1:0]
rw
rw
OSPEED2[1:0]
rw
rw
rw
OSPEED1[1:0]
rw
rw
OSPEED0[1:0]
rw
rw
Bits 31:30 OSPEED15[1:0]: Port PC15 output speed configuration
Bits 29:28 OSPEED14[1:0]: Port PC14 output speed configuration
Bits 27:26 OSPEED13[1:0]: Port PC13 output speed configuration
Bits 25:14 Reserved, must be kept at reset value.
Bits 13:12 OSPEED6[1:0]: Port PC6 output speed configuration
Bits 11:10 OSPEED5[1:0]: Port PC5 output speed configuration
Bits 9:8 OSPEED4[1:0]: Port PC4 output speed configuration
Bits 7:6 OSPEED3[1:0]: Port PC3 output speed configuration
Bits 5:4 OSPEED2[1:0]: Port PC2 output speed configuration
Bits 3:2 OSPEED1[1:0]: Port PC1 output speed configuration
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General-purpose I/Os (GPIO)
RM0461
Bits 1:0 OSPEED0[1:0]: Port PC0 output speed configuration
These bits are written by software to configure the I/O output speed.
00: Low speed
01: Medium speed
10: Fast speed
11: High speed
Note: Refer to the device datasheet for the frequency specifications and the power supply
and load conditions for each speed.
8.4.15
GPIOC pull-up/pull-down register (GPIOC_PUPDR)
Address offset: 0x080C
Reset value: 0x0000 0000
31
30
PUPD15[1:0]
26
25
24
23
22
21
20
19
18
17
16
PUPD14[1:0]
29
28
PUPD13[1:0]
27
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
Res.
Res.
PUPD6[1:0]
PUPD5[1:0]
PUPD4[1:0]
PUPD3[1:0]
PUPD2[1:0]
PUPD1[1:0]
PUPD0[1:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:30 PUPD15[1:0]: Port PC15 pull configuration
Bits 29:28 PUPD14[1:0]: Port PC14 pull configuration
Bits 27:26 PUPD13[1:0]: Port PC13 pull configuration
Bits 25:14 Reserved, must be kept at reset value.
Bits 13:12 PUPD6[1:0]: Port PC6 pull configuration
Bits 11:10 PUPD5[1:0]: Port PC5 pull configuration
Bits 9:8 PUPD4[1:0]: Port PC4 pull configuration
Bits 7:6 PUPD3[1:0]: Port PC3 pull configuration
Bits 5:4 PUPD2[1:0]: Port PC2 pull configuration
Bits 3:2 PUPD1[1:0]: Port PC1 pull configuration
Bits 1:0 PUPD0[1:0]: Port PC0 pull configuration
These bits are written by software to configure the I/O pull-up or pull-down.
00: No pull-up, pull-down
01: Pull-up
10: Pull-down
11: Reserved
8.4.16
GPIOC input data register (GPIOC_IDR)
Address offset: 0x0810
Reset value: 0x0000 XXXX
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RM0461 Rev 10
rw
RM0461
General-purpose I/Os (GPIO)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ID15
ID14
ID13
Res.
Res.
Res.
Res.
Res.
Res.
ID6
ID5
ID4
ID3
ID2
ID1
ID0
r
r
r
r
r
r
r
r
r
r
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:13 IDy: Port PCy input data bit (y = 15 to 13)
These bits are read-only. They contain the input value of the corresponding I/O port.
Bits 12:7 Reserved, must be kept at reset value.
Bits 6:0 IDy: Port PCy input data bit (y = 6 to 0)
8.4.17
GPIOC output data register (GPIOC_ODR)
Address offset: 0x0814
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OD15
OD14
OD13
Res.
Res.
Res.
Res.
Res.
Res.
OD6
OD5
OD4
OD3
OD2
OD1
OD0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:13 ODy: Port PCy output data bit (y = 15 to 13)
These bits can be read and written by software.
Note: For atomic bit set/reset, OD bits can be individually set and/or reset by writing to the
GPIOC_BSRR and GPIOC_BRR registers.
Bits 12:7 Reserved, must be kept at reset value.
Bits 6:0 ODy: Port PCy output data bit (y = 6 to 0)
8.4.18
GPIOC bit set/reset register (GPIOC_BSRR)
Address offset: 0x0818
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
Res.
Res.
Res.
Res.
Res.
Res.
BR15
BR14
BR13
rc_w1
rc_w1
rc_w1
22
21
20
19
18
17
16
BR6
BR5
BR4
BR3
BR2
BR1
BR0
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BS15
BS14
BS13
Res.
Res.
Res.
Res.
Res.
Res.
BS6
BS5
BS4
BS3
BS2
BS1
BS0
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
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General-purpose I/Os (GPIO)
RM0461
Bits 31:29 BRy: Port PCy reset output data bit [y] in GPIOC_ODR (y = 15 to 13)
These bits are read clear-write 1. A read to these bits returns the value 0.
0: No action on the corresponding GPIOC_ODR.OD0
1: Resets the corresponding GPIOC_ODR.OD0.
Note: If both BS0 and BR0 are set, BS0 has priority.
Bits 28:23 Reserved, must be kept at reset value.
Bits 22:16 BRy: Port PCy reset output data bit [y] in GPIOC_ODR (y = 6 to 0)
Bits 15:13 BSy: Port PCy set output data bit [y] in GPIOC_ODR (y = 15 to 13)
These bits are read clear-write 1. A read to these bits returns the value 0.
0: No action on the corresponding GPIOC_ODR.OD0
1: Resets the corresponding GPIOC_ODR.OD0.
Note: If both BS0 and BR0 are set, BS0 has priority.
Bits 12:7 Reserved, must be kept at reset value.
Bits 6:0 BSy: Port PCy set output data bit [y] in GPIOC_ODR (y = 6 to 0)
8.4.19
GPIOC configuration lock register (GPIOC_LCKR)
Address offset: 0x081C
Reset value: 0x0000 0000
This register is used to lock the configuration of the port bits when a correct write sequence
is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the
GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the lock
sequence has been applied on a port bit, the value of this port bit can no longer be modified
until the next MCU reset or peripheral reset.
Note:
A specific write sequence is used to write to the GPIOC_LCKR register. Only word access
(32-bit long) is allowed during this locking sequence.
Each lock bit freezes a specific configuration register (control and alternate function
registers).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
LCKK
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LCK15
LCK14
LCK13
Res.
Res.
Res.
Res.
Res.
Res.
LCK6
LCK5
LCK4
LCK3
LCK2
LCK1
LCK0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:17 Reserved, must be kept at reset value.
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RM0461
General-purpose I/Os (GPIO)
Bit 16 LCKK: Lock key
This bit can be read any time. It can only be modified using the lock key write sequence.
0: Port PC configuration lock key not active
1: Port PC configuration lock key active. GPIOC_LCKR is locked until the next MCU reset or
peripheral reset.
LOCK key write sequence:
WR LCKR[16] = 1 + LCKR[15:0]
WR LCKR[16] = 0 + LCKR[15:0]
WR LCKR[16] = 1 + LCKR[15:0]
RD LCKR
RD LCKR[16] = 1 (This read operation is optional but it confirms that the lock is active.)
Note: During the LOCK key write sequence, the value of LCK[15:0] must not change.
Any error in the lock sequence aborts the lock.
After the first lock sequence on any bit of the port, any read access on the LCKK bit
returns 1 until the next MCU reset or peripheral reset.
Bits 15:13 LCKy: Port PCy lock configuration (y = 15 to 13)
This bit is read/write but can only be written when the LCKK bit is 0.
0: Port PCy configuration not locked
1: Port PCy configuration locked
Bits 12:7 Reserved, must be kept at reset value.
Bits 6:0 LCKy: Port PCy lock configuration (y = 6 to 0)
8.4.20
GPIOC alternate function low register (GPIOC_AFRL)
Address offset: 0x0820
Reset value: 0x0000 0000
31
30
29
28
Res.
Res.
Res.
Res.
27
rw
15
14
13
12
11
AFSEL3[3:0]
rw
rw
rw
26
25
24
23
AFSEL6[3:0]
rw
rw
rw
rw
10
9
8
7
AFSEL2[3:0]
rw
rw
rw
rw
22
21
20
19
AFSEL5[3:0]
rw
rw
rw
rw
6
5
4
3
AFSEL1[3:0]
rw
rw
rw
rw
18
17
16
AFSEL4[3:0]
rw
rw
rw
2
1
0
AFSEL0[3:0]
rw
rw
rw
rw
rw
Bits 31:28 Reserved, must be kept at reset value.
Bits 27:24 AFSEL6[3:0]: Port PC6 alternate function selection
Bits 23:20 AFSEL5[3:0]: Port PC5 alternate function selection
Bits 19:16 AFSEL4[3:0]: Port PC4 alternate function selection
Bits 15:12 AFSEL3[3:0]: Port PC3 alternate function selection
Bits 11:8 AFSEL2[3:0]: Port PC2 alternate function selection
Bits 7:4 AFSEL1[3:0]: Port PC1 alternate function selection
RM0461 Rev 10
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General-purpose I/Os (GPIO)
RM0461
Bits 3:0 AFSEL0[3:0]: Port PC0 alternate function selection
These bits are written by software to configure alternate function I/Os.
0x0: AF0 selected
0x1: AF1 selected
0x2: AF2 selected
...
0xE: AF14 selected
0xF: AF15 selected
8.4.21
GPIOC alternate function high register (GPIOC_AFRH)
Address offset: 0x0824
Reset value: 0x0000 0000
31
30
29
28
27
AFSEL15[3:0]
26
25
24
23
AFSEL14[3:0]
22
21
20
AFSEL13[3:0]
19
18
17
16
Res.
Res.
Res.
Res.
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Bits 31:28 AFSEL15[3:0]: Port PC15 alternate function selection
Bits 27:24 AFSEL14[3:0]: Port PC14 alternate function selection
Bits 23:20 AFSEL13[3:0]: Port PC13 alternate function selection
These bits are written by software to configure alternate function I/Os.
0x0: AF0 selected
0x1: AF1 selected
0x2: AF2 selected
...
0xE: AF14 selected
0xF: AF15 selected
Bits 19:0 Reserved, must be kept at reset value.
8.4.22
GPIOC bit reset register (GPIOC_BRR)
Address offset: 0x0828
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BR15
BR14
BR13
Res.
Res.
Res.
Res.
Res.
Res.
BR6
BR5
BR4
BR3
BR2
BR1
BR0
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
Bits 31:16 Reserved, must be kept at reset value.
324/1290
RM0461 Rev 10
RM0461
General-purpose I/Os (GPIO)
Bits 15:13 BRy: Port PCy reset output data bit [15] in GPIOC_ODR (y = 15 to 13)
These bits are read clear-write 1. A read to this bit returns the value 0.
0: No action on the corresponding GPIOC_ODR.OD0
1: Resets the corresponding GPIOC_ODR.OD0.
Bits 12:7 Reserved, must be kept at reset value.
Bits 6:0 BRy: Port PCy reset output data bit [6] in GPIOC_ODR (y = 6 to 0)
8.4.23
GPIOH mode register (GPIOH_MODER)
Address offset: 0x1C00
Reset value: 0x0000 00C0
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
MODE3[1:0]
rw
rw
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:6 MODE3[1:0]: Port PH3 IO type configuration
These bits are written by software to configure the I/O mode.
00: Input mode
01: General purpose output mode
10: Alternate function mode
11: Analog mode (reset state)
Bits 5:0 Reserved, must be kept at reset value.
8.4.24
GPIO H output type register (GPIOH_OTYPER)
Address offset: 0x1C04
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
OT3
Res.
Res.
Res.
rw
Bits 31:4 Reserved, must be kept at reset value.
Bit 3 OT3: Port PH3 output type configuration
These bits are written by software to configure the I/O output type.
0: Output push-pull (reset state)
1: Output open-drain
RM0461 Rev 10
325/1290
333
General-purpose I/Os (GPIO)
RM0461
Bits 2:0 Reserved, must be kept at reset value.
8.4.25
GPIOH output speed register (GPIOH_OSPEEDR)
Address offset: 0x1C08
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
7
6
15
14
13
12
11
10
9
8
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
OSPEED3[1:0]
rw
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
rw
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:6 OSPEED3[1:0]: Port PH3 output speed configuration
These bits are written by software to configure the I/O output speed.
00: Low speed
01: Medium speed
10: Fast speed
11: High speed
Note: Refer to the device datasheet for the frequency specifications and the power supply
and load conditions for each speed.
Bits 5:0 Reserved, must be kept at reset value.
8.4.26
GPIOH pull-up/pull-down register (GPIOH_PUPDR)
Address offset: 0x1C0C
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
7
6
15
14
13
12
11
10
9
8
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PUPD3[1:0]
rw
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
rw
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:6 PUPD3[1:0]: Port PH3 pull configuration
These bits are written by software to configure the I/O pull-up or pull-down.
00: No pull-up, pull-down
01: Pull-up
10: Pull-down
11: Reserved
Bits 5:0 Reserved, must be kept at reset value.
326/1290
RM0461 Rev 10
RM0461
General-purpose I/Os (GPIO)
8.4.27
GPIOH input data register (GPIOH_IDR)
Address offset: 0x1C10
Reset value: 0x0000 000X
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
ID3
Res.
Res.
Res.
r
Bits 31:4 Reserved, must be kept at reset value.
Bit 3 ID3: Port PH3 input data bit
This bit is read-only. It contains the input value of the corresponding I/O port.
Bits 2:0 Reserved, must be kept at reset value.
8.4.28
GPIOH output data register (GPIOH_ODR)
Address offset: 0x1C14
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
OD3
Res.
Res.
Res.
rw
Bits 31:4 Reserved, must be kept at reset value.
Bit 3 OD3: Port PH3 output data
This bit can be read and written by software.
Note: For atomic bit set/reset, OD bits can be individually set and/or reset by writing to the
GPIOH_BSRR and GPIOH_BRR registers.
Bits 2:0 Reserved, must be kept at reset value.
8.4.29
GPIO H bit set/reset register (GPIOH_BSRR)
Address offset: 0x1C18
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
BR3
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
BS3
Res.
Res.
Res.
rc_w1
rc_w1
RM0461 Rev 10
327/1290
333
General-purpose I/Os (GPIO)
RM0461
Bits 31:20 Reserved, must be kept at reset value.
Bit 19 BR3: Port PH3 reset output data bit [3] in GPIOH_ODR
This bit is read clear-write 1. A read to this bit returns the value 0.
0: No action on the corresponding GPIOH_ODR.OD3
1: Resets the corresponding GPIOH_ODR.OD3.
Note: If both BS3 and BR3 are set, BS3 has priority.
Bits 18:4 Reserved, must be kept at reset value.
Bit 3 BS3: Port PH3 set output data bit [3] in GPIOH_ODR
This bit is read clear-write 1. A read to this bit returns the value 0.
0: No action on the corresponding GPIOH_ODR.OD3
1: Sets the corresponding GPIOH_ODR.OD3.
Bits 2:0 Reserved, must be kept at reset value.
8.4.30
GPIOH configuration lock register (GPIOH_LCKR)
Address offset: 0x1C1C
Reset value: 0x0000 0000
This register is used to lock the configuration of the port bits when a correct write sequence
is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the
GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the lock
sequence has been applied on a port bit, the value of this port bit can no longer be modified
until the next MCU reset or peripheral reset.
Note:
A specific write sequence is used to write to the GPIOH_LCKR register. Only word access
(32-bit long) is allowed during this locking sequence.
Each lock bit freezes a specific configuration register (control and alternate function
registers).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
LCKK
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
LCK3
Res.
Res.
Res.
rw
rw
Bits 31:17 Reserved, must be kept at reset value.
328/1290
RM0461 Rev 10
RM0461
General-purpose I/Os (GPIO)
Bit 16 LCKK: Lock key
This bit can be read any time. It can only be modified using the lock key write sequence.
0: Port PH configuration lock key not active
1: Port PH configuration lock key active. GPIOH_LCKR is locked until the next MCU reset or
peripheral reset.
LOCK key write sequence:
WR LCKR[16] = 1 + LCKR[15:0]
WR LCKR[16] = 0 + LCKR[15:0]
WR LCKR[16] = 1 + LCKR[15:0]
RD LCKR
RD LCKR[16] = 1 (This read operation is optional but it confirms that the lock is active.)
Note: During the LOCK key write sequence, the value of LCK[15:0] must not change.
Any error in the lock sequence aborts the lock.
After the first lock sequence on any bit of the port, any read access on the LCKK bit
returns 1 until the next MCU reset or peripheral reset.
Bits 15:4 Reserved, must be kept at reset value.
Bit 3 LCK3: Port PH3 lock configuration
This bit is read/write but can only be written when the LCKK bit is 0.
0: Port PH3 configuration not locked
1: Port PH3 configuration locked
Bits 2:0 Reserved, must be kept at reset value.
8.4.31
GPIOH alternate function low register (GPIOH_AFRL)
Address offset: 0x1C20
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
14
13
12
15
AFSEL3[3:0]
rw
rw
rw
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:12 AFSEL3[3:0]: Port PH3 alternate function selection
These bits are written by software to configure alternate function I/Os.
0x0: AF0 selected
0x1: AF1 selected
0x2: AF2 selected
...
0xE: AF14 selected
0xF: AF15 selected
Bits 11:0 Reserved, must be kept at reset value.
RM0461 Rev 10
329/1290
333
General-purpose I/Os (GPIO)
8.4.32
RM0461
GPIOH bit reset register (GPIOH_BRR)
Address offset: 0x1C28
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
BR3
Res.
Res.
Res.
rc_w1
Bits 31:4 Reserved, must be kept at reset value.
Bit 3 BR3: Port PH3 reset output data bit [3] in GPIOH_ODR
This bit is read clear-write 1. A read to this bit returns the value 0.
0: No action on the corresponding GPIOH_ODR.OD3
1: Resets the corresponding GPIOH_ODR.OD3.
Bits 2:0 Reserved, must be kept at reset value.
8.4.33
GPIOA register map
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
GPIOA_OTYPER
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
OT2
OT1
OT0
0
0
0
0
OSPEED0[1:0]
OT3
OT4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GPIOA_IDR
RM0461 Rev 10
ID15
ID14
ID13
ID12
ID11
ID10
ID9
ID8
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
OD15
OD14
OD13
OD12
OD11
OD10
OD9
OD8
OD7
OD6
OD5
OD4
OD3
OD2
OD1
OD0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
GPIOA_ODR
PUPD0[1:0]
0
PUPD1[1:0]
0
PUPD2[1:0]
0
PUPD3[1:0]
0
PUPD4[1:0]
1
PUPD5[1:0]
0
PUPD6[1:0]
0
PUPD7[1:0]
1
PUPD8[1:0]
1
PUPD9[1:0]
0
Res.
0
Res.
OSPEED1[1:0]
OT5
OT6
0
OSPEED2[1:0]
OT7
0
OSPEED3[1:0]
0
OSPEED4[1:0]
OT8
0
OT9
OT11
OT10
OT12
0
OSPEED5[1:0]
OT13
OT14
0
OSPEED6[1:0]
OT15
OSPEED7[1:0]
OSPEED8[1:0]
OSPEED9[1:0]
OSPEED10[1:0]
0
Reset value
Reset value
330/1290
0
0
Reset value
0x0014
0
0
0
Res.
0
0
Res.
0
0
GPIOA_PUPDR
PUPD11[1:0]
PUPD10[1:0]
0
0
Res.
0
0
Res.
0
0
Res.
0
0
Res.
PUPD12[1:0]
0
0
Res.
0
0
Res.
PUPD13[1:0]
0
0
Res.
1
OSPEED11[1:0]
OSPEED12[1:0]
OSPEED13[1:0]
OSPEED14[1:0]
1
PUPD14[1:0]
0
0
Res.
0x0010
0
0
Res.
0x000C
0
0
Res.
0
0
PUPD15[1:0]
Reset value
0
Res.
GPIOA_OSPEEDR
0
Res.
0x0008
OSPEED15[1:0]
Reset value
MODE0[1:0]
1
MODE1[1:0]
1
MODE2[1:0]
1
MODE3[1:0]
1
MODE4[1:0]
1
MODE5[1:0]
1
MODE6[1:0]
1
MODE7[1:0]
0
MODE8[1:0]
1
MODE9[1:0]
0
Res.
MODE10[1:0]
1
MODE11[1:0]
0
Res.
MODE12[1:0]
1
Res.
MODE13[1:0]
Reset value
Res.
MODE14[1:0]
MODE15[1:0]
0x0004
GPIOA_MODER
Res.
0x0000
Res.
Offset Register name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 60. GPIOA register map and reset values
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GPIOB_BSRR
BR10
BR9
BR8
BR7
BR6
BR5
BR4
BR3
BR2
BR1
BR0
BS15
BS14
BS13
BS12
BS11
BS10
BS9
BS8
BS7
BS6
BS5
BS4
BS3
BS2
BS1
BS0
0x0418
BR11
0x0414
GPIOB_ODR
RM0461 Rev 10
OD10
OD9
OD8
OD7
OD6
OD5
OD4
OD3
OD2
OD1
OD0
Reset value
OD11
0
0
0
0
0
0
0
0
GPIOB_IDR
ID0
1
ID1
0
ID2
0
ID3
0
ID4
0
ID5
0
ID6
0
ID7
0
ID8
0
ID9
0
ID10
0
ID11
0
ID12
Reset value
OD12
1
0
1
0
1
1
1
1
1
1
GPIOB_OTYPER
0
0
0
0
0
0
0
0
0
OT10
0
0
0
0
OT8
0
0
0
1
0
0
1
0
0
0
0
0
OT1
OT0
MODE0[1:0]
MODE1[1:0]
0
0
0
0
0
0
0
0
0
0
GPIOA_BRR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
BR15
BR14
BR13
BR12
BR11
BR10
BR9
BR8
BR7
BR6
BR5
BR4
BR3
BR2
BR1
BR0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OSPEED0[1:0]
OT2
0
0
OT3
MODE2[1:0]
0
0
OSPEED1[1:0]
OT4
0
0
OT5
MODE3[1:0]
0
0
OSPEED2[1:0]
OT6
MODE4[1:0]
MODE5[1:0]
MODE6[1:0]
0
0
OT7
OSPEED3[1:0]
OT9
OSPEED4[1:0]
OT11
OSPEED5[1:0]
OT12
OSPEED6[1:0]
0
OT13
MODE7[1:0]
MODE8[1:0]
0
0
PUPD0[1:0]
1
Res.
0
0
PUPD1[1:0]
1
Res.
0
0
PUPD2[1:0]
1
MODE9[1:0]
0
0
PUPD3[1:0]
1
Res.
0
0
PUPD4[1:0]
1
Res.
0
0
PUPD5[1:0]
1
OT14
OSPEED7[1:0]
1
MODE10[1:0]
0
0
PUPD6[1:0]
0
ID13
0
OD13
0
PUPD7[1:0]
1
OT15
Reset value
ID14
0
OSPEED8[1:0]
1
Res.
0
0
OD14
0
PUPD8[1:0]
1
Res.
0
0
ID15
0
Res.
0
OSPEED9[1:0]
1
MODE11[1:0]
0
Res.
GPIOA_BSRR
BR15
BR14
BR13
BR12
BR11
BR10
BR9
BR8
BR7
BR6
BR5
BR4
BR3
BR2
BR1
BR0
BS15
BS14
BS13
BS12
BS11
BS10
BS9
BS8
BS7
BS6
BS5
BS4
BS3
BS2
BS1
BS0
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GPIOA_LCKR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
LCKK
LCK15
LCK14
LCK13
LCK12
LCK11
LCK10
LCK9
LCK8
LCK7
LCK6
LCK5
LCK4
LCK3
LCK2
LCK1
LCK0
Reset value
OD15
0
Res.
0
PUPD9[1:0]
1
Res.
0
0
Res.
0
Res.
0
OSPEED10[1:0]
1
Res.
0
0
Res.
0
Res.
0
PUPD10[1:0]
1
MODE12[1:0]
0
0
Res.
0
Res.
0
OSPEED11[1:0]
1
Res.
0
0
Res.
0
Res.
0
PUPD11[1:0]
1
Res.
0
0
Res.
0
Res.
0
OSPEED12[1:0]
0
0
Res.
0
Res.
0
PUPD12[1:0]
1
MODE13[1:0]
0
0
Res.
0
Res.
1
Res.
AFSEL15[3:0] AFSEL14[3:0] AFSEL13[3:0] AFSEL12[3:0] AFSEL11[3:0] AFSEL10[3:0] AFSEL9[3:0] AFSEL8[3:0]
Reset value
0
Res.
0
Res.
0
OSPEED13[1:0]
1
Res.
GPIOA_AFRH
0
Res.
0
PUPD13[1:0]
1
Res.
0
0
Res.
0
Res.
1
MODE14[1:0]
1
Res.
Reset value
0
Res.
0
Res.
Reset value
OSPEED14[1:0]
AFSEL7[3:0] AFSEL6[3:0] AFSEL5[3:0] AFSEL4[3:0] AFSEL3[3:0] AFSEL2[3:0] AFSEL1[3:0] AFSEL0[3:0]
0
Res.
Reset value
Res.
GPIOB_OSPEEDR
PUPD14[1:0]
GPIOB_PUPDR
Res.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Offset Register name
Res.
MODE15[1:0]
Reset value
GPIOA_AFRL
0
Res.
0x0410
BR12
0x040C
BR13
0x0408
Reset value
Res.
0x0404
GPIOB_MODER
Res.
0x0400
OSPEED15[1:0]
8.4.34
PUPD15[1:0]
0x0028
Res.
0x0024
Res.
0x0020
Res.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Offset Register name
Res.
0x001C
BR14
0x0018
BR15
RM0461
General-purpose I/Os (GPIO)
Table 60. GPIOA register map and reset values (continued)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Refer to Section 2.4 for the register boundary addresses.
GPIOB register map
Table 61. GPIOB register map and reset values
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
331/1290
333
0x081C
0x0820
332/1290
GPIOC_AFRL
Reset value
Reset value
0
0
0
0
0
AFSEL6[3:0] AFSEL5[3:0] AFSEL4[3:0] AFSEL3[3:0] AFSEL2[3:0] AFSEL1[3:0] AFSEL0[3:0]
0
0
BR4
BR3
BR2
BR1
BR0
BS15
BS14
BS13
0
0
0
0
0
0
0
0
0
Res.
0
Res.
0
Res.
0
Res.
0
LCKK
0
RM0461 Rev 10
LCK15
LCK14
LCK13
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BS6
BS5
BS4
BS3
BS2
BS1
BS0
0
0
0
0
0
0
0
LCK5
LCK4
LCK3
LCK2
LCK1
LCK0
OD6
OD5
OD4
OD3
OD2
OD1
OD0
Res.
0
0
ID0
0
ID1
0
ID2
0
ID3
0
ID4
0
ID5
0
Res.
1
1
1
1
1
1
1
1
Res.
0
0
0
0
0
0
0
0
0
OT1
OT0
0
MODE0[1:0]
MODE1[1:0]
0
0
0
0
0
GPIOB_BRR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
BR15
BR14
BR13
BR12
BR11
BR10
BR9
BR8
BR7
BR6
BR5
BR4
BR3
BR2
BR1
BR0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OSPEED0[1:0]
OT2
MODE2[1:0]
0
0
OT3
OSPEED1[1:0]
OT4
OSPEED2[1:0]
0
OT5
MODE3[1:0]
MODE4[1:0]
0
0
PUPD0[1:0]
1
Res.
0
0
PUPD1[1:0]
1
Res.
0
0
PUPD2[1:0]
OSPEED3[1:0]
OSPEED4[1:0]
1
OT6
0
PUPD3[1:0]
0
ID6
0
Res.
PUPD4[1:0]
0
LCK6
0
MODE5[1:0]
0
0
Res.
0
0
0
Res.
1
Res.
0
0
Res.
0
0
Res.
0
Res.
0
0
Res.
x
0
Res.
x
OSPEED5[1:0]
0
0
Res.
x
0
PUPD5[1:0]
0
0
Res.
0
Res.
0
0
Res.
0
0
Res.
0
Res.
LCK7
LCK6
LCK5
LCK4
LCK3
LCK2
LCK1
LCK0
LCK12
LCK8
LCK13
LCK9
LCK14
LCK11
LCK15
LCK10
LCKK
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
1
Res.
0
Res.
Res.
0
Res.
0
Res.
0
Res.
MODE6[1:0]
Res.
Res.
0
Res.
Res.
Res.
0
Res.
1
Res.
OT13
0
OSPEED6[1:0]
OT14
0
Res.
0
Res.
0
Res.
0
PUPD6[1:0]
OT15
0
Res.
Res.
Res.
0
0
Res.
ID13
Res.
Res.
Res.
Res.
Res.
0
0
Res.
OD13
Reset value
ID14
Reset value
ID15
Res.
Reset value
OD14
Res.
Res.
Res.
Res.
0
0
OD15
Res.
Res.
Res.
Res.
Res.
Res.
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
0
Res.
Res.
Res.
Res.
Res.
Res.
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
0
Res.
Res.
Res.
Res.
Res.
Res.
0
0
Res.
Res.
Res.
Res.
Res.
0
0
Res.
BR5
0
Res.
Res.
Res.
Res.
Res.
0
Res.
Reset value
Res.
BR6
Res.
Res.
Res.
MODE13[1:0]
0
0
Res.
Res.
GPIOC_IDR
Res.
0
Res.
0
Res.
Res.
GPIOC_OTYPER
Res.
0
0
Res.
0
0
Res.
1
Res.
1
Res.
AFSEL15[3:0] AFSEL14[3:0] AFSEL13[3:0] AFSEL12[3:0] AFSEL11[3:0] AFSEL10[3:0] AFSEL9[3:0] AFSEL8[3:0]
Reset value
0
Res.
0
OSPEED13[1:0]
1
Res.
0
PUPD13[1:0]
1
Res.
GPIOB_AFRH
0
Res.
0
Res.
1
MODE14[1:0]
1
Res.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
Res.
Reset value
0
Res.
0
Res.
0
Res.
OSPEED14[1:0]
MODE15[1:0]
Reset value
Res.
Reset value
0
Res.
0
Res.
GPIOC_MODER
Res.
AFSEL7[3:0] AFSEL6[3:0] AFSEL5[3:0] AFSEL4[3:0] AFSEL3[3:0] AFSEL2[3:0] AFSEL1[3:0] AFSEL0[3:0]
0
Res.
Reset value
PUPD14[1:0]
GPIOC_PUPDR
Res.
0
Res.
0
Res.
Reset value
Res.
GPIOC_BSRR
BR13
GPIOC_OSPEEDR
OSPEED15[1:0]
Reset value
GPIOB_AFRL
0
Res.
Res.
GPIOC_LCKR
Res.
0x0818
GPIOC_ODR
Res.
0x0814
Res.
0x0810
Res.
0x080C
PUPD15[1:0]
0x0808
Res.
0x0804
Res.
Offset Register name
Res.
8.4.35
Res.
0x0428
BR14
0x0424
BR15
0x0420
Res.
0x0800
GPIOB_LCKR
Res.
0x041C
Res.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Offset Register name
Res.
General-purpose I/Os (GPIO)
RM0461
Table 61. GPIOB register map and reset values (continued)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Refer to Section 2.4 for the register boundary addresses.
GPIOC register map
Table 62. GPIOC register map and reset values
0
x
x
x
x
x
x
x
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x1C28
GPIOH_BRR
RM0461 Rev 10
0
Reserved.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
BR3
Res.
Res.
Res.
0
Res.
AFSEL3[3:0]
Res.
0
Res.
0
Res.
Res.
Reset value
0
Res.
Res.
0
Res.
Res.
Res.
Res.
Reset value
Res.
Res.
Res.
OD3
Reset value
BS3
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
ID3
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
LCK3
Res.
Res.
OSPEED3[1:0]
Res.
0
Res.
0
Res.
0
Res.
PUPD3[1:0]
Res.
Res.
Res.
Res.
Res.
Res.
OT3
Res.
Res.
Res.
MODE3[1:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
1
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
1
Res.
Res.
Reset value
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
BR2
BR1
BR0
Res.
Res.
BR3
Res.
Res.
Res.
Res.
Res.
BR4
Res.
Res.
Res.
Res.
Res.
BR5
Res.
BR13
Res.
Res.
BR14
BR6
Res.
BR15
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
LCKK
Res.
Res.
Reset value
Res.
Res.
Res.
Reset value
Res.
Reserved
Res.
Reset value
Res.
GPIOC_BRR
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
BR3
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
AFSEL15[3:0] AFSEL14[3:0] AFSEL13[3:0]
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
GPIOC_AFRH
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0x1C24
GPIOH_AFRL
Res.
0x1C20
GPIOH_LCKR
Res.
0x1C1C
GPIOH_BSRR
Res.
0x1C18
GPIOH_ODR
Res.
0x1C14
GPIOH_IDR
Res.
0x1C10
GPIOH_PUPDR
Res.
0x1C0C
GPIOH_OSPEEDR
Res.
0x1C08
GPIOH_OTYPER
Res.
0x1C04
GPIOH_MODER
Res.
0x1C00
Res.
Offset Register name
Res.
8.4.36
Res.
0x0828
Res.
0x0824
Res.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Offset Register name
Res.
RM0461
General-purpose I/Os (GPIO)
Table 62. GPIOC register map and reset values (continued)
0
0
0
0
0
0
0
Refer to Section 2.4 for the register boundary addresses.
GPIOH register map
Table 63. GPIOH register map and reset values
0
x
0
0
0
0
Refer to Section 2.4 for the register boundary addresses.
333/1290
333
System configuration controller (SYSCFG)
RM0461
9
System configuration controller (SYSCFG)
9.1
SYSCFG main features
STM32WLEx devices feature a set of configuration registers. The main purposes of the
system configuration controller are the following:
•
Remapping memory areas
•
Managing the external interrupt line connection to the GPIOs
•
Managing robustness feature
•
Setting SRAM2 write protection and SRAM2 software erase
•
SRAM1, SRAM2 and PKA SRAM erase busy flags
•
Enabling /disabling I2C Fast-mode Plus driving capability on some I/Os and voltage
booster for I/Os analog switches.
9.2
SYSCFG registers
9.2.1
SYSCFG memory remap register (SYSCFG_MEMRMP)
This register is used for specific configurations on memory remap.
Address offset: 0x000
Reset value: 0x0000 000X
MEM_MODE[2:0] is the memory mode selected by the BOOT0 pin and BOOT1 option bit.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
2
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
MEM_MODE[2:0]
rw
rw
rw
Bits 31:3 Reserved, must be kept at reset value.
Bits 2:0 MEM_MODE[2:0]: memory mapping selection
These bits control the memory internal mapping at address 0x0000 0000. These bits are
used to select the physical remap by software and so, bypass the BOOT mode setting.
After reset, these bits take the value selected by BOOT0 (pin or option bit depending on
nSWBOOT0 option bit) and BOOT1 option bit.
000: Main flash memory mapped at CPU 0x00000000
001: System flash memory mapped at CPU 0x00000000
010: Reserved
011: SRAM1 mapped at CPU 0x00000000
100: Reserved
101: Reserved
110: Reserved
111: Reserved
334/1290
RM0461 Rev 10
RM0461
System configuration controller (SYSCFG)
9.2.2
SYSCFG configuration register 1 (SYSCFG_CFGR1)
Address offset: 0x004
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
I2C3_FMP
I2C2_FMP
I2C1_FMP
I2C_PB9_FMP
I2C_PB8_FMP
I2C_PB7_FMP
I2C_PB6_FMP
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
BOOSTEN
Reset value: 0x7C00 0001
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
rw
Bits 31:23 Reserved, must be kept at reset value.
Bit 22 I2C3_FMP: I2C3 Fast-mode Plus driving capability activation
This bit enables the Fm+ driving mode on I2C3 pins selected through AF selection bits.
0: Fm+ mode is not enabled on I2C3 pins selected through AF selection bits
1: Fm+ mode is enabled on I2C3 pins selected through AF selection bits.
Bit 21 I2C2_FMP: I2C2 Fast-mode Plus driving capability activation
This bit enables the Fm+ driving mode on I2C2 pins selected through AF selection bits.
0: Fm+ mode is not enabled on I2C2 pins selected through AF selection bits
1: Fm+ mode is enabled on I2C2 pins selected through AF selection bits.
Bit 20 I2C1_FMP: I2C1 Fast-mode Plus driving capability activation
This bit enables the Fm+ driving mode on I2C1 pins selected through AF selection bits.
0: Fm+ mode is not enabled on I2C1 pins selected through AF selection bits
1: Fm+ mode is enabled on I2C1 pins selected through AF selection bits.
Bit 19 I2C_PB9_FMP: Fast-mode Plus (Fm+) driving capability activation on PB9
This bit enables the Fm+ driving mode for PB9.
0: PB9 pin operates in standard mode.
1: Fm+ mode enabled on PB9 pin, and the speed control is bypassed.
Bit 18 I2C_PB8_FMP: Fast-mode Plus (Fm+) driving capability activation on PB8
This bit enables the Fm+ driving mode for PB8.
0: PB8 pin operates in standard mode.
1: Fm+ mode enabled on PB8 pin, and the speed control is bypassed.
Bit 17 I2C_PB7_FMP: Fast-mode Plus (Fm+) driving capability activation on PB7
This bit enables the Fm+ driving mode for PB7.
0: PB7 pin operates in standard mode.
1: Fm+ mode enabled on PB7 pin, and the speed control is bypassed.
Bit 16 I2C_PB6_FMP: Fast-mode Plus (Fm+) driving capability activation on PB6
This bit enables the Fm+ driving mode for PB6.
0: PB6 pin operates in standard mode.
1: Fm+ mode enabled on PB6 pin, and the Speed control is bypassed.
Bits 15:9 Reserved, must be kept at reset value.
RM0461 Rev 10
335/1290
343
System configuration controller (SYSCFG)
RM0461
Bit 8 BOOSTEN: I/O analog switch voltage booster enable
0: I/O analog switches are supplied by VDDA voltage. This is the recommended configuration
when using the ADC in high VDDA voltage operation.
1: I/O analog switches are supplied by a dedicated voltage booster (supplied by VDD). This is
the recommended configuration when using the ADC in low VDDA voltage operation.
Bits 7:0 Reserved, must be kept at reset value.
9.2.3
SYSCFG external interrupt configuration register 1
(SYSCFG_EXTICR1)
Address offset: 0x008
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
EXTI3[2:0]
rw
rw
Res.
rw
EXTI2[2:0]
rw
rw
Res.
rw
EXTI1[2:0]
rw
rw
Res.
rw
EXTI0[2:0]
rw
rw
rw
Bits 31:15 Reserved, must be kept at reset value.
Bits 14:12 EXTI3[2:0]: EXTI3 configuration bits
These bits are written by software to select the source input for the EXTI3 external interrupt.
000: PA3 pin
001: PB3 pin
010: PC3 pin
111: PH3 pin
Others: Reserved
Bit 11 Reserved, must be kept at reset value.
Bits 10:8 EXTI2[2:0]: EXTI2 configuration bits
These bits are written by software to select the source input for the EXTI2 external interrupt.
000: PA2 pin
001: PB2 pin
010: PC2 pin
Others: Reserved
Bit 7 Reserved, must be kept at reset value.
Bits 6:4 EXTI1[2:0]: EXTI1 configuration bits
These bits are written by software to select the source input for the EXTI1 external interrupt.
000: PA1 pin
001: PB1 pin
010: PC1 pin
Others: Reserved
Bit 3 Reserved, must be kept at reset value.
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RM0461 Rev 10
RM0461
System configuration controller (SYSCFG)
Bits 2:0 EXTI0[2:0]: EXTI0 configuration bits
These bits are written by software to select the source input for the EXTI0 external interrupt.
000: PA0 pin
001: PB0 pin
010: PC0 pin
Others: Reserved
Note:
Some of the I/O pins mentioned in this register may not be available on small packages.
9.2.4
SYSCFG external interrupt configuration register 2
(SYSCFG_EXTICR2)
Address offset: 0x00C
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
EXTI7[2:0]
rw
rw
Res.
rw
EXTI6[2:0]
rw
rw
Res.
rw
EXTI5[2:0]
rw
rw
Res.
rw
EXTI4[2:0]
rw
rw
rw
Bits 31:15 Reserved, must be kept at reset value.
Bits 14:12 EXTI7[2:0]: EXTI7 configuration bits
These bits are written by software to select the source input for the EXTI7 external interrupt.
000: PA7 pin
001: PB7 pin
Others: Reserved
Bit 11 Reserved, must be kept at reset value.
Bits 10:8 EXTI6[2:0]: EXTI6 configuration bits
These bits are written by software to select the source input for the EXTI6 external interrupt.
000: PA6 pin
001: PB6 pin
010: PC6 pin
0Others: Reserved
Bit 7 Reserved, must be kept at reset value.
Bits 6:4 EXTI5[2:0]: EXTI5 configuration bits
These bits are written by software to select the source input for the EXTI5 external interrupt.
000: PA5 pin
001: PB5 pin
010: PC5 pin
Others: Reserved
Bit 3 Reserved, must be kept at reset value.
RM0461 Rev 10
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System configuration controller (SYSCFG)
RM0461
Bits 2:0 EXTI4[2:0]: EXTI4 configuration bits
These bits are written by software to select the source input for the EXTI4 external interrupt.
000: PA4 pin
001: PB4 pin
010: PC4 pin
Others: Reserved
Note:
Some of the I/O pins mentioned in this register may not be available on small packages.
9.2.5
SYSCFG external interrupt configuration register 3
(SYSCFG_EXTICR3)
Address offset: 0x010
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
EXTI11[2:0]
rw
rw
Res.
rw
EXTI10[2:0]
rw
rw
Res.
rw
EXTI9[2:0]
rw
rw
Res.
rw
EXTI8[2:0]
rw
rw
rw
Bits 31:15 Reserved, must be kept at reset value.
Bits 14:12 EXTI11[2:0]: EXTI11 configuration bits
These bits are written by software to select the source input for the EXTI11 external interrupt.
000: PA11 pin
001: PB11 pin
Others: Reserved
Bit 11 Reserved, must be kept at reset value.
Bits 10:8 EXTI10[2:0]: EXTI10 configuration bits
These bits are written by software to select the source input for the EXTI10 external interrupt.
000: PA10 pin
001: PB10 pin
Others: Reserved
Bit 7 Reserved, must be kept at reset value.
Bits 6:4 EXTI9[2:0]: EXTI9 configuration bits
These bits are written by software to select the source input for the EXTI9 external interrupt.
000: PA9 pin
001: PB9 pin
Others: Reserved
Bit 3 Reserved, must be kept at reset value.
Bits 2:0 EXTI8[2:0]: EXTI8 configuration bits
These bits are written by software to select the source input for the EXTI8 external interrupt.
000: PA8 pin
001: PB8 pin
Others: Reserved
338/1290
RM0461 Rev 10
RM0461
System configuration controller (SYSCFG)
Note:
Some of the I/O pins mentioned in this register may not be available on small packages.
9.2.6
SYSCFG external interrupt configuration register 4
(SYSCFG_EXTICR4)
Address offset: 0x014
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
EXTI15[2:0]
rw
rw
Res.
rw
EXTI14[2:0]
rw
rw
Res.
rw
EXTI13[2:0]
rw
rw
Res.
rw
EXTI12[2:0]
rw
rw
rw
Bits 31:15 Reserved, must be kept at reset value.
Bits 14:12 EXTI15[2:0]: EXTI15 configuration bits
These bits are written by software to select the source input for the EXTI15 external interrupt.
000: PA15 pin
001: PB15 pin
010: PC15 pin
Others: Reserved
Bit 11 Reserved, must be kept at reset value.
Bits 10:8 EXTI14[2:0]: EXTI14 configuration bits
These bits are written by software to select the source input for the EXTI14 external interrupt.
000: PA14 pin
001: PB14 pin
010: PC14 pin
Others: Reserved
Bit 7 Reserved, must be kept at reset value.
Bits 6:4 EXTI13[2:0]: EXTI13 configuration bits
These bits are written by software to select the source input for the EXTI13 external interrupt.
000: PA13 pin
001: PB13 pin
010: PC13 pin
Others: Reserved
Bit 3 Reserved, must be kept at reset value.
Bits 2:0 EXTI12[2:0]: EXTI12 configuration bits
These bits are written by software to select the source input for the EXTI12 external interrupt.
000: PA12 pin
001: PB12 pin
Others: Reserved
Note:
Some of the I/O pins mentioned in this register may not be available on small packages.
RM0461 Rev 10
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System configuration controller (SYSCFG)
9.2.7
RM0461
SYSCFG SRAM control and status register (SYSCFG_SCSR)
Address offset: 0x18
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PKASR
AMBSY
Res.
Res.
Res.
Res.
Res.
Res.
r
SRAM SRAM2
BSY
ER
r
rw
Bits 31:9 Reserved, must be kept at reset value.
Bit 8 PKASRAMBSY: PKA SRAM busy by erase operation
0: No PKA SRAM erase operation is ongoing.
1: PKA SRAM erase operation is ongoing.
See Section 2.3: SRAM erase for more information on SRAM erase conditions
Bits 7:2 Reserved, must be kept at reset value.
Bit 1 SRAMBSY: SRAM1 or SRAM2 busy by erase operation
0: No SRAM1 or SRAM2 erase operation is ongoing.
1: SRAM1 or SRAM2 erase operation is ongoing.
See Section 2.3: SRAM erase for more information on SRAM erase conditions
Bit 0 SRAM2ER: SRAM2 erase
Setting this bit starts a hardware SRAM2 erase operation. This bit is automatically cleared at
the end of the SRAM2 erase operation.
Note: This bit is write-protected: setting this bit is possible only after the correct key sequence
is written in the SYSCFG_SKR register.
9.2.8
SYSCFG configuration register 2 (SYSCFG_CFGR2)
Address offset: 0x01C
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
SPF
Res.
Res.
Res.
Res.
ECCL
PVDL
SPL
CLL
rs
rs
rs
rs
rc_w1
Bits 31:9 Reserved, must be kept at reset value.
Bit 8 SPF: SRAM2 parity error flag
This bit is set by hardware when an SRAM2 parity error is detected. It is cleared by software
by writing ‘1’.
0: No SRAM2 parity error detected
1: SRAM2 parity error detected
340/1290
RM0461 Rev 10
RM0461
System configuration controller (SYSCFG)
Bits 7:4 Reserved, must be kept at reset value.
Bit 3 ECCL: ECC lock
This bit is set by software and cleared only by a system reset. It can be used to enable and
lock the flash ECC error connection to TIM1/16/17 break input.
0: ECC error disconnected from TIM1/16/17 break input.
1: ECC error connected to TIM1/16/17 break input.
Bit 2 PVDL: PVD lock enable bit
This bit is set by software and cleared only by a system reset. It can be used to enable and
lock the PVD connection to TIM1/16/17 break input, as well as the PVDE and PLS[2:0] in the
PWR_CR2R register.
0: PVD interrupt disconnected from TIM1/16/17 break input. PVDE and PLS[2:0] bits can be
programmed by the application.
1: PVD interrupt connected to TIM1/16/17 break input. PVDE and PLS[2:0] bits are read only.
Bit 1 SPL: SRAM2 parity lock bit
This bit is set by software and cleared only by a system reset. It can be used to enable and
lock the SRAM2 parity error signal connection to TIM1/16/17 break inputs.
0: SRAM2 parity error signal disconnected from TIM1/16/17 break inputs
1: SRAM2 parity error signal connected to TIM1/16/17 break inputs
Bit 0 CLL: CPU LOCKUP (Hardfault) output enable bit
This bit is set by software and cleared only by a system reset. It can be used to enable and
lock the connection of CPU LOCKUP (Hardfault) output to TIM1/16/17 break inputs.
0: CPU LOCKUP output disconnected from TIM1/16/17 break inputs
1: CPU LOCKUP output connected to TIM1/16/17 break inputs
9.2.9
SYSCFG SRAM2 write protection register (SYSCFG_SWPR)
Address offset: 0x020
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
P31WP P30WP P29WP P28WP P27WP P26WP P25WP P24WP P23WP P22WP P21WP P20WP P19WP P18WP P17WP P16WP
rs
rs
rs
rs
rs
rs
15
14
13
12
11
10
P15WP P14WP P13WP P12WP P11WP P10WP
rs
rs
rs
rs
rs
rs
rs
rs
rs
rs
rs
rs
rs
rs
rs
rs
9
8
7
6
5
4
3
2
1
0
P9WP
P8WP
P7WP
P6WP
P5WP
P4WP
P3WP
P2WP
P1WP
P0WP
rs
rs
rs
rs
rs
rs
rs
rs
rs
rs
Bits 31:0 PxWP: SRAM2 1 Kbyte page x write protection (x = 31 to 0)
These bits are set by software and cleared only by a system reset. Number of pages depend
on SRAM2 size available from the device type, see data sheet.
0: Write protection of SRAM2 1 Kbyte page x is disabled.
1: Write protection of SRAM2 1 Kbyte page x is enabled.
RM0461 Rev 10
341/1290
343
System configuration controller (SYSCFG)
9.2.10
RM0461
SYSCFG SRAM2 key register (SYSCFG_SKR)
Address offset: 0x024
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
w
w
w
w
w
w
w
KEY[7:0]
w
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 KEY[7:0]: SRAM2 write protection key for software erase
The following steps are required to unlock the write protection of the SRAM2ER bit in the
SYSCFG_SCSR register.
1. Write 0xCA into Key[7:0].
2. Write 0x53 into Key[7:0].
Writing a wrong key reactivates the write protection.
9.2.11
SYSCFG radio debug control register (SYSCFG_RFDCR)
Address offset: 0x208
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
RFTBS
EL
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
rw
Bits 31:1 Reserved, must be kept at reset value.
Bit 0 RFTBSEL: radio debug test bus selection
0 Digital test bus selected on RF_ADTB[3:0]
1: Analog test bus selected on RF_ADTB[3:0]
9.2.12
SYSCFG register map
Reset value
342/1290
MEM_MODE
[2:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
SYSCFG_
MEMRMP
Res.
0x000
Res.
Offset Register name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 64. SYSCFG register map and reset values
x
RM0461 Rev 10
x
x
0x208
SYSCFG_RFDCR
RM0461 Rev 10
Reset value
Reset value
P5WP
P4WP
0
0
0
0
0
0
0
0
SYSCFG_SKR
SPL
CLL
0
PVDL
Res.
Res.
Res.
Res.
0
0
0
0
0
0
0
0
SRAM2ER
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
SRAMBSY
0
Res.
EXTI13
[2:0]
Res.
0
Res.
0
Res.
Res.
EXTI9
[2:0]
ECCL
0
Res.
Res.
0
0
Res.
0
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
0
PKASRAMBSY
0
EXTI5
[2:0]
P0WP
P6WP
0
Res.
EXTI14
[2:0]
Reserved
0
0
0
0
0
0
0
0
RFTBSEL
P7WP
Reset value
SPF
Reset value
0
0
P1WP
P8WP
0
Res.
Res.
0
Res.
Res.
0
Res.
P9WP
0
Res.
Res.
Res.
0
0
P2WP
P10WP
0
Res.
Res.
0
Res.
EXTI15
[2:0]
EXTI10
[2:0]
Res.
P11WP
0
Res.
Res.
0
Res.
0
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
EXTI1
[2:0]
P3WP
P12WP
0
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
EXTI11
[2:0]
0
Res.
P13WP
0
Res.
Res.
Res.
Reset value
0
0
EXTI6
[2:0]
Res.
P14WP
0
Res.
Res.
Res.
Res.
Res.
0
0
0
Res.
P15WP
0
Res.
Res.
Res.
Res.
Reset value
EXTI7
[2:0]
0
Res.
P16WP
0
Res.
Res.
Res.
Res.
Res.
Res.
0
0
EXTI2
[2:0]
Res.
P17WP
0
Res.
Res.
Res.
Res.
Reset value
0
Res.
P18WP
0
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
P19WP
0
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
EXTI3
[2:0]
Res.
P20WP
0
Res.
Res.
Res.
Res.
Res.
Res.
I2C_PB8_FMP
I2C_PB7_FMP
I2C_PB6_FMP
0
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
BOOSTEN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
I2C1_FMP
I2C2_FMP
I2C_PB9_FMP
I2C3_FMP
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
P21WP
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
P22WP
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
P23WP
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
P24WP
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Reserved
Res.
Res.
Res.
P25WP
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
P26WP
0
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
P27WP
0
Res.
Res.
Res.
Res.
Reset value
Res.
Res.
Res.
Res.
P28WP
SYSCFG_CFGR2
Res.
P29WP
Reset value
Res.
SYSCFG_SCSR
Res.
SYSCFG_EXTICR4
Res.
0x028 to
0x204
SYSCFG_SWPR
Res.
0x024
SYSCFG_EXTICR3
Res.
0x020
SYSCFG_EXTICR2
Res.
0x01C
SYSCFG_EXTICR1
Res.
0x018
SYSCFG_CFGR1
Res.
0x014
P30WP
0x010
P31WP
0x00C
Res.
0x008
Res.
0x004
Res.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Offset Register name
Res.
RM0461
System configuration controller (SYSCFG)
Table 64. SYSCFG register map and reset values (continued)
0
EXTI0
[2:0]
0
EXTI4
[2:0]
0
EXTI8
[2:0]
0
EXTI12
[2:0]
0
0
0
0
0
0
0
0
0
0
KEY[7:0]
0
Refer to Section 2.4 for the register boundary addresses.
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Peripherals interconnect matrix
RM0461
10
Peripherals interconnect matrix
10.1
Introduction
Several peripherals have direct connections between them, enabling autonomous
communication and/or synchronization between them. This saves CPU resources and,
consequently power consumption. In addition, these hardware connections remove
software latency and result in more predictable system design.
Depending on peripherals, these interconnections can operate in Run, Sleep, LPRun,
LPSleep, Stop 0, Stop 1 and Stop 2 modes.
10.2
Connection summary
Table 65. STM32WLEx peripherals interconnect matrix(1) (2)
TIM1
TIM2
TIM16
TIM17
LPTIM1
LPTIM2
LPTIM3
ADC
DAC
COMP1
COMP2
DMAMUX1
IRTIM
SUBGHZSPI
Destination
TIM1
-
1
-
-
-
-
-
3
3
8
8
-
-
-
TIM2
1
-
-
-
-
-
-
3
3
8
8
-
-
-
TIM16
-
-
-
-
-
-
-
-
-
-
-
-
12
-
TIM17
1
-
-
-
-
-
-
-
-
-
-
-
12
-
LPTIM1
-
-
-
-
-
-
2
-
4
-
-
13
-
-
LPTIM2
-
-
-
-
-
-
2
-
4
-
-
13
-
-
LPTIM3
-
-
-
-
-
-
-
-
-
-
-
13
-
14
ADC
5
-
-
-
-
-
-
-
-
-
-
-
-
Temperature
sensor
-
-
-
-
-
-
-
9
-
-
-
-
-
-
VBAT
-
-
-
-
-
-
-
9
-
-
-
-
-
-
VREFINT
-
-
-
-
-
-
-
9
-
-
-
-
-
-
HSE32
-
-
-
6
-
-
-
-
-
-
-
-
-
-
LSE
-
6
6
-
-
-
-
-
-
-
-
-
-
-
MSI
-
-
-
6
-
-
-
-
-
-
-
-
-
-
LSI
-
-
6
-
-
-
-
-
-
-
-
-
-
-
MCO
-
-
-
6
-
-
-
-
-
-
-
-
-
-
GPIO EXTI
-
-
-
-
-
-
-
3
3
-
-
13
-
-
RTC
-
-
6
-
7
7
-
-
-
-
-
-
-
-
TAMP
-
-
-
-
7
7
-
-
-
-
-
-
-
-
Source
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Table 65. STM32WLEx peripherals interconnect matrix(1) (2) (continued)
TIM1
TIM2
TIM16
TIM17
LPTIM1
LPTIM2
LPTIM3
ADC
DAC
COMP1
COMP2
DMAMUX1
IRTIM
SUBGHZSPI
Destination
COMP1
10
10
10
10
7
7
-
-
-
-
-
-
-
-
COMP2
10
10
10
10
7
7
-
-
-
-
-
-
-
-
SYST ERR
11
-
11
11
-
-
-
-
-
-
-
-
-
-
Source
1. Numbers in this table are links to corresponding subsections of Section 10.3: Interconnection details.
2.
The “-” symbol in grayed cells means no interconnect.
10.3
Interconnection details
10.3.1
From timer (TIM1/TIM2/TIM17) to timer (TIM1/TIM2)
Purpose
Some timers are linked together internally for synchronization or chaining.
When one timer is configured in Master mode, it can reset, start, stop or clock the counter of
another timer configured in Slave mode. A description of the feature is provided in
Section 23.3.26: Timer synchronization.
The synchronization modes are detailed in the following sections:
•
Section 23.3.26: Timer synchronization for advanced-control timers (TIM1)
•
Section 24.3.18: Timers and external trigger synchronization for general-purpose
timers (TIM2)
Triggering signals
The output (from master) is on signal TIMx_TRGO (and TIMx_TRGO2 for TIM1) following a
configurable timer event. The input (to slave) is on signals TIMx_ITR0/ITR1/ITR2/ITR3.
The input and output signals for TIM1 are shown in Figure 114: Advanced-control timer
block diagram.
The possible master/slave connections are given in tables below:
•
Table 168: TIM1 internal trigger connection for TIM1
•
Table 172: TIM2 internal trigger connection for TIM2
Active power modes
Run, Sleep, LPRun, LPSleep
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10.3.2
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From timer (LPTIM1/LPTIM2) to timer (LPTIM3)
Purpose
Some timers are linked together internally for synchronization or chaining.
When one timer is configured in Master mode, it can reset, start, stop or clock the counter of
another timer configured in Slave mode. A description of the feature is provided in
Section 23.3.26: Timer synchronization.
Triggering signals
The output is on signals LPTIMx_OUT following a configurable timer event. The input (to
slave) is on signals LPTIM3_ETR.
The input and output signals for LPTIM are shown in Figure 248: Low-power timer block
diagram.
The possible connections are given inTable 183: LPTIM3 external trigger connections.
Active power modes
Run, Sleep, LPRun, LPSleep, Stop 0, Stop 1
10.3.3
From timer (TIM1/TIM2) and GPIO pin EXTI to ADC/DAC
Purpose
Advanced-control timer TIM1, general-purpose timer TIM2 and GPIO pin EXTI can be used
to generate an ADC/DAC trigger event.
TIMx synchronization is described in Section 23.3.27: ADC synchronization.
GPIO pin EXTI mux is described in Section 9: System configuration controller (SYSCFG).
ADC synchronization is described in Section 16.4: Conversion on external trigger and
trigger polarity (EXTSEL, EXTEN).
DAC synchronization is described in Section 17.4.7: DAC trigger selection.
Triggering signals
The output from timer is on signals TIMx_TRGO, TIMx_TRGO2, TIMx_CCx, TIMx_CHn
event. The output from GPIO pin is on EXTI mux signal from SYSCFG.
The input to ADC is on signals TRG[7:0].
The connection between timers, GPIO pin EXTI mux and ADC, is provided inTable 90:
External triggers.
The input to DAC is on signals dac_ch1_trg[15:0].
The connection between timers, GPIO pin EXTI mux and DAC, is provided inTable 102:
DAC interconnection.
Active power modes
Run, Sleep, LPRun, LPSleep
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10.3.4
Peripherals interconnect matrix
From timer (LPTIM1/LPTIM2) to DAC
Purpose
Low-power timer LPTIM1/LPTIM2 can be used to generate an DAC trigger event.
DAC triggering is described in Section 17.4.7: DAC trigger selection.
Triggering signals
The output from low-power timer is on signals LPTIMx_OUT event.
The input to DAC is on signals dac_ch1_trg[15:0].
The connection between timers and DAC is provided in Table 102: DAC interconnection.
Active power modes
Run, Sleep, LPRun, LPSleep
10.3.5
From ADC to timer (TIM1)
Purpose
ADC can provide trigger event through watchdog signals to advanced-control timers (TIM1).
A description of the ADC analog watchdog setting is provided in Section 16.8.2: Analog
watchdog.
Trigger settings on the timer are provided in Section 23.3.4: External trigger input.
Triggering signals
The output (from ADC) is on signals ADC_AWDx_OUT, x = 1, 2, 3 (3 watchdogs on ADC)
and the input (to timer) on signal TIMx_ETR (external trigger).
Active power modes
Run, Sleep, LPRun, LPSleep
10.3.6
From HSE32, LSE, LSI, MSI, MCO, RTC to timers
(TIM2/TIM16/TIM17)
Purpose
External clocks (HSE32, LSE), internal clocks (LSI, MSI), microcontroller output clock
(MCO), GPIO and RTC wake-up interrupt can be used as input to general-purpose timers
(TIM16/17) channel 1.
This makes possible calibration of the HSI16/MSI system clocks (with TIM16 and LSE) or of
the LSI (with TIM16 and HSE32). This is also used to precisely measure LSI (with TIM16
and HSI16) or MSI (with TIM17 and HSI16) oscillator frequency.
When the low-speed external (LSE) oscillator is used, no additional hardware connections
are required.
This feature is described in Section 6.2.20: Internal/external clock measurement with
TIM16/TIM17.
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External clock LSE can be used as input to general-purpose timers (TIM2) on TIM2_ETR
pin (see TIM2 option register 1 (TIM2_OR1)).
Active power modes
Run, Sleep, LPRun, LPSleep
10.3.7
From RTC, TAMP, COMP1, COMP2 to low-power timers
(LPTIM1/LPTIM2)
Purpose
RTC alarm A/B, TAMP_IN1/2/3 input detection and COMP1/2_OUT can be used as trigger
to start LPTIM1/LPTIM2 counters.
Triggering signals
This trigger feature is described in Section 26.4.7: Trigger multiplexer (and following
sections).
The input selection is described in Table 181: LPTIM1 external trigger connections and
Table 182: LPTIM2 external trigger connections.
Active power modes
Run, Sleep, LPRun, LPSleep, Stop 0, Stop 1, Stop 2 (LPTIM1 only)
10.3.8
From timer (TIM1/TIM2) to comparators (COMP1/COMP2)
Purpose
Advanced-control timer (TIM1) and general-purpose timer (TIM2) can be used as blanking
window input to COMP1/COMP2.
The blanking function is described in Section 19.3.7: Comparator output blanking function.
The blanking sources are given in the following registers:
•
COMP1 control and status register (COMP1_CSR) bits 20:18 BLANKING[2:0]
•
COMP2 control and status register (COMP2_CSR) bits 20:18 BLANKING[2:0]
Triggering signals
Timer output signals TIMx_OCx are the inputs to blanking source of COMP1/COMP2.
Active power modes
Run, Sleep, LPRun, LPSleep
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10.3.9
Peripherals interconnect matrix
From internal analog to ADC
Purpose
Internal temperature sensor (VTS), Internal reference voltage (VREFINT) and VBAT monitoring
channel are connected to ADC input channel.
This is according to the following sections:
•
Section 16.2: ADC main features
•
Section 16.3.8: Channel selection (CHSEL, SCANDIR, CHSELRMOD)
•
Section 16.9: Temperature sensor and internal reference voltage
•
Section 16.10: Battery voltage monitoring
Active power modes
Run, Sleep, LPRun, LPSleep
10.3.10
From comparators (COMP1/COMP2) to timers
(TIM1/TIM2/TIM16/TIM17)
Purpose
Comparators (COMP1/COMP2) output values can be connected to timers
TIM1/TIM2/TIM16/TIM17 input captures or TIMx_ETR signals.
Comparators (COMP1/COMP2) output values can also generate break input signals for
timer TIM1 on input pins TIMx_BKIN or TIMx_BKIN2 through GPIO alternate function
selection using open drain connection of I/Os.
The possible connections are given in the following sections:
•
Section 23.4.23: TIM1 option register 1 (TIM1_OR1)
•
Section 23.4.28: TIM1 Alternate function register 2 (TIM1_AF2)
•
Section 24.4.22: TIM2 option register 1 (TIM2_OR1)
•
Section 24.4.23: TIM2 alternate function option register 1 (TIM2_AF1)
•
Section 25.4.21: TIM17 alternate function register 1 (TIM17_AF1)
Active power modes
Run, Sleep, LPRun, LPSleep
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10.3.11
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From system errors to timers (TIM1/TIM16/TIM17)
Purpose
CSS, CPU hard fault, RAM parity error, FLASH ECC double error detection and PVD can
generate system errors in the form of timer break toward timers (TIM1/TIM16/TIM17).
The purpose of the break function is to protect power switches driven by PWM signals
generated by the timers.
List of possible source of break are described in the following sections:
•
Section 23.3.16: Using the break function (TIM1)
•
Section 25.3.11: Using the break function (TIM16/TIM17)
Active power modes
Run, Sleep, LPRun, LPSleep
10.3.12
From timers (TIM16/TIM17) to IRTIM
Purpose
General-purpose timer (TIM16/TIM17) output channels TIMx_OC1 are used to generate the
waveform of infrared signal output.
The functionality is described in Section 27: Infrared interface (IRTIM).
Active power modes
Run, Sleep, LPRun, LPSleep
10.3.13
From timer (LPTIM1/LPTIM2/LPTIM3/GPIO pin EXTI)
to DMAMUX1 trigger
Purpose
Low-power timers LPTIM1/LPTIM2/LPTIM3 and GPIO pin EXTI mux in SYSCFG, can be
used to generate a DMAMUX1 trigger event.
GPIO pin EXTI mux is described in Section 9: System configuration controller (SYSCFG).
DMAMUX1 triggering is described in Section 12.3.2: DMAMUX1 mapping.
Triggering signals
The output from low-power timer is on signals LPTIMx_OUT event. The output from GPIO
pin is on EXTI mux signal from SYSCFG.
The input to DMAMUX1 is on signals trigger input [20:0].
The connection between timers, GPIO pin EXTI mux and DMAMUX1, is provided in
Table 72: DMAMUX1: assignment of multiplexer inputs to resources.
Active power modes
Run, Sleep, LPRun, LPSleep
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10.3.14
Peripherals interconnect matrix
From timer (LPTIM3) to sub-GHz radio SPI NSS
Purpose
Low-power timer LPTIM3 can be used to generate a sub-GHz radio SPI NSS event.
Triggering signals
The output from low-power timer is on signal LPTIM3_OUT event.
The connection between timers and sub-GHz radio SPI NSS is provided in PWR sub-GHz
SPI control register (PWR_SUBGHZSPICR).
Active power modes
Run, Sleep, LPRun, LPSleep
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11
Direct memory access controller (DMA)
11.1
Introduction
The direct memory access (DMA) controller is a bus master and system peripheral.
The DMA is used to perform programmable data transfers between memory-mapped
peripherals and/or memories, upon the control of an off-loaded CPU.
The DMA controller features a single AHB master architecture.
There are two instances of DMA, DMA1 and DMA2.
Each channel is dedicated to managing memory access requests from one or more
peripherals. Each DMA includes an arbiter for handling the priority between DMA requests.
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•
Single AHB master
•
Peripheral-to-memory, memory-to-peripheral, memory-to-memory and peripheral-toperipheral data transfers
•
Access, as source and destination, to on-chip memory-mapped devices such as flash
memory, SRAM, and AHB and APB peripherals
•
All DMA channels independently configurable:
–
Each channel is associated either with a DMA request signal coming from a
peripheral, or with a software trigger in memory-to-memory transfers. This
configuration is done by software.
–
Priority between the requests is programmable by software (4 levels per channel:
very high, high, medium, low) and by hardware in case of equality (such as
request to channel 1 has priority over request to channel 2).
–
Transfer size of source and destination are independent (byte, half-word, word),
emulating packing and unpacking. Source and destination addresses must be
aligned on the data size.
–
Support of transfers from/to peripherals to/from memory with circular buffer
management
–
Programmable number of data to be transferred: 0 to 218 - 1
•
Generation of an interrupt request per channel. Each interrupt request is caused from
any of the three DMA events: transfer complete, half transfer, or transfer error.
•
Privileged/unprivileged support:
–
Support for AHB privileged and unprivileged DMA transfers, independently of a
channel level
–
Privileged-aware AHB slave port
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11.3
DMA implementation
11.3.1
DMA1 and DMA2
DMA1 and DMA2 are implemented with the hardware configuration parameters shown
in Table 66.
Table 66. DMA1 and DMA2 implementation
Feature
DMA1
DMA2
7
7
Number of channels
11.3.2
DMA request mapping
The DMA controller is connected to DMA requests from the AHB/APB peripherals through
the DMAMUX peripheral.
For the mapping of the different requests, refer to the Section 12.3: DMAMUX
implementation.
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11.4
DMA functional description
11.4.1
DMA block diagram
The DMA block diagram is shown in Figure 36.
Figure 36. DMA block diagram
DMA1
AHB master interface
32-bit AHB bus
AHB slave interface
32-bit AHB bus
AHB master interface
32-bit AHB bus
AHB slave interface
32-bit AHB bus
Ch 1
Ch 2
...
Ch 7
dma1_req [1..7]
dma1_ack [1..7]
Arbiter
dma1_priv[1..7]
Interrupt
interface
DMAMUX1
dma1_it[1..7]
DMA2
Ch 1
Ch 2
...
Ch 7
dma2_req [1..7]
dma2_ack [1..7]
dma2_priv[1..7]
Arbiter
Interrupt
interface
dma2_it[1..7]
MSv61545V1
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The DMA controller performs direct memory transfer by sharing the AHB system bus with
other system masters. The bus matrix implements round-robin scheduling. DMA requests
may stop the CPU access to the system bus for a number of bus cycles, when CPU and
DMA target the same destination (memory or peripheral).
According to its configuration through the AHB slave interface, the DMA controller arbitrates
between the DMA channels and their associated received requests. The DMA controller
also schedules the DMA data transfers over the single AHB port master.
The DMA controller generates a privileged bus, to keep the DMAMUX peripheral informed
of the privileged or unprivileged state of each channel x.
The DMA controller generates an interrupt per channel to the interrupt controller.
11.4.2
DMA pins and internal signals
Table 67. DMA internal input/output signals
11.4.3
Signal name
Signal type
Description
dma_req[x]
Input
DMA channel x request
dma_ack[x]
Output
DMA channel x acknowledge
dma_it[x]
Output
DMA channel x interrupt
dma_priv[x]
Output
DMA channel x privileged state
DMA transfers
The software configures the DMA controller at channel level, in order to perform a block
transfer, composed of a sequence of AHB privileged or unprivileged bus transfers.
A DMA block transfer may be requested from a peripheral, or triggered by the software in
case of memory-to-memory transfer.
After an event, the following steps of a single DMA transfer occur:
1.
The peripheral sends a single DMA request signal to the DMA controller.
2.
The DMA controller serves the request, depending on the priority of the channel
associated to this peripheral request.
3.
As soon as the DMA controller grants the peripheral, an acknowledge is sent to the
peripheral by the DMA controller.
4.
The peripheral releases its request as soon as it gets the acknowledge from the DMA
controller.
5.
Once the request is de-asserted by the peripheral, the DMA controller releases the
acknowledge.
The peripheral may order a further single request and initiate another single DMA transfer.
The request/acknowledge protocol is used when a peripheral is either the source or the
destination of the transfer. For example, in case of memory-to-peripheral transfer, the
peripheral initiates the transfer by driving its single request signal to the DMA controller. The
DMA controller reads then a single data in the memory and writes this data to the peripheral.
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For a given channel x, a DMA block transfer consists of a repeated sequence of:
•
•
a single DMA transfer, encapsulating two AHB transfers of a single data, over the DMA
AHB bus master:
–
a single data read (byte, half-word or word) from the peripheral data register or a
location in the memory, addressed through an internal current peripheral/memory
address register.
The start address used for the first single transfer is the base address of the
peripheral or memory, and is programmed in the DMA_CPARx or DMA_CMARx
register.
–
a single data write (byte, half-word or word) to the peripheral data register or a
location in the memory, addressed through an internal current peripheral/memory
address register.
The start address used for the first transfer is the base address of the peripheral or
memory, and is programmed in the DMA_CPARx or DMA_CMARx register.
post-decrementing of the programmed DMA_CNDTRx register
This register contains the remaining number of data items to transfer (number of AHB
‘read followed by write’ transfers).
This sequence is repeated until DMA_CNDTRx is null.
Note:
The AHB master bus source/destination address must be aligned with the programmed size
of the transferred single data to the source/destination.
11.4.4
DMA arbitration
The DMA arbiter manages the priority between the different channels.
When an active channel x is granted by the arbiter (hardware requested or software
triggered), a single DMA transfer is issued (such as a AHB ‘read followed by write’ transfer
of a single data). Then, the arbiter considers again the set of active channels and selects the
one with the highest priority.
The priorities are managed in two stages:
•
•
software: priority of each channel is configured in the DMA_CCRx register, to one of
the four different levels:
–
very high
–
high
–
medium
–
low
hardware: if two requests have the same software priority level, the channel with the
lowest index gets priority. For example, channel 2 gets priority over channel 4.
When a channel x is programmed for a block transfer in memory-to-memory mode,
re arbitration is considered between each single DMA transfer of this channel x. Whenever
there is another concurrent active requested channel, the DMA arbiter automatically
alternates and grants the other highest-priority requested channel, which may be of lower
priority than the memory-to-memory channel.
11.4.5
DMA channels
Each channel may handle a DMA transfer between a peripheral register located at a fixed
address, and a memory address. The amount of data items to transfer is programmable.
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The register that contains the amount of data items to transfer is decremented after each
transfer.
A DMA channel is programmed at block transfer level.
Programmable data sizes
The transfer sizes of a single data (byte, half-word, or word) to the peripheral and memory
are programmable through, respectively, the PSIZE[1:0] and MSIZE[1:0] fields of the
DMA_CCRx register.
Pointer incrementation
The peripheral and memory pointers may be automatically incremented after each transfer,
depending on the PINC and MINC bits of the DMA_CCRx register.
If the incremented mode is enabled (PINC or MINC set to 1), the address of the next
transfer is the address of the previous one incremented by 1, 2 or 4, depending on the data
size defined in PSIZE[1:0] or MSIZE[1:0]. The first transfer address is the one programmed
in the DMA_CPARx or DMA_CMARx register. During transfers, these registers keep the
initially programmed value. The current transfer addresses (in the current internal
peripheral/memory address register) are not accessible by software.
If the channel x is configured in non-circular mode, no DMA request is served after the last
data transfer (once the number of single data to transfer reaches zero). The DMA channel
must be disabled in order to reload a new number of data items into the DMA_CNDTRx
register.
Note:
If the channel x is disabled, the DMA registers are not reset. The DMA channel registers
(DMA_CCRx, DMA_CPARx and DMA_CMARx) retain the initial values programmed during
the channel configuration phase.
In circular mode, after the last data transfer, the DMA_CNDTRx register is automatically
reloaded with the initially programmed value. The current internal address registers are
reloaded with the base address values from the DMA_CPARx and DMA_CMARx registers.
Privileged / unprivileged mode
Any channel x is a privileged or unprivileged hardware resource, as configured by a
privileged software via the PRIV bit of the DMA_CCRx register.
When a channel x is configured in privileged mode, the following access controls rules are
applied:
•
An unprivileged read access to a register field of this channel is forced to return 0,
except for the privileged state of this channel x (PRIV bit of the DMA_CCRx register)
which is readable by an unprivileged software.
•
An unprivileged write access to a register field of this channel has no impact.
When a channel is configured in a privileged (or unprivileged) mode, the AHB master
transfers from the source and to the destination, are privileged (respectively unprivileged).
DMA generates a privileged bus, dma_priv[7:0], reflecting the PRIV bit of the DMA_CCRx
register, in order to keep the other hardware peripherals, like DMAMUX, informed of the
privileged / unprivileged state of each DMA channel x.
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Channel configuration procedure
The following sequence is needed to configure a DMA channel x:
1.
Set a channel x to privileged or unprivileged, by a privileged write access to the
privileged PRIV bit of the DMA_CCRx register.
2.
Set the memory address in the DMA_CMARx register.
The data is written to/read from the memory after the peripheral event or after the
channel is enabled in memory-to-memory mode.
3.
Configure the total number of data to transfer in the DMA_CNDTRx register.
After each data transfer, this value is decremented.
4.
Configure the parameters listed below in the DMA_CCRx register:
5.
–
the channel priority
–
the data transfer direction
–
the circular mode
–
the peripheral and memory incremented mode
–
the peripheral and memory data size
–
the interrupt enable at half and/or full transfer and/or transfer error
Activate the channel by setting the EN bit in the DMA_CCRx register.
A channel, as soon as enabled, may serve any DMA request from the peripheral connected
to this channel, or may start a memory-to-memory block transfer.
Note:
The two last steps of the channel configuration procedure may be merged into a single
access to the DMA_CCRx register, to configure and enable the channel.
Channel state and disabling a channel
A channel x in active state is an enabled channel (read DMA_CCRx.EN = 1). An active
channel x is a channel that must have been enabled by the software (DMA_CCRx.EN set
to 1) and afterwards with no occurred transfer error (DMA_ISR.TEIFx = 0). In case there is a
transfer error, the channel is automatically disabled by hardware (DMA_CCRx.EN = 0).
The three following use cases may happen:
•
Suspend and resume a channel
This corresponds to the two following actions:
–
An active channel is disabled by software (writing DMA_CCRx.EN = 0 whereas
DMA_CCRx.EN = 1).
–
The software enables the channel again (DMA_CCRx.EN set to 1) without
reconfiguring the other channel registers (such as DMA_CNDTRx, DMA_CPARx
and DMA_CMARx).
This case is not supported by the DMA hardware, that does not guarantee that the
remaining data transfers are performed correctly.
•
Stop and abort a channel
If the application does not need any more the channel, this active channel can be
disabled by software. The channel is stopped and aborted but the DMA_CNDTRx
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register content may not correctly reflect the remaining data transfers versus the
aborted source and destination buffer/register.
•
Abort and restart a channel
This corresponds to the software sequence: disable an active channel, then
reconfigure the channel and enable it again.
This is supported by the hardware if the following conditions are met:
–
The application guarantees that, when the software is disabling the channel, a
DMA data transfer is not occurring at the same time over its master port. For
example, the application can first disable the peripheral in DMA mode, in order to
ensure that there is no pending hardware DMA request from this peripheral.
–
The software must operate separated write accesses to the same DMA_CCRx
register: First disable the channel. Second reconfigure the channel for a next block
transfer including the DMA_CCRx if a configuration change is needed. There are
read-only DMA_CCRx register fields when DMA_CCRx.EN=1. Finally enable
again the channel.
When a channel transfer error occurs, the EN bit of the DMA_CCRx register is cleared by
hardware. This EN bit can not be set again by software to re-activate the channel x, until the
TEIFx bit of the DMA_ISR register is set.
Circular mode (in memory-to-peripheral/peripheral-to-memory transfers)
The circular mode is available to handle circular buffers and continuous data flows (such as
ADC scan mode). This feature is enabled using the CIRC bit in the DMA_CCRx register.
Note:
The circular mode must not be used in memory-to-memory mode. Before enabling a
channel in circular mode (CIRC = 1), the software must clear the MEM2MEM bit of the
DMA_CCRx register. When the circular mode is activated, the amount of data to transfer is
automatically reloaded with the initial value programmed during the channel configuration
phase, and the DMA requests continue to be served.
In order to stop a circular transfer, the software needs to stop the peripheral from generating
DMA requests (such as quit the ADC scan mode), before disabling the DMA channel.
The software must explicitly program the DMA_CNDTRx value before starting/enabling a
transfer, and after having stopped a circular transfer.
Memory-to-memory mode
The DMA channels may operate without being triggered by a request from a peripheral. This
mode is called memory-to-memory mode, and is initiated by software.
If the MEM2MEM bit in the DMA_CCRx register is set, the channel, if enabled, initiates
transfers. The transfer stops once the DMA_CNDTRx register reaches zero.
Note:
The memory-to-memory mode must not be used in circular mode. Before enabling a
channel in memory-to-memory mode (MEM2MEM = 1), the software must clear the CIRC
bit of the DMA_CCRx register.
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Peripheral-to-peripheral mode
Any DMA channel can operate in peripheral-to-peripheral mode:
•
when the hardware request from a peripheral is selected to trigger the DMA channel
This peripheral is the DMA initiator and paces the data transfer from/to this peripheral
to/from a register belonging to another memory-mapped peripheral (this one being not
configured in DMA mode).
•
when no peripheral request is selected and connected to the DMA channel
The software configures a register-to-register transfer by setting the MEM2MEM bit of
the DMA_CCRx register.
Programming transfer direction, assigning source/destination
The value of the DIR bit of the DMA_CCRx register sets the direction of the transfer, and
consequently, it identifies the source and the destination, regardless the source/destination
type (peripheral or memory):
•
•
DIR = 1 defines typically a memory-to-peripheral transfer. More generally, if DIR = 1:
–
The source attributes are defined by the DMA_MARx register, the MSIZE[1:0]
field and MINC bit of the DMA_CCRx register.
Regardless of their usual naming, these ‘memory’ register, field and bit are used to
define the source peripheral in peripheral-to-peripheral mode.
–
The destination attributes are defined by the DMA_PARx register, the PSIZE[1:0]
field and PINC bit of the DMA_CCRx register.
Regardless of their usual naming, these ‘peripheral’ register, field and bit are used
to define the destination memory in memory-to-memory mode.
DIR = 0 defines typically a peripheral-to-memory transfer. More generally, if DIR = 0:
–
The source attributes are defined by the DMA_PARx register, the PSIZE[1:0] field
and PINC bit of the DMA_CCRx register.
Regardless of their usual naming, these ‘peripheral’ register, field and bit are used
to define the source memory in memory-to-memory mode
–
360/1290
The destination attributes are defined by the DMA_MARx register, the
MSIZE[1:0] field and MINC bit of the DMA_CCRx register.
Regardless of their usual naming, these ‘memory’ register, field and bit are used to
define the destination peripheral in peripheral-to-peripheral mode.
RM0461 Rev 10
RM0461
Direct memory access controller (DMA)
11.4.6
DMA data width, alignment and endianness
When PSIZE[1:0] and MSIZE[1:0] are not equal, the DMA controller performs some data
alignments as described in Table 68.
Table 68. Programmable data width and endian behavior (when PINC = MINC = 1)
Source
port
width
(MSIZE
if
DIR = 1,
else
PSIZE)
Destinat
ion port
Number
width
of data
(PSIZE
items to
if
transfer
DIR = 1,
(NDT)
else
MSIZE)
Source content:
address / data
(DMA_CMARx if
DIR = 1, else
DMA_CPARx)
DMA transfers
Destination
content:
address / data
(DMA_CPARx if
DIR = 1, else
DMA_CMARx)
8
8
8
@0x0 / B0
@0x1 / B1
@0x2 / B2
@0x3 / B3
1: read B0[7:0] @0x0 then write B0[7:0] @0x0
2: read B1[7:0] @0x1 then write B1[7:0] @0x1
3: read B2[7:0] @0x2 then write B2[7:0] @0x2
4: read B3[7:0] @0x3 then write B3[7:0] @0x3
@0x0 / B0
@0x1 / B1
@0x2 / B2
@0x3 / B3
8
16
4
@0x0 / B0
@0x1 / B1
@0x2 / B2
@0x3 / B3
1: read B0[7:0] @0x0 then write 00B0[15:0] @0x0
2: read B1[7:0] @0x1 then write 00B1[15:0] @0x2
3: read B2[7:0] @0x2 then write 00B2[15:0] @0x4
4: read B3[7:0] @0x3 then write 00B3[15:0] @0x6
@0x0 / 00B0
@0x2 / 00B1
@0x4 / 00B2
@0x6 / 00B3
8
32
4
@0x0 / B0
@0x1 / B1
@0x2 / B2
@0x3 / B3
1: read B0[7:0] @0x0 then write 000000B0[31:0] @0x0
2: read B1[7:0] @0x1 then write 000000B1[31:0] @0x4
3: read B2[7:0] @0x2 then write 000000B2[31:0] @0x8
4: read B3[7:0] @0x3 then write 000000B3[31:0] @0xC
@0x0 / 000000B0
@0x4 / 000000B1
@0x8 / 000000B2
@0xC / 000000B3
16
8
4
@0x0 / B1B0
@0x2 / B3B2
@0x4 / B5B4
@0x6 / B7B6
1: read B1B0[15:0] @0x0 then write B0[7:0] @0x0
2: read B3B2[15:0] @0x2 then write B2[7:0] @0x1
3: read B5B4[15:0] @0x4 then write B4[7:0] @0x2
4: read B7B6[15:0] @0x6 then write B6[7:0] @0x3
@0x0 / B0
@0x1 / B2
@0x2 / B4
@0x3 / B6
16
16
4
@0x0 / B1B0
@0x2 / B3B2
@0x4 / B5B4
@0x6 / B7B6
1: read B1B0[15:0] @0x0 then write B1B0[15:0] @0x0
2: read B3B2[15:0] @0x2 then write B3B2[15:0] @0x2
3: read B5B4[15:0] @0x4 then write B5B4[15:0] @0x4
4: read B7B6[15:0] @0x6 then write B7B6[15:0] @0x6
@0x0 / B1B0
@0x2 / B3B2
@0x4 / B5B4
@0x6 / B7B6
16
32
4
@0x0 / B1B0
@0x2 / B3B2
@0x4 / B5B4
@0x6 / B7B6
1: read B1B0[15:0] @0x0 then write 0000B1B0[31:0] @0x0
2: read B3B2[15:0] @0x2 then write 0000B3B2[31:0] @0x4
3: read B5B4[15:0] @0x4 then write 0000B5B4[31:0] @0x8
4: read B7B6[15:0] @0x6 then write 0000B7B6[31:0] @0xC
@0x0 / 0000B1B0
@0x4 / 0000B3B2
@0x8 / 0000B5B4
@0xC / 0000B7B6
32
8
4
@0x0 / B3B2B1B0
@0x4 / B7B6B5B4
@0x8 / BBBAB9B8
@0xC / BFBEBDBC
1: read B3B2B1B0[31:0] @0x0 then write B0[7:0] @0x0
2: read B7B6B5B4[31:0] @0x4 then write B4[7:0] @0x1
3: read BBBAB9B8[31:0] @0x8 then write B8[7:0] @0x2
4: read BFBEBDBC[31:0] @0xC then write BC[7:0] @0x3
@0x0 / B0
@0x1 / B4
@0x2 / B8
@0x3 / BC
32
16
4
@0x0 / B3B2B1B0
@0x4 / B7B6B5B4
@0x8 / BBBAB9B8
@0xC / BFBEBDBC
1: read B3B2B1B0[31:0] @0x0 then write B1B0[15:0] @0x0
2: read B7B6B5B4[31:0] @0x4 then write B5B4[15:0] @0x2
3: read BBBAB9B8[31:0] @0x8 then write B9B8[15:0] @0x4
4: read BFBEBDBC[31:0] @0xC then write BDBC[15:0] @0x6
@0x0 / B1B0
@0x2 / B5B4
@0x4 / B9B8
@0x6 / BDBC
32
32
4
@0x0 / B3B2B1B0
@0x4 / B7B6B5B4
@0x8 / BBBAB9B8
@0xC / BFBEBDBC
1: read B3B2B1B0[31:0] @0x0 then write B3B2B1B0[31:0] @0x0
2: read B7B6B5B4[31:0] @0x4 then write B7B6B5B4[31:0] @0x4
3: read BBBAB9B8[31:0] @0x8 then write BBBAB9B8[31:0] @0x8
4: read BFBEBDBC[31:0] @0xC then write BFBEBDBC[31:0] @0xC
@0x0 / B3B2B1B0
@0x4 / B7B6B5B4
@0x8 / BBBAB9B8
@0xC / BFBEBDBC
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Direct memory access controller (DMA)
RM0461
Addressing AHB peripherals not supporting byte/half-word write transfers
When the DMA controller initiates an AHB byte or half-word write transfer, the data are
duplicated on the unused lanes of the AHB master 32-bit data bus (HWDATA[31:0]).
When the AHB slave peripheral does not support byte or half-word write transfers and does
not generate any error, the DMA controller writes the 32 HWDATA bits as shown in the two
examples below:
•
To write the half-word 0xABCD, the DMA controller sets the HWDATA bus to
0xABCDABCD with a half-word data size (HSIZE = HalfWord in AHB master bus).
•
To write the byte 0xAB, the DMA controller sets the HWDATA bus to 0xABABABAB
with a byte data size (HSIZE = Byte in the AHB master bus).
Assuming the AHB/APB bridge is an AHB 32-bit slave peripheral that does not take into
account the HSIZE data, any AHB byte or half-word transfer is changed into a 32-bit APB
transfer as described below:
11.4.7
•
An AHB byte write transfer of 0xB0 to one of the 0x0, 0x1, 0x2 or 0x3 addresses, is
converted to an APB word write transfer of 0xB0B0B0B0 to the 0x0 address.
•
An AHB half-word write transfer of 0xB1B0 to the 0x0 or 0x2 addresses, is converted to
an APB word write transfer of 0xB1B0B1B0 to the 0x0 address.
DMA error management
A DMA transfer error is generated when reading from or writing to a reserved address
space. When a DMA transfer error occurs during a DMA read or write access, the faulty
channel x is automatically disabled through a hardware clear of its EN bit in the
corresponding DMA_CCRx register.
The TEIFx bit of the DMA_ISR register is set. An interrupt is then generated if the TEIE bit of
the DMA_CCRx register is set.
The EN bit of the DMA_CCRx register can not be set again by software (channel x reactivated) until the TEIFx bit of the DMA_ISR register is cleared (by setting the CTEIFx bit of
the DMA_IFCR register).
When the software is notified with a transfer error over a channel which involves a
peripheral, the software has first to stop this peripheral in DMA mode, in order to disable any
pending or future DMA request. Then software may normally reconfigure both DMA and the
peripheral in DMA mode for a new transfer.
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RM0461 Rev 10
RM0461
Direct memory access controller (DMA)
11.5
DMA interrupts
An interrupt can be generated on a half transfer, transfer complete or transfer error for each
DMA channel x. Separate interrupt enable bits are available for flexibility.
Table 69. DMA interrupt requests
Event flag
Interrupt
enable bit
Half transfer on channel x
HTIFx
HTIEx
Transfer complete on channel x
TCIFx
TCIEx
Transfer error on channel x
TEIFx
TEIEx
Half transfer or transfer complete or transfer error on channel x
GIFx
-
Interrupt request
Channel x interrupt
11.6
Interrupt event
DMA registers
Refer to Section 1.2 for a list of abbreviations used in register descriptions.
The DMA registers have to be accessed by words (32-bit).
11.6.1
DMA interrupt status register (DMA_ISR)
Address offset: 0x00
Reset value: 0x0000 0000
This register may mix privileged and unprivileged information, depending on the privileged
mode of each channel (PRIV bit of the DMA_CCRx register). A privileged software can read
the full interrupt status. An unprivileged software is restricted to read the status of
unprivileged channel(s), other privileged bit fields returning zero.
Every status bit is cleared by hardware when the software sets the corresponding clear bit
or the corresponding global clear bit CGIFx, in the DMA_IFCR register, provided that, if the
channel x is in privileged mode, then the software access to DMA_IFCR is also privileged.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
TEIF7
HTIF7
TCIF7
GIF7
TEIF6
HTIF6
TCIF6
GIF6
TEIF5
HTIF5
TCIF5
GIF5
r
r
r
r
r
r
r
r
r
r
r
r
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TEIF4
HTIF4
TCIF4
GIF4
TEIF3
HTIF3
TCIF3
GIF3
TEIF2
HTIF2
TCIF2
GIF2
TEIF1
HTIF1
TCIF1
GIF1
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
Bits 31:28 Reserved, must be kept at reset value.
Bit 27 TEIF7: Transfer error (TE) flag for channel 7
0: No TE event
1: A TE event occurred.
Bit 26 HTIF7: Half transfer (HT) flag for channel 7
0: No HT event
1: An HT event occurred.
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Direct memory access controller (DMA)
RM0461
Bit 25 TCIF7: Transfer complete (TC) flag for channel 7
0: No TC event
1: A TC event occurred.
Bit 24 GIF7: Global interrupt flag for channel 7
0: No TE, HT, or TC event
1: A TE, HT, or TC event occurred.
Bit 23 TEIF6: Transfer error (TE) flag for channel 6
0: No TE event
1: A TE event occurred.
Bit 22 HTIF6: Half transfer (HT) flag for channel 6
0: No HT event
1: An HT event occurred.
Bit 21 TCIF6: Transfer complete (TC) flag for channel 6
0: No TC event
1: A TC event occurred.
Bit 20 GIF6: Global interrupt flag for channel 6
0: No TE, HT, or TC event
1: A TE, HT, or TC event occurred.
Bit 19 TEIF5: Transfer error (TE) flag for channel 5
0: No TE event
1: A TE event occurred.
Bit 18 HTIF5: Half transfer (HT) flag for channel 5
0: No HT event
1: An HT event occurred.
Bit 17 TCIF5: Transfer complete (TC) flag for channel 5
0: No TC event
1: A TC event occurred.
Bit 16 GIF5: Global interrupt flag for channel 5
0: No TE, HT, or TC event
1: a TE, HT, or TC event occurred.
Bit 15 TEIF4: Transfer error (TE) flag for channel 4
0: No TE event
1: A TE event occurred.
Bit 14 HTIF4: Half transfer (HT) flag for channel 4
0: No HT event
1: An HT event occurred.
Bit 13 TCIF4: Transfer complete (TC) flag for channel 4
0: No TC event
1: A TC event occurred.
Bit 12 GIF4: Global interrupt flag for channel 4
0: No TE, HT, or TC event
1:A TE, HT, or TC event occurred.
Bit 11 TEIF3: Transfer error (TE) flag for channel 3
0: No TE event
1: A TE event occurred.
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Direct memory access controller (DMA)
Bit 10 HTIF3: Half transfer (HT) flag for channel 3
0: No HT event
1: An HT event occurred.
Bit 9 TCIF3: Transfer complete (TC) flag for channel 3
0: no TC event
1: A TC event occurred.
Bit 8 GIF3: Global interrupt flag for channel 3
0: No TE, HT, or TC event
1: A TE, HT, or TC event occurred.
Bit 7 TEIF2: Transfer error (TE) flag for channel 2
0: No TE event
1: A TE event occurred.
Bit 6 HTIF2: Half transfer (HT) flag for channel 2
0: No HT event
1: An HT event occurred.
Bit 5 TCIF2: Transfer complete (TC) flag for channel 2
0: No TC event
1: A TC event occurred.
Bit 4 GIF2: Global interrupt flag for channel 2
0: No TE, HT, or TC event
1: A TE, HT, or TC event occurred.
Bit 3 TEIF1: Transfer error (TE) flag for channel 1
0: No TE event
1: A TE event occurred.
Bit 2 HTIF1: Half transfer (HT) flag for channel 1
0: No HT event
1: An HT event occurred.
Bit 1 TCIF1: Transfer complete (TC) flag for channel 1
0: No TC event
1: A TC event occurred.
Bit 0 GIF1: Global interrupt flag for channel 1
0: No TE, HT, or TC event
1: A TE, HT, or TC event occurred.
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Direct memory access controller (DMA)
11.6.2
RM0461
DMA interrupt flag clear register (DMA_IFCR)
Address offset: 0x04
Reset value: 0x0000 0000
This register may mix privileged and unprivileged information, depending on the privileged
mode of each channel (PRIV bit of the DMA_CCRx register).
A privileged software is able to set any flag clear bit of the DMA_IFCR, and order DMA
hardware to clear any corresponding flag(s) in the DMA_ISR register.
An unprivileged software is restricted to order DMA hardware to clear the unprivileged
flag(s) in the DMA_ISR, by setting any unprivileged corresponding flag clear bit(s) of the
DMA_IFCR register.
Setting the global clear bit CGIFx of the channel x in this DMA_IFCR register, causes the
DMA hardware to clear the corresponding GIFx bit and any individual flag among TEIFx,
HTIFx, TCIFx, in the DMA_ISR register.
Setting any individual clear bit among CTEIFx, CHTIFx, CTCIFx in this DMA_IFCR register,
causes the DMA hardware to clear the corresponding individual flag and the global flag
GIFx in the DMA_ISR register, provided that none of the two other individual flags is set.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
CTEIF7
CHTIF7
CTCIF7
CGIF7
CTEIF6
CHTIF6
CTCIF6
CGIF6
CTEIF5
CHTIF5
CTCIF5
CGIF5
w
w
w
w
w
w
w
w
w
w
w
w
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CTEIF4
CHTIF4
CTCIF4
CGIF4
CTEIF3
CHTIF3
CTCIF3
CGIF3
CTEIF2
CHTIF2
CTCIF2
CGIF2
CTEIF1
CHTIF1
CTCIF1
CGIF1
Writing 0 into any flag clear bit has no effect.
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
Bits 31:28 Reserved, must be kept at reset value.
Bit 27 CTEIF7: Transfer error flag clear for channel 7
Bit 26 CHTIF7: Half transfer flag clear for channel 7
Bit 25 CTCIF7: Transfer complete flag clear for channel 7
Bit 24 CGIF7: Global interrupt flag clear for channel 7
Bit 23 CTEIF6: Transfer error flag clear for channel 6
Bit 22 CHTIF6: Half transfer flag clear for channel 6
Bit 21 CTCIF6: Transfer complete flag clear for channel 6
Bit 20 CGIF6: Global interrupt flag clear for channel 6
Bit 19 CTEIF5: Transfer error flag clear for channel 5
Bit 18 CHTIF5: Half transfer flag clear for channel 5
Bit 17 CTCIF5: Transfer complete flag clear for channel 5
Bit 16 CGIF5: Global interrupt flag clear for channel 5
Bit 15 CTEIF4: Transfer error flag clear for channel 4
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Direct memory access controller (DMA)
Bit 14 CHTIF4: Half transfer flag clear for channel 4
Bit 13 CTCIF4: Transfer complete flag clear for channel 4
Bit 12 CGIF4: Global interrupt flag clear for channel 4
Bit 11 CTEIF3: Transfer error flag clear for channel 3
Bit 10 CHTIF3: Half transfer flag clear for channel 3
Bit 9 CTCIF3: Transfer complete flag clear for channel 3
Bit 8 CGIF3: Global interrupt flag clear for channel 3
Bit 7 CTEIF2: Transfer error flag clear for channel 2
Bit 6 CHTIF2: Half transfer flag clear for channel 2
Bit 5 CTCIF2: Transfer complete flag clear for channel 2
Bit 4 CGIF2: Global interrupt flag clear for channel 2
Bit 3 CTEIF1: Transfer error flag clear for channel 1
Bit 2 CHTIF1: Half transfer flag clear for channel 1
Bit 1 CTCIF1: Transfer complete flag clear for channel 1
Bit 0 CGIF1: Global interrupt flag clear for channel 1
11.6.3
DMA channel x configuration register (DMA_CCRx)
Address offset: 0x08 + 0x14 * (x - 1), (x = 1 to 7)
Reset value: 0x0000 0000
This register contains privileged information: the privileged state of the channel x (PRIV
control bit).
Modifying the PRIV bit must be performed by a privileged write access to this register.
Except PRIV control bit, any other register field is non-readable by an unprivileged software
if the PRIV bit is set.
The register fields/bits PRIV, MEM2MEM, PL[1:0], MSIZE[1:0], PSIZE[1:0], MINC, PINC,
and DIR are read-only when EN = 1.
The states of MEM2MEM and CIRC bits must not be both high at the same time.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PRIV
Res.
Res.
Res.
Res.
rw
15
14
Res.
MEM2
MEM
rw
13
12
PL[1:0]
rw
rw
11
10
9
8
MSIZE[1:0]
PSIZE[1:0]
rw
rw
rw
rw
7
6
5
4
3
2
1
0
MINC
PINC
CIRC
DIR
TEIE
HTIE
TCIE
EN
rw
rw
rw
rw
rw
rw
rw
rw
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Direct memory access controller (DMA)
RM0461
Bits 31:21 Reserved, must be kept at reset value.
Bit 20 PRIV: Privileged mode
This bit can only be set and cleared by a privileged software.
0: Disabled
1: Enabled
This bit must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).
Bits 19:15 Reserved, must be kept at reset value.
Bit 14 MEM2MEM: Memory-to-memory mode
0: Disabled
1: Enabled
Note: This bit is set and cleared by software (privileged software if the channel is in privileged
mode).
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).
Bits 13:12 PL[1:0]: Priority level
00: Low
01: Medium
10: High
11: Very high
Note: This bitfield is set and cleared by software (privileged software if the channel is in
privileged mode).
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).
Bits 11:10 MSIZE[1:0]: Memory size
Defines the data size of each DMA transfer to the identified memory.
In memory-to-memory mode, this bitfield identifies the memory source if DIR = 1 and the
memory destination if DIR = 0.
In peripheral-to-peripheral mode, this bitfield identifies the peripheral source if DIR = 1 and
the peripheral destination if DIR = 0.
00: 8 bits
01: 16 bits
10: 32 bits
11: Reserved
Note: This bitfield is set and cleared by software (privileged software if the channel is in
privileged mode).
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).
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Direct memory access controller (DMA)
Bits 9:8 PSIZE[1:0]: Peripheral size
Defines the data size of each DMA transfer to the identified peripheral.
In memory-to-memory mode, this bitfield identifies the memory destination if DIR = 1 and the
memory source if DIR = 0.
In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination if DIR = 1
and the peripheral source if DIR = 0.
00: 8 bits
01: 16 bits
10: 32 bits
11: Reserved
Note: This bitfield is set and cleared by software (privileged software if the channel is in
privileged mode).
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).
Bit 7 MINC: Memory increment mode
Defines the increment mode for each DMA transfer to the identified memory.
In memory-to-memory mode, this bit identifies the memory source if DIR = 1 and the memory
destination if DIR = 0.
In peripheral-to-peripheral mode, this bit identifies the peripheral source if DIR = 1 and the
peripheral destination if DIR = 0.
0: Disabled
1: Enabled
Note: This bit is set and cleared by software (privileged software if the channel is in privileged
mode).
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).
Bit 6 PINC: Peripheral increment mode
Defines the increment mode for each DMA transfer to the identified peripheral.
n memory-to-memory mode, this bit identifies the memory destination if DIR = 1 and the
memory source if DIR = 0.
In peripheral-to-peripheral mode, this bit identifies the peripheral destination if DIR = 1 and
the peripheral source if DIR = 0.
0: Disabled
1: Enabled
Note: This bit is set and cleared by software (privileged software if the channel is in privileged
mode).
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).
Bit 5 CIRC: Circular mode
0: Disabled
1: Enabled
Note: This bit is set and cleared by software (privileged software if the channel is in privileged
mode).
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).
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Bit 4 DIR: Data transfer direction
This bit must be set only in memory-to-peripheral and peripheral-to-memory modes.
0: Read from peripheral
–
Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register.
This is still valid in a memory-to-memory mode.
–
Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx
register. This is still valid in a peripheral-to-peripheral mode.
1: Read from memory
–
Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx
register. This is still valid in a memory-to-memory mode.
–
Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register.
This is still valid in a peripheral-to-peripheral mode.
Note: This bit is set and cleared by software (privileged software if the channel is in privileged
mode).
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).
Bit 3 TEIE: Transfer error interrupt enable
0: Disabled
1: Enabled
Note: This bit is set and cleared by software (privileged software if the channel is in privileged
mode).
It must not be written when the channel is enabled (EN = 1).
It is not read-only when the channel is enabled (EN = 1).
Bit 2 HTIE: Half transfer interrupt enable
0: Disabled
1: Enabled
Note: This bit is set and cleared by software (privileged software if the channel is in privileged
mode).
It must not be written when the channel is enabled (EN = 1).
It is not read-only when the channel is enabled (EN = 1).
Bit 1 TCIE: Transfer complete interrupt enable
0: Disabled
1: Enabled
Note: This bit is set and cleared by software (privileged software if the channel is in privileged
mode).
It must not be written when the channel is enabled (EN = 1).
It is not read-only when the channel is enabled (EN = 1).
Bit 0 EN: Channel enable
When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again
by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by
setting the CTEIFx bit of the DMA_IFCR register).
0: Disabled
1: Enabled
Note: This bit is set and cleared by software (privileged software if the channel is in privileged
mode)
370/1290
RM0461 Rev 10
RM0461
Direct memory access controller (DMA)
11.6.4
DMA channel x number of data to transfer register (DMA_CNDTRx)
Address offset: 0x0C + 0x14 * (x - 1), (x = 1 to 7)
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
NDT[17:16]
16
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
NDT[15:0]
rw
Bits 31:18 Reserved, must be kept at reset value.
Bits 17:0 NDT[17:0]: Number of data to transfer (0 to 218 - 1)
This bitfield is updated by hardware when the channel is enabled:
–
It is decremented after each single DMA ‘read followed by write’ transfer, indicating
the remaining amount of data items to transfer.
–
It is kept at zero when the programmed amount of data to transfer is reached, if the
channel is not in circular mode (CIRC = 0 in the DMA_CCRx register).
–
It is reloaded automatically by the previously programmed value, when the transfer
is complete, if the channel is in circular mode (CIRC = 1).
If this bitfield is zero, no transfer can be served whatever the channel status (enabled or not).
Note: This bitfield is set and cleared by software (privileged software if the channel is in
privileged mode).
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).
11.6.5
DMA channel x peripheral address register (DMA_CPARx)
Address offset: 0x10 + 0x14 * (x - 1), (x = 1 to 7)
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
PA[31:16]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
PA[15:0]
rw
RM0461 Rev 10
371/1290
374
Direct memory access controller (DMA)
RM0461
Bits 31:0 PA[31:0]: Peripheral address
It contains the base address of the peripheral data register from/to which the data is
read/written.
When PSIZE[1:0] = 01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned
to a half-word address.
When PSIZE = 10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically
aligned to a word address.
In memory-to-memory mode, this bitfield identifies the memory destination address if DIR = 1
and the memory source address if DIR = 0.
In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination address
DIR = 1 and the peripheral source address if DIR = 0.
Note: This bitfield is set and cleared by software (privileged software if the channel is in
privileged mode).
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).
11.6.6
DMA channel x memory address register (DMA_CMARx)
Address offset: 0x14 + 0x14 * (x - 1), (x = 1 to 7)
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
23
22
21
20
19
18
17
16
rw
rw
rw
rw
rw
rw
rw
rw
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
MA[31:16]
MA[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:0 MA[31:0]: Peripheral address
It contains the base address of the memory from/to which the data is read/written.
When MSIZE[1:0] = 01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned
to a half-word address.
When MSIZE = 10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically
aligned to a word address.
In memory-to-memory mode, this bitfield identifies the memory source address if DIR = 1 and
the memory destination address if DIR = 0.
In peripheral-to-peripheral mode, this bitfield identifies the peripheral source address DIR = 1
and the peripheral destination address if DIR = 0.
Note: This bitfield is set and cleared by software (privileged software if the channel is in
privileged mode).
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).
11.6.7
DMA register map
372/1290
RM0461 Rev 10
GIF1
0
TCIF1
0
HTIF1
0
GIF2
0
TEIF1
0
TCIF2
0
HTIF2
0
GIF3
0
TEIF2
0
TCIF3
0
HTIF3
0
GIF4
0
TEIF3
0
TCIF4
0
HTIF4
0
GIF5
0
TEIF4
0
TCIF5
0
HTIF5
0
GIF6
0
TEIF5
TCIF6
0
HTIF6
0
GIF7
TCIF7
0
TEIF6
HTIF7
Res.
TEIF7
Reset value
Res.
DMA_ISR
Res.
0x000
Res.
Offset Register name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 70. DMA register map and reset values
0
0
0
0
0
RM0461
Direct memory access controller (DMA)
0
0
0
0
0
0
0
0
Res.
MEM2MEM
PL[1:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x054
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PINC
CIRC
DIR
TEIE
HTIE
TCIE
EN
0
MINC
0
PSIZE[1:0]
PL[1:0]
0
MSIZE[1:0]
MEM2MEM
Res.
Res.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PL[1:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PINC
CIRC
DIR
TEIE
HTIE
TCIE
EN
PSIZE[1:0]
MINC
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
MSIZE[1:0]
MEM2MEM
Res.
Res.
Res.
Res.
Res.
PRIV
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
NDT[17:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MA[31:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PINC
CIRC
DIR
TEIE
HTIE
TCIE
EN
PSIZE[1:0]
MINC
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
MSIZE[1:0]
PL[1:0]
Res.
Res.
Res.
Res.
Res.
PRIV
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reserved.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
NDT[17:0]
0
0
0
PA[31:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DMA_CMAR4
Reset value
0
0
MEM2MEM
0x050
0
0
DMA_CPAR4
Reset value
0
PA[31:0]
Reset value
0x04C
0
0
Res.
DMA_CNDTR4
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Reset value
0x048
0
NDT[17:0]
Reserved
DMA_CCR4
0
0
Res.
0x044
0
DMA_CMAR3
Reset value
0
Res.
Res.
Res.
PRIV
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
0x040
0
Reserved.
Res.
0x03C
0
DMA_CPAR3
Reset value
CGIF1
Res.
Res.
Res.
Res.
0
Reset value
0x038
0
MA[31:0]
Res.
DMA_CNDTR3
CTCIF1
Res.
0
Reset value
0x034
0
EN
Res.
0
Reserved
DMA_CCR3
0
PA[31:0]
Res.
0x030
CHTIF1
Res.
0
DMA_CMAR2
Reset value
0
TCIE
PRIV
0
0
Res.
0x02C
0
0
Res.
0x028
0
HTIE
Res.
0
DMA_CPAR2
Reset value
0
CGIF2
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Reset value
0x024
0
0
Reserved.
Res.
0x020
0
CTEIF1
Res.
0
Reset value
DMA_CNDTR2
0
0
NDT[17:0]
Reserved
DMA_CCR2
0
MA[31:0]
Res.
0x01C
0
TEIE
Res.
0
DMA_CMAR1
Reset value
0
PA[31:0]
Res.
0x018
0
CTCIF2
Res.
0
0
Res.
0x014
0
DIR
0
CHTIF2
0
PINC
0
CIRC
0
CGIF3
CHTIF4
0
CTEIF2
CGIF5
CTEIF4
0
MINC
CTCIF5
0
DMA_CPAR1
Reset value
CTCIF3
CHTIF5
0
PSIZE[1:0]
CGIF6
CTEIF5
0
Reset value
0x010
CHTIF3
CTCIF6
0
MSIZE[1:0]
CHTIF6
0
Res.
Res.
Res.
Res.
Res.
0x00C
CGIF4
CGIF7
CTEIF6
0
0
CTEIF3
CTCIF7
0
Reset value
DMA_CNDTR1
CTCIF4
CHTIF7
0
Res.
Res.
CTEIF7
Res.
Res.
DMA_CCR1
Res.
0x008
Res.
Reset value
Res.
Res.
DMA_IFCR
Res.
0x004
Res.
Offset Register name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 70. DMA register map and reset values (continued)
0
0
MA[31:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reserved
0
0
Reserved.
RM0461 Rev 10
373/1290
374
Direct memory access controller (DMA)
RM0461
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x08C
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PSIZE[1:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PL[1:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PINC
CIRC
DIR
TEIE
HTIE
TCIE
EN
PSIZE[1:0]
MINC
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
MSIZE[1:0]
MEM2MEM
Res.
Res.
Res.
Res.
Res.
PRIV
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MA[31:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PINC
CIRC
DIR
TEIE
HTIE
TCIE
EN
0
MINC
0
PSIZE[1:0]
PL[1:0]
0
0
MSIZE[1:0]
MEM2MEM
Res.
Res.
Res.
Res.
Res.
PRIV
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reserved.
0
0
0
0
0
0
0
0
NDT[17:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PA[31:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MA[31:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Refer to Section 2.4 for the register boundary addresses.
374/1290
MSIZE[1:0]
Res.
Res.
0
0
PA[31:0]
DMA_CMAR7
Reset value
0
0
NDT[17:0]
DMA_CPAR7
Reset value
0
0
Reset value
0x088
0
0
Res.
0x084
0
0
0
Reserved.
Reset value
DMA_CNDTR7
0
EN
0
Reserved
DMA_CCR7
0
TCIE
0
Res.
0x080
0
HTIE
0
DMA_CMAR6
Reset value
0
DIR
0
Res.
0x07C
0
TEIE
0
Res.
0x078
0
PINC
0
DMA_CPAR6
Reset value
0
CIRC
0
Reset value
0x074
0
0
MA[31:0]
Res.
DMA_CNDTR6
0
MINC
0
Reset value
0x070
PL[1:0]
0
Reserved
DMA_CCR6
MEM2MEM
0
Res.
0x06C
0
DMA_CMAR5
Reset value
0
PA[31:0]
Res.
0x068
DMA_CPAR5
Reset value
0
NDT[17:0]
0
Res.
0x064
Res.
Res.
Res.
Res.
Reset value
0x060
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DMA_CNDTR5
Res.
0x05C
0
0
Res.
Reset value
PRIV
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DMA_CCR5
Res.
0x058
Res.
Offset Register name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 70. DMA register map and reset values (continued)
RM0461 Rev 10
RM0461
DMA request multiplexer (DMAMUX)
12
DMA request multiplexer (DMAMUX)
12.1
Introduction
A peripheral indicates a request for DMA transfer by setting its DMA request signal. The
DMA request is pending until served by the DMA controller that generates a DMA
acknowledge signal, and the corresponding DMA request signal is deasserted.
In this document, the set of control signals required for the DMA request/acknowledge
protocol is not explicitly shown or described, and it is referred to as DMA request line.
The DMAMUX request multiplexer enables routing a DMA request line between the
peripherals and the DMA controllers of the product. The routing function is ensured by a
programmable multi-channel DMA request line multiplexer. Each channel selects a unique
DMA request line, unconditionally or synchronously with events from its DMAMUX
synchronization inputs. The DMAMUX may also be used as a DMA request generator from
programmable events on its input trigger signals.
The number of DMAMUX instances and their main characteristics are specified in
Section 12.3.1.
The assignment of DMAMUX request multiplexer inputs to the DMA request lines from
peripherals and to the DMAMUX request generator outputs, the assignment of DMAMUX
request multiplexer outputs to DMA controller channels, and the assignment of DMAMUX
synchronizations and trigger inputs to internal and external signals depend upon product
implementation. They are detailed in Section 12.3.2.
RM0461 Rev 10
375/1290
392
DMA request multiplexer (DMAMUX)
12.2
RM0461
DMAMUX main features
•
14-channel programmable DMA request line multiplexer output
•
4-channel DMA request generator
•
21 trigger inputs to DMA request generator
•
21 synchronization inputs
•
Per DMA request generator channel:
•
•
–
DMA request trigger input selector
–
DMA request counter
–
Event overrun flag for selected DMA request trigger input
Per DMA request line multiplexer channel output:
–
38 input DMA request lines from peripherals
–
One DMA request line output
–
Synchronization input selector
–
DMA request counter
–
Event overrun flag for selected synchronization input
–
One event output, for DMA request chaining
Privileged / Unprivileged support:
–
Support for AHB privileged and unprivileged DMA transfers, independently, at a
channel level.
–
Privileged-aware AHB slave port.
12.3
DMAMUX implementation
12.3.1
DMAMUX1 instantiation
DMAMUX1 instantiated with the hardware configuration parameters listed in the following
table.
Table 71. DMAMUX instantiation
12.3.2
Feature
DMAMUX1
Number of DMAMUX output request channels
14
Number of DMAMUX request generator channels
4
Number of DMAMUX request trigger inputs
21
Number of DMAMUX synchronization inputs
21
Number of DMAMUX peripheral request inputs
38
DMAMUX1 mapping
The mapping of resources to DMAMUX1 is hardwired.
DMAMUX1 is used with DMA1 and DMA2
376/1290
•
DMAMUX1 channels 0 to 6 are connected to DMA1 channels 1 to 7
•
DMAMUX1 channels 7 to 13 are connected to DMA2 channels 1 to 7
RM0461 Rev 10
RM0461
DMA request multiplexer (DMAMUX)
Table 72. DMAMUX1: assignment of multiplexer inputs to resources
DMA
request
MUX input
Resource
DMA
request
MUX input
Resource
DMA
request
MUX input
Resource
1
dmamux_req_gen0
22
LPUART1_TX
43
Reserved
2
dmamux_req_gen1
23
TIM1_CH1
44
Reserved
3
dmamux_req_gen2
24
TIM1_CH2
45
Reserved
4
dmamux_req_gen3
25
TIM1_CH3
46
Reserved
5
ADC
26
TIM1_CH4
47
Reserved
6
DAC_OUT1
27
TIM1_UP
48
Reserved
7
SPI1_RX
28
TIM1_TRIG
49
Reserved
8
SPI1_TX
29
TIM1_COM
50
Reserved
9
SPI2_RX
30
TIM2_CH1
51
Reserved
10
SPI2_TX
31
TIM2_CH2
52
Reserved
11
I2C1_RX
32
TIM2_CH3
53
Reserved
12
I2C1_TX
33
TIM2_CH4
54
Reserved
13
I2C2_RX
34
TIM2_UP
55
Reserved
14
I2C2_TX
35
TIM16_CH1
56
Reserved
15
I2C3_RX
36
TIM16_UP
57
Reserved
16
I2C3_TX
37
TIM17_CH1
58
Reserved
17
USART1_RX
38
TIM17_UP
59
Reserved
18
USART1_TX
39
AES_IN
60
Reserved
19
USART2_RX
40
AES_OUT
61
Reserved
20
USART2_TX
41
SUBGHZSPI_RX
62
Reserved
21
LPUART1_RX
42
SUBGHZSPI_TX
63
Reserved
Table 73. DMAMUX1: assignment of trigger inputs to resources
Trigger input
Resource
Trigger input
Resource
0
EXTI LINE0
16
dmamux_evt0
1
EXTI LINE1
17
dmamux_evt1
2
EXTI LINE2
18
LPTIM1_OUT
3
EXTI LINE3
19
LPTIM2_OUT
4
EXTI LINE4
20
LPTIM3_OUT
5
EXTI LINE5
21
Reserved
6
EXTI LINE6
22
Reserved
7
EXTI LINE7
23
Reserved
8
EXTI LINE8
24
Reserved
9
EXTI LINE9
25
Reserved
10
EXTI LINE10
26
Reserved
11
EXTI LINE11
27
Reserved
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Table 73. DMAMUX1: assignment of trigger inputs to resources (continued)
Trigger input
Resource
Trigger input
Resource
12
EXTI LINE12
28
Reserved
13
EXTI LINE13
29
Reserved
14
EXTI LINE14
30
Reserved
15
EXTI LINE15
31
Reserved
Table 74. DMAMUX1: assignment of synchronization inputs to resources
378/1290
Sync. input
Resource
Sync. input
Resource
0
EXTI LINE0
16
dmamux_evt0
1
EXTI LINE1
17
dmamux_evt1
2
EXTI LINE2
18
LPTIM1_OUT
3
EXTI LINE3
19
LPTIM2_OUT
4
EXTI LINE4
20
LPTIM3_OUT
5
EXTI LINE5
21
Reserved
6
EXTI LINE6
22
Reserved
7
EXTI LINE7
23
Reserved
8
EXTI LINE8
24
Reserved
9
EXTI LINE9
25
Reserved
10
EXTI LINE10
26
Reserved
11
EXTI LINE11
27
Reserved
12
EXTI LINE12
28
Reserved
13
EXTI LINE13
29
Reserved
14
EXTI LINE14
30
Reserved
15
EXTI LINE15
31
Reserved
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RM0461
DMA request multiplexer (DMAMUX)
12.4
DMAMUX functional description
12.4.1
DMAMUX block diagram
Figure 37 shows the DMAMUX block diagram.
Figure 37. DMAMUX block diagram
32-bit AHB bus
dmamux_hclk
DMAMUX
Request multiplexer
AHB slave
interface
Channel m
DMAMUX_CmCR
DMA requests
from peripherals:
dmamux_req_inx
Channel 1
dm
am
ux
_r
eq
x
p
1
Channel 0
DMAMUX_C0CR
m
1
0
Privileged state of
the DMA channels:
dma_privx
m
1
0
DMA requests
to DMA
controllers:
dmamux_req_outx
m
1
0
DMA channels
events:
dmamux_evtx
Channel Ctrl
select
0
Request generator
Channel n
DMAMUX_RGCnCR
n
Channel 1
DMAMUX_RGC1CR
1
Channel 0
DMAMUX_RGC0CR
0
dmamux_req_genx
n+p+2
n+3
Sync
n+2
n+1
s
1 0
2
1
Interrupt
interface
t
Control registers
1
0
Trigger inputs:
dmamux_trgx
s
dmamux_ovr_it
1
0
Synchronization inputs:
dmamux_syncx
MS51702V1
DMAMUX features two main sub-blocks: the request line multiplexer and the request line
generator.
The implementation assigns:
•
DMAMUX request multiplexer sub-block inputs (dmamux_reqx) from peripherals
(dmamux_req_inx) and from channels of the DMAMUX request generator sub-block
(dmamux_req_genx)
•
DMAMUX request outputs to channels of DMA controllers (dmamux_req_outx)
•
Internal or external signals to DMA request trigger inputs (dmamux_trgx)
•
Internal or external signals to synchronization inputs (dmamux_syncx)
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12.4.2
RM0461
DMAMUX signals
Table 75 lists the DMAMUX signals.
Table 75. DMAMUX signals
Signal name
dmamux_hclk
dmamux_req_inx
dmamux_trgx
dmamux_req_genx
DMAMUX AHB clock
DMAMUX DMA request line inputs from peripherals
DMAMUX DMA request triggers inputs (to request generator sub-block)
DMAMUX request generator sub-block channels outputs
dmamux_reqx
DMAMUX request multiplexer sub-block inputs (from peripheral
requests and request generator channels)
dmamux_syncx
DMAMUX synchronization inputs (to request multiplexer sub-block)
dmamux_req_outx
DMAMUX requests outputs (to DMA controllers)
dma_privx
12.4.3
Description
Privileged mode of each DMA controller request channel
dmamux_evtx
DMAMUX events outputs
dmamux_ovr_it
DMAMUX overrun interrupts
DMAMUX channels
A DMAMUX channel is a request multiplexer channel that can include, depending upon the
selected input of the request multiplexer, an additional DMAMUX request generator
channel.
A DMAMUX request multiplexer channel is connected and dedicated to a single channel of
DMA controller(s).
Channel configuration procedure
Follow the sequence below to configure a DMAMUX x channel and the related DMA
channel y:
1.
12.4.4
Set to privileged or unprivileged the DMA channel y by a privileged write access to the
privileged control bit of the DMA channel y configuration register.
2.
Set and configure completely the DMA channel y, except enabling the channel y.
3.
Set and configure completely the related DMAMUX y channel.
4.
Last, activate the DMA channel y by setting the EN bit in the DMA y channel register.
1.
Set and configure completely the DMA channel y, except enabling the channel y.
2.
Set and configure completely the related DMAMUX y channel.
3.
Last, activate the DMA channel y by setting the EN bit in the DMA y channel register.
DMAMUX privileged / unprivileged channels
The DMAMUX is aware of the privileged or unprivileged state of a given DMA connected
channel, and manages consequently its DMAMUX requested channel.
Note:
380/1290
A DMA controller(s) channel must be first configured as privileged or unprivileged, before
the configuration of the connected DMAMUX channel.
RM0461 Rev 10
RM0461
Note:
DMA request multiplexer (DMAMUX)
A privileged software is able to access any DMAMUX register, privileged or unprivileged. An
unprivileged software is restricted to access only unprivileged DMAMUX register or register
fields.
When a privileged software configures a DMA channel x either as privileged, an
unprivileged software is not able to access (write is ignored, read returns zero) the related
DMAMUX channel registers or register fields.
12.4.5
DMAMUX request line multiplexer
The DMAMUX request multiplexer with its multiple channels ensures the actual routing of
DMA request/acknowledge control signals, named DMA request lines.
Each DMA request line is connected in parallel to all the channels of the DMAMUX request
line multiplexer.
A DMA request is sourced either from the peripherals, or from the DMAMUX request
generator.
The DMAMUX request line multiplexer channel x selects the DMA request line number as
configured by the DMAREQ_ID field in the DMAMUX_CxCR register.
Note:
The null value in the field DMAREQ_ID corresponds to no DMA request line selected.
Caution:
A same non-null DMAREQ_ID cannot be programmed to different x and y DMAMUX
request multiplexer channels (via DMAMUX_CxCR and DMAMUX_CyCR), except when the
application guarantees that the two connected DMA channels are not simultaneously active.
On top of the DMA request selection, the synchronization mode and/or the event generation
may be configured and enabled, if required.
Synchronization mode and channel event generation
Each DMAMUX request line multiplexer channel x can be individually synchronized by
setting the synchronization enable (SE) bit in the DMAMUX_CxCR register.
DMAMUX has multiple synchronization inputs. The synchronization inputs are connected in
parallel to all the channels of the request multiplexer.
The synchronization input is selected via the SYNC_ID field in the DMAMUX_CxCR register
of a given channel x.
When a channel is in this synchronization mode, the selected input DMA request line is
propagated to the multiplexer channel output, once a programmable rising/falling edge is
detected on the selected input synchronization signal, via the SPOL[1:0] field of the
DMAMUX_CxCR register.
Additionally, internally to the DMAMUX request multiplexer, there is a programmable DMA
request counter, which can be used for the channel request output generation, and for an
event generation. An event generation on the channel x output is enabled through the EGE
bit (event generation enable) of the DMAMUX_CxCR register.
As shown in Figure 39, upon the detected edge of the synchronization input, the pending
selected input DMA request line is connected to the DMAMUX multiplexer channel x output.
Note:
If a synchronization event occurs while there is no pending selected input DMA request line,
it is discarded. The following asserted input request lines is not connected to the DMAMUX
multiplexer channel output until a synchronization event occurs again.
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RM0461
From this point on, each time the connected DMAMUX request is served by the DMA
controller (a served request is deasserted), the DMAMUX request counter is decremented.
At its underrun, the DMA request counter is automatically loaded with the value in the
NBREQ field of the DMAMUX_CxCR register and the input DMA request line is
disconnected from the multiplexer channel x output.
Thus, the number of DMA requests transferred to the multiplexer channel x output following
a detected synchronization event, is equal to the value in the NBREQ field, plus one.
Note:
The NBREQ field value can be written by software only when both synchronization enable
bit (SE) and event generation enable bit (EGE) of the corresponding multiplexer channel x
are disabled.
Figure 38. Synchronization mode of the DMAMUX request line multiplexer channel
Selected DMA request line transferred to the output
DMA requests served
DMA request pending
Selected
dmamux_reqx
Not pending
dmamux_syncx
dmamux_req_outx
DMA request counter
4
3
2
1
0
4
dmamux_evtx
Synchronization event
Input DMA request line connected to output
DMA request counter underrun
DMA request counter auto-reload to NBREQ
Input DMA request line disconnected from output
Example: DMAMUX_CCRx configured with: NBREQ=4, SE=1, EGE=1, SPOL=01 (rising edge)
MSv41974V1
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DMA request multiplexer (DMAMUX)
Figure 39. Event generation of the DMA request line multiplexer channel
Selected DMA request line transferred to the output
Selected
dmamux_reqx
DMA request pending
Not pending
dmamux_req_outx
DMA request counter
3
2
1
0
3
2
1
0
3
2
1
0
SE
EGE
dmamux_evtx
DMA request counter reaches zero
Event is generated on the output
DMA request counter auto-reloads with NBREQ value
Example with: DMAMUX_CCRx configured with: NBREQ=3, SE=0, EGE=1
MSv41975V1
If EGE is enabled, the multiplexer channel generates a channel event, as a pulse of one
AHB clock cycle, when its DMA request counter is automatically reloaded with the value of
the programmed NBREQ field, as shown in Figure 38 and Figure 39.
Note:
If EGE is enabled and NBREQ = 0, an event is generated after each served DMA request.
Note:
A synchronization event (edge) is detected if the state following the edge remains stable for
more than two AHB clock cycles.
Upon writing into DMAMUX_CxCR register, the synchronization events are masked during
three AHB clock cycles.
Synchronization overrun and interrupt
If a new synchronization event occurs before the request counter underrun (the internal
request counter programmed via the NBREQ field of the DMAMUX_CxCR register), the
synchronization overrun flag bit SOFx is set in the DMAMUX_CSR register.
Note:
The request multiplexer channel x synchronization must be disabled
(DMAMUX_CxCR.SE = 0) when the use of the related channel of the DMA controller is
completed. Else, upon a new detected synchronization event, there is a synchronization
overrun due to the absence of a DMA acknowledge (that is, no served request) received
from the DMA controller.
The overrun flag SOFx is reset by setting the associated clear synchronization overrun flag
bit CSOFx in the DMAMUX_CFRDMAMUX_CCFR register.
Setting the synchronization overrun flag generates an interrupt if the synchronization
overrun interrupt enable bit SOIE is set in the DMAMUX_CxCR register.
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DMA request multiplexer (DMAMUX)
12.4.6
RM0461
DMAMUX request generator
The DMAMUX request generator produces DMA requests following trigger events on its
DMA request trigger inputs.
The DMAMUX request generator has multiple channels. DMA request trigger inputs are
connected in parallel to all channels.
The outputs of DMAMUX request generator channels are inputs to the DMAMUX request
line multiplexer.
Each DMAMUX request generator channel x has an enable bit GE (generator enable) in the
corresponding DMAMUX_RGxCR register.
The DMA request trigger input for the DMAMUX request generator channel x is selected
through the SIG_ID (trigger signal ID) field in the corresponding DMAMUX_RGxCR register.
Trigger events on a DMA request trigger input can be rising edge, falling edge or either
edge. The active edge is selected through the GPOL (generator polarity) field in the
corresponding DMAMUX_RGxCR register.
Upon the trigger event, the corresponding generator channel starts generating DMA
requests on its output. Each time the DMAMUX generated request is served by the
connected DMA controller (a served request is deasserted), a built-in (inside the DMAMUX
request generator) DMA request counter is decremented. At its underrun, the request
generator channel stops generating DMA requests and the DMA request counter is
automatically reloaded to its programmed value upon the next trigger event.
Thus, the number of DMA requests generated after the trigger event is GNBREQ + 1.
Note:
The GNBREQ field value can be written by software only when the enable GE bit of the
corresponding generator channel x is disabled.
There is no hardware write protection.
A trigger event (edge) is detected if the state following the edge remains stable for more
than two AHB clock cycles.
Upon writing into DMAMUX_RGxCR register, the trigger events are masked during three
AHB clock cycles.
Trigger overrun and interrupt
If a new DMA request trigger event occurs before the DMAMUX request generator counter
underrun (the internal counter programmed via the GNBREQ field of the DMAMUX_RGxCR
register), and if the request generator channel x was enabled via GE, then the request
trigger event overrun flag bit OFx is asserted by the hardware in the DMAMUX_RGSR
register.
Note:
The request generator channel x must be disabled (DMAMUX_RGxCR.GE = 0) when the
usage of the related channel of the DMA controller is completed. Else, upon a new detected
trigger event, there is a trigger overrun due to the absence of an acknowledge (that is, no
served request) received from the DMA.
The overrun flag OFx is reset by setting the associated clear overrun flag bit COFx in the
DMAMUX_RGCFR register.
Setting the DMAMUX request trigger overrun flag generates an interrupt if the DMA request
trigger event overrun interrupt enable bit OIE is set in the DMAMUX_RGxCR register.
384/1290
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RM0461
12.5
DMA request multiplexer (DMAMUX)
DMAMUX interrupts
An interrupt can be generated upon:
•
a synchronization event overrun in each DMA request line multiplexer channel
•
a trigger event overrun in each DMA request generator channel
For each case, per-channel in.dividual interrupt enable, status, and clear flag register bits
are available.
Table 76. DMAMUX interrupts
Interrupt signal
dmamuxovr_it
Interrupt event
Event flag
Clear bit
Enable bit
Synchronization event overrun
on channel x of the
DMAMUX request line multiplexer
SOFx
CSOFx
SOIE
Trigger event overrun
on channel x of the
DMAMUX request generator
OFx
COFx
OIE
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DMA request multiplexer (DMAMUX)
12.6
RM0461
DMAMUX registers
Refer to the table containing register boundary addresses for the DMAMUX base address.
DMAMUX registers may be accessed per byte (8-bit), half-word (16-bit), or word (32-bit).
The address must be aligned with the data size.
12.6.1
DMAMUX request line multiplexer channel x configuration register
(DMAMUX_CxCR)
Address offset: 0x000 + 0x04 * x (x = 0 to 13)
Reset value: 0x0000 0000
This register must be accessed by a privileged or unprivileged read/write, according to the
privileged mode of the considered DMAMUX request line multiplexer channel x, depending
on the privileged control bit of the connected of the connected DMA controller channel y.
This assumes that the DMAMUX x channel output is connected to the y channel of the DMA
(refer to the DMAMUX mapping implementation section).
31
30
29
Res.
Res.
Res.
28
27
rw
rw
26
25
24
23
22
rw
rw
rw
rw
rw
7
6
SYNC_ID[4:0]
21
20
19
18
rw
rw
rw
5
4
3
NBREQ[4:0]
15
14
13
12
11
10
9
8
Res.
Res.
Res.
Res.
Res.
Res.
EGE
SOIE
rw
rw
17
16
SPOL[1:0]
SE
rw
rw
rw
2
1
0
rw
rw
rw
DMAREQ_ID[7:0]
rw
rw
rw
rw
rw
Bits 31:29 Reserved, must be kept at reset value.
Bits 28:24 SYNC_ID[4:0]: Synchronization identification
Selects the synchronization input (see ).
Bits 23:19 NBREQ[4:0]: Number of DMA requests minus 1 to forward
Defines the number of DMA requests to forward to the DMA controller after a synchronization
event, and/or the number of DMA requests before an output event is generated.
This field must only be written when both SE and EGE bits are low.
Bits 18:17 SPOL[1:0]: Synchronization polarity
Defines the edge polarity of the selected synchronization input:
00: No event (no synchronization, no detection).
01: Rising edge
10: Falling edge
11: Rising and falling edges
Bit 16 SE: Synchronization enable
0: Synchronization disabled
1: Synchronization enabled
Bits 15:10 Reserved, must be kept at reset value.
Bit 9 EGE: Event generation enable
0: Event generation disabled
1: Event generation enabled
386/1290
RM0461 Rev 10
RM0461
DMA request multiplexer (DMAMUX)
Bit 8 SOIE: Synchronization overrun interrupt enable
0: Interrupt disabled
1: Interrupt enabled
Bits 7:0 DMAREQ_ID[7:0]: DMA request identification
Selects the input DMA request. See the DMAMUX table about assignments of multiplexer
inputs to resources.
12.6.2
DMAMUX request line multiplexer interrupt channel status register
(DMAMUX_CSR)
Address offset: 0x080
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
SOF13
SOF12
SOF11
SOF10
SOF9
SOF8
SOF7
SOF6
SOF5
SOF4
SOF3
SOF2
SOF1
SOF0
r
r
r
r
r
r
r
r
r
r
r
r
r
r
Bits 31:14 Reserved, must be kept at reset value.
Bits 13:0 SOF[13:0]: Synchronization overrun event flag
The flag is set when a synchronization event occurs on a DMA request line multiplexer
channel x, while the DMA request counter value is lower than NBREQ.
The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR
DMAMUX_CCFR register.
12.6.3
DMAMUX request line multiplexer interrupt channel clear flag register
(DMAMUX_CCFR)
Address offset: 0x084
Reset value: 0x0000 0000
This register must be written at bit level by an unprivileged or privileged write, according to
the privileged mode of the considered DMAMUX request line multiplexer channel x,
depending on the privileged control bit of the connected DMA controller channel y, and
considering that the DMAMUX x channel output is connected to the y channel of the DMA
(refer to the DMAMXUX mapping implementation section).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
CSOF
13
CSOF
12
CSOF
11
CSOF
10
CSOF
9
CSOF
8
CSOF
7
CSOF
6
CSOF
5
CSOF
4
CSOF
3
CSOF
2
CSOF
1
CSOF
0
w
w
w
w
w
w
w
w
w
w
w
w
w
w
Res.
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DMA request multiplexer (DMAMUX)
RM0461
Bits 31:14 Reserved, must be kept at reset value.
Bits 13:0 CSOF[13:0]: Clear synchronization overrun event flag
Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR
register.
12.6.4
DMAMUX request generator channel x configuration register
(DMAMUX_RGxCR)
Address offset: 0x100 + 0x04 * x (x = 0 to 3)
Reset value: 0x0000 0000
This register must be written by an unprivileged or privileged write, according to the
privileged mode of the considered DMAMUX request line multiplexer channel y it is
assigned to, and considering that the DMAMUX request generator x channel output is
selected by the y channel of the DMAMUX request line channel (refer to
DMAMUX_CyCR.DMAREQ_ID[7:0] and to the DMAMXUX mapping implementation
section).
31
30
29
28
27
26
25
24
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
23
22
21
20
19
17
16
GPOL[1:0]
GE
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
rw
rw
rw
rw
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
OIE
Res.
Res.
Res.
rw
rw
rw
rw
GNBREQ[4:0]
rw
18
SIG_ID[4:0]
rw
Bits 31:24 Reserved, must be kept at reset value.
Bits 23:19 GNBREQ[4:0]: Number of DMA requests to be generated (minus 1)
Defines the number of DMA requests to be generated after a trigger event. The actual
number of generated DMA requests is GNBREQ +1.
Note: This field must be written only when GE bit is disabled.
Bits 18:17 GPOL[1:0]: DMA request generator trigger polarity
Defines the edge polarity of the selected trigger input
00: No event, i.e. no trigger detection nor generation.
01: Rising edge
10: Falling edge
11: Rising and falling edges
Bit 16 GE: DMA request generator channel x enable
0: DMA request generator channel x disabled
1: DMA request generator channel x enabled
Bits 15:9 Reserved, must be kept at reset value.
Bit 8 OIE: Trigger overrun interrupt enable
0: Interrupt on a trigger overrun event occurrence is disabled
1: Interrupt on a trigger overrun event occurrence is enabled
Bits 7:5 Reserved, must be kept at reset value.
Bits 4:0 SIG_ID[4:0]: Signal identification
Selects the DMA request trigger input used for the channel x of the DMA request generator
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DMA request multiplexer (DMAMUX)
12.6.5
DMAMUX request generator interrupt status register
(DMAMUX_RGSR)
Address offset: 0x140
Reset value: 0x0000 0000
This register must be accessed at bit level by an unprivileged or privileged read, according
to the privileged mode of the considered DMAMUX request line multiplexer channel x,
depending on the privileged control bit of the connected DMA controller channel y, and
considering that the DMAMUX x channel output is connected to the y channel of the DMA
(refer to the DMAMXUX mapping implementation section).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
OF3
OF2
OF1
OF0
r
r
r
r
Bits 31:4 Reserved, must be kept at reset value.
Bits 3:0 OF[3:0]: Trigger overrun event flag
The flag is set when a new trigger event occurs on DMA request generator channel x, before
the request counter underrun (the internal request counter programmed via the GNBREQ
field of the DMAMUX_RGxCR register).
The flag is cleared by writing 1 to the corresponding COFx bit in the DMAMUX_RGCFR
register.
12.6.6
DMAMUX request generator interrupt clear flag register
(DMAMUX_RGCFR)
Address offset: 0x144
Reset value: 0x0000 0000
This register must be written at bit level by an unprivileged or privileged write, according to
the privileged mode of the considered DMAMUX request line multiplexer channel y it is
assigned to, and considering that the DMAMUX request generator x channel output is
selected by the y channel of the DMAMUX request line channel (refer to
DMAMUX_CyCR.DMAREQ_ID[7:0] and to the DMAMXUX mapping implementation
section).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
COF3
COF2
COF1
COF0
w
w
w
w
RM0461 Rev 10
389/1290
392
DMA request multiplexer (DMAMUX)
RM0461
Bits 31:4 Reserved, must be kept at reset value.
Bits 3:0 COF[3:0]: Clear trigger overrun event flag
Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RGSR
register.
390/1290
RM0461 Rev 10
RM0461
12.6.7
DMA request multiplexer (DMAMUX)
DMAMUX register map
The following table summarizes the DMAMUX registers and reset values. Refer to the
register boundary address table for the DMAMUX register base address.
Res.
SOIE
SOIE
Res.
Res.
SOIE
SOIE
Res.
Res.
SOIE
SOIE
Res.
Res.
SOIE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DMAREQ_ID[6:0]
0
Res.
SOIE
0
0
0
0
0
0
0
DMAREQ_ID[6:0]
0
Res.
SOIE
0
0
0
0
0
0
DMAREQ_ID[6:0]
0
0
0
0
0
0
0
DMAREQ_ID[6:0]
0
0
0
0
0
0
0
DMAREQ_ID[6:0]
0
0
0
0
0
0
0
DMAREQ_ID[6:0]
0
0
0
0
0
0
0
DMAREQ_ID[6:0]
0
0
0
0
0
0
0
DMAREQ_ID[6:0]
SOF0 Res.
0
SOF1 Res.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CSOF0
0
SOF2 Res.
0
CSOF1
0
SOF3 Res.
0
CSOF2
0
SOF4 Res.
0
0
DMAREQ_ID[6:0]
Res.
SOIE
0
0
Res.
SOIE
0
0
DMAREQ_ID[6:0]
Res.
SOIE
0
0
Res.
SOIE
0
0
DMAREQ_ID[6:0]
Res.
0
SOIE
Res.
Res.
Res.
Res.
EGE
EGE
EGE
EGE
EGE
EGE
EGE
EGE
EGE
EGE
EGE
EGE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
0
CSOF3
Res.
Res.
Res.
0
0
SOF5 Res.
Res.
Res.
0
0
CSOF4
Res.
Res.
Res.
Res.
0
DMAREQ_ID[6:0]
CSOF5
Res.
Res.
Res.
0
0
SOF6 Res.
Res.
Res.
Res.
0
0
CSOF6
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
RM0461 Rev 10
Res.
Res.
Res.
Res.
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DMAMUX_CCFR
Res.
0x084
Res.
Reset value
Res.
Res.
Res.
DMAMUX_CSR
Res.
Res.
Reserved
Res.
Res.
SE
Res.
Res.
SE
SE
Res.
Res.
SE
SE
Res.
Res.
SE
0
0
Res.
SPOL
[1:0]
SPOL
[1:0]
SPOL
[1:0]
SPOL
[1:0]
SPOL
[1:0]
0
Res.
0
Res.
0
Res.
0
Res.
0
0
0
Res.
0
0
0
0
SOF7 Res.
0
0
0
SOF8 Res.
0
Res.
0
0
Res.
0
0
NBREQ[4:0]
0
0
0
0
CSOF7
0
0
Res.
0
0
Res.
0
0
NBREQ[4:0]
SYNC_ID[4:0]
0
0
0
0
CSOF8
0
0
0
EGE
0
0
0
Res.
NBREQ[4:0]
0
0
EGE
0
0
0
0
SOF9 Res.
0
0
0
0
CSOF9
0
0
Res.
0
0
Res.
0
0
0
Res.
NBREQ[4:0]
0
0
0
SOF10 Res.
0
0
0
0
CSOF10
0
0
Res.
0
0
Res.
0
0
0
0
Res.
0
0
0
0
SOF11 Res.
0
0
0
0
CSOF11
0
0
Res.
0
0
Res.
0
0
NBREQ[4:0]
Res.
0
0
0
Res.
NBREQ[4:0]
0
Res.
0
0
0
0
DMAREQ_ID[6:0]
SOF12 Res.
0
0
0
0
CSOF12
0
0
Res.
0
0
Res.
0
0
0
Res.
NBREQ[4:0]
0
Res.
0
0
Res.
0
0
Res.
0
0
Res.
0
0
SE
0
0
0
Res.
NBREQ[4:0]
0
Res.
0
0
SE
0
0
SE
0
0
Res.
0
0
0
0
SE
0
0
Res.
0
0
SE
0
0
Res.
0
0
SE
0
0
NBREQ[4:0]
0
0
SPOL
[1:0]
0
0
SPOL
[1:0]
0
0
Res.
0x080
0
0
Res.
Reset value
0x038 0x07C
0
0
0
0
0
SOF13 Res.
Res.
Res.
0x034
0
SYNC_ID[4:0]
0
Res.
Reset value
DMAMUX_C13CR
0
0
0
0
DMAREQ_ID[6:0]
CSOF13
Res.
DMAMUX_C12CR
Res.
0x030
0
0
NBREQ[4:0]
SYNC_ID[4:0]
0
Res.
Reset value
0
0
0
0
Res.
Res.
DMAMUX_C11CR
Res.
0x02C
0
SYNC_ID[4:0]
0
Res.
Reset value
0
0
0
SE
Res.
DMAMUX_C10CR
Res.
0x028
0
0
NBREQ[4:0]
SYNC_ID[4:0]
0
Res.
Reset value
0
0
Res.
Res.
Res.
0x024
0
SYNC_ID[4:0]
0
Res.
Reset value
DMAMUX_C9CR
0
0
0
0
SE
Res.
DMAMUX_C8CR
Res.
0x020
0
SYNC_ID[4:0]
0
Res.
Reset value
0
0
0
Res.
Res.
DMAMUX_C7CR
Res.
0x01C
0
0
NBREQ[4:0]
SYNC_ID[4:0]
0
Res.
Reset value
0
0
SPOL
[1:0]
Res.
DMAMUX_C6CR
Res.
0x018
0
SYNC_ID[4:0]
0
Res.
Reset value
0
0
SPOL
[1:0]
Res.
Res.
0x014
0
SYNC_ID[4:0]
0
Res.
Reset value
DMAMUX_C5CR
0
0
SPOL
[1:0]
Res.
DMAMUX_C4CR
Res.
0x010
0
0
NBREQ[4:0]
SYNC_ID[4:0]
0
Res.
Reset value
0
SPOL
[1:0]
Res.
DMAMUX_C3CR
Res.
0x00C
0
SYNC_ID[4:0]
0
Res.
Reset value
0
SPOL
[1:0]
Res.
DMAMUX_C2CR
Res.
0x008
0
SYNC_ID[4:0]
0
Res.
Reset value
0
NBREQ[4:0]
SPOL
[1:0]
Res.
Res.
0x004
0
Res.
Reset value
DMAMUX_C1CR
SYNC_ID[4:0]
SPOL
[1:0]
Res.
DMAMUX_C0CR
Res.
0x000
Register
Res.
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 77. DMAMUX register map and reset values
0
0
0
0
0
0
0
0
0
0
0
0
0
0
391/1290
392
0x148 0x3FC
392/1290
Reserved
RM0461 Rev 10
Refer to Section 2.4 on page 62 for the register boundary addresses.
COF1
COF0
0
0
0
0
Res.
Reset value
Res.
0
0
0
OF0 Res.
0
OF1 Res.
0
OF2 Res.
Reset value
COF2
0
Res.
0
OF3 Res.
0
COF3
Res.
Res.
Res.
OIE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
OIE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
0
0
0
0
0
0
Res.
Res.
Res.
Res.
Res.
Res. Res.
Res. Res.
Res. Res.
OIE Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
GE
Res.
0
Res.
Res.
Res.
Res.
OIE
Res.
Res.
Res.
Res.
Res.
Res.
0
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res.
GE
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
GE
Res.
Res. Res.
GPOL Res.
[1:0] Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
GE
0
Res.
0
Res. Res.
0
Res. Res.
0
Res.
Reserved
0
Res.
0
Res. Res.
0
Res.
0
0
Res.
GPOL
[1:0]
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x088 0x0FC
0
0
Res.
GPOL
[1:0]
0
0
Res.
GPOL
[1:0]
0
Res. Res.
0
0
0
Res.
Register
GNBREQ[4:0]
Res.
0
Res. Res.
0
0
Res.
0
0
0
Res.
0
Res. Res.
0
0
Res.
GNBREQ[4:0]
0
0
Res.
0
Res. Res.
GNBREQ[4:0]
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
GNBREQ[4:0]
Res. Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res.
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
Res.
Res.
Res.
Res.
DMAMUX_RGCFR
Res.
0x144
DMAMUX_RGSR
Res.
0x140
Reserved
Res.
0x110 0x13C
DMAMUX_RG3CR
Res. Res.
0x10C
DMAMUX_RG2CR
Res. Res.
0x108
DMAMUX_RG1CR
Res.
0x104
Res.
Offset
DMAMUX_RG0CR
Res.
0x100
Res.
DMA request multiplexer (DMAMUX)
RM0461
Table 77. DMAMUX register map and reset values (continued)
SIG_ID[4:0]
0
0
SIG_ID[4:0]
0
0
SIG_ID[4:0]
0
0
SIG_ID[4:0]
0
0
0
0
RM0461
Nested vectored interrupt controller (NVIC)
13
Nested vectored interrupt controller (NVIC)
13.1
NVIC main features
•
62 maskable interrupt channels (not including the sixteen Cortex-M4 with DSP interrupt
lines)
•
16 programmable priority levels (four bits of interrupt priority used)
•
Low-latency exception interrupt handling
•
Power management control
•
Implementation of system control registers
The NVIC and the processor core interfaces are closely coupled, resulting in low-latency
interrupt processing and efficient processing of late arriving interrupts.
All interrupts including the core exceptions are managed by the NVIC.
For more information on exceptions and NVIC programming, refer to the PM0214
programming manual for Cortex®-M4 (PM0214).
13.2
Interrupt and exception vectors
The vector table is given in Table 78 (shaded cells indicate the processor exceptions).
Position
Priority
Table 78. Vector table
Type of
priority
-
-
-
-
-
-3
Fixed
-
-2
-
Acronym
Description(1)
Address
Reserved
0x0000 0000
Reset
Reset
0x0000 0004
Fixed
NMI
Non maskable interrupt HSE32 CSS, flash ECC and
SRAM2 parity
0x0000 0008
-1
Fixed
HardFault
All classes of fault
0x0000 000C
-
0
Settable
MemManager
Memory manager
0x0000 0010
-
1
Settable
BusFault
Prefetch fault, memory access fault
0x0000 0014
-
2
Settable
UsageFault
Undefined instruction or illegal state
0x0000 0018
-
-
-
-
Reserved
0x0000 001C
0x0000 0028
-
3
Settable
SVCall
System service call via SWI instruction
0x0000 002C
-
4
Settable
Debug
Debug monitor
0x0000 0030
-
-
-
-
Reserved
0x0000 0034
-
5
Settable
PendSV
Pendable request for system service
0x0000 0038
-
6
Settable
SysTick
SysTick timer
0x0000 003C
0
7
Settable
WWDG
Window watchdog early wake-up
0x0000 0040
RM0461 Rev 10
393/1290
395
Nested vectored interrupt controller (NVIC)
RM0461
Position
Priority
Table 78. Vector table (continued)
Type of
priority
1
8
Settable
Acronym
PVD,
PVM[3]
Description(1)
Address
PVD through EXTI[16]
PVM[3] through EXTI[34]
0x0000 0044
Settable
TAMP,
RTC_STAMP,
LSE_CSS,
RTC_SSRU
TAMP tamper
RTC timestamp
LSECSS interrupt
RTC SSR underflow interrupt
0x0000 0048
3 10 Settable
RTC_WKUP
RTC wake-up interrupt
0x0000 004C
4 11 Settable
FLASH
Flash memory global interrupt and flash memory ECC
single error interrupt
0x0000 0050
5 12 Settable
RCC
RCC global interrupt
0x0000 0054
6 13 Settable
EXTI0
EXTI line 0 interrupt through EXTI[0]
0x0000 0058
7 14 Settable
EXTI1
EXTI line 1 interrupt through EXTI[1]
0x0000 005C
8 15 Settable
EXTI2
EXTI line 2 interrupt through EXTI[2]
0x0000 0060
9 16 Settable
EXTI3
EXTI line 3 interrupt through EXTI[3]
0x0000 0064
10 17 Settable
EXTI4
EXTI line 4 interrupt through EXTI[4]
0x0000 0068
11 18 Settable
DMA1_CH1
DMA1 channel 1 non-secure interrupt
0x0000 006C
12 19 Settable
DMA1_CH2
DMA1 channel 2 non-secure interrupt
0x0000 0070
13 20 Settable
DMA1_CH3
DMA1 channel 3 non-secure interrupt
0x0000 0074
14 21 Settable
DMA1_CH4
DMA1 channel 4 non-secure interrupt
0x0000 0078
15 22 Settable
DMA1_CH5
DMA1 channel 5 non-secure interrupt
0x0000 007C
16 23 Settable
DMA1_CH6
DMA1 channel 6 non-secure interrupt
0x0000 0080
17 24 Settable
DMA1_CH7
DMA1 channel 7 non-secure interrupt
0x0000 0084
18 25 Settable
ADC
ADC global interrupt
0x0000 0088
19 26 Settable
DAC
DAC global interrupt
0x0000 008C
20 27 Settable
Reserved
Reserved
0x0000 0090
21 28 Settable
COMP
COMP2 and COMP1 interrupt through EXTI[22:21]
0x0000 0094
22 29 Settable
EXTI[9:5]
EXTI line [9:5] interrupt through EXTI[9:5]
0x0000 0098
23 30 Settable
TIM1_BRK
Timer 1 break interrupt
0x0000 009C
24 31 Settable
TIM1_UP
Timer 1 Update
0x0000 00A0
25 32 Settable
TIM1_TRG_COM
Timer 1 trigger and communication
0x0000 00A4
26 33 Settable
TIM1_CC
Timer 1 capture compare interrupt
0x0000 00A8
27 34 Settable
TIM2
Timer 2 global interrupt
0x0000 00AC
28 35 Settable
TIM16
Timer 16 global interrupt
0x0000 00B0
29 36 Settable
TIM17
Timer 17 global interrupt
0x0000 00B4
30 37 Settable
I2C1_EV
I2C1 event interrupt
0x0000 00B8
2
9
394/1290
RM0461 Rev 10
RM0461
Nested vectored interrupt controller (NVIC)
Priority
Position
Table 78. Vector table (continued)
Type of
priority
Acronym
31 38 Settable
I2C1_ER
I2C1 error interrupt
0x0000 00BC
32 39 Settable
I2C2_EV
I2C2 event interrupt
0x0000 00C0
33 40 Settable
I2C2_ER
I2C2 error interrupt
0x0000 00C4
34 41 Settable
SPI1
SPI1 global interrupt
0x0000 00C8
35 42 Settable
SPI2S2
SPI2S2 global interrupt
0x0000 00CC
36 43 Settable
USART1
USART1 global interrupt
0x0000 00D0
37 44 Settable
USART2
USART2 global interrupt
0x0000 00D4
38 45 Settable
LPUART1
LPUART1 global interrupt
0x0000 00D8
39 46 Settable
LPTIM1
LP timer 1 global interrupt
0x0000 00DC
40 47 Settable
LPTIM2
LP timer 2 global interrupt
0x0000 00E0
41 48 Settable
EXTI[15:10]
EXTI line [15:10] interrupt through EXTI[15:10]
0x0000 00E4
42 49 Settable
RTC_ALARM
RTC alarms A and B interrupt
0x0000 00E8
43 50 Settable
LPTIM3
LP timer 3 global interrupt
0x0000 00EC
44 51 Settable
Reserved
Reserved
0x0000 00F0
45 52 Settable
Reserved
Reserved
0x0000 00F4
46 53 Settable
Reserved
Reserved
0x0000 00F8
47 54 Settable
HSEM
Semaphore interrupt 0 to CPU
0x0000 00FC
48 55 Settable
I2C3_EV
I2C3 event interrupt
0x0000 0100
49 56 Settable
I2C3_ER
I2C3 error interrupt
0x0000 0104
50 57 Settable
Radio IRQ,
Busy
Radio IRQs
RFBUSY interrupt through EXTI[45]
0x0000 0108
51 58 Settable
AES
AES global interrupt
0x0000 010C
52 59 Settable
True RNG
True random number generator interrupt
0x0000 0110
53 60 Settable
PKA
Private key accelerator interrupt
0x0000 0114
54 61 Settable
DMA2_CH1
DMA2 channel 1 non-secure interrupt
0x0000 0118
55 62 Settable
DMA2_CH2
DMA2 channel 2 non-secure interrupt
0x0000 011C
56 63 Settable
DMA2_CH3
DMA2 channel 3 non-secure interrupt
0x0000 0120
57 64 Settable
DMA2_CH4
DMA2 channel 4 non-secure interrupt
0x0000 0124
58 65 Settable
DMA2_CH5
DMA2 channel 5 non-secure interrupt
0x0000 0128
59 66 Settable
DMA2_CH6
DMA2 channel 6 non-secure interrupt
0x0000 012C
60 67 Settable
DMA2_CH7
DMA2 channel 7 non-secure interrupt
0x0000 0130
61 68 Settable
DMAMUX1_OVR
DMAMUX1 overrun interrupt
0x0000 0134
Description(1)
Address
1. EXTI[n] refer to the input event number [n] of the EXTI.
RM0461 Rev 10
395/1290
395
Extended interrupts and event controller (EXTI)
14
RM0461
Extended interrupts and event controller (EXTI)
The extended interrupts and event controller (EXTI) manages the individual CPU and
system wake-up through configurable and direct event inputs. It provides wake-up requests
to the power control and generates an interrupt request to the CPU NVIC and events to the
CPU event input.
For the CPU, an additional event Generation block (EVG) is needed to generate the CPU
event signal.
The EXTI wake-up requests allow the system to be woken up from Stop modes and the
CPU to be woken up from the CStop and CStandby modes.
The interrupt request and event request generation can also be used in Run modes.
14.1
EXTI main features
The EXTI main features are the following:
•
47 input events are supported.
•
All event inputs allow the system to be waked up.
•
Events which do not have an associated wake-up flag in the peripheral, have a flag in
the EXTI and generate an interrupt to the CPU from the EXTI.
The asynchronous event inputs are classified in the following two groups:
•
Configurable events (signals from I/Os or peripherals able to generate a pulse), with
features listed below:
–
•
14.2
Selectable active trigger edge
–
Interrupt pending status register bit
–
Individual interrupt and event generation mask, used for conditioning the CPU
wake-up, interrupt and event generation
–
SW trigger possibility
Direct events (interrupt and wake-up sources from peripherals, having an associated
flag to be cleared in the peripheral), with features listed below:
–
Fixed rising edge active trigger
–
No interrupt pending status register bit in the EXTI (The interrupt pending status
flag is provided by the peripheral generating the event.)
–
Individual interrupt and event generation mask, used for conditioning the CPU
wake-up and event generation
–
No software trigger possibility
EXTI block diagram
The EXTI consists of a register block accessed via an AHB interface, the event input trigger
block and the masking block as shown in Figure 40.
The register block contains all the EXTI registers.
The event input trigger block provides event input edge trigger logic.
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The masking block provides the event input distribution to the different wake-up, interrupt
and event outputs, and the masking of these.
Figure 40. EXTI block diagram
AHB interface
Registers
hclk
sys_wakeup
PWR
c_wakeup
it_exti_per(y)(1)
Masking
Peripheral
Wakeup
Direct event(x) or
configurable event(y)
Interrupt
c_evt_exti
Event Events
trigger
Pulse
c_event
c_evt_rst
EVG
Direct event(x)
c_fclk
rxev
nvic(x)
CPU
nvic(y)
EXTI
1) it_exti_per(y) only available for configurable events (y)
MSv60759V1
Table 79. EXTI pin overview
Pin name
I/O
Description
AHB interface
I/O
EXTI register bus interface
hclk
I
AHB bus clock and EXTI system clock
Configurable
event(y)
I
Asynchronous wake-up events from peripherals which do not have an associated interrupt
and flag in the peripheral
Direct event(x)
I
Synchronous and asynchronous wake-up events from peripherals which have an
associated interrupt and flag in the peripheral
it_exti_per (y)
O
Interrupts to the CPU associated with the configurable event (y)
c_evt_exti
O
High-level sensitive event output for the CPU, synchronous to hclk
c_evt_rst
I
Asynchronous reset input to clear c_evt_exti
sys_wakeup
O
Asynchronous system wake-up request to PWR for ck_sys and hclk
c_wakeup
O
Wake-up request to PWR for the CPU, synchronous to hclk
Table 80. EVG pin overview
Pin name
I/O
Description
c_fclk
I
CPU free running clock
c_evt_in
I
High-level sensitive events input from EXTI, asynchronous to the CPU clock
c_event
O
Event pulse, synchronous to the CPU clock
c_evt_rst
O
Event reset signal, synchronous to the CPU clock
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14.3
RM0461
EXTI connections between peripherals and CPU
The peripherals able to generate wake-up or interrupt events when the system is in Stop
mode, are connected to the EXTI.
Peripheral wake-up signals that generate a pulse or that do not have an interrupt status bits
in the peripheral, are connected to an EXTI configurable event input. For these events, the
EXTI provides a status pending bit which requires to be cleared. It is the EXTI interrupt
associated with the status bit that interrupts the CPU.
Peripheral interrupt and wake-up signals that have a status bit in the peripheral which
requires to be cleared in the peripheral, are connected to an EXTI direct event input. There
is no status pending bit within the EXTI. The interrupt or wake-up is cleared by the CPU in
the peripheral. It is the peripheral interrupt that interrupts the CPU directly.
The EXTI configurable event interrupts are connected to the NVIC of the CPU.
The dedicated EXTI/EVG CPU event is connected to the CPU rxev input.
The EXTI CPU wake-up signalis connected to the PWR block and are used to wake up the
system and CPU sub-system bus clocks.
14.3.1
EXTI wake-up interrupt list
The wake-up sources are listed in Table 81: Wake-up interrupts.
Some wake-up sources are able to generate an event to the CPU (see ‘Event’ column).
For CPU interrupt handling, see Section 13: Nested vectored interrupt controller (NVIC).
Table 81. Wake-up interrupts
EXTI
no
Acronym
Description
EXTI type
Event
Wake-up
0
EXTI[0]
EXTI line 0 from SYSCFG
Configurable
Yes
CPU
1
EXTI[1]
EXTI line 1 from SYSCFG
Configurable
Yes
CPU
2
EXTI[2]
EXTI line 2 from SYSCFG
Configurable
Yes
CPU
3
EXTI[3]
EXTI line 3 from SYSCFG
Configurable
Yes
CPU
4
EXTI[4]
EXTI line 4 from SYSCFG
Configurable
Yes
CPU
5
EXTI[5]
EXTI line 5 from SYSCFG
Configurable
Yes
CPU
6
EXTI[6]
EXTI line 6 from SYSCFG
Configurable
Yes
CPU
7
EXTI[7]
EXTI line 7 from SYSCFG
Configurable
Yes
CPU
8
EXTI[8]
EXTI line 8 from SYSCFG
Configurable
Yes
CPU
9
EXTI[8]
EXTI line 9 from SYSCFG
Configurable
Yes
CPU
10
EXTI[10]
EXTI line 10 from SYSCFG
Configurable
Yes
CPU
11
EXTI[11]
EXTI line 11 from SYSCFG
Configurable
Yes
CPU
12
EXTI[12]
EXTI line 12 from SYSCFG
Configurable
Yes
CPU
13
EXTI[13]
EXTI line 13 from SYSCFG
Configurable
Yes
CPU
14
EXTI[14]
EXTI line 14 from SYSCFG
Configurable
Yes
CPU
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Table 81. Wake-up interrupts (continued)
EXTI
no
Acronym
Description
EXTI type
Event
Wake-up
15
EXTI[15]
EXTI line 15 from SYSCFG
Configurable
Yes
CPU
16
PVD
PVD line
Configurable
No
CPU
17
RTC_ALARM
RTC alarms A and B interrupt
Direct
Yes
CPU
18
SSRU
RTC SSR underflow interrupt
Direct
Yes
CPU
19
TAMP,
RTC_STAMP,
LSE_CSS
TAMP tamper interrupt
RTC timestamp interrupt
RCC LSECSS interrupt
Direct
Yes
CPU
20
RTC_WKUP
RTC wake-up interrupt
Direct
Yes
CPU
21
COMP1
COMP1 line
Configurable
Yes
CPU
22
COMP2
COMP2 line
Configurable
Yes
CPU
23
I2C1 wake-up
I2C1 wake-up
Direct
No
CPU
24
I2C2 wake-up
I2C2 wake-up
Direct
No
CPU
25
I2C3 wake-up
I2C3 wake-up
Direct
No
CPU
26
USART1
USART1 wake-up
Direct
No
CPU
27
USART2
USART2 wake-up
Direct
No
CPU
28
LPUART1
LPUART1 wake-up
Direct
No
CPU
29
LPTIM1 wake-up
LPtimer 1 wake-up
Direct
No
CPU
30
LPTIM2 wake-up
LPtimer 2 wake-up
Direct
No
CPU
31
LPTIM3 wake-up
LPtimer 3 wake-up
Direct
No
CPU
32
Reserved
-
Direct
No
-
33
Reserved
-
Direct
No
-
34
PVM[3]
PVM[3] line
Configurable
No
CPU
35
Reserved
-
Direct
No
-
36
Reserved
-
Direct
No
-
37
Reserved
-
Direct
No
-
38
HSEM interrupt 0
Semaphore interrupt 0 with CPU
Direct
No
CPU
39
Reserved
-
Direct
No
-
40
Reserved
-
Configurable
No
-
41
Reserved
-
Configurable
No
-
42
Flash
Flash ECC and global interrupts
Direct
No
CPU
43
HSE32 CSS
interrupt
RCC HSE32 CSS interrupt
Direct
No
CPU
44
Radio IRQs
Radio IRQs interrupts
Direct
No
CPU
45
Radio Busy
RFBUSY wake-up
Configurable
No
CPU
46
CDBGPWRUPREQ
Debug power-up request wake-up
Direct
No
CPU
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14.4
RM0461
EXTI functional description
Depending on the EXTI event input type and wake-up targets, different logic
implementations are used. The applicable features are controlled from register bits as
detailed below:
•
Active trigger edge enable
–
by rising edge selection
EXTI rising trigger selection register (EXTI_RTSR1)
EXTI rising trigger selection register (EXTI_RTSR2)
–
by falling edge selection
EXTI falling trigger selection register (EXTI_FTSR1)
EXTI falling trigger selection register (EXTI_FTSR2)
•
Software trigger
EXTI software interrupt event register (EXTI_SWIER1)
EXTI software interrupt event register (EXTI_SWIER2)
•
Interrupt pending flag
EXTI pending register (EXTI_PR1)
EXTI pending register (EXTI_PR2)
•
CPU wake-up and interrupt enable
EXTI interrupt mask register (EXTI_IMR1)
EXTI interrupt mask register (EXTI_IMR2)
•
CPU wake-up and event enable
EXTI event mask register (EXTI_EMR1)
Table 82. EXTI event input configurations and register control
Event input
type
Logic implementation
EXTI_
RTSR
EXTI_
FTSR
EXTI_
SWIER
EXTI_
PR
EXTI_
IMR
EXTI_
EMR(1)
Configurable
Configurable event input wake-up logic
x
x
x
x
x
x
Direct event input wake-up logic
-
-
-
-
x
x
Direct
1. Only for input events with configuration “rxev generation” enabled.
14.4.1
EXTI configurable event input wake-up
The extended interrupt/event block diagram for configurable events is shown in Figure 41.
The configurable events allow the system and CPU wake-up from Sleep and Stop modes,
and provide a pending flag in the EXTI.
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Figure 41. Configurable event trigger logic CPU wake-up
AHB
interface
hclk
Peripheral interface
Falling
trigger
selection
register
Rising Software
trigger interrupt
selection
event
register register
CPU
event
mask
register
CPU
interrupt
mask
register
Pending
request
register
it_exti_per(y)
Asynchronous edge
detection circuit
rst
EVG
ck_fclk_c
Same circuit for configurable
and direct events
Rising
edge
detect
pulse
generator
hclk
CPU event(y)
c_evt_rst
(1)
Rising edge
detect rst
CPU
other events(x,y)
CPU
other wakeups
CPU
wakeup(y)
c_evt_exti
CPU rising
edge detect
pulse
generator
c_event
hclk
Synch
Configurable
event
input(y)
Delay
hclk
Other wakeups
c_wakeup
sys_wakeup
EXTI
1) Only for the input events supporting the CPU rxrev generation c_event.
MSv60761V1
The software interrupt event register allows configurable events to be triggered by software,
writing the corresponding register bit, irrespective of the edge selection setting.
The rising and falling edges selection registers allow the configurable event active trigger
edge (or both edges) to be enabled.
The CPU has its dedicated interrupt mask and event mask registers. The enabled event
allows the generation of an event on the CPU. All events for a CPU are ORed together into
a single CPU event signal. The event pending register (EXTI_PR) is not set for an
unmasked CPU event.
The configurable events have unique interrupt pending request registers, shared by the
CPU. The pending register is only set for an unmasked interrupt. Each configurable event
provides a common interrupt to the CPU. The configurable event interrupts need to be
acknowledged by software in the EXTI_PR register.
When a CPU interrupt or CPU event is enabled, the asynchronous edge detection circuit is
reset by the clocked delay and rising edge detect pulse generator. This guarantees that the
EXTI hclk clock is woken up before the asynchronous edge detection circuit is reset.
Note:
A detected configurable event interrupt pending request may be cleared by the CPU. The
system is not able to enter into low-power modes as long as an interrupt pending request is
active.
14.4.2
EXTI direct event input wake-up
The extended interrupt/event block diagram for direct events is shown in Figure 42. The
direct events allow the wake-up of the system and of the CPU from Sleep and Stop modes.
The direct events do not have an associated EXTI interrupt. The EXTI only wakes up the
system and CPU sub-system clocks and may generate a CPU wake-up event. The
peripheral synchronous interrupt associated with the direct wake-up event, wake up the
CPU. The EXTI direct event is able to generate a CPU event. This CPU event wakes up the
CPU.
The CPU event may occur before the associated peripheral interrupt flag is set.
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RM0461
Figure 42. Direct event trigger logic CPU wake-up
AHB
interface
Peripheral interface
hclk
CPU
interrupt
mask register
hclk
CPU
event
mask register
Same circuit for configurable
and direct events
EVG
ck_fclk_c
hclk
Delay
CPU event(x)(1)
Rising edge
detect
CPU
other events(x,y)
Asynchronous
rising edge
detect circuit
rst
c_wakeup
CPU other wakeups
Other wakeups
sys_wakeup
Wakeup(x)
hclk
1) Only for the input events supporting the CPU rxrev generation c_event.
14.5
c_event
hclk
CPU wakeup(x)
Falling edge
detect pulse
generator
EXTI
rst
CPU
rising edge
detect pulse
generator
c_evt_exti
Synch
Direct event
input(x)
c_evt_rst
MSv60763V1
EXTI functional behavior
The direct event inputs are enabled in the respective peripheral generating the wake-up
event. The configurable events are enabled by enabling at least one of the trigger edges.
Once an event input is enabled, the generation of a CPU wake-up is conditioned by the
CPU interrupt mask and the CPU event mask.
Table 83. Masking functionality
CPU interrupt enable
EXTI_IMRm.IMb
0
1
CPU event enable
EXTI_EMRm.EMb
Configurable
event inputs
EXTI_PRm.PIFb
it_exti_per(y)
CPU event
CPU wakeup
0
No
Masked
Masked
Masked
1
No
Masked
Yes
Yes
0
Status latched
Yes
Masked
Yes(1)
1
Status latched
Yes
Yes
Yes
1. Only if the CPU interrupt is enabled in EXTI_IMRm.IMb.
For configurable event inputs, when the enabled edges occur on the event input, an event
request is generated. When the associated it_exti_per(y) interrupt is unmasked, the
corresponding pending bit in EXTI_PR is set, the CPU sub-system wakes up and the CPU
interrupt signal is activated. The EXTI_PR pending bit must be set to 1 by software. This
clears the it_exti_per(y) interrupt.
For direct event inputs, when enabled in the associated peripheral, an event request is
generated on the rising edge only. There is no corresponding CPU pending bit in the EXTI.
When the associated direct event is unmasked in EXTI_IM, the CPU sub-system wakes up.
The CPU is woken up (interrupted) by the peripheral synchronous interrupt.
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The CPU event must be unmasked in EXTI_EMR to generate an event. When the enabled
edges occur on the event input, a CPU event pulse is generated. There is no event pending
bit.
For the configurable event inputs, an event request can be generated by software, setting to
1 the corresponding bit in the interrupt/event register EXTI_SWIER. This allows the
generation of a rising edge on the event. The edge event pending bit must be set in
EXTI_PR, irrespective of the setting in EXTI_RTSR.
14.6
EXTI registers
The EXTI register map is divided in sections listed in the table below.
Table 84. EXTI register map sections
Address
Description
0x000 - 0x01C
General configurable event [31:0] configuration
0x020 - 0x03C
General configurable event [63:32] configuration
0x080 - 0x0BC
CPU input event configuration
All these registers can be accessed with word (32-bit), half-word (16-bit) and byte (8-bit)
access.
14.6.1
EXTI rising trigger selection register (EXTI_RTSR1)
Address offset: 0x000
Reset value: 0x0000 0000
Contains only register bits for configurable events.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
RT22
RT21
Res.
Res.
Res.
Res.
RT16
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RT15
RT14
RT13
RT12
RT11
RT10
RT9
RT8
RT7
RT6
RT5
RT4
RT3
RT2
RT1
RT0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:23 Reserved, must be kept at reset value.
Bit 22 RT22: rising trigger event configuration bit of configurable event input 22
0: Rising trigger disabled (for event and interrupt) for input line
1: Rising trigger enabled (for event and interrupt) for input line
Note: The configurable event inputs are edge triggered. No glitch must be generated on
these inputs. If a rising edge on the configurable event input occurs while writing to the
register, the associated pending bit is not set.
Rising and falling edge triggers can be set for the same configurable event input. In this
case, both edges generate a trigger.
Bit 21 RT21: rising trigger event configuration bit of configurable event input 21
Bits 20:17 Reserved, must be kept at reset value.
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RM0461
Bit 16 RT16: rising trigger event configuration bit of configurable event input 16
Bit 15 RT15: rising trigger event configuration bit of configurable event input 15
Bit 14 RT14: rising trigger event configuration bit of configurable event input 14
Bit 13 RT13: rising trigger event configuration bit of configurable event input 13
Bit 12 RT12: rising trigger event configuration bit of configurable event input 12
Bit 11 RT11: rising trigger event configuration bit of configurable event input 11
Bit 10 RT10: rising trigger event configuration bit of configurable event input 10
Bit 9 RT9: rising trigger event configuration bit of configurable event input 9
Bit 8 RT8: rising trigger event configuration bit of configurable event input 8
Bit 7 RT7: rising trigger event configuration bit of configurable event input 7
Bit 6 RT6: rising trigger event configuration bit of configurable event input 6
Bit 5 RT5: rising trigger event configuration bit of configurable event input 5
Bit 4 RT4: rising trigger event configuration bit of configurable event input 4
Bit 3 RT3: rising trigger event configuration bit of configurable event input 3
Bit 2 RT2: rising trigger event configuration bit of configurable event input 2
Bit 1 RT1: rising trigger event configuration bit of configurable event input 1
Bit 0 RT0: rising trigger event configuration bit of configurable event input 0
14.6.2
EXTI falling trigger selection register (EXTI_FTSR1)
Address offset: 0x004
Reset value: 0x0000 0000
Contains only register bits for configurable events.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
FT22
FT21
Res.
Res.
Res.
Res.
FT16
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FT15
FT14
FT13
FT12
FT11
FT10
FT9
FT8
FT7
FT6
FT5
FT4
FT3
FT2
FT1
FT0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:23 Reserved, must be kept at reset value.
Bit 22 FT22: falling trigger event configuration bit of configurable event input 22
0: falling trigger disabled (for event and interrupt) for input line
1: falling trigger enabled (for event and interrupt) for input line
Note: The configurable event inputs are edge triggered. No glitch must be generated on
these inputs. If a falling edge on the configurable event input occurs while writing to the
register, the associated pending bit is not set.
Rising and falling edge triggers can be set for the same configurable event input. In this
case, both edges generate a trigger.
Bit 21 FT21: falling trigger event configuration bit of configurable event input 21
Bits 20:17 Reserved, must be kept at reset value.
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Bit 16 FT16: falling trigger event configuration bit of configurable event input 16
Bit 15 FT15: falling trigger event configuration bit of configurable event input 15
Bit 14 FT14: falling trigger event configuration bit of configurable event input 14
Bit 13 FT13: falling trigger event configuration bit of configurable event input 13
Bit 12 FT12: falling trigger event configuration bit of configurable event input 12
Bit 11 FT11: falling trigger event configuration bit of configurable event input 11
Bit 10 FT10: falling trigger event configuration bit of configurable event input 10
Bit 9 FT9: falling trigger event configuration bit of configurable event input 9
Bit 8 FT8: falling trigger event configuration bit of configurable event input 8
Bit 7 FT7: falling trigger event configuration bit of configurable event input 7
Bit 6 FT6: falling trigger event configuration bit of configurable event input 6
Bit 5 FT5: falling trigger event configuration bit of configurable event input 5
Bit 4 FT4: falling trigger event configuration bit of configurable event input 4
Bit 3 FT3: falling trigger event configuration bit of configurable event input 3
Bit 2 FT2: falling trigger event configuration bit of configurable event input 2
Bit 1 FT1: falling trigger event configuration bit of configurable event input 1
Bit 0 FT0: falling trigger event configuration bit of configurable event input 0
14.6.3
EXTI software interrupt event register (EXTI_SWIER1)
Address offset: 0x008
Reset value: 0x0000 0000
Contains only register bits for configurable events.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
SWI22
SWI21
Res.
Res.
Res.
Res.
SWI16
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SWI15
SWI14
SWI13
SWI12
SWI11
SWI10
SWI9
SWI8
SWI7
SWI6
SWI5
SWI4
SWI3
SWI2
SWI1
SWI0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:23 Reserved, must be kept at reset value.
Bit 22 SWI22: Software interrupt on line 22
A software interrupt is generated independently from the setting in EXTI_RTSR and
EXTI_FTSR. This bit always returns 0 when read.
0: Writing 0 has no effect.
1: Writing 1 to this bit triggers an event on line 22.
This bit is automatically cleared by hardware.
Bit 21 SWI21: Software interrupt on line 21
Bits 20:17 Reserved, must be kept at reset value.
Bit 16 SWI16: Software interrupt on line 16
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RM0461
Bit 15 SWI15: Software interrupt on line 15
Bit 14 SWI14: Software interrupt on line 14
Bit 13 SWI13: Software interrupt on line 13
Bit 12 SWI12: Software interrupt on line 12
Bit 11 SWI11: Software interrupt on line 11
Bit 10 SWI10: Software interrupt on line 10
Bit 9 SWI9: Software interrupt on line 9
Bit 8 SWI8: Software interrupt on line 8
Bit 7 SWI7: Software interrupt on line 7
Bit 6 SWI6: Software interrupt on line 6
Bit 5 SWI5: Software interrupt on line 5
Bit 4 SWI4: Software interrupt on line 4
Bit 3 SWI3: Software interrupt on line 3
Bit 2 SWI2: Software interrupt on line 2
Bit 1 SWI1: Software interrupt on line 1
Bit 0 SWI0: Software interrupt on line 0
14.6.4
EXTI pending register (EXTI_PR1)
Address offset: 0x00C
Reset value: 0x0000 0000
Contains only register bits for configurable events.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PIF22
PIF21
Res.
Res.
Res.
Res.
PIF16
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PIF15
PIF14
PIF13
PIF12
PIF11
PIF10
PIF9
PIF8
PIF7
PIF6
PIF5
PIF4
PIF3
PIF2
PIF1
PIF0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:23 Reserved, must be kept at reset value.
Bit 22 PIF22: pending bit on event input 22
These bits are set when the selected edge event or an EXTI_SWIER software trigger arrives
on the configurable event line. This bit is cleared by writing 1 to it.
0: No trigger request occurred.
1: Trigger request occurred.
Bit 21 PIF21: pending bit on event input 21
Bits 20:17 Reserved, must be kept at reset value.
Bit 16 PIF16: pending bit on event input 16
Bit 15 PIF15: pending bit on event input 15
Bit 14 PIF14: pending bit on event input 14
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Bit 13 PIF13: pending bit on event input 13
Bit 12 PIF12: pending bit on event input 12
Bit 11 PIF11: pending bit on event input 11
Bit 10 PIF10: pending bit on event input 10
Bit 9 PIF9: pending bit on event input 9
Bit 8 PIF8: pending bit on event input 8
Bit 7 PIF7: pending bit on event input 7
Bit 6 PIF6: pending bit on event input 6
Bit 5 PIF5: pending bit on event input 5
Bit 4 PIF4: pending bit on event input 4
Bit 3 PIF3: pending bit on event input 3
Bit 2 PIF2: pending bit on event input 2
Bit 1 PIF1: pending bit on event input 1
Bit 0 PIF0: pending bit on event input 0
14.6.5
EXTI rising trigger selection register (EXTI_RTSR2)
Address offset: 0x020
Reset value: 0x0000 0000
Contains only register bits for configurable events.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
RT45
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
RT34
Res.
Res.
rw
rw
Bits 31:14 Reserved, must be kept at reset value.
Bit 13 RT45: rising trigger event configuration bit of configurable event input 45
0: Rising trigger disabled (for event and interrupt) for input line
1: Rising trigger enabled (for event and interrupt) for input line
Note: The configurable event inputs are edge triggered. No glitch must be generated on
these inputs. If a rising edge on the configurable event input occurs while writing to the
register, the associated pending bit is not set.
Rising and falling edge triggers can be set for the same configurable event input. In this
case, both edges generate a trigger.
Bits 12:3 Reserved, must be kept at reset value.
Bit 2 RT34: rising trigger event configuration bit of configurable event input 34
Bits 1:0 Reserved, must be kept at reset value.
RM0461 Rev 10
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Extended interrupts and event controller (EXTI)
14.6.6
RM0461
EXTI falling trigger selection register (EXTI_FTSR2)
Address offset: 0x024
Reset value: 0x0000 0000
Contains only register bits for configurable events.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
FT45
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
FT34
Res.
Res.
rw
rw
Bits 31:14 Reserved, must be kept at reset value.
Bit 13 FT45: falling trigger event configuration bit of configurable event input 45
0: Falling trigger disabled (for event and interrupt) for input line
1: Falling trigger enabled (for event and interrupt) for input line
Note: The configurable event inputs are edge triggered. No glitch must be generated on
these inputs. If a falling edge on the configurable event input occurs while writing to the
register, the associated pending bit is not set.
Rising and falling edge triggers can be set for the same configurable event input. In this
case, both edges generate a trigger.
Bits 12:3 Reserved, must be kept at reset value.
Bit 2 FT34: falling trigger event configuration bit of configurable event input 34
Bits 1:0 Reserved, must be kept at reset value.
14.6.7
EXTI software interrupt event register (EXTI_SWIER2)
Address offset: 0x028
Reset value: 0x0000 0000
Contains only register bits for configurable events.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
SWI45
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
SWI34
Res.
Res.
rw
rw
Bits 31:14 Reserved, must be kept at reset value.
Bit 13 SWI45: software interrupt on event 45
A software interrupt is generated independently from the setting in EXTI_RTSR and
EXTI_FTSR. This bit always returns 0 when read.
0: Writing 0 has no effect.
1: Writing 1 to this bit triggers an event on line 45.
This bit is automatically cleared by hardware.
408/1290
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RM0461
Extended interrupts and event controller (EXTI)
Bits 12:3 Reserved, must be kept at reset value.
Bit 2 SWI34: software interrupt on event 34
Bits 1:0 Reserved, must be kept at reset value.
14.6.8
EXTI pending register (EXTI_PR2)
Address offset: 0x02C
Reset value: 0x0000 0000
Contains only register bits for configurable events.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
PIF45
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PIF34
Res.
Res.
rw
rw
Bits 31:14 Reserved, must be kept at reset value.
Bit 13 PIF45: pending bit on event input 45
These bits are set when the selected edge event or an EXTI_SWIER software trigger arrives
on the configurable event line. This bit is cleared by writing 1 to it.
0: No trigger request occurred.
1: Trigger request occurred.
Bits 12:3 Reserved, must be kept at reset value.
Bit 2 PIF34: pending bit on event input 34
Bits 1:0 Reserved, must be kept at reset value.
14.6.9
EXTI interrupt mask register (EXTI_IMR1)
Address offset: 0x080
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
23
22
21
20
19
18
17
16
rw
rw
rw
rw
rw
rw
rw
rw
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
IM[31:16]
IM[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:0 IM[31:0]: Wake-up with interrupt mask on event input x (x= 31 to 0)
For each bit of this field:
0: Wake-up with interrupt request from line x is masked.
1: Wake-up with Interrupt request from line x is unmasked.
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Extended interrupts and event controller (EXTI)
14.6.10
RM0461
EXTI event mask register (EXTI_EMR1)
Address offset: 0x084
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
EM22
EM21
EM20
EM19
EM18
EM17
Res.
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
EM15
EM14
EM13
EM12
EM11
EM10
EM9
EM8
EM7
EM6
EM5
EM4
EM3
EM2
EM1
EM0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:23 Reserved, must be kept at reset value.
Bit 22 EM22: Wake-up with event generation mask on event input 22
0: Event request from line 22 is masked.
1: Event request from line 22 is unmasked.
Bit 21 EM21: Wake-up with event generation mask on event input 21
Bit 20 EM20: Wake-up with event generation mask on event input 20
Bit 19 EM19: Wake-up with event generation mask on event input 19
Bit 18 EM18: Wake-up with event generation mask on event input 18
Bit 17 EM17: Wake-up with event generation mask on event input 17
Bit 16 Reserved, must be kept at reset value.
Bit 15 EM15: Wake-up with event generation mask on event input 15
Bit 14 EM14: Wake-up with event generation mask on event input 14
Bit 13 EM13: Wake-up with event generation mask on event input 13
Bit 12 EM12: Wake-up with event generation mask on event input 12
Bit 11 EM11: Wake-up with event generation mask on event input 11
Bit 10 EM10: Wake-up with event generation mask on event input 10
Bit 9 EM9: Wake-up with event generation mask on event input 19
Bit 8 EM8: Wake-up with event generation mask on event input 8
Bit 7 EM7: Wake-up with event generation mask on event input 7
Bit 6 EM6: Wake-up with event generation mask on event input 6
Bit 5 EM5: Wake-up with event generation mask on event input 5
Bit 4 EM4: Wake-up with event generation mask on event input 4
Bit 3 EM3: Wake-up with event generation mask on event input 3
Bit 2 EM2: Wake-up with event generation mask on event input 2
Bit 1 EM1: Wake-up with event generation mask on event input 1
Bit 0 EM0: Wake-up with event generation mask on event input 0
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RM0461
Extended interrupts and event controller (EXTI)
14.6.11
EXTI interrupt mask register (EXTI_IMR2)
Address offset: 0x090
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
IM46
IM45
IM44
IM43
IM42
Res.
Res.
Res.
IM38
Res.
Res.
Res.
IM34
Res.
Res.
rw
rw
rw
rw
rw
rw
rw
Bits 31:15 Reserved, must be kept at reset value.
Bit 14 IM46: Wake-up with interrupt mask on event input 46
0: Wake-up with interrupt request from line 46 is masked.
1: Wake-up with interrupt request from line 46 is unmasked.
Bit 13 IM45: Wake-up with interrupt mask on event input 45
Bit 12 IM44: Wake-up with interrupt mask on event input 44
Bit 11 IM43: Wake-up with interrupt mask on event input 43
Bit 10 IM42: Wake-up with interrupt mask on event input 42
Bits 9:7 Reserved, must be kept at reset value.
Bit 6 IM38: Wake-up with interrupt mask on event input 38
Bits 5:3 Reserved, must be kept at reset value.
Bit 2 IM34: Wake-up with interrupt mask on event input 34
Bits 1:0 Reserved, must be kept at reset value.
14.6.12
EXTI register map
RT1
RT0
0
0
PIF4
PIF3
PIF2
PIF1
PIF0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Res.
Res.
RT34
Res.
Res.
0
PIF5
0
Res.
0
PIF6
0
Res.
0
PIF7
0
Res.
0
PIF8
0
PIF9
0
Res.
0
Res.
0
PIF10
0
Res.
0
PIF11
0
Res.
0
PIF12
0
Res.
0
PIF13
0
RT45
0
PIF14
SWI0
FT0
RT2
0
SWI1
FT1
RT3
0
SWI2
FT2
RT4
0
SWI3
0
SWI4
0
SWI5
0
SWI6
0
SWI7
0
SWI8
0
SWI9
0
SWI10
0
SWI11
0
SWI12
0
SWI13
0
SWI14
0
SWI15
FT3
RT5
0
FT4
RT6
0
FT5
RT7
0
FT6
RT8
0
FT7
RT9
0
FT8
0
FT9
RT11
RT10
0
FT10
RT12
0
FT11
RT13
0
FT12
RT14
0
FT13
RT15
0
FT14
0
FT15
0
PIF15
Res.
RT16
0
FT16
0
SWI16
Res.
0
PIF16
Res.
Res.
Res.
Res.
0
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reserved.
Res.
EXTI_RTSR2
Res.
Res.
Res.
Res.
Res.
Res.
Res.
RT21
0
Res.
FT21
0
Res.
0
Res.
RT22
0
Reserved
Res.
0x020
0
SWI21
Reset value
0x0100x01C
0
PIF21
Res.
Res.
Res.
Res.
Res.
Res.
Res.
EXTI_PR1
Res.
0x00C
Res.
Reset value
0
FT22
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
EXTI_SWIER1
Res.
0x008
Res.
Reset value
0
SWI22
Res.
Res.
Res.
Res.
Res.
Res.
Res.
EXTI_FTSR1
Res.
0x004
Res.
Reset value
PIF22
Res.
Res.
Res.
Res.
Res.
Res.
EXTI_RTSR1
Res.
0x000
Res.
Offset Register name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 85. EXTI register map and reset values
0
RM0461 Rev 10
0
411/1290
412
0x090
412/1290
EXTI_IMR2
Res.
Res.
IM1
IM0
0
EXTI_EMR1
Res.
Res.
Res.
Res.
Res.
EM22
EM21
EM20
EM19
EM18
EM17
Res.
EM15
0
0
0
0
0
0
Reserved.
0
RM0461 Rev 10
EM0
0
EM1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Res.
0
Res.
IM2
0
EM2
IM3
0
IM34
IM4
0
EM3
IM5
0
Res.
IM6
0
EM4
IM7
0
Res.
IM8
0
EM5
IM9
0
Res.
IM10
0
EM6
IM11
0
IM38
IM12
0
EM7
IM13
0
Res.
IM14
0
EM8
IM15
0
Res.
IM16
0
EM9
IM17
0
Res.
IM18
0
EM10
IM19
0
IM42
IM20
0
EM11
IM21
0
EM12
IM22
0
IM46
IM23
0
IM44
IM24
0
EM13
IM25
0
IM45
IM26
0
EM14
IM27
0
IM46
Reset value
Res.
Reserved
Res.
IM28
Reserved
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
IM29
0
Res.
Reset value
0
Refer to Section 2.4 for the register boundary addresses.
0
0
0
0
0
0
0
0
0
Res.
Res.
SWI34
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
PIF34
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
SWI45
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
PIF45
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
EXTI_PR2
Res.
0x08C
EXTI_IMR1
Reset value
Res.
0x084
EXTI_SWIER2
Res.
0x080
Res.
Res.
FT34
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
FT45
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
EXTI_FTSR2
Res.
Reset value
IM30
0x0300x07C
IM31
0x02C
Res.
0x028
Res.
0x024
Res.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Offset Register name
Res.
Extended interrupts and event controller (EXTI)
RM0461
Table 85. EXTI register map and reset values (continued)
0
0
0
Reserved.
RM0461
Cyclic redundancy check calculation unit (CRC)
15
Cyclic redundancy check calculation unit (CRC)
15.1
Introduction
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from 8-, 16or 32-bit data word and a generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the functional safety standards, they offer a means of
verifying the flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link
time and stored at a given memory location.
15.2
CRC main features
•
Uses CRC-32 (Ethernet) polynomial: 0x4C11DB7
X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 +X8 + X7 + X5 + X4 + X2+ X +1
•
Alternatively, uses fully programmable polynomial with programmable size (7, 8, 16, 32
bits)
•
Handles 8-,16-, 32-bit data size
•
Programmable CRC initial value
•
Single input/output 32-bit data register
•
Input buffer to avoid bus stall during calculation
•
CRC computation done in 4 AHB clock cycles (HCLK) for the 32-bit data size
•
General-purpose 8-bit register (can be used for temporary storage)
•
Reversibility option on I/O data
•
Accessed through AHB slave peripheral by 32-bit words only, with the exception of
CRC_DR register that can be accessed by words, right-aligned half-words and
right-aligned bytes
RM0461 Rev 10
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Cyclic redundancy check calculation unit (CRC)
15.3
CRC functional description
15.3.1
CRC block diagram
RM0461
Figure 43. CRC calculation unit block diagram
32-bit AHB bus
read access
write access
Data register
(output)
crc_hclk
32-bit accesses
Data register
(input)
CRC_INIT
CRC_CR
CRC computation
CRC_POL
CRC_IDR
MS19882V3
15.3.2
CRC internal signals
Table 86. CRC internal input/output signals
15.3.3
Signal name
Signal type
crc_hclk
Digital input
Description
AHB clock
CRC operation
The CRC calculation unit has a single 32-bit read/write data register (CRC_DR). It is used to
input new data (write access), and holds the result of the previous CRC calculation (read
access).
Each write operation to the data register creates a combination of the previous CRC value
(stored in CRC_DR) and the new one. CRC computation is done on the whole 32-bit data
word or byte by byte depending on the format of the data being written.
The CRC_DR register can be accessed by word, right-aligned half-word and right-aligned
byte. For the other registers only 32-bit accesses are allowed.
The duration of the computation depends on data width:
•
4 AHB clock cycles for 32 bits
•
2 AHB clock cycles for 16 bits
•
1 AHB clock cycles for 8 bits
An input buffer allows a second data to be immediately written without waiting for any
wait-states due to the previous CRC calculation.
414/1290
RM0461 Rev 10
RM0461
Cyclic redundancy check calculation unit (CRC)
The data size can be dynamically adjusted to minimize the number of write accesses for a
given number of bytes. For instance, a CRC for 5 bytes can be computed with a word write
followed by a byte write.
The input data can be reversed to manage the various endianness schemes. The reversing
operation can be performed on 8 bits, 16 bits and 32 bits depending on the REV_IN[1:0] bits
in the CRC_CR register.
For example, 0x1A2B3C4D input data are used for CRC calculation as:
•
0x58D43CB2 with bit-reversal done by byte
•
0xD458B23C with bit-reversal done by half-word
•
0xB23CD458 with bit-reversal done on the full word
The output data can also be reversed by setting the REV_OUT bit in the CRC_CR register.
The operation is done at bit level. For example, 0x11223344 output data are converted to
0x22CC4488.
The CRC calculator can be initialized to a programmable value using the RESET control bit
in the CRC_CR register (the default value is 0xFFFFFFFF).
The initial CRC value can be programmed with the CRC_INIT register. The CRC_DR
register is automatically initialized upon CRC_INIT register write access.
The CRC_IDR register can be used to hold a temporary value related to CRC calculation. It
is not affected by the RESET bit in the CRC_CR register.
Polynomial programmability
The polynomial coefficients are fully programmable through the CRC_POL register, and the
polynomial size can be configured to be 7, 8, 16 or 32 bits by programming the
POLYSIZE[1:0] bits in the CRC_CR register. Even polynomials are not supported.
Note:
The type of an even polynomial is X+X2+..+Xn, while the type of an odd polynomial is
1+X+X2+..+Xn.
If the CRC data is less than 32-bit, its value can be read from the least significant bits of the
CRC_DR register.
To obtain a reliable CRC calculation, the change on-fly of the polynomial value or size can
not be performed during a CRC calculation. As a result, if a CRC calculation is ongoing, the
application must either reset it or perform a CRC_DR read before changing the polynomial.
The default polynomial value is the CRC-32 (Ethernet) polynomial: 0x4C11DB7.
RM0461 Rev 10
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419
Cyclic redundancy check calculation unit (CRC)
15.4
RM0461
CRC registers
The CRC_DR register can be accessed by words, right-aligned half-words and right-aligned
bytes. For the other registers only 32-bit accesses are allowed.
15.4.1
CRC data register (CRC_DR)
Address offset: 0x00
Reset value: 0xFFFF FFFF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
DR[31:16]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
DR[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:0 DR[31:0]: Data register bits
This register is used to write new data to the CRC calculator.
It holds the previous CRC calculation result when it is read.
If the data size is less than 32 bits, the least significant bits are used to write/read the correct
value.
15.4.2
CRC independent data register (CRC_IDR)
Address offset: 0x04
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
IDR[31:16]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
IDR[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:0 IDR[31:0]: General-purpose 32-bit data register bits
These bits can be used as a temporary storage location for four bytes.
This register is not affected by CRC resets generated by the RESET bit in the CRC_CR
register
416/1290
RM0461 Rev 10
RM0461
Cyclic redundancy check calculation unit (CRC)
15.4.3
CRC control register (CRC_CR)
Address offset: 0x08
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
REV_
OUT
Res.
Res.
RESET
Res.
Res.
Res.
Res.
Res.
Res.
Res.
REV_IN[1:0]
rw
rw
rw
POLYSIZE[1:0]
rw
rw
rs
Bits 31:8 Reserved, must be kept at reset value.
Bit 7 REV_OUT: Reverse output data
This bit controls the reversal of the bit order of the output data.
0: Bit order not affected
1: Bit-reversed output format
Bits 6:5 REV_IN[1:0]: Reverse input data
This bitfield controls the reversal of the bit order of the input data
00: Bit order not affected
01: Bit reversal done by byte
10: Bit reversal done by half-word
11: Bit reversal done by word
Bits 4:3 POLYSIZE[1:0]: Polynomial size
These bits control the size of the polynomial.
00: 32 bit polynomial
01: 16 bit polynomial
10: 8 bit polynomial
11: 7 bit polynomial
Bits 2:1 Reserved, must be kept at reset value.
Bit 0 RESET: RESET bit
This bit is set by software to reset the CRC calculation unit and set the data register to the
value stored in the CRC_INIT register. This bit can only be set, it is automatically cleared by
hardware
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Cyclic redundancy check calculation unit (CRC)
15.4.4
RM0461
CRC initial value (CRC_INIT)
Address offset: 0x10
Reset value: 0xFFFF FFFF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
CRC_INIT[31:16]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
22
21
20
19
18
17
16
CRC_INIT[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:0 CRC_INIT[31:0]: Programmable initial CRC value
This register is used to write the CRC initial value.
15.4.5
CRC polynomial (CRC_POL)
Address offset: 0x14
Reset value: 0x04C1 1DB7
31
30
29
28
27
26
25
24
23
POL[31:16]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
POL[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:0 POL[31:0]: Programmable polynomial
This register is used to write the coefficients of the polynomial to be used for CRC
calculation.
If the polynomial size is less than 32 bits, the least significant bits have to be used to program
the correct value.
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RM0461 Rev 10
RM0461
15.4.6
Cyclic redundancy check calculation unit (CRC)
CRC register map
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CRC_CR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
0x10
CRC_INIT
Reset value
0x14
0
0
0
0
0
CRC_INIT[31:0]
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CRC_POL
Reset value
0
Res.
0
POLYSIZE[1:0]
Reset value
Res.
IDR[31:0]
Res.
CRC_IDR
1
Res.
0x08
1
Res.
0x04
1
REV_IN[1:0]
Reset value
Res.
DR[31:0]
RESET
CRC_DR
Res.
0x00
Register
name
REV_OUT
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 87. CRC register map and reset values
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
1
0
1
1
0
1
1
1
POL[31:0]
0
0
0
0
0
1
0
0
1
1
0
0
0
0
0
1
0
0
Refer to Section 2.4 for the register boundary addresses.
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Analog-to-digital converter (ADC)
RM0461
16
Analog-to-digital converter (ADC)
16.1
Introduction
The 12-bit ADC is a successive approximation analog-to-digital converter. It has up to 18
multiplexed channels allowing it to measure signals from 12 external and 4 internal sources.
A/D conversion of the various channels can be performed in single, continuous, scan or
discontinuous mode. The result of the ADC is stored in a left-aligned or right-aligned 16-bit
data register.
The analog watchdog feature allows the application to detect if the input voltage goes
outside the user-defined higher or lower thresholds.
An efficient low-power mode is implemented to allow very low consumption at low
frequency.
A built-in hardware oversampler allows analog performances to be improved while offloading the related computational burden from the CPU.
420/1290
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RM0461
16.2
Analog-to-digital converter (ADC)
ADC main features
•
•
•
•
•
High performance
–
12-bit, 10-bit, 8-bit or 6-bit configurable resolution
–
ADC conversion time: 0.4 µs for 12-bit resolution (2.5Msps), faster conversion
times can be obtained by lowering resolution.
–
Self-calibration
–
Programmable sampling time
–
Data alignment with built-in data coherency
–
DMA support
Low-power
–
The application can reduce PCLK frequency for low-power operation while still
keeping optimum ADC performance. For example, 0.4 µs conversion time is kept,
whatever the PCLK frequency
–
Wait mode: prevents ADC overrun in applications with low PCLK frequency
–
Auto off mode: ADC is automatically powered off except during the active
conversion phase. This dramatically reduces the power consumption of the ADC.
Analog input channels
–
12 external analog inputs
–
1 channel for internal temperature sensor (VTS)
–
1 channel for internal reference voltage (VREFINT)
–
1 channel for monitoring external VBAT power supply pin
–
1 channel for monitoring DAC internal channel input
Start-of-conversion can be initiated:
–
By software
–
By hardware triggers with configurable polarity (timer events or GPIO input
events)
Conversion modes
–
Can convert a single channel or can scan a sequence of channels.
–
Single mode converts selected inputs once per trigger
–
Continuous mode converts selected inputs continuously
–
Discontinuous mode
•
Interrupt generation at the end of sampling, end of conversion, end of sequence
conversion, and in case of analog watchdog or overrun events
•
Analog watchdog
•
Oversampler
•
–
16-bit data register
–
Oversampling ratio adjustable from 2 to 256x
–
Programmable data shift up to 8-bits
ADC input range: VSSA ≤ VIN ≤ VREF+
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Analog-to-digital converter (ADC)
16.3
RM0461
ADC functional description
Figure 44 shows the ADC block diagram and Table 88 gives the ADC pin description.
Figure 44. ADC block diagram
Analog supply
VREF+
1.62 to 3.6 V
AREADY
EOSMP
EOSEQ
EOC
OVR
AWD
AUTOFF
Auto-off mode
ADEN/ADDIS
CH_SEL[17:0]
CONT
single/cont.
ADC_IN[11:0]
DATA[15:0]
Supply &
reference
LFTRIG
VBAT/3
VREFINT
Input
VTS
selection
dac_out1
& scan
VIN[x] control
ADCAL self
calibration
Master
DMA request
CONVERTED Overs
start
DATA ampler
OVRMODE
(overrun mode)
ALIGN (left/right)
RES[1:0]
(12, 10, 8 bits)
ADSTART
SW trigger
ADSTP
stop conversion
TIM1_TRGO2
TIM1_CC4
TIM2_TRGO
TIM2_CH4
TIM2_CH3
EXTI[11]
APB
interface
DMA
Start & stop
control
AUTDLY
Auto-delayed
conversion
CPU
Master
AHB
to slave
APB
SAR ADC
VIN
SMP[2:0]
sampling
time
ADC interrupt IRQ
AHB
SCANDIR
up/down
DMAEN
DMACFG
ADC_AWDx_OUT
To analog watchdog
AWDxEN
AWDxSGL
AWDCHx[4:0]
LTx[11:0]
TOVS
HTx[11:0]
OVSS[3:0]
OVSR[3:0]
HW
EXTEND[1:0] trigger
Trigger enable
and edge
selection
OVSE
DISCEN
Discontinuous
mode
EXTSEL[2:0]
Trigger selection
MSv61353V3
16.3.1
ADC pins and internal signals
Table 88. ADC input/output pins
422/1290
Name
Signal type
Remarks
VDDA
Input, analog power
supply
Analog power supply and positive reference voltage
for the ADC
VSSA
Input, analog supply
ground
Ground for analog power supply
VREF+
Input, analog reference
positive
The higher/positive reference voltage for the ADC.
ADC_INx
Analog input signals
12 external analog input channels
RM0461 Rev 10
RM0461
Analog-to-digital converter (ADC)
Table 89. ADC internal input/output signals
Internal signal
name
Signal type
VIN[x]
Analog input
channels
TRGx
Input
ADC conversion triggers
VTS
Input
Internal temperature sensor output voltage
VREFINT
Input
Internal voltage reference output voltage
VBAT/3
Input
VBAT pin input voltage divided by 3
dac_out1
Input
DAC internal channel1 input
ADC_AWDx_OUT
Output
Internal analog watchdog output signal connected to onchip timers (x = Analog watchdog number = 1,2,3)
Description
Connected either to internal channels or to ADC_INi
external channels
Table 90. External triggers
Name
16.3.2
Source
EXTSEL[2:0]
TRG0
TIM1_TRGO2
000
TRG1
TIM1_CC4
001
TRG2
TIM2_TRGO
010
TRG3
TIM2_CH4
011
TRG4
Reserved
100
TRG5
TIM2_CH3
101
TRG6
Reserved
110
TRG7
EXTI11
111
ADC voltage regulator (ADVREGEN)
The ADC has a specific internal voltage regulator which must be enabled and stable before
using the ADC.
The ADC internal voltage regulator can be enabled by setting ADVREGEN bit to 1 in the
ADC_CR register. The software must wait for the ADC voltage regulator startup time
(tADCVREG_STUP) before launching a calibration or enabling the ADC. This delay must be
managed by software (for details on tADCVREG_STUP, refer to the device datasheet).
After ADC operations are complete, the ADC is disabled (ADEN = 0). To keep power
consumption low, it is important to disable the ADC voltage regulator before entering lowpower mode (LPRun, LPSleep or Stop mode). Refer to Section : ADC voltage regulator
disable sequence).
Note:
When the internal voltage regulator is disabled, the internal analog calibration is kept.
Analog reference from the power control unit
The internal ADC voltage regulator internally uses an analog reference delivered by the
power control unit through a buffer. This buffer is always enabled when the main voltage
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Analog-to-digital converter (ADC)
RM0461
regulator of the power control unit operates in normal Run mode (refer to Reset and clock
control and power control sections).
If the main voltage regulator enters low-power mode (such as Low-power run mode), this
buffer is disabled and the ADC cannot be used.
ADC Voltage regulator enable sequence
To enable the ADC voltage regulator, set ADVREGEN bit to 1 in ADC_CR register.
ADC voltage regulator disable sequence
To disable the ADC voltage regulator, follow the sequence below:
16.3.3
1.
Make sure that the ADC is disabled (ADEN = 0).
2.
Clear ADVREGEN bit in ADC_CR register.
Calibration (ADCAL)
The ADC has a calibration feature. During the procedure, the ADC calculates a calibration
factor which is internally applied to the ADC until the next ADC power-off. The application
must not use the ADC during calibration and must wait until it is complete.
Calibration should be performed before starting A/D conversion. It removes the offset error
which may vary from chip to chip due to process variation.
The calibration is initiated by software by setting bit ADCAL to 1. It can be initiated only
when all the following conditions are met:
•
the ADC voltage regulator is enabled (ADVREGEN = 1),
•
the ADC is disabled (ADEN = 0), and
•
the Auto-off mode is disabled (AUTOFF = 0).
ADCAL bit stays at 1 during all the calibration sequence. It is then cleared by hardware as
soon the calibration completes. After this, the calibration factor can be read from the
ADC_DR register (from bits 6 to 0).
The internal analog calibration is kept if the ADC is disabled (ADEN = 0). When the ADC
operating conditions change (VREF+ changes are the main contributor to ADC offset
variations and temperature change to a lesser extend), it is recommended to re-run a
calibration cycle.
The calibration factor is lost in the following cases:
•
The power supply is removed from the ADC (for example when the product enters
Standby or VBAT mode)
•
The ADC peripheral is reset.
The calibration factor is lost each time power is removed from the ADC (for example when
the product enters Standby or VBAT mode). Still, it is possible to save and restore the
calibration factor by software to save time when re-starting the ADC (as long as temperature
and voltage are stable during the ADC power-down).
The calibration factor can be written if the ADC is enabled but not converting (ADEN = 1 and
ADSTART = 0). Then, at the next start of conversion, the calibration factor is automatically
injected into the analog ADC. This loading is transparent and does not add any cycle
latency to the start of the conversion.
424/1290
RM0461 Rev 10
RM0461
Analog-to-digital converter (ADC)
Software calibration procedure
1.
Ensure that ADEN = 0, AUTOFF = 0, ADVREGEN = 1 and DMAEN = 0.
2.
Set ADCAL = 1.
3.
Wait until ADCAL = 0 (or until EOCAL = 1). This can be handled by interrupt if the
interrupt is enabled by setting the EOCALIE bit in the ADC_IER register
4.
The calibration factor can be read from bits 6:0 of ADC_DR or ADC_CALFACT
registers.
5.
To reduce the noise effect of the calibration factor extraction, the software can make
average of eight CALFACT[6:0] values (optional).
Figure 45. ADC calibration
t CAB
ADCAL
ADC State
OFF
Startup
ADC_DR[6:0]
ADC_CALFACT[6:0]
by SW
OFF
CALIBRATE
CALIBRATION
FACTOR
0x00
by HW
MSv33703V2
Calibration factor forcing software procedure
1.
Ensure that ADEN = 1 and ADSTART = 0 (ADC started with no conversion ongoing)
2.
Write ADC_CALFACT with the saved calibration factor
3.
The calibration factor is used as soon as a new conversion is launched.
Figure 46. Calibration factor forcing
ADC state
Internal calibration
factor[6:0]
Ready (not converting)
Updating
caibration
Converting channel
(Single ended)
Ready
Converting channel
(Single ended)
F2
F1
Start conversion
(hardware or software)
WRITE ADC_CALFACT
CALFACT[6:0]
by S/W
F2
by H/W
MSv31925V2
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Analog-to-digital converter (ADC)
16.3.4
RM0461
ADC on-off control (ADEN, ADDIS, ADRDY)
At power-up, the ADC is disabled and put in power-down mode (ADEN = 0).
As shown in Figure 47, the ADC needs a stabilization time of tSTAB before it starts
converting accurately.
Two control bits are used to enable or disable the ADC:
•
Set ADEN = 1 to enable the ADC. The ADRDY flag is set as soon as the ADC is ready
for operation.
•
Set ADDIS = 1 to disable the ADC and put the ADC in power down mode. The ADEN
and ADDIS bits are then automatically cleared by hardware as soon as the ADC is fully
disabled.
Conversion can then start either by setting ADSTART to 1 (refer to Section 16.4: Conversion
on external trigger and trigger polarity (EXTSEL, EXTEN)) or when an external trigger event
occurs if triggers are enabled.
Follow this procedure to enable the ADC:
1.
Clear the ADRDY bit in ADC_ISR register by programming this bit to 1.
2.
Set ADEN = 1 in the ADC_CR register.
3.
Wait until ADRDY = 1 in the ADC_ISR register (ADRDY is set after the ADC startup
time). This can be handled by interrupt if the interrupt is enabled by setting the
ADRDYIE bit in the ADC_IER register.
Follow this procedure to disable the ADC:
1.
Check that ADSTART = 0 in the ADC_CR register to ensure that no conversion is
ongoing. If required, stop any ongoing conversion by writing 1 to the ADSTP bit in the
ADC_CR register and waiting until this bit is read at 0.
2.
Set ADDIS = 1 in the ADC_CR register.
3.
If required by the application, wait until ADEN = 0 in the ADC_CR register, indicating
that the ADC is fully disabled (ADDIS is automatically reset once ADEN = 0).
4.
Clear the ADRDY bit in ADC_ISR register by programming this bit to 1 (optional).
Figure 47. Enabling/disabling the ADC
ADEN
tSTAB
ADRDY
ADDIS
ADC
state
by S/W
OFF
Startup
RDY
Converting CH
RDY
REQ
-OF
OFF
by H/W
MSv62472V1
426/1290
RM0461 Rev 10
RM0461
Note:
Analog-to-digital converter (ADC)
In Auto-off mode (AUTOFF = 1) the power-on/off phases are performed automatically, by
hardware and the ADRDY flag is not set.
When the bus clock is much faster than the analog ADC clock (fADC), a minimum delay of
ten fADC clock cycles must be respected between ADEN and ADDIS bit settings.
16.3.5
ADC clock (CKMODE, PRESC[3:0])
The ADC has a dual clock-domain architecture, so that the ADC can be fed with a clock
(ADC asynchronous clock) independent from the APB clock (PCLK).
Figure 48. ADC clock scheme
ADITF
RCC
(Reset & Clock Controller)
APB interface
PCLK
Bits CKMODE[1:0]
of ADC_CFGR2
ADC
asynchronous
clock
/1 or /2 or /4
Others
/1,2,4,6,8,10,12
16,32,64,128,256
00
Bits PRESC[3:0]
of ADC_CCR
Analog ADC
clock (fADC)
Analog
ADC
Bits CKMODE[1:0]
of ADC_CFGR2
MSv31926V5
1. Refer to Section Reset and clock control (RCC) for how the PCLK clock and ADC asynchronous clock are
enabled.
The input clock of the analog ADC can be selected between two different clock sources (see
Figure 48: ADC clock scheme to see how the PCLK clock and the ADC asynchronous clock
are enabled):
a)
The ADC clock can be a specific clock source, named “ADC asynchronous clock“
which is independent and asynchronous with the APB clock.
Refer to RCC Section for more information on generating this clock source.
To select this scheme, bits CKMODE[1:0] of the ADC_CFGR2 register must be
reset.
b)
The ADC clock can be derived from the APB clock of the ADC bus interface,
divided by a programmable factor (1, 2 or 4) according to bits CKMODE[1:0].
To select this scheme, bits CKMODE[1:0] of the ADC_CFGR2 register must be
different from “00”.
In option a), the generated ADC clock can eventually be divided by a prescaler (1, 2, 4, 6, 8,
10, 12, 16, 32, 64, 128, 256) when programming the bits PRESC[3:0] in the ADC_CCR
register).
Option a) has the advantage of reaching the maximum ADC clock frequency whatever the
APB clock scheme selected.
Option b) has the advantage of bypassing the clock domain resynchronizations. This can be
useful when the ADC is triggered by a timer and if the application requires that the ADC is
RM0461 Rev 10
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Analog-to-digital converter (ADC)
RM0461
precisely triggered without any uncertainty (otherwise, an uncertainty of the trigger instant is
added by the resynchronizations between the two clock domains).
Table 91. Latency between trigger and start of conversion(1)
ADC clock source
Latency between the trigger event
and the start of conversion
CKMODE[1:0]
HSI16, SYSCLK or
PLLPCLK(2)
00
Latency is not deterministic (jitter)
PCLK divided by 2
01
Latency is deterministic (no jitter) and equal to
3.25 fADC cycles
PCLK divided by 4
10
Latency is deterministic (no jitter) and equal to
3.125 fADC cycles
PCLK divided by 1
11
Latency is deterministic (no jitter) and equal to
3 fADC cycles
1. Refer to the device datasheet for the maximum fADC frequency.
2. Selected with ADCSEL bitfield of the RCC_CCIPR register
Caution:
428/1290
For correct operation of the ADC analog block, the analog ADC clock (fADC) must have a
duty cycle ranging from 45% to 55%. This is granted when the incoming clock (PCLK or
ADC asynchronous clock) is divided by a factor of two or higher, using one of the scaler
blocks inside the ADC. If it is not the case, some additional rules must be followed:
•
When CKMODE[1:0] = 11 (PCLK divided by one), the AHB and APB prescalers in the
RCC must be configured in bypass mode.
•
When the analog ADC clock is derived from the HSE or LSE bypass clock, this bypass
clock must have a 45-to-55% duty cycle unless this clock is routed to the ADC through
the PLL.
RM0461 Rev 10
RM0461
16.3.6
Analog-to-digital converter (ADC)
ADC connectivity
ADC inputs are connected to the external channels as well as internal sources as described
in Figure 49.
Figure 49. ADC connectivity
STM32WLxx
ADC
Channel selection
VIN[0]
ADC_IN0
VIN[1]
ADC_IN1
VIN[2]
ADC_IN2
VIN[3]
ADC_IN3
VIN[4]
ADC_IN4
VIN[5]
ADC_IN5
VIN[6]
ADC_IN6
VIN[7]
ADC_IN7
VREF+
VIN[8]
ADC_IN8
VIN
VIN[9]
ADC_IN9
SAR
ADC
VIN[10]
ADC_IN10
VIN[11]
ADC_IN11
VTS
VREFINT
VBAT/3
reserved
reserved
dac_out1
VREF-
VIN[12]
VIN[13]
VIN[14]
VIN[15]
VIN[16]
VIN[17]
MSv61354V1
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Analog-to-digital converter (ADC)
16.3.7
RM0461
Configuring the ADC
The software must write the ADCAL and ADEN bits in the ADC_CR register and configure
the ADC_CFGR1 and ADC_CFGR2 registers only when the ADC is disabled (ADEN must
be cleared).
The software must only write to the ADSTART and ADDIS bits in the ADC_CR register only
if the ADC is enabled and there is no pending request to disable the ADC (ADEN = 1 and
ADDIS = 0).
For all the other control bits in the ADC_IER, ADC_SMPR, ADC_CHSELR and ADC_CCR
registers, refer to the description of the corresponding control bit in Section 16.12: ADC
registers.
ADC_AWDTRx registers can be modified when conversion is ongoing.
The software must only write to the ADSTP bit in the ADC_CR register if the ADC is enabled
(and possibly converting) and there is no pending request to disable the ADC (ADSTART =
1 and ADDIS = 0).
Note:
There is no hardware protection preventing software from making write operations forbidden
by the above rules. If such a forbidden write access occurs, the ADC may enter an
undefined state. To recover correct operation in this case, the ADC must be disabled (clear
ADEN = 0 and all the bits in the ADC_CR register).
16.3.8
Channel selection (CHSEL, SCANDIR, CHSELRMOD)
There are up to 18 multiplexed channels:
•
12 analog inputs from GPIO pins (ADC_INx)
•
4 internal analog inputs (temperature sensor, internal reference voltage, DAC internal
channel1, VBAT channel)
•
2 reserved analog inputs (ADC VIN[16] and VIN[15])
It is possible to convert a single channel or a sequence of channels.
The sequence of the channels to be converted can be programmed in the ADC_CHSELR
channel selection register: each analog input channel has a dedicated selection bit
(CHSELx).
The ADC scan sequencer can be used in two different modes:
•
Sequencer not fully configurable:
The order in which the channels are scanned is defined by the channel number
(CHSELRMOD bit must be cleared in ADC_CFGR1 register):
430/1290
–
Sequence length configured through CHSELx bits in ADC_CHSELR register
–
Sequence direction: the channels are scanned in a forward direction (from the
lowest to the highest channel number) or backward direction (from the highest to
the lowest channel number) depending on the value of SCANDIR bit
(SCANDIR = 0: forward scan, SCANDIR = 1: backward scan)
RM0461 Rev 10
RM0461
Analog-to-digital converter (ADC)
–
•
Any channel can belong to in these sequences
Sequencer fully configurable
The CHSELRMOD bit is set in ADC_CFGR1 register.
–
Sequencer length is up to 8 channels
–
The order in which the channels are scanned is independent from the channel
number. Any order can be configured through SQ1[3:0] to SQ8[3:0] bits in
ADC_CHSELR register.
–
Only channel 0 to channel 14 can be selected in this sequence
–
If the sequencer detects SQx[3:0] = 0b1111, the following SQx[3:0] registers are
ignored.
–
If no 0b1111 is programmed in SQx[3:0], the sequencer scans full eight channels.
After programming ADC CHSELR, SCANDIR and CHSELRMOD bits, it is mandatory to wait
for CCRDY flag before starting conversions. It indicates that the new channel setting has
been applied. If a new configuration is required, the CCRDY flag must be cleared prior to
starting the conversion.
The software is allowed to program the CHSEL, SCANDIR, CHSELRMOD bits only when
ADSTART bit is cleared (which ensures that no conversion is ongoing).
Temperature sensor, DAC output, VREFINT and VBAT internal channels
The temperature sensor is connected to channel ADC VIN[12].
The internal voltage reference VREFINT is connected to channel ADC VIN[13].
VBAT channel is connected to ADC VIN[14] channel.
The internal dac_out1 output voltage is connected to ADC VIN[17] channel.
When VREF+ is lower than VDDA, this channel is not converted.
16.3.9
Programmable sampling time (SMPx[2:0])
Before starting a conversion, the ADC needs to establish a direct connection between the
voltage source to be measured and the embedded sampling capacitor of the ADC. This
sampling time must be enough for the input voltage source to charge the sample and hold
capacitor to the input voltage level.
Having a programmable sampling time allows the conversion speed to be trimmed
according to the input resistance of the input voltage source.
The ADC samples the input voltage for a number of ADC clock cycles that can be modified
using the SMP1[2:0] and SMP2[2:0] bits in the ADC_SMPR register.
Each channel can choose one out of two sampling times configured in SMP1[2:0] and
SMP2[2:0] bitfields, through SMPSELx bits in ADC_SMPR register.
The total conversion time is calculated as follows:
tCONV = Sampling time + 12.5 x ADC clock cycles
Example:
With fADC = 16 MHz and a sampling time of 1.5 ADC clock cycles:
tCONV = 1.5 + 12.5 = 14 ADC clock cycles = 0.875 µs
The ADC indicates the end of the sampling phase by setting the EOSMP flag.
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Analog-to-digital converter (ADC)
16.3.10
RM0461
Single conversion mode (CONT = 0)
In Single conversion mode, the ADC performs a single sequence of conversions, converting
all the channels once. This mode is selected when CONT = 0 in the ADC_CFGR1 register.
Conversion is started by either:
•
Setting the ADSTART bit in the ADC_CR register
•
Hardware trigger event
Inside the sequence, after each conversion is complete:
•
The converted data are stored in the 16-bit ADC_DR register
•
The EOC (end of conversion) flag is set
•
An interrupt is generated if the EOCIE bit is set
After the sequence of conversions is complete:
•
The EOS (end of sequence) flag is set
•
An interrupt is generated if the EOSIE bit is set
Then the ADC stops until a new external trigger event occurs or the ADSTART bit is set
again.
Note:
To convert a single channel, program a sequence with a length of 1.
16.3.11
Continuous conversion mode (CONT = 1)
In continuous conversion mode, when a software or hardware trigger event occurs, the ADC
performs a sequence of conversions, converting all the channels once and then
automatically re-starts and continuously performs the same sequence of conversions. This
mode is selected when CONT = 1 in the ADC_CFGR1 register. Conversion is started by
either:
•
Setting the ADSTART bit in the ADC_CR register
•
Hardware trigger event
Inside the sequence, after each conversion is complete:
•
The converted data are stored in the 16-bit ADC_DR register
•
The EOC (end of conversion) flag is set
•
An interrupt is generated if the EOCIE bit is set
After the sequence of conversions is complete:
•
The EOS (end of sequence) flag is set
•
An interrupt is generated if the EOSIE bit is set
Then, a new sequence restarts immediately and the ADC continuously repeats the
conversion sequence.
Note:
To convert a single channel, program a sequence with a length of 1.
It is not possible to have both discontinuous mode and continuous mode enabled: it is
forbidden to set both bits DISCEN = 1 and CONT = 1.
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RM0461
16.3.12
Analog-to-digital converter (ADC)
Starting conversions (ADSTART)
Software starts ADC conversions by setting ADSTART = 1.
When ADSTART is set, the conversion:
•
Starts immediately if EXTEN = 00 (software trigger)
•
At the next active edge of the selected hardware trigger if EXTEN ≠ 00
The ADSTART bit is also used to indicate whether an ADC operation is currently ongoing. It
is possible to re-configure the ADC while ADSTART = 0, indicating that the ADC is idle.
The ADSTART bit is cleared by hardware:
•
In single mode with software trigger (CONT = 0, EXTEN = 00)
–
•
In discontinuous mode with software trigger (CONT = 0, DISCEN = 1, EXTEN = 00)
–
•
At end of conversion (EOC = 1)
In all cases (CONT = x, EXTEN = XX)
–
Note:
At any end of conversion sequence (EOS = 1)
After execution of the ADSTP procedure invoked by software (see
Section 16.3.14: Stopping an ongoing conversion (ADSTP) on page 435)
In continuous mode (CONT = 1), the ADSTART bit is not cleared by hardware when the
EOS flag is set because the sequence is automatically relaunched.
When hardware trigger is selected in single mode (CONT = 0 and EXTEN = 01), ADSTART
is not cleared by hardware when the EOS flag is set (except if DMAEN = 1 and
DMACFG = 0 in which case ADSTART is cleared at end of the DMA transfer). This avoids
the need for software having to set the ADSTART bit again and ensures the next trigger
event is not missed.
After changing channel selection configuration (by programming ADC_CHSELR register or
changing CHSELRMOD or SCANDIR), it is mandatory to wait until CCRDY flag is asserted
before asserting ADSTART, otherwise the value written to ADSTART is ignored.
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Analog-to-digital converter (ADC)
16.3.13
RM0461
Timings
The elapsed time between the start of a conversion and the end of conversion is the sum of
the configured sampling time plus the successive approximation time depending on data
resolution:
tCONV = tSMPL + tSAR = [1.5 |min + 12.5 |12bit] x 1/fADC
tCONV = tSMPL + tSAR = 42.9 ns |min + 357.1 ns |12bit = 0.400 µs |min (for fADC = 35 MHz)
Figure 50. Analog-to-digital conversion time
ADC state
Sampling Ch(N)
RDY
Analog channel
Sampling Ch(N+1)
Ch(N+1)
Ch(N)
Internal S/H
Hold AIN(N)
Sample AIN(N)
tSMPL
ADSTART
Converting Ch(N)
Sample AIN(N+1)
(2)
(1)
tSAR
Set by
SW
Cleared
by SW
Set by
HW
EOSMP
Cleared by
HW/SW
Set by
HW
EOC
ADC_DR
Data N
Data N-1
Indicative timings
MSv30532V5
1. tSMPL depends on SMP[2:0].
2. tSAR depends on RES[2:0].
3. The synchronization between the analog clock and the digital clock domains is not described in the above
figure.
Figure 51. ADC conversion timings
ADSTART(1)
ADC state
tLATR (2)
Ready
S0
Conversion 0
S1
WLATENCY
Conversion 1
(3)
S2
WLATENCY
Conversion 2
(3)
S3
Conversion 3
WLATENCY (3)
ADC_DR
Data 0
Data 1
Data 2
MSv33174V2
1. EXTEN = 00 or EXTEN ≠ 00.
2. Trigger latency (refer to datasheet for more details).
3. ADC_DR register write latency (refer to datasheet for more details).
434/1290
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RM0461
16.3.14
Analog-to-digital converter (ADC)
Stopping an ongoing conversion (ADSTP)
The software can decide to stop any ongoing conversions by setting ADSTP = 1 in the
ADC_CR register.
This resets the ADC operation and the ADC is idle, ready for a new operation.
When the ADSTP bit is set by software, any ongoing conversion is aborted and the result is
discarded (ADC_DR register is not updated with the current conversion).
The scan sequence is also aborted and reset (meaning that restarting the ADC would restart a new sequence).
Once this procedure is complete, the ADSTP and ADSTART bits are both cleared by
hardware and the software must wait until ADSTART=0 before starting new conversions.
Figure 52. Stopping an ongoing conversion
ADC state
RDY
ADSTART
set by
SW
SAMPLING CH(N)
CONVERTING CH(N)
RDY
cleared by HW
set by SW
ADSTOP
ADC_DR
cleared by HW
DATA N-1
MSv30337V2
16.4
Conversion on external trigger and trigger polarity (EXTSEL,
EXTEN)
A conversion or a sequence of conversion can be triggered either by software or by an
external event (for example timer capture). If the EXTEN[1:0] control bits are not equal to
“0b00”, then external events are able to trigger a conversion with the selected polarity. The
trigger selection is effective once software has set bit ADSTART = 1.
Any hardware triggers which occur while a conversion is ongoing are ignored.
If bit ADSTART = 0, any hardware triggers which occur are ignored.
Table 92 provides the correspondence between the EXTEN[1:0] values and the trigger
polarity.
Table 92. Configuring the trigger polarity
Source
EXTEN[1:0]
Trigger detection disabled
00
Detection on rising edge
01
Detection on falling edge
10
Detection on both rising and falling edges
11
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Analog-to-digital converter (ADC)
Note:
RM0461
The polarity of the external trigger can be changed only when the ADC is not converting
(ADSTART = 0).
The EXTSEL[2:0] control bits are used to select which of 8 possible events can trigger
conversions.
Refer to Table 90: External triggers in Section 16.3.1: ADC pins and internal signals for the
list of all the external triggers that can be used for regular conversion.
The software source trigger events can be generated by setting the ADSTART bit in the
ADC_CR register.
Note:
The trigger selection can be changed only when the ADC is not converting (ADSTART = 0).
16.4.1
Discontinuous mode (DISCEN)
This mode is enabled by setting the DISCEN bit in the ADC_CFGR1 register.
In this mode (DISCEN = 1), a hardware or software trigger event is required to start each
conversion defined in the sequence. On the contrary, if DISCEN = 0, a single hardware or
software trigger event successively starts all the conversions defined in the sequence.
Example:
•
•
DISCEN = 1, channels to be converted = 0, 3, 7, 10
–
1st trigger: channel 0 is converted and an EOC event is generated
–
2nd trigger: channel 3 is converted and an EOC event is generated
–
3rd trigger: channel 7 is converted and an EOC event is generated
–
4th trigger: channel 10 is converted and both EOC and EOS events are
generated.
–
5th trigger: channel 0 is converted an EOC event is generated
–
6th trigger: channel 3 is converted and an EOC event is generated
–
...
DISCEN = 0, channels to be converted = 0, 3, 7, 10
–
1st trigger: the complete sequence is converted: channel 0, then 3, 7 and 10. Each
conversion generates an EOC event and the last one also generates an EOS
event.
–
Any subsequent trigger events restarts the complete sequence.
Note:
It is not possible to have both discontinuous mode and continuous mode enabled: it is
forbidden to set both bits DISCEN = 1 and CONT = 1.
16.4.2
Programmable resolution (RES) - Fast conversion mode
It is possible to obtain faster conversion times (tSAR) by reducing the ADC resolution.
The resolution can be configured to be either 12, 10, 8, or 6 bits by programming the
RES[1:0] bits in the ADC_CFGR1 register. Lower resolution allows faster conversion times
for applications where high data precision is not required.
Note:
The RES[1:0] bit must only be changed when the ADEN bit is reset.
The result of the conversion is always 12 bits wide and any unused LSB bits are read as
zeros.
436/1290
RM0461 Rev 10
RM0461
Analog-to-digital converter (ADC)
Lower resolution reduces the conversion time needed for the successive approximation
steps as shown in Table 93.
Table 93. tSAR timings depending on resolution
RES[1:0]
(bits)
16.4.3
tSAR at
tSMPL(min)
fADC = 35 MHz
(fADC cycles)
(fADC cycles)
(ns)
tSAR
tCONV(min) at
tCONV with min. tSMPL
fADC = 35 MHz
(fADC cycles)
(ns)
12
12.5
357
1.5
14
400
10
10.5
300
1.5
12
343
8
8.5
243
1.5
10
286
6
6.5
186
1.5
8
229
End of conversion, end of sampling phase (EOC, EOSMP flags)
The ADC indicates each end of conversion (EOC) event.
The ADC sets the EOC flag in the ADC_ISR register as soon as a new conversion data
result is available in the ADC_DR register. An interrupt can be generated if the EOCIE bit is
set in the ADC_IER register. The EOC flag is cleared by software either by writing 1 to it, or
by reading the ADC_DR register.
The ADC also indicates the end of sampling phase by setting the EOSMP flag in the
ADC_ISR register. The EOSMP flag is cleared by software by writing1 to it. An interrupt can
be generated if the EOSMPIE bit is set in the ADC_IER register.
The aim of this interrupt is to allow the processing to be synchronized with the conversions.
Typically, an analog multiplexer can be accessed in hidden time during the conversion
phase, so that the multiplexer is positioned when the next sampling starts.
Note:
As there is only a very short time left between the end of the sampling and the end of the
conversion, it is recommenced to use polling or a WFE instruction rather than an interrupt
and a WFI instruction.
16.4.4
End of conversion sequence (EOS flag)
The ADC notifies the application of each end of sequence (EOS) event.
The ADC sets the EOS flag in the ADC_ISR register as soon as the last data result of a
conversion sequence is available in the ADC_DR register. An interrupt can be generated if
the EOSIE bit is set in the ADC_IER register. The EOS flag is cleared by software by writing
1 to it.
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16.4.5
RM0461
Example timing diagrams (single/continuous modes
hardware/software triggers)
Figure 53. Single conversions of a sequence, software trigger
ADSTART(1)
EOC
EOS
SCANDIR
ADC state(2)
RDY
CH0
ADC_DR
by S/W
CH9
CH10 CH17
D0
D9
RDY
D17
D10
CH17 CH10 CH9
CH0
RDY
D17
D9
D0
D10
by H/W
MSv30338V3
1. EXTEN = 00, CONT = 0
2. CHSEL = 0x20601, WAIT = 0, AUTOFF = 0
Figure 54. Continuous conversion of a sequence, software trigger
ADSTART(1)
EOC
EOS
ADSTP
SCANDIR
ADC state(2)
RDY
ADC_DR
by S/W
CH0
CH9
CH10 CH17
CH0
CH9
D0
D9
D17
D0
D10
RDY
CH10 STP
D9
CH17
CH10
D17
by H/W
MSv30339V2
1. EXTEN = 00, CONT = 1,
2. CHSEL = 0x20601, WAIT = 0, AUTOFF = 0
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RM0461
Analog-to-digital converter (ADC)
Figure 55. Single conversions of a sequence, hardware trigger
ADSTART(1)
EOC
EOS
TRGx(1)
ADC state(2)
RDY
CH0
CH1
CH2
CH3
RDY CH0
CH1
CH2
CH3
RDY
D0
D1
D2
D3
D0
D1
D2
D3
ADC_DR
by S/W
by H/W
triggered
ignored
MSv30340V2
1. EXTSEL = TRGx (over-frequency), EXTEN = 01 (rising edge), CONT = 0
2. CHSEL = 0xF, SCANDIR = 0, WAIT = 0, AUTOFF = 0
Figure 56. Continuous conversions of a sequence, hardware trigger
ADSTART(1)
EOC
EOS
ADSTP
TRGx(1)
ADC state(2)
RDY
ADC_DR
by S/W
by H/W
triggered
ignored
CH0
CH1
CH2
CH3
CH0
CH1
CH2
CH3
CH0 STOP
D0
D1
D2
D3
D0
D1
D2
D3
RDY
MSv30341V2
1. EXTSEL = TRGx, EXTEN = 10 (falling edge), CONT = 1
2. CHSEL = 0xF, SCANDIR = 0, WAIT = 0, AUTOFF = 0
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16.4.6
RM0461
Low frequency trigger mode
Once the ADC is enabled or the last ADC conversion is complete, the ADC is ready to start
a new conversion. The ADC needs to be started at a predefined time (tidle) otherwise ADC
converted data might be corrupted due to the transistor leakage (refer to the device
datasheet for the maximum value of tidle).
If the application has to support a time longer than the maximum tidle value (between one
trigger to another for single conversion mode or between the ADC enable and the first ADC
conversion), then the ADC internal state needs to be rearmed. This mechanism can be
enabled by setting LFTRIG bit to 1 in ADC_CFGR2 register. By setting this bit, any trigger
(software or hardware) sends a rearm command to ADC. The conversion starts after a one
ADC clock cycle delay compared to LFTRIG cleared.
It is not necessary to use this mode when AUTOFF bit is set. For Wait mode, only the first
trigger generates an internal rearm command.
16.5
Data management
16.5.1
Data register and data alignment (ADC_DR, ALIGN)
At the end of each conversion (when an EOC event occurs), the result of the converted data
is stored in the ADC_DR data register which is 16-bit wide.
The format of the ADC_DR depends on the configured data alignment and resolution.
The ALIGN bit in the ADC_CFGR1 register selects the alignment of the data stored after
conversion. Data can be right-aligned (ALIGN = 0) or left-aligned (ALIGN = 1) as shown in
Figure 57.
Figure 57. Data alignment and resolution (oversampling disabled: OVSE = 0)
ALIGN RES
0
0x0
0x1
0x2
15
14
13
12
11
9
8
0x0
7
6
5
4
3
2
1
0
DR[11:0]
0x00
DR[9:0]
0x00
DR[7:0]
0x00
0x3
1
10
DR[5:0]
DR[11:0]
0x0
0x0
0x00
DR[9:0]
0x1
0x2
DR[7:0]
0x3
0x00
0x00
DR[5:0]
0x0
MS30342V1
16.5.2
ADC overrun (OVR, OVRMOD)
The overrun flag (OVR) indicates a data overrun event, when the converted data was not
read in time by the CPU or the DMA, before the data from a new conversion is available.
The OVR flag is set in the ADC_ISR register if the EOC flag is still at ‘1’ at the time when a
new conversion completes. An interrupt can be generated if the OVRIE bit is set in the
ADC_IER register.
440/1290
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RM0461
Analog-to-digital converter (ADC)
When an overrun condition occurs, the ADC keeps operating and can continue to convert
unless the software decides to stop and reset the sequence by setting the ADSTP bit in the
ADC_CR register.
The OVR flag is cleared by software by writing 1 to it.
It is possible to configure if the data is preserved or overwritten when an overrun event
occurs by programming the OVRMOD bit in the ADC_CFGR1 register:
•
OVRMOD = 0
–
•
An overrun event preserves the data register from being overwritten: the old data
is maintained and the new conversion is discarded. If OVR remains at 1, further
conversions can be performed but the resulting data is discarded.
OVRMOD = 1
–
The data register is overwritten with the last conversion result and the previous
unread data is lost. If OVR remains at 1, further conversions can be performed
and the ADC_DR register always contains the data from the latest conversion.
Figure 58. Example of overrun (OVR)
ADSTART(1)
EOC
EOS
OVR
ADSTP
TRGx(1)
ADC state(2)
RDY
CH0
CH1
CH2
CH0
CH1
CH0 STOP
RDY
OVERRUN
ADC_DR read
access
ADC_DR
(OVRMOD=0)
D0
D1
D2
D0
ADC_DR
(OVRMOD=1)
D0
D1
D2
D0
by S/W
CH2
D1
D2
by H/W
triggered
MSv30343V3
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Analog-to-digital converter (ADC)
16.5.3
RM0461
Managing a sequence of data converted without using the DMA
If the conversions are slow enough, the conversion sequence can be handled by software.
In this case the software must use the EOC flag and its associated interrupt to handle each
data result. Each time a conversion is complete, the EOC bit is set in the ADC_ISR register
and the ADC_DR register can be read. The OVRMOD bit in the ADC_CFGR1 register
should be configured to 0 to manage overrun events as an error.
16.5.4
Managing converted data without using the DMA without overrun
It may be useful to let the ADC convert one or more channels without reading the data after
each conversion. In this case, the OVRMOD bit must be configured at 1 and the OVR flag
should be ignored by the software. When OVRMOD = 1, an overrun event does not prevent
the ADC from continuing to convert and the ADC_DR register always contains the latest
conversion data.
16.5.5
Managing converted data using the DMA
Since all converted channel values are stored in a single data register, it is efficient to use
DMA when converting more than one channel. This avoids losing the conversion data
results stored in the ADC_DR register.
When DMA mode is enabled (DMAEN bit set in the ADC_CFGR1 register), a DMA request
is generated after the conversion of each channel. This allows the transfer of the converted
data from the ADC_DR register to the destination location selected by the software.
Note:
The DMAEN bit in the ADC_CFGR1 register must be set after the ADC calibration phase.
Despite this, if an overrun occurs (OVR = 1) because the DMA could not serve the DMA
transfer request in time, the ADC stops generating DMA requests and the data
corresponding to the new conversion is not transferred by the DMA. Which means that all
the data transferred to the RAM can be considered as valid.
Depending on the configuration of OVRMOD bit, the data is either preserved or overwritten
(refer to Section 16.5.2: ADC overrun (OVR, OVRMOD) on page 440).
The DMA transfer requests are blocked until the software clears the OVR bit.
Two different DMA modes are proposed depending on the application use and are
configured with bit DMACFG in the ADC_CFGR1 register:
•
DMA one shot mode (DMACFG = 0).
This mode should be selected when the DMA is programmed to transfer a fixed
number of data words.
•
DMA circular mode (DMACFG = 1)
This mode should be selected when programming the DMA in circular mode or double
buffer mode.
DMA one shot mode (DMACFG = 0)
In this mode, the ADC generates a DMA transfer request each time a new conversion data
word is available and stops generating DMA requests once the DMA has reached the last
DMA transfer (when a transfer complete interrupt occurs, see Section 11: Direct memory
access controller (DMA) on page 352) even if a conversion has been started again.
442/1290
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RM0461
Analog-to-digital converter (ADC)
When the DMA transfer is complete (all the transfers configured in the DMA controller have
been done):
•
The content of the ADC data register is frozen.
•
Any ongoing conversion is aborted and its partial result discarded
•
No new DMA request is issued to the DMA controller. This avoids generating an
overrun error if there are still conversions which are started.
•
The scan sequence is stopped and reset
•
The DMA is stopped
DMA circular mode (DMACFG = 1)
In this mode, the ADC generates a DMA transfer request each time a new conversion data
word is available in the data register, even if the DMA has reached the last DMA transfer.
This allows the DMA to be configured in circular mode to handle a continuous analog input
data stream.
16.6
Low-power features
16.6.1
Wait mode conversion
Wait mode conversion can be used to simplify the software as well as optimizing the
performance of applications clocked at low frequency where there might be a risk of ADC
overrun occurring.
When the WAIT bit is set in the ADC_CFGR1 register, a new conversion can start only if the
previous data has been treated, once the ADC_DR register has been read or if the EOC bit
has been cleared.
This is a way to automatically adapt the speed of the ADC to the speed of the system that
reads the data.
Note:
Any hardware triggers which occur while a conversion is ongoing or during the wait time
preceding the read access are ignored.
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RM0461
Figure 59. Wait mode conversion (continuous mode, software trigger)
ADSTART
EOC
EOS
ADSTP
ADC_DR Read access
ADC state
RDY
ADC_DR
by S/W
CH1
CH2
DLY
DLY CH3
D2
D1
DLY
D3
CH1
DLY
STOP
RDY
D1
by H/W
MSv30344V2
1. EXTEN = 00, CONT = 1
2. CHSEL = 0x3, SCANDIR = 0, WAIT = 1, AUTOFF = 0
16.6.2
Auto-off mode (AUTOFF)
The ADC has an automatic power management feature which is called auto-off mode, and
is enabled by setting AUTOFF = 1 in the ADC_CFGR1 register.
When AUTOFF = 1, the ADC is always powered off when not converting and automatically
wakes-up when a conversion is started (by software or hardware trigger). A startup-time is
automatically inserted between the trigger event which starts the conversion and the
sampling time of the ADC. The ADC is then automatically disabled once the sequence of
conversions is complete.
Auto-off mode can cause a dramatic reduction in the power consumption of applications
which need relatively few conversions or when conversion requests are timed far enough
apart (for example with a low frequency hardware trigger) to justify the extra power and
extra time used for switching the ADC on and off.
Auto-off mode can be combined with the wait mode conversion (WAIT = 1) for applications
clocked at low frequency. This combination can provide significant power savings if the ADC
is automatically powered-off during the wait phase and restarted as soon as the ADC_DR
register is read by the application (see Figure 61: Behavior with WAIT = 1, AUTOFF = 1).
Note:
444/1290
Refer to the Section Reset and clock control (RCC) for the description of how to manage
the dedicated 14 MHz internal oscillator. The ADC interface can automatically switch
ON/OFF the 14 MHz internal oscillator to save power.
RM0461 Rev 10
RM0461
Analog-to-digital converter (ADC)
Figure 60. Behavior with WAIT = 0, AUTOFF = 1
TRGx
EOC
EOS
ADC_DR Read
access
RDY Startup
ADC state
CH1
CH2
CH3
CH4
D1
D2
D3
ADC_DR
by S/W
OFF
Startup
D4
by H/W
triggered
MSv30345V2
1. EXTSEL = TRGx, EXTEN = 01 (rising edge), CONT = x, ADSTART = 1, CHSEL = 0xF, SCANDIR = 0, WAIT = 1,
AUTOFF = 1
Figure 61. Behavior with WAIT = 1, AUTOFF = 1
TRGx
EOC
EOS
Startup
CH1
DLY
DLY
DLY
Startup CH2
D1
ADC_DR
by S/W
OFF
Startup
D2
CH3
OFF
Startup
CH1
OFF
ADC state
DLY
RDY
OFF
ADC_DR Read
access
D3
CH2
D4
by H/W
triggered
MSv30346V2
1. EXTSEL = TRGx, EXTEN = 01 (rising edge), CONT = x, ADSTART = 1, CHSEL = 0xF, SCANDIR = 0, WAIT = 1,
AUTOFF = 1
16.7
Analog window watchdogs
The three AWD analog watchdogs monitor whether some channels remain within a
configured voltage range (window).
RM0461 Rev 10
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Analog-to-digital converter (ADC)
16.7.1
RM0461
Description of analog watchdog 1
AWD1 analog watchdog is enabled by setting the AWD1EN bit in the ADC_CFGR1 register.
It is used to monitor that either one selected channel or all enabled channels (see Table 95:
Analog watchdog 1 channel selection) remain within a configured voltage range (window) as
shown in Figure 62.
The AWD1 analog watchdog status bit is set if the analog voltage converted by the ADC is
below a lower threshold or above a higher threshold. These thresholds are programmed in
HT1[11:0] and LT1[11:0] bits of ADC_AWD1TR register. An interrupt can be enabled by
setting the AWD1IE bit in the ADC_IER register.
The AWD1 flag is cleared by software by programing it to 1.
When converting data with a resolution of less than 12-bit (according to bits DRES[1:0]), the
LSB of the programmed thresholds must be kept cleared because the internal comparison
is always performed on the full 12-bit raw converted data (left aligned).
Table 94 describes how the comparison is performed for all the possible resolutions.
Table 94. Analog watchdog comparison
Resolution
Analog Watchdog comparison between:
bits
RES[1:0]
Raw converted
data, left aligned(1)
Thresholds
00: 12-bit
DATA[11:0]
LTx[11:0] and HTx[11:0] -
01: 10-bit
DATA[11:2],00
LTx[11:0] and HTx[11:0] The user must configure LTx[1:0] and HTx[1:0] to “00”
10: 8-bit
DATA[11:4],0000
LTx[11:0] and HTx[11:0]
The user must configure LTx[3:0] and HTx[3:0] to
“0000”
11: 6-bit
DATA[11:6],000000 LTx[11:0] and HTx[11:0]
The user must configure LTx[5:0] and HTx[5:0] to
“000000”
Comments
1. The watchdog comparison is performed on the raw converted data before any alignment calculation.
Table 95 shows how to configure the AWD1SGL and AWD1EN bits in the ADC_CFGR1
register to enable the analog watchdog on one or more channels.
Figure 62. Analog watchdog guarded area
Analog voltage
Higher threshold
HTx
Guarded area
Lower threshold
LTx
MS45396V1
Table 95. Analog watchdog 1 channel selection
Channels guarded by the analog watchdog
None
446/1290
RM0461 Rev 10
AWD1SGL bit
AWD1EN bit
x
0
RM0461
Analog-to-digital converter (ADC)
Table 95. Analog watchdog 1 channel selection (continued)
Channels guarded by the analog watchdog
AWD1SGL bit
AWD1EN bit
All channels
0
1
Single(1) channel
1
1
1. Selected by the AWD1CH[4:0] bits
16.7.2
Description of analog watchdog 2 and 3
The second and third analog watchdogs are more flexible and can guard several selected
channels by programming the AWDxCHy in ADC_AWDxCR (x = 2, 3).
The corresponding watchdog is enabled when any AWDxCHy bit (x = 2,3) is set in
ADC_AWDxCR register.
When converting data with a resolution of less than 12 bits (configured through DRES[1:0]
bits), the LSB of the programmed thresholds must be kept cleared because the internal
comparison is always performed on the full 12-bit raw converted data (left aligned).
Table 94 describes how the comparison is performed for all the possible resolutions.
The AWD2/3 analog watchdog status bit is set if the analog voltage converted by the ADC is
below a low threshold or above a high threshold. These thresholds are programmed in
HTx[11:0] and LTx[11:0] of ADC_AWDxTR registers (x = 2 or 3). An interrupt can be
enabled by setting the AWDxIE bit in the ADC_IER register.
The AWD2 and ADW3 flags are cleared by software by programming them to 1.
16.7.3
ADC_AWDx_OUT output signal generation
Each analog watchdog is associated to an internal hardware signal, ADC_AWDx_OUT (x
being the watchdog number) that is directly connected to the ETR input (external trigger) of
some on-chip timers (refer to the timers section for details on how to select the
ADC_AWDx_OUT signal as ETR).
ADC_AWDx_OUT is activated when the associated analog watchdog is enabled:
•
ADC_AWDx_OUT is set when a guarded conversion is outside the programmed
thresholds.
•
ADC_AWDx_OUT is reset after the end of the next guarded conversion which is inside
the programmed thresholds. It remains at 1 if the next guarded conversions are still
outside the programmed thresholds.
•
ADC_AWDx_OUT is also reset when disabling the ADC (when setting ADDIS to 1).
Note that stopping conversions (ADSTP set), might clear the ADC_AWDx_OUT state.
•
ADC_AWDx_OUT state does not change when the ADC converts the none-guarded
channel (see Figure 65)
AWDx flag is set by hardware and reset by software: AWDx flag has no influence on the
generation of ADC_AWDx_OUT (as an example, ADC_AWDx_OUT can toggle while AWDx
flag remains at 1 if the software has not cleared the flag).
The ADC_AWDx_OUT signal is generated by the fADC clock domain. This signal can be
generated even the APB clock is stopped.
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Analog-to-digital converter (ADC)
RM0461
The AWD comparison is performed at the end of each ADC conversion. The
ADC_AWDx_OUT rising edge and falling edge occurs two fADC clock cycles after the
comparison.
As ADC_AWDx_OUT is generated by the fADC clock domain and AWD flag is generated by
the APB clock domain, the rising edges of these signals are not synchronized.
Figure 63. ADC_AWDx_OUT signal generation
ADC STATE
RDY
Conversion1
Conversion2
Conversion3
Conversion4
Conversion5
Conversion6
Conversion7
inside
outside
inside
outside
outside
outside
inside
Cleared
by SW
Cleared
by SW
Cleared
by SW
EOC FLAG
Cleared
by SW
AWDx FLAG
ADC_AWDx_OUT
- Converted channels: 1,2,3,4,5,6,7
- Guarded converted channels: 1,2,3,4,5,6,7
MSv45362V1
Figure 64. ADC_AWDx_OUT signal generation (AWDx flag not cleared by software)
ADC STATE RDY
Conversion1
Conversion2
Conversion3
inside
outside
inside
Conversion4
Conversion5
Conversion6
Conversion7
outside
outside
outside
inside
EOC FLAG
not cleared by SW
AWDx FLAG
ADC_AWDx_OUT
- Converted channels: 1,2,3,4,5,6,7
- Guarded converted channels: 1,2,3,4,5,6,7
MSv45363V1
448/1290
RM0461 Rev 10
RM0461
Analog-to-digital converter (ADC)
Figure 65. ADC_AWDx_OUT signal generation (on a single channel)
ADC STATE
Conversion1
Conversion2
outside
Conversion1
Conversion2
inside
Conversion1
Conversion2
Conversion1
outside
Conversion2
outside
EOC FLAG
EOS FLAG
Cleared
by SW
Cleared
by SW
AWDx FLAG
ADC_AWDx_OUT
- Converted channels: 1 and 2
- Only channel 1 is guarded
MSv45364V2
16.7.4
Analog watchdog threshold control
LTx[11:0] and HTx[11:0] can be changed during an analog-to-digital conversion (that is
between the start of the conversion and the end of conversion of the ADC internal state). If
HTx and LTx bits are programmed during the ADC guarded channel conversion, the
watchdog function is masked for this conversion. This mask is cleared when starting a new
conversion, and the resulting new AWD threshold is applied starting the next ADC
conversion result. AWD comparison is performed at each end of conversion. If the current
ADC data are out of the new threshold interval, this does not generated any interrupt or an
ADC_AWDx_OUT signal. The Interrupt and the ADC_AWDx_OUT generation only occurs
at the end of the ADC conversion that started after the threshold update. If
ADC_AWDx_OUT is already asserted, programming the new threshold does not deassert
the ADC_AWDx_OUT signal.
Figure 66. Analog watchdog threshold update
ADC state
Conversion
Conversion
Conversion
Conversion
Threshold updated
LTx, HTx
Comparison
XXXX
XXXY
Active
XXXZ
Masked
Active
MSv45365V1
RM0461 Rev 10
449/1290
477
Analog-to-digital converter (ADC)
16.8
RM0461
Oversampler
The oversampling unit performs data preprocessing to offload the CPU. It can handle
multiple conversions and average them into a single data with increased data width, up to
16-bit.
It provides a result with the following form, where N and M can be adjusted:
1
Result = ----- ×
M
n = N–1
∑ Conversion ( tn )
n=0
It allows the following functions to be performed by hardware: averaging, data rate
reduction, SNR improvement, basic filtering.
The oversampling ratio N is defined using the OVSR[2:0] bits in the ADC_CFGR2 register. It
can range from 2x to 256x. The division coefficient M consists of a right bit shift up to 8 bits.
It is configured through the OVSS[3:0] bits in the ADC_CFGR2 register.
The summation unit can yield a result up to 20 bits (256 x 12-bit), which is first shifted right.
The upper bits of the result are then truncated, keeping only the 16 least significant bits
rounded to the nearest value using the least significant bits left apart by the shifting, before
being finally transferred into the ADC_DR data register.
Note:
If the intermediate result after the shifting exceeds 16 bits, the upper bits of the result are
simply truncated.
Figure 67. 20-bit to 16-bit result truncation
19
15
11
7
3
0
Raw 20-bit data
Shifting
15
0
Truncation
and rounding
MS31928V2
Figure 68 gives a numerical example of the processing, from a raw 20-bit accumulated data
to the final 16-bit result.
Figure 68. Numerical example with 5-bit shift and rounding
19
Raw 20-bit data:
15
3
11
7
3
B
7
D
7
1
D
B
F
15
Final result after 5-bits shift
and rounding to nearest
0
MS31929V1
450/1290
RM0461 Rev 10
RM0461
Analog-to-digital converter (ADC)
Table 96 gives the data format for the various N and M combination, for a raw conversion
data equal to 0xFFF.
Table 96. Maximum output results vs N and M. Grayed values indicates truncation
No-shift
Oversa
Max
mpling
OVSS =
Raw data
ratio
0000
1-bit
shift
2-bit
shift
3-bit
shift
4-bit
shift
5-bit
shift
6-bit
shift
7-bit
shift
8-bit
shift
OVSS =
0001
OVSS =
0010
OVSS =
0011
OVSS =
0100
OVSS =
0101
OVSS =
0110
OVSS = OVSS =
0111
1000
2x
0x1FFE
0x1FFE
0x0FFF
0x0800
0x0400
0x0200
0x0100
0x0080
0x0040
0x0020
4x
0x3FFC
0x3FFC
0x1FFE
0x0FFF
0x0800
0x0400
0x0200
0x0100
0x0080
0x0040
8x
0x7FF8
0x7FF8
0x3FFC
0x1FFE
0x0FFF
0x0800
0x0400
0x0200
0x0100
0x0080
16x
0xFFF0
0xFFF0
0x7FF8
0x3FFC
0x1FFE
0x0FFF
0x0800
0x0400
0x0200
0x0100
32x
0x1FFE0
0xFFE0
0xFFF0
0x7FF8
0x3FFC
0x1FFE
0x0FFF
0x0800
0x0400
0x0200
64x
0x3FFC0
0xFFC0
0xFFE0
0xFFF0
0x7FF8
0x3FFC
0x1FFE
0x0FFF
0x0800
0x0400
128x
0x7FF80
0xFF80
0xFFC0
0xFFE0
0xFFF0
0x7FF8
0x3FFC
0x1FFE
0x0FFF
0x0800
256x
0xFFF00
0xFF00
0xFF80
0xFFC0
0xFFE0
0xFFF0
0x7FF8
0x3FFC
0x1FFE
0x0FFF
The conversion timings in oversampled mode do not change compared to standard
conversion mode: the sample time is maintained equal during the whole oversampling
sequence. New data are provided every N conversion, with an equivalent delay equal to N x
tCONV = N x (tSMPL + tSAR). The flags features are raised as following:
16.8.1
•
the end of the sampling phase (EOSMP) is set after each sampling phase
•
the end of conversion (EOC) occurs once every N conversions, when the oversampled
result is available
•
the end of sequence (EOCSEQ) occurs once the sequence of oversampled data is
completed (i.e. after N x sequence length conversions total)
ADC operating modes supported when oversampling
In oversampling mode, most of the ADC operating modes are available:
Note:
•
Single or continuous mode conversions, forward or backward scanned sequences and
up to 8 channels programmed sequence
•
ADC conversions start either by software or with triggers
•
ADC stop during a conversion (abort)
•
Data read via CPU or DMA with overrun detection
•
Low-power modes (WAIT, AUTOFF)
•
Programmable resolution: in this case, the reduced conversion values (as per RES[1:0]
bits in ADC_CFGR1 register) are accumulated, truncated, rounded and shifted in the
same way as 12-bit conversions are
The alignment mode is not available when working with oversampled data. The ALIGN bit in
ADC_CFGR1 is ignored and the data are always provided right-aligned.
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Analog-to-digital converter (ADC)
16.8.2
RM0461
Analog watchdog
The analog watchdog functionality is available, with the following differences:
•
the RES[1:0] bits are ignored, comparison is always done on using the full 12-bits
values HTx[11:0] and LTx[11:0]
•
the comparison is performed on the most significant 12 bits of the 16 bits oversampled
results ADC_DR[15:4]
Note:
Care must be taken when using high shifting values. This reduces the comparison range.
For instance, if the oversampled result is shifted by 4 bits thus yielding a 12-bit data rightaligned, the affective analog watchdog comparison can only be performed on 8 bits. The
comparison is done between ADC_DR[11:4] and HTx[7:0] / LTx[[7:0], and HTx[11:8] /
LTx[11:8] must be kept reset.
16.8.3
Triggered mode
The averager can also be used for basic filtering purposes. Although not a very efficient filter
(slow roll-off and limited stop band attenuation), it can be used as a notch filter to reject
constant parasitic frequencies (typically coming from the mains or from a switched mode
power supply). For this purpose, a specific discontinuous mode can be enabled with TOVS
bit in ADC_CFGR2, to be able to have an oversampling frequency defined by a user and
independent from the conversion time itself.
Figure 69 below shows how conversions are started in response to triggers in discontinuous
mode.
If the TOVS bit is set, the content of the DISCEN bit is ignored and considered as 1.
Figure 69. Triggered oversampling mode (TOVS bit = 1)
Trigger
CONT = 0
(DISCEN = 1)*
TOVS = 0
Trigger
Ch(N) Ch(N) Ch(N) Ch(N)
0
1
2
3
Ch(N) Ch(N) Ch(N) Ch(N)
0
1
2
3
EOC flag set
Trigger Trigger Trigger
CONT = 0
(DISCEN = 1)*
TOVS = 1
Ch(N)
0
Ch(N)
1
Ch(N)
2
Trigger Trigger Trigger Trigger
Ch(N)
3
Ch(N)
0
Ch(N)
1
Ch(N)
2
EOC flag set
(DISCEN = 1)*: DISCEN bit is forced to 1 by software when TOVS bit is set
MS33700V1
16.9
Temperature sensor and internal reference voltage
The temperature sensor can be used to measure the junction temperature (TJ) of the
device. The temperature sensor is internally connected to the ADC VIN[12] input channel
which is used to convert the sensor’s output voltage to a digital value. The sampling time for
the temperature sensor analog pin must be greater than the minimum TS_temp value
specified in the datasheet. When not in use, the sensor can be put in power down mode.
452/1290
RM0461 Rev 10
RM0461
Analog-to-digital converter (ADC)
The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the
ADC and comparators. VREFINT is internally connected to the ADC VIN[13] input channel.
The precise voltage of VREFINT is individually measured for each part by ST during
production test and stored in the system memory area.
Figure 70 shows the block diagram of connections between the temperature sensor, the
internal voltage reference and the ADC.
The TSEN bit must be set to enable the conversion of ADC VIN[12] (temperature sensor)
and the VREFEN bit must be set to enable the conversion of ADC VIN[13] (VREFINT).
The temperature sensor output voltage changes linearly with temperature. The offset of this
line varies from chip to chip due to process variation (up to 45 °C from one chip to another).
The uncalibrated internal temperature sensor is more suited for applications that detect
temperature variations instead of absolute temperatures. To improve the accuracy of the
temperature sensor measurement, calibration values are stored in system memory for each
device by ST during production.
During the manufacturing process, the calibration data of the temperature sensor and the
internal voltage reference are stored in the system memory area. The user application can
then read them and use them to improve the accuracy of the temperature sensor or the
internal reference. Refer to the datasheet for additional information.
Before entering any Stop mode, the temperature sensor and the internal reference voltage
must be disabled by clearing TSEN and VREFEN, respectively.
Main features
•
Linearity: ±2 °C max, precision depending on calibration
Figure 70. Temperature sensor and VREFINT channel block diagram
TSEN control bit
Temperature
sensor
+
VTS
ADC VIN[12]
converted data
VREFEN control bit
+
Internal power
block
ADC
VREFINT
ADC VIN[13]
Address/data bus
Note:
-
MSv45366V2
RM0461 Rev 10
453/1290
477
Analog-to-digital converter (ADC)
RM0461
Reading the temperature
1.
Select the ADC VIN[12] input channel.
2.
Select an appropriate sampling time specified in the device datasheet (TS_temp).
3.
Set the TSEN bit in the ADC_CCR register to wake up the temperature sensor from
power down mode and wait for its stabilization time (tSTART).
4.
Start the ADC conversion by setting the ADSTART bit in the ADC_CR register (or by
external trigger).
5.
Read the resulting VTS data in the ADC_DR register.
6.
Calculate the temperature using the following formula
TS_CAL2_TEMP – TS_CAL1_TEMP
Temperature ( in °C ) = ---------------------------------------------------------------------------------------------------- × ( TS_DATA – TS_CAL1 ) + TS_CAL1_TEMP
TS_CAL2 – TS_CAL1
Where:
•
TS_CAL2 is the temperature sensor calibration value acquired at TS_CAL2_TEMP
(refer to the datasheet for TS_CAL2 value)
•
TS_CAL1 is the temperature sensor calibration value acquired at TS_CAL1_TEMP
(refer to the datasheet for TS_CAL1 value)
•
TS_DATA is the actual temperature sensor output value converted by ADC
Refer to the specific device datasheet for more information about TS_CAL1 and
TS_CAL2 calibration points.
Note:
The sensor has a startup time after waking from power down mode before it can output VTS
at the correct level. The ADC also has a startup time after power-on, so to minimize the
delay, the ADEN and TSEN bits should be set at the same time.
Calculating the actual VREF+ voltage using the internal reference voltage
VREF+ voltage may be subject to variation or not precisely known. The embedded internal
reference voltage (VREFINT) and its calibration data acquired by the ADC during the
manufacturing process at VREF+_charac can be used to evaluate the actual VREF+ voltage
level.
The following formula gives the actual VREF+ voltage supplying the device:
V REF+ = V REF + _Charac × VREFINT_CAL ⁄ VREFINT_DATA
Where:
•
VREF+_Charac is the value of VREF+ voltage characterized at VREFINT during the
manufacturing process. It is specified in the device datasheet.
•
VREFINT_CAL is the VREFINT calibration value
•
VREFINT_DATA is the actual VREFINT output value converted by ADC
Converting a supply-relative ADC measurement to an absolute voltage value
The ADC is designed to deliver a digital value corresponding to the ratio between the analog
power supply and the voltage applied on the converted channel. For most application use
cases, it is necessary to convert this ratio into a voltage independent of VREF+. For
applications where VREF+ is known and ADC converted values are right-aligned you can
use the following formula to get this absolute value:
454/1290
RM0461 Rev 10
RM0461
Analog-to-digital converter (ADC)
V REF+
V CHANNELx = -------------------------------------- × ADC_DATA x
NUM_CODES
For applications where VREF+ value is not known, you must use the internal voltage
reference and VREF+ can be replaced by the expression provided in Calculating the actual
VREF+ voltage using the internal reference voltage, resulting in the following formula:
V REF+_Charac × VREFINT_CAL × ADC_DATA x
V CHANNELx = -----------------------------------------------------------------------------------------------------------------------------------VREFINT_DATA × NUM_CODES
Where:
•
VREF+_Charac is the value of VREF+ voltage characterized at VREFINT during the
manufacturing process. It is specified in the device datasheet.
•
VREFINT_CAL is the VREFINT calibration value
•
ADC_DATAx is the value measured by the ADC on channelx (right-aligned)
•
VREFINT_DATA is the actual VREFINT output value converted by the ADC
•
NUM_CODES is the number of ADC output codes. For example with 12-bit resolution,
it is 212 = 4096 or with 8-bit resolution, 28 = 256.
Note:
If ADC measurements are done using an output format other than 12 bit right-aligned, all the
parameters must first be converted to a compatible format before the calculation is done.
16.10
Battery voltage monitoring
The VBATEN bit in the ADC_CCR register allows the application to measure the backup
battery voltage on the VBAT pin. As the VBAT voltage can be higher than VREF+, to ensure
the correct operation of the ADC, the VBAT pin is internally connected to a bridge divider.
This bridge is automatically enabled when VBATEN is set, to connect VBAT to the ADC
VIN[14] input channel. As a consequence, the converted digital value is VBAT/3. To prevent
any unwanted consumption on the battery, it is recommended to enable the bridge divider
only when needed for ADC conversion.
Figure 71. VBAT channel block diagram
VBATEN control bit
ADC
VBAT/3
+
ADC VIN[14]
Address/data bus
VBAT
-
MSv69533V1
RM0461 Rev 10
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Analog-to-digital converter (ADC)
16.11
RM0461
ADC interrupts
An interrupt can be generated by any of the following events:
•
End Of Calibration (EOCAL flag)
•
ADC power-up, when the ADC is ready (ADRDY flag)
•
End of any conversion (EOC flag)
•
End of a sequence of conversions (EOS flag)
•
When an analog watchdog detection occurs (AWD1, AWD2, AWD3 flags)
•
When the Channel configuration is ready (CCRDY flag)
•
When the end of sampling phase occurs (EOSMP flag)
•
when a data overrun occurs (OVR flag)
Separate interrupt enable bits are available for flexibility.
Table 97. ADC interrupts
Interrupt event
Event flag
Enable control bit
End Of Calibration
EOCAL
EOCALIE
ADC ready
ADRDY
ADRDYIE
End of conversion
EOC
EOCIE
End of sequence of conversions
EOS
EOSIE
Analog watchdog 1 status bit is set
AWD1
AWD1IE
Analog watchdog 2 status bit is set
AWD2
AWD2IE
Analog watchdog 3 status bit is set
AWD3
AWD3IE
Channel Configuration Ready
CCRDY
CCRDYIE
End of sampling phase
EOSMP
EOSMPIE
OVR
OVRIE
Overrun
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Analog-to-digital converter (ADC)
16.12
ADC registers
Refer to Section 1.2 for a list of abbreviations used in register descriptions.
16.12.1
ADC interrupt and status register (ADC_ISR)
Address offset: 0x00
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
CCRD
Y
Res.
rc_w1
Res.
EOCAL
rc_w1
Res.
AWD3
AWD2
AWD1
rc_w1
rc_w1
rc_w1
Res.
Res.
OVR
EOS
EOC
EOSM
ADRDY
P
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
Bits 31:14 Reserved, must be kept at reset value.
Bit 13 CCRDY: Channel Configuration Ready flag
This flag bit is set by hardware when the channel configuration is applied after programming to
ADC_CHSELR register or changing CHSELRMOD or SCANDIR. It is cleared by software by
programming it to it.
0: Channel configuration update not applied.
1: Channel configuration update is applied.
Note: When the software configures the channels (by programming ADC_CHSELR or changing
CHSELRMOD or SCANDIR), it must wait until the CCRDY flag rises before configuring again
or starting conversions, otherwise the new configuration (or the START bit) is ignored. Once the
flag is asserted, if the software needs to configure again the channels, it must clear the CCRDY
flag before proceeding with a new configuration.
Bit 12 Reserved, must be kept at reset value.
Bit 11 EOCAL: End Of Calibration flag
This bit is set by hardware when calibration is complete. It is cleared by software writing 1 to it.
0: Calibration is not complete
1: Calibration is complete
Bit 10 Reserved, must be kept at reset value.
Bit 9 AWD3: Analog watchdog 3 flag
This bit is set by hardware when the converted voltage crosses the values programmed in
ADC_AWD3TR and ADC_AWD3TR registers. It is cleared by software by programming it to 1.
0: No analog watchdog event occurred (or the flag event was already acknowledged and cleared by
software)
1: Analog watchdog event occurred
Bit 8 AWD2: Analog watchdog 2 flag
This bit is set by hardware when the converted voltage crosses the values programmed in
ADC_AWD2TR and ADC_AWD2TR registers. It is cleared by software programming it it.
0: No analog watchdog event occurred (or the flag event was already acknowledged and cleared by
software)
1: Analog watchdog event occurred
RM0461 Rev 10
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RM0461
Bit 7 AWD1: Analog watchdog 1 flag
This bit is set by hardware when the converted voltage crosses the values programmed in ADC_TR1
and ADC_HR1 registers. It is cleared by software by programming it to 1.
0: No analog watchdog event occurred (or the flag event was already acknowledged and cleared by
software)
1: Analog watchdog event occurred
Bits 6:5 Reserved, must be kept at reset value.
Bit 4 OVR: ADC overrun
This bit is set by hardware when an overrun occurs, meaning that a new conversion has complete
while the EOC flag was already set. It is cleared by software writing 1 to it.
0: No overrun occurred (or the flag event was already acknowledged and cleared by software)
1: Overrun has occurred
Bit 3 EOS: End of sequence flag
This bit is set by hardware at the end of the conversion of a sequence of channels selected by the
CHSEL bits. It is cleared by software writing 1 to it.
0: Conversion sequence not complete (or the flag event was already acknowledged and cleared by
software)
1: Conversion sequence complete
Bit 2 EOC: End of conversion flag
This bit is set by hardware at the end of each conversion of a channel when a new data result is
available in the ADC_DR register. It is cleared by software writing 1 to it or by reading the ADC_DR
register.
0: Channel conversion not complete (or the flag event was already acknowledged and cleared by
software)
1: Channel conversion complete
Bit 1 EOSMP: End of sampling flag
This bit is set by hardware during the conversion, at the end of the sampling phase.It is cleared by
software by programming it to ‘1’.
0: Not at the end of the sampling phase (or the flag event was already acknowledged and cleared by
software)
1: End of sampling phase reached
Bit 0 ADRDY: ADC ready
This bit is set by hardware after the ADC has been enabled (ADEN = 1) and when the ADC reaches
a state where it is ready to accept conversion requests.
It is cleared by software writing 1 to it.
0: ADC not yet ready to start conversion (or the flag event was already acknowledged and cleared
by software)
1: ADC is ready to start conversion
16.12.2
ADC interrupt enable register (ADC_IER)
Address offset: 0x04
Reset value: 0x0000 0000
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31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
CCRD
YIE
Res.
EOCAL
IE
Res.
rw
rw
Res.
AWD3I AWD2I AWD1I
E
E
E
rw
rw
rw
Res.
Res.
OVRIE
EOSIE
EOCIE
rw
rw
rw
EOSM ADRDY
PIE
IE
rw
rw
Bits 31:14 Reserved, must be kept at reset value.
Bit 13 CCRDYIE: Channel Configuration Ready Interrupt enable
This bit is set and cleared by software to enable/disable the channel configuration ready interrupt.
0: Channel configuration ready interrupt disabled
1: Channel configuration ready interrupt enabled
Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no
conversion is ongoing).
Bit 12 Reserved, must be kept at reset value.
Bit 11 EOCALIE: End of calibration interrupt enable
This bit is set and cleared by software to enable/disable the end of calibration interrupt.
0: End of calibration interrupt disabled
1: End of calibration interrupt enabled
Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no
conversion is ongoing).
Bit 10 Reserved, must be kept at reset value.
Bit 9 AWD3IE: Analog watchdog 3 interrupt enable
This bit is set and cleared by software to enable/disable the analog watchdog interrupt.
0: Analog watchdog interrupt disabled
1: Analog watchdog interrupt enabled
Note: The Software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no
conversion is ongoing).
Bit 8 AWD2IE: Analog watchdog 2 interrupt enable
This bit is set and cleared by software to enable/disable the analog watchdog interrupt.
0: Analog watchdog interrupt disabled
1: Analog watchdog interrupt enabled
Note: The Software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no
conversion is ongoing).
Bit 7 AWD1IE: Analog watchdog 1 interrupt enable
This bit is set and cleared by software to enable/disable the analog watchdog interrupt.
0: Analog watchdog interrupt disabled
1: Analog watchdog interrupt enabled
Note: The Software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no
conversion is ongoing).
Bits 6:5 Reserved, must be kept at reset value.
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RM0461
Bit 4 OVRIE: Overrun interrupt enable
This bit is set and cleared by software to enable/disable the overrun interrupt.
0: Overrun interrupt disabled
1: Overrun interrupt enabled. An interrupt is generated when the OVR bit is set.
Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no
conversion is ongoing).
Bit 3 EOSIE: End of conversion sequence interrupt enable
This bit is set and cleared by software to enable/disable the end of sequence of conversions
interrupt.
0: EOS interrupt disabled
1: EOS interrupt enabled. An interrupt is generated when the EOS bit is set.
Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no
conversion is ongoing).
Bit 2 EOCIE: End of conversion interrupt enable
This bit is set and cleared by software to enable/disable the end of conversion interrupt.
0: EOC interrupt disabled
1: EOC interrupt enabled. An interrupt is generated when the EOC bit is set.
Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no
conversion is ongoing).
Bit 1 EOSMPIE: End of sampling flag interrupt enable
This bit is set and cleared by software to enable/disable the end of the sampling phase interrupt.
0: EOSMP interrupt disabled.
1: EOSMP interrupt enabled. An interrupt is generated when the EOSMP bit is set.
Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no
conversion is ongoing).
Bit 0 ADRDYIE: ADC ready interrupt enable
This bit is set and cleared by software to enable/disable the ADC Ready interrupt.
0: ADRDY interrupt disabled.
1: ADRDY interrupt enabled. An interrupt is generated when the ADRDY bit is set.
Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no
conversion is ongoing).
16.12.3
ADC control register (ADC_CR)
Address offset: 0x08
Reset value: 0x0000 0000
31
ADCAL
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
ADVRE
GEN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rs
rw
15
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
ADSTP
rs
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RM0461
Analog-to-digital converter (ADC)
Bit 31 ADCAL: ADC calibration
This bit is set by software to start the calibration of the ADC.
It is cleared by hardware after calibration is complete.
0: Calibration complete
1: Write 1 to calibrate the ADC. Read at 1 means that a calibration is in progress.
Note: The software is allowed to set ADCAL only when the ADC is disabled (ADCAL = 0,
ADSTART = 0, ADSTP = 0, ADDIS = 0, AUTOFF = 0, and ADEN = 0).
The software is allowed to update the calibration factor by writing ADC_CALFACT only when
ADEN = 1 and ADSTART = 0 (ADC enabled and no conversion is ongoing).
Bits 30:29 Reserved, must be kept at reset value.
Bit 28 ADVREGEN: ADC Voltage Regulator Enable
This bit is set by software, to enable the ADC internal voltage regulator. The voltage regulator output
is available after tADCVREG_STUP.
It is cleared by software to disable the voltage regulator. It can be cleared only if ADEN is cleared.
0: ADC voltage regulator disabled
1: ADC voltage regulator enabled
Note: The software is allowed to program this bit field only when the ADC is disabled (ADCAL = 0,
ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).
Bits 27:5 Reserved, must be kept at reset value.
Bit 4 ADSTP: ADC stop conversion command
This bit is set by software to stop and discard an ongoing conversion (ADSTP Command).
It is cleared by hardware when the conversion is effectively discarded and the ADC is ready to
accept a new start conversion command.
0: No ADC stop conversion command ongoing
1: Write 1 to stop the ADC. Read 1 means that an ADSTP command is in progress.
Note: Setting ADSTP to ‘1’ is only effective when ADSTART = 1 and ADDIS = 0 (ADC is enabled and
may be converting and there is no pending request to disable the ADC)
Bit 3 Reserved, must be kept at reset value.
Bit 2 ADSTART: ADC start conversion command
This bit is set by software to start ADC conversion. Depending on the EXTEN [1:0] configuration bits,
a conversion either starts immediately (software trigger configuration) or once a hardware trigger
event occurs (hardware trigger configuration).
It is cleared by hardware:
– In single conversion mode (CONT = 0, DISCEN = 0), when software trigger is selected
(EXTEN = 00): at the assertion of the end of Conversion Sequence (EOS) flag.
– In discontinuous conversion mode(CONT = 0, DISCEN = 1), when the software trigger is selected
(EXTEN = 00): at the assertion of the end of Conversion (EOC) flag.
– In all other cases: after the execution of the ADSTP command, at the same time as the ADSTP bit is
cleared by hardware.
0: No ADC conversion is ongoing.
1: Write 1 to start the ADC. Read 1 means that the ADC is operating and may be converting.
Note: The software is allowed to set ADSTART only when ADEN = 1 and ADDIS = 0 (ADC is enabled
and there is no pending request to disable the ADC).
After writing to ADC_CHSELR register or changing CHSELRMOD or SCANDIRW, it is
mandatory to wait until CCRDY flag is asserted before setting ADSTART, otherwise, the value
written to ADSTART is ignored.
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RM0461
Bit 1 ADDIS: ADC disable command
This bit is set by software to disable the ADC (ADDIS command) and put it into power-down state
(OFF state).
It is cleared by hardware once the ADC is effectively disabled (ADEN is also cleared by hardware at
this time).
0: No ADDIS command ongoing
1: Write 1 to disable the ADC. Read 1 means that an ADDIS command is in progress.
Note: Setting ADDIS to ‘1’ is only effective when ADEN = 1 and ADSTART = 0 (which ensures that no
conversion is ongoing)
Bit 0 ADEN: ADC enable command
This bit is set by software to enable the ADC. The ADC is effectively ready to operate once the
ADRDY flag has been set.
It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS command.
0: ADC is disabled (OFF state)
1: Write 1 to enable the ADC.
Note: The software is allowed to set ADEN only when ADCAL = 0, ADSTP = 0, ADSTART = 0,
ADDIS = 0, ADEN = 0, and ADVREGEN = 1.
16.12.4
ADC configuration register 1 (ADC_CFGR1)
Address offset: 0x0C
Reset value: 0x0000 0000
The software is allowed to program ADC_CFGR1 only when ADEN is cleared in ADC_CR.
31
30
29
Res.
28
27
26
AWD1CH[4:0]
15
rw
rw
14
Res.
rw
rw
rw
13
12
11
10
AUTOF
F
WAIT
CONT
OVRM
OD
rw
rw
rw
rw
25
EXTEN[1:0]
rw
rw
9
24
Res.
23
8
Res.
22
21
AWD1E AWD1S CHSEL
N
GL
RMOD
rw
rw
rw
7
6
5
EXTSEL[2:0]
rw
rw
ALIGN
rw
rw
20
Res.
19
Res.
18
Res.
17
16
Res.
DISCE
N
rw
4
3
RES[1:0]
rw
rw
2
1
SCAND DMAC
IR
FG
rw
rw
0
DMAE
N
rw
Bit 31 Reserved, must be kept at reset value.
Bits 30:26 AWD1CH[4:0]: Analog watchdog channel selection
These bits are set and cleared by software. They select the input channel to be guarded by
the analog watchdog.
00000: ADC analog input Channel 0 monitored by AWD
00001: ADC analog input Channel 1 monitored by AWD
.....
10001: ADC analog input Channel 17 monitored by AWD
Others: Reserved
Note: The channel selected by the AWDCH[4:0] bits must be also set into the CHSELR
register.
Bits 25:24 Reserved, must be kept at reset value.
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Analog-to-digital converter (ADC)
Bit 23 AWD1EN: Analog watchdog enable
This bit is set and cleared by software.
0: Analog watchdog 1 disabled
1: Analog watchdog 1 enabled
Bit 22 AWD1SGL: Enable the watchdog on a single channel or on all channels
This bit is set and cleared by software to enable the analog watchdog on the channel
identified by the AWDCH[4:0] bits or on all the channels
0: Analog watchdog 1 enabled on all channels
1: Analog watchdog 1 enabled on a single channel
Bit 21 CHSELRMOD: Mode selection of the ADC_CHSELR register
This bit is set and cleared by software to control the ADC_CHSELR feature:
0: Each bit of the ADC_CHSELR register enables an input
1: ADC_CHSELR register is able to sequence up to 8 channels
Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register
or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
Bits 20:17 Reserved, must be kept at reset value.
Bit 16 DISCEN: Discontinuous mode
This bit is set and cleared by software to enable/disable discontinuous mode.
0: Discontinuous mode disabled
1: Discontinuous mode enabled
Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is
forbidden to set both bits DISCEN = 1 and CONT = 1.
Bit 15 AUTOFF: Auto-off mode
This bit is set and cleared by software to enable/disable auto-off mode..
0: Auto-off mode disabled
1: Auto-off mode enabled
Bit 14 WAIT: Wait conversion mode
This bit is set and cleared by software to enable/disable wait conversion mode..
0: Wait conversion mode off
1: Wait conversion mode on
Bit 13 CONT: Single / continuous conversion mode
This bit is set and cleared by software. If it is set, conversion takes place continuously until it
is cleared.
0: Single conversion mode
1: Continuous conversion mode
Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is
forbidden to set both bits DISCEN = 1 and CONT = 1.
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RM0461
Bit 12 OVRMOD: Overrun management mode
This bit is set and cleared by software and configure the way data overruns are managed.
0: ADC_DR register is preserved with the old data when an overrun is detected.
1: ADC_DR register is overwritten with the last conversion result when an overrun is
detected.
Bits 11:10 EXTEN[1:0]: External trigger enable and polarity selection
These bits are set and cleared by software to select the external trigger polarity and enable
the trigger.
00: Hardware trigger detection disabled (conversions can be started by software)
01: Hardware trigger detection on the rising edge
10: Hardware trigger detection on the falling edge
11: Hardware trigger detection on both the rising and falling edges
Bit 9 Reserved, must be kept at reset value.
Bits 8:6 EXTSEL[2:0]: External trigger selection
These bits select the external event used to trigger the start of conversion (refer to Table 90:
External triggers for details):
000: TRG0
001: TRG1
010: TRG2
011: TRG3
100: TRG4
101: TRG5
110: TRG6
111: TRG7
Bit 5 ALIGN: Data alignment
This bit is set and cleared by software to select right or left alignment. Refer to Figure 57:
Data alignment and resolution (oversampling disabled: OVSE = 0) on page 440
0: Right alignment
1: Left alignment
Bits 4:3 RES[1:0]: Data resolution
These bits are written by software to select the resolution of the conversion.
00: 12 bits
01: 10 bits
10: 8 bits
11: 6 bits
Bit 2 SCANDIR: Scan sequence direction
This bit is set and cleared by software to select the direction in which the channels is scanned
in the sequence. It is effective only if CHSELMOD bit is cleared.
0: Upward scan (from CHSEL0 to CHSEL17)
1: Backward scan (from CHSEL17 to CHSEL0)
Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register
or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
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Analog-to-digital converter (ADC)
Bit 1 DMACFG: Direct memory access configuration
This bit is set and cleared by software to select between two DMA modes of operation and is
effective only when DMAEN = 1.
0: DMA one shot mode selected
1: DMA circular mode selected
For more details, refer to Section 16.5.5: Managing converted data using the DMA on
page 442.
Bit 0 DMAEN: Direct memory access enable
This bit is set and cleared by software to enable the generation of DMA requests. This allows
the DMA controller to be used to manage automatically the converted data. For more details,
refer to Section 16.5.5: Managing converted data using the DMA on page 442.
0: DMA disabled
1: DMA enabled
16.12.5
ADC configuration register 2 (ADC_CFGR2)
Address offset: 0x10
Reset value: 0x0000 0000
The software is allowed to program ADC_CFGR2 only when ADEN is cleared in ADC_CR.
31
30
CKMODE[1:0]
29
28
27
26
25
24
23
22
21
20
19
18
17
16
LFTRI
G
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
8
7
6
5
4
3
2
rw
rw
rw
15
14
13
12
11
10
9
Res.
Res.
Res.
Res.
Res.
Res.
TOVS
rw
OVSS[3:0]
rw
rw
rw
OVSR[2:0]
rw
rw
rw
rw
1
0
Res.
OVSE
rw
Bits 31:30 CKMODE[1:0]: ADC clock mode
These bits are set and cleared by software to define how the analog ADC is clocked:
00: ADCCLK (Asynchronous clock mode), generated at product level (refer to RCC section)
01: PCLK/2 (Synchronous clock mode)
10: PCLK/4 (Synchronous clock mode)
11: PCLK (Synchronous clock mode). This configuration must be enabled only if PCLK has a 50%
duty clock cycle (APB prescaler configured inside the RCC must be bypassed and the system clock
must by 50% duty cycle)
In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of a
conversion.
Note: The software is allowed to write these bits only when the ADC is disabled (ADCAL = 0,
ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).
Bit 29 LFTRIG: Low frequency trigger mode enable
This bit is set and cleared by software.
0: Low Frequency Trigger Mode disabled
1: Low Frequency Trigger Mode enabled
Note: The software is allowed to write this bit only when ADEN bit is cleared.
Bits 28:10
Reserved, must be kept at reset value.
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RM0461
Bit 9 TOVS: Triggered Oversampling
This bit is set and cleared by software.
0: All oversampled conversions for a channel are done consecutively after a trigger
1: Each oversampled conversion for a channel needs a trigger
Note: The software is allowed to write this bit only when ADEN bit is cleared.
Bits 8:5 OVSS[3:0]: Oversampling shift
This bit is set and cleared by software.
0000: No shift
0001: Shift 1-bit
0010: Shift 2-bits
0011: Shift 3-bits
0100: Shift 4-bits
0101: Shift 5-bits
0110: Shift 6-bits
0111: Shift 7-bits
1000: Shift 8-bits
Others: Reserved
Note: The software is allowed to write this bit only when ADEN bit is cleared.
Bits 4:2 OVSR[2:0]: Oversampling ratio
This bit filed defines the number of oversampling ratio.
000: 2x
001: 4x
010: 8x
011: 16x
100: 32x
101: 64x
110: 128x
111: 256x
Starting from 32x, it is mandatory to use OVSS[3:0] to reduce the data size to less than 16 bits to fit
to the ADC_DR register. For example, if OVSR[2:0] is configured to 32x, the data width is 17 bits,
and OVSS[3:0] must be set to 1-bit shift.
Note: The software is allowed to write this bit only when ADEN bit is cleared.
Bit 1
Reserved, must be kept at reset value.
Bit 0 OVSE: Oversampler Enable
This bit is set and cleared by software.
0: Oversampler disabled
1: Oversampler enabled
Note: The software is allowed to write this bit only when ADEN bit is cleared.
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Analog-to-digital converter (ADC)
16.12.6
ADC sampling time register (ADC_SMPR)
Address offset: 0x14
Reset value: 0x0000 0000
31
30
29
28
27
26
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
25
24
rw
rw
rw
rw
rw
22
21
20
19
18
17
16
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
9
8
7
6
5
4
3
2
1
0
SMPSE SMPSE SMPSE SMPSE SMPSE SMPSE SMPSE SMPSE
L7
L6
L5
L4
L3
L2
L1
L0
rw
23
SMPSE SMPSE SMPSE SMPSE SMPSE SMPSE SMPSE SMPSE SMPSE SMPSE
L17
L16
L15
L14
L13
L12
L11
L10
L9
L8
rw
Res.
rw
SMP2[2:0]
rw
rw
Res.
rw
SMP1[2:0]
rw
rw
rw
Bits 31:26 Reserved, must be kept at reset value.
Bits 25:8 SMPSELx: Channel-x sampling time selection (x = 17 to 0)
These bits are written by software to define which sampling time is used.
0: Sampling time of CHANNELx use the setting of SMP1[2:0] register.
1: Sampling time of CHANNELx use the setting of SMP2[2:0] register.
Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no
conversion is ongoing).
Bit 7 Reserved, must be kept at reset value.
Bits 6:4 SMP2[2:0]: Sampling time selection 2
These bits are written by software to select the sampling time that applies to all channels.
000: 1.5 ADC clock cycles
001: 3.5 ADC clock cycles
010: 7.5 ADC clock cycles
011: 12.5 ADC clock cycles
100: 19.5 ADC clock cycles
101: 39.5 ADC clock cycles
110: 79.5 ADC clock cycles
111: 160.5 ADC clock cycles
Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no
conversion is ongoing).
Bit 3 Reserved, must be kept at reset value.
Bits 2:0 SMP1[2:0]: Sampling time selection 1
These bits are written by software to select the sampling time that applies to all channels.
000: 1.5 ADC clock cycles
001: 3.5 ADC clock cycles
010: 7.5 ADC clock cycles
011: 12.5 ADC clock cycles
100: 19.5 ADC clock cycles
101: 39.5 ADC clock cycles
110: 79.5 ADC clock cycles
111: 160.5 ADC clock cycles
Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no
conversion is ongoing).
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16.12.7
RM0461
ADC watchdog threshold register (ADC_AWD1TR)
Address offset: 0x20
Reset value: 0x0FFF 0000
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
27
26
25
24
23
22
21
20
19
18
17
16
HT1[11:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
LT1[11:0]
rw
Bits 31:28 Reserved, must be kept at reset value.
Bits 27:16 HT1[11:0]: Analog watchdog 1 higher threshold
These bits are written by software to define the higher threshold for the analog watchdog.
Refer to Section 16.7: Analog window watchdogs on page 445.
Bits 15:12 Reserved, must be kept at reset value.
Bits 11:0 LT1[11:0]: Analog watchdog 1 lower threshold
These bits are written by software to define the lower threshold for the analog watchdog.
Refer to Section 16.7: Analog window watchdogs on page 445.
16.12.8
ADC watchdog threshold register (ADC_AWD2TR)
Address offset: 0x24
Reset value: 0x0FFF 0000
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
27
26
25
24
23
22
21
20
19
18
17
16
HT2[11:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
LT2[11:0]
rw
rw
rw
rw
rw
rw
rw
Bits 31:28 Reserved, must be kept at reset value.
Bits 27:16 HT2[11:0]: Analog watchdog 2 higher threshold
These bits are written by software to define the higher threshold for the analog watchdog.
Refer to Section 16.7: Analog window watchdogs on page 445.
Bits 15:12 Reserved, must be kept at reset value.
Bits 11:0 LT2[11:0]: Analog watchdog 2 lower threshold
These bits are written by software to define the lower threshold for the analog watchdog.
Refer to Section 16.7: Analog window watchdogs on page 445.
16.12.9
ADC channel selection register (ADC_CHSELR)
Address offset: 0x28
Reset value: 0x0000 0000
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Analog-to-digital converter (ADC)
The same register can be used in two different modes:
– Each ADC_CHSELR bit enables an input (CHSELRMOD = 0 in ADC_CFGR1). Refer to
the current section.
– ADC_CHSELR is able to sequence up to 8 channels (CHSELRMOD = 1 in
ADC_CFGR1). Refer to next section.
CHSELRMOD = 0 in ADC_CFGR1
31
30
29
28
27
26
25
24
23
22
21
20
19
18
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
17
16
CHSEL CHSEL
17
16
rw
rw
1
0
CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:18 Reserved, must be kept at reset value.
Bits 17:0 CHSEL[17:0]: Channel-x selection
These bits are written by software and define which channels are part of the sequence of channels
to be converted. Refer to Figure 49: ADC connectivity for ADC inputs connected to external
channels and internal sources.
0: Input Channel-x is not selected for conversion
1: Input Channel-x is selected for conversion
Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no
conversion is ongoing).
If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or
changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
16.12.10 ADC channel selection register [alternate] (ADC_CHSELR)
Address offset: 0x28
Reset value: 0x0000 0000
The same register can be used in two different modes:
– Each ADC_CHSELR bit enables an input (CHSELRMOD = 0 in ADC_CFGR1). Refer to
the current previous section.
– ADC_CHSELR is able to sequence up to 8 channels (CHSELRMOD = 1 in
ADC_CFGR1). Refer to this section.
CHSELRMOD = 1 in ADC_CFGR1:
31
30
rw
rw
15
14
29
28
27
26
rw
rw
rw
rw
13
12
11
10
SQ8[3:0]
rw
rw
24
23
22
rw
rw
rw
rw
9
8
7
6
SQ7[3:0]
SQ4[3:0]
rw
25
rw
rw
rw
20
19
18
rw
rw
rw
rw
rw
rw
5
4
3
2
1
0
SQ6[3:0]
SQ3[3:0]
rw
21
rw
RM0461 Rev 10
rw
rw
16
SQ5[3:0]
SQ2[3:0]
rw
17
SQ1[3:0]
rw
rw
rw
rw
rw
469/1290
477
Analog-to-digital converter (ADC)
RM0461
Bits 31:28 SQ8[3:0]: 8th conversion of the sequence
These bits are programmed by software with the channel number (0...14) assigned to the 8th
conversion of the sequence. 0b1111 indicates the end of the sequence.
When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are
ignored.
0000: CH0
0001: CH1
...
1100: CH12
1101: CH13
1110: CH14
1111: No channel selected (End of sequence)
Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no
conversion is ongoing).
Bits 27:24 SQ7[3:0]: 7th conversion of the sequence
These bits are programmed by software with the channel number (0...14) assigned to the 8th
conversion of the sequence. 0b1111 indicates end of the sequence.
When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are
ignored.
Refer to SQ8[3:0] for a definition of channel selection.
Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no
conversion is ongoing).
Bits 23:20 SQ6[3:0]: 6th conversion of the sequence
These bits are programmed by software with the channel number (0...14) assigned to the 8th
conversion of the sequence. 0b1111 indicates end of the sequence.
When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are
ignored.
Refer to SQ8[3:0] for a definition of channel selection.
Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no
conversion is ongoing).
Bits 19:16 SQ5[3:0]: 5th conversion of the sequence
These bits are programmed by software with the channel number (0...14) assigned to the 8th
conversion of the sequence. 0b1111 indicates end of the sequence.
When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are
ignored.
Refer to SQ8[3:0] for a definition of channel selection.
Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no
conversion is ongoing).
Bits 15:12 SQ4[3:0]: 4th conversion of the sequence
These bits are programmed by software with the channel number (0...14) assigned to the 8th
conversion of the sequence. 0b1111 indicates end of the sequence.
When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are
ignored.
Refer to SQ8[3:0] for a definition of channel selection.
Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no
conversion is ongoing).
470/1290
RM0461 Rev 10
RM0461
Analog-to-digital converter (ADC)
Bits 11:8 SQ3[3:0]: 3rd conversion of the sequence
These bits are programmed by software with the channel number (0...14) assigned to the 8th
conversion of the sequence. 0b1111 indicates end of the sequence.
When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are
ignored.
Refer to SQ8[3:0] for a definition of channel selection.
Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no
conversion is ongoing).
Bits 7:4 SQ2[3:0]: 2nd conversion of the sequence
These bits are programmed by software with the channel number (0...14) assigned to the 8th
conversion of the sequence. 0b1111 indicates end of the sequence.
When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are
ignored.
Refer to SQ8[3:0] for a definition of channel selection.
Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no
conversion is ongoing).
Bits 3:0 SQ1[3:0]: 1st conversion of the sequence
These bits are programmed by software with the channel number (0...14) assigned to the 8th
conversion of the sequence. 0b1111 indicates end of the sequence.
When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are
ignored.
Refer to SQ8[3:0] for a definition of channel selection.
Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no
conversion is ongoing).
16.12.11 ADC watchdog threshold register (ADC_AWD3TR)
Address offset: 0x2C
Reset value: 0x0FFF 0000
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
27
26
25
24
23
22
21
20
19
18
17
16
HT3[11:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
LT3[11:0]
rw
rw
rw
rw
rw
rw
rw
Bits 31:28 Reserved, must be kept at reset value.
Bits 27:16 HT3[11:0]: Analog watchdog 3 higher threshold
These bits are written by software to define the higher threshold for the analog watchdog.
Refer to Section 16.7: Analog window watchdogs on page 445.
Bits 15:12 Reserved, must be kept at reset value.
Bits 11:0 LT3[11:0]: Analog watchdog 3lower threshold
These bits are written by software to define the lower threshold for the analog watchdog.
Refer to Section 16.7: Analog window watchdogs on page 445.
RM0461 Rev 10
471/1290
477
Analog-to-digital converter (ADC)
RM0461
16.12.12 ADC data register (ADC_DR)
Address offset: 0x40
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r
r
r
r
r
r
r
r
r
r
r
r
r
r
DATA[15:0]
r
r
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 DATA[15:0]: Converted data
These bits are read-only. They contain the conversion result from the last converted channel. The
data are left- or right-aligned as shown in Figure 57.
Just after a calibration is complete, DATA[6:0] contains the calibration factor.
16.12.13 ADC analog watchdog 2 configuration register (ADC_AWD2CR)
Address offset: 0xA0
Reset value: 0x0000 0000
31
Res.
30
Res.
29
Res.
28
Res.
27
Res.
26
Res.
25
Res.
24
Res.
23
Res.
22
Res.
21
Res.
20
Res.
19
Res.
18
17
16
Res.
AWD2
CH17
AWD2
CH16
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
AWD2
CH15
AWD2
CH14
AWD2
CH13
AWD2
CH12
AWD2
CH11
AWD2
CH10
AWD2
CH9
AWD2
CH8
AWD2
CH7
AWD2
CH6
AWD2
CH5
AWD2
CH4
AWD2
CH3
AWD2
CH2
AWD2
CH1
AWD2
CH0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:18 Reserved, must be kept at reset value.
Bits 17:0 AWD2CH[17:0]: Analog watchdog channel selection
These bits are set and cleared by software. They enable and select the input channels to be guarded
by analog watchdog 2 (AWD2).
0: ADC analog channel-x is not monitored by AWD2
1: ADC analog channel-x is monitored by AWD2
Note: The channels selected through ADC_AWD2CR must be also configured into the
ADC_CHSELR registers. The software is allowed to write this bit only when ADEN = 0.
472/1290
RM0461 Rev 10
RM0461
Analog-to-digital converter (ADC)
16.12.14 ADC Analog Watchdog 3 Configuration register (ADC_AWD3CR)
Address offset: 0xA4
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
AWD3
CH17
AWD3
CH16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
AWD3
CH15
AWD3
CH14
AWD3
CH13
AWD3
CH12
AWD3
CH11
AWD3
CH10
AWD3
CH9
AWD3
CH8
AWD3
CH7
AWD3
CH6
AWD3
CH5
AWD3
CH4
AWD3
CH3
AWD3
CH2
AWD3
CH1
AWD3
CH0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:18 Reserved, must be kept at reset value.
Bits 17:0 AWD3CH[17:0]: Analog watchdog channel selection
These bits are set and cleared by software. They enable and select the input channels to be guarded
by analog watchdog 3 (AWD3).
0: ADC analog channel-x is not monitored by AWD3
1: ADC analog channel-x is monitored by AWD3
Note: The channels selected through ADC_AWD3CR must be also configured into the
ADC_CHSELR registers. The software is allowed to write this bit only when ADEN = 0.
16.12.15 ADC calibration factor (ADC_CALFACT)
Address offset: 0xB4
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
6
5
4
3
2
1
0
rw
rw
rw
15
14
13
12
11
10
9
8
7
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CALFACT[6:0]
rw
rw
rw
rw
Bits 31:7 Reserved, must be kept at reset value.
Bits 6:0 CALFACT[6:0]: Calibration factor
These bits are written by hardware or by software.
– Once a calibration is complete, they are updated by hardware with the calibration factors.
– Software can write these bits with a new calibration factor. If the new calibration factor is different
from the current one stored into the analog ADC, it is then applied once a new conversion is
launched.
– Just after a calibration is complete, DATA[6:0] contains the calibration factor.
Note: Software can write these bits only when ADEN=1 (ADC is enabled and no calibration is ongoing
and no conversion is ongoing).
RM0461 Rev 10
473/1290
477
Analog-to-digital converter (ADC)
RM0461
16.12.16 ADC common configuration register (ADC_CCR)
Address offset: 0x308
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
Res.
Res.
Res.
Res.
Res.
Res.
Res.
VBATEN
TSEN
VREFEN
21
20
19
18
17
16
Res.
Res.
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PRESC[3:0]
Bits 31:25 Reserved, must be kept at reset value.
Bit 24 VBATEN: VBAT enable
This bit is set and cleared by software to enable/disable the VBAT channel.
0: VBAT channel disabled
1: VBAT channel enabled
Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no
conversion is ongoing)
Bit 23 TSEN: Temperature sensor buffer enable
This bit is set and cleared by software to enable/disable the temperature sensor buffer.
0: Temperature sensor buffer disabled
1: Temperature sensor buffer enabled
Note: Software is allowed to write this bit only when ADSTART = 0 (which ensures that no
conversion is ongoing).
This bit must be cleared before entering low-power modes to avoid unwanted power
consumption.
Bit 22 VREFEN: VREFINT buffer enable
This bit is set and cleared by software to enable/disable the VREFINT buffer.
0: VREFINT buffer disabled
1: VREFINT buffer enabled
Note: Software is allowed to write this bit only when ADSTART = 0 (which ensures that no
conversion is ongoing).
This bit must be cleared before entering low-power modes to avoid unwanted power
consumption.
474/1290
RM0461 Rev 10
RM0461
Analog-to-digital converter (ADC)
Bits 21:18 PRESC[3:0]: ADC prescaler
Set and cleared by software to select the frequency of the clock to the ADC.
0000: input ADC clock not divided
0001: input ADC clock divided by 2
0010: input ADC clock divided by 4
0011: input ADC clock divided by 6
0100: input ADC clock divided by 8
0101: input ADC clock divided by 10
0110: input ADC clock divided by 12
0111: input ADC clock divided by 16
1000: input ADC clock divided by 32
1001: input ADC clock divided by 64
1010: input ADC clock divided by 128
1011: input ADC clock divided by 256
Other: Reserved
Note: Software is allowed to write these bits only when the ADC is disabled (ADCAL = 0,
ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).
Bits 17:0 Reserved, must be kept at reset value.
16.13
ADC register map
The following table summarizes the ADC registers.
7
6
5
4
3
2
1
0
AWD1
Res.
Res.
RM0461 Rev 10
OVR
EOS
EOC
EOSMP
ADRDY
0
EOSMPIE
ADRDYIE
Res.
0
0
0
0
0
0
ADEN
0
RES
[1:0]
0
0
0
DMAEN
0
EXTSEL
[2:0]
ADDIS
0
DMACFG
EOSIE
EOCIE
0
ADSTART
OVRIE
0
SCANDIR
0
0
0
ALIGN
EXTEN[1:0]
0
Res.
OVRMOD
0
WAIT
0
CONT
AUTOFF
Res.
Res.
0
Res.
0
Res.
Res.
0
DISCEN
0
0
0
ADSTP
Res.
Res.
0
Res.
8
AWD2
0
Res.
9
AWD3
AWD1IE
Res.
0
Res.
Res.
Res.
CCRDYIE
Res.
Res.
0
AWD2IE
Res.
Res.
Res.
0
AWD3IE
15
Res.
Res.
Res.
0
Res.
16
Res.
Res.
Res.
0
Res.
17
Res.
Res.
Res.
11
18
Res.
Res.
Res.
Res.
Res.
Res.
10
19
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
20
Res.
0
CHSELRMOD
0
0
Res.
21
Res.
0
AWD1SGL
0
AWD1EN
Reset value
0
0
Res.
0x0C
Res.
AWDCH[4:0]
Res.
ADC_CFGR1
Res.
0
Res.
0
Res.
ADCAL
Reset value
Res.
ADVREGEN
0
ADC_CR
0x08
0
0
Res.
22
Res.
12
23
Res.
Res.
Reset value
EOCAL
24
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
ADC_IER
0x04
0
EOCALIE
25
Res.
Reset value
Res.
26
Res.
13
27
Res.
Res.
28
Res.
14
29
Res.
Res.
30
ADC_ISR
0x00
CCRDY
Register name
Reset value
31
Offset
Res.
Table 98. ADC register map and reset values
0
0
0
475/1290
477
476/1290
0xA4
ADC_AWD3CR
AWD2CH15
AWD2CH14
AWD2CH13
AWD2CH12
AWD2CH11
AWD2CH10
AWD2CH9
AWD2CH8
AWD2CH7
AWD2CH6
AWD2CH5
AWD2CH4
AWD2CH3
AWD2CH2
AWD2CH1
AWD2CH0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AWD3CH15
AWD3CH14
AWD3CH13
AWD3CH12
AWD3CH11
AWD3CH10
AWD3CH9
AWD3CH8
AWD3CH7
AWD3CH6
AWD3CH5
AWD3CH4
AWD3CH3
AWD3CH2
AWD3CH1
AWD3CH0
Reset value
0
1
RM0461 Rev 10
HT3[11:0]
Reset value
0
0
0
0
Res.
0
Res.
SQ5[3:0]
0
0
0
0
0
0
0
0
CHSEL1
CHSEL0
0
0
CHSEL2
0
0
CHSEL3
0
0
CHSEL4
0
0
CHSEL5
CHSEL13
0
0
CHSEL6
CHSEL14
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reserved
CHSEL7
CHSEL15
Reserved
CHSEL8
1
CHSEL16
0x1C
CHSEL9
1
CHSEL17
Reserved
CHSEL10
1
Res
Reserved
CHSEL11
1
Res
0x18
CHSEL12
1
Res
HT2[11:0]
Res.
1
Res
Res.
Res.
HT1[11:0]
Res.
1
Res
1
Res.
Reserved
AWD2CH16
1
AWD3CH16
1
0
Res.
1
Res.
1
AWD2CH17
0
Res.
SQ6[3:0]
Res
1
Res.
1
Res
1
Res.
0
Res
1
Res.
1
Res
1
Res.
0
Res
1
1
Res
1
Res.
0
Res
1
Res.
Reset value
1
Res.
Res.
1
Res
0
Res.
SQ7[3:0]
Res
1
1
Res
0
Res.
1
1
Res.
0
Res.
1
1
Res.
1
0
Res.
Reset value
Res.
ADC_AWD3TR
0
Res.
0
Res.
0
Res.
SQ8[3:0]
1
AWD3CH17
Reset value
1
Res.
ADC_AWD2CR
Res.
Reset value
Res.
0
Res.
Reset value
Res.
0xA0
Res.
SMPSEL15
SMPSEL14
SMPSEL13
SMPSEL12
SMPSEL11
SMPSEL10
SMPSEL9
SMPSEL8
SMPSEL7
SMPSEL6
SMPSEL5
SMPSEL4
SMPSEL3
SMPSEL2
SMPSEL1
SMPSEL0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
SQ4[3:0]
1
0
0
0
0
0
0
0
0
0
0
0
Res.
SMPSEL16
Res..
Res..
Res..
22
21
20
19
18
17
16
15
14
13
12
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
0
0
SQ3[3:0]
0
0
0
0
0
0
OVSR[2:0]
0
SMP2
[2:0]
0
0
0
0
SQ2[3:0]
0
SMP1
[2:0]
1
0
OVSE
0
Res.
2
3
0
Res.
4
0
5
6
7
0
OVSS[3:0]
8
9
23
Res.
TOVS
24
Res.
11
25
Res.
10
26
Res.
Res.
27
Res.
Res.
28
Res.
Res..
30
29
Res..
31
LFTRIG
Res.
SMPSEL17
Reset value
Res.
Reserved
Res.
0
Res.
0
Res.
0
Res.
...
Res.
0
Res.
ADC_DR
Res.
CKMODE[1:0]
Reset value
Res.
0x40
Res.
ADC_CFGR2
Res.
0x30
0x34
0x38
0x3C
Res.
ADC_CHSELR
(CHSELRMOD=
1)
Res.
ADC_CHSELR
(CHSELRMOD=
0)
Res.
0x2C
Reset value
Res.
ADC_AWD2TR
Res.
0x24
Res.
ADC_AWD1TR
Res.
0x20
Res.
ADC_SMPR
Res.
0x14
Res.
0x28
Res.
0x10
Res.
0x28
Register name
Reset value
Res.
Offset
Res.
Analog-to-digital converter (ADC)
RM0461
Table 98. ADC register map and reset values (continued)
0
0
0
0
0
LT1[11:0]
0
0
0
0
0
LT2[11:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
SQ1[3:0]
LT3[11:0]
0
0
0
0
0
0
0
0
0
0
0
Reserved
DATA[15:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reserved
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RM0461
Analog-to-digital converter (ADC)
0
1
2
3
7
Res.
4
8
Res.
0
Res.
Res.
Res.
0
0
0
Res.
0
Res.
0
Res.
0
Res.
Res.
Res.
Res.
Res.
0
Res.
0
Res.
PRESC0
0
Res.
PRESC1
0
Res.
PRESC2
0
Res.
PRESC3
0
Res.
VREFEN
0
Res.
TSEN
Res.
Res.
Res.
Res.
Res.
VBATEN
Reset value
Res.
ADC_CCR
CALFACT[6:0]
Reserved
Res.
Reserved
0x308
5
9
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
...
6
11
10
Res.
12
Res.
13
Res.
14
Res.
15
16
17
18
19
20
21
22
23
24
25
26
27
29
28
Res.
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