Sample Midterm Exam

Sample Midterm Exam
MidDay, MidMonth, MidYear
ELEC4708: Advanced Digital Electronics
Department of Electronics, Carleton University
Instructor: Maitham Shams
Booklets: None
Aids Allowed: Calculator
Exam Duration: 1 hour
Number of Pages: 4 with this
Number of Students: MidNumber
Last Name:
First Name:
ID:
Q1
Q2
Q3
Q4
Total
Write your name and ID number clearly on all pages. No questions answered.
Attempt all questions. Marking scheme for all questions are given.
If in a question you are asked to make an assumption, then you must use it.
Formula
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&/.10
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.
.
&)(+087-9:,<;
Data
EGFHFI
JLK
E
v ,M0
4JON
E
v ,P7
4J1
v
Name & ID: ................................................................................................................................
2
[1] (10 marks, 1 marks each) Mark True or False.
1. Body (substrate) of PMOS transistors are usually grounded.
Q True Q False
2. A CMOS transmission gate consists of a PMOS and an NMOS transistor
connected in parallel.
Q True Q False
3. Stick diagrams may be used to estimate the area of logic gates.
Q True Q False
4. Using only the true (not inverted) inputs, it is impossible to implement a
CMOS non-inverting logic gate in one stage.
Q True Q False
5. An ideal flip-flop is never transparent.
Q True Q False
6. in modern CMOS IC technologies diffusion capacitances are much smaller
than gate-oxide capacitances.
Q True Q False
7. In modern CMOS digital circuits electron velocity doesn’t saturate.
Q True Q False
8. MOS threshold voltage is independent of source-body potential.
Q True Q False
9. In modern CMOS digital circuits junction leakage current is less than
subthreshold leakage current.
Q True Q False
Q True Q False
10. CMOS circuits operate faster at lower temperatures.
[2] (5 marks) Obtain the steady-state voltages
at the nodes of the following circuit. All capacitances are
TS
U
0.1 pF each and all the transistors have R
.
VDD
A
D
EGVW
EYX
EYZ[
EYF\
EG]
B
C
E
Name & ID: ................................................................................................................................
3
[3] (20 marks) Consider the following circuit. The inverter has an input capacitance of 6 units (i.e. twice
as large as the unit inverter). The output capacitance is 345.6 units.
y
x
6
x
y
z
345.6
y
Calculate the minimum possible delay for the circuit, if the delay of a unit inverter is 15 ps in this
technology.
Find the size of all unknown PMOS and NMOS transistors in the circuit.
Name & ID: ................................................................................................................................
4
[4] (15 marks) Implement the following function in conventional CMOS. Assume that both the true and
inverted inputs are available. If there are more than one possible implementations, do the one that imposes
less capacitive loas at the output, i.e., faster.
f h
_^ `bac &ed gi
Size the transistors such that the logic gate is equivalent (in resistance and current) to a unit inverter
S TS 7
0
(i.e. R 7
and R 0
). If there are more than one way of sizing, do the one that results
in a faster circuit.
If the output diffusion capacitance of a unit inverter is 12 fF, calculate the energy dissipation at the
output ^ .
How much power do you save by operating with a power supply of 1.2 v instead of 1.8 v.