NXP SCF5250 Integrated ColdFire® V2 Microprocessor Data Sheet

Freescale Semiconductor

Data Sheet

Document Number: SCF5250

Rev. 1.1, 04/2005

SCF5250 Integrated ColdFire®

Microprocessor Data Sheet

1 Introduction

This document provides an overview of the SCF5250

ColdFire

®

processor and general descriptions of

SCF5250 features and its various modules.

The SCF5250 was designed as a system controller/decoder for compressed audio music players, especially portable and automotive CD and hard disk drive players. The 32-bit ColdFire core with Enhanced

Multiply Accumulate (EMAC) unit provides optimum performance and code density for the combination of control code and signal processing required for audio decoding and post processing, file management, and system control.

Low power features include a hardwired CD ROM decoder, advanced 0.13um CMOS process technology,

1.2V core power supply, and on-chip 128KByte SRAM that enables Windows Media Audio (WMA) decoding without the need for external DRAM in CD applications.

The SCF5250 is also an excellent general purpose system controller with over 110 Dhrystone 2.1 MIPS @

120MHz performance at a very competitive price. The integrated peripherals and enhanced MAC unit allow the

Table of Contents

1 Introduction.......................................................... 1

2 SCF5250 Block Diagram ..................................... 8

3 Documentation ....................................................8

4 Signal Descriptions.............................................. 9

5 Electrical Characteristics ................................... 21

6 Pin-Out and Package Information ..................... 38

© Freescale Semiconductor, Inc., 200

5. All rights reserved.

2

Introduction

SCF5250 to replace both the microcontroller and the DSP in certain applications. Most peripheral pins can also be remapped as General Purpose I/O pins.

1.1

Orderable Part Numbers

1.1.1

Orderable Part Table

Orderable Part

Number

SCF5250AG120

SCF5250CAG120

SCF5250VM120

Maximum Clock

Frequency

120 MHz

120 MHz

120 MHz

Table 1. Orderable Part Numbers

Package Type

144 pin QFP

144 pin QFP

196 ball MAPBGA

Operating

Temperature Range

-20

°C to 70°C

-40

°C to 85°C

-20

°C to 70°C

Part Status

Lead Free

Lead Free

Lead Free

1.2

SCF5250 Features

1.2.1

ColdFire V2 Core

The ColdFire processor Version 2 core consists of two independent, decoupled pipeline structures to maximize performance while minimizing core size.The instruction fetch pipeline (IFP) is a two-stage pipeline for prefetching instructions. The prefetched instruction stream is then gated into the two-stage operand execution pipeline (OEP), which decodes the instruction, fetches the required operands, and then executes the required function. Because the IFP and OEP pipelines are decoupled by an instruction buffer that serves as a FIFO queue, the IFP can prefetch instructions in advance of their actual use by the OEP, which minimizes time stalled waiting for instructions. The OEP is implemented in a two-stage pipeline featuring a traditional RISC data path with a dual-read-ported register file feeding an arithmetic/logic unit

(ALU).

1.2.2

DMA Controller

The SCF5250 provides four fully programmable DMA channels for quick data transfer. Single and dual address mode is supported with the ability to program bursting and cycle stealing. Data transfer is selectable as 8, 16, 32, or 128-bits. Packing and unpacking is supported.

Two internal audio channels and the dual UART can be used with the DMA channels. All channels can perform memory to memory transfers. The DMA controller has a user-selectable, 24- or 16-bit counter and a programmable DMA exception handler.

External requests are not supported.

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

Freescale Semiconductor

Introduction

1.2.3

Enhanced Multiply and Accumulate Module (EMAC)

The integrated EMAC unit provides a common set of DSP operations and enhances the integer multiply instructions in the ColdFire architecture. The EMAC provides functionality in three related areas:

1. Faster signed and unsigned integer multiplies

2. New multiply-accumulate operations supporting signed and unsigned operands

3. New miscellaneous register operations

Multiplies of 16x16 and 32x32 with 48-bit accumulates are supported in addition to a full set of extensions for signed and unsigned integers plus signed, fixed-point fractional input operands. The EMAC has a single-clock issue for 32x32-bit multiplication instructions and implements a four-stage execution pipeline.

1.2.4

Instruction Cache

The instruction cache improves system performance by providing cached instructions to the execution unit in a single clock. The SCF5250 processor uses a 8K-byte, direct-mapped instruction cache to achieve 107

MIPS at 120 MHz. The cache is accessed by physical addresses, where each 16-byte line consists of an address tag and a valid bit. The instruction cache also includes a bursting interface for 16-bit and 8-bit port sizes to quickly fill cache lines.

1.2.5

Internal 128-KByte SRAM

The 128-KByte on-chip SRAM is available in two banks, SRAM0 (64K) and SRAM1 (64K). It provides one clock-cycle access for the ColdFire core. This SRAM can store processor stack and critical code or data segments to maximize performance. Memory in SRAM1 can be accessed under DMA.

1.2.6

SDRAM Controller

The SCF5250 SDRAM controller provides a glueless interface for one bank of SDRAM up to 32 MB (256

Mbits). The controller supports a 16-bit data bus. A unique addressing scheme allows for increases in system memory size without rerouting address lines and rewiring boards. The controller operates in page mode, non-page mode, and burst-page mode and supports SDRAMS.

1.2.7

System Interface

The SCF5250 provides a glueless interface to 16-bit port size SRAM, ROM, and peripheral devices with independent programmable control of the assertion and negation of chip-select and write-enable signals.

The SCF5250 also supports bursting ROMs.

1.2.8

External Bus Interface

The bus interface controller transfers information between the ColdFire core or DMA and memory, peripherals, or other devices on the external bus. The external bus interface provides 23 bits of address bus

Freescale Semiconductor

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

3

Introduction space, a 16-bit data bus, Output Enable, and Read/Write signals. This interface implements an extended synchronous protocol that supports bursting operations.

1.2.9

Serial Audio Interfaces

The SC5250 digital audio interface provides three serial Philips IIS/Sony EIAJ interfaces. One interface is a 4-pin (1 bit clock, 1 word clock, 1 data in, 1 data out), the other two interfaces are 3-pin (1 bit clock,

1 word clock, 1 data in or out). The serial interfaces have no limit on minimum sampling frequency.

Maximum sampling frequency is determined by maximum frequency on bit clock input. This is 1/3 the frequency of the internal system clock.

1.2.10 IEC958 Digital Audio Interfaces

The SCF5250 has one digital audio input interface, and one digital audio output interface. The single output carries the consumer “c” channel.

1.2.11 Audio Bus

The audio interfaces connect to an internal bus that carries all audio data. Each receiver places its received data on the audio bus and each transmitter takes data from the audio bus for transmission. Each transmitter has a source select register.

In addition to the audio interfaces, there are six CPU accessible registers connected to the audio bus. Three of these registers allow data reads from the audio bus and allow selection of the audio source. The other three register provide a write path to the audio bus and can be selected by transmitters as the audio source.

Through these registers, the CPU has access to the audio samples for processing.

Audio can be routed from a receiver to a transmitter without the data being processed by the core so the audio bus can be used as a digital audio data switch. The audio bus can also be used for audio format conversion.

1.2.12 CD-ROM Encoder/Decoder

The SCF5250 is capable of processing CD-ROM sectors in hardware. Processing is compliant with

CD-ROM and CD-ROM XA standards.

The CD-ROM decoder performs following functions in hardware:

• Sector sync recognition

• Descrambling of sectors

• Verification of the CRC checksum for Mode 1, Mode 2 Form 1, and Mode 2 Form 2 sectors

• Third-layer error correction is not performed

The CD-ROM encoder performs following functions in hardware:

• Sector sync recognition

• Scrambling of sectors

4

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

Freescale Semiconductor

Introduction

• Insertion of the CRC checksum for Mode 1, Mode 2 Form 1, and Mode 2 Form 2 sectors.

• Third-layer error encoding needs to be done in software. This can use approximately 5-10 Mhz of performance for single-speed.

1.2.13 Dual UART Module

Two full-duplex UARTs with independent receive and transmit buffers are in this module. Data formats can be 5, 6, 7, or 8 bits with even, odd, or no parity, and up to 2 stop bits in 1/16 increments. Four-byte receive buffers and two-byte transmit buffers minimize CPU service calls. The Dual UART module also provides several error-detection and maskable-interrupt capabilities. Modem support includes request-to-send (RTS) and clear-to-send (CTS) lines.

The system clock provides the clocking function from a programmable prescaler. You can select full duplex, auto-echo loopback, local loopback, and remote loopback modes. The programmable Dual UARTs can interrupt the CPU on various normal or error-condition events.

1.2.14 Queued Serial Peripheral Interface QSPI

The QSPI module provides a serial peripheral interface with queued transfer capability. It supports up to

16 stacked transfers at a time, making CPU intervention between transfers unnecessary. Transfers of up to

15 Mbits/second are possible at a CPU clock of 120 MHz. The QSPI supports master mode operation only.

1.2.15 Timer Module

The timer module includes two general-purpose timers, each of which contains a free-running 16-bit timer.

Timer0 has an external pin TOUT0, which can be used in Output Compare mode. This mode triggers an external signal or interrupts the CPU when the timer reaches a set value, and can also generate waveforms on TOUT0.

The timer unit has an 8-bit prescaler that allows programming of the clock input frequency, which is derived from the system clock. In addition to the ÷1 and ÷16 clock derived from the bus clock (CPU clock

/ 2), the programmable timer-output pins either generate an active-low pulse or toggle the outputs.

1.2.16 IDE and SmartMedia Interfaces

The SCF5250 system bus allows connection of an IDE hard disk drive or SmartMedia flash card with a minimum of external hardware. The external hardware consists of bus buffers for address and data and are intended to reduce the load on the bus and prevent SDRAM and Flash accesses to propagate to the IDE bus. The control signals for the buffers are generated in the SCF5250.

1.2.17 Analog/Digital Converter (ADC)

The six channel ADC is a based on the Sigma-Delta concept with 12-bit resolution. Both the analogue comparator and digital sections of the ADC are provided internally. An external integrator circuit

(resistor/capacitor) is required, which is driven by the ADC output. A software interrupt is provided when the ADC measurement cycle is complete.

Freescale Semiconductor

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

5

Introduction

1.2.18 I

2

C Module

The two-wire I

2

C bus interface, which is compliant with the Philips I

2

C bus standard, is a bidirectional serial bus that exchanges data between devices. The I

2

C bus minimizes the interconnection between devices in the end system and is best suited for applications that need occasional bursts of rapid communication over short distances among several devices. Bus capacitance and the number of unique addresses limit the maximum communication length and the number of devices that can be connected.

1.2.19 Chip-Selects

Up to four programmable chip-select outputs provide signals that enable glueless connection to external memory and peripheral circuits. The base address, access permissions and automatic wait-state insertion are programmable with configuration registers. These signals also interface to 16-bit ports.

CS0 is active after reset to provide boot-up from external FLASH/ROM.

1.2.20 GPIO Interface

A total of 60 General Purpose inputs and 57 General Purpose outputs are available. These are multiplexed with various other signals. Seven of the GPIO inputs have edge sensitive interrupt capability.

1.2.21 Interrupt Controller

The interrupt controller provides user-programmable control of a total of 57 interrupts. There are 49 internal interrupt sources. In addition, there are 7 GPIOs where interrupts can be generated on the rising or falling edge of the pin. All interrupts are autovectored and interrupt levels are programmable.

1.2.22 JTAG

To help with system diagnostics and manufacturing testing, the SCF5250 includes dedicated user-accessible test logic that complies with the IEEE 1149.1A standard for boundary scan testability, often referred to as Joint Test Action Group, or JTAG. For more information, refer to the IEEE 1149.1A standard. Freescale provides BSDL files for JTAG testing.

1.2.23 System Debug Interface

The ColdFire processor core debug interface supports real-time instruction trace and debug, plus background-debug mode. A background-debug mode (BDM) interface provides system debug.

In real-time instruction trace, four status lines provide information on processor activity in real time (PST pins). A four-bit wide debug data bus (DDATA) displays operand data and change-of-flow addresses, which helps track the machine’s dynamic execution path.

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SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

Freescale Semiconductor

Introduction

1.2.24 Crystal and On-chip PLL

Typically, an external 16.92 Mhz or 33.86 Mhz clock input is used for CD R/W applications, while an

11.2896 MHz clock is more practical for Portable CD player applications. However, the on-chip programmable PLL, which generates the processor clock, allows the use of almost any low frequency external clock (5-35 Mhz).

Two clock outputs (MCLK1 and MCLK2) are provided for use as Audio Master Clock. The output frequencies of both outputs are programmable to Fxtal, Fxtal/2, Fxtal/3, and Fxtal/4. The Fxtal/3 option is only available when the 33.86 Mhz crystal is connected.

The SCF5250 supports VCO operation of the oscillator by means of a 16-bit pulse density modulation output. Using this mode, it is possible to lock the oscillator to the frequency of an incoming IEC958 or IIS signal. The maximum trim depends on the type and design of the oscillator. Typically a trim of +/- 100 ppm can be achieved with a crystal oscillator and over +/- 1000 ppm with an LC oscillator.

1.2.25 Boot ROM

The boot ROM on the SCF5250 serves to boot the CPU in designs which do not have external Flash memory or ROM. Typically this occurs in systems which have a separate MCU to control the system, and/or the SCF5250 is used as a stand-alone decoder.

The SCF5250 can be booted in one of three modes:

• External ROM

• Internal ROM Master mode – boots from I2C, SPI, or IDE

• Internal ROM Slave mode – boots from I2C or UART

1.2.26 Voltage Regulator

The SCF5250 contains an on-chip linear regulator that generates 1.2V from a 3.3V input. The regulator is self-contained and drives the 1.2V core voltage out on one pin that can be used to power the core supply pins at the board level. In battery powered portable applications, it is recommended that an external dc-dc converter be used to generate the 1.2V core voltage to minimize power consumption.

Freescale Semiconductor

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

7

SCF5250 Block Diagram

2 SCF5250 Block Diagram

Flash

Media Int

IDE

Interface

QSPI

BDM

CD ROM block encode

& decode

12-bit

ADC

I 2 C x2

PLL

I 2 S Rx x3

UART x2

DMAs /

Timers

GPI/O

I 2 S Tx x2

SPDIF

Tx

SPDIF

Rx

1.2V

Regulator

Boot

ROM

JTAG

8K

I-Cache

V2

ColdFire

®

Core

128K

SRAM

System

Bus

Controller

Oscillator

SDRAM Ctr

&

Chip Selects

Figure 1. SCF5250 Block Diagram

3 Documentation

Table 2 lists the documents that provide a complete description of the SCF5250 and are required to design properly with the part. Documentation is available from a local Freescale distributor, a Freescale semiconductor sales office, a Freescale Literature Distribution Center, or through the Freescale DSP home page on the Internet; http://e-www.Freescale.com/ (the source for the latest information).

8

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

Freescale Semiconductor

Signal Descriptions

Document Name

CFPRM/D

ColdFire2UM

ColdFire2UMAD

SCF5250UM

.

Table 2. SCF5250 Documentation

Description

ColdFire Family Programmer’s Reference Manual

Version 2/2M ColdFire Core

Processor User’s Manual

Version 2/2M ColdFire Core

Processor User’s Manual Addendum

SCF5250 User’s Manual

Order Number

CFPRM/D

ColdFire2UM/D

ColdFire2UMAD/D

SCF5250UM/D

4 Signal Descriptions

4.1

Introduction

This section describes the SCF5250 input and output signals. The signal descriptions as shown in Table

2-A are grouped according to relevant functionality.

Signal Name

Address

Read-write control

Output enable

Data

Synchronous column address strobe

D[31:16]

Synchronous row address SDRAS/GPIO59 strobe

SDCAS/GPIO39

SDRAM write enable SDWE/GPIO38

SDRAM upper byte enable SDUDQM/GPO53

SDRAM lower byte enable SDLDQM/GPO52

SDRAM chip selects

SDRAM clock enable

System clock

A[24:1]

A[23]/GPO54

R/W

OE

SD_CS0/GPIO60

BCLKE/GPIO63

BCLK/GPIO40

Table 3. SCF5250 Signal Index

Mnemonic Function

24 address lines, address line 23 multiplexed with GPO54 and address

24 is multiplexed with A20 (SDRAM access only).

Bus write enable - indicates if read or write cycle in progress

Output enable for asynchronous memories connected to chip selects

Data bus used to transfer word data

Row address strobe for external

SDRAM.

Column address strobe for external

SDRAM

Write enable for external SDRAM

Indicates during write cycle if high byte is written

Indicates during write cycle if low byte is written

SDRAM chip select

SDRAM clock enable

SDRAM clock output

Input/

Output

Out

Out

Out

In/Out

Out

Out

Out

Out

Out

In/Out

Out

In/Out

Reset

State

X

H negated

Hi-Z negated negated negated negated

Freescale Semiconductor

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

9

Signal Descriptions

Signal Name

ISA bus read strobe

ISA bus write strobe

ISA bus wait signal

Chip Selects[2:0]

Buffer enable 1

Buffer enable 2

Transfer acknowledge

Wake Up

Serial Clock Line

Serial Data Line

Receive Data

Transmit Data

Request-To-Send

Clear-To-Send

Timer Output

IEC958 inputs

IEC958 outputs

Serial data in

Serial data out

Word clock

Bit clock

Table 3. SCF5250 Signal Index (continued)

Mnemonic Function

IDE-DIOR/GPIO31

(CS2)

IDE-DIOW/GPIO32

(CS2)

IDE-IORDY/GPIO33

CS0/CS4

CS1/QSPI_CS3/GPIO28

BUFENB1/GPIO29

BUFENB2/GPIO30

TA/GPIO12

WAKE_UP/GPIO21

SCL0/SDATA1_BS1/GPIO41

SCL1/TXD1/GPIO10

SDA0/SDATA3/GPIO42

SDA1/RXD1/GPIO44

There is 1 ISA bus read strobe and 1

ISA bus write strobe. They allow connection of one independent ISA bus peripherals, e.g. an IDE slave device.

ISA bus wait line - available for both busses

Enables peripherals at programmed addresses.

CS[0] provides boot ROM selection

Two programmable buffer enables allow seamless steering of external buffers to split data and address bus in sections.

Transfer Acknowledge signal

Wake-up signal input

Clock signal for Dual I

2

C module operation

Serial data port for second I

2

C module operation

SDA1/RXD1/GPIO44

RXD0/GPIO46

SCL1/TXD1/GPIO10

TXD0/GPIO45

DDATA3/RTS0/GPIO4

DDATA1/RTS1/SDATA2_BS2/GPIO2

DDATA2/CTSO/GPIO3

DDATA0/CTS1/SDATA0_SDIO1/GPIO1

Signals to DUART that data can be transmitted to peripheral

SDATAO1/TOUT0/GPIO18

DUART signals a ready to receive data query

Capable of output waveform or pulse generation audio interfaces IEC958 inputs EBUIN1/GPIO36

EBUIN2/SCLK_OUT/GPIO13

EBUIN3/CMD_SDIO2/GPIO14

QSPI_CS0/EBUIN4/GPIO15

EBUOUT1/GPIO37

QSPI_CS1/EBUOUT2/GPIO16

SDATAI1/GPIO17

SDATAI3/GPIO8

Signal is receive serial data input for

DUART

Signal is transmit serial data output for

DUART audio interfaces IEC958 outputs audio interfaces serial data inputs

SDATAO1/TOUT0/GPIO18

SDATAO2/GPIO34

LRCK1/GPIO19

LRCK2/GPIO23

LRCK3/GPIO43/AUDIO_CLOCK

SCLK1/GPIO20

SCLK2/GPIO22

SCLK3/GPIO35 audio interfaces serial data outputs audio interfaces serial word clocks audio interfaces serial bit clocks

Input/

Output

In/Out

In/Out

In/Out

Out

In/Out

In/Out

In/Out

In/Out

In

In/Out

In/Out

In

Out

Out

In

Out

In

Out

In

In/Out

Out

In/Out

In/Out

Reset

State negated

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SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

Freescale Semiconductor

Signal Descriptions

Table 3. SCF5250 Signal Index (continued)

Signal Name Mnemonic Function

Serial input

Serial input

Subcode clock

ADC IN

ADC OUT

EF/GPIO6

CFLG/GPIO5

RCK/QSPI_DIN/QSPI_DOUT/

GPIO26 error flag serial in

C-flag serial in audio interfaces subcode clock

Subcode sync

Subcode data

Clock frequency trim

Audio clocks out

Audio clock in

MemoryStick/SecureDigita l interface

QSPI_DOUT/SFSY/GPIO27

QSPI_CLK/SUBR/GPIO25

XTRIM/GPIO0

MCLK1/GPIO11

QSPI_CS2/MCLK2/GPIO24

LRCK3/GPIO43/AUDIO_CLOCK

EBUIN3/CMD_SDIO2/GPIO14 audio interfaces subcode sync audio interfaces subcode data clock trim control

DAC output clocks

Optional Audio clock Input

Secure Digital command lane

MemoryStick interface 2 data i/o

EBUIN2/SCLK_OUT/GPIO13 Clock out for both MemoryStick interfaces and for Secure Digital

DDATA0/CTS1/SDATA0_SDIO1/GPIO1 SecureDigital serial data bit 0

MemoryStick interface 1 data i/o

SCL0/SDATA1_BS1/GPIO41 SecureDigital serial data bit 1

MemoryStick interface 1 strobe

DDATA1/RTS1/SDATA2_BS2/GPIO2 SecureDigital serial data bit 2

MemoryStick interface 2 strobe

Reset output signal

SDA0/SDATA3/GPIO42 SecureDigital serial data bit 3

Analog to Digital converter input signals

ADIN0/GPI52

ADIN1/GPI53

ADIN2/GPI54

ADIN3/GPI55

ADIN4/GPI56

ADIN5/GPI57

ADREF

ADOUT/SCLK4/GPIO58

QSPI_CLK/SUBR/GPIO25

Analog to digital convertor output signal. Connect to ADREF via integrator network.

QSPI clock signal QSPI clock

QSPI data in

QSPI data out

QSPI chip selects

Crystal in

Crystal out

Reset In

Freescale Test Mode

Linear regulator output

RCK/QSPI_DIN/QSPI_DOUT/GPIO26 QSPI data input

RCK/QSPI_DIN/QSPI_DOUT/GPIO26

QSPI_DOUT/SFSY/GPIO27

QSPI data out

QSPI chip selects QSPI_CS0/EBUIN4/GPIO15

QSPI_CS1/EBUOUT2/GPIO16

QSPI_CS2/MCLK2/GPIO24

CS1/QSPI_CS3/GPIO28

CRIN Crystal input

CROUT

RSTI

TEST[2:0]

LINOUT

Crystal Out

Processor Reset Input

TEST pins.

outputs 1.2 V to supply core

In/Out

In/Out

In/Out

In/Out

In/Out

Input/

Output

In/Out

In/Out

In/Out

Reset

State

In/Out

In/Out

Out

Out

In/Out

In

In/Out

In/Out

In/Out

In/Out

In/Out

In

Out

In

In

Out

Freescale Semiconductor

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

11

Signal Descriptions

Table 3. SCF5250 Signal Index (continued)

Signal Name Mnemonic Function

Linear regulator input LININ

Linear regulator ground LINGND

High Impedance

Debug Data

Processor Status

Input, typically I/O supply (3.3V)

HI-Z

PST0/GPIO50

PST1/GPIO49

PST2/INTMON2/GPIO48

PST3/INTMON1/GPIO47

Assertion Tri-states all output signal pins.

DDATA0/CTS1/SDATA0_SDIO1/GPIO1

DDATA1/RTS1/SDATA2_BS2/GPIO2

DDATA2/CTS0/GPIO3

DDATA3/RTS0/GPIO4

Displays captured processor data and break-point status.

Indicates internal processor status.

Processor clock

Test Clock

Test Reset/Development

Serial Clock

PSTCLK/GPIO51

TCK

TRST/DSCLK processor clock output

Clock signal for IEEE 1149.1A JTAG.

Multiplexed signal that is asynchronous reset for JTAG controller. Clock input for debug module.

Test Mode Select/ Break

Point

Test Data Input /

Development Serial Input

TMS/BKPT

TDI/DSI

Test Data

Output/Development Serial

Output

TDO/DSO

Multiplexed signal that is test mode select in JTAG mode and a hardware break-point in debug mode.

Multiplexed serial input for the JTAG or background debug module.

Multiplexed serial output for the JTAG or background debug module.

Input/

Output

In

In

In/Out

In/Out

Out

In

In

In

In

Out

Reset

State

Hi-Z

Hi-Z

4.2

GPIO

Many pins have an optional GPIO function.

• General purpose input is always active, regardless of state of pin.

• General purpose output or primary output is determined by the appropriate setting of the Pin

Multiplex Control Registers, GPIO-FUNCTION, GPIO1-FUNCTION and PIN-CONFIG.

• At Power-on reset, all pins are set to their primary function.

4.3

SCF5250 Bus Signals

These signals provide the external bus interface to the SCF5250.

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SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

Freescale Semiconductor

Signal Descriptions

4.3.1

Address Bus

• The address bus provides the address of the byte or most significant byte of the word or longword being transferred.The address lines also serve as the DRAM address pins, providing multiplexed row and column address signals.

• Bits 23 down to 1 and 24 of the address are available. A24 is intended to be used with 256 Mbit

DRAM’s. Signals are named:

— A[23:1]

— A20/24

4.3.2

Read-Write Control

This signal indicates during any bus cycle whether a read or write is in progress. A low is write cycle and a high is a read cycle.

4.3.3

Output Enable

The OE signal is intended to be connected to the output enable of asynchronous memories connected to chip selects. During bus read cycles, the ColdFire processor will drive OE low.

4.3.4

Data Bus

The data bus (D[31:16]) is bi-directional and non-multiplexed. Data is registered by the SCF5250 on the rising clock edge. The data bus uses a default configuration if none of the chip-selects or DRAM bank match the address decode. All 16 bits of the data bus are driven during writes, regardless of port width or operand size.

4.3.5

Transfer Acknowledge

The TA/GPIO12 pin is the transfer acknowledge signal.

4.4

SDRAM Controller Signals

The following SDRAM signals provide a glueless interface to external SDRAM. An SDRAM width of 16 bits is supported and can access as much as 32MB of memory. ADRAMs are not supported.

Table 4. SDRAM Controller Signals

SDRAM Signal Description

Synchronous DRAM row address strobe The SDRAS/GPIO59 active low pin provides a seamless interface to the

RAS input on synchronous DRAM

Synchronous DRAM Column Address Strobe The SDCAS/GPIO39 active low pin provides a seamless interface to

CAS input on synchronous DRAM.

Synchronous DRAM Write The SDWE/GPIO38 active-low pin is asserted to signify that a SDRAM write cycle is underway. This pin outputs logic ‘1’ during read bus cycles.

Freescale Semiconductor

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

13

Signal Descriptions

Table 4. SDRAM Controller Signals (continued)

SDRAM Signal

Synchronous DRAM Chip Enable

Synchronous DRAM UDQM and LQDM signals

Synchronous DRAM clock

Synchronous DRAM Clock Enable

Description

The SD_CS0/GPIO60 active-low output signal is used during synchronous mode to route directly to the chip select of a SDRAM device.

The DRAM byte enables UDMQ and LDQM are driven by the

SDUDQM/GPO53 and SDLDQM/GPO52 byte enable outputs.

The DRAM clock is driven by the BCLK/GPIO40 signal

The BCLKE active high output signal is used during synchronous mode to route directly to the SCKE signal of external SDRAMs. This signal provides the clock enable to the SDRAM.

4.5

Chip Selects

There are three chip select outputs on the SCF5250 device. CS0/CS4 and CS1/QSPI_CS3/GPIO28 and

CS2 which is associated with the IDE interface read and write strobes - IDE-DIOR and IDE-DIOW.

CS0 and CS4 are multiplexed. The SCF5250 has the option to boot from an internal Boot Rom.

The function of the CS0/CS4 pin is determined by the boot mode. When the device is booted from internal

ROM, the internal ROM is accessed with CS0 (required for boot) and the CS0/CS4 pin is driven by CS4.

When the device is booted from external ROM / Flash, the CS0/CS4 pin is driven by CS0 and the internal

ROM is disabled.

The active low chip selects can be used to access asynchronous memories. The interface is glueless.

4.6

ISA bus

The SCF5250 supports an ISA bus. Using the ISA bus protocol, reads and writes for one ISA bus peripheral is possible. IDE-DIOR/GPIO31 and IDE-DIOW/GPIO32 are the read and write strobe. The peripheral can insert wait states by pulling IDE-IORDY/GPIO33.

CS2 is associated with the IDE-DIOR and IDE-DIOW.

4.7

Bus Buffer Signals

As the SCF5250 has a complicated slave bus, which allows SDRAM, asynchronous memories, and ISA peripherals on the bus, it may become necessary to introduce a buffer on the bus in certain applications.

The SCF5250 has a glueless interface to steer these bus buffers with two bus buffer output signals

BUFENB1/GPIO29 and BUFENB2/GPIO30.

4.8

I

2

C Module Signals

There are two I

2

C interfaces on this device.

The I

2

C module acts as a two-wire, bidirectional serial interface between the SCF5250 processor and peripherals with an I

2

C interface (e.g., LED controller, A-to-D converter, D-to-A converter). When

14

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

Freescale Semiconductor

Signal Descriptions devices connected to the I

2

C bus drive the bus, they will either drive logic-0 or high-impedance. This can be accomplished with an open-drain output.

I

2 c Module Signal

I

2

C Serial Clock

I

2

C Serial Data

Table 5. I

2

C Module Signals

Description

The SCL0/SDATA1_BS1/GPIO41 and SCL1/TXD1/GPIO10 bidirectional signals are the clock signal for first and second I

2

C module operation. The I

2

C module controls this signal when the bus is in master mode; all I

2

C devices drive this signal to synchronize I

2

C timing.

Signals are multiplexed

The SDA0/SDATA3/GPIO42 and SDA1/RXD1/GPIO44 bidirectional signals are the data input/output for the first and second serial I

2

C interface.

Signals are multiplexed

4.9

Serial Module Signals

The following signals transfer serial data between the two UART modules and external peripherals.

Serial Module Signal

Receive Data

Transmit Data

Request To Send

Clear To Send

Table 6. Serial Module Signals

Description

The RXD0/GPIO46 and SDA1/RXD1/GPIO44 are the inputs on which serial data is received by the DUART. Data is sampled on RxD[1:0] on the rising edge of the serial clock source, with the least significant bit received first.

The DUART transmits serial data on the TXD0/GPIO45 and

SCL1/TXD1/GPIO10 output signals. Data is transmitted on the falling edge of the serial clock source, with the least significant bit transmitted

(LSB) first. When no data is being transmitted or the transmitter is disabled, these two signals are held high. TxD[1:0] are also held high in local loopback mode.

The DDATA3/RTS0/GP104 and DDATA1/RTS1/SDATA2_BS2/GPIO2 request-to-send outputs indicate to the peripheral device that the

DUART is ready to send data and requires a clear-to-send signal to initiate transfer.

Peripherals drive the DDATA2/CTS0/GPIO3 and

DDATA0/CTS1/SDATA0_SDIO1/GPIO1 inputs to indicate to the

SCF5250 serial module that it can begin data transmission.

4.10 Timer Module Signals

The following signal provides an external interface to Timer0.

Serial Module Signal

Timer Output

Table 7. Timer Module Signals

Description

The SDATAO1/TOUT0/GPIO18 programmable output pulse or toggle on various timer events.

Freescale Semiconductor

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

15

Signal Descriptions

4.11 Serial Audio Interface Signals

The following signals provide the external audio interface.

Serial Module Signal

Serial Audio Bit Clock

Serial Audio Word Clock

Serial Audio Data In

Serial Audio Data Out

Serial audio error flag

Serial audio CFLG

Table 8. Serial Audio Interface Signals

Description

The SCLK1/GPIO20, SCLK2/GPIO22 and SCLK3/GPIO35, multiplexed pins can serve as general purpose I/Os or serial audio bit clocks. As bit clocks, these bidirectional pins can be programmed as outputs to drive their associated serial audio (IIS) bit clocks. Alternately, these pins can be programmed as inputs when the serial audio bit clocks are driven internally. The functionality is programmed within the

Audio module. During reset, these pins are configured as input serial audio bit clocks.

The LRCK1/GPIO19, LRCK2/GPIO23 and

LRCK3/GPIO43/AUDIO_CLOCK multiplexed pins can serve as general purpose I/Os or serial audio word clocks. As word clocks, the bidirectional pins can be programmed as inputs to drive their associated serial audio word clock. Alternately, these pins can be programmed as outputs when the serial audio word clocks are derived internally. The functionality is programmed within the Audio module. During reset, these pins are configured as input serial audio word clocks.

LRCK3/GPIO43/AUDIO_CLOCK can be used as the external audio clock input. If the core clock chosen to be non-audio specific.

The SDATAI1/GPIO17 and SDATAI3/GPIO8 multiplexed pins can serve as general purpose I/Os or serial audio inputs. As serial audio inputs the data is sent to interfaces 1and 3 respectively. During reset, the pins are configured as serial data inputs.

SDATO1/TOUT0/GPIO18 AND SDATAO2/GPIO34 multiplexed pins can serve as general purpose I/Os or serial audio outputs. During reset, the pins are configured as serial data outputs.

The EF/GPIO6 multiplexed pin can serve as general purpose I/Os or error flag input. As error flag input, this pin will input the error flag delivered by the CD-DSP. EF/GPIO6 is only relevant for serial interface

SDATAI1.

The CFLG/GPIO5 multiplexed pin can serve as general purpose I/O or

CFLG input. As CFLG input, the pin will input the CFLG flag delivered by the CD-DSP. CFLG/GPIO5 is only relevant for serial interface

SDATAI1.

16

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

Freescale Semiconductor

Signal Descriptions

4.12 Digital Audio Interface Signals

Serial Module Signal

Digital Audio In

Digital Audio Out

Table 9. Digital Audio Interface Signals

Description

The EBUIN1/GPIO36, EBUIN2/SCLK_OUT/GPIO13,

EBUIN3/CMD_SDIO2/GPIO14, and QSPI_CS0/EBUIN4/GPIO15 multiplexed signals can serve as general purpose input or can be driven by various digital audio (IEC958) input sources. Both functionalities are always active. Input chosen for IEC958 receiver is programmed within the audio module. Input value on the 4 pins can always be read from the appropriate GPIO register.

The EBUOUT1/GPIO37 and QSPI_CS1/EBUOUT2/GPIO16 multiplexed pins can serve as general purpose I/O or as digital audio

(IEC958) output. EBUOUT1 is digital audio out for consumer mode,

EBUOUT2 is digital audio out for professional mode. During reset, the pin is configured as a digital audio output.

4.13 Subcode Interface

There is a 3-line subcode interface on the SCF5250. This 3-line subcode interface allows the device to format and transmit subcode in EIAJ format to a CD channel encoder device. The three signals are described in Table 10 .

Table 10. Subcode Interface Signal

Signal name Description

RCK/QSPI_DIN/QSPI_DOUT/GPIO26 Subcode clock input. When pin is used as subcode clock, this pin is driven by the CD channel encoder.

QSPI_DOUT/SFSY/GPIO27

QSPI_CLK/SUBR/GPIO25

Subcode sync output

This signal is driven high if a subcode sync needs to be inserted in the

EFM stream.

Subcode data output

This signal is a subcode data out pin.

4.14 Analog to Digital Converter (ADC)

The ADOUT signal on the ADOUT/SCLK4/GPIO58 pin provides the reference voltage in PWM format.

This output requires an external integrator circuit (resistor/capacitor) to convert it to a DC level to be input to the ADREF pin.

The six AD inputs are each fed to their own comparator. The reference input to each (ADREF) is then multiplexed as only one AD comparison can be made at any one time.

NOTE

To use the ADINx as General Purpose inputs (rather than there analogue function) it is necessary to generate a fixed comparator voltage level of

VDD/2. This can be accomplished by a potential divider network connected to the ADREF pin. However in portable applications where stand-by power

Freescale Semiconductor

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

17

Signal Descriptions consumption is important the current taken by the divider network (in stand-by mode) could be excessive. Therefore it is possible to generate a

VDD/2 voltage by selecting SCLK4 output mode and feeding this clock signal (which is 50% duty cycle) through an external integration circuit.

This would generate a voltage level equal to VDD/2 but would be disabled when stand-by mode was selected.

4.15 Secure Digital/ MemoryStick Card Interface

The device has a versatile flash card interface that supports both SecureDigital and MemoryStick cards.

The interface can either support one SecureDigital or two MemoryStick cards. No mixing of card types is possible. Table 11 gives the pin descriptions.

Table 11. Flash Memory Card Signals

Flash Memory Signal

EBUIN2/SCLKOUT/GPIO13

EBUIN3/CMD_SDIO2/GPIO14

SDA0/SDATA3/GPIO42

Description

Clock out for both MemoryStick interfaces and for SecureDigital

Secure Digital command line

MemoryStick interface 2 data i/o

DDATAO/CTS1/SDATA0_SDIO1/GPIO1 SecureDigital serial data bit 0

MemoryStick interface 1 data i/o

SCL0/SDATA1_BS1/GPIO41 SecureDigital serial data bit 1

MemoryStick interface 1 strobe

DDATA1/RTS1/SDATA2_BS2/GPIO2 SecureDigital serial data bit 2

MemoryStick interface 2 strobe

Reset output signal

Selection between Reset function and SDATA2_BS2 is done by programming PLLCR register.

SecureDigital serial data bit 3

4.16 Queued Serial Peripheral Interface (QSPI)

The QSPI interface is a high-speed serial interface allowing transmit and receive of serial data. Pin descriptions are given in Table 12 .

Table 12. Queued Serial Peripheral Interface (QSPI) Signals

Serial Module Signal

QSPICLK/SUBR/GPIO25

RCK/QSPIDIN/QSPI_DOUT/GPIO26

RCK/QSPI_DIN/QSPI_DOUT/GPIO26

QSPI_DOUT/SFSY/GPIO27

Description

Multiplexed signal IIC interface clock or QSPI clock output

Function select is done via PLLCR register.

Multiplexed signal IIC interface data or QSPI data input.

Function select is done via PLLCR register.

QSPI data output

18

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

Freescale Semiconductor

Table 12. Queued Serial Peripheral Interface (QSPI) Signals (continued)

Serial Module Signal

QSPICS0/EBUIN4GPIO15

QSPICS1/EBUOUT2/GPIO16

QSPICS2/MCLK2/GPIO24

CS1/QSPICS3/GPIO28

4 different QSPI chip selects

Description

Signal Descriptions

4.17 Crystal Trim

The XTRIM/GPIO0 output produces a pulse-density modulated phase/frequency difference signal to be used after low-pass filtering to control varicap-voltage to control crystal oscillation frequency. This will lock the crystal to the incoming digital audio signal.

4.18 Clock Out

The MCLK1/GPIO11 and QSPI_CS2/MCLK2/GPIO24 can serve as DAC clock outputs. When programmed as DAC clock outputs, these signals are directly derived from the crystal oscillator or clock

Input (CRIN).

4.19 Debug and Test Signals

These signals interface with external I/O to provide processor debug and status signals.

4.19.1 Test Mode

The TEST[2:0] inputs are used for various manufacturing and debug tests. For normal mode TEST [2:1] should be ways be tied low. TEST0 should be set high for BDM debug mode and set low for JTAG mode.

4.19.2 High Impedance

The assertion of HI_Z will force all output drivers to a high-impedance state. The timing on HI_Z is independent of the clock.

NOTE

JTAG operation will override the HI_Z pin.

4.19.3 Processor Clock Output

The internal PLL generates this PSTCLK/GPIO51 and output signal, and is the processor clock output that is used as the timing reference for the Debug bus timing (DDATA[3:0] and PST[3:0]). The

PSTCLK/GPIO51 is at the same frequency as the core processor.

Freescale Semiconductor

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

19

Signal Descriptions

4.19.4 Debug Data

The debug data pins, DDATA0/CTS1/SDATA0_SDIO1/GPIO1, DDATA1/RTS1/SDATA2_BS2/GPIO2,

DDATA2/CTS0/GPIO3, and DDATA3/RTS0/GPIO4, are four bits wide. This nibble-wide bus displays captured processor data and break-point status.

4.19.5 Processor Status

The processor status pins, PST0/GPIO50, PST1/GPIO49, PST2/INTMON/GPIO48, and

PST3/INTMON/GPIO47, indicate the SCF5250 processor status. During debug mode, the timing is synchronous with the processor clock (PSTCLK) and the status is not related to the current bus transfer.

Table 13 shows the encodings of these signals.

.

Table 13. Processor Status Signal Encodings

(HEX)

$B

$C

$D

$E

$F

$7

$8

$9

$A

$3

$4

$5

$6

$0

$1

$2

PST[3:0]

Definition

(BINARY)

0111

1000

1001

1010

1011

1100

1101

1110

1111

0000

0001

0010

0011

0100

0101

0110

Continue execution

Begin execution of an instruction

Reserved

Entry into user-mode

Begin execution of PULSE and WDDATA instructions

Begin execution of taken branch or Synch_PC

1

Reserved

Begin execution of RTE instruction

Begin 1-byte data transfer on DDATA

Begin 2-byte data transfer on DDATA

Begin 3-byte data transfer on DDATA

Begin 4-byte data transfer on DDATA

Exception processing

2

Emulator mode entry exception processing

2

Processor is stopped, waiting for interrupt

2

Processor is halted

2

Rev. B enhancement.

These encodings are asserted for multiple cycles.

20

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

Freescale Semiconductor

Electrical Characteristics

4.20 BDM/JTAG Signals

The SCF5250 complies with the IEEE 1149.1A JTAG testing standard. The JTAG test pins are multiplexed with background debug pins.

4.21 Clock and Reset signals

These signals configure the SCF5250 and provide interface signals to the external system.

4.21.1 Reset In

Asserting RSTI causes the SCF5250SCF5250 to enter reset exception processing. When RSTI is recognized, the data bus is tri-stated.

4.21.2 Clock Input

SCF5250 includes on -chip crystal oscillator. The crystal should be connected between CRIN and CROUT.

An externally generated clock signal can also be used and should be connected directly to the CRIN pin.

4.22 Wake-Up Signal

To exit power down mode, apply a LOW level to the WAKE_UP/GPIO21 input pin.

4.23 On-chip Linear Regulator

The SCF5250 includes an on-chip linear regulator. This regulator provides an 1.2 V output which is intended to be used to power the SCF5250 core. Three pins are associated with this function.

LININ, LINOUT and LINGND. Typically LININ would be fed by the I/O (PAD) supply (3.3 V) with separate filtering recommended to provide some isolation between the I/O and the core.

In portable solutions this linear regulator may not be efficient enough and in this case we would expect the

1.2 V supply to be generated externally, possibly by a highly efficient DC-DC convertor.

If not used leave pins not connected.

5 Electrical Characteristics

Rating

Supply Core Voltage

Maximum Core Operating Voltage

Minimum Core Operating Voltage

Table 14. Maximum Ratings

Symbol

V cc

V cc

V cc

Value

-0.5 to +2.5

+1.32

+1.08

Units

V

V

V

Freescale Semiconductor

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

21

Electrical Characteristics

Rating

Table 14. Maximum Ratings (continued)

Symbol Value Units

Supply I/O Voltage

Maximum I/O Operating Voltage

Minimum I/O Operating Voltage

Input Voltage

Storage Temperature Range

V cc

V cc

V cc

V in

T stg

-0.5 to +4.6

+3.6

+3.0

-0.5 to +6.0

-65 to150

V

V

V

V o

C

Table 15. Operating Temperature

Characteristic Symbol Value Units

Maximum Operating Ambient Temperature T

Amax

85

1

ο

C

Minimum Operating Ambient Temperature T

Amin

-40 o

C

Note: This published maximum operating ambient temperature should be used only as a system design guideline. All device operating parameters are guaranteed only when the junction temperature does not exceed 105

°

C.

Table 16. Recommended Operating Supply Voltages

Pin Name

CORE-VDD

CORE-VSS

PAD-VDD

PAD-VSS

ADVDD

ADGND

OSCPAD-VDD

OSCPAD-GND

PLLCORE1VDD

PLLCORE1GND

PLLCORE2VDD

PLLCORE2GND

LIN

Min

1.08V

3.0V

3.0V

3.0V

1.08V

1.08V

3.0v

Typ

1.2V

gnd

3.3v

gnd

3.3v

gnd

3.3v

gnd

1.2V

gnd

1.2v

gnd

3.3V

Max

1.32V

---

3.6V

3.6V

3.6V

1.32V

1.32V

3.6V

22

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

Freescale Semiconductor

Electrical Characteristics

Table 17. Linear Regulator Operating Specification

Characteristic Symbol Min Typ Max

Input Voltage

Output Voltage (LINOUT)

Output Current

Power Dissipation

Vin

Vout

Iout

Pd

3.0V

1.14V

3.3V

1.2V

100mA

3.6

1.26V

150mA

436uW

Load Regulation

10% Iout -> 90% Iout

40mV 50mV 60mV

Power Supply Rejection PSRR 40dB

Note: A pmos regulator is employed as a current source in this Linear regulator, so a 10µF capacitor (ESR 0 ... 5 Ohm) is needed on the output pin (LINOUT) to integrate the current. Typically this will require the use of a Tantalum type capacitor.

Freescale Semiconductor

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

23

Electrical Characteristics

Table 18. DC Electrical Specifications (I/O Vcc = 3.3 Vdc + 0.3 Vdc)

Characteristic Symbol Min Max Units

Operation Voltage Range for I/O

Input High Voltage

Input Low Voltage

Input Leakage Current @ 0.0 V /3.3 V

During Normal Operation

Hi-Impedance (Three-State) Leakage Current

@ 0.0 V/3.3 V During Normal Operation

Output High Voltage I

OH

= 8mA

1

, 4mA

2

, 2mA

3

Output Low Voltage I

OL

= 8mA

1

, 4mA

2

, 2mA

3

Schmitt Trigger Low to High Threshold Point

6

Schmitt Trigger High to Low Threshold Point

6

Load Capacitance (DATA[31:16], SCLK[4:1], SCLKOUT,

EBUOUT[2:1], LRCK[3:1], SDATAO[2:1], CFLG, EF, DDATA[3:0],

PST[3:0], PSTCLK, IDE-DIOR, IDE-DIOW, IORDY)

V cc

V

IH

V

IL

I in

I

TSI

V

OH

V

OL

V

T+

V

T-

C

L

-

2.4

-

1.47

-

-

3.0

2

-0.3

-

3.6

5.5

0.8

±1

±1

- V

0.4

-

V

V

.95

50

V pF

V

V

V

µ

µA

µ

µA

Load Capacitance (ADDR[24:9], BCLK)

Load Capacitance (BCLKE, SDCAS, SDRAS, SDLDQM,

SD_CS0, SDUDQM, SDWE, BUFENB[2:1])

C

L

C

L

-

40

30 pF pF

Load Capacitance (SDA0, SDA1, SCL0, SCL1, CMD_SDIO2,

SDATA2_BS2, SDATA1_BS1, SDATA0_SDIO1, CS0/CS4, CS1,

OE, R/W, TA, TXD[1:0], XTRIM, TDO/DSO, RCK, SFSY, SUBR,

SDATA3, TOUT0, QSPID_OUT, QSPICS[3:0], GP[6:5])

Capacitance

5

, V in

= 0 V, f = 1 MHz

C

L

20 pF

C

IN

6 pF

DATA[31:16], ADDR[24:9], PSTCLK, BCLK

SCL, SDA, PST[3:0], DDATA[3:0], TDSO, SDRAS, SDCAS, SDWE, SD_CS0, SDLDQM, SDUDQM, R/W

TOUT0, RTS[1:0], TXD[1:0], SCLK[4:1]

BKPT/TMS, DSI/TDI, DSCLK/TRST

Capacitance C

IN

is periodically sampled rather than 100% tested.

SCLK[4:1], SCL0, SCL1, SDA0, SDA1, CRIN, RSTI

24

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

Freescale Semiconductor

Electrical Characteristics

Table 19. Clock Timing Specification

NUM Characteristic Units

Min Max

C5

C6

CRIN Frequency

1

PSTCLK cycle time

PSTCLK duty cycle

5.00

7.1

40

33.86

—

60

MHz nSec

%

C7 BCLK cycle time 14.2

— nSec

C8 BCLK duty cycle 45 55 %

Note: There are only three choices for the valid Audio frequencies 11.29 MHz, 16.93 MHz, or

33.86 MHz; no other values are allowed. The System Clock is derived from one of these crystals via an internal PLL.

CRIN

PSTCLK

C6

C7

C6

BCLK

C8

C8

Figure 2. Clock Timing Definition

NOTE

Signals above are shown in relation to the clock. No relationship between signals is implied or intended.

Freescale Semiconductor

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

25

Electrical Characteristics

Table 20. Input AC Timing Specification

Num Characteristic Units

Min Max

B1

1,2

B2

1

B3

1

Signal Valid to BCLK Rising (setup)

BCLK Rising to signal Invalid (hold)

3

2

—

— nSec nSec

BCLK to Input High Impedance — 5 BCLK cycle

1.

Inputs (rising): DATA[31:16]

2.

AC timing specs assume 40pF load capacitance on BCLK and 50pF load capacitance on output pins. If this value is different, the input and output timing specifications would need to be adjusted to match the clock load.

Table 21. Output AC Timing Specification

Num Characteristic

5

Units

Min Max

• B10

1

• B11

1

• B10

2

• B11

2

• B12

3

BCLK (8mA) Rising to signal Valid

BCLK (8mA) Rising to signal Invalid (hold)

BCLK (4mA) Rising to signal Valid

BCLK (4mA) Rising to signal Invalid (hold)

BCLK to High Impedance

(Three-State)

• H1 HIZ to High Impedance

---

3.5

---

4

---

10

—

11

—

14 nSec nSec nSec nSec nSec

— tbd nSec

• H2 HIZ to Low Impedance — tbd nSec

1.

Outputs (8mA): DATA[31:16], ADDR[25,23:9]

2.

Outputs (4mA): SDRAS, SDCAS, SDWE, SD_CS0, SDUDQM, SDLDQM, BCLKE

3.

High Impedance (Three-State): DATA[31:16]

4.

AC timing specs assume 40pF load capacitance on BCLK and a 50pF load capacitance on output pins. If this value is different, the input and output timing specifications would need to be adjusted to match the clock load.

26

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

Freescale Semiconductor

Electrical Characteristics

Figure 3. Input/Output Timing Definition-I

Freescale Semiconductor

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

27

Electrical Characteristics

BCLK

INPUTS

B3

BCLK

OUTPUTS

HIZ

OUTPUTS

B13

H1

Figure 4. Input/Output Timing Definition-III

B4

B14

H2

28

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

Freescale Semiconductor

PSTCLK

DSCLK

DSI

PST[3:0]

DDATA[3:0]

DSO

Electrical Characteristics

Table 22. Debug AC Timing Specification

Num Characteristic Units

Min Max

D1

D2

D3

1

PSTCLK to signal Valid (Output valid)

PSTCLK to signal Invalid (Output hold)

Signal Valid to PSTCLK (Input setup)

---

1.8

3

6

—

— nSec nSec nSec

D4 PSTCLK to signal Invalid (Input hold) 5 — nSec

1.

DSCLK and DSI are internally synchronized. This setup time must be met only if recognition on a particular clock is required.

2.

AC timing specs assume 50pF load capacitance on PSTCLK and output pins. If this value is different, the input and output timing specifications would need to be adjusted to match the clock load.

D3

D3

D1

D4

D4

D2

Figure 5. Debug Timing Definition

Freescale Semiconductor

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

29

Electrical Characteristics

Num

Table 23. Timer Module AC Timing Specification

Characteristic

T4

T5

T6

T7

T1

T2

T3

TIN Cycle time

TIN Valid to BCLK (input setup)

BCLK to TIN Invalid (input hold)

BCLK to TOUT Valid (output valid)

BCLK to TOUT Invalid (output hold)

TIN Pulse Width

TOUT Pulse Width

Min

— tbd

1T

1T

3T

6

0

Units

Max

10

—

—

—

—

—

— bus clocks nSec nSec nSec nSec bus clocks bus clocks

BCLK

TIN T2

T6

TIN

T3

T1

T7

TOUT

T4

Figure 6. Timer Module Timing Definition

T5

30

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

Freescale Semiconductor

Electrical Characteristics

Num

Table 24. UART Module AC Timing Specifications

Characteristic

U4

U5

U6

U7

U8

U1

U2

U3

RXD Valid to BCLK (input setup)

BCLK to RXD Invalid (input hold)

CTS Valid to BCLK (input setup)

BCLK to CTS Invalid (input hold)

BCLK to TXD Valid (output valid)

BCLK to TXD Invalid (output hold)

BCLK to RTS Valid (output valid)

BCLK to RTS Invalid (output hold)

Min

0

---

3

---

3

6

0

6

Max

— tbd

— tbd

—

—

—

—

Units nSec nSec nSec nSec nSec nSec nSec nSec

BCLK

U1

RXD

CTS

U3

U2

U4

U5

TXD

U6

U7

RTS

U8

Figure 7. UART Timing Definition

Freescale Semiconductor

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

31

Electrical Characteristics

Table 25. I2C-Bus Input Timing Specifications Between SCL and SDA

Num

M1

M2

M3

M4

M5

M6

M7

M8

Characteristic

Start Condition Hold Time

Clock Low Period

SCL/SDA Rise Time

(VIL= 0.5 V to VIH = 2.4 V)

Data Hold Time

SCL/SDA Fall Time

(VIH= 2.4 V to VIL = 0.5 V)

Clock High time

Data Setup Time

Start Condition Setup Time

(for repeated start condition only)

Stop Condition Setup Time

Min

2

8

—

0

—

4

0

2

Units

Max

—

—

1 bus clocks bus clocks mSec

—

1

—

—

— nSec mSec bus clocks nSec bus clocks

M9 2 — bus clocks

Table 26. I2C-Bus Output Timing Specifications Between SCL and SDA

Num Characteristic Units

Min Max

M1

M2

M3

M4

M5

M6

M7

M8

1

1

2

1

3

1

1

1

Start Condition Hold Time

Clock Low Period

SCL/SDA Rise Time

(V

IL

= 0.5 V to V

IH

= 2.4 V)

Data Hold Time

SCL/SDA Fall Time

(V

IH

= 2.4 V to V

IL

= 0.5 V)

Clock High time

Data Setup Time

Start Condition Setup Time

(for repeated start condition only)

Stop Condition Setup Time

6

10 note 2

7

—

10

2

20

—

— note 2

—

3

—

—

— bus clocks bus clocks mSec bus clocks nSec bus clocks bus clocks bus clocks

M9

1

10 — bus clocks

1.

Note: Output numbers are dependent on the value programmed into the MFDR; an MFDR programmed with the maximum frequency (MFDR = 0x20) will result in minimum output timings as shown in the above table. The MBUS interface is designed to scale the actual data transition time to move it to the middle of the SCL low period. The actual position is affected by the prescale and division values programmed into the MFDR; however, numbers given in the above table are the minimum values.

2.

Since SCL and SDA are open-collector-type outputs, which the processor can only actively drive low, the time required for SCL or SDA to reach a high level depends on external signal capacitance and pull-up resistor values.

3.

Specified at a nominal 20 pF load.

32

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

Freescale Semiconductor

Electrical Characteristics

SCL

M1

M2

M4

M6

M7 M8

M5

M3

M9

SDA

Figure 8. I2C Timing Definition

Table 27. I2C Output Bus Timings

96 MHz

Num Characteristic Units

Min Max

M10

3

SCL, SDA Valid to BCLK (input setup) 2 — nSec

1.

2.

3.

M11

M12

1

M13

2

BCLK to SCL, SDA Invalid (input hold)

BCLK to SCL, SDA Low (output valid)

4.5

—

—

10 nSec nSec

BCLK to SCL, SDA Invalid (output hold) 3 — nSec

Since SCL and SDA are open-collector-type outputs, which the processor can only actively drive low, this specification applies only when SCL or SDA are driven low by the processor. The time required for SCL or

SDA to reach a high level depends on external signal capacitance and pull-up resistor values.

Since SCL and SDA are open-collector-type outputs, which the processor can only actively drive low, this specification applies only when SCL or SDA are actively being driven or held low by the processor.

SCL and SDA are internally synchronized.This setup time must be met only if recognition on a particular clock is required.

Freescale Semiconductor

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

33

Electrical Characteristics

BCLK

SCL, SDA IN

M10

M11

SCL, SDA OUT

M12

SCL, SDA OUT

M13

Figure 9. I2C and System Clock Timing Relationship

Num

Table 28. General-Purpose I/O Port AC Timing Specifications

Characteristic

P1

P2

P3

P4

GPIO Valid to BCLK (input setup)

BCLK to GPIO Invalid (input hold)

BCLK to GPIO Valid (output valid)

BCLK to GPIO Invalid (output hold)

Units

Min

—

1

6

0

Max

—

— tbd

— nSec nSec nSec nSec

34

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

Freescale Semiconductor

Electrical Characteristics

BCLK

P1

GPIO IN

P2

P3

GPIO OUT

P4

Figure 10. General-Purpose Parallel Port Timing Definition

Table 29. IEEE 1149.1 (JTAG) AC Timing Specifications

-

J1

J2a

J2b

J3a

J4

J5

J6

J7

J8

Num

J3b

J9

J10

J11

Characteristic

TCK Frequency of Operation

TCK Cycle Time

TCK Clock Pulse High Width

TCK Clock Pulse Low Width

TCK Fall Time

(V

IH

=2.4 V to V

IL

=0.5 V)

TCK Rise Time

(V

IL

=0.5 v to V

IH

=2.4 V)

TDI, TMS to TCK rising (Input Setup)

TCK rising to TDI, TMS Invalid (Hold)

Boundary Scan Data Valid to TCK (Setup)

TCK to Boundary Scan Data Invalid to rising edge (Hold)

TRST Pulse Width

(asynchronous to clock edges)

TCK falling to TDO Valid

(signal from driven or three-state)

TCK falling to TDO High Impedance

TCK falling to Boundary Scan Data Valid

(signal from driven or three-state)

Min

0

100

25

25

—

—

—

—

—

8

10 tbd tbd

12

Max

10

-

-

-

5

5

15

15 tbd

—

—

—

—

—

Units nSec nSec nSec nSec

MHz nSec nSec nSec nSec nSec nSec nSec nSec nSec

Freescale Semiconductor

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

35

Electrical Characteristics

Table 29. IEEE 1149.1 (JTAG) AC Timing Specifications (continued)

Num Characteristic

J12 TCK falling to Boundary Scan

Data High Impedance

Units

Min

—

Max tbd nSec

J1

J3A

TCK J2A J2B

J4

J3B

TDI, TMS

BOUNDARY

SCAN DATA

INPUT

J6

J5

J7

TRST

J8

J9

TDO

BOUNDARY

SCAN DATA

OUTPUT

J11

J10

J12

Figure 11. JTAG Timing

36

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

Freescale Semiconductor

Electrical Characteristics

5.1

IIS Module AC Timing Specifications

Table 30. SCLK INPUT, SDATAO OUTPUT Timing Specifications

Name Characteristic

TU SCLK fall to SDATAO rise

TD SCLK fall to SDATAO fall

Min

---

---

Max

25

25

Unit ns ns

SCLK (INPUT)

SDATAO1, 2 (OUTPUT)

TU TD

Figure 12. SCLK Input, SDATA Output Timing

Name

TU

TD

Table 31. SCLK OUTPUT, SDATA0 OUTPUT Timing Specifications

Characteristic

SCLK fall to SDATAO rise

SCLK fall to SDATAO fall

Min

---

---

Max

3

3

Unit ns ns

SCLK (OUTPUT)

SDATAO1, 2 (OUTPUT)

TU TD

Figure 13. SCLK Output, SDATAO Output Timing Diagram

Freescale Semiconductor

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

37

Pin-Out and Package Information

Table 32. SCLK INPUT, SDATAI INPUT Timing Specifications

Name Characteristic

TSU SDATAI IN to SCLKn

TH SCLK rise to SDATAI

Min

-5

3

Max

—

—

Unit ns ns

(

SCLK

INP UT OR OUTPUT )

SDATA1, 3, 4 (INPUT)

TSU TH

Figure 14. SCLK Input/Output, SDATAI Input Timing Diagram

6 Pin-Out and Package Information

6.1

Pinning Chart

Table 33. 144 QFP Pin Assignments

144 QFP

Pin

Number

01

02

Name

DATA16

A23/GPO54

Type Description

I/O

I/O

Data

SDRAM address / static adr

Pin State

After Reset

X

Out (requires pull up /down for boot-up selection)

03

04

05

06

07

08

PAD-VDD

A22

A21

A20/A24

A19

A18

O

O

O

O

O

SDRAM address / static adr

SDRAM address / static adr

SDRAM address / static adr

SDRAM address / static adr

SDRAM address / static adr

Out

Out

Out

Out

Out

38

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

Freescale Semiconductor

144 QFP

Pin

Number

21

22

23

24

17

18

19

20

13

14

15

16

09

10

11

12

29

30

31

25

26

27

28

32

33

34

Table 33. 144 QFP Pin Assignments (continued)

Pin-Out and Package Information

Name Type Description

Pin State

After Reset

A11

CORE-VDD

CORE-GND

A10

A9

A8

A7

A6

PAD-GND

A17

A16

A15

A14

A13

PAD-VDD

A12

A5

PAD-GND

A4

A3

A2

A1

CS0/CS4

O

O

O

O

O

O

O

O

O

O

O o o

O o o

O

O o

SDRAM address / static adr

SDRAM address / static adr

SDRAM address / static adr

SDRAM address / static adr

SDRAM address / static adr

SDRAM address / static adr

SDRAM address / static adr

SDRAM address / static adr

SDRAM address / static adr

SDRAM address / static adr

SDRAM address / static adr

SDRAM address / static adr

SDRAM address / static adr

PAD-GND

SDRAM address / static adr

SDRAM address / static adr

SDRAM address / static adr

SDRAM address / static adr

Static chip select 0 / static chip select 4

Bus write enable

Out

Out

Out

Out

Out

Out

Out

Out

Out

Out

Out

Out

Out

Out

Out

Out

Out

Out

Out RW

OSC PAD VDD

CRIN I Crystal / external clock input X

Freescale Semiconductor

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

39

Pin-Out and Package Information

Table 33. 144 QFP Pin Assignments (continued)

51

52

53

54

55

56

144 QFP

Pin

Number

39

40

41

42

35

36

37

38

43

44

45

46

47

48

49

50

Name

CROUT

OSC PAD GND

PLL CORE1 VDD

PLL CORE2 VDD

PLL CORE2 GND

PLL CORE1 GND

OE

IDE-DIOW/GPIO32

IDE-IORDY/GPIO33

IDE-DIOR/GPIO31

BUFENB2/GPIO30

BUFENB1/GPIO29

TA/GPIO12

WAKE_UP/

GPIO21

EBUIN2/SCLK_OUT/

GPIO13

EBUIN3/CMD_SDIO2/

GPIO14

PAD VDD

EBUIN1/GPIO36

EBUOUT1/GPIO37

XTRIM/GPIO0

CS1/QSPI_CS3/GPIO28

RCK/

QSPI_DIN/QSPI_DOUT/

GPIO26

Type

O

I/O

I/O

I/O

O

I/O

I/O

I/O

I/O

I/O

I/O

Description

Crystal clock output

OSC_PAD_GND

Output Enable

IDE DIOW

IDE interface IORDY

IDE interface DIOR

External buffer 2 enable

External buffer 1 enable

Transfer acknowledge

Wake-up input

Audio interfaces EBU in 2 /

FlashMedia Clock

Audio interfaces EBU in 3 /

FlashMedia Command interface

X

Pin State

After Reset

Out

Out / HIGH

In / LOW

Out / HIGH

Out / HIGH

Out / HIGH

In (requires pull-up for normal operation)

In (requires pull-up for normal operation)

In / LOW

In / LOW

I/O

I/O

I/O

I/O

I/O

Audio interfaces EBU in 1

Audio interfaces EBU out 1

Audio interfaces X-tal trim

In / LOW

Out / LOW

Out / clock out

Chip select 1/ QSPI Chip Select 3 Out / HIGH

Subcode RCK interface /

QSPI Data In / Data Out

Out / LOW

40

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

Freescale Semiconductor

Table 33. 144 QFP Pin Assignments (continued)

Pin-Out and Package Information

73

74

75

76

69

70

71

72

77

78

79

144 QFP

Pin

Number

57

58

59

60

61

62

63

64

65

66

67

68

Name

QSPI_CLK/SUBR/

GPIO25

QSPI_DOUT/SFSY/

GPIO27

QSPI_CS1/EBUOUT2/

GPIO16

QSPI_CS0/EBUIN4/

GPIO15

PAD GND

SCLK1/GPIO20

LRCK1/GPIO19

SDATAO1/TOUT0/

GPIO18

SDATAI1/GPIO17

CFLG/GPIO5

EF/GPIO6

QSPI_CS2/MCLK2/

GPIO24

SDATAI3/GPIO8

ADIN0/GPI52

ADIN1/GPI53

ADIN2/GPI54

ADVDD

ADGND

ADIN3/GPI55

ADIN4/GPI56

ADIN5/GPI57

ADREF

ADOUT/SCLK4/

GPIO58

Type Description

I/O

I/O

I/O

QSPI Data Output / subcode interface SFSY

QSPI Chip select 1 output / audio interface EBU output 2

QSPI chip select 0 / audio interface EBUIN 4

A

A

A

A

I/O

AD input 3

AD input 4

AD input 5

ADC reference input

AD output / SCLK4

(for GPI function in low power applications)

Pin State

After Reset

I/O QSPI clock pin / subcode interface Out / LOW

Out / LOW

Out / LOW

Out / LOW

I/O

I/O

I/O

I

I/O

I/O

I/O

I/O

A

A

A

Audio interfaces serial clock 1

Audio interfaces word clock 1

Audio interfaces serial data output 1 / Timer output 0

Audio interfaces serial data in 1

In / LOW

In / LOW

Out / LOW

CFLG input

Error flag input

QSPI Chip Select output 2 / audio master clock output 2

In / LOW

In / LOW

In / LOW

Out / LOW

Audio interfaces serial data input 3 In / LOW

AD input 0 In only

AD input 1

AD input 2

In only

In only

In only

In only

In only

In

Out / clock output

Freescale Semiconductor

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

41

Pin-Out and Package Information

Table 33. 144 QFP Pin Assignments (continued)

144 QFP

Pin

Number

80

Name Type

I/O

Description

81

82

83

84

85

86

87

88

LRCK3/GPIO43/

AUDIO_CLOCK

SCLK3/GPIO35

SCL0/SDATA1_BS1/

GPIO41

SDA0/SDATA3/

GPIO42

DDATA0/CTS1/

SDATA0_SDIO1/

GPIO1

DDATA1/RTS1/

SDATA2_BS2/GPIO2

DDATA2/CTS0/GPIO3

DDATA3/RTS0/GPIO4

SCL1/TXD1/GPIO10

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

Pin State

After Reset

Audio interface LRCK3 /

Audio master clock input

Audio interface SCLK3

I2C0 clock line / FlashMedia

Data interface

I2C0 data / FlashMedia data interface

Debug / UART1 CTS / FlashMedia data interface

In / LOW

In / LOW

Out / LOW

Hi-Z

Out / HIGH

Debug / UART1 RTS / FlashMedia data interface

Debug / UART0 CTS

Debug / UART0 RTS

I2C1 clock line / second

UART transmit data output

Out / HIGH

Out / HIGH

Out / HIGH

Out / LOW

89

90

91

CORE VDD

CORE GND

SDA1/RXD1/GPIO44 I/O I2C1 data line / second UART receive data input

Hi-Z

97

98

99

100

101

92

93

94

95

96

PAD VDD

TXD0/GPIO45

RXD0/GPIO46

PST3/INTMON1/

GPIO47

PST2/INTMON2/

GPIO48

PAD GND

PST1/GPIO49

PST0/GPIO50

PSTCLK/GPIO51

TDO/DSO

I/O

I/O

I/O

I/O

I/O

I/O

I/O

O

First UART transmit data output Out / HIGH

First UART receive data input In / LOW

Debug / interrupt monitor output 1 Out / HIGH

Debug / interrupt monitor output 2 Out / HIGH

Debug

Debug

Debug

JTAG/debug

Out / HIGH

Out / HIGH

Out / clock output

BDM

42

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

Freescale Semiconductor

144 QFP

Pin

Number

122

123

124

125

118

119

120

121

126

127

128

114

115

116

117

110

111

112

113

106

107

108

109

102

103

104

105

Table 33. 144 QFP Pin Assignments (continued)

Pin-Out and Package Information

Name Type Description

Pin State

After Reset

TDI/DSI

TCK

TMS/BKPT

TRST/DSCLK

RSTI

SCLK2/GPIO22

LRCK2/GPIO23

LINOUT

LININ

LINGND

SDATAO2/GPIO34

MCLK1/GPIO11

HI-Z

TEST2

TEST1

TEST0

SDWE/GPIO38

SDCAS/GPIO39

PAD VDD

SDRAS/GPIO59

SD_CS0/GPIO60

SDLDQM/GPO52

SDUDQM/GPO53

BCLKE/GPIO63

BCLK/GPIO40

DATA31

DATA30

I

I/O

I/O

A

A

I

I

I

I

I/O

I/O

I

I

I

I

I/O

I/O

JTAG/debug

JTAG

JTAG/debug

JTAG/Debug

Reset

Audio interfaces serial clock 2

Audio interfaces EBU out 1

Linear regulator output

BDM

BDM

BDM

BDM

X

In / LOW

In /LOW

X

Linear regulator input

Linear regulator ground

X

X

Audio interfaces serial data output 2 Out / LOW

Audio master clock output 1 Out / clock output

JTAG

Test

Test

Test

SDRAM write enable

SDRAM CAS

X

X

X

X

Out / HIGH

Out / HIGH

O

I/O

I/O

I/O

I/O

I/O

I/O

O

SDRAM RAS

SDRAM chip select out 0

SDRAM LDQM

SDRAM UDQM

SDRAM clock enable output

SDRAM clock output

Data

Data

Out / HIGH

Out / HIGH

Out / HIGH

Out / HIGH

Out / HIGH

Out / HIGH

X

X

Freescale Semiconductor

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

43

Pin-Out and Package Information

Table 33. 144 QFP Pin Assignments (continued)

144 QFP

Pin

Number

141

142

143

144

137

138

139

140

133

134

135

136

129

130

131

132

Name

DATA23

DATA22

DATA21

DATA20

PAD GND

DATA19

DATA18

DATA17

PAD GND

DATA29

DATA28

DATA27

DATA26

DATA25

PAD-VDD

DATA24

Type

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

Data

Data

Data

Data

Data

Data

Data

Data

Data

Data

Data

Data

Data

Description

X

X

X

X

X

X

X

X

X

X

X

X

X

Pin State

After Reset

6.2

Package

The SCF5250 is assembled in 144-pin QFP package. Thermal characteristics are not available at this time.

44

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

Freescale Semiconductor

THIS PAGE INTENTIONALLY LEFT BLANK

Freescale Semiconductor

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

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46

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

Freescale Semiconductor

THIS PAGE INTENTIONALLY LEFT BLANK

Freescale Semiconductor

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

47

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Document Number: SCF5250

Rev. 1.1

04/2005