Intel 8080 CPU Electronics User Manual

1/0 INTERFACE
Ganeral Theory
As in any computer based system, the 8080 CPU must
be able to communicate with devices or structures that exist
outside its normal memory array, Devices like keyboards,
paper tape, floppy disks, printers, displays and other control
structures are used to input information into the BOSO CPU
and display or store the results of the computational activity.
Probably the most important and strongest feature of
the 8080 Microcomputer System is the flexibility and power
of its 1/0 structure and the components that support it. There
are many ways to structure the 1/0 array so that it will “fit”
the total system environment to maximize efficiency and
minimize component count.
The basic operation of the 1/0 structure can best be
viewed as an array of single byte memory locations that can
be Read from or Written into. The BOBO CPL has special in-
structions devoted to managing such transfers (IN, QUT).
These instructions generally isolate memory and 1/0 arrays
so that memory address space is not effected by the 1/0
structure and the general concept is that of a simple transfer
to or from the Accumulator with an addressed "PORT". An-
other method of 1/0 architecture is to treat the 1/0 structure
as part of the Memory array. This is generally referred to as
“Memory Маррей 1/07 and provides the designer with a
powerful new "instruction set’ devoted to |/O manipulation,
SOLATED | 5
a N ASK à
Ja 1
| MEMORY |
| |
| © 256 |
| i
1-9 1
1
| i
Fm mm mm ———— À
| à AZM B5K y
| 1
| |
| MEMORY He '
| 3
|
MEMORY MAPRPER I OO
E O == === === TT TE свя оны —— — о —
Figure 3-8. Memeory/t/0 Mapging.
Isolated 1/0
In Figure 3-9 the system control signals, previously de-
tailed in this chapter, are shown, This type of I/O architecture
separates the memory address space from the 1/0 address
space and uses a conceptually simple transfer to or from Ac-
cumulator technique. Such an architecture is easy to under-
stand because 1/Q communicates only with the Accumulator
using the IN or QUT instructions. Also because of the isola
tion of memory and 1/0, the full address space (65K) is un-
effected by 1/0 addressing.
3-8
MEMA
_— TOMEMORY
- DEVICES
MEMW |
SYSTEM
CONTROL
(R228)
—
vor |
Г TO VO DEVICES
Figure 3-9. Isolated 1/0.
Mamory Mapped 1/0
By assigning an arez of memory address space as 1/0 a
powerful architecture can be developed that can manipulate
10 using the same instructions that are Used to manipulate
memory locations, Thus, a “new” instruction set is created
that is devoted to 1/0 handling.
As shown in Figure 3-10, new control signals are gene-
rated by gating the MEMA and MEMW signals with 445, the
most significant address bit. The new 1/0 control signals con-
nect in exactly the same manner as Isolated 1/0, thus the
system bus characteristics are unchanged.
By assigning Ads as the 1/0 “flag”, a simple method of
1/0 discipline is maintained:
If A116 is a “zero” then Memaory is active.
If Ads is a “one” then 1/0 is active.
Other address bits can also be used for this function. À 15 was
chosen because it is the most significant address bit so it is
easier to control with software and because it still allows
memory addressing of 37K.
1/0 devices are still considered addressed “ports” but
instead of the Accumulator as the only transfer medium any
of the internal registers can be used. All instructions that
could be used to operate on memory locations can be used
in 170.
Examples:
MOVr, M {Input Port to any Register]
MOV Mr (Output any Register to Port!
MYI M [Output immediate data to Port)
LOA {Input to ACC)
STA (Output from ACC to Part)
LHL (16 Bit Input}
SHLD (16 Bit Output!
ADD M (Add Port ta ACC]
ANA M ('ANC” Port with ACC)
it is easy to see that from the list of possible “new”
Instructions that this type of 1/0 architecture could have a
drastic effect on increased system throughput, It is concép-
tually more difficult to understand than Isolated 1/0 and it
does limit memory address space, but Memory Mapped 1/0
can mean a significant increase in overall speed and at the
same time reducing required program memory area.
+ + МЕМЯ то
: L MEMORY
-
SYSTEM
CONTROL ДН
187781 оной’ ar FER
USED _ TONO
КАИ 1 DEVICES
TW IMM) |
Aig
Figure 3-10. Memory Mapped 1/0.
1/0 Addressing
With both systems of |/O structure the addressing of
each device can be configured to optimize efficiency and re-
duce component count, One method, the most common, 1$
to decode the address bus into exclusive “chip selects” that
enable the addressed 1/0 device, similar to generating chip-
selects in memory arrays.
Another method is called “linear select”. in this method,
instead of decoding the Address Bus, a singular bit from the
bus is assigned as the exclusive enable for a specific 1/0 de-
vice. This method, of course, limits the number of 1/0 de-
vices that can be addressed but eliminates the need for extra
decoders, an important consideration in small system design,
A simple example illustrates the power of such a flexi-
ble 1/0 structure, The first example illustrates the format of
the second byte of the IN or QUT instruction using the lso:
lated 1/0 technique, The devices used are Intel“8255 Pro-
grammable Peripheral Interface units and are linear selected,
Each device has three ports and from the format it can be
seen that six devices can be addressed without additional de-
coders.
EXAMPLE #1
|| 5 |5 | ^ | 5 |3, ® |» |
| ||
POAT SELECTS
| _ _— —
DEVICE SELECTS
ADORMESSES — E - №2554
118 PORTE — 144 BITE]
Figure 3-11. Isolated 1/0 — [Linear Select) (8255)
3-9
The second example uses Memory Mapped 1/0 and
linear select to show how thirteen devices (8295) can be ad-
dressed without the use of extra decoders. The format shown
could be the second and third bytes of the LDA or STA in-
structions or any other instructions used to manipulate 1/0
using the Memory Mapped technique.
It is easy to see that such a flexible HO structure, that
can be “tailored” to the overall system environment, provides
the designer with a powerful tool to optimize efficiency and
minimize component count.
EXAMPLE #2
EE Ay EE
— 1
| | | | POAT SELECTS
N
loo,
DEVICE SELECTS
Ag Aga | Aaa Az! Aaa A0 Ag a
rol
! Li DEVICE SELECTS
Пс
|
| |
eo
De MEMORY
l'O FLAG
ADDRESSES — 13 - 82564
139 PORTS — 317 BITSI
Figure 3-12. Mamory Mappad 1/0 — (Linear Select (8255)
1/0 Interface Example
In Figure 3-16 a typical 1/0 system is shown that uses a
variety of devices (8212, 8251 and 82551, It could be used
to interface the peripherals around an intelligent CRT termi
nals: keyboards, display, and communication interface. An-
other application could be in à process controller to interface
sensors, relays, and motor controls. The limitation of the ap-
plication area for such a circuit is solely that of the designers
imagination.
The I/O structure shown interfaces то the 8080 CPU
using the bus architecture developed previously in this chap-
ter. Either lsalated or Memory Mapped techniques can be
used, depending on the system 1/0 environment,
The 8251 provides a serial data communication inter-
face so that the system can transmit and receive data over
communication links such as telephone lines.
| _ Y = DATA
CC CONTROL 1 — COMMAND
8751 SELECT
(ACTIVE LOW!
The three 82125 can be used to drive long lines or LED
indicators due to their high drive capability. (15mA)
Figure 3-13. 8257 Format.
The two (21 82555 provide twenty four bits each of
programmable 1/0 data and control so that keyboards, sen-
8212 =1 SELECT
ACTIVE HIGH]
8212 22 SELECT
ACTIVE HIGH]
8212 =3 SELECT
{ACTIVE HIGH!
|» |415 |! |+ |+ XTX
I
sors, paper tape, etc, can be interfaced to the system.
CTA]
Te]
L
11 — COMMAND
PORT SELECT
Figura 3-15. 8212 Format.
20 — PORT А
OT — PORT 8
10 — PORT £
Addressing the structure is described in the formats il-
lustrated in Figures 3-13, 3-14, 3-15. Linear Select is used so
that nc decoders are required thus, each device has an ex-
clusive “enable bit”.
9456 51 SELECT
| 4006 «e SELECT The example shows how a powerful yet flexible 1/0
{ACTIVE LOW structure can be created using a minimum component count
with devices that are all members of the 8080 Microcomputer
System,
Figure 3-14. 8255 Format.
SERIAL DATA
COMMUNICATION {1 |
! | | | {1 0 |}
47 =1
8261 EZ55 ATES
RD WA 0501 CE C6 AD WR 07D, CE Ay Ay AD WA В,б, 5 My A:
1 A
“| Е {3 |e Ay | o o Ba |A, | À
я DATA BUS `
F
Г
|
r
[
CONTROL BUS
|
|
|
|
A
AUDRHESS BUS
|
А;
4
#12
#3
gp
5
kl
MD
cn
081 DE
Figure 3-16. Typical 1/0 Interface.
+10
CAMP
ca? So
e
A.
A computer, no matter how sophisticated, can only
do what it is told” to do. One tells” the computer what
to do via a series of coded instructions referred to as a Pro-
gram. The realm of the programmer (5 referred to as Soft-
ware, in contrast to the Hardware that comprises the actual
computer equipment, Á computer's software refers to all of
the programs that have been writtan for that computer.
When a computer is designed, the engineers provide
the Central Processing Unit (CPU) with the ability to per-
form a particular set of operations. The CPU is designed
such that a specific operation is performed when the CPU
control logic decodes a particular instruction, Consequently,
the operations that can be performer by a CPU define the
computer's Instruction Set.
Each computer instruction allows the programmer to
initiate the performance of a specific operation, All com-
puters implement certain arithmetic operations in their in-
struction set, such as an instruction to add the contents of
two registers. Often logical operations leg, OR the con-
tents of two registers) and register operate instructions fe.g.,
increment a register) are included in the instruction set. A
computers instruction set will also have instructions that
move data between registers. between aregister and memaory,
and between a register and an 1/0 device, Most instruction
sets also provide Conditional Instructions. & conditional
instruction specifies an operation to be performed only if
certain conditions have been met; for example, jump to a
particular instruction ¡f the result of the last operation was
zero. Conditional instructions provide a program with a
decision-making capability,
By logically organizing a sequence of instructions into
a coherent program, the programmers can “tell” the com-
puter to perform a vary specific and useful function.
The computer, however, can only execute programs
whose instructions are in a binary coded form (i.e. a series
of 1's and 0's), that is called Machine Code. Because it
would be extremely cumbersome to program in machine
code, programming languages have been developed. There
4-1
are programs available which convert the programming lan-
quage instructions into machine code that can be inter-
preted by the processor.
One type of programming language is Assembly Lan-
guage, À unique assembly language mnemenic is assigned to
each of the computers instructions, The programmer can
write a program (calied the Source Program) using these
mnemontes and certain operands; the source program 15
then converted into machine instructions (called the Object
Code). Each assembly language instruction is converted into
one machine code instruction (1 or more bytes) by an
Assembler program. Assembly languages are usually ma-
chine dependent (Le,, they are usualiy able to run on only
one type of computer].
THE 8080 INSTRUCTION SET
The 8080 instruction set includes five differant types
of instructions:
« Data Transfer Group—move data between registers
or between memory and registers
«e Arithmetic Group — add, subtract, increment or
decrement data in registers or in memory
e Logical Group — AND, OR, EXCLUSIVE-OR,
compare, rotate or complement data in registers
or in memory
« Branch Group — conditional and unconditional
jump instructions, subroutine call instructions and
return instructions
« Stack, 1/0 and Machine Control Group — includes
1/0 instructions, as well as instructiens for main-
taining the stack and internal control flags.
Instruction and Data Formats:
Memory for the 8080 is organized into 8-bit quanti-
ties, called Bytes. Each byte has à unique 15-bit binary
address corresponding to its sequential position in memory.
The 8080 can directly address up to 65 536 bytes of mem-
ary, which may consist of both read-only memory (ROM)
elements and random-access memory (RAM) elements (read/
write memoryi.
Data in the 8080 is stared in the form of 8-bit binary
integers:
DATA WORD
| |
C5 De De Da Ds Ds D, Do
MEE LSB
When a register ar data word contains a binary num:
ber, it 15 necessary to establish the order in which the bits
of the number are written, In the Intel 8080, BIT © is re-
ferred to as the Least Significant Bit (LSB), and BIT 7 {of
an 8 bit number} 15 referred to as the Most Significant Bit
{MSE}.
The BOBO program instructions may be one, two or
three bytes in length, Multiple byte instructions must be
stored in successive memory locations; the address of the
first byte is always used as the address of the instructions.
The exact instruction format will depend on the particular
operation to be executed.
Single Byte Instructions
E BE “Do | Op Code
Two-Byte instructions
] | | | |
Byte One | 0, | Do | Op Code
| | | | | | | Dat
Byte Two | Dy Do | Data or
Address
Three-Byte Instructions
Byte One | D, ) ' | ' ' Ba | Op Code
E
Byte Two | р, | ' ! Data
or
Byte Three | О; | Address
Addressing Modes:
Often the data that is to be operated on is stored in
memory. When multi-byte numeric data is used, the data,
like instructions, Is stored in successive memory locations,
with the least significant byte first, followed by increasingly
significant bytes. The 8080 has four different modes for
addressing data stored in memory or in registers:
e Direct — Bytes 2 and 3 of the instruction contain
the exact memory address of the data
item (the low-order bits of the address are
in byte 2, the high-order bits in byte 3),
e Register — The instruction specifies the register or
register-pair in which the data is located,
e Register indirect — The instruction specifies a reg-
ister-pair which contains the memory
4.2
address where the data is located (the
high-order bits of the address are in the
first register of the pair, the low-order
hits in the second).
* Immediate — The instruction contains the data it-
self. This is either an 8-bit quantity or a
16-bit quantity {least significant byte first,
mast significant byte second).
Unless directed by an interrupt or branch instruction,
the execution of instructions proceeds through consecu-
tively increasing memory locations, À branch instruction
tan specify the address of the next instruction to be exe-
cuted in one of two ways:
e Direct — The branch instruction contains the ad-
dress of the next instruction to be exe-
cuted. {Except for the ‘AST’ instruction,
byte 2 contains the low-order address and
byte 3 the high-order address.)
indirect — The branch instruction indi-
cates a register-pair which contains the
address of the next instruction to be exe-
cuted. |The high-order bits of the address
are in the first register of the pair, the
low-order bits in the second.)
& Register
The RST instruction is a special one-byte call instruc-
tion {usually used during interrupt sequences). BST in-
cludes a three-bit field; program control is transferred to
the instruction whose address 15 eight times the contents
af this three-bit field.
Condition Flags:
There are five condition flags associated with the exe-
cution of instructions on the 8080. They are Zero, Sign,
Parity, Carry, and Auxiliary Carry, and are esch represented
by a i-tit register ın the CPU, A flag is “'set’’ by forcing the
bit 10 1; “reset” by forcing the bit to Q.
Unless indicated otherwise, when an instruction af.
fects a flag, it affects it in the following manner:
Zero: If the result of an instruction has the
value 0, this flag is set; otherwise it is
reset.
sign: If the most significant bit of the result of
the operation has the value 1, this flag is
set: otherwise it is reset.
If the modulo 2 sum of the bits of the re-
sult of the opération is 0 {i.a., if the
result has even parity), this flag is set;
otherwise it is reset (i.e. if the result has
odd parity),
Parity:
Carry: If the instruction resulted in a carry
(from addition), or a borrow {fram sub-
traction or a comparison) out of the high-
order bit, this flag is set; otherwise it is
reset,
Auxiliary Carry: If the instruction caused a carry out
of hit 3 and into bit 4 of the resulting
value, the auxiliary carry is set; otherwise
it is reset. This flag is affected by single
precision additions, subtractions, incre.
ments, decrements, comparisons, and log-
ical operations, but is principally used
with additions and increments preceding
a DAA (Decimal Adjust Accumulator)
Instruction,
Symbols and Abbreviations:
The following symbols and abbreviations are used in
the subsequent description of the 8080 instructions:
SYMBOLS
accumulator
addr
data
data 16
byte 2
byte 3
port
rrir2
DDD, SSS
Pp
HP
MEANING
Register A
16-bit address quantity
8-bit data quantity
18-bit data quantity
The second byte of the instruction
The third byte of the instruction
8-bit address of an 1/( device
One of the registers A,B.C.D EH L
The bit pattern designating ong of the regis-
ters AB.COD,E,H,L (DOD=destination, 555=
source! :
ODO or 55% REGISTER NAME
111 A
000 B
001 C
010 GC
011 E
100 H
101 L
One of the register pairs:
B represents the B,C pair with B as the high-
order register and C as the low-order register;
D represents the D,E pair with O as tha high-
order register and E as the low-order register;
H represents the H,L pair with H as the high-
order register and L as the low-order register,
SP represents the 16-bit stack pointer
register.
The bit pattern designating one of the regis-
ter pairs §,0,H SP:
RP REGISTER PAIR
00 B-C
O1 D-E
10 H-L
11 SP
4-3
rh
ri
PC
SP
г
Z5PCY AC
> li * 1 4 S +>1
NNN
The first (high-order) register of a designated
register pair,
The second {low-order} register of a desig
nated register pair.
16-bit program counter register (PCH and
PCL are used to refer to the high-order and
low-order 8 bits respectively).
18-bit stack pointer register ISPH and SPL
are used to refer to the high-order and {ow-
order 8 bits respectively].
Bit m of the register r (bits are number 7
through O from left to right).
The condition flags:
Zero,
Sign,
Parity,
Carry,
and Auxiliary Carry, respectively.
The contents of the memory location or reg-
isters enciosed in the parentheses.
"1s transferred to”
Logical AND
Exclusive OR
Inclusive OR
Addition
Two's complement subtraction
Multiplication
“ls exchanged with”
The one's complement (e.g., LA}}
The restart number O through 7
The hinary representation 000 through 111
for restart number O through 7 respectively.
Descrintion Format:
The following pages provide a detailed description of
the instruction set of the BOBO, Each instruction is de-
scribed in the following manner;
1. The MAC 80 assembler format, consisting of
the instruction mnemonic and operand fields, is
printad in BOLDFACE on the left side of the first
lina,
2. The name of the instruction is enclosed in paren:
thesis on the right side of the first line,
3, The next line{s} contain a symbolic description
of the operation of the instruction.
4. This is followed by a narative description of the
operation of the instruction.
5. The following linejs) contain the binary fields and
patterns that comprise the machine instruction.
6, The last four lines contain incidental information
about the execution of the instruction. The num-
ber of machine cycles and states required to exe-
cute the instruction are listed first, If the instruc-
tion has two possible execution times, as in a
Conditional Jump, both times will be listed, sep-
arated by a slash. Next, any significant data ad-
dressing modes {see Page 4-2) are listed. The last
line lists any of the five Flags that are affected by
the execution of the instruction,
Data Transfer Group:
This group of instructions transfers data to and from
registers and memory. Condition flags are not affected by
any instruction in this group.
MOV 1, r2 (Move Register!
fr1} —— (r2}
The content of register r2 is moved to register rl.
|o'1|0'n'o s ss;
MY| r, data
fr} =— (byte 21
The content of byte 2 of
register r,
{Move Immediate)
the instruction 15 moved to
o ololelolililo
data
Cycles: 2
States: 7
Addressing: immediate
Flags: none
MY! M, data
(HI (LIN -— (byte 2)
The content of byte ? of
(Move to memory immediate)
the instruction is moved to
the memory location whose address is in registers H
and L.
Cycles: 1 T | | | | | |
States: 5 0 0 1 1 0 1 1 0
Addressing: register data
Flags: none
Cycles: 3
States: 10
Addressing: immed reg, indirect
МОУ к, М ¡Move from memory! + 7 | E
Flags: none
{re} >— CH] 613)
The content of the memory location. whose address
i5 in registers H and L, is moved to register r.
¡o 11'075 1 1 4 "9
Cycles: 2
States: 7 LX! rp, data 16 {Lead register pair immediate)
Addressing: — reg. indirect trh) =— {byte 3)
Flags: none
fri} -— {byte 2)
Byte 3 of the instruction is moved into the high-order
register {rh} of the register pair rp. Byte 2 of the in-
struction is moved into the low-order register (rl! af
MOV M r (Move to memory) the register pair rp.
(HY tL) + tr) T | | |
The content of register r is moved to the memory la- 0 0 A P 0 0 0 1
cation whose address is in registers H and L, low-order data
Lo 1 a Ty Te Ts Tg 5] high-order data
Cycles: 2 Cycles: 3
States: 7 States: 10
Addressing: — reg. indirect Addressing: immediate
Flags: none Flags: none
4-4
LOA addr (Load Accumulator direct)
(A) =—— tibyte 3) (byte 2I)
The content of the memory location, whose address
is specified in byte 2 and byte 3 of the instruction, is
moved to register A.
o ‘ao "4 ‘41 a ‘0 ' + Ty
low-order addr
high-order addr
Cycles: 4
States: 13
Addressing: direct
Flags: none
STA addr {Store Accumulator direct)
[byte 3)(byte 21) —— (A)
The content of the accumulator is moved to the
memory location whose address 15 specified in byte
2 and byte 3 of the instruction.
a lola
low-order addr
high-order addr
Cycles: 4
States: 13
Addressing: direct
Flags: none
LHLD addr (Load H and L direct!
{L} —— ((byte 3Nbyte 21)
IH} -— ((byte 3libyte 2) 4 1)
The content of the memory location, whose address
is specified in byte 2 and byte 3 of the instruction, is
moved to register L. The content of the memary 1оса-
tion at the succeeding address is moved to register H,
| TT
o "al 1 Го 0
low-order addr
high-order addr
Cycles: 5
States: 16
Addressing: direct
Flags: none
4.5
SHLD addr (Store H and L direct)
(byte 3 byte 2)) -— {LI
(byte Jifbyte 2) + 1) =— (HI
The content of register L is moved to the memory lo-
catión whose address 15 specified in byte 2 and byte
3. The content of register H is moved to the succeed-
IN memory location.
o og я Го то Го тт о
low-order addr
high-order addr
Cycles: 5
States: 16
Addressing: direct
Flags: none
LOAX rp {Load accumulator indirect)
LA) =— tirp)}
The content of the memory location, whose address
15 In the register pair rp, is moved to register À. Note:
only register pairs rp=8 (registers B and C) or rp=D
(registers D and E) may be specified.
| 0 0 | В | Р 1 | 0
Cycles: 2
States: 7
Addressing: req. indirect
Flags: none
STAX rp {Store accumulator indirect)
{{rp}} =— (A)
The content of register À is moved to the memory |o-
cation whose address is in the register pair rp, Note:
only register pairs rp=8 (registers B and C) or rp=D
tregisters D and El may be specified,
o'0|r'r|0'0o'1'o
Cycles: 2
States: 7
Addressing: reg, indirect
Flags: mane
XCHG (Exchange Hand L with D and Е)
EH) =—= (D)
(L] + (E)
The contents of registers H and L are axchanged with
the contents of registers © and E.
0
Cycles: 1
States: 4
Addressing: register
Flags: none
Arithmetic Group:
This group of instructions performs arithmetic срег-
ations on data :n registers and memory.
Unless indicated otherwise, all instructions in this
group affect the Zero, Sign, Parity, Carry, and Auxiliary
Carry flags according to the standard rules.
All subtraction operations are performed via two's
complement arithmetic and set the carry flag to one to in-
dicate a Dorrow and clear it ta indicate no barrow,
ADD r (Add Register)
(A) +— 1A) +r)
The content of register r is added to the content of the
accumulator. The result is placed in thé accumulator.
ADC r (Add Register with carry!
{А} = (A) + {r] + (CY)
The content of register r and the content of the carry
bit are added to the content of the accumulator. The
résult 15 placed in the accumulator.
1! 0
Cycles: 1
States: 4
Addressing. register
Flags: 2.5.P.CY AC
ADC M rAdd memory with carry)
(A) »— {A} + (НЕЙ) + (СУ)
The content of the memory location whose address is
contained in the H and L registers and the content of
the CY flag are added to the accumulator, The result
IS placed in the accumuiator.
1 9 o'oloao|sls!s |
Cycles: 1
States: 4
Addressing. register
Flags: 2.5 P.CY AC
ADD M Add memory)
{A} — Mi + ((H) (LI)
| то то
Cycles: 7
States: 7
Addressing: reg. indirect
Flags: ZS5PCY AC
ACI data {Add immediate with carry)
The content of the memory location whose address
ls contained an the H and L registers is added to the
content of the accumulator, The result is placed in
the accumulator,
(A) =-— (Al + (byte 2) + (CY)
The content of the second byte of the instruction and
the content of the CY flag are added to the contents
of the accumulator. The result is placed in the
accumulator,
1! 0 ото го Та ГТО |
Cycles: 2
States: 7
Addressing: reg, indirect
Flags: ZSPCY, AC
ADI data ¡Add immediate)
(A) =— (A) + {byte 2)
The content of the second byte of the instruction is
added to the content of the accumulator. The result
is placed in the accumulator.
тя Го то Пу По
data
Cycles: >
States: 7
Addressing: immediate
Flags: 2,5 PCY AC
SUB r (Subtract Register)
[A] —— {A} = {r]
The content of register r is subtracted from the con-
tent of the accumulator, The result is placed in the
Pato lg Te TTT
data
Cycles: 2
States: 7
Addressing: — immediate
Flags: Z.,5P.CY AC
accumulator.
BERERERER
О 5 S Si
Cycles:
States:
Addressing.
Flags:
4-6
i
4
register
ВР СУ АС
SUS M [Subtract memory)
(A| (А) — ((H) LH
The content of the memory location whose address 15
contained in the H and L registers is subtracted from
the content of the accumulator. The result is placed
in the accumulator,
1
Cycles: 2
States: 7
Addressing: reg. indirect
Flags: Z,5P.CY¥ AC
SUI data [Subtract immediate}
lA) =— (A) — (byte 2)
The content of the second byte of the instruction is
subtracted from the content of the accumulator, The
result is placed in the accumulator.
114 10 4 "0 "a ‘1 ‘0
data
Cycles: 2
States: 7
Addressing. immediate
Flags: ZP CY, AC
SBBr {Subtract Register with borrow)
LA} — (A) — IN — ICY
The content of register r and the content of the CY
flag are both subtracted from the accumulator. The
result is placed in the accumulator.
| 1atolala ss! |
Cycles:
States: 4
Addressing: register
Flags: ZEP,CY AC
SBE M (Subtract memory with borrow)
{A] =— (A) — (MH) (LI) — (CY)
The content of the memory location whose address is
contained in the H and L registers and the content of
the CY flag are both subtracted from the accumula
tor. The result is placed in the accumulator.
| о!
ol ol
Cycles: 2
States: 7
Addressing: — reg. indirect
Flags: ZSP.CY,AC
4.7
SBI data {Subtract immediate with borrow)
IA) =— (A) — (byte 2) — (CY)
The contents of the second byte of the instruction
and the contents of the CY flag are both subtracted
from the accumulator, The result is placed in the
accumulator,
О 1 0
data
Cycles: 2
states: 7
Addressing: immediate
Flags: Z.5P.CY AC
INR r {Increment Register]
fr} + {г) + 1
The content of register r is incremented by ane,
Note: All condition flags except CY are affected.
оТо [о То Тото Го |
Cycles: 1
States: 5
Addressing: register
Flags: ZS5P, AC
INR M {increment memory]
(OH) (LY) —— (HI {LH} +1
The content of the memary location whose address
is contained in the H and L registers is incremented
by one, Mote: All condition flags except CY are
affected,
Foto: la oli ora
Cycles: 3
States: 10
Addressing: req. indirect
Flags: ESPAC
DCR r {Decrement Register)
ir} +—— {r} — 1
The content of register r is decremented by one.
Note: All condition flags except CY are affected,
(0'0o jo 'n'o'1'0 1
Cycles: 1
States: 5
Addressing: register
Flags: Z.5P AC
DCR M
{Decrement memary)
(НЕ о +—— {IH} (L}} — 1
The content of the memory location whose address is
contained in the H and L registers is decremented by
one, Note: All condition flags except CY are affected,
alatila
o (14 "9 ‘+
Cycles:
States:
Addressing:
Flags:
INX rp
3
10
req. indirect
ZS PAC
[Increment register pair!
rh} (ri) >— {rh} (ri) +1
The content of the register pair ro is incremented by
one. Note: No condition flags are affected,
a o Rp
Cycles:
States:
Addressing:
Flags:
DCX rp
o "ala Ty]
1
5
register
none
(Decrement register pair)
(rh) (rth — {rh} irl} — 1
The content of the register pair rp is decremented by
one, Note: No condition flags are affected.
| olo|ar!o
Cycles:
States:
Addressing:
Flags:
DAD rp
110‘ 1 "0 |
1
5
register
nang
(Add register pair to H and L}
(НЕС) =— CHO LL) + (rfi) Cri)
The content of the register pair rp is added to the
content of the register pair H and L. The result is
placed in the register pair H and L. Nate: Only the
CY flag is affected. It is set if there is a carry out of
the double precision add; otherwise it is reset,
oo RR Praia]
Cycles:
States:
Addressing:
Flags:
3
10
register
CY
4-8
DAA {Decimal Adjust Accumulator)
The erght-bit number in the accumulator 15 adjusted
to form two four-bit Binary-Coded-Decimal digits by
the following process:
1. If the value of the least significant 4 bits of the
accumulator is greater than $ or if the AC flag
is set, 6 is added to the accumulator.
2. If the value of the most significant 4 bits of the
accumulator 15 now greater than 9, orif the CY
flag is set, 6 is added to the most significant 4
bits of the accumulator.
NOTE: All flags are affected.
| o!atitalalr lr la
Cycles: 1
States: 4
Flags: ZSPCY,AC
Logical Group:
This group of instructions performs logical (Boviean]
operations on data in registers and memory and on condi-
tion flags.
Unless indicated otherwise, all instructions in this
group affect the Zero, Sign, Parity, Auxiliary Carry, and
Carry flags according to the standard rules,
ANA r (AMD Register)
[A] -— (A) A tr]
The content of register.r is togically anded with the
content of the accumulator, The resuit is placed in
the accumulator. The CY flag is cleared.
| 1 | О 0 E | 5 | 5
Cycles: 1
States: à
Addressing: — register
Flags: Z5PCY AC
ANA M [AND memory!
{A} »— (A) A CHI (Li)
The contents of the memory location whose address
is contained in the H and L registers is logically anded
with the content of the accumulator. The result is
placed in the accumulator. The CY flag is cleared.
Calo ta Tole Th TiTy
Cycles: 2
States: 7
Addressing: reg. indirect
Flags: Z.5P.CY AC
ANI data ¡AND immediate)
LA) =— (A) À (byte 2]
The content af the second byte of the instruction 15
logicaliy andea with the contents of the accumulator.
The result 15 placed in the accumulator. The CY and
AC flags are cleared.
т
pa a Eo la ala ae
data
Cycles: 2
States: Y
Addressing: immediate
Flags: £5 P.CY AC
ХНА: (Exclusive OR Register]
Арн [A1 %7 (rl
The content of register r is exclusive-or'd' with the
content of the accumulator, The resuit 15 placed «7
the accumulator. The CY and AC flags are cleared.
[1 10! 1 to ‘its’ ss |
Cycles: 1
states: 4
Addressing: register
Flags: Z.5P.CY AC
ХНА M ¡Exclusive OR Memory]
[A] =— (AL Y (HEIL)
The content of the memory location «whose address
is contained in the H and L registers 15 exclusive a
with the content of the accumulator. The result 1s
piaced in the accumulator. The CY and AC flags are
cleared.
pate a 10 1 e
Cycles: 2
States: 7
Acdressing: reg, indirect
Flags: Z.5P.CY AC
XAI data (Exclusive OR immediate!
(A) =— (A) Y tbyre 2]
The content of the second byte of the Instruction 15
exclustve-OR'd with the content of the accumulator.
The result 15 placed in the accumulator. The CY and
AL flags are cleared.
data
Cycles: 2
States: 7
Addressmg: immediate
Flags: 2.5 PCY AC
4.3
ОРАг (OR Register)
(А) === (A) Y ir)
The content of register r is inclusive OR'd with the
content af the accumulator, The result is placed in
the accumulator. The CY and AC flags are cleared.
rho Uy Ty Tg |
5 5 |
Cycles: 1
States: 4
Addressing: register
Flags: SP CY AC
ОНА М (DR memary)
LAY <*— [АР М (1H) (LI
The content of the memory location whose address Is
contained in the H and L registers is Inclusive OR d
with the content of the accumulator. The result 15
placed in the accumulator. The CY and AC flags are
cleared.
Coto Ty Ty Te Tah Tg |
Cycles: 2
States: 7
Addressing: reg. indirect
Flags: 2 S5FCT AC
ORI data (OR Immediate}
(А + (Al Y (byte 2)
The content at the second byte of the instruction is
Inclusive OR cd with the content af the accumulator.
The result is placed an he accumulator. The CY and
AC flags are cleared.
ааа о Та Тао
data
Cycles: 2
States: 7
Addressing: immediate
Flags: Z,5 PCY AC
CMP r (Compare Register!
(A) — tr}
The content of register ris subtracted from the ac-
cumulator. The accurmulator remains unchanged, The
condition flags are set as a result of the subtraction.
The Z flag is set to 1 if (A) = (r}, The CY flag is set to
Tif {AY = let.
1 ' 0 | 1 | 1 ' 1 5 ! 5 | 5
Cycles: 1
States: 4
Addressing: — register
Flags: ZSPCY AC
CMP M
{Compare memory]
(A) — 46H) (Li)
The content of the memory location whose address
is contained in the H and L registers is subtracted
from the accumulator. The accumulater remains un-
changed. The condition flags are set as a result of the
subtraction. The Z flag is set to 1 if (AI = MH} {il}.
The CY Flag is set to $ if (A) < ((H) (L)).
RRC
(Rotate right)
[An] —— {An};
(CY) +— (Ant
The content af the accumulator is rotated right ane
position, The high order bit and the CY flag are both
set to the value shifted out of the iow order bit posi-
tion, Only the CY flag is affected.
{A7) + (Ag)
lol oalo oly Ty THT,
Lr Po ToT TT TT Cycles: 1
States: 4
Cycles: 2 Flags: CY
States: 7
Addressing: reg. indirect
Flags: 2Z,8P.CY.AC RAL (Rotate left through carry)
(An+1) +— (Ад); (СУ) «== (Ау)
(Ap) = (СУ)
CPI data
(Compare immediate)
(A) — (byte 2)
The content of the second byte of the instruction is
subtracted from the accumulator. The condition flags
The content of the accumulator is rotated left one
position through the CY flag. The low order bit is set
equal to the CY flag and the CY flag is set to the
valug shifted out of the high order bit. Only the CY
flag is affected,
o olaldatola TT,
are set by the result of the subtraction. The Z flag is Cycles: 4
set to $ if (A) = (byte 2), The CY flag is set to 1 if States:
Flags: CY
(A) < {byte 2),
RLC
{| { | ; ! 1 | {| ; | | 0 RAR (Rotate right through carry)
(An) +— {A 1}; ICY) -— (Ag)
data (Ag) =— ICY]
The content of the accumulator is rotated right one
Cycles: 2 position through the CY flag, The high order bit is set
States: 7 te the CY flag and the CY flag is set to the value
Addressing: — immediate shifted out of the low order bit. Only the CY flag is
Flags: ZS.P.CY AC affected.
a o lalala Ta Ta,
Cycles: 1
States: 4
Flags: CY
[Rotate left)
{Ant == (An) : (Ag) — (Aq)
(СУ) «= (Ay)
The content of the accumulator is rotated left one
position, The low order bit and the CY flag are both
set to the value shifted out of the high order bit posi-
tion, Only the CY flag is affected,
CMA
{Complement accumulator}
(A) =— (A)
The contents of the accumulator are complemented
[zero bits become 1 one bits become 0, No flags ara
affected.
0 0 | D 0 0 | 1 | 1 ' 1 | | 0 | 0
Cycles: 1 Cycles: 1
States: 4 States: 4
Flags: CY Flags: none
4.10
CMC [Compiement carry:
(CY) = (CY!
The CY flag s complemented. No other flags are
affected.
501 9141 4° 4 11 14 là
Cycles: 1
States: 4
Flags: CY
STE [Set carry!
(CY) =— 1
The CY flag 15 set to 1. No other flags are affected.
0° 0' 4 Пя Тот Та Г
Cycles: 1
States: 4
Flags: CY
Branch Group:
This group of instructions alter normal sequential
program flow.
Condition flags are not affected by any instruction
In this group.
The two types of branch instructions are uncondi-
tional and conditional, Unconditional transfers simply per-
form the specifiea operation an register PC (the program
counter). Conditional transfers examine the status of one of
the four processor flags to determine if the specified branch
15 to be executed. The conditions that may be specified are
as follows:
CONDITION CCC
NZ — notzero (Z= MH 000
@ — zero lZ = 1) 001
NC — nocarry (CY = 0 010
C — carry (СУ = 1) 011
PO — parity odd (P=0 100
PE — parity even (F = 1} 101
P — plus (5= 0) 110
M — minus (5= 1) 111
JMP addr {Jumel
{PC} =— (byte 31 (byte 2}
Control is transferred то the instruction whose ad:
4.11%
dress is specified in byte 3 and byte 2 of the current
Instruction,
yy Pg Tg hg Tg Ty by
iow-order addr
high-grder addr
Cycles: 3
States: 10
Addressing: immediate
Flags: none
Jeondition addr
If (CCC),
(PC) =+— {byte 3) (byte 2)
If the specified condition is true, control is trans
ferred to the instruction whose address is specified in
byte 3 and byte 2 of the current instruction; other-
wise, control continues sequentially.
{Conditional jump)
1 | 1 с С | с 0 | 1 0
low-order addr
high-grder addr
Cycles: 3
States: 10
Addressing: immediate
Flags: none
CALL addr (Call)
(SP) — 11 -— {PCH}
(SP) — 2) =— {PCL}
(SP) =— (SPP — 2
{PC} =— (byte 3) (hyte 2)
The high-order eight bits of the next instruction ad-
dress are moved to the memory location whose
address is one less than the content of register SP.
The low-orcer eight bits of the next instruction ad-
dress are moved to the memory iocatron whose
address is two less than the content of register SP.
The content of register SP is decremented by 2. Con-
trol is transferred to the instruction whose address 15
specified in byte 3 and byte 2 of the current
instruction,
Tg Tg tg Ty Tg Ty
low-order addr
high-order addr
Cycles: 5
States: 17
Addressing. immediate/reg, indirect
Flags: none
Ceondition addr {Condition call)
if (CCC),
[SP) — 1) -— (РСН)
SP) — 2) *+— (PCL)
(SP) -— [5P) —7
(PC) =— (byte 3) (byte 21
If the specified condition is true, the actions specified
in the CALL instruction {see above) are performed:
otherwise, cantral continues sequentially.
| |
vl eT ele] 1 oT pg
low-order addr
high-order addr
Cycles: 3/5
States: 11/17
Addressing: immediate/reg. indirect
Flags: попе
RET {Return}
(PEL) -— {{SP});
[PCH! -— (SF) +13;
(SP! =+— [SF] + 2;
The content of the memory location whose address
15 specified in register SP 15 moved to the low-order
eight mits of register PC, The content of the memory
location whose address 1s one more than the content
of register SP is moved to the high-order ergnt bits of
register PC, The content of register SP is ircrementer]
by 2.
1 le To Ty Tg Tg vy]
Cycles: 3
States: 10
Addressing: req. indirect
Flags: none
Recondition {Conditional return)
НЕ ССС)
(PEL) =— ((SPH
(PCH) =— SP) +1)
(SP) -— (SF) +2
[If the specified condition is true, the actions specified
in the RET instruction (see above) are performed;
otherwise, contral continues seguentially.
y le tele ото Го |
Cycles: 1/3
States: 5:11
Addressing: req. indirect
Flags: none
ASTr (Restart)
SP) — 1) -— {PCH}
SP) —2) =— (POL)
(SP) +— (SP) — 2
(PC) >— 8 * (МММ)
The high-order eight bits of the next instruction ad-
dress are moved to the memory location whose
address is one less than the content of register SP,
The low-order eight bits of the next instruction ad-
dress are moved to the memory location whose
address is two less than the content of register SP.
The content of register SP 15 decremented by two.
Control 15 transferred to the instruction whose ad-
dress 15 eight times the content of NNN,
Dan NN
Cycles: 3
States: 11
Addressing: reg. indirect
Flags: none
1514 1312111098 7 6 5 4 3 2 10
|0/0[/0|0|0;0/0/0/0/0/N MIN ооо,
Program Counter After Restart
PCHL {Jump H and L indirect — move H and L 10 PC)
¡PCH) =+— {Н)
(PELI -— IL)
The content of register H 15 moveg to the high-orger
eight bits of register PC. The content of register L is
moved to the low-order eight bits of register PC,
Roa a 1 0 ati
Cycles: 7
States: 5
Addressing: — register
Flags: none
Stack, 1/0, and Machine Control Group:
This group of instructions performs 1/0, manipulates
the Stack, and alters internal control flags,
Unless otherwise specified, condition flags are not
affacted Dy any instructions in this group.
PLUSH rp (Push)
SP) — 11 =+— rel
HSPI — 2) =— irl)
[SP} =— (SP) — 2
The content of the high-order register of register pair
гр 1$ moved to the memory location whose addrass is
one less than the content of register SP, The content
af the low-order register of register pair rp is moved
to the memory location whose address is two less
than the content of register SP, The content of reg-
ister SP is decremented by 2. Note: Register pair
rp = SP may not be specified.
para я! Р C 1
Q | 1 |
Cycles: 3
states: 11
Addressing: — reg. indirect
Flags: none
PUSH PSW Push processor status word}
(SP) — 1) -— (A)
(SP) —2)g =— ¡CYhH, (SPP — 214 +— 1
(SP) — 219 -— IP), (SP) —2)9 =— 0
(SP) — 233 — (AC). SP) — 215 =— 0
(SP) — 215 — (21, USPI- 213 + [5]
(SP) -— [SP} - 2
The content of register À is moved to the memory
location whose address is one less than register SP.
The contents of the condition flags are assembied
intô a processor status word and the word is moved
to the memory location whose address is two less
than the content of register SP. The content of reg-
ister 5P 15 decremented by two,
Cycles: 3
states: 11
Acdressing: reg indirect
Flags: none
FLAG WORD
В; De Ds Da D Ds Da Ca
sz) olaio|P|r]|er|
POP rp (Pop!
(FI) =— {{5P]}
бр = {{SF} + 1}
(SP) =— [5P} + 2
The content of the memory location, whose address
is specified by the content of register SP, is moved to
the low-order register of register pair rp, The content
of the memory location, whose address is one mare
than the content of register SP, is moved to the high:
order register of register pair rg, The content of reg-
ister SP is incremented by 2. Note: Register pair
rp = SP may not be specified.
Pa RIE oo
0 1
Cycles: 3
States: 10
Addressing: reg indirect
Flags: none
POP PSW {Pop processor status word)
(CY) =— (ISPHho
{P} ~— ({5Р))э
(ACC) — ASPIRA
(2) — (SP)
(5) -— 05P117
(A) =—- {ISP} + 1)
(SP) +— {SP]+2
The content of the memory location whose address
is specified by thé content of register SP is used to
restore the condition flags, The content of the mem-
ory location whose address 15 one more than the
content of register SP is moved to register A. The
content of register SP is incremented by 2,
Fa Ta Ta Te To Te
Cycles: 3
states: 10
Addressing: reg, indirect
Flags: ZSPCY AC
XTHL {Exchange stack top with H and L)
И = ЦОР
HH) e ((5SP) + 11
The content of the L register is exchanged with the
content of the memory location whose address is
specified by the content of register SP. The content
of the H register is exchanged with the content of the
memory locatron whose addréss is one more than the
content of register SP,
1 te ela |
Cycles: 5
States; 18
Addressing: req. indirect
Flags: none
SPHL (Move HL to SP}
(SP) -— HI FL)
The contents of registers H and L {16 bits} are moved
to register SP,
1 yr ate elt|
Cycles: 1 >
States: 5
Addressing: register
Flags: none
IN port (Input)
(A) «+— {data}
The data placed on the eight bit bi-directional data
bus Oy the specified port is moved to register A.
T
пя То Га Го о По
рог!
Cycles: 3
States: 10
Addressing: direct
Flags: none
QUT port (Output)
idatal =— (AI
The content of register À is placed on the eight bit
bi-directióonal data bus for transmission to the spec-
ified port,
11 4 10 ta *o То Г) Г,
port
Cycles: 3
States: 10
Addressing: direct
Flags: none
Ei {Enable interrupts)
Tha interrupt system is enabled following the execu-
tion of the next instruction.
| aba ta Ta Tola
Cycles: 1
States: 4
Flags: none
ol (Disable interrupts)
The interrupt system is disabled immediately fol-
lowing the execution of the DI instruction,
La a hh Te Tg TT
Cycles: 1
States: 4
Flags: none
HLT [Halt]
The processor is stopped. The registers and flags are
unaffected.
Col ha Te Ty TTT
Cycles: 1
States: 7
Flags: none
NOP (Ma op}
Mo operation is performed. The registers and flags
are unaffected.
Cycles: 1
States: 4
Flags: none
INSTRUCTION SET
Summary of Processor Instructions
Intructan Cade ! Clack - Instruction Code. Clock ©.
Mramanic Dewopbian 0; De Og Dg Dy 0; Dy By Cycles "anemanie — Descraprión 07 Dg № 24 0) @ O: Dn Cycles
МОМ, ‚ро Mr regis tán 16 Liégaster ] 1 O 0 0 5 5 8 5 AZ Return ter 1 1 пот ос 11
MON Mr Move regiser 1 mempry Lt 11 1 O E 5% I ANT Aeturo gr na rea 1 1 90 1 3: DI 5 11
MOY r M Move memary rd register a 1 a no n 1! +» A 7 НР fedurr où gottie | 1 1 13 0 2907 5 11
oT Hair | 1 1 0 1 | o ; Hi Aer am mins 1 1 1 - 0 Tn 5 11
yl Tr ‘ree Meda Leger 13 1 92 0 60 rod ' RPE Returis 07 party even | 1 . 0: 3 5 11
MA RAs rime ge Memory : Q 1 1 n 1 + 5 In HPD Return gn gar iy odd Nod Lo OT 51
WE booremand regis я пе 9 оп: n ug 1 AST Resear | 1 А = #4 1 - - 11
e CAr Cecramen| register 5 #8 1 H 9 * 1 5 + row | 1 1°" - 0 12
qe M |= статор у В у Ü n ! 1 0 i e HI] QT Tahu I 1 : - % 0 i
FM Qezieenkr] memo y 0 1] | 1 П 1 П 1 “Il IA Lad immediate regisler - Ü Û 2 a Ú : 10
au: Ardregisle ip A BA UÙ O 3 5 à 4 Far BAC
АСС Sd EQU 13 A wath rary 1 A OD TES + „x О Laad immediate reqicier 200 3 7 € и!
SUR 1 Suttrac! reger drum À 1 1 a 1 0 5 5 à 1 Far O KE
ЗНА г Gab nl regesrer Irpm A 1 ÿ 1 1 % 5 85 " Lgl | Laad immediate reqisier So 1 Dor 10
A SORTE Farr HE |
ANA Ad regener wah A 1.0 1 10 0 5% 5 3 - LAI SP Lied immediate stack poomer 0 2 + mon a 16
ERA Exctysrye Or register will à Tn | 11 5 5 à + PUSH B PLah register Fan BB Can Po] ü 7 0 1 Lo 11
CRA r J- regler were À 1 10 I 1 4 5 §5 = + Tach
CMP Compare register with A 1 0 | 1 1 5 5 à 4 PUSH E Push register Pan 0 8 E un I С a 1 no i
AOÛ M Ad memory in А 1 E oon a TÚ ï лась
AOC M Аба memory co A aii carry 1 a 0 0 1 1 11 ! PUSH H Fish reqisies Pan HE Lun I 1 1 1 0 1 Ü 1 11
SUE WM Sibrract memory fram à 1 6 3 1 qd 7 10 9 “lack
250 M SLtIract memuay irgm A Io Nn LL 1 1 1 PLUSH PSR Push & god Flags Io 1 ото! 11
Wilh Bure nw J Slack,
Ayam Sn MAN А Im 1 ù 0 1 1 1 FOPA Pro register get B 5 Cad I NR A O DS 17
ERA М Exe cave O: memory wah А Il f 1 5 1 1 1 Stark
ОНА М Memory wir à PO FR TO о ' "РО Pron requester ga 0% E olf ' 1 ] ÿ 0 1 15
СМР М ботзагв тату мель А | 1 | ! I I ! Lack
All Ho TEA de À | | 0 a - ! | TF ! FIP H Fup egss ier gr H & & nls | ! 1 1 п 1 ! 10
ALI Add immed are ia 5 vif "o [1 | Г ! “luck
Cate FOR PSWí Pup A and Flags I 1.0 © 10
SUI Enbrariiamenedahe lan ! | I n ! al gl
Bl Saba ета РЕ rom A ' ' N 1 I oh STA SAPO reci оо =: 0 10 11
АГРО ГИ LITA Coad Boers no 0 ! To li
ah DL ma pt д 1.1 ! Ц ' УГ НТ, Exriange Det MEL 1.1 i 2? i
asl Erp guys Ur ommend gts wath 1 1 | 1] 1 1 ' Auy vars
A THI Cary ye up ria k AL ! 1 e 3
JA De Amen re cai E 1 1 ! i 1 1 N SFHL HE Lt siack paivter | | ' - - ! E
="! Lo—oare immediaie wih À [1 Lo FHL HY Lawgragrarm counter 1.1 - I € E
ALE Pare A Jele оо: 11 JADA Ad BA Cio HE E ol û : 13
TEC Rare à righl зоо bold - САЙ О Add GRE ta MEL = 1 € 3 € 1£
HAL Atrae A lt AL Carry 2 41 0" odo 1 ann Add HA LW HEL AI xk 15
AAR Atate A right Through чат Pod i САП БР Add crac pander tz H Boo 20501" TU E 1 10
carry S3TAX A S-are À indirect a 0 охот: 1
me «эВ инте чаи BB OT 10 I3TAXD Sure dorndwec] 5 27 0 * 97 0 : }
iL за TOO Carr 1"! «117 0 1% 10 JANE Load A indirect 0 oo 5 1 0 101 I
MC TO ON NO Carry 1 1 n I a O Y = 10 LDAN E Lrad & indirect а «10 © * I 7
d « THor sere 1.1 0 79 1 E IE 1чх В trcrement BB Comérars посл! 5
NI “TD I A) LÉO 11 0 0 9 0 1 nb "ui 15 X D reEmen; DA E cegstert DB $3 "TO 5
P «TID AN POSTIVE 11 тот Ш INX H rcremen НОВ квота on ле 5
M UT TD FAURE 1 1 1 ы Ia 1 1 LE INX SP 'reremera siach privi DD I ' noon ! 5
«PE Jumg an pardy even 1 1 1 0 1 ÿ 1 0 Hi DCX & Gecrement B & оп с я: 5
PO U710 OA parily add 1 1 0. 25 a0 1 À "a ocx Decrempry OF & E ooo ota @ "! 5
CALL Cal unto | 1 O po * IP 0 1 1! OCX H Frecrerment H & L 0 0 NO 1! go" 4
EL Cad an carry [1 a ' U à A1 17 OCA SP Decrement ack pointer n a : 1 I " 5
CNC Cal an по carey HO 0 1 D 1 90 0 "117 CMA Cumpléman: A qb 0 1 {1 101 4
cz Cail an zero Rol 0 A TOO 1117 STC Sel Carry g a 5 + 1 d
CHZ Ca! on nn rer9 | | 0 ul ta * 1 СМС Complement tarty | | ' 1 | 1 1 4
FP Callar posar Eo O AO 111 CAA decimo adjust A an * =: Tr 1! 4
ем Сан а minus 11111 * 0% 11 SMLO блоге # & | direct Ad * : O 1 16
CPE Cal on parity even тат 1111 LLO Load H & L direct don поет IB
Pa Cail on parity add : + 1 0 6 1 D 2 11:17 Ei Enable Intersupts E фт 4
RET Rel 11 D od IT O 0 * 10 DI Ob inner pl | 1 Y По! 4
AL Retusn ar carry 1 1 1 1 000 5 NOP Ya-apitatian : #& 001 5 3 70! 4
ANC Че an na Car 1 1 n 1 0 0 AD 5-11
NOTES. t. DOD or 5585 - 0008 001 © - 010 О - ОЛ Е
100 Hd -- 161 L = 110 Memory — 111 A,
2. Two posuble cyche times, (57111 indicate instruction cycles dependent an condauion Fags.
4-15
CPU Group
£8224 Clock Generator
8228 System Controller ...... . 2... eres...
BOBOA Central Processor . . ......... en...
8080A-1 Central Processor {1.3usl ................
BOBOA-2 Central Processor (1.6us)l .. 11214 144 4 44 414
MBOSQA Central Processor [-55° to +125°C) ........
~ 4 печки чл ги ги ги ги лин сни ине
ROMs
B8702A Erasable PROM {266 xB} .................
8708/3704 Erasable PROM (IK x 8) . .. ............
8302 Mask ROM 4266 x 8) .................... .
8308 Mask ROM MK x SB) aaa .
8216A Mask ROM I2K x 8)
+ ии гии ии ии ии ря + PF EH + = 4 x
RAM:
8101-2 Static RAM (256 x 4)
8111-2 Static RAM (2586 x 4)
B102-2Static RAM (TK x 10 ©... .....
810244 Static RAM (TK x 11... arre,
81078-4 Dynamic RAM {4K x 1)
8101 Static CMOS RAM {256 x 4)
8210 Dynamic RAM Driver .....................
B222 Dynamic RAM Refresh Controller
= = = + + 8 ® 4 FB 1 ww EEE
гии ини a2 ® a2 ® » ®B 4 F 4 + EB d r =
Fk я ии пи ии ти а питал
= =» ® 4 ® 4 ® 4 r 4 F = = Fr = °F
и ии ки зв на д
170
3212 E Bit 1/0 Port... KR LL
8265 Programmable Peripheral Interface ............
8251 Programmable Communication Interface
Peripherals
8205 One of Eight Decoder . . ...................
2214 Priority Interrupt Control Unit... .........,
8216/8226 4-Bit Bi-Directional Bus Driver
Coming Soon
8253 Programmable interval Timer . . .. ............
6257 Programmable DMA Controller ..............
3259 Programmable Interrupt Contrelier
и тит ин ви ль
CPU Group
8224
8228
GOGOA
8080A-1
8080A-2
M8080-A
STST8 CLOCk 3774 ;
GENERATOR HOLD REQ
AMD DRIVER |
y |
1 + Y +
EYNC > 1 IESET
‚NT has
AO BORA CPL
WR 00-D7 DÉIN HLDA AC-A15
¿ Ab
A778 | nz ADDRESS
SYSTEM И gms BUFFERS! |
CONTROLLER I DECODER |
if;
218 1OPTIDNALI |
8704 ROMs
Broa
811-2
B111-2
8102-2
RAMs 8210
5181
TL
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RY
||
DATA Bl BUS {8}
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SANT RGL BUS Te)
IL 4 ||
LL {15
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8251
HD
COMMUNICATION
INTERFACE
ETE ALS 1161
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#212 vo ata
8755 PERIFHERAL EH.
INTERFACE
PRIORITY
INTERRUPT
ntel
u Single Chip Clock Generator/ Driver
Schottky Bipolar 8224
CLOCK GENERATOR AND DRIVER
FOR 8080A CPU
for 80BOA CPU
u Power-Up Reset for CPU
E Ready Synchronizing Flip-Flop
E Advanced Status Strobe
E Oscillator Output for External
System Timing
E Crystal Controlled for Stable System
Operation
® Reduces System Package Count
The 8224 is a single chip clock generator/driver for the 8080A CPU. Ît is controlled by a crystal, selected by
the designer, to meet a variety of system speed requirements.
Also included are circuits to provide power-up reset, advance status strobe and synchronization of ready.
The B224 provides the designer with a significant reduction of packages used to generate clocks and timing
for 8080A.
PIN CONFIGURATION
BLOCK DIAGRAM
XTAL1 —
Pa
E XTAL2 — OSCILLATOR >” OS (=>
mEser [| el Yee [> TANK ——
RESIN 157 )XTAL1 Po [i>
Abri 14 [ ]XTALI Co E >
READY [| 12] TANK
B224 D. a, À ag
sync 17[ jose
„тес "Hs [E> sync — Dom F>
STSTR [ 1h || +
E>» AEER Er Le
Guo sf) Yoc SCHMITT
INPUT чё |. REEET [1 >
[> movin oa HEADY [4 >>
+
PIN NAMES
CUNNÉCTIONE
FOR CAYETAL
OVERTONE KTAL
ск LEVEL]
STATUE ITH
ACTIVE LOW]
BORO
CLOCKE
5-1
SCHOTTKY BIPOLAR 8224
FUNCTIONAL DESCRIPTION
General
The 8224 is a single chip Clock Generator/Driver for the
BOBDA CPU. It contains a crystal-controlied oscillator, a
“divide by nine” counter, two high-level drivers and several
auxiliary logic functions,
Oscillator
The oscillator circuit derives its basic operating frequency
from an external, series resonant, fundamental mode crystal,
Two inputs are provided for the crystal connections (XT ALT,
XTAL2!.
The selection of the external crystal frequency depends
mainly on the speed at which the 808B0A is to be run at.
Basically, the oscillator operates at 9 times the desired pro-
cessor speed.
A simple formula to guide the crystal selection Es:
1 ;
Crystal Frequency = — times 9
cy
Example 1: {500ns toy)
2mHz times 9 = 18mHz*
Example 2: (800nstev!
1.25mHz times 9 = 11.25mHz
Another input to the oscillator is TANK, This input allows
the use overtone mode crystals. This type of crystal gen.
erally has much lower “gain” than the fundamental type so
an external LC network is necessary to provide the additional
‘'qain”” for propér oscillatôr operation. The external LC net-
work is connected to the TANK input and is AC coupled to
ground. See Figure 4,
Thé formula for the LC network is:
Е = —
2m + LC
The output of the oscillator is buffered and brought out
on G50 (pin 12} so that other system timing signais can be
derived from this stable, crystal-controlled source.
*When using crystals above 10mHZ a small amount of frequency
“trimmine” may bé necessary to produce the exact desired fre-
quency. The addition of a small selected capacitance (3pF - 10pF1
tn series with the crystal will accomplish this function,
Clock Generator
The Clock Generator consists of a synchronous “divide by
ning” counter and the associated decode gating to create the
waveforms of the two ВОВОА clocks and auxiliary timing
signals.
5-2
The waveforms generated by the decode gating follow a
simple 2-5-2 digital pattern, See Figure 2. The clocks gen-
erated; phase 1 and phase 2, can best be thought of as con-
sisting of ‘units’ based on the oscillator frequency. Assume
that one “unit” equals the period of the oscillator frequency.
By multiplying the number of units‘ that are contained in
a pulse width or delay, times the period of the oscillator fre-
quency, the approximate time in nanoseconds can be derived,
The outputs of the clock generator are connected to two
high level drivers for direct interface to the 80804 CPU. A
TTL level phase 2 is also brought out $9 {TTL} for external
timing purposes. |t ls especially useful in DMA dependant
activities. This signal is used to gate the requesting device on-
to the bus once the 80804 CPU issues the Hold Ack-
nowledgement (HLDA).
Several other signals are also generated internally so that
optimum timing of the auxiliary flip-flops and status strobe
{STSTBI is achieved,
| > ‚тел
OSCILLATOR
[> XYALA
[> TANK
[> sync
[> REN
SCHMITT
INPUT
[> movin
©
1
1 LIT = DEE
FRED
4
11:
|
"> 1
EXAMPLE: (BOBO ca, + SOM
OSC = 1B Hz "S50
4 1710012 a 550061
wa = 7750515 a Boma
засл т 1100517 a SSnil
1 | - |
1 | 2 | 3 * 4
| : i !
SCHOTTKY BIPOLAR 8224
STSTB (Status Strobe)
At the beginnina of esch machine cycle the 80804 CPU 15-
sues status information on its data bus, This information
tells what type of action will take place during that machine
cycle. By bringing in the SYNC signal from the CPU, and
gating it with an internal timing signal {$14}, an active low
strobe can be derived that occurs at the start cf each ma-
chine cycle at the éarliést possible moment that status data
is stable on the bus. The STSTB signal connects directly to
the 8228 System Controller.
The power-on Heset also generates STSTB, but of course,
for a lenger period of time. This feature allows the 8228 to
be automatically reset without additional pins devoted for
this function.
Power-On Reset and Ready Flip-Flops
A common function in 80804 Microcomputer systems is the
generation of an automatic system reset and start-up upon
initial power-on. The 8224 has a built in feature to accomp-
lish this feature.
An external RC network is connected to the RESIN input.
Tha slow transition of the power supply rise is sensed by an
internal Schmitt Trigger. This circuit converts the slow trans
ition into a clean, fast edge when its input level reaches a
predetermined value. The output of the Schmitt Trigger is
connected to a 0” type flip-flop that is clocked with ¢20
lan internal timing signal). The flip-flop is synchronously
reset and an active high level that complies with the 808CA
Input spec is generated, For manual switch type system Re-
set Circuits, an active low switch closing can be connected
to the RESIN input in addition to the power-on RC net-
network.
5-3
The READY input to the B080A CPU has certain timing
specifications such as “set-up and hold" thus, an external
synchronizing flip-flop is required, The 8224 has this feature
built-in. The RDYIN input presents the asynchronous “wait
request” to the “0D” type flip-flop. By clocking the flip-flop
with ¢2D, 2 synchronized READY signal at the correct in-
put level, can be connected directly to the BOBOA.
The reason for requiring an external flip-flop to synchro-
nize the “wait request” rather than internselly in the 8080
CPU is that due to the relatively long delays of MOS logic
such an implementation would “rob” the designer of about
200ns during the time his logic is determining if a “wait”
is necessary. An external bipolar circuit built into the clock
generator eliminates most of this delay and has no effect on
component count.
bs — — o an pm — m]
ñ
pe
Zr LC
USED ONLY
FOR OYERTONE
CRYSTALS
— 1 3:40 E
{ {ONLY NEEDED
— 4 ABOVE 14 Mhz}
15
1 22
12
OSC y
19 15
5
ey ATTLE =—rt
1 4 23
ROYIN —=
Vee 5224
lo 2 4 12
AESIN
5
GND T и 19
GND
7
To STSTE (TC 6228 FIN 1}
SCHOTTKY BIPOLAR 8224
D.C. Characteristics
Ta = 0°C to 70°C; Vec = +5.0V 25%; Мрр = +12\ +5%.
Limits
Symbol Paramatar Min. Typ. Max. Units Tast Conditions
Ip Input Current Loading -.25 mA Ve = 45V
la Input Leakage Current 10 ДА Va = 5.25V
Ve ; Input Forward Clamp Voltage | 1.0 \ le = -5mA
IL Input “Low” Voltage ‚8 Y Vee = 5.0V
Y H Input “High” Yoltage 2.6 \ Reset Input
2.0 All Other inputs
Vin-Vi © REDIN Input Hysteresis ‚25 my Vee = 5.0V
VOL | Output "Low" Voltage 45 \ 1.02), Ready, Reset, STSTB
lor =2.5тА
‚45 Y All Other Outputs
lo = 15mÁ
YoH Qutput “High” Voltage
ogy Lo 9.4 \ lon = -100pA
READY, RESET 3.6 \ юн = -100д А
All Other Outputs 2.4 \ lon = -1mA
leg!!! Output Short Circuit Current -10 -60 mA, Vo = UY
| AI Low Voltage Outputs Only} Vee = 5.0V
lec Power Supply Currant | 115 mA
Ino Power Supply Current 12 | mA
Note: $, Caution, $ and #5 output drivers do not have short circuit protection
CRYSTAL REQUIREMENTS
Tolerance: .005% at 0°C -70°C
Resonance: Series {(Fundzmental)®
Load Capacitance; 20-35pF
Equivalent Résistance: 76-20 ohms
Power Dissipation (Min): 4mW
"With tank circuit usa rd overtone mode.
5-4
SCHOTTKY BIPOLAR 8224
A.C. Characteristics
Усс = +5.0V = 5%; Vpp = +12.0V £ 5%; T4 =0°Cto 70°C
Limits Test
Symbol Parameter Min. Typ. Max. Units Conditions
tas 61 Pulse Width a - 20ns
ton $, Pulse Width - 35ns
to 94 ta pa Delay | 0 ns
|
toz 62 to 61 Delay | a - ans CL = 20pF to 50pF
; 21
tos 4 to ds Delay | есь = + 2015
IR de and dy Rise Time | 20
tr фу and ba Fall Time | 20
tDé2 4 to da (TTL) Delay | -5 +15 ns $ TTL,CL=30
Ry ==30061
Нь=6000
= Btey Étcy
toss H to STSTB Delay о” 30ns a
tow STSTE Pulse Width tey _15ns eu Spf
1 =
RDYIN Setup Time to 50ns - NEY Во = 4К
DRS hs -
Status Strobe 9
1 ROYIN Hold Time Atcy
PRE After STSTE 9
tor ROYIN or RESIN to dtcy 25ns Ready & Reset
$n Delay 9 Ci=10pF
R1=2K
Ro=4K
tCLE CLK Period =
Maximum Oscillating
f 7 MHz
max Frequeney 2
Cin Input Capacitance 8 pF Voc=+5.0V
Ypop=+12V
Vgias=2.5V
f=1MHz
5-5
INPUT >
Meo
CIRCUIT
A"
SCHOTTKY BIPOLAR 8224
WAVEFORMS
—-- key 1 -—— A
>
I
Pa Las „| = "о a
|
"Her — ha —
FTL: A
|
|
SYNC
¡FAM BOBA; \ ) /
|
[a tay = |" toss a
|
STETB
Toa — =! r—
= nan === = -——- --——
ACYIN OR AESIM X Y
AEADY OUT X
RESET OUT X
VOLTAGE MEASUREMENT POINTS: di, 49 Logic "07 = 1.0V, Logic "1" = 8,0V. AH other signals messured ar 1.54.
EXAMPLE:
A.C. Characteristics {For toy = 488.28 ns)
Ta = O°C to 70°C: Vpp = +5V +5%: Vop = +12V 16%.
| Limits
Symbol Parameter Min, Typ. Wax. Units Tatt Conditions
tol $1 Pulse Width 89 ns |. tey=488.28ns
taz $= Pulse Width 236 ns
to Delay © to do 0 1. ns
too Delay #3 10 04 95 a ns |L ®; & da Loaded to
tos Delay $1 to dy Leading Edges 108 129 ns CL = 20 to SOpF
t, Output Rise Time i 20 ns
tr Output Fall Time 20 - ns
1055 $, to STSTB Delay 296 326 ns
‘рф? Ga to Ga (TTL) Delay 6 +15 ns
thw “Status Strobe Pulse width _ | | a0 ns Ready & Reset Loaded
tons ADCYIN Setup Timeto STSTB -167 ns to ImA/10pF
tORH RDYIN Hold Time after STSTB 217 ns All measurements
ton READY or RESET 192 ns remo © 15V
ou is pct
fMAX Osciliator Frequency 18.432 MHz
5-6
intel chottky Bipolar 8228
SYSTEM CONTROLLER AND BUS DRIVER
FOR 8080A CPU
a Single Chip System Control for E User Selected Single Level Interrupt
MCS-80 Systems Vector (RST 7)
m Built-in Bi-Directional Bus Driver m 28 Pin Dual In-Line Package
for Data Bus isolation
B Allows the use of Multiple Byte
Instructions (e.g. CALL) for
interrupt Acknowledge
Eu Reduces System Package Count
The 8228 is a single chip system controller and bus driver for MCS-BO. It generates all signals required to
directly interface MCS-80 family RAM, ROM, and 1/0 components.
A bi-directional bus driver is included to provide high system TTL fan-out. It also provides isolation of the
8080 data bus from memory and 1/0. This allows for the optimization of control signals, enabling the sys-
tems deisgner to use slower memory and |/O. The isolation of the bus driver alse provides for enhanced
system noise immunity.
A user selected single level interrupt vector {RST 7} is provided to simplify real time, interrupt driven, small
system requirements. The 8228 also generates the correct control signals to allow the use of multiple byte
instructions {e.g., CALL) in response to an INTERRUPT ACKNOWLEDGE by the 8080A. This feature
permits large, interrupt driven systems to have an unlimited number of interrupt levels.
The 8228 is designed to support a wide variety of system bus structures and also reduce system package
count for cost effective, reliable, design of the MCS-80 systems.
PIN CONFIGURATION 8228 BLOCK DIAGRAM
er — —
OD, ———— ———— DE,
1578 [| 1 23 7 ver NT DE
1 o *
Hoa (2 = [iow DATA D, ——=— BIDIRECTIONAL |—e—-— 08) | cocoon pata sus
— — ая == | BUS DRIVER = DB,
“A C + 76 Г] ME MW BUS sn DA:
Te ' p, —— че её дн ОВ;
cein [7] 4 25 {_] VOR | > ba De
pes [Es 24 [J MEMA = т |
Da [tE 73 [INTA | | DRIVER CONTROL
087 [ 7 22 [7 BUSEN | N |
С 5228 - —— = = ЧЕМ В
ora n[ Jos : |
| STATUS р ЧЕМ Ой
Dela 20 [-] nes LATCH -
= OR
ез [1 + 19 [_] о | GATING E
ARRAY
onz [C] 1+ 18 |] oes | p—— GW
SETE —
pz [] 12 7 Co BRAIN bu —— BUSEN
cer CH 13 16 [] ver We
HLDOA e INTA
sno [C114 15 [Jo
PIN NAMES
0709 + CATA BUS ОБО МО: — INTA
DET-CAD | CATA AUS SYSTEM SIDE, BED)
KOM |g READ :
МОИ 1 WRITE BUS EMABLE INPUT
MENA MEMORY ACÁD STATUS STROBNE JFROM 82241
MENW MEMORY WRITE
. DBIN DEIN IF ROM 808} 0 VOL
5-7
SCHOTTKY BIPOLAR 8228
FUNCTIONAL DESCRIPTION
General
The 8228 is a single chip System Controller and Data Bus
driver for the BOBO Microcomputer System. !t generates all
control signals required to directly interface MCS-80™ family
RAM, ROM, and 1/0 components.
Schottky Bipolar technology is used to maintain low delay
times and provide high output drive capability to support
small to medium systems.
Bi-Directional Bus Driver
An eight bit, bi-directional bus driver is provided to buffer
the 8090 data bus from Memory and 1/0 devices. The 8D80A
data bus has an input requirement of 3.3 volts (mint and
can drive {sink} a maximum current of 1.9mA. The 8228
data bus driver assures that these input requirements wsll
be not only met but exceeded far enhanced noise immunity.
Also, on the system side of the driver adequate drive cur-
rent is available (10mA Typ.) so that a large number of
Memory and 1/0 devices can be directly connected to the
bus,
The 8i-Directional Bus Driver is controlled by signals from
the Gating Array so that proper bus flow is maintained and
its cutputs can be forced into their high impedance state
[3-state) for DMA activities,
Status Latch
At the beginning of each machine cycle the 8080 CPU issues
“status” information on its data bus that indicates the type
of activity that will occur during the cycle. The 8228 stores
this information in the Status Latch when the STST8 input
goes "low". The output of the Status Latch is connected to
the Gating Array and is part of the Control Signal generation.
Gating Array
The Gating Array generates control signals {MEM R, MEM W,
1/0 R, 1/0 W and INTA) by gating the cutputs of the Status
Latch with signals from the 8080 CPU (DBIN, WR, and
НЕВА).
The “read” control signals ¡MEM R, 1/0 R and INTA! are
derived from the logical combination of the appropriate
Status Bit (or bits) and the DBIN input from the 8080 CPU.
The “write” control signals ¡MEM W, 1/0 W) are derived
from the logical combination of the appropriate Status Sit
lor bits) and the WR input from the 8080 CPU.
All Control Signals are "active low" and directly interface
to MCS-80 family HAM, ROM and 1/0 components.
The INTÁ contro! signal is normally used to gate the “inter-
rupt instruction port” onto the bus. It also provides a
special feature in the 8228. |f only one basic vector is need:
ed in the interrupt structure, such as in small systems, the
8228 can automatically insert a RST 7 instruction onto the
bus at the proper time. To use this option, simply connect
the INTA output of the 5228 (pin 23) to the +12 volt
supply through a series resistor (1K ohms). The voltage is
sensed internally by the 8228 and logic В “set-up” so that
when the CBIN input is active a RST 7 instruction is gated
on to the bus when an interrupt is acknowledged. This
feature provides a singie interrupt vector with no additional
components, such as an interrupt instruction port.
When using CALL as an Interrupt instruction the B228
will generate an INTA pulse for each of the three bytes.
The BUSEN {Bus Enabie} input to the Gating Array is an
asynchronous input that forces the data bus output buffers
and control signal buffers into their high-impedance state
if itis a “one”. |f BUSEN is a “zero” normal operation of
the data buffer and control signals take place.
8228 BLOCK DIAGRAM
В; — | —— OB,
DD, —s i br er GR,
cru Ta mi — ej |—]—— DE,
DB, —4 BI-DIRÉCTIONAL te sg [J
3
DATA o SUS DRIVER pe: SYSTEM DATA BUS
Oy —— + ел LE,
Dre — "À je дн. се,
Dy — — mie ml al DE,
CAIVER CONTROL
= p——=e MEME
STATUS — = НЕМОЙ
== LATCH
о!
LF GATING "OR
ARRAY
] p— HOW
ESTA
Dm pa——— BUEER
Wi —.e
HLOÁ _
SCHOTTKY BIPOLAR 8228
=}
ov
J
Ta
EZ
= 5
CO
LI ¿A
2 |
ca = | = = = |= се!
5 ë < 2 |< |2 |= [= |= |= |2 [=
al = E OE lolo (yw |w ju | iw
= a = ЕЕ Е ЖЕ
oa ol
| |
| EEE
HA
Eo NN ow E E
Soma Eee = "a
>
PLE] E
sho fett] HESS z ol-olola-
UE = 1 5 I
— e ia | В « afola|-|ajo -
a] a x
+ BES ! El = —
sus | = w ola-jelele--- ——
za I 5 a
= ajajoj oo nn
ne ill — | m
+ 5.05: = E |
Sn -lofajlajaje = бен —
ДА) Si ed | | са) mél ur) — т
EE dascaddé s -lole|olo|-|— —
a 2 = 3 — d...k —. A Y
al = 1 | | | | с -
£2 3
= рр
= fom J Om om mn Im - —
=
ud -
z E {3 | +3 | 3 | = | —
«Г
: 5
T м
a of =
x 515] 55
= DIO ES
La
= TT
- ся Е 11 | wy ga] m™
и 21| | |
oh
SCHOTTKY BIPOLAR 8228
WAVEFORMS
ci
ESTATUS STADE
A080 DATA BUS
DEIN f \
= [gp =
INTA, IA. MERA 4 /
CC —ан
HLDA © Fd
= = tun
INTA 106. MEME
DURING HLOA X у
= los + он =
— — — — — 2 2 Em dd o de e
WR \ /
[М8 OR MEM Ww
LEE pe a
8080 BLS DURING WRITE
E a
SYSTEM BLS DURING WRITE = = = == == == = == = — <
SYSTEM BUS ENABLE
SYETEM BUS OUTFUTS = == == == == == —-=-=-— == == = =
= — = — — —т rar Er Eas EEE EEE Eas | каки. Она. —
VOLTAGE MEASUREMENT POINTS: Dg-D7 (when outputs) Logie "0% = 0.8Y, Lagic 17 = 3.0V, Allather signals measured
at 1.54.
A.C. Characteristics T, = 0°C to 70°C; Voce = BV 15%.
| Limits
Symbol | Parameter Min. | Max. Units Condition
tow Width of Status Strobe 22 rs
tss | Setup Time, Status Inputs Da-D7 8 ns
ts HoldTime, Status inputs Dg-D7 ОО 50 ns
toc Delay trom STSTEB to any Control Signal __——— | 20 | 60 ns CL = 100pF
tan Delay from DBIN to Control Outputs o | 30 4 CL = 100pF
tRE Delay from DBIN to Enable:Disable 8030 Bus | 45 15 C, = 25pF
teo Delay from System Bus to B060 Bus during Read ; : 30 75 | C, = 25pF
WR Delay from WR to Controt Qutputs 5 | 4 4 | C, = 100pF
WE Delay to Enable System Bus DBy-DBz after STSTE | 30 as | ©, = 100pF
twp Delay from 8080 Bus Da-Dy 10 System Bus 15 | CL = 100pF
] DBy-DB7 during Write 5 | 40
te Delay from System Bus Enable to System Bus DBo-DB, 30 ~s | C, = 100pF
typ | HLDA to Read Status Outputs ВОО 025 в
tos Setup Time, System Bus Inputs to HUDA ) 10 i 75
‘он Hold Time, System Bus Inputs to HLD A 20 | ns Cp = 100pF
5-10
SCHOTTKY BIPOLAR 8228
D.C. Characteristics To = 0°C to 70°C: Мос = БУ 5%.
T
Limits
Symbol Parameter Min. [Typ.111! Max. Unit Test Conditions
Ve Input Clamp Voltage, All Inputs 75 | -1.0 Y Vee=4.75V; lp=-BmA,
le Input Load Current, | ; |
— STSTS i | 500 НА Vee =5.25V
| 0; & De 7800 LA Ve =0.46V
: Do. Di. Da, Ds. | | | НА
| &D7 | | | 250 |
All Other Inputs | ° 250 | НА
| . Input Leskage Current
| STSTÉ 100 HA Vec=5.25V
| DBy-DB7 ; | 20 нА | Vr =5.25V
All Other Inputs | 190 НА
\тн Input Threshold Voltage, All Inputs 08 : 20 | y Vee = BY
lec Power Supply Current ; 140 | 190 T mA Voc=5.25V
VoL Output Low Voltage,
‚ Роб; ‚45 \ Veo=4.75V; lg =2mA
| All Other Outputs : 45 YW lor = 10mA
Von Output High Voltage, |
By-D7 36 : 3.8 Y Vec=4.75Y: lgH=-104A
All Other Outputs 24 | \ lgH = -IMÁ
los Short Circuit Current, All Outputs 15 90 mA Vec=5V
loto: Off State Output Current, | |
All Control Outputs | 100 | pA Vec=5.25Y: Vo=5.25
| ; -100 KA à Vo=45V
WNT INTA Current : | 5 mA | (See Figure below}
Mote 1; Typical values are for Ta = 75°C and namınal supply vo! tages.
Capacitance This parameter X Darodically sampled and nor 100% tested,
Limits
Symbol Parameter Ми. | Тур!!! | Мах. Unit „12
Cin Input Capacitance 8 12 : pF
Сост o o. , 15 pF 17 - 10%
1/0 a ee 8 15 | pF
8278
TEST CONDITIONS: Vg ag=2.5V, Vee =5.0V, Ta = 25°C. f = 1MHz,
Nota 2:
For Dy-D7: Ry = 4K0, Aye ef, [Ver
CL = 25pF. For all other outputs: TEST CIRCUIT"! 4
Ry = 5009, Вэ = 1K9, CL = 100pF. gn
QUTÉLT
FIN
E
Е В
INTA
hry
INTA Test Circuit (for AST 7)
5-11
SCHOTTKY BIPOLAR 8228
£ 25 -
GH — e — = A.
20 *
SOY mm a А, cé = А
т 77
вм a] Ay —
78 29 °
«12% | Ay “A
30
A, — a.
31
A;
az
А == А
3080.40. Ela, *
Le a ba
Vu "ay — ACORESS aus
а, =: a,
13 as -
SYSTEM IMA REO | HOLT Ад = A
: a
Arc = A.
40
А,, = à.
14 1 17 à
—i
SYSTEMINT AED ——— ont i +
Ay = а
th 38
INT ENABLE == INTE PE — A,
А 35 N
15 | 18 Ae |
у; В 7
17
MTAL DEIN : .
21 E.
(+ OLA i
14 79 2| 4! 34
12 11 22
TANK em \ 10 15 13 a
12 10 15, Pol DEL = =————— DE,
Ost +— — —} ; 9 17 16
6 7, = = 86
; 'TTL| — za A 12 11
od WAT a, № ор LH,
3 82724 a 3 7 1 8228
Ар! — — = BLOCK — ———e | READY п = +— —d Bl DIRECTONAL E —e a —. DB,
GENERATOR 3 BJ HUSNRIVER En - CATA BUS
E DRIVER 1 12 poe —e = — В,
BEGIN — = —— -———— «| arfser 4 15 1Ё
q De — - oe,
+12 — — | 5 21 20
16 Da A EE == —| H— — © а — ба,
+5 ——eb 5 1 ñ В
E pa = —— SHC OD, ra — CE.
ЭМО — — += =F —- — — — — — 1 —
а ву —— = Ге = | ТА
r 14 dd
i см — — = Li. MERA PO
STATUS STROBE 1 SYSTEM | 26 —
CONTROL > — MEM NL CORTADA BUS
72 — | OR
ВЫбЕМ — — — — — = {3 27 XT
e OW
8080A CPU Standard Interface
intel Silicon Gate MOS 8080A
SINGLE CHIP 8-BIT N-CHANNEL MICROPROCESSOR
The 80804 is functionally and electrically compatible with the Intef® 8080.
as TTL Drive Capability a Sixteen Bit Stack Pointer and Stack
Manipulation Instructions for Rapid
“ 2 us Instruction Cycle Switching of the Program Environment
= Powerful Problem Solving » Decimal Binary and Double
Instruction Set Precision Arithmetic
= Six General Purpose Registers a Ability to Provide Priority Vectored
and an Accumulator interrupts
» Sixteen Bit Program Counter for =" 512 Directly Addressed 1/0 Ports
Directly Addressing up to 64K Bytes
of Memory
The Intel® 80804 is a complete 8-bit parallel central processing unit {CPU}, It is fabricated on a single LSI chip using Intel's
n-channel silicon gate MOS process, This offers the user a high performance solution to controi and processing applications.
The 8080A contains six 8-bit general purpose working registers and an accumulater, The six general purpose registers may be
addressed individually or in pairs providing both single and double precision operators. Arithmetic and legical instructions set
or reset Tour testable flags. A fifth flag provides decimal arithmetic operation.
The 8080A has an external stack feature wherein any portion of memory may be used as à last in/first out stack to store/
retrieve the contents of the accumulator, flags, program counter and all of the six general purpose registers. The sixteen bit
stack pointer controls the addressing of this external stack. This stack gives the B08DA the ability to easily handle multiple
level priority interrupts by rapidly storing and restoring processor status. it also provides almost unlimited subroutine nesting.
This microprocessor has been designed to simplify systems design. Separate 16-line address and 8-line bi-directional data
busses are used to facilitate easy interface to memory and 1/0. Signals to control the interface to memory and 1/0 are pro-
vided directly by the 8080A. Ultimate control of the address and data busses resides with the HOLD signal, tt provides the
ability to suspend processor operation and force the address and data busses into a high impedance state. This permits OR-
tying these busses with other controlling devices for [DMA] direct memory access or multi-processor operation.
a *
7". S080A CPU FUNCTIONAL | a De ,
que - 0 B-DIRECTIONAL A
С BLOCK DIAGRAM 54... + DATA BUS . ло
CRE : sid
ECU 7 A LH и В
ЧАИ: о : 5 ЗЫ
За o LEAT ee SATE. EL RE bon
. A ; "INTERNAL DATA BLE INTERMAL DATA SLX HE
a - 1 1 N
WAHR ZX Ir ' ra 1 т 2. e ' RE. т.
AC ACCUMULATOR TEMP, REG. E. 5. | WSTAUCTION 74] n ` ES
TA i Зе. : - | "a 18! 7 TT ETT
MT - 4 FLAG М - ET
o 1 уч TEMP REG. TEMP REG. peña
RE FLIP FLOPS ;
mee ACCUMULATOR 1... > - a El £ Ig
же LATCH 181 FE - cr REC. REG а
ir TS - er
Ca 4 JAR ITHMET IE - INSTRUCTION is о el E A EE
SE | Mo LOGIC DELODER o REG. REG. GET El
al : wait | EE. MACHINE " = HO LH __REGISTER
5 ALU fre m REG. REG ARRAY.
Me : E ; ENCODING щ 1 EE
ЖЕ, - nl = a STACK POINTER mf
У 1 IES . 118 1" o
tr , " - E Tes PFROGHAM COUNTER *, '
a Eo o EE
HERE DECIMAL . o INCAEMEN TER/DECREMENTER Bo
- 20 В Мо 1 ADS . - ADDRESS LATCH 1161 . ve meto
x PE Tew TT . : EC Toa. ‚ . eE q
ON . . a “ e o i ZA ABEL С.
ae . .. - E In. - . .. - . ETE, .
a = _ TIMING ‚о RÁ E UTA MERA 4
SED ado * * - AND | E : ee EET
©. . … CONTROL +. E.
Lo - 1161 ad
vo TOWER |e aly | ADDRESS BUFFER | E
_ SUPPLIES | — y DATA BUS INTERRUPT HOLD WAIT oy. Tu
WRITE CONTROL CONTROL CONTROL CONTAGL SYNC CLOCKS RT ER отов.
` r— БМ : : : - TE
—— | Py | bd €
. o CE : - В 2. WET
WR OEM INTE INT HOLD NOLOWAIT | SYNC ef où RESET Ay + Ag Lu Re
. ACK -.. READY ; . : appacet BUS TT EL
513
SILICON GATE MOS 8080A
8080A FUNCTIONAL PIN DEFINITION
The following describes the function of all of the ВОВОА 1/0 pins.
Several of the descriptions refer to internal timing periods.
A45.A9 (output three-state}
ADDRESS BUS, the address bus provides the address to memory
(up to B4K B-bit words) or denotes the 1/0 device number for up
to 256 input and 256 output devices. Ag is the least significant
address bit.
D7-Dg (input/output three-statel
DATA BUS; the data bus provides bi-directional communication
between the CPU, memory, and 1/0 devices for instructions and
data transfers. Also, during the first clock cycie of each machine
cycle, the SOBÜA outputs a status word on the data bus that de-
scribes the current machine cycle, Dg is the least significant bit.
SYNC loutput}
SYNCHRONIZING SIGNAL; the SYNC pin provides a signal to
indicate the beginning of each machine cycle,
DBIN (output)
DATA BUS IN; the DBIN signal indicates to external circuits that
the data bus is in the input mode. This signal should be used to
enable the gating of data onto the B0BUA data bus from memory
or 1/0.
READY {input)
READY; the READY signal indicates to the 808A that valid
memory or input data is available on the BOBDA data bus. This
signal is used to synchronize the CPU with slower memory or 1/0
devices. If after sending an address out the 80804 does not re-
ceive a READY input, the B0BOA will enter a WAIT state for as
long as the READY line is low, READY can also be used to single
step the CPU,
WAIT (output)
WAIT; the WAIT signal acknowledges that the CPU is in a WAIT
state.
WR loutput)
WRITE; the WR signal is used for memory WRITE or 1/0 output
control. The data on the data bus is stable while the WR signal is
active low (WR = 0).
HOLD (input)
HOLD; the HOLD signal requests the CPU to enter the HOLD
state. The HOLD state allows an external device to gain control
of the BOSOA address and data bus as soon as the 8080A has com-
pleted its use of these buses for the current machine cycle. It is
reccgnized under the following conditions:
® the CPU isn the HALT state.
* the CPU isin the T2 or TW state and the READY signal is active.
As a result of entering the HOLD state the CPU ADDRESS RUS
lA15-Ag} and DATA BUS (D4-Dg) will be in their High impedance
state, The CPU acknowledges its state with the HOLD AC-
KNOWLEDGE (HLDA) pin.
HLDA (output)
HOLD ACKNOWLEDGE: the HLDA signal appears in response
to the HOLD signal and indicates that the data and address bus
1 =_=
A. O! 40 p—e0 Ay
GND Cm 2 39 -——0 Aya
о, ©«—1 3 38 С А1;
D, очей 4 37 +0 А:
D; O+— | 5 36 [О А);
0, ож 6 35 p—=0 Ay
D, a 7 М p—=0 Ag
D, 0=-—{ 8 INTEL 33 H—0 Az
0, 0+—— 5 32 О Ад
p, 90 60804 ios
EV O—o 11 30 ES A
RESET 0— 17 29 С) Ay
HOLD O=—ed 13 28 РО +12\
INT O——{ за 27 FO A,
“2 O—— 15 26 —0 A
INTE 04 16 25 p——0 A
DEIN Co 17 24 e) WAIT
WR O=— 18 24 pr--Q) READY
SYNC O-— 19 272 [0 61
+5V O— 20 21 =O HLDA
1
Pin Configuration
will go to the high impedance state. The HLDA signal begins at
Ta for READ memory or input.
# The Clock Period following T3 for WRITE memory or OUT
PUT operation.
In either case, the HLDA signal appears after the rising edge of à
and high impedance occurs after the rising edge of de.
INTE {output)
INTERRUPT ENABLE; indicates the content of the internal inte:
rupt enable flip/flop. This flip/flop may be set or reset by the Er
able and Disable Interrupt instructions and inhibits interrupt
from being accepted by the CPU when it is reset. It is autc
matically reset (disabling further interrupts) at time T1 of the ir
struction fetch cycle (M1) when an interrupt is accepted and |
also reset by the RESET signal.
INT {input)
INTERRUPT REQUEST; the CPU recognizes an interrupt re
Quest on this line at the end of the current instruction or while
halted. If the CFU isin the HOLD state or if the Interrupt Emable
fhp/flop is reset it will not honor the request.
RESET (input}(1!
RESET; while the RESET signal is activated, the content of th
program counter is cleared. After RESET, the program will star
at location O in memory. The INTE and HLDA flip/flops are aise
reset. Note that the flags, accurnulator, stack pointer, and register:
are not cleared,
Yes Ground Reference.
“bb +12 3 5% Volts,
Yee — +5 + 6% Volts,
Vag -5 +5% Volts lsubstrate bias).
21,92 2 externally supplied ciock phases. {non TTL compatible
> 14
SILICON GATE MOS 8080 À
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ....... . eee... OC to+70%C “COMMENT: Stresses above those listed under “Absolute Maxi-
Storage Temperature .... .. 2.2... „55°C to +150°C mum Ratings may cause permanent damage to the device,
This is a stress rating onfy and functional operation of the de
All Input or Output Voltages vice at these or any other conditions above those indicated in
With Respectto Vag .............. -0.3V to +20V the operational sections of this specification is not implied. Ex-
Vec. Yoo and Vgg With Respect to Vag -0.3V to +20V posure to absolute maximum rating conditions for extended
Power Dissipation © ©... CL oo ea 1.6W periods may affect device reliability.
D.C. CHARACTERISTICS
Ta =0°C tc 70°C, Wap - +12V + 5%, Ver = +5V 2 5%, Veg = —5V 1 5%, Ves = OV, Unless Otherwise Noted.
-
Symbol Parameter i Min. Typ. Max. Unit ! Test Condition
Vile Clock Input Low Voltage | Vge—1 Yest0.a : Y
Ya Clock Input High Yoltage | 2.0 Yno+1 \
IL input Low Voltage , Ves-1 Veg +08 Y
\ ин Input High Voltage 3.3 ¡ Mce*1 1 Y
|
You Output Low Voltage 1 0.45 V lo = 1,9má an all outputs,
Von Output High Voltage 137 у Юн =-159дА.
Io (AV: Avg. Power Supply Current (Vp) - 40 70 mA
— | Operation
lec LAI Ava. Power Supply Current (Мес! 60 80 mA Tey = 48 usec
laniavi Avg. Power Supply Current (Ygg) 01 1 mA J
UT Input Leakage 10 НА Vgs & Vin # Усс
ler Clock Leakage +10 HA Ves € YcLock = Yno
Ig (2! © Data Bus Leakage in Input Mode -100 | нА Ve Мы =Vsg+0.8v
- J
| 72.0 | MA | Ves +0.8V<Vy €Vec
|
' 1
не | |
| Adaress and Data Bus Leakage +10 LA VADDA/DATA Ÿ Yet
FL ; bo =
During HOLD i 100 VADDR/DATA 7 Vss + 0.4BV
] 1
CAPACITANCE TYPICAL SUPPLY CURRENT vs
= RS _ = = = RE, NORMALIZED.
Ta = 25 С Vee = Voo = Vss 7 OV, Vpa = -5V 5 TEMPERATU ,
* |
Symbol | Parameter Typ. Max. Unit Test Condition -
. mel
Ce Clock Capacitance 17 25 pf f. = 1 MHz z |
В 1.04 =
Cin Input Capacitance 6 10 pf Unmeasured Pins > 1
E
CouT Output Capacitance 10 20 pf Returned to Vgg a ' ;
NOTES: |
1. The RESET signal must ba actwe for a minimum of 3 clock cycles, 9°, +25 -55 "75
2. When DBIN is high and Y gy > Y (y an internal active pull up will AMBIENT TEMPERATURE CE
be switched onto me Cata Bus,
3 Alsupply : ATA =-045%C.
DATA BUS CHARACTERISTIC
DURING DBIN
|
MAX IH —— ——R—
Tn
бо м
сс
5-15
SILICON GATE MOS 8080A
A.C. CHARACTERISTICS
Ta =0°C to 70°C, Vpp = +12V + 5%, Veo = +5V 4 5%, Ygg = -5V + 5%,
Yes = OV, Unless Otherwise Noted
Symbol Parameter Min. | Max. | Unit Tast Condition
toy 31 | Clock Period 0.48 | 2.0 | usec
LO Clock Rise and Fall Time D 50 | nsec
ta #1 Pulse Width 60 | nsec
tez dy Pulse Width 220 | nsec
tos Delay 6; to de G nsec
‘02 Delay 05 to фу 70 nsec
‘03 Delay © to ¢5 Leading Edges 80 sec
tpa [2] | Address Output Delay From $3 200 | nsec } CL = 10008
top 12! | Data Output Delay From 6, 220 | nsec
toc!2! | Signal Output Delay From d, or Ga (SYNC, WRWAIT, HLDA) 120 | nsec
tor [21 | DBIN Delay From 6 25 140 | nsec ta sopt
tg 1] Delay for input Bus to Enter input Mode tor | nsec
1051 Data Setup Time During $1 and DEIN 30 nsec
TIMING WAVEFORMS !'*
Note: Timing measurements are made at the following reference voltages: CLOCK “17 = 8,04
“0 = 1,0V; INPUTS “1° = 3.3V, “07 = 0.8V; OUTPUTS "1° = 2.0V, "0" = 08V.]
| ———— = ‘ом — |
— = в,
A
A:
| ор
= 7 -| |
“| ta |=
Bm Ag
Pr a
‘np ——
[очи Ú— |
y DATA OUT
LO = ла = нь P N a mr
SYNC i
—r| ng ==
DEIN A,
|
‚ Ты —=
READY ABA
. Toei Le 1 . |
tag [ei p5 —e DE e
WANT бу rw 7 \ |
‘ос — vi — Hoe --
HOLD |
ex
— e —
HLCA
INT a
Тен
by am =
INTE
518
SILICON GATE MOS 8080A
A.C. CHARACTERISTICS (Continued)
Ta = 0°C to 70°C, Vpp = +12V + 5%, Vec = +5V + 5%, Vag = -5V £ 5%, Vgg = OV, Unless Otherwise Noted
Symbol Parameter | Min. | Max. | Unit \ Test Condition
tos: Data Setup Time to 67 During DRIN 150 nsec
tpn it! | Data Hold Time From dy During D81N [1] nsec
te [2] INTE Output Delay From de 200 | nsec CL = 50pf
tas READY Setup Time During #7 120 nsec
tHs HOLD Setup Time to 9» 140 nsec
Lg INT Setup Time During 93 (During ey in Halt Modal 120 nsec
tH Hold Time From g9.1READY, INT, HOLD) : 0 nsec
tro Delay to Float During Hold {Address and Data Bus) 120 { nsec
tawl2! | Address Stable Prior to WR (5) nsec | |
towl?! | Output Data Stable Prior to WR [6] rt sec
twol?! | Output Data Stable From WR [7] nsec
twal?] | Address Stable From WR [7] nsec — са вор WR. bt DA, DEIN
tyHel2! HLDA to Ficat Delay [8] nsec
twel21 | WA to Fioat Delay [9] nsec
tan [2] | Address Hold Time After DBIN During HLDA -20 | [nsec |_|
MITES.
1.
Cara input ihould ba го Нео) with DE statu,
Ho bus eoniher can Lhén бб ВР и hold бий и вином,
tH * BO ng Or thE. whichever 15 Tess
2. Load Circuil,
1 TN A FEY
2.1K
* :
a SOBDA
OUTPUT
u ED —
. 1 ' FL
Ay Ay === RS - =
[+ wa 3. toy “103 tez + tez * Tg7 7 107 + pt > ABONS, =
DD вн — ! я den = _ +2 — - | - |
+ — typ É
> +10 —
SYNC tos | x | |
| . - „| |" Тан = а | A Ç
1 . = | “,
DEIN : jf \ = В “SEC |
=
= - T
1 : | 1 © " Pa :
WA |! - 7 |
I dt] ; 1 mm
i 100 „50 | +50 +100
laa] ‘с \
| |
READY > » CAPACITANCE fai)
IC - E 1
| te — ACTUAL CPE.
WaT |
| 4, Tha following are relevant when intertacing the BOB0A to devices having V ¡y - 3.3:
al Maximum output rise teme trom BY to 3.3% = 1000s & Cy = SPELL,
HOLD *— be! Ouipat delay when meayzurad to 1,0% = SPEC +60 @ Ç, = SPEC.
a ef IFC = SPEC, add EnvipF 1 C[> Cspeg, wbrract Ins/pF trom modified delay] il C| < Cgpeg.
i —| toc |=e— 5. fau" 2tCY -tog Ir? - 40ntec
HLDA = E. OCW: tcy -[09 “tráz -1 TOnsec.
fm i T. Monat HLDA two = ya = TO4 * tag *T0ns. ML HLDA, wo = ya “ TWF.
4. "HF =ug3 * trp? -Bûns.
мт К 9. WE = 103 + Lgz - 1065
Fr 10. Data in must be stable for this period during DE IN “Ta. Bath ing and 1059 must be tatisfied.
11. Ready wgnal must be stable for this period during To or Ty. [Must be externally synchronized.)
la- Le i 17, Hold signal must be sirble tor tha cariód during To ór Tu hen entering hold moda, and during T4, Ta, Ts
E and Twy when in hold mode. ¡External ey nchromzation 15 not required.)
INTE - 13. Interrupi egral must ba stable guring this period of the last clock cycle of any imiTruELIOA IN Grder To ba
==! recognized on the following instruction. ¡External ryschronization it not required.
1d. This tmming digram shows Timeng ralaucnyhipn only; it does NOT represent any saci Machine Cycia.
ha TR
517
SILICON GATE MOS 8080A
INSTRUCTION SET
The accumulator group instructions include arithmetic and
logical operators with direct, indirect, and immediate ad-
dressing modes,
Mave, load, and store instruction groups provide the ability
to move either B ar 16 bits of data between memory, the
six working registers and the accumulator using direct, in-
direct, ang immediate addressing modes,
The ability to branch to differant portions of the program
is provided with jump, jump conditional, and computed
Jumps. Also the ability to call to and return from sub-
routines is provided both conditionally and unconditionally.
The RESTART (or single byte call instruction) is useful for
interrupt vector operation.
Double precision operators such as stack manipulation and
double add instructions extend both the arithmetic and
interrupt handling capability of the 8080A. The ability to
Data and Instruction Formats
increment and decrement memory, the six general registers
and the accumulator is provided as well as extended incre-
ment and decrement instructions ta operate on the register
pairs and stack pointer. Further capability is provided by
the ability to rotate the accumulator left or right through
or around the carry hit.
input and output may be accomplished using memory ad-
dresses as 1/0 ports or the directly addressed |/O provided
tor in the 8080A instruction set.
The following special instruction group compietes the 80804
instruction set: the NOP instruction, HALT to ston pro-
cessor execution and the DAA instructions provide decimal
arithmetic capability. STC allows the carry flag to be di-
rectly set, and the CMC instruction allows it to be compie-
mented. CMA complements the contents of the accumulator
and XCHG exchanges the contents of two 16-bit register
pairs directly.
Data in the BOBOA is stored in the form of B-bit binary integers. All data transfers to the system data bus will be in the
same format.
[D7 Dg Ds Da Da Dy O Do |
DATA WORD
The program instructions may be one, two, or three bytes in length. Muitiple byte instructions must be stored
in successive words in program memory. The instruction formats then depend on the particular operation
executed.
One Byte Instructions
| 07 Dg Ds Dg Dy Dy Dy Dy | OP CODE
Two Byte Instructions
| Dr Ds Ds D4 D3 Dy Dy Dy | OP CODE
[D7 Dg Ds Dg D3 Dy Dy Do | OPERAND
Three Byte Instructions
| D7 Dg Dg Dg D3 Dy Dy Dy | OP CODE
| D; De Ds Da D3 Dy Dy Do |
| D; Dg Ds D4 Da Dp D;
Do |
TYPICAL INSTRUCT IONS
Register to register, memory refer-
ence, arithmetic or logical, rotate,
return, push, pop, enabie or disable
Interrupt instructions
Immediate mode or 1/0 instructions
Jump, call or direct toad and store
instructions
LOW ADDRESS OR OPERAND 1
HIGH ADDRESSOR OFERAND?
For the SODA a logic 1 is defined as a high level and a logic O” is defined as a low level.
518
SILICON GATE MOS 8080A
INSTRUCTION SET
Summary of Processor Instructions
Imtruction Code!!! Clock 12] instruction Codalt) Clock (2!
Меынтинис — Dmerigtion Dr Oy Os Dy D; № Dy On Сус Maemenic — Description bh Dy № 0, Dy Op O04 Og Cycles
MOV yz Mave register to register DD 0 0. 0. 5 5 5 5 RZ Artur gn cero 1 1 0 0 1 0 = CE 511
МОМ М, г Move segislar to memory # 1 1 1 0 5 5 5 7 ANZ Retum pn ng Zero 11 A O 0 9 2 0 5/1!
MOV. WM Move memory tó regitcad ú I à 0 & ! 1 0 7 Ap Return gn pouties 1 1 1 10 0 0 0 5/11
HLT Hal û 1 1 3 1 10 T AM Return gn minus 1 1 1 1 1 6 0 0 8/11
ММГ Move »IMMediate register ù à D D D 1 1 Ù 1 RPE Return on parity ween 1.1 1 0 1 0 0 0 5/1
MyL M Move smmedinie mammary gg 1 10 tt 1 0 19 RPO Katurn on perity vdd 1 1 1 a YX D 0 D $T
'HAr Ircrément régirter 9 à IS 0 0 Vv 0 0 3 RET Arstart 1 1 A A A 1 1 1 11
OCA y Decrament regrstor 0 DO T 1 01 3 I Iapul 1.1 00 1 1 ÿ 1 1 10
INF Incremant memory g 0 1 + E 1 O Y 19 OUT Qutpur 1 1 0 1 9 0 + 1 10
OCA M Decremant mamory 0 0 1 1 D 1 0 1 17 LX 8 Load immadisie ragicier B 4 A 0 a 0 à t 0
ADD Fr Add reger 10 A 10 0 0 0 5 SÉ + Pair B EC
ADC r Add ragesiar to & with carey 1 9 0 0 17 5 58 5 + LXI D Losd immedinte registér 9 a 0 1 O © 0 1 10
SUB + Subtract register from à tr O 9 1 U 5 5 5 4 Раг О & Е
SEBr Subtract register from À 1 nb» 1 5 5 a LXI H Load immediate register 00 1 1 O 4 9 1 10
мет Barrow Pair H AL
ANA r And regiarar with A 1 06 1 0 0 5 5 3 4 LXI SP Load immédiald stack pointer UB 1 1 ÿ 0 0 1 10
XAA r Evctunive Or regrinar anih A 1 0 1 01 5 8 0 8 4 PUSH A Push register Pair B & C an 1 1 ù 0 0 1 0 1 1
ОКА г Or register with А TM 1 1 0 5 §& § 4 atack
CMPI Compara regirter with À 1 0 1 1 1 85 § 5 4 FUEH D Push register Parr O AE on Por O 1 0 1 BA 11
ADD M Add memory 16 À 1 0 ÑO A #® 1: 1! M 7 Hack
ADC M Add mámery 16 A wth carry 100 O MT 1 A 1 PUSH H Push register Pair H & |. оп 1 1 1 0 O 1 DA 11
SUB M Subtract memory Tram A 1 04 7 0 1 TO T stäch
588 M Subiract memory tam A 1 0 BB 1 1 1 1 9 PUSHPSW Push A and Flags 1,1 + 1 ÿ 1 0 ! 11
with bôrrôner on stack
ANA WM And memory ve À Po 1 ÿ 6 1% O 7 РОР В Pop register pair 8 8 Coll 1 1 6 0 0 9 0 1 10
XFA Mi Exclusive Cr mamery wah A то тет то ! stack
ORAM Or memory wilh A 10 1 1 9 1 1 Q 7 POP O Pog register pair O 8 E ofi 1 1 0 1 0 9 a 1 10
CHF M Compare memory with A 180 1 1 1 F 1 0 7 stack
All Add immediate to A t 1 ag 0 E ECO 7 FOF H Pop register peer H & L aff 11 1 $ 0 0 0 1 10
ACI Add immediate 10 A with Tr 00 1 * #t 0 7 stach
Eur FOP PSW Pop A and Flag 1 1 1 1 8 0 0 1 10
stn Subtract immadvate fram & 1 1 0 … a 1 1 0 7 Dl mack
Sal Subtract immediata Hur A тя ото : STA Store A diract D o 1 ra AE 13
wilh borrow LOA Load A direct D O 1 TA AD 13
ANI And immediate with A 1.1 1 Ù 1 1 0 1 CHO Exchange D&E, H&L 1.1 1 0 1 0 1 1 4
ХИ! Extlutiva Or imma diate with тя то ТЕТ 7 Regina:
A XTHL Exchange 10p ot Hack, Hal 1.1 1 @ & 0 MM 18
CAI Dr amadas wah A 1 1 1 1 0.0 1 1! À 7 SPHL H& | m stack pointer 1 + 1 1 * oot F
CPI Compare immadisie wih A 1 1 1 1 + 1 1 Û 7 FCHL HA Lig program counter t 1 1 6 TOA! a
RLE Aosta A [aft ooo 0 a 1 101 à DACE Add BACTtIHAL 0 0 do о 1 BD 1 10
RAL Rotate A right a 00 0 o 1 1 11 4 DADO Add DSEt HAL 0 0 0 1 1 6 MA 10
MAL Rotate Á lelt through caríy nog ео 1 0 t 1 1 1 DAD H Add HALIHAL 0 6 1 0 1 0 4 | 10
AAR Роша А night through a 4 ÿ 1 1 1 1 1 4 DAD SP Add rtack ponte на Н & 1 D 1 1 1 D 1 10
carry STAX E Store A indirect 0 O O O O O 1 Y 7
JMF Jump unconditional 1 1 0 0 9 O TOA] “0 STAXD Store A mdirect a 9 9 1 2 0 1 0 7
JC Jump on carry 1 1 0 1 4 € 1 M ‘0 LDAXE Load A indirect 0 0 0 0 IT € 1 À 7
HC Jump on na carry + 1 0 1 D 0 1 0 10 LDAXD Load A indirect 6 0 0. 1 1 0 1 e 7
12 Jump gn Isp 1 + OM O 1 A TO 19 NX B Increment B & © registers O O O Ú 0 1 1 5
INZ Jump on ng care 1 1 4 0 O O 1 A 10 E E: Ineramant D 8 É register 0 6 O 1 a 0 11 5
JP Jump on positive l 1 | 1 A 0 1 © 10 INKH Imcrement H 6 L registers à à 1 60 O 1 5
JM Jump on minut 1 1 1 1 1 aa 0 INX SP Increment slack pointer 0 0 1 1 4 8 11 5
FE Jump on panty even t 1 1 D + 0 1 0 11 DCX B Decrement 8 & С 9 0 © BS 1 a 5
JO Jump on pamy odd 11 1 0 0 0 IT 0 -3 DEXO Dacramant 0 & E 0 0 0 Ir + @ 1 1 5
CALL Call yncondingnal 1 1 a ù 1 1 0 1 17 . DCX H Decramant MEL оо 1 o1 4 1 t 5
CC Call on carry 111 A TIT TT PO 21-17 OCA SP Dacremant stack porntar 0 à 1 1 1 D toa 5
CHE Coll on no cam 11.0 1 qd 1 4 9 117 CMA Complement A ag ù 1 0 1 1 11 4
СЁ Call on zaro 1 1 0 & 1 1 0 0 117 STC Sel carry Ó o t 1 0 1 101 4
ENZ Call oa no zero 1 1 $ 6 * D 0 11.17 CMC Complement carey a 0 +r 1 1 1 1 4
CF Call an positive 1 1 1 + 5 1 D 0 0 11.17 CAR Decimal edjuxt À a a 1 9 0 1 1! 1 4
CM Call an minus 1 1 1 1 + 1 0 0 14-17 SHLO Segre H & L direst 0 0 1 6 8 0 1 0 16
CPE Call on party en 1 t 1 AO 11717 LHLD Lows H & L direct à 0 1 g 1 & Ea 16
СРО Call on parity odd 1 1 1 Oli 0 o 19117 El Erable Interrupts 1 1 1 1 1 Ÿÿ 1 1 a
RET Aaturn Por O Oo 1 0 DE 10 Qi Disable interrupt 1 1 O A ta à
RC Arun on carry 1 1 0 # 1 U @ Û Et NOP No operation 0 0 0 0 AN 90 0 0 a
RNC Return gn ng carry 1 1 0 1 5 0 OE 5.11
NOTES:
1. DOC or 555 — 000 E — 601 € — 010 D — 011 Е - 100 Н — 101 L-— 110 Memory — 111 А.
2. Two possible cycle times, (5:11) indicate instruction cycles dapandent on condition flags.
5-18
intel Silicon Gate MOS 8080A-1
SINGLE CHIP 8-BIT N-CHANNEL MICROPROCESSOR
The 80804 is functionaliv and electricaliy compatible with the intel? SOB0
ев TTL Drive Capability = Sixteen Bit Stack Pointer and Stack
. Manipulation Instructions for Rapid
" 1.3 us Instruction Cycle Switching of the Program Environment
= Powerful Problem Solving
| a Decimal, Binary and Double
Instruction Set Precision Arithmetic
" Six General Purpose Registers E Ability to Provide Priority Vectored
and an Accumulator Interrupts
= Sixteen Bit Program Counter for « 512 Directly Addressed 1/0 Ports
Directly Addressing up to 64K Bytes
of Memory
The Intel® ВОВОА is a complete B-bit parallel central processing unit (CPU). It is fabricated on a single LSI chip using Intel's
n-channel silicon gate MOS process. This offers the user a high performance solution to control and processing applications.
The SOBOA contains six B-bit general purpose working registers and an accumulator. The síx general purpose registers may be
addressed individually or in pairs providing both single and double precision operators, Arithmetic and logical instructions set
or reset four testable flags. A fifth flag provides decimal arithmetic operation.
The 80804 has an external stack feature wherein any portion of memory may be used as a last in/first out stack to store/
retrieve the contents of the accumulator, flags, program counter and all of the six general purpose registers, The sixteen bit
stack pointer cantrols the addressing of this external stack. This stack gives the B080A the ability to easily handle multiple
level priority interrupts by rapidly storing and restoring processor status. It also provides almost unlimited subroutine nesting.
This microprocessor has been designed te simplify systems design. Separate 15-line address and 8-line bi-directional data
busses are used to facilitate easy interface to memory and 1/0. Signals to control the interface ta memory and +/0 are pro-
vided directly by the 80804, Ultimate control of the address and data busses resides with the HOLD signal, It provides the
ability to suspend processor operation and force the address and data busses into à high impedance state. This permits OR-
tying these busses with other controlling devices for (DMA) direct memory access or multi-processor operation.
8080A CPU FUNCTIONAL Ш 7D
a сс. BE-CIRECTIONAL рта
BLOCK DIAGRAM ET Le SUN DATABUS NE
aa +
Зет
>
>: Re DATA BUS E
1 - °.: A BUFFER:LATCH bio
INTERNAL DATA HUE : | La
1 NDA
. Lx . , ь ..A Е ko Е У ОВ
ar. . e at
. =} > : , 5 . E К . Ad
ACCUMULATOR TEMP RES 7 Cr | INSTRUCTION RARES
- 91 a 4 To REGISTER A Peor EE
: A a SL E A r 2 MP. ММ:
- MP REG, TEMP REG. PEE RS
ACCUMULATOR 2 4 3 E. 6 MBE ue. MEDAL EF
LA a ; | o: 38 AEG REG. capone dag
i - Al ARITHMETIC . 1 , - INSTRUCTOR = = a E El e A ET -
. ri LOGIC CE DECODER in San REG A ;, CA,
i 1? ANC Er — EPT AA
LIMIT | MACHINE ыы has + AH L [Hi |, REGISTER .
ALU) — o CYCLE 2 Si. REG -. ARRAY,
E . г ENCODING ‚ TE: пу : ; ce м
- wer x STACK POINTER CL me dh
' " | N т ET
У т. . L ney: -
LT но : FAOGRAM COUNTER Caf 0
; DECIMAL 1. | ACSEMENTER/DECREMENTER | у. 5 EA
mi | E DST rier ADDRESS LATCH nef PT A
2° a E ‚ 07 2 = gpl ©. 5 vase ne
to > ju a УВЫ #, В ia
‚ RAA ra . si
= TIMING ; o io et ra fh +,
a AND X + + ; A ; y TT a hE po Pa ge Hs
Sh CONTROL TIT. wR E
POWER | — +t2v Ш роса. A Уре o
WRITE CONTROL CONTROL CONTROL CONTROL SYNC CLOCXA e ET
— BV EA
— GO .- } | КН - 1 Ш. $ |. a | ! | E
2 т OBIN TE: INT HOLD HOLD WAIT: ol од. РЕЗО: TD \ FTE AE
a TT
SET ae ET 2” EE зле. ka US TRE
EA a : EGET con émise titi tin :
SILICON GATE MOS 8080A-1
ABSOLUTE MAXIMUM RATINGS"
Temperature Under Bias
Storage Temperat."=
All Input or Cutout Voltages
With Respect 19 Vgg
Vee, Wop and Ves With Respect 10 Vag
Power Dissipation
-0.3V to +20V
-0.3V to +20V
1.5
| ‘COMMENT: Stresses above those fisted under Absolute Maxi
| mum Ratings” may cause permanent damage to the device,
o TAS iS a stress rating only and functional operation of tha de
\ vite at thèse or any other conditions above those indicated in
| the operational sections of this specification is not implied. Ex
posure to absolute maximum rating conditions for extended
periods may affect device refiability.
D.C. CHARACTERISTICS
Ta =0°C to 70°C, Vpg = +12V £ BY% Vee - +8V + 5%, Veg - -5Y © 5%, Veg = OV, Unless Otherwise Noted.
Symbol Parameter | Min. Typ. Max. | Unit Test Condition
|
Vire Clock input Low Voltage Veg —1 VegtOB | Y
Vine Cigek Input High Voltage 9.0 | Vip + y
VL Input Low Voltage Vsg—1 | Ves 18B O Y
VIH out High Voltage 23,3 | Vegtl © Y |
Yo Jutput Low Voltage 0.45 | \ lgL = 1.9mA on all cutputs,
Усн Output High Voltage 3.7 | ı | \ lon = 150A.
lbp LA AO. Power Supply Current (Yoo! | 40 | 0 mA
| "006 Supoiv Current Vrai 60 $ 30 A Operation
4, Power Su urr | m
CC LAV ~~ PRY CC | Tey = 32usec
leg aw: ~+3 Power Supply Current {Vggt 01 1 MÁ +
> ha T
Hu Input Leakage +10 | HA Vg ® Мм ® Усс
let Clock Leax age +10 | НА Vos = YELOCK = Ven
lp, 12 Data Bus Leakage in Input Mode -100 UA Ves S: Vin Ss Vos + 0.0 Y
| 728 MA Ves +0 8VEVN Veo
„о ; | | —
| Adress and Data Bus Leakage | | | +10 | UA : MADDR/DATA 7 Ver
FE | |
During HOLD ‚ 7109, VADDR/DATA * Vss + 0,45V
CAPACITANCE TYPICAL SUPPLY CURRENT VS.
Т = 25°С Vce = Voo = Vss = OV, Vgg = -5V 5 TEMPERATURE, NORMALIZED, [3]
|
Symbol Parameter ° Тур. Мах. Unit Test Condition =
С Clock Capacitance 17 25 f = $
5 | pacitanc | E f, = 1 MHz 5 ‚Г ] | 1
Cr | Input Capacitance 6 : 10 of Unmeasured Pins = —
Саут ; Output Capacitance 10 20 pi Returned to Veg >
NOTES:
1, The RESET signal must be active for a minimum of 3 clock cycles, 0.50 25 50 75
2. When DBIN ts high and Vp = Vy an internal active Bull up wild
ba switched ont the Data Bus. AMBIENT TEMPERATURE 176)
3 Al supply P ATA = 045% С.
DATA BUS CHARACTERISTIC
DURING DEIN
max = = — _
Le
6-21
SILICON GATE MOS 8080A-1
A.C. CHARACTERISTICS CAUTION When operanng me SOBTA 1 at or Arar fill speed, card must be Xan to U DOC Bring compatiblity telweer S004. 1 8224 and 5:
Ta =0°C ta 70°C, Vpp = +12V + 5%, Vep = +5V + 5%, Vag = -BV * 5%, Vgg = OV, Unless Otherwise Noted
Symbol Parameter Min. | Max. | Unit Tast Condition
toy] + Clock Period 32 | 2.0 | tisec
tr, te Clock Rise and Fall Time 0 25 | nsec
tp $y Pulse Width 50 nsec
ta da Pulse Width 145 nsec
10+ . Delay de to de 0 п бес
tos Delay dy to de 60 п5ес
tos Delay & to 5 Leading Edges 60 nsec |
tna t2] | Address Output Delay From ©) 150 | nsec |
top (2? | Data Output Delay From 05 180 | nsec + CL = 5001
tne (21 | Signal Output Delay From ©, or 92 ISYNC, WB WAIT, HLDA) 119 | nsec | !
tor [21 | DEIN Delay From és 25 130 | nsec | С. = 505!
tp! Delay for input Bus to Enter Input Mode tor | nsec
1051 | Data Setup Time During ¢ and DBIN 10 nsec |
[14]
TIMING WAVEFORMS (Note: Timing measurements are made at the following reference voitages: CLOCK 71” = 8.0V
“0” = 1.0V; INPUTS "1" = 3.3V, 0” = 0.8Y; OUTPUTS "1" = 2,0V, “0” = BY.
| we den
I ¡hai
i
' 1 1
ag | } € j \ ; ;
. | '
‘аз | en ty ee ! e
—_
A
15"
| | — Ñr— чи ны сн TS VET EE Ee ны ны —— на —= —= le EE EE
—=—— ha “+ | —- ‘ди —— —_
=— 0 —— + | — | !; A
— Lu 1 ==,
x 22 DATAN | МО DATA QUT
0, Oy — Tip — — —— PE EE ЧЕН ЧН — —— rr - | Ts zn ka rr A =
1 . - =
— = 251 а le Upa —
SYNC FF \ os — |
—e tap +— — np : '
DEIN E \ |
e ур — np +
READY LL E Ba
—— — не ен не = ыы ны мен e — — ==
WAIT Tw wl | - 7 \
HOLD FE
ex
HLDA
INT 7 13 À |
tig =
Ly — pli
INTE
5-21
SILICON GATE MOS 8080A-1
A.C. CHARACTERISTICS (Continued]
TA = 0°C to 70°C, Vop = +12V + 5%, Veo = +5V = 5%, Vag = -5Y + B%, Vez = 0V, Unless Otherwise Noted
Symbol Parameter Min. | Max. | Unit Test Condition
tpsz Data Setup Time to $, During DBIN 120 | nsec
tow [1] | Data Hold Time From $, During OBIN {11 nsec
tyz [21 INTE Output Delay From 04 200 | nsec CL = 50pt
tes READY Setup Time During 67 90 msec
ths HOLD Setup Time to de 170 nsec
115 INT Setup Time During 09 (Quring 61 in Halt Model 100 nsec |
IH Hold Time From @5 (READY, INT, HOLD! 0 Sec -
teo Delay to Figat During Hold {Address and Data Bus) 120 | nsec
taw!1?] | Address Stable Prior to WR [5: | nsec |
tpyy [2] Output Data Stable Prior to WR : [61 nsec
twol21 | Output Data Stable From WR [7] nsec | |
twal2l | Address Stable From WR [7] nsec |_ Cp =50pf: Address, Data
C\=50pf: WR, HLDA, DBIN
typ [21 HLDA to Float Delay [8] nsec
tw [2] | WR ta Float Delay [9] nsec
14412] | Address Hold Time After DBIN During HLDA -20 nsec | |
NOTES:
1. Oatà input ahquid he enabled Ah DEIN status Ne bus conilict can Then occur and dara holg time is assured.
rH = 800s or snp. whichever 15 less.
3 Load Circan,
$ 2.1K
co _ | A BOBA > К +
: OUTPUT Y
— ‘rep a — Ta © van
— EEE EEE EEE SE SE EE EE a = a +
AA == - we = =
16° E ин ЧН — refer
Г F4 toa 1 toy = 103 + tez + te7 + Hgo + 107 + tral > 37005. -
e ет ето нк що TYPICAL A QUTPUT DELAY VS. 1 CAPACITANCE
916, Вне =" +20 Г .- :
Twi E | |
SYNC >= + _ 1
k a
— сан 5 7
i = 1 1 2e . —
DBIN / \ 2 . o
— | = Вой spec
=
, | J = 10 ' ‚
| .
mT fe we 1m
x he -100 -50 1 +50 + FCO
bu de
READ Y - CAPACITANCE pi
L4— Me —e actual - Cseer
АГ
+— | 4. Tha lollowing ate relevant when interfacing tha BOBOA го devices having VW = 3.34
! ab Maximum output rise rima from ‚BV m 33V = 100m @ CL = SPEC.
Hato *— | bl Output delay whan measured to 3.0М = БРЕС +60г4 & С | = SPEC.
— ; ch 110, + SPEC, add Bns/pF if C > Cgpee, subtract 3ne/pF om modified delay HiF CL < Cepec.-
! | Tne -— 5. La 2 CY 163 -Crgz = Опаае.
HILDA = —0o [5 y CY 103 -'!ra7 =1 БО,
fe— } TI noi HLDA, yo * wa = to * re *100k H ALCA, yp = ra = WE.
B. THÉ" tD5 + lym -H0ns.
NT — 9. twe = to4 + trg7 -10nt
в | 10. Data in must be stable dor this period during DBIN "Tq. Bowh iggy and tog) uit be satisfied.
T 11, Péady eigral must be stable For this pariod быгича То ог Туду, Must be axternally synchronized.)
" e 12. Hold signal must be stable for thiy pared during Ts gr Tw when entaning hold mode, and during Tg, Ta, TR
fC and TWwWy whan in hald mode. (External synchronization 13 aot required.)
INTE 13, interrupt ngnal must be sabie duting this period of the ley clock cycla of Any INSIrucTION IN Order ta be
— recognized on tha lallowing instruction. External ty nchroniZatwon 15 not requined,]
14. The timing diagram shows timing relauonshipy only; it does not regresant any НИЙ machine cyols.
9-23
intel Silicon Gate MOS 8080A-2
SINGLE CHIP 8-BIT N-CHANNEL MICROPROCESSOR
The 80804 is functionally and electrically compatible with the inte? 8080.
a TIL Drive Capability » Sixteen Bit Stack Pointer and Stack
Manipulation Instructions for Rapid
= 1.5 us Instruction Cycle Switching of the Program Environment
= Powerfui Problem Solving = Decimal Binary and Double
Instruction Set Precision Arithmetic
a Six General Purpose Registers w Ability to Provide Priority Vectored
and an Accumulator Interrupts
= Sixteen Bit Program Counter for » 512 Directly Addressed 1/0 Ports
Directly Addressing up to 64K Bytes
of Memory
The Intel® 8080A is a complete 8-bit paratlel central processing unit {CPU). It is fabricated on a single LSI chip using Intel's
n-channel silicon gate MOS process. This offers the user a high performance solution to control and processing applications.
The 80804 contains six B-bit genaral purpose working registers and an accumulator. The six general purpose registers may be
addressed individually er in pairs providing both single and double precision operators. Arithmetic and logical instructions set
or reset four testable flags. A fifth flag provides decimal arithmetic operation.
The BDBOA has an external stack feature wherein any portion of memory may be used as a last in/first out stack to store/
retrieve the contents of the accumulator, flags, program counter ang all of the six general purpose registers, The sixteen bit
stack pointer controls the addressing of this external stack. This stack gives the BOBOA the ability to easily handle multiple
level priority interrupts by rapidly storing and restoring processor status. (t alse provides aimost unlimited subroutine nesting.
This microprocessor has been designed to simplify systems design. Separate 18-line address and 8-line bi-directional! data
busses are used to facilitate easy interface to memory and 1/0, Signals to control the interface to memory and 1/0 are pro-
vided directly by the SOSO0A. Ultimate control of the address and data busses resides with the HOLD signal. It provides the
ability to suspend processor operation and force the address and data busses into a high impedance state. This permits OR-
tying these busses with other controlling devices for (DMÁ) direct memory access or muiti-processor operation.
BUFFER/LATCH
—— daccumuLaTOR| | TEMP REG.
ле wl.
REGISTER : — MULTIFLEXEA |:
INSTRUCT ION
DECODER
AMO
MACHINE
CYCLE
ENCODING
AEG.
L
REG.
REGISTER
STACK FOINTER
PROGRAM COUNTER
INCREMENTEADECAEMENTER
ADDRESE LATCH
TIMING
AND
CONTROL
DATA BUS INTERALPT HOLD ADDRESS BUFFER
WRITE CONTROL CONTROL CONTROL CLOCKS
5-24
SILICON GATE MOS 8080A-2
ABSOLUTE MAXIMUM RATINGS"
Temperature Under Bias .
a. 0°C ta +707 C
Storage Temperature . . . . .. . ........ -65"C 10 150”
Ali Input or Output Voltages
With Respect to Yag ..... e .enme.. -0.3V to +20
‘ec. Yon and Vges With Respect to Van -0.3V to + 20V
Fower Dissipation ....11 112120100110 00 111440 1,5W
| "COMMENT: Stresses above those listed under Absolute Maxi-
| mum Ratings” may cause permanent damage to the device.
| This is a stress rating only and functional operation of the de-
- vice at these or any other conditions above those indicated in
the operations! sections of this specification is not impiied, Ex-
posure to absolute maximum rating conditions for extended
periods may affect device reliability.
D.C. CHARACTERISTICS
Ta = 0 to 70'C, Yopg 7 +12Y + 5%, Veg = +5V + 5%, Ygg 5 -5Y = 5%, Veg = OV, Unless Otherwise Noted.
Symbol Parameter Min. Typ. © Max, nit Test Condition
Мис Clock Input Low Voltage Veg —1 Vss+08 | Y
Y HC Clock Input High Voltage 9.0 ° Упор +1 \
VIL Input Low Voltage Weg =1 | | gg t0.8 Y
Vin input High Voltage 33 | Vce+1 Y
VOL Output Low Voltage | 0.45 Vv lo = 1.8mA on all outputs,
Vou Output High Voltage 3.7 Vv lon = 150uA.
loo tavi , Ava. Power Supply Current {Vol 40 #0 - mA |
| : Avg. Power Supply Current Мос! 60 80 ma | Operation
CCÍAVI - EL Toy = .3Busec
lgB lav Avg. Power Supply Current ‘ap! 01 1 Ma ,
fie Input Leakage +10 - uA Vee € Vin € Vro
leu Clock Leakage +10 HA Vee £ YcLock € Yon
lg 121 Data Bus Leakage in Input Mode | 100 ЦА Yes = Vin = Veg +0.8Y
20 MA +0.BVS Vin SVer
; aa À |
| Address and Data Bus Leakage | +10 | A VADOR:DATA = Ycs
L ; ; Ll
Curing HOLD i -100 | “ADOR/DATA 5 Yes + 0.45 Y
CAPACITANCE TYPICAL SUPPLY CURRENT М5,
T,=25°C Veo = Vpp = Vas = ОМ. Ува = -5V TEMPERATURE, NORMALIZED. [3]
Symbol Parameter Тур. Мах. Unit Test Condition E
=
Ca Clock Capacitance 17 25 pf fo = 1 MHz 5
! =
Cin 1 Input Capacitance 6 : 10 pf Unmeasured Pins >
: - E
Cour | Output Capacitance | 10 20 pf Returned to Vag 2
i
NOTES: ;
1. Tha RESET signal must be active for 3 minimum of 3 clock cycles. " "e +75 -50 +75
2. When DBIN is high and Yi > Vi y an internal active pull up will .
ba switched onto the Data Bus, AMBIENT TEMPERATURE rt
3. álsupply / ATA = -0.45%C
DATA BUS CHARACTERISTIC
CURING DBIN
MAR — — — — —
gu
"5 Vic
y
5-25
SILICON GATE MOS 8080A-2
A.C. CHARACTERISTICS
Ta = 0°Cto 70°C, Vpp = ~12V + 5%, Veg = +5V £ 5%, Van = -5V £ 5%, Vgg = OV, Unless Otherwise Noted
Symbol | Parameter Min. | Max. | Unit | Test Condition
toy 31 Clock Period .38 1 2.0 | usec |
tr, t+ ! Clock Rise and Fall Time ı © 50 | nsec |
Tay “6, Pulse Width . 60 | nsec
152 6 Pulse Width 175 nsec
11 Delay 91 10.64 0 nsec
tos Delay 09 to da | 70 | | nsec
tos Delay 6 ta © Leading Edges 7 “nsec |
tpa 121 Address Output Delay Егот фо 175 | nsec
inp 2: Data Output Delay From de | | 200 | nsec Ш GL 7 1008!
tocl2l Signal Output Delay From #4, or 05 SYNC, WA.WA1T, HLDA] 120 | nsec
‘ОЕ 12: |! DBIN Delay From д) 25 140 | nsec person
tpl] | Delay for Input Bus to Enter Input Mode tor | nsec
1051 Data Setup Time During dy and OBIN 20 | nsec
TIMING WAVEFORMS *'“
{Mote: Timing measurements are made at the following reference voltages: CLOCK "17 = 8.0V
0 = 10 INPUTS 1 = 3.34, 70 = dav: QUTPUTS 17 = 2.00, "0" = 08V.)
Icy — — ariel itp y —
ema . |
: A A AS A A
=‘ —| nz I=
—— L i Ve
x | —
Aug Bg —— — от! нае кн ное же ое —— — —. = — — — — = — — — == —
—+ na += fe —-. — Taw —— _ =
== tap —| — Im я —* ‘ан |=— = bpp 1
xX a j DATA CUT
ВВ, EE EE EE EE sl —— prt 7 — er —— ae — — — —' —
— 151 — - * Toy + — e
1 , !
SYNC A ED“ —-"n52—+ | i
—_— toc || —| toc -— :
DEIN | Л A ВЕ
I im Epp em
wr Ls
og |
EE EEE EE CEE ОЛЕНЬ се сн а — AS E = Ч
WAIT вое! 7 \
HLDA
INT DEY = г
N ¡
"ny EE |
INTE
5-26
SILICON GATE MOS 8080A-2
A.C. CHARACTERISTICS (Continued)
Ta = 0°C to 70°C, Vpp = +12V + 5%, Ver = +5V + 5%, Vag = -5Y + 5%, Veg = OV, Unless Otherwise Noted
Symbol Parameter Min. | Max. | Unit Test Condition
1052 Data Setup Time to 64 During DEIN 130 nsec
toy [1] * Data Hold Time From ¢5 During DBIN (1] nsec
tigl2l INTE Sutput Delay From de | 200 | nsec CL = B0pf
ÎRS READY Setup Time During ça 0 |! nsec
IHS HOLD Setup Time to 69 120 | nsec
tis INT Setup Time During $9 (During dy in Hart Model 100 nsec
tH ; Hold Time From pa READY, INT, HOLD! О п чес
ten Delay to Float During Hole {Address and Data Bus! | 120 | nsec
tawl2] | Address Stable Prior to WR [5] | nsec | |
tow 2! | Output Data Stable Prior to WR i [8] sec
twpl2! | Output Data Stable From WR [71 nsec
wall?! | Address Stable From WR om nsec CL =100pf: Address, Data
CL=50pf: WA, HLDA, CBIN
‘НЕ (2! HLDA to Float Delay (8] nsec
twe (21 | WR to Float Delay [9] nsec
tag 12) | Address Hold Time After DEIN During HLDA -20 [nsec | |
NOTES:
1 Cata input shoud be ecableg woh OBIN wares. No bus contict ea than accor sad Jans bald ome 15 atbur ed
"SH = SO nrar ipgr. »Aicheyer 15 less.
A A 7 Losd Circuit
+5
; : 2.1K
/ \ / \ B0BOA , . К .
OUTPUT LL с 5 |
| Le um TI © 150.
9 ror —]l — ai - ——
aT 3. Y " TO4 + TraZ * 162 + Hat + tb2 ttre) > 280M -
XII Ta TYPICAL A OUTPUT DELAY V5 a CAPACITANCE
n Pt с у - +2 ———— TT sre
E — afm y E 7 |
| Е
© a" го
! — HA ay = :
a
No |! =
— | — не |
| = |
| || 3 0 | } À
mo F © |
— bar "E, — ;
e toc - 10H 50 a +50 + 1
——
> 1 CAPACITANCE [pti
a Gp —— 'Cactuar - Cgrec*
iT
—— 4. Tha lollowiog are relevant when interfacing the ÉCEDA to devices having Y ¡y = 1.3%:
— | ab Maximum output rw time from 8 ro 1.3 = 100ny @ | = SPEC,
0 | bl Qutput delay when measured 10 3.0% = SPEC +80n1 @ Cy = SPEC.
Jen ; ch 11 Cy + SPEC add GrypF it 0, > CSPEC, Mubrrace Ini/pF Hrom modified dejey) if Cp = Casper,
—j ‘ос | 5 Ay Zw -1D7 “tra? -130nmme
A = 5. (Ou 7 1CY -1Q3 <1re2 - T0nsec.
fo | À 7oleot HLDA, tp wa = tog * Trap * One. IFEDA, ho > wa" TwE.
B. tHF 193 + Teg7 «SO,
— 9. t =
IT - gE = to t+ traz -1Cns
Foam 10. Data an must be srabie for this period during OBIN “T+, Bath tpgy and tgs Rust ba satisfied.
11. Ready signal must ba table tor this period during Ty ce Tuy. {Must be externally synchronized. |
Ja Le | 12. Hold signal must be table for this period during Ta or Ty; whan entering hold mode, snd during T3, T4, T5
"e _ año Ty whan in hold mode, LExtar na ey nehronizatión xi nót cguired.)
13. Inerrupt ngnal must ba stable during this period of 1he fant clock cycle of any instruction in order to be
== recognized on the lolloweng inatructon. (External synchronization is nor regained.
14, Thit timing diagram shows timing relationshios only; it dos not represent any mpecil machine cycie.
—
5-27
intel Silicon Gate MOS M8080A
SINGLE CHIP 8-BIT N-CHANNEL MICROPROCESSOR
The MBOBNA is functionally compatible with the Intel” 8080
= Full Military Temperature Range a Sixteen Bit Stack Pointer and Stack
— 55°C to +125°C Manipulation Instructions for Rapid
» +10% Power Supply Tolerance Switching of the Program Environment
в 2451 ti le * Decimal Binary and Double
us Instruction Cyc Precision Arithmetic
* Powerful Problem Solving o
Instruction Set " Ability to Provide Priority Vectored
Int
* Six General Purpose Registers N errupts
and an Accumulator « 512 Directly Addressed 1/O Ports
= Sixteen Bit Program Counter for a TTL Drive Capability
Directiy Addressing up to 64K Bytes
of Memory
The Intel® MBOBOA is a complete 8-bit parallel central processing unit (CPU]. lt is fabricated on a single LS! chip using Intel's
n-channel silicon gate MOS process. This offers the user a high performance solution to contrel and processing applications.
The M80804 contains six 8-bit general purpose wo rking registers and an accumulator. The six general purpose registers may Бе
addressed individually or in pairs providing both single ang double precision operators, Arithmetic and logical instructions set
or reset four testable flags, A fifth flag provides decimal arithmetic operation.
The MSOSDA has ar external stack feature wherein amy portion of memory may be used as a last in/first out stack to store/
retrieve the contents of the accumulator, flags, program counter and all of the six general purpose registers. The sixteen bit
stack pointer controls the addressing of this external stack. This stack gives the M8080A the ability to easily handle multiple
level priority interrupts by rapidly storing and restoring processor status. It alsa provides almost unlimited ‘subroutine nesting.
This microprocessor has been designed to simplify systems design. Separate 16-line address and 8-line bi-directional data
busses are used to facilitate easy interface to memory and HO, Signals to control the interface to memory and 1/0 are pra:
vided directly by the MBOSO0A. Ultimate control of the address and data busses resides with the HOLD signal, |t provides the
ability to suspend processor aperation and force the address and data busses into a high impedance state. This permits OR-
tying these busses with other controlling devices for {DMA} direct Memory access of multi-processor operation.
—.- ..: M90804 CPU PUNCHONAL - E ideo ona
en BLOCK DIAGRAM = ‚ E IA AAA DA - NIP A -
TN RT Ba TE В ns | т ; U
Уна : Al ile FE Cif Cara aus = si ART
E SAA Че KO KO ii Ea NA
- > Like aer : ik HT) * Vie . eo - _ a Bn: . ais
a a. INTERNAL DATES BU | INTERNAL DATA BUS ай
eh pe emia Eg 1 ле A ho . E. " Ня :
E = - ato :
xa AP pai BE 2. „ЧЁ ; Зы If . cher,
D ES “A BLA 2 За tr A ‚5 : adas : ыы . : ‚об Te
АУ) 2 | eT EA EE | 5 . FT
Dei > ne. eg "E es . gd! Cd > To В Tr . . E .
; “ui [AceumuLaTo] TEMP REG 2, Е | INSTRUCTION — 5 E,
UR: A | ml ДЕ U ~ | REGISTER ор. E AU, TIPLEXER Ee
EA ip FLAG Jr | A TEMP REY; TEMP AFG ELLE
: fa FLIP FLLPS Ll e CR
‚Зо ACCUMULATOR a x 1 я я С A Eee
LATCH & Зы REG REG AP
dm IT 4 INSTRUCTION За о EE ea
E DECODER я ALL REG ahi
AND = fa : + DET,
MACHINE a E H 3 L a |__AEGHSTER
CYCLE E HEL; REG ARRAY...
} о.
ENCODING o A o
i cle STACK POINTER | PANEL
: REE
ES E "E REA
E СВ PROGA LW COUNTER ; САРАЙ
WR e ES Li
| RA ME AE EN INCREMENTER DECREMENTER MIT
raid E E AODRÉSS LATCH "E TE
ra E id Am —
VE i RE NES x
_ TIMING SER
al AND EEN IO > 10 RE TAI
CONTROL ga 5
Ta "A
das AODRESS BUFFER |
CATA BLS INTERRUPT HOLD WalT HE к: 50
WRITE CONTAQU CONTROL CONTRAL CONTROL o ay
ét dt Ja G 3 fi
к TE a vo - o , “3 '
: A
dies
SILICON GATE MOS M8080A
INSTRUCTION SET
The accumulator group instructions include arithmetic and
logical operators with direct, indirect, and immediate ad-
dressing modes.
Move, load, and store instruction groups provide the ability
to move either B or 16 bits of data between memory, the
six working registers and the accumulator using direct, in-
direct, and immediate addressing modes.
The ability to branct to différent portions of the program
is provided with jump, jump conaitional, and computed
jumps. Also the ability to call to and return from sub-
routines is provided both conditionally and unconditionally.
The RESTART dor single byte call instruction) is useful for
interrupt vector operation.
Double precision operators such as stack manipulation and
double add instructions extend both the arithmetic and
interrupt handling capability of the MSOBDA. The ability to
Data and Instruction Formats
increment and decrement memory, the six general registers
and the accumulator 15 provided as well as extended incre-
ment and decrement instructions to operate on the register
pairs and stack pointer, Further capability is provided by
the ability to rotate the accumulator left or right through
or around the carry bit,
Input and output may be accomplished using memory ad-
dresses as 1/0 ports or the directly addressed 1/0 provided
for in the MBOB0A instruction set.
The following special instruction group completes the
МВОВОА instruction set: the NOP instruction, HALT to stop
processor execution and the DAA instructions provide deci
mal arithmetic capability. STC allows the carry flag to be di-
rectly set, and the CMC instruction allows it to be comple-
mented. CMA complements the contents of the accumulator
and XCHG exchanges the contents of two 16-bit register
pairs directly.
Data in the MBOBOA is stored in the form of 8-bit binary integers. All data transfers to the system datz bus will be in the
same format,
07 De Ds Da Di Oy Dy Dg
DATA WORD
The program instructions may be one, two, or three bytes in length. Multiple byte instructions must be stored
In successive words in program memory.
executed,
One Byte Instructions
07 Dg 05 04 D; 07 D; Dg | OP CODE
Two Byte Instructions
| Ds Dg Ds Da О) О» О) бо |} OP CODE
|D7 Dg Ds Dy D3 Dy Dy Dg | OPERAND
Three Byte Instructions
[Ds Dg Dg Dg D3 Dy Dy Dg | OP CODE
| 0, De Ds Dy D3 Do Dy Do |
| D; De Ds Dg D3 Dy Dy Dg |
LOW ADDRESS OR OPERANDA
The instruction formats then depend on the particular operation
TYPICAL INSTRUCTIONS
Register to register, memary refer.
enca, arithmetic or logical, rotate,
return, push, nop, enable or disable
Interrupt instructions
tmmediate made ar 170 instructions
Jump, cail or direct load and store
Instructions
HIGH ADDRESS OR OPERAND 2
For the MBOBOA a logic “17 is defined as a high level and a logic 07 is defined as a low level,
5-30
SILICON GATE MOS M8080A
INSTRUCTION SET
Summary of Processor Instructions
[struction Codeil. Clock = | Instruction Codal 1 Clack ©
Mermonic = Ceveripiion 0; Dg Og D4 Oy De Oy Op Coches Mpemanie Description В; O5 Og Dy E; В; 0, Oy Cycles
MOW.y 2 Mowe requrer 5g reg ome 1 1 0 0 0 5 5 5 RZ SElyrn ЭП гг TT 1 0 49 1 I 0 10 E;
MOM Mr Muve regisier 17 mp=o ey 01 11 0 5 5 5 Въ Яегуём ап пб ёето 1 9 0 9 C Q 51
MOV BM Mave memire reg ooze fo A A O 1 1 7 AF Serafin de fte ve 11 1 1 0 0 0 0 EU
HLT Hale ooo 1 1 0 1 Iq FM RETIN 50 mings 1 1 I 1 1 0 do ET
MAI 1 Mowe immediate regots: oof 9 9 M 1 1 € APE Séfgrn 50 parity Even 1 : 0 1 = C 0 Ea
Mi MM Mave immediate ne— ry Lo 1 1 I | ! > Réf era ua panty odd 1 | | 0 npn = D 1a ET!
ELE Increment ‘egierer 52 8.019020 25 1 708 EST uctar! | 1 A A 4 1 1 1 11
OCAr Clecremenr eegisrer o 2 oon n IN - pul | ! 0 1 1 E 1 1 "i
INR M INT лёг у Joo | 1 [1 J 1 OUT road 1 I 0 1 900 1 | Tr
OCA M Decremes| mein y о Гао! LXIE Ad Mmediare register 200 0 0 © coo | "E
ADO r Add regrsier to A E 2 5 5 5 Pur В & С
ADC Add register Fa A ow tt carry оО ы Ly C -184 mmediale register 1: 0 0 1 27 0 0! ©
SUR T Jubtract regesesr from 2 1 0 J ! 1 5 5 5 - Par DEE
SEA Subtraci regisres irn 4 1 0 0 1 5 5 5 + LENH 140 MMediarE register I 10 1 0 132 2 1 "=
win formée Pair H&L
АМА г And register wis A ro 1 an 5 5 5 + LX. EP сай тиф нате «гаек роке: ÑO OD 11 0 0 0 1 13
XFAr talamive Orregisjaer 4 1 A | À 1 0 1 5 5 5 : PUEHE Posh register Parr AS Coon 1 1 g a 0 1 0 1 НЫ
ОБА, O regrtjer w-1h A 1 QU 1 Tn 5% 5 5 - rack
CMPr Compare register mo1* à POB SAS - PUSH 2 2046 register Parr O & Е оп 11 € 1 0 1 0 1 ЫЕ
ADD M Add memory má . | 7 O 0 a0 1 ID - Мася,
AOC M Add memory 10 6 оу 1 тату ао т to FLGH H Muze register Barr HB Eon 1 1 1 1 10 1 0 1 1
SUR M Subtract mverars leo” à I a 4 IG | Stack
SEAM Subtract memory 17 à BRAD PLUSH PS Puin A and Flags 1.1 | ES O 1 0 1 1
with Про РГО 1 41ALk
АМА М ANZ memory wil” A Po оао PORE Pap oegister pair B & C nll 1 1 OD 0 O do oa 11]
ХНА М Еч сони Ог тв сг, & 1 а 1 À 1 4 = 1 1 10 ack
QRA M Or memory wh 5 1 ma 1 2° 1 1 Ô POP Pop register pair O & Е и! 1 1 1 1 a 9 g 1 10
СМР М Compara eemory xr A " 0 1 RIO : Trach
ADI Add immédiate to À 1.1 0 a 07 1 Ia | POR H Po register gd НО & | ой | | 1 D u go Cd I
ACI Add чит HE IA 5 té I O 2 1 1 1 ; stack
Carry РОР Л, #45 À and Flags . 1 1 1 & 4 9 I "5
SLI Sub m men alter A 1] n 1 0 1 1 i ' A
5El Subiraci Meat! — A 1] n 1 1 1 1 x : STA Tire A direct do 1 T a E "i
wiih bore ow «РА „там А Инег1 1°5 1 1 17 : 1 0 ‘I
AMI And immediate w 17 À 1 1 1 0 0 101 LHI Sachange D&E HEL О! 1 1 7 1 0! A
XR Exclusive Or mmez.ats woth 1.1 1 A 1 1 - ; SEE
A ATH: Exchange top Hi ласк Н & | "101 € 9 70 101 13
OAI Ce mmediate sal” 4 1 1 1 1 ûÙ 1 1 7 ' LAW| = & L ra slacw gointer 1 0 1 1 1 2 I 1 5
CPI Compare immeg-318 Arn & | 1 1 1°1 1 1 TT PERL = KL 13 program courier to 1 0 J 23 * 4
ALE Rorate A afr соо оо 1 1 1 : DALE 214 ACISHAL 1 0 0 a - 901 1:
ARC Rotate A right 92 0 0 4 1 1 1 1 - DAZ LC 539 ОЖ Его НА 1: 0 0 1 Ion 1%
Ral Hatate A elt trough carey зо от | - OAT H a: & LS Hal à 0 1 0 1 10 ù j 10
RAR Aoiate Aeght 1kro og" за о ттт : Dal SP Ааа lace porter to H & L 20 1 1 + 3% 9"! 1
carry ETAGE беге Апофис! d d 0 à 0 0 1 9 E
JME Jump uncondiluna | Co 0 0 C I ! "i {TANT 3 ru À migirec1 о 0 0 | 0 = " ù
JC Jump an carry 1.1 0 11 8 17 ë | LOAx3 Load Andie DO O O TA TD
JNE Jump an na carry Toy 9° 1 6 0 9 CE LUAX 7 Lad Aocidireci D O A 1 1 0 1 0
Jê Jump an zero "1 9 6 1 0 93 1 1 INXE icemenr 86 Cregitrers ооо ево тя E
JNZ Jump gn ra rea сосет © i INX D lac-emént D E E registers поп +» 0 00101 5
JP JuMp ya pesirve . 5 | «9 u 17 я | INE = «“:rement H & L register; nn 1 a ni 7 1 1 E
JM Jump on mint 11 1 Пат il | INE LF ‘nprement stack pointer 0 a 1 1 0 oo 1 1 3
IPE Jump an parity eve” To 1 9 1 9 1 Q 2 | Dex à Decrement B à € ooo & 9 1 9 1 1 5
IPQ Jump an party une 1 E °C ; pox Decrément CG à E nog e : 1 © 1 1 3
CALL Call uncond: Horal 1.1 0 9 3 1 001 1? ocx H Decrement H & L Dd + 9°1 00101 5
Lc Call on carcy 1.1 0 | Шо 1 OLX Sr Jecrement stack pointer о 1 1 1 0 1 1 $
ENT Сай on no Larry 1 1 0 A Y 0 0 1 CMA Comglement A on 1 0 1 1 1 1 :
CZ Canon raro 11 BB Y 1 NU 2 1 STE Ser carry a a + 1 0 1 1 1 4
Chi Call an ra ero 1 1 ûi 9 9 1" 0 0 11: CML complement carry [1 0 | T 1 1 1 I 4
CP Call on positive 1.1 Тот 1117 DAA Decimal adjust A O od + 0 a 1 1 1 4
CM Call an minus 11 1 1 1 1 0 0 1107 SALI Sidre MB L direct a 0 1 0 d то 16
LPE Call an panty even 1.1 O 1 0 00 1117 LHLD Lcd HAB direct оо гот то 16
СРО Call an parity odd 1 1 1 oo 1 0 Ù nis El E"able hnterruprs Fo] 1 1. 1 0 101 4
RET Return 11 0 0 1 0 a 1 19 BE D:sabie interrupt тя O O 4
AC Return pn carry 1 1 6 1 1 0 OE El МОР ча-ореганол по dx 0 0 0 0 7 à
ANC Return pn np carry Food a 1 0 9 6 7 5 11
NOTES:
1. QUD or 555 — V00 B — 001 С - 0190 — 011 E — 106 H - 161 L — 110 emorv — 111 À
2. Two possible cycle times, 18/11} indicate instruction cycles dependent on condition flags,
5-31
SILICON GATE MOS M8080A
MBOSDA FUNCTIONAL PIN DEFINITION
The following describes the function of all of the MB8080A 1/0
pins. Several of the descriptions refer to internal timing periods.
Aq. Ap [output three-state!
ADDRESS BUS; the address bus provides the address to memory
tup to 64K B-bit wordsl or denotes the 1/0 device numner for up
to 256 input and 258 output devices. Ap is the least significant
address bit.
Dy-Gy linput/output three-state)
DATA BUS: the data bus provides bi-directional communication
netween the CPU, memory, and 1/0 devices for instructions and
data transfers. Also, during the first clock cycle of each machine
cycle, the M&8080A outputs a status word on the data bus that de-
scribes the current machine cycle. Dj is the least significant bit.
SYNC loutput)
SYNCHRONIZING SIGNAL: the SYNC pin provides à signal to
indicate the beginning of each machine cycle.
DEIN (output!
DATA BUS IN; the DBIN signal indicates to external circuits that
the data bus is in the input mode. This signal should be used to
enable the gatingof data onto the MBOBOA data bus from memory
or 1/0,
READY (input)
READY; the READY signal indicates to the MBOB0A that valid
memory of input data is available on the MBOBDA data bus. This
signal is used to synchronize the CPU with slawer memory or l/O
devices. If after sending an address out the MBO80A does not re-
ceive a READY input, the MBOB0A will enter a WAIT state for as
long as the READY line is low, READY can also be used to single
step the CPU,
WAIT (output)
WAIT; the WAIT signal acknowledges that the CPU is ina WAIT
state.
WR (output)
WRITE; the WR signal is used for memory WRITE or 1/0 output
control. The data on the data bus is stable while the WH signal is
active low (WH = D,
HOLD (input)
HOLD: the HOLD signal requests the CPU to enter the HOLD
state, The HOLD state allows an external device to gain control
of the MEDS0A address and data bus as soon as the MBO080A has
completed its use of these buses for the current machine cycle. It
is recognized under the following conditions:
“ the CPU isin the HALT state.
# the CPU isin the T2 or TW state and the READY signal 15 active.
As a result of entering the HOLD state the CPU ADDRESS BUS
(A15-Agl and DATA BUS {D;-Dgl will be in their high impedance
state. The CPU acknowledges its state with the HOLD AC
KNOWLEDGE (HLBA} pin,
HLOA loutput!
HOLD ACENOYWLEDGE:; the HLDA signal appears in response
to the HG LD signal and indicates that the data and address bus
p—— ro —
| Ay $C" 40 p—0 Ara
: GND © 2 38 О Аза
* D, O+—1 3 38 — 0 513
О, Oma 4 37 |—0 Ay
| о, ©] 5 36 [--——0 As
| D, Ge 6 35 — 0 Ag
D, ож 7 . 34 p—=0 Ap
MOT INTEL *—es |
p, 0=+—— 19 | Ag
D, O 10 M8OBOA 31 FCO Ar
_5y O-—— 11 30 О А,
О НЕЗЕТ О— 12 29 |-—.0 A;
| HOLO O-—— 13 28 F—o +12v
INT 0—} 14 27 p—=0 A,
“7 Qe 15 26 9—0 А
INTÉ G+——— 16 25 О А, |
DEIN 0+— 17 24 |—.0 WAIT |
WR O=—=—] 18 23 pr) READY
SYNC Cr 10 22 Pr--0 2,
+54y O— 20 21 F—=0 HLDA
|
Pin Configuration
will go to the high impeaz~ce state. The HLDÁ signal begins at:
& T3 for READ memory ar input.
® The Clock Period folla. ng T3 for \VRITE memory or QUT-
FUT operation.
In either case, the HLDÁ sonal appears after the rising edge of (1
and high impedance occurs after the rising edge of de.
INTE (output)
INTERRUPT ENABLE, ~c:cates the content of the internal inter
rupt enable flip/flop, This flip/flop may be set or reset by the En
able and Disable Interrugt instructions and inhibits interrupts
from being accepted by the CPU when it 15 reset. It is auto
matically reset {disabling ‘urther interrupts) at time T1 of the in
struction fetch cycle (31 when an interrupt is accepted and в
also reset by the RESET signal.
iNT finput!
INTERRUPT REQUEST; the CPU recognizes an interrupt re
guest on this line at the end of the current instruction or while
halted. |f the CPU isin tra HOLD state or if the interrupt Enable
flip/flop 1s reset it will not honor the request.
RESET (input)?
RESET; while the RESET signal 15 activated, the content of the
program counter is cleared. After RESET, the program will star!
at location 0 in memory. The INTE and HLDA flip/fiops are alsí
reset, Mote that the flags. accumulator, stack pointer, and register
are not cleared.
Yes — Ground Reference
Yoo +12 Volts 210%.
Vee +5 Volts £10%.
Vee -5 Volts 410%,
Ф1. 92 2 externally supplied clock phases. (nan TTL compatible
——
5-32
SILICON GATE MOS M8080A
ABSOLUTE MAXIMUM RATINGS"
-55°С то +125°С
-65°C to +150°C
Temperature Under Bias |
Storage Temperature .... .. . .... ..
All Input ar Dutput Voltages
With Respect to Ygg . . ............ -0.3V to +20V
Vee, Мор aod Ves With Respect to Van -0.3V to +20V
Power Dissipation . . 1.7W
"COMMENT: Stresses abave those listed under "Absolute Maxi-
mum Ratings” may cause permanent damage to the device.
This is a stress rating onfv and functional operation of the de
vice at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Ex-
periods may affect device reliability.
D.C. CHARACTERISTICS
Та = -55°С 10 +125°С, Урр = +12\ 410%, Усс = +5V 210%, Vgg =-5V £10%, Vos = OV, Unless Otherwise Noted.
Symbol Parameter Min. Typ. Max. Unit Tast Condition
Vie Ciock Ingut Low Voltage Vas —1 Vec+08 \
VIHC Clack Input High Voltage 8.5 Voo+1| Y
vin Input Low Voltage Vee —1 Vas 10.8 | \
Vis Input High Voltage 3.0 Vee +1 \
Vou Output Low Voltage 0.45 Y _|LloL = 1.9MA on all outputs,
Von Outpur High Voltage 3.7 V 'OH = I50LA.
Ino tavi | Avg. Power Supply Current (Yo! 5 80 | ma |
"| Operation
lcctav; 1 Avg. Power Supply Current [Vcc]! 60 100 ' mA !+
+ Tow = 48 psec
'МИв (ду) Avg Power Supply Current {Vgg! 01 1 MA
mn Input Leakzge +10 | 4A Vss = Vin =< Усс
to Clock Leakage £10 HA | Ves € Verock € Ypo
Fey, 121] Data Bus Leakage in Input Mode -100 НА 1 Yes Vin E Ves +08
0 | MA | Ves 0.8V<VN Ve
Address and Data Bus Leakage +10 VaDDR/DATA = Veo
FL During HOLD -100 нА
3 . | VADDA/DATA 7 Vss + 0.45V
1 ]
CAPACITANCE TYPICAL SUPPLY CURRENT VS.
T, =25°C Vce = Von = Vgg = OV, Vgg =-5V TEMPERATURE, NORMALIZED, [3]
1.5
Symbol Parameter Typ. Max. Unit Test Condition = в <
x
Ca Clock Capacitance 17 25 р? fe = 1 MHz x + в
Cin Input Capacitance | 6 10 pf Unmeasured Pins ; Da
Court Qutput Capacitance i 10 20 pf Returned to Vg E A
NOTES:
1.
2.
The AESET signal must be active for a minimum of 3 clock cycles
When DBIN is high ano YEN Wi | an internal active pull up will
be switched onto the Dara Bus,
3. Al supply ? ATA =-0 45%" C
+80 +125
AMBIENT TEMPERATURE {1 С]
DATA BUS CHARACTERISTIC
DURING DBIN
МАХ
Гол,
ci
>43
posure to absolute maximum rating conditions for extended
SILICON GATE MOS M8080A
A.C. CHARACTERISTICS
Ta = -55°C to +125°C, Von = +12V +10%, Vec = +5V +10%, Vag = -5V +10%, Мое = OV, Unless Otherwise Noted.
1
Min. | Мах.
Symbol : Parameter Unit Test Condition
toyl3H | Clock Period 0.48 | 2.0 | usec
tr, U Clock Rise and Fall Time 0 50 | nsec
tol #1 Pulse Width 60 | nsec
tez 5) Pulse Width 220 NSEC
‘01 | Delay 6, to 095 0 nsec
too Delay 55 to de 80 nsec
103 | Delay CG to © Leadıng Edges 80 ner
tpa (2! | Address Output Delay Fram 22 200 | nsec
top [2 | Data Output Delay From og 220 | nsec
toc?) | Signal Output Delay From 67, or 09 SYNC, WEWAIT, HLDA) 1 140 | nsec
toe [2] | DEIN Delay From gy | 25 1 150 | nsec CL. = OP
tpl! ; Delay for Input Bus to Enter Input Mode top | nsec
1051 Data Setup Time Durning ¢ and OBIN | 30 | nsec
TIMING WAVEFORMS
[14]
|
| ı
o
| 17 +-
FUN A
A
—* +
/
G.8V; QUTPUTS "1° =
(Note: Timing measurements are made at the following reference voitages: CLOCK 1 = 7.0Y,
“O = 1,0: INFUTS “17 = 3.0V, 0 =
UV, "0° =08V.1
— — —
=
L
ad
Ag By : = —— o a EE EEE EE ee me жен == — — Hr ry
= Toa — TT Taw ee
! il
[= fon — + MO - "paf Ap !
|= == == -. = E Li mi
— CATA 1 1, DATA OUT
ВР, = на — к РНР ЛИНЬ EES or — EE fle i: -----———!
—— Iggy = — м - ‘руд — 1
SYNC \ - Tp Pa :‘ : _
7 1. 57 In ;
—l toc == = pg =-— i |
CAIN i \ | |
‘о la tng || " —
|
T
WH |
pt ==
i бр соо
; ! |
. 7 r
ey TT ST ET
яз | sia foc ew 1
WANT 144 — | la À \ |
Тс —= | — "y т -
| —l
| tas l=—
HLDA
INT 13
Ty
ty me =
m]
INTE
д
6-34
SILICON GATE MOS M8080A
A.C. CHARACTERISTICS {Continued}
Тд = -55°С 10 +125°С, Мор = +12\ +10%, Мос = +5\ 110%, Vgg = -5V £10%, Vgg = OV,
Unless Otherwisa Noted.
2. Load Carey.
= +
T
a F \ j \ $ 2K
2
НОВО |”,
| buteur | с Ты —
—| to — Lt 150. 4 :
YT Tm - 5
hy Je — —]o— al ! A ma - =
[=i Twa, 1 CY = 1034 trez + 197 + Mez * 102 + tray 2 ВОт. -
! Y Ei TYPICAL 5 QUTPUT DELAY VS. 4 CAPACITANCE
By ке a +20
| Ло E
rec = +"
| и
J =
kk
— LP tan a
НН E
E / a
—
в | g -w
| : a
MA
SS — Ly p=] 70
= ly - 100
—.
AD Y L CAPACITANCE тр!)
ha las —= Cacruar Taree’
AI
je 4. Tha following are relevant when interfecing the MBOBOA 10 devices having Y y = 3.3
= 2) Maximum output rise hme (rom BV to 3.3% = 1000s & Cp = SPEC
OLE : bl Quipul delay when massured 10 3.0V = SPEC +BQny ® C= SPEC.
— ‘| el 1 CL + SPEC, add &nv/pF of CL» Cgpeg, subiract 3ns/pF rom modified delay и! C, ESPEC
— toc |-=— 5 lav = 7 ey 104 -tra? = 1400,
LOA | E OWTICY -1D3 -1rpz -t7Orsec
фон. / ТОЙ пни! НОСА. wo "ta 103 7 tray “08: IF ALCA, tuo = was = we
! В. tHE = 103 + 1,57 -5Ont.
— 9 = + >10
INT . WE DS + Trgz Tung
о | 10. Data in must be viable (or thi penod during DEIN Ty. Both toga ang eyed Must ore arista.
11. Paady носа! ый be stable for thes pariod during To or Ti. (Mutt Be externally sync=-am zed. }
== Lg —el 14. Motd signat muit ba stable for this period during Ta or Tyy when entering hold mode and during T3. T4. Ta
_ and TWwy when in hold mode. {External ynchronizanon ob not regulred.|
NTE X 13, Intercupt ола! плит! Бе сибе during this parod 0 tha last cloce evcia ol AMY iNStucicr an arder la he
== recograzad ón ihe tollgwaing mitruchón. External sy РН а НО бе О
14. This trming diagram shows Liming relationship only: if dons no represent ¿ny SOCIE Machine EEE
a
Symbol Parameter Min. | Max. | Unit Test Condition
tos? — | Data Setup Time to 63 During DBÍN 130 nsec ;
ton! | Data Hold Time From dy During DEIN 50 nsec |
ТЕ 121 INTE Output Delay From Фо | 200 | nsec Cy = 50pf
‘Rg READY Setup Time During e 120 nsec
tus HOLD Setup Time to da 140 nsec
tig INT Setup Time During 95 (Guring oy in Halt Mode) 120 M sec
TH | Hold Time From ¢4 (READY, INT, HOLD! 0 nsec
teo Delay to Firat Curing Hold {Address and Data Bus) 130 | nsec
tawl21 | Address Stable Prior to WR [5] nsec | 7
tow!2l | Output Data Stable Prior to WR 16 nsec
two 2) | Output Data Stable From WR (7] nsec
twal?l | Address Stable From WR [7] nsec | Cp =50pf
1нЕ (2! HLDA to Float Delay [8] nsec
twe 21 | WR to Float Delay [9] nsec |
tay 121 | Address Hold Time After DBIN During HLOA -20 nsec | |
NOTES:
1. Darganput Móvuid ba tnabled with DEIN status.
ICH = S0mor gE. whichever 1 legs,
Ма bus conf hed can {hen coco and dats raid dime 15 assured.
5-35
, Ko e >
NN à
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ROMS
8702A 8302
8704 8308
8708 8316A
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Silicon Gate MOS 8702A
intel
2048 BIT ERASABLE AND ELECTRICALLY
REPROGRAMMABLE READ ONLY MEMORY
« Access Time — 1.3 usec " Inputs and Outputs TTL Compatible
Max. " Three-State Output — OR-Tie
= Fast Programming — 2 Minutes for Capabitity
All 2048 Bits an » Simple Memory Expansion Chip
a Fully Decoded, 256 x 8 Organization Select Input Lead
E
Static MOS — No Clocks Required
The 87024 is a 256 word by 8 bit electrically programmabie ROM ideally suited for Microcomputer system
development where fast turn-around and pattern experimentation are important. The 87024 undergoes
complete programming and functionel testing on each bit position prior to shipment, thus insuring 100%
programmability,
TheB702A is packaged in a 24 pin dual-in line package with a transparent quartz lid. The transparent quartz
lid allows the user to expose the chip to ultraviolet light 10 erase the bit pattern. A new pattern can then be
written into the device. This procedure can be repeated as many times as required.
The circuitry of the 8702A is entirely static: no clocks are required.
A pin-for-pin metal mask programmed ROM, the Intel 8302, is ideal for large volume production runs of
systems initially using the 8702A.
The 8702A is fabricated with silicon gate technology. This low threshold technology allows the design and
production of higher performance MOS circuits and provides a higher functional density on 8 monolithic
chip than conventional MOS technologies.
PIN CONFIGURATION BLOCK DIAGRAM
DATAOUT1 — DATAQUTE
a |: ~ га Г ]Упо |
w]e 23[ Vee
OUTPUT
NE 22 [ ]Yec 5 — BUFFERS
*DATA QUT 1[_|4 :LsB) 21 A; |
“DATA DUT 20 |5 2a] Aq 2048 BIT
PROGRAM — | PROM MATRIX
*oaTa out 3[ Je 19] | Ag 1258 X El
8702A
“DATA OUT 4 [7|7 18] 4s |
"DATA OUT S[ Ya "La DÉCOOER
*Data QUT ef ds 8] es
‘DATA GUT 7 16 15 v
Г ve INPUT
*DATA OUT 8[_] 11 :Msa) af Es DRIVERS
vee L [17 11) JEROGRAM Î | ————— !
О _ AA, я
“THIS PIN 15 THE DATA INPUT LEAD DURING PROGRAMMING.
PIN NAMES
AyA7 ADDRESS INPUTS
CHIP SELECT INPUT
DO, - DO; DATA QUTPUTS
—
SILICON GATE MOS 8702A
PIN CONNECTIONS
The external lead connections to the B702A differ, depending on whether the device is being programmed 1! or used in read
mode. (See following table.)
TT las | 15 16 | 22 23
— PIN 12 13 14
MODE us Wee ] | (Program {CS} (Vay ] i Wag } ! Wee ] (Мес i
Read Vee Veco (GND Мес, “бб Усс | Усс
Programming GND | Program Pulse | GND : Yap | Pulsed Мас Y Lap) GND | GND
ABSOLUTE MAXIMUM RATINGS”
Ambient Temperature Under Bias OC to +70%C ‘COMMENT
Storage Temperature —65°С to +125°C
Soldering Temperature of Leads {10sec} . ....... +300°C
Power Dissipation . ............. ......... 2 Warts
Read Operation: Input Voltages and Supply
Voltages with respect to Vee 2... 2... +0.5V то —20V
Program Operation: Input Voltages and Supply
Voltages with respect to Vee 2121221010 11e 040 —48V
Ctresses above those listed under “Absolute Maximum Rat
ings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at
these or at any other condition above those indicated in
the operational sections of this specification is not implied,
Exposure to Absolute Maximum Rating conditions for ex-
tended periods may affect device reliabidity,
READ OPERATION
D.C. AND OPERATING CHARACTERISTICS
Ta = 0% to 70%, Veo = +5V+5%, Vo = -9VE5%, VÍA = —9V+5%,
unless otherwise noted,
SYMBOL TEST | MIN. ТУР!) MAX. | UNIT CONDITIONS
№ Address and Chip Select 10 pA Mi 7 00V
Input Load Currant _
Lo | Output Leakage Current 10 ГНА ! Vour 7 0.0V,CS = Ver 2
lono Power Supply Current 5 10 | ma | Уса “Усс. CS-Vec—2
_ | lo = 0.0mA. T,=25 с
logs | Power Supply Current 35 50 0j mA | C5=Vcc -2
- hot =. Oma, Ta = 25°C
Inne Power Supply Current 32 46 MA CS-0.0
lo =0.0mA, Ta = 25°C
| я = ; За Е — Continuous
DD3 ower Supply Current 50 mA C5=V- 2 Operation
ha TO.0MÁ . Ta = OC
leg, ; Output Clamp Current a 14 má Y UT = — 1.0, T, = OC
lero Output Clamp Current 13 má Vout = —1.0V. T, = 25°C
|: Gate Supply Current 10 нА
М Input Low Voltage for —1.0 0.65 Y
TTL Interface В _
ML? Input Low Voltage for Yon Yec -—5 \
MOS Interface
Y Address and Chip Select Vec-2 Ver 0.31 Y
Input High Voltage ;
lo | Qutpur Sink Current | 18 _ а mA ; Your 7 0.45
Y or Output Low voltage | 7 0.45 Y | 15, 7 1.6mA
Vey | Output High Voltage 35 LV I он = —200 uA
ote 1: In the programming mode, the dats mputs 1-8 are ping 4— 11 respectively, cs = GMD.
Note 2: Vg may be clocked to reduce power dissipation. in the mode average Ing increases in proportion to Vga duty cycle, See p. 5)
Note 3: Typical values are at nominal voltages and T 4 = 25°C,
5-38
SILICON GATE MOS 87024
A.C. CHARACTERISTICS
T, =0°C to +70°C, Veo
= +5V +5%, Van = —9V 25%, Var = —9V 15% unless otherwise noted
SYMBOL TEST MINIMUM | TYPICAL | MAXIMUM | UNIT
Freq. Repetition Rate 1 | MHz
‘он Previous read data valid 100 ns
ТАСС : Address to output delay a I 13 Lis
‘русс Clocked Мод setup 1.0 о Hs
tes Chip select delay | 400 ns
Teo Cutput delay from C5 900 rs
ton Output deselect ! ! 400 ns
tone | Data out hold in clocked Мод mode (Note 1) | 5 HS
Nom 1. The output will remain valid dor tH 5 long as clocked V5] is at Vee An address change may occur ak 3000 as the output ly sanyer
tclocked Yo; may +til be at Ycgl, Dats becomes Invalid for the old address when clocked Y G5 1 returned to Van,
CAPACITANCE* T, = 25%
SYMBOL TEST MINIMUM | TYPICAL | MAXIMUM "UNIT CONDITIONS
CN Input Capacitance 8 15 pF Vin = Усс | All
Cour Output Capacitance 10 15 BF GB Meg unused pins
Cree Von Capacitance x pr Your Yee are MAC
(Clocked Vi; Mode) | | | Ge ej Y
4 Thts parameter 15 periodically samplad and is not 100% tested.
SWITCHING CHARACTERISTICS
Conditions of Test:
Input pulse amplitudes: O to 4% tt. <50 06
Output load 15 1 TTL gate. measurements made
at output of TTL gate tor, = 15 msi
A) Constant Vo. Operation
— LE | =
Yin 104,
ADDRESS
Qi.
W
SATA OUT
Y ALIO
SESEL ETICA de Cata CIUTELT IN Qe TIRO SFE Pa
me} À
wi Te
ADDRESS X
y em
-L LE
Vin — =
cé
ss
LT
= ‘зу =
“сн т
NATA
our
Yo
— r =
5-39
Bl Clocked Vos Operation
— 1e UE FED —
М,
H Ti
ADCALES
aor.
Y
CLEKCAHEO
Yor
SEC NOTE 1!
vu
METE 2 — — 7 тя
vu FU — = =“ E ir =
cs ; 1
I
= I
= Le E Ga го. = -
Mir! !
CLOCKED |
“no
Veg
I — 350141 +
|
Von
LATA CUT |
face
I
“IH
MOTE 1 The ouigur wall an «3003 100 Frye 36 Clock EA Voss
ma Ver a ad a Kane May DOCH 16 ECON 42106 Oulpul 5 vérséol
icloch eg Угу remy shill be Ar Wel Cala Auigires ovalo ier The old
add rar wen CC Veo 3 MAPEO 10 МО.
METE 7 11 C5 races лгал rom Via TO YO who CIOChed Yo
mat Др Than Oele Tier al Dodo? Gory at em a Aca e adi
DORE ACER COPRANS VOS
SILICON GATE MOS 8702A
TYPICAL CHARACTERISTICS
lop CURRENT VS, TEMPERATURE
op CURREM md)
1 a +0
ARE TENMPEMAa TUE BC
a
E
F
LT)
=
I
=
-
x
IMPUTA + Yee т
Ln
DLITEL:TA ABE OFEN -
т —- т - E
5
"re 1
. =
EL an 104
CHTFUT SOURCE CUHALNT al
or
OUTPUT SINK CURRENT
V5. OUTPUT VOLTAGE
QUTPUT CUARENT VE,
Ypo SUPPLY VOLTAGE
doar ng Hg
- -E -7 -B
Vip SURFLY wOLTADE тм!
L
OUTPUT CURRENT VS.
TEMPERATURE
fp CUITRUT MK CLIRRENT Cm)
-
i | y
Ll |
= Ur 1 |
1 MON E 4 E мн
- | AMBIENT TEMPERATURE 4°R1] |
y ! a . a
x PET |
2 | |;
Wom gw :
Бы re | 1
= "1 Yen * x : I ,
3 Von" 0.87 ; | i
: ||
TL. any :
2 boy
: |
= +
AVERAGE CURRENT VS. DUTY
| CYCLE FOR CLOCKED Vgg
]
ла 0 1 45
! =
ee E 129 45
>
! = logs 15
+ —— £ 190 -
2 =
= E ja
z CE] 8 =
м =
5 м
Eq
$ :
= = 00
Dag! я
DA
—___—lerme—i
je von +
a
4 -3 7 1 с "1 1 +1 4 [| 1h 29 añ I =] 6 0 Init an Le
QUTEUT VO, TAGE МУН Гб SUTT CYCLE dal
ACCESS TIME VS. ACCESS TIME YA.
LOAD CAPACITAMCE TEMPERATURE
1400 т 1400 |
: : . i
1300 - Ze A —— — Pr + _ TR] =. —.- о 1 1 4 1 — +
120 н.о — - —_— —— “290 } - -— Le а a -
1
100 = 1100 -1
= E
= on = 1000 4
= =
= =
= MH —- = 00 |— — - _ ‘ + ——
a A
SDE еее =a ATTLLOAD -- = se AAA
4 мор ОМ 7 TTL LOAD - 20 pt
70D — . TR = Maa 15 '
“oo - Въ ес
BL + da Yao + a 4 AK x. Yoo = SOY
т, ZA “cs = Aw
599 | - - += ——-—— -—+——--"—4 500 - -
= : — В
a т : 1 —
Û 10 26 30 dd $ KO Mp BD OÙ 100 5 20 № 49 54 6 TÚ AD 90
LOAU CAPACITAWCE [pF] SYBIENT TEMPERSTURE © €!
SEE TT TET Tle 7 a TE Hahei
SILICON GATE MOS 8702A
PROGRAMMING OPERATION
D.C. AND OPERATING CHARACTERISTICS FOR PROGRAMMING OPERATION
Ta = 25°C, Vec = ОМ, Мав = +12V + 10%, CS = OV unless otherwise noted
SYMBOL TEST MIN. TYP. MAX. UNIT CONDITIONS
lap ı Address and Data Input 10 mA, Vi, = —48Y
Load Current
Psp Program and V 10 mA Via = —48V
Load Current . |
lag Vag Supply Load Current | 05 | mA
lope! Peak Ing Supply 200 MA | Von= Voca= -48BV
Loäd Current | Vos = 55V
Y Le Input High Voltage | 0.3 y
| Y...» Pulsed Data Input | =46 | C1 0-48 | у
Low Voltage |
Vize Address input Low —40 48 Vv
Voltage
V. y Pulsed Input Low Vo, |-46 —a8 V
and Program Voltage
Van Pulseg Input Low -35 -80 \
| Мос Voltage
Mote 1:
A.C. CHARACTERISTICS FOR PROGRAMMING OPERATION
Tawgient * 285€, Yoo = OV, Van = + 12V + 10%, CS = 0Y unless otherwise noted
inne flows anly during Y pg, Ycg on time, Ingp should nat be allowed to excead 300 mA for greater than 100 usec. Average power
supply current ipgp typically JO má ar 20% duty cycle.
| TEST
SYMBOL MIN, TYP, MAX. | UNIT CONDITIONS
| Duty Сус! (Мор, Уса | 20 %
Tap Program Pulse Width 3 ms Vas = —35Y, Yoo =
prog = —48V
ow Data Set Up Time 25 ps
‘рн Data Hoid Time 10 us
tuw | Ypo - ‘aa Set Up 100 | HS
typ | Vpn , Vag Hold 10 “100 us
tacw '% : Address Complement 25 | ps
: Set Up
tacH'? | Address Complement 25 us
| Hold :
ТАТУ Address True Set Up 10 #5
ТАТН | Address True Hold 10 | HS
Note 2.
258] must ba programmed as shown in the timing diagram for a minimum of 142 times,
Ali 8 address bits must be in tha complement state when pulsed Vp and Vig Move to their negative levels. The addresses (0 through
SILICON GATE MOS 8702A
SWITCHING CHARACTERISTICS FOR PROGRAMMING OPERATION
PROGRAM OPERATION
Conditions of Test:
Input pulse rise and fall times = usec
CS = Ov
PROGRAM WAVEFORMS
=! Тен |"
| |
Я АСМ
|, |
E |
|
BINARY COMPLEMENT DOF BINARY ADDRESS
ADDRESS ADDRESS OF WORD OF WORD TO BE
TD BE PROGRAMMED FROGRAMMED
—40 ta AB :
' ! =Tupg > °
I
9 — be Tay
PULSEO Yon
POWER SUPPLY
—&6 10 --48
9
PULSED Yes
POWER SUPPLY
—35 ra —40
0
FROGHAMMING
tary ——
... E tou ..
PULSE
—6 10 — AR
> ла
0 ст =
DATA INPUT 2 Ue
DEVICE 7 Ae
OUTPUT % J H
LINES) ; LLO
— 46 tn —48
DATA STABLE
Gi
TIME CHANGE
PROGRAMMING OPERATION OF THE 8702A
ADDRESS
When tha Date Input for © Ther the Dats Output WORD hy Ag Ag Ay A3 Az AL Ap
tha Program Mada is: during the Read Mods 15:
= Q | Q 0 0 Ú О 0 0 0
Мая = —4B8V pulsed Logic 1 = Мон = 'Р' ат таре 1 | 9 0 9 9 | ; ;
| | jL 11
НР = Y Loge Ù = Vo ="N Gr tape ER | 1 1 1 1 1 1 1 1
Address Logic Level Quring Aaad Mode:
Address Logic Laval During Program Mode :
Logie Q = Wi 1.3)
Logie 0 = Vy ap [™ —40W1
Logic 1 Y y 7
Lage 1 + Y yp (7 OvI
SILICON GATE MOS 8702A
PROGRAMMING INSTRUCTIONS
FOR THE 67024
|. Operation of the 87024 in
Program Mode
Initially, all 2048 bits of the ROM are in
the "Ô" state (output low). Information
is introduced by selectively program-
ming *'1's (output high) in the proper
bit locations.
Word address selection is done by the
same decoding circuitry used in the
READ mode (see table on page 6 for
togic levels). All 6 address bits mustbe
in the binary complement state when
pulsed Yon and VV... move to their nega-
tive levels. The addresses must be held
in their binary complement state for a
minimum of 25 sec after Y... and Y.
have moved to their negative levels.
The addresses must then make the
transition to their true state a minimum
of 10 „sec before the program pulse
is applied. The addresses should be
programmed in the sequence 0 through
255 for a minimum of 32 times. The
eight output terminals are used as data
inputs to determine the information
pattern in the eight bits of each word,
À low data inputlevel ( — 4841 will pro-
grama'1 anda high data input level
(around) will leave a "0" (see table on
page 6). All eight bits of one word are
programmed simultangousty by setting
the desired bit information patterns on
the data input terminals.
During the programming, Y. Y-- and
the Program Pulse are pulsed signals.
N. Programming of the 87024 Using
Intal *Microcomputers
Intel provides low cost program devel-
opment systems which may be used to
program its electrically programmable
ROMs, Note that the programming
specifications that apply to the 87024
are identical to those for Intel's 1702A.
A intellec®
The Intellec series of pragram de-
velopment systems, the intellec
8/Mod 8 and intellec 8/Maod BO, are
used as program development tools
for the 8008 and 8080 microproces-
sors respectively. As such, they are
equipped with a PROM programmer
card and may be used to program
Intel's electrically programmable
and ultraviolet erasable ROMs,
An ASR-31 teletype terminal is used
as the input device, Through use of
the Intellec software system monitor,
programs to be loaded into PROM
may be typed in directly or loaded
through the paper tape reader. The
system monitor allows the program
:0 be reviewed or altered at wili
prior to actually programming the
FROM, For more complete informa-
‘ion on these program development
systems, refer to the Intel Micro-
computer Catalog or the intellec
Specifications.
B. Users of the SIM8 microcomputer
programming systems may also
program the 8702A using the
MP7-03 programmer card and the
appropriate control ROMs:
SIMS system—Control ROMs
A0860, A0861 and ADAGA.
44
Il. 8702A Erasing Procedurs
The §702A may be erased Бу ехро-
sure to high intensity short-wave ultra-
violat light at a wavelength of 2537 A,
The recommended integrated dose (1.e.,
UY intensity x exposure time) is
6W-sec/cm?. Examples of ultraviolet
sources which can erase the 8702A
in 10 to 20 minutes are the Model
UYS-54 and Model 5-52 short-wave
ultraviolet lamps manufactured by
Ultra-Violet Products, Inc. (5114 Walnut
Grove Avenue, San Gabriel, California).
The lamps should be used without
short-wave filters, and the 8702A to
be erased should be placed about one
inch away from the lamp tubes.
intal Silicon Gate MOS 8708/8704
8192/4096 BIT ERASABLE AND ELECTRICALLY
REPROGRAMMABLE READ ONLY MEMORY
+12V, =5V
+ 8708 1024x8 Organization
* 3704 512x8 Organization
® Fast Programming —
Typ. 100 sec. For All 8K Bits
® Low Power During Programming
® Access Time — 450 ns
m Standard Power Supplies —
# Static— No Clocks Required
=" Inputs and Outputs TTL
Compatible During Both Read
and Program Modes
» Three-State Output—OR-Tie
Capability
®
The Intel 8708/8704 are high speed 8132/4096 hit erasable and electrically reprogrammable ROM's (EPROM) ideally suited
where fast turn around and pattern experimentation are important requirements,
The 8708/8704 are packaged »m a 24 pin dual-in-line package with transparent lid. The transparent lid allows the user to ex-
pose the chip to ultraviolet light to erase the bit pattern. A new pattern can then be written into the devices.
Á pin for pin mask programmed RO", the intel 8308, is available for large volume production runs of systems Initially using
the 8708.
The 8708/8704 is fabricated with the time proven N-channet silicon gate technology.
PIN CONFIGURATIONS
—
а, Г] 20 [wie
a: 23] 2»
As): 777) -
sa] 4 21/77] ne
аз] = вто: |] 75 we
«(à 8704 19 [7] wen
a. CA» гв [О] вн км
а. (в 17 Г] гла
ma ив [7] го.
о, [1] 1 [e
Ca a [Jee
wi] 7 Hs
“BIH Vo
8708 - A,
FIN NAMES
ba Au | AODRÉSS INÉUYS
Oy 0g | DATA GUEPUTE
CME | CHIP SELECT NRAITE ENABLE [%PUT
BLOCK DIAGRAM
DATA QUTAUT
a, a
]
||
CHIP SELECT
LOGIC
al
Lr
ñ
QUTPUT BUFFERS
Y
DECODER ¥ GATING
ny hy
I
ANA EE a
IMPLITS |
|
x 64 x 178
DECODER ROM ARRAY
L
5-45
SILICON GATE MOS 8708/8704
Absolute Maximum Ratings *
Temperature Under Bias
Storage Temperature | rer a ea 1
All Input or Qutput Voltages with Respect to Ves
{except Program| _ . aaa
Program Input to Vgg
rm 1 1 1 br rb EL EE 4 4 EE = ал тии ти wm
Supply Voltages Vcc and Ves with Respect to Vgp. . . . . . .
Voo with Respect to Vka
Power Dissipation
READ OPERATION
D.C. and Operating Characteristics
Toe me me ma 1 ви к 1 ns er
. -25 Cto+85°C
. -65°C to +125°C
. *15Y to -0.3V
‚ +35Vto-03V
+15Y to -03V
‚ *20V to -0,3V
1.5W
*COMMENT
Streams above those listed under "Absolute Maximum
Ratings” may cause permanent damage 10 tha device.
This ix a stress rating only and functional operation
of the device at these or any othar conditions above
those indicated in tha operational sections of this
specification is not implied. Exposure to absolute
Maximum rating conditions for axtended pariods may
affect device reliaebilivy.
Ta = 0°C to 70°C, Ver = +5V +5%, Vgp = +12V 15%, Vap = -5Y 15%, Yes = OV, Unless Otherwise Noted,
Symbol: Parameter
Min. Typ. [11 Max, | Unit Conditions
lu . Address and Chip Select Input Load Current 10 UA Vin = B.25V
lo, Output Leakage Current 10 | wA | Vout = 5.25V, CS/WE = 5V
Ion | ‘co Supply Current 50 65 MÁ Worst Case Supply Currents:
lec Ver Supply Current 10 MÁ All Inputs High
e : Veg Supply Current . 30 45 - mA CS/WE = 5V; T, = 0°C
VL Input Low Voltage Ves 0.65 \
VIH Input High Voltage — 3.0 Yec+1 V
VoL Output Low Voltage 0.45 \ bal = 1.6mA,
VoH1 Output High Voltage ) 3.7 v | Igy = -100uA
VoH2 — Output High Voltage ) 24 V | log =-1mA
Ро ~ Power Dissipation
300 ri Ta = 70°C
NOTES: 1. Typical values ara far Ta = 25°C and mominal supply vôltages.
e. The program input ¿Pin 18) may be tiad to Vas or Voc during the read mode.
SILICON GATE MOS 8708/8704
A.C. Characteristics
Ta = 0°€ to 70°C, Vee = +BY 15%, Vop = -12Y 6%, Vag = -5V 15%, Vgg = OV, Unless Otherwise Noted.
Symbol Parameter Min, Typ. Max. Unit
ТАСС Address to Cutput Delay 280 450 ns
teo Chip Select to Output Delay - 120 ns
tor | Chip De-Select to Output Float 0 120 ns
toH | Address to Output Hold 0 ns
Capacitance!) 1, = 25°C, f = IMHz
symbol "Parameter Тур. | Max. Unit| Conditions
Сы Input Capacitance - 4 6 РЁ | М\№=0\
Cour Output Capacitance 1 8 12 pF | Vour-0V
Mote 1. This parameter 15 perindicatly sampled ang not 180% tested.
A.C. Test Conditions: .
Output Load: 1 TTL gate and C, = 100pF
Input Rise and Fall Times: =20ns
Timing Measurement Reference Levels: 0.28Y and 2. 8Y for inputs; 0.8Y and 2.4Y for outputs
Input Pulse Levels: 0,65Y to 3.0V
Waveforms
ADDRESS x X
- ‘он -
C5. WE N VA
a BO» _ ШИ
= TACE -
DATA -. ORTA os DATA DUT ©
. DATA OUT INVALID i
OUT Lo" | o X CUE FLOATING по:
SILICON GATE MOS 8708/8704
PROGRAMMING OPERATION
Description
Initiatly, and after each erasure, all bits of the 8708/8704 are in the 17 state (Output High). Information is introduced by select
ively programming “0” into the desired bit locations.
The circuit is set up for programming operation by raising the CS/WE input (Pin 200 to +12V. The word address is selected in the
same manner as in the read mode. Data to be programmed are presented, B-bits in parallel, to the data output lines 101 -0g).
Logic levels for address and data lines and the supply voltages are the same as for the read mode. After address and data set up
one program pulse {Vp] per address is applied to the program input {Pin 18), One pass through all addresses to be programmed is
defined as a program loop. The number of toops {M} required is a function of the program pulse width (tay) according ta
М x toy = 100 ms,
For program verification, program loops and read loops may be alternated as shown in waveform В.
Program Characteristics
Ta = 25°C, Voc = +5V t5%, Vop = +12V 25%, Vgg = -BV 15%, Veg = OV, CS/WE = +12V, Unless Otherwise Noted.
Symbol Parameter ; Min, Typ. Max. Units
tag Address Setup Time 10 Hs
{055 CS/WE Setup Time 10 us
tos Data Setup Time 10 | Hs
ТАН Address Hold Time 1 us
‘сн CS/WE Hold Time 5 HS
‘он Data Hold Time 1 us
tor Chip Deselect to Cutput Float Delay 0 120 ns
tora Program To Read Delay 10 ME
tr Program Pulse Width Л 1.0 ms
tpg Program Pulse Rise Time D 2.0 5
ter Program Pulse Fall Time 5 2.0 Lis
Ip Programming Current 10 20 mA
Vp Program Pulse Amplitude 25 1 27 \
NOTE: imtels standard product warranty applies only 10 devices programmed to specifications described here.
Erasing Procedure
The 8708/8704 may be erased by exposure to high intensity short-wave ultraviolet light at a wavelength of 2537A. The recom:
mended integrated dose. (ie, UV intensity x exposure timel is 10W-seciem2. Examples of ultraviolet sources which can erase the
8/08/8704 in 20 to 30 minutes are the Model UVS-54 and Model 5-52 short-wave ultraviolet lamps manufactured by Ultra-Violet
Products, Inc, (5114 Walnut Grove Avenue, San Gabriel, California). The lamps should be used without shertwave filters, and the
8708/8704 to be erased should be placed about one inch away from the {amp tubes.
SILICON GATE MOS 8708/8704
Waveforms
(Logic levels and timing reference levels same as in the Read Mode unless noted otherwise.)
A) Program Mode
CSAWE = +12V
I
——. OME PROGRAM LOQF |
i
y
+
ADDRESS LDODRAERED ; ADDRESS 1 + # + ADDRESS 1023
d
1
lage ет toy ow a Taya
|
By
PROGRAM
PULSE
ns
Lug rdf =. mfr ча ‘юн — =
J 4
"
CATA
0.0,
+
ir
B) Read/Program/Read Transitions
READ A am PROGRAM = READ
Loge ae LOOP To ск
i
i
| 1
!
17 -
CEMNE RY ———l — — \
fn л
. эта |
1 ‘ен 1
рр oe ee
Hy 1
I
PROGA AM — I — =
PULSE .
a
Tne -— wm rel lpg
== ny A
DATA DATA OUT DATA DATA IN DATA IN DATA OUT
G, Oy VALID FLOAT VALID WALID МАНЫ
SILICON GATE MOS 8708/8704
Typical Characteristics ¡Nominal supply voltages uniess otherwise noted):
Ly LAA
т (се!
OUTPUT SINK CURRENT
V5. OUTFUT VOLTAGE
|
Wan = 4. 75V
7
Teo.
„350 + '
| Te EN 7
64+— т, = 20°C a
: +
d [rer mer aan NE SEE LE ES = то —
2 ‚о —.
— PEC
&
û 2 4 .E в 1.0
Ma, [VOLTS
MAXIMUM JUNCTION TEMPERATURE
YS. AMBIENT TEMPERATURE
TED
| #12 7 50 CT
1 an = -hZ5V |
100 } ba |
i
5
I
|
0 L
0 20 40 RL 70
T, I El
ACCESS TIME
VE. LOAD CAPACITANCE
SUPPLY CURRENTS (má)
Taco im)
BO
RANGE OF SUPPLY CURRENTS
VS. TEMPERATURE
ALL POSSIBLE OPERATING
CONDITIONS:
Vee " 5.25V
Мор = 12.8
Vag * -5.25v
Pay :
RIN lo,
Pa.
Crea й тт
, , TE .
o
1
= = —— nn
a - A x Po
1 isa |
a . co!
SWE = . ‚
L E E Lo , a * A 5 !
A dl
+! o i . a * La . =; I
Let maida nan (RARER “|
LOSE + LOW !
ec
Fer
Q zu 40 ES #0 100
т, се
ACCESS TIME VS, TEMPERATURE
ыы
1TTL LOAD + 100oF
Ta CE
Ta = 25°с
Tar. nal
ma
=
200
5-50
44)
500
intel Silicon Gate MOS 8302
2048 BIT MASK PROGRAMMABLE
READ ONLY MEMORY
a Access Time — 1 „sec Max. w Static MOS — No Clocks Required
Fully Decoded, 255 x 8 Organization = Simple Memory Expansion — Chip
Inputs and Outputs TTL Compatible Select input Lead .
, = 24-Pin Dual-In-Line Hermetically
Three-State Output — OR-Tie Sealed Ceramic Package
Capability
The Intel 8302 is a fully decoded 256 word by 8 bit metal mask ROM. It is ideal for large volume produc-
tion runs of microcomputer systems initially using the 87024 erasable and electrically programmable ROM.
The 8302 has the same pinning as the 8702A.
The 8302 is entirely static — no clocks are required. Inputs and outputs of the 8302 are TTL compatible,
The output is three-state for OR-tie capability. A separate chip select input allows easy memory expansion.
The 8302 is packaged in a 24 pin dual-in-ling hermetically sealed ceramic package.
The 8302 is fabricated with p-channet silicon gate technology. This low threshold allows the design and
production of higher performance MOS circuits and provides a higher functional density on a monolithic
chip than conventional MOS technologies.
PIN CONFIGURATION BLOCK DIAGRAM
NA DATAQUT1 DATAOUTA
A: 24 [_] Yun | |
A 12 zal Yer
OUTPUT
ay a 221 | re CS — BUFFERS
DATA OUT 177] 4 ILSEI 21% }
—_ ha
DATA QUT 27 |5 sof 4 2048 BIT
= ROM MATRIX
DATA OUT 36 af Jas 1256 X 8)
B302
DATA OUT al |? 18 e
Data OUT 5 Ye la; DECODER
DATA QUE Bi | a 16 se |
DATA OUT 71 | 10 15) mc
— = INPUT
DATA QUT SÍ | 1+ (мб | 14 ES DRIVERS
мес [| 12 13 Inc | 1 TT |
> — An Ay А)
PIN NAMES
Ag ADDRESS INPUTS
Cs CHIP SELECT INPUT
DO DOg DATA OUTPUTS
5-51
SILICON GATE MOS 8302
Absolute Maximum Ratings *
Ambient Ter~perature Under Bias
Storage Temperature
Soldering Temperature of Leads [10 sec) ........ +300°C
Power Cissipatión a 2 Watts
Ingut Valtages and Supply
Voltages veith respect ta Vee LL +05 to —20Y
0” 10 +70"
—587C to +125°C
“COMMENT
Stresses above those listed under "Absolute Maximum Нат.
ings" may cause permanent damage to the device. This is a
stress rating andy and functional operation of the device at
these or at any other condition above those indicated in
the operational sections of this specification is not implied.
Exposure to Absolute Maximum Rating conditions for ex-
tended periods may affect device reliability.
READ OPERATION
D.C. and Operating Characteristics
T, = 0°C to 70°C, Vo, = +5V+5%, Ypo = —9V+5%, Var = —9V£5%, unless otherwise noted.
SYMBOL | TEST MIN. Tyri2b MAX. | UNIT CONDITIONS
ho Address and Chap Select 1 нА Vi, = 00W
Input Load Current
lg Output Leakage Current Е bA Your 7 0.0V,CS= Veo =2
lope Power Supply Current 5 10 mA Meg Mec. CS=Voe—2
| lg = 0.0mA.T, = 25°C
Moi | Power Supply Current 35 50 | mA: ES:Voc—2
- . (a!
lan =0.OmA. Ta, - 2h С
laca Power Supply Current 37 6 |! mA cE=0.0
lo COMA Ta = 25"
| Paver Supply Current — 385 60 A CB-v_. -2 Contmueus
207 wer supply LUrrent . ti re E Man — ; Operation
| la 0.0mA | T, = 0°
ler Output Champ Current X 14 md YT = 10VW,T, = 09%
_ — о
lego Qutput Clamp Current 13 ma Vout = —1.0¥, Ta = 25 C
Lee Gate Supply Current 1 HA
Mila “Input Low Voltage for 1.0 0.65 Y
TTL Interface
: Vita Input Low Voltage for ‘oo Vee —B Y
MOS Interface
» Address and Chip Select | Vo -2 Yo 03 1 м
Input High Valtage
|. Output Sink Current 16 4 _ mA Maut > 0.45М
] пн Output Source Current —* 0 . ma. Voor” 0.0v
We Output Low Voltage == 0.45 | Y la, = 1.6mA
Von Dutput High Voltage 3.5 45 | bop = — 100 pA
ore 1, моб ия ГРОСНОСКВа 10 reduce power dessipadina, te [his cnnde average Io T0PASés 10 Aroport Or 10 Yoo duty cycle
NOTE Ta D CA! ACER Are a1 novbnal vonages and Ta 569
5-54
SILICON GATE MOS 8302
A.C. Characteristics
T, =0°C 0 +70°C, Мос = OV 15% Von 7 —-8V +8% Ver = —9V +5% unless otherwise noted
SYMBOL TEST MINIMUM | TYPICAL MAXIMUM UNIT
Freq. Repetition Rate 1 MHz
Ton . Previous read data valid 100 ris
tacc Address to output delay - ! ‚700 1 us
| tbvac Clocked Vag set Up 1 Hs
tos Chin select delay 200 ne
teo Output delay from CE 500 ns
Тор Output deselect 300 ns
tout | Data out hold in clocked V;4g Made (Note 1): 5 | Hs
Note 1, The output will ramain valid for toy ge as 100g se clocked Yoo in st Woe, An sddress change May occur ag $000 IH tha autput 15 waned
lclocked М сд may stl e at Vogt. Cata bacomes Invalid far tha old sodrasy when clocked Yoo ls raturnad to Yoo.
Capacitance’ 7, = 25°C
Switching Characteristics |
|
Conditions ot Test:
Input puise amplitudés: D to 4: tp. t, $50 ns
Qutput Icad is 1 TTL gate) measurements made
at output of TTL дате (Гор = 15 ns)
Al Constant V_. Operation
CrSLE T ME IF AF ——rr
I
Y
IH Ns
ALOE
Hs
Y
— rs mm 1
a | = "ом —
1
cs 1 !
I
чм
hk I
i -
Ten !
DATA E CATA OUT .
aur : IP WALD - !
1
“es, ! !
tr large CaTh OUT .
MY ALID
DESELECTION OF DATS QUTHIT IN OR TIE DFEIATION i
x
Won = |
ACNE TA X
3
У ГЕ
I
Wy =p
=
1
vi, о 1
| — log
Y ai —
TATA !
OUT 1
5-53
rr VLE TIME
Мы то.
ADORE SE ,
ы
SYMBOL TEST MINIMUM * TYPICAL MAXIMUM | UNIT CONDITIONS
Cin Input Capacitance 5 10 | pF MNT Усс All
Cour Qutput Capacitance : 5 10 nF = Vee unused ping
Су Veg Capacitance 0 nr
Go | Vas = Veo ground
“This parameter is pariodically sampled and 15 not 100% tested.
8B! Clocked V__ Operation
| FREQ —————— dl
1
A
iL ! -
a] Ls Y 1
11 Pca '
Wed | I
ÉLOCNED I] I
W I I
GG
Veg | 1 {SEE NOTE HM
[лье дес — — = | rel Lane
1
“пы |
DATA CATA DAT | CATA QUT
CHT | МАЛО INVALID
Yo |
, DESELECTION OF DATA OUTPUT 9 06 TIE QÉERATION
Ча
ABRES ‘|
Ya I
NOTE 7 — В (нм
a UP
vu I ” = a a "== тая тв =) =
: r .
cn \ 7
i
“a ! 1
‘Den Tap = ==
Vo
ons
DATA OUT |
aer
MOTE 1: The gurput wilh ramen valid lar oH A long eL [AHR Lr] ie
"AT Мет. An add das cha A A ai {Rd GUIPUT IF PENT
Ictackad Yeso má BOC Ear Rob. CO become nego dr De dd
pddi @4d when RI Yon qd O Mg
NOTE 2 4 CS mákiei a Era En om MIL 10 y da ciocked Yoo
Mar Yo, ham Oman on af QuiAut OCCUFS At Toy} Br EA HM АО
Oran Ar Corta Ye.
SILICON GATE MOS 8302
Typical Characteristics
Ing ÉLRAENT {mi}
ACCESS TIME (md
чи
= HEY Y
4 xa
Ion CURRENT VS. TEMPERATURE
го
"E
Ye”
Мор" - #4
Yes” —W
INPUTS = Y
CITFUTS ARE OMEN
= Weg
Ay "e MH 100 120
AMISENT TEMPERATURE 192)
1
ACCESS TIME VS.
TEMPERATURE
1 TTL LÜAG Sr 20 pt
Мос HM
“oo "FF
“ño - VW
MM к 40 5% MD
AM TEA TUE PACO
Ld
зы ЕЁ
AVEARGE IL, Ima) da
=
=
>
10 © om
ACCESS TIME VS.
LOAD CAPACITANCE
1 TTL LOA
= +54
Усс
- Yon "9
“ов п —9м
*, = 5°C
ACCESS TIME na)
- 8 8 8B НЕВЕ
=
LOAD CAFACI TANCE ipFl
OUTPUT CURRENT VS.
Vpp SUPPLY VOLTAGE
1M X № #0 BM 8 70 к HO
x B |
£ EY
= vec 7
т
wr Vee WY =
= Y OL = 4 SY i
BD pp Ta - 28°C
x
; Y
Lu
> 1 _
= Ema A
3 anne ng. 1
Lolly
a , |
[ i : 1 |
a Ly ? T :
| + i -" E | —# | -1 L
Yoo SUPPLY VOLTAGE {wh
— -— | |
Mon < +5# 1
“as = -qy }
Vos " 0.0 |
„ой
Ta BE 1.
[ts
он ОН ТРЫТ SOURCE CURRENT ¿mal
+
AVERAGE CURRENT VS. DUTY
CYCLE FOR CLOCKED Vgg
CLACKED We ú
Yop
a
TA
2 30 Le ы an 10
DUTY CYCLE [A
5-54
Ia, OUTPUT HNK CURRENT (mA)
Igy CUTEUT SOURCE CUAHERT ina]
1] a
Í ¢ 0 E X KM MN)
AMBIENT TEMPERATURE PC} |
wl 111
Wer" + I 1 !
a"! + —
Y ADV | |
TE ÜV - ;
QUTPUT SiNK CURRENT
V5. OUTPUT VOLTAGE
|
149
Y BY
| Fed — са ° т
= Ya" A
= 1 Yoo —
Е e Ta 2600
n | pd
5 10 T
и CE = gow
IL. Á—. 2 ED Pal на =
=
LB wo“)
=
+
1
L
|
ы
|
Le
я
-
wo
+1 ri + +4
САРы YOLTAGE (VOLTA
OUTPUT CURRENT VS.
TEMPERATURE
Ros ' Мор = HI I
) ' Yoo" N
I ) Yon" — М .
‘ SN Vou» +
В «вом To]
| a!
intel
a Fast Access — 450 ns
Silicon Gate MOS 8308
8192 BIT STATIC MOS READ ONLY MEMORY
Organization -- 1024 Words x 8 Bits
8 Three State Output — OR-Tie
u Directly Compatible with 8080 CPU Capability
at Maximum Processor Speed
# Two Chip Select Inputs for Easy
Memory Expansion
® Fully Decoded
# Standard Power Supplies
+12V DC, +5V DC
Bm Directiy TTL Compatible — All Inputs
and Qutputs
The Intel® 8308 is an 8,192 bit static MOS mask programmable Read Only Memory organized as 1024 words by B-bits. This
ROM is designed for 80BO microcomputer system applications where high performance, large bit storage, and simple inter-
facing are important design objectives, The inputs and outputs are fully TTL compatible.
A pin for pin compatible electrically programmed erasanle ROM, the Intel 8708, is available for system development and
small quantity production use,
Two Chip Selects are provided — CS, which is negative true, and CS4/C3, which may be programmed either negative or
positive true at the mask level.
Tha 8308 read only memory is fabricated with N-channel silicon gate technology. This technology provides the designer with
high performance, easy-to-use MOS circuits.
PIN CONFIGURATION
BLOCK DIAGRAM
—Í — DATA QUT1 ВАТА ОТ В
a; Ch 2407) vee |
aD]? 3 A 68, —= OUTPUT
As [3 22 Ja, es, E — BUFFERS
a4 21] van
a, (ds (JS, 2192 BIT
ROM MATRIX
az 6 8308 19] vo 11074 X El
a []7 18ÿ_) cs, €, |
Jet 17] os DECODER
a (Дэ o
оз (19 15 [J os —
03 [7 14] os BUFFERS
Ves 12 13 o | | mar TT Î
С - * Ay A} Ay
PIN NAMES
Ag Ay ADORESS INPUTS |
‚ Oro DATA OUTPUTS
ı 65,053 CHIP SELECT INPUTS
A — —
5-55
SILICON GATE MOS 8308
Absolute Maximum Ratings*
-25 C to +85°C
-65“€ to +150°C
Ambient Temperature Under Bias
Storage Temperature... LL... LLL.
Voltage On Any Pin With Respect
To Vag
Power Dissipation
+ + #4 = = +
-0.3V to 20V
1.0 Watt
D.C. and Operating Characteristics
Ta =0 Cto+70 €, Vor = BY 5%; Von = 124 £5%, Vag = -5V +5%,
"COMMENT
Stresses above those listed under “Absolute Maximum Ratings‘ may
cause permanent damage to “he device. This is a stress rating only
and functional oparâtion of the device at these or any orhar condi-
tons above thosa indicated in thea oparational sections of this speci-
fication is nat implied. Exposure to absolute maximum rating condi-
tions for axtendad periods may affect davice reliability.
Vee = OV Unless Otherwise Specified.
Symbol Parameter - me Unit Test Conditions
Min. Тур. | Мах
ГЕ Input Load Current i 10 HA Vin = O to 5.25Y
{All Input Pins Except C54}
lel Input Load Current on CS, 1.6 mA Vin = 0.45Y
I pe Input Peak Load Current on CS, 4 mA Vin = 0.8V to 3.3V
Lee Input Leakage Current on CS, 10 LA Vin = 3.3V to 5.25V
lo Output Leakage Current 10 НА Chip Deselected
Vi Input “Low” Voltage Ves-1 0.3v Y
Y H Input High“ Voltage 3.3 Vec+1.0 Y
VOL Output "Low" Voltage 0.45 \ lo = 2mA,
Von, Output “High” Voltage | 2 4 V1 Igy = -4mA
Vou? Output “High” Voltage 37 | V | lon =-1mA
lec Power Supply Current Yec 8 2 MA
Ina Power Supply Current VDD | 23 60 má
leg Power Supply Current Vgg 10uA 1 MÁ |
Po Power Dissipation 775 mW |
MOTE 1: Typical values lor TA = 25°C and nominal supply voltage
O.C. OUTPUT CHARACTERISTICS
TYPICAL
br ra
Vo, WOLTS
CC. OUTPUT CHARACTERISTICS
ta Dra TIE
` TYPICAL
: `
ко. Ma a
“
=
| 24 28 78 30 37 la 36 IE 40 47
Van VOLTS
SILICON GATE MOS 8308
A.C. Characteristics
Ta = 0°C to +70°C, Vec = +5V 25%: Vop = +12V +5%, Vap =
—5> Y 18%, Ves = 0Y, Unless Otherwise Specified.
Symbol Parameter Limits Unit
Min. Typ. Max.
tacr Address to Output Delay Time 200 450 rs
tco Chip Select 1 to Output Delay Time 85 160 Ms
tcos Chip Select 2 to Output Delay Time 125 220 ns
tor Chip Deselect to Output Data Figat Time 125 | 220 ns
NOTE 2: Refer 10 conditions of Test for AC, Characteristics, Add 50
VOH = 1.7% Elgg a - мА, С) = 100pF,
CONDITIONS OF TEST FOR
A.C. CHARACTERISTICS
nanoseconds (worst casel ta specified valuas at
CAPACITANCE T,=25°C,f=1 MHz, Vag =-5Y. Ypo.
Vee and all other pins tied to Ves.
Qutput Load. ....... 1 TTL Gate, and Ch gap = 100pF Limits
Input Pulse Levels .. aa B5V to 3.3V Symbol Test
Input Pulse Rise and Fall Times ........,... 20 nsec Typ. Мах.
Timing Measurement Reference Level Cin ; input Capacitance GpF
Ce eee A 14140 2,4V Vin. Von: 08Ÿ Vi. V
|H. COH IL OL Cour Qutput Capacitance 12pF
- face -
ADOMERS
^^, X
. ‘ен |
с5, \
Or ET OE OE. AEE SE ar aa НН EE = Mal 4%
%
8,8,
: DATA
INVALID
5-57
SILICON GATE MOS 8308
Typical Characteristics (Nominal supply voltages unless otherwise noted.)
I, imal
inp V5. TEMPERATURE
INCAMALIZED:
1.4 T т — T
. 1 1
13 H—--—--———-<-—.- т
12 —— + HH es HH
1.1 +-—--— -
1.6 mm oe
9 H-—— ————— - ac
8 Dee о
|
7 |----- i но =
E +
À.
о = : '
р 19 XD 30 40 5 80 70 #6 =
AMBIENT TEMPERATURE T, IC]
CS, INPUT
CHARACTERISTICS
15 y
- |
|
#.5 —-— = res Г —
!
20 F— +
15 }- —_ i
1
1.0+
Ll
a L
a 5 10 15 2.0 25 in
Vi [VOLTS]
5-58
À GLITFLIT DELAY (nSEC)
A QUTPUT CAPACITANCE
V5. A OUTPUT DELAY
+
Th
=
|
A CAPACITANCE [pF)
Tape VS. TEMPERATURE
(NORMALIZED)
Ö 1 20 30 40 50 #0 70 a
AMBIENT TEMPERATURE T, MC)
+ 00
>
intel
MCS™
CUSTOM ROM
ORDER FORM
8308
ROM
CUSTOMER
Р.О. NUMBER
DATE
For Intel use oniy
Sr PPPP
STD ZZ
DD
APP DATE
All custom 2308 ROM orders must be submitted on this form. Programming informar
punched card: or punched paper tape per the formats designated on
lon should be sent in the form of computer
this order form. Additional forms are available from intel
MARKING
—— INTEL PATTERN NUMBER
The marking as shown at the fight must conta the Intel logo, the и
product type (PB308), the 4-digit Intel pattern number (PPPP}, à date
code (XXXX], and the 2-digit chrp number (DD). An opt onal customer
identification number may be substituted for the chip Number {ZZ
Optional Customer Number {maximum 9 characters Or spaces,
CUSTOMER NUMBER
——
8308 РРРР
KX KX 22
— —_
DATE CODE
— CHIP NUMBER QA
CUSTOMER NUMBER
MASK OPTION SPECIFICATIONS
A, CHIP NUMBER {CHIP SELECT
SPTION]
Must be specified 0 or 1.
The chip number will he coded in
terms of positive logic where a logic
“1” is high level input.
Chip Select Truth Table
Chip —
Number 51 CS Selected
0 0 0 Y es
1 G 1 Yes
0 1 0 Мо
1 1 1 Мо
Chip Number
B. ROM Truth Table Format
Programming information should be
sent in the form of computer punched
cards or punched paper tape. In either
case, a printout of the truth table
should be accompanied with the order.
The following general format 15 apptic-
able to the programming information
sent to Intel:
® Data fields should be ordered begin:
Ming with the least significant address
(0000) and ending with the most sig-
nificant address (1023).
® A data field should start with the
Most significant bit and end with the
least significant bit,
5-59
+ The data field should consist of P's
and N's, & P is to indicate 4 high level
output (most posit.vel and an N a low
level output {most negative), in terms
of positive logic, a P is defined as a
logic “1° and an N is defined as à logic
COS. if the programming information
is sent on a punched paper tape, then
a start character, 8, and an end charac-
ter. F, must be used in the data field,
See paragraph 2.
t. Punched Card Format
An 8Q-column Hallerith card {prefer
abiy interpreted) punched by an (BM
026 or 029 keypurch should be sub-
mitted. The first card will be a title
card; the format is as follows:
MCS™ CUSTOM ROM ORDER FORM 8308
a. Title Card
TITLE CARD
VO OF OUTPUTS
4 ur e
ZUSTZWMERS
DESIGNATION CUSTOMER S 91854 CR MEET eA Colyme Р pate
COMPARY “ENE LA OH CUSTOMERS F'M и В TABLE NUMBER unch a T
| | , = , — =u LE Yu 2-9 Blank
; — Tr — ELE та TT 0-30 Customer Company Name
na an à Е ВЕНЕ 61 1 31-34 Blank
Pin nn I NI i 35-54 Customer's Company Oivisian or locator
A ETS EEE as En a at IRE Reeds) 55-57 Elank
pa ra 1 11M $ LE à Carr Ero at ' 58—66 Customer Part Number
127521752720 1 52 рум бов" 67 Blank
Boron ie ind Cll EE I II aa 68-75 Punch the Intel 4-digit basic part number
MAULE AULA BIEN dE er ds a dd TL Eda andin( )the number of output bits
Bat ea EE Eira EE at: tic" tt. E... 8306181.
dE bir idas aia Era EE asar kEkSbwvLh 16—78 Blank
pe, a E e E 73-80 Punch a 2-digit decimal number to gen
Edie EEN IEEE FATE ERFANE ERA FIAR ETE[E ERICA pame - En naadtr tify the truth Table number {mask
NN TEE ETAPA BRLE Rot ERAe br Ea daba я 5 programmed chip select number).
b. For a 1024 word X 8-bit organiza-
ton only, cards 2 and the follogw:ng Column > Data
1- unch the S-digit decimal Équivalent of
r 1 . .
cards should be puncned as shown, the binary coded location which be.
gins each card. The address is right
мые justified, i.e. 00000, 30008, 0016
> ия 58 ETC.
DECIMAL WORD LTL A = Ete : DECIMAL NUMBER 6 Blank
ACORESA BE CI há ME IRNCICATIMNO THE .
EACH CARD & DATE FIELCS TAUTH FABLE NUMBER ae Date Field
i : : 1 lank
: \ — Data F
/ ' Li. DE RER Dan 11 E eplf.t.e. "ram fol pepa ptalh E Cal.» e а . à 16-23 gta mld
33 Blank
DSDS EEE FANUFUON CACNENEN DADESATFE MEEEUUNE WUGELRES JANINE 34-41 Data Field
ANIOS 130000 59EE5TETOCIIPMISPNEIENSETIIIDO ai CET angine CIS MI 47 Blank
Lin ea aa UT UY `. 43-50 Data Field
TIT aris - 51 Blank
Peli 11 NS pe E 52-59 Data Field
BILL. DD "тон. 4 Wi EEE PE += e Blank
Se INE: 25-00 ABRE. BONO UB Ho non 61-68 Data Field
Ehen Nah LE- EE TA 59 Blank
ти. Cada 1n UN BAN ma NE NE Hl 8 EE NUCA 70-77 Data Feld
: nea 78 Biank
LL ELE tr IRE rn i Ra AAR pean ws
Vee ann ann 79-80 Punch same 2-digit decimal number as ir
x Е
title card.
2. Paper Tape Format
1° wide paper tape using 7- or E-bit
ASCII! code, such as a model 33 ASR
teletype produces, or tne 11/16" wige
paper tape using a 5-0:1 Baudot code,
such as a Telex produces.
The format requirements are as fol:
lows:
a. AN word fields are to be punched in
consecutive Order, starting with word
feld O (all addresses low]. There must
be exactly 1024 word fields for the
1024 X 8 ROM organization,
b. Each word field must begin with
the start character B and end with the
stop character F, There must be ex-
actly 8 data characters petween tre B
and F.
Sari Charactar ——
у
Cercar Ay Key dor TWE ard carter
Kay lor Tales Lae lead) 75 горела
Sto Cha лете:
EFPPNNNNNFENNNNNNFPPF
L 11 ]
NO OTHER CHARACTERS, SUCH
AS RUBCUTS, ARE ALLOWED ANY.
WHERE IN AWORD FIÉELO. Ifinpre-
paring à tape an error is made, the en-
tire word field, including the B and F,
must be rubbed out. Within the word
field, a P results in a high level output
and an MN results in a low level output.
¢. Preceding the furst word field and
following the last word field, there
must be a leader/traiter tength of at
feast 25 characters This showid consist
of rubout or null punches {letter key
for Telex tapes).
d. Between word fields, comments not
containing 8's or F's may be inserted.
{Carriage return and line feed characters
should be inserted as a comment”)
Clary Foalg Ea
Y
'
BNPNPPPNNF
L Jd
just before each word field (or at least
between every four word fields), When
these carriage returns, etc, are inserte.
the tape may be easily listed gn the
teletype for purposes ef errar check-
ing, The customer may also find и
helpful to insert the word number Las
a comment] at least every four word
fields.
e. Included in the tape before 178
leader should be the customer's corm
plete Telex or TWX number and,
more than one pattern is being trans
rmitted, the ROM pattern number.
f. MSB and LSB are the most and leas!
significant bit of the device outputs
Refer to the data sheet for the pl"
numbers,
"58
Trager А дну Kay Ta Tes apa Leti
wey lod TEE la Eati 46 Irampeyl
Word Field D
Т
Ward Foedd 1
5-80
Word Feel 1073
intel Silicon Gate MOS ROM 8316A
16,384 BIT STATIC MOS READ ONLY MEMORY
Organization—2048 Words x 8 Bits
Access Time-850 ns max
* Single +5 Volts Power Supply Voltage = Three-State Output — OR-Tie
» Directly TTL Compatible — All Inputs Capability
and Outputs * Fully Decoded — On Chip Address
» Low Power Dissipation of 31.4 „МУВИ Decode
Maximum
a inputs Protected — All Inputs Have
« Three Programmable Chip Select Protection Against Static Charge
Inputs for Easy Memory Expansion
The Intel
facing are
The inputs and outputs are fully TTL compatible. This device operates with a single +5V power supply. The
three chip select inputs are programmable. Any combination of active high or low {evel chip select inputs can be
defined and the desired chip select code is fixed during the masking process. These three programmable chip
important design objectives.
select inputs, as well as OR-tie compatibility on the outputs, facilitate easy memory expansion.
The 8316A read only memory is fabricated with N-channel silicon gate technology. This technology provides the
designer with high performance, easy-to-use MOS circuits. Qnty a single +5V power supply 5 needed and all
devices are directly TTL compatible.
PIN CONFIGURATION BLOCK DIAGRAM
Pi JE 3, E Ta О, cl {y il, 9,
' a ; - °
sao,
Jo,
La,
2000,
19 ] 9,
190,
Hi Jo,
eo,
= es, A,
AD '4 Js,
GND CJ 7 ‘3 с®,
Q Vor
ll} GML
в BF >
wow
TA
1. PUT BUFFEAS DECODE
a
F
wh En hat RJ
ыы
2
“VESOGER OF TE +
BI16A
CHIP
SFAECT
PHO
BEF в >
O E
E
de
CLA LR
+
pur)
wr
CITE HLT Ri
1
TT "
CHIP
SELECT
INPUT
HUFFERS
DH
PIN NAMES
Ap Ao | ACORÉSS INFUTS
O, Sa
CÉTS OUITPUTS
C5, C5, | PROGRAMMABLE CHIP SELECT INFUTS
5461
B31GA 15 a 16,384-bit static MOS read only memory organized as 2048 words by 8 bits. This ROM is
designed for microcomputer memory applications where fugh performance, large bit storage, and simple inter-
SILICON GATE MOS ROM 8316A
ABSOLUTE MAXIMUM RATINGS"
Ambient Temperature Under Bias a , 0% to 70°C *COMMENT: Stresses above those bisted under ‘ Acsclute Maximum
Storage Temperature . ... ........... -65°C to +180°C
Voltage On Any Pin With Respect
Te Ground
Power Dissipation
-0.5Y to +7
1.0 Watt
Ratings” may cause permarent damagé to (Mé dév.ce. This asa stress
rating ony and luncrónal operation of the dev ce at these or any
other conditions above those indicated in the operatiônal séctions of
this spécification 15 not Imp'ed. Exposuré 10 aBso.u te Maximum rating
CONGITIONS tor extended periods may affect Семее "в. аб Ну.
D.C. AND OPERATING CHARACTERISTICS
Та = О°С то «70°C, Vee = 5 =5% unless otherwise spac ed
LIMITS |
: I | UNIT TEST CONDITIONS
SYMBOL | FARAMETER MIN. . TYPi!! ! MAX
NL Input Load Current 10 ЦА Y =010525Y
{All Input Pins)
| oH Dutput Leakage Current i 10 HA CS = 2.2%, Vout =4.0V
ILOL Qutput Leakage Current -20 EA C8 =2.2V, Vout = 0.45V
tre Power Supply Current — 40 aß mA Al inputs 5.25Y Data Out Open
VL Input ‘Low Voltage —0.5 | 0.8 \
Y 1H Input “High” Voltage 2.0 Yeg+1.0V \
Ya Output ‘Low Voltagé 0.45 \ lot = 2.0 mA
VOH | Qutput "High" Voltage | 2.2 | Y юн =-1004A |
11 Typ cal values for Ta - 2575 and nominal supply voltage.
A.C. CHARACTERISTICS
Ta = 0°C to +70°C, Vec = +5V +5% unless otherwise spec: fied
| LIMITS |
UNIT
SYMBOL PARAMETER MIN. typ | МАХ.
ta Address to Output Delay Time 400 350 nS |
Les Chip Select to Output Enable Delay Time 300 nS |
| OF Chip Deselect to Output Data Float Delay Time 0 | 300 ng |
CONDITIONS OF TEST FOR CAPACITANCE? T, = 25°C, 1 = 1 MHz
A.C. CHARACTERISTICS
| |
Output Load ... 1 TTL Gate, and Cy gap = 100 oF SYMBOL | TEST LiMiTs
Input Pulse Levels . _...... DB to 2 0V ТУР, МАХ.
Input Pulse Rise and Fall Times (10% 10 90%) 20 nS - —
Timing Measurement Reference Level CN All Pins Except Pin Under | a nF 10 pF
Input aaa 1.9V Test Tied 10 AC Ground :
Output... ........... о 4 | | | | с
MER D.45V го 2,2V CouT All Pins Except Pin Under ВЕР 15 pF
| Test Tied to AC Groung —
121 This parameter is periodically sampled and is not 100% tasted.
562
SILICON GATE MOS ROM 8316A
WAVEFORMS
ADDRESS X X
| —-— Lg — —- 10 р — — —=-
—
PROGRAMMABLE Xx X
CHIF SELECTS
À
a — TA
y a , >
MMT
TP ПО , QUTEUT HIGH 7
DUTPET A a И IMPEDANCE / 7 y 1 7 OUTPUT VALID
FE # FE i Air 7
мо, ELE ПИ A
16K ROM PROTOTYPING
ROM systems may be developed and programs may be verified using Intel's 170724 or 2708 PROMs,
5-63
ИИ
7
SILICON GATE MOS ROM 8316A
TYPICAL D.C. CHARACTERISTICS
14 Inf)
TI
25
20
Igy rl
TL
EDO
ACCESS TIME VS. AMBIENT
TEMPERATURE
red
|
LT WORST CASE
arr
ge TYPICAL
OUTPUT SINK CURRENT VA.
OUTPUT VOLTAGE
“ор ОСТ
ACCESS TIME YS. LOAD
CAPACITANCE
La MORET CASE
I
1
a
ТУРА
щен |
1
17 200 300 400 EOL
CLOAQ ‘erdi
Vin УСТ
dgyp4 der]
leg (ma
Vin LIMITS VS. TEMPERATURE
1.8 я _
| ! . | |
1 ‘ | |
| TYPICAL |
IE : | rn A
N —— , У НН АТ;
Ya ; ;
| |
| | “co 7 adv
|
1 | 1 ' .
1.0 nl 1
1 10 Hl AG a) Sl) EL iz
Ta Cl
QUTPUT SOURCE CURRENT VS.
OUTPUT VOLTAGE
-3G T T
п —]
: ;
-75 N 1
æ À |
\ TYPICAL | i
15 4 N i
N OT
-19 я
Ne 25€ 0 |
“CL #.-N 1 |
E *
| N |
1
i ] ]
0 ! i 3
ga !YOLTS1
STATIC Ipc VE. AMBIENT TEMPERATURE
НЮ
WORST CASE
Bo
NU
ED
Ус вм |
ALL ADDRESSES TIED 1
ТО Мес
CHIP DESELECTEDO 1
20 40 6 BD
ТА СС!
intel
MCS™
CUSTOM ROM
ORDER FORM
8316A
ROM
CUSTOMER —
Р.О. NUMBER
DATE_. —
Far Intel use only
== О РРРР
SD ZZ.
. — DD nn.
APP_. ‘ - DATE
All custom B316A ROM orders must be submitted on this form. Programming information should be sent in the form of computer
punched cards or punched paper tape per the formats designated on this order form. Additional forms are available from Intel.
MARKING
The marking as shown at the right must contain the Intel logo, the
product type [PS316A), the 4-digit intel pattern number (PPPP), a date
code (XXX XX), and the 2-digit chip number DD). An optional customer
identification number may be supstituted for the chip number (27),
[INTEL PATTERN NUMBER
EB 23164 PPPP
XXXX ZZ
LS
mass
Optional Customer Number (maximum 9 enaracters or spaces),
CUSTOMER NUMBER
DATE CODE
|
L CHIP NUMBER OR
CUSTOMER NUMBER
MASK OPTION SPECIFICATIONS
A. CHIP NUMBER (Must be
specifred—any number from О through
1-00}.
The chip number will be coded in
terms of positive logic where a logic
“1 is a high level input.
Chip
Number Cs3 C52
0
a
—
“NN PWR =
= ©) == E 5] = са
B. ROM Truth Table Format
Programming information should be
sent in the form of computer punched
cards or punched paper tape. In either
case, a printout of the truth table
should be accompanied with the order.
The following general format is applic-
able to the programming information
sent to intel:
e Data fields should be ordered begin-
ning with the least significant address
{0000} and ending with the most sig-
nificant address (2047),
* A data field should start with the
Most significant bit and end with tha
least significant bit.
5-65
® The data field should consist of P's
and N's. A P is to indicate a high level
output {most positivel and an N a low
level output (most negative. In terms
of positive logic, a P is defined as a
logic “17 and an N is defined as a logic
OC, If the programming information
is sent ón a punched paper tape, than
a start character, B, and an end charac:
ter, F, must be used in the data field,
1. Punched Card Format
An BO-column Holierith card {prefer
ably interpreted} punched by an IBM
026 or 029 keypunch should be sub
mitted. The first card will be a title
card; the format is as follows:
MCS™ CUSTOM ROM ORDER FORM
a. Title Card
OO OF OUTPUTS
dr A
TITEE CARD '
DESIGHATION CLSTQMERS ITE 25 SEAL MUMBEH
: LEE
- CO OMER 15M OR 6 I ‚ ,
СА ТИМО TRE
СОМРАМУ ЧАМЕ LOCATION CUSTOMERS PIN | ! .. т
4 x = STH TABLE MW WVBES
[ 1 I rm —
: FE ot. a "gi BE WL, IA iG ™
“IE I I E ETE NAL ‘
1 1 EI I Il i I
DE ` AUT DEAL 41: A gl
"1514 Med wh Ee] HN TE
LE. pape" „11 e an SB OT aa
ALTE ES III ELL API IE Isa
Briar: adi Ps
RT SRI hn ble he hE a
111. Yip Tagg tilt
An rd LL HE Tn TR rd Rp LH Hs Ema
int FE hob iach iv ERA hand:
ERE ERASER hh ERAN EAP Nov
EAGLE
JA at
Column Data
1 Punch aT
2—5 Blank
5-30 Customer Company Name
41-34 Blank
35-54 Customer's Company Division or location
55-57 Blank
58—66 Customer Part Number
67 Blank
68-75 Punch the intel 4-digit basic part number
and in { | the number of output hits,
e.g. 9316A[8}.
BE a k6htbisiababkoektELIa tE hF RECAER ECtR dE airada EEndbakrswtehk #6—78 Blank . .
Er ve iii iti CE 79-89 Punch a Z-digrt decimal number to »den-
LE ELA LEE RRE LL RE A > | PEO tify the truth table number {mask
Guerra és Eee programmed chip select number).
\ Rs 1 = rrr irr om ou. . J
b. For a 2048 word X B-bit organiza
tion only, cards 2 and the following Column Data
d hould 4 1-5 Punch the S-digit decimal equivalent of
cards should be punched as shown, the binary coded location which be-
gins each card. The address is right
justified, i.e., ODA A008, 0016,
hs a , LSB ete,
DECIMAL WORD QuUTPUTRi — STARS М! GECIMAL HO MEER 6 Blank
AGORESS BEGIMNM ING IA CACA Ti THE '
EACH CARD AGATA FIELDS TRUTH TABLE NUMBER a Dar Field
- 1 4 1 lank
Fab Aal-ralira TR ER r-iaÉ Вкл бобов Е тара тов Гар ÉL prat PR ER ya Etapa dE [tab we lpr a % 16-23 Data Field
33 Blank
SLABRAAN KANNE GESNNEON ANDRANAN DUNOEUES CUSEEZER EUFEMENE FANONONE 3441 Data Field
HME. DeiariacióN LEE TILIA: ree RAE ELA LE EEL EI SEL RES ei 42 Blank
INTERESSE Da Er 44-50 Data Fietd
UC TT E E E Lo 61 Blank
PLL] RIA PIE EL aa Ea PER is 52-59 Sata Field
EVER EAU EPP EE PEER IIA IAEA ELA ia Ia! 50 Blank
85:40 0a DANNA: OEE os. DU 0656 00D6 0: HOPE: 233 UD: SPUR: Ne: NES 51-68 Data Field
LECF-L Fabia ira E Le" cel hn makes at ltrs kre tL md hi Lee ro ee 69 Blank
CES VO OUR Ieee ae UNE: 000 00 MEN 70-17 Data Field
BB Babk!® - 107-111 pipe: mA hu EURE Pm msmme gee neo 8 Blank
AA PARKER eee. 73-80 Punch same Z-digit decimal number asar,
a. J title card,
2. Paper Tape Format
17 wide paper tape using 7- or B-bit
ASCIL code, such as a model 33 ASR
teletype produces, or the 11/16" wide
paper tape using a 5-hit Baudot code,
such as a Telex produces.
The format requirements are as fol-
lows:
a. All word fields are to be punched in
consecutive order, starting with word
field Q {all addresses low), There must
be exactly 2048 word fields for the
2043 X 8 ROM organization,
b. Each ward field must begin with
the start character B and end with the
stop character F, There must be ex-
actly 8 data characters between the B
and F.
Slait Charscier ——
Leader. Avbgut Eder lor TW and Larter
Kay tor Telas Lar lenst 25 Iramest.
Warg Fpl 0
Sino Characis
Li
EPPPNANNNFENNNANNNPPF
NO OTHER CHARACTERS, SUCH
AS RUBOUTS, ARE ALLOWED ANY.
WHERE IN AWORD FIELD. If in pre-
paring a tape an error is made, the en-
tire word field, including the B and F,
must be rubbed out. Within the word
field, a P results in a high level output
and an M results in ¿low level output.
¢. Preceding the first word field and
following the last ward field, there
must be à igader/tracer length of at
least 25 characters. This showld consist
of rubout or null punches fletter key
far Telex tapes).
d. Between word fields, comments not
containing 8's or F's may be inserted.
Carriage return and line feed characters
should be inserted as a comment’)
Qua Fred EB
ne ee —— a
Vire Fila 1
5-68
¥
BNPNPPPNNF
just before each word field tor at least
between avery four word fields). When
these carriage returns, ete. are inserted,
the tape may be easily listed on the
teletype for purposes of error check-
ing. Fhe customer may also find it
helpful to insert the word number las
a comment] at least every four word
fields.
e. Included in the tape before the
leader should be the customers com-
plate Telex or TWX number and,
mora than one pattern 15 being trans
mirted, the ROM pattern number.
f. MSB and LSB are the most and least
significant bit of the device outputs
Refer to the data sheet for the pi”
numbers,
LSB
Trader Huobiowl Edy Tor TWEE gag Leti?
ew hor Tema (at leasy 2% ramps!
word Field ae
RAMs
8102-2 5101
G102A- 8210
8107B - 8222
; DOTES IO TORRE PAR TRIE ST en a ,
y . epa Y E . Ex - -
- Me Tar
- = бд _ ‘ . : de
BR A
" г > e RB
SIETE cLOCK 8724: TT te DNA
AND OMIZER О ДОР ро. A.
ы — I. a e."
SYNC #2 - 61 - RESET - ,
TL Lima te ee - HIT in
ROY ‚ RÉÉGACPE : IT" a. a ЗО
WI 0007 DAIN HLDA aoû18 | ; |
a " 1 [
] 1
ee a mwa
#228: DO hy 8212 . ADDRESS 87074 EI 8101-72 810204
SYSTEM: | Pagos - OUEFERE/ | E704 ROMs — 830€ 8111-2 MAMI
CONTROLLER - tl | DÉCODER | 8708 IA , B21D
- BN [OPTIONAL | | В -. 831 #1028 5101 8222
UT 17 GT
UE DATA BUS (9) +.
Lo CONTROL BUS (8) - es
EE ADDRESS SUS 116} : Es
. 11 | 629 Ho ol 8212 wo | EL
; ; COMMUNICATION - 3755 FER!PHEMAL — => amy ary ‚
Es Y INTERFACE © © |. INTERFACÉ Las EE :
- - 3 N > " . ЖЕ - 534 7
| E ie - ME.
NE e IU mo г.
intel Silicon Gate MOS 8101-2
1024 BIT (256 x 4) STATIC MOS RAM
WITH SEPARATE 1/0
a 256 x 4 Organization to Meet Needs = Inputs Protected — All Inputs Have
for Small System Memories Protection Against Static Charge
= Access Time — B50 nsec Max. a Low Cost Packaging — 22 Pin Plastic
» Single +5V Supply Voltage Dual-in-Line Configuration
1 Directliy TTL Compatible — All inputs a Low Power — Typically 150 mW
and Output » Three-State Output — OR-Tie
= Static MOS — No Clocks or Capability
Refreshing Required
« Simple Memory Expansion — Chip
Enable Input
a Output Disable Provided for Ease of
Use in Common Data Bus Systems
®
The Intel 8101-2 is a 256 word by 4 bit static random access memory element using normally off N-channel
MOS devices integrated ona monolithicarray. |t uses fully DC stable static) circuitry and therefore requires
no clocks or refreshing to operate. The data is read out nondestructively and has the same polarity as the
Input data.
The 8101-2 is designed for memory applications where high performance, low cost, large bit storage, and sim-
ple interfacing are important design objectives.
tt is directly TTL compatible in all respects: inputs, outputs, and a single +5V supply. Two chip-enables
allow easy selection of an individual package when outputs are OR-tied. An output disable is provided so that
data inputs and outputs can be tied for common 1/0 systems. Qutput disable is then used to eliminate any
bidirectional logic.
E
The Intel 3101-2 is fabricated with N-channel silicon gate technology. This technology aliows the design and
production of high perfarrrance, easy-to-use MOS circuits and provides a higher functional density on a mon-
olithic chip than either conventional MOS technology or P-channel silicon gate technology.
Intel's silicon gate technology also provides excellent protection against contamination. This permits the use
of low cost silicone packaging.
PIN CONFIGURATION LOGIC SYMBOL BLOCK DIAGRAM
pea Je"
Ay - 1 22 vec — à, DE
Az СД 8 nl Ta — A, co, — 8 27
Ас - a
4: efes A © | Jen m
_ — А, DO; ----- oo - r | 5 м
A, a 19 [1 Cin A on > ACI CELL ARRAY GND
— "+ 1 a; — DE seecr 27 POWS
A 5 18 [— oo — a po; E T 37 COLUMNS
B101-2 8101-2 y by I
ae 17 [7] се — * oo LC 2h | —
— à, ‚ | да ===
a, | 18 [—] co, В T T
GND Cc a 15 Hoi, on Fi — LF COLUMN LD CIRCUITS
= — x
DI 9 14 DO 1 —
y |] оо, ARE INPUT " 00
Di, -— LA Y Data 1
po, [] 10 13 Jo, ai CONTAOL =
Di, 11 17 De = à DO 7
С Ho AM CEZ CEN
T 1
a [HJ
PIN NAMES -
Эл DATA INPUT Do OUTPUT DISABLE Cos PIN NUMBERS
A,-A ADDRESS INPUTS dr DATA OUTPUT
RAW AEADMWRITE INPUT L.. POWER Iv) |
FET CEZ” CHIP ENABLE
SILICON GATE MOS 8101-2
Absolute Maximum Ratings”
Ambient Temperature Under Bias. ..... OC to 70% C
Storage Temperature ........... -65°С то +150° С
Voltage On Any Pin
With Respect to Ground . ........ —0.5 Y to +7Y
Power Dissipation ............ ee 1 Watt
"COMMENT.
Stresses above those fisted under "Absolute Maximum
Rating may cause permanent damage to the device. This
fs 8 stress rating only and Functional operation of the de
vice at these or at any other condition above those indi-
cated in the operational sections of this specification 15
nor implied. Exposure to absolute maximum rating con-
dittons for extended periods may affect device reliability.
D.C. and Operating Characteristics
Ta = 0°C to 70%, Yee = 5Y +5% unless otherwise specified.
Symbol | Parameter Min. Тур!!! Мах Unit Test Conditions
IL Input Current 10 UA Vin = Oto 5.25V
сон 1/0 Leakage Current (2] 15 HA | СЕ = 2.2\, Моот = 4.0V :
LoL 1/0 Leakage Current? -50 UA CE = 2.2V, VouT = 0.45V |
loci Power Supply Current 30 50 MA Vin = 5.25Y, lo = ОтА
Ta = 25°C
lec: Power Supply Current 70 | má Vin = 5.25Y, lg = OmA
Ta =0"C
VIL Input “Low' Voltage -05 +065 V 1
YH Input “High” Yoltage 2.2 Vee Y
VoL Output “Low” Voltage +045. Y lo, = 2.0mA
‘ Von ; Output “High” Voltage 2.2 | \ Гон = -150 нА
NOTE: 1. Typical values are for Ta = 25" C and nominal supply voitage.
2. Input and Output tied together.
OUTPUT SOURCE CURRENT VS.
QUTPUT VOLTAGE
- AMBIENT TEMPERATURE
GC
‚25 С
1
‚зас i !
"mal
"rH
Wer - 4 754
QLITPUT MICH TY PIC AL
Мон : VOLTS
5-58
OUTPUT SINK CURRENT VS,
OUTPUT VOLTAGE
AMBIENT TEMPERATURE -
"5
lg, (mAl
i
L . van =~ i THY
CUTPUT "LGW" TYPICAL
. 1
a oa 10 1.5
Vo, 'OLTSI
SILICON GATE MOS 8101-2
A.C. Characteristics
READ CYCLE Ta =0°C to 70°C, Ver = BV 25% unless otherwise specified.
Symbol Parameter | Min. Typ. Max. Unit Test Conditions
tec Read Cycle i B50 ns
ta Access Time | 850 ns
‘со Chip Enable To Output | 650 ns [See below)
top Output Disable To Cutput 550 ns
to] - Data Qutputto High Z State 0 200 ns
ton Previous Data Read Vaud 0 ms
after change of Address
WRITE CYCLE
Symbol | Parameter Min. Typ. Max Unit Test Conditions
wey | Write Cycle 850 ns
ТАМу Write Delay 150 ns
tow Chip Enable To Write 750 ns
(See below!
tow Data Setup 500 ns
‘он Data Hole 100 rs
twe Write Pulse 630 ns
wr Write Recovery 50 ne
A.C. CONDITIONS OF TEST
Capacitance 7, = 25°C, {= 1MHz
A
Input Pulse Levels: +085 Volt to 2.2 Volt Limits {pF}
Symbol Test
Input Pulse Rise and Fall Times: Z0nsec Typ. | Max.
Timing Measurement Reference Level: 1,5 Volt Cin Input Capacitance Га 8
О | VTTLG 100 nF (AN Input Pins) Vin = OV !
tout : ‚ = .
uteut Load TL Gate ana Cy Р CouT Output Capacitance Vour = OV 8 12
Waveforms
READ CYCLE WRITE CYCLE Г?!
laca .— “el la-——.-. бару - _ ri
ADDRESS X ADDRESS X X
— - "co — i To low a 7 |
— — |
CE | FE !
\ A | / |
| `
CE? Y \ CEZ f 4 |
— pa Lon — :
¡COMMON 110) 3 ee ” Lou = — Bo /
\ = A |
log — la e “lor TT | |- == | бон —— |
pata те X DAT à GUT I DATA DATA IN
QUT i VALID IN STABLE
= = + TT == = - low Ч
ня) бала Бе -— Lua
IR ———— Lup |
NOTES: 1. [OE 15 With respect to the trading edge of CET CEZ, or OD, whichevar occurs first.
éd During the write cycle, OÙ is à 'ogical 1 tor common 10 and ''don'tcare”' for separate LC operation,
3. OD should be tied cuy Tor separate (iQ operaron,
intel Silicon Gate MOS 8111-2
1024 BIT (256 x 4) STATIC MOS RAM
WITH COMMON 1/0 AND OUTPUT DISABLE
= Organization 256 Words by 4 Bits * Fully Decoded — On Chip Address
* Access Time — 850 nsec Max. Decode
« Common Data Input and Output * Inputs Protected — All Inputs Have
» Single +5V Supply Voltage Protection Against Static Charge
= Directly TTL Compatible — All Inputs « Low Cost Packaging — 18 Pin Plastic
and Output Dual-In-Line Configuration
mn Static MOS — No Clocks or a Low Power — Typicaily 150 mW
Refreshing Required " Three-State Output — OR-Tie
= Simple Memory Expansion — Chip Capability
Enable Input
The intel"8111-2 is a 256 word by 4 bit static random access memory element using normally off N-channel
MOS devices integrated on a monolithic array. It uses fully DC stable (static! circuitry and therefore requires
no clocks or refreshing to operate. The data is read out nondestructively and has the same polarity as the
input data. Common input/output pins are provided.
The 8111-2 is designed for memory applications in small systems where high performance, low cost, large bit
storage, and simple interfacing are important design objectives.
It is directly TTL compatible in all respects: inputs, outputs, and a single +5V supply. Separate chip enable
(CE) leads allow easy selection of an individual package when outputs are OR tied,
The Intel*8111-2 is fabricated with N-channel silicon gate technology. This technology allows the design and
production of high performance, easy-to-use MOS circuits and provides a higher functional density on a mon-
olithic chip than either conventional MOS technology or P-channel silicon gate technology.
Intei’s silicon gate technology also provides excellent protection against contamination. This permits the use
of low cost silicone packaging.
PIN CONFIGURATION LOGIC SYMBOL BLOCK DIAGRAM
BE"
I 1 15 vec A —
—— Q 4
An — | is
a: Ï 47 ay А, LG, Я || —a Мос
a. 5 A ©.
Ay J 16 rw — 5 1:53, ps ES ADN MEMORY ARRAY MD 1
7 LE etc $7 AOWS ;
an] «sf CE, A 10 т 32 COLUMNS
"4 Ir = Bg
as [1s 8191.2 40. La vo, fn agi pe и
ase E — 14, 8111-2 dé y
av} COLUMN CG CIRCUITS :
a? zl ro; — #5 an — Co -
1 == ле 1
. 17 INPUT oa ! i
сме [в io Ja, 0) A Y nara А А E В
EF CONTADL —
aos 10 [ JcE, RW CE, CE, | © me Si © © |
PY DE "A |
ще |
]
— |.
PIN NAMES i
¡_AyAr — ADDRESS INFUTS a > Вер =
Fa OUTPUT DISABLE TA |
| AM READMAITE INPUT — L,
Г CE, CHIP ENABLE Y (J FIV NUMBERS
CE CHIP ENABLE 2
TROL: 1704 DATA INPUTQUTPUT
5-71
SILICON GATE MOS 8111-2
Absolute Maximum Ratings*
Ambient Temperature Under Bias..,.... OC ta 70%
Storage Temperature , ......... ‚ -65°С to +150°C
Voltage On Any Pin
with Respect to Ground ........ ‚ -0.5V to +7V
Power Dissipation ... 21100101 44 uu... 1 Watt
“COMMENT:
Stresses above those listed under “Absolute Maximum
Rating” may cause permanent damage ro the device, This
is 8 stress rating onfy and functional operation of the de-
vice at these or at any other condition above those indi-
cated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating con-
ditions for ex tended periods may affect device reliability.
D.C. and Operating Characteristics
Ta = 0°Cto 70°C, Vec = 5V 25% | unless otherwise specified.
Symbol Parameter Min. | Typ. (11| Max. Unit Teast Conditions
Nu Input Load Current 10 ЦА Vin = O to 5,25 \
Пон 1/0 Leakage Current 1.18 НА СЕ = 2.2\, Мо = 4.0V
LOL 1/0 Leakage Current i -50 ph | CE=2.2V,V,0=0.45V
сел Power Supply Current 30 60 mA Vin = 5.25V
Io = OmA, T, = 25°C
сс? - Power Supply Current 70 mA | Vin = 5.25V
| ho = Imá, Ta = 0%
Y IL Input Low Voltage -0.5 +0.65 \
Vin Input High Voltage 2.2 Y ec Y |
Мет Output Low Valtage 0.45 Y lo. = 2.0mA a
Von | Output High Voltage 2.2 Y юн = -150 дА
NOTES. 1. Typical values are for Tp = 25°C and nomunat supply voltage.
OUTPUT SOURCE CURRENT VS.
OUTPUT VOLTAGE
| AMBIENT TEMPERATURE
oc
sc
OE
laa IA
|
Vie : a TY
EUTPQT "HIGH" TYPICAL
i i a
Vox (VOLTSI
OUTPUT SINK CURRENT VS.
DUTPUT VOLTAGE
AMBIENT TEMFERATLINE =
15
TOPE |
Igy [mal
5 Yer = 4. THY
QUTPUT ‘Li TYPICAL
? Us 10 16
Yo. 1YOL TS)
9-12
SILICON GATE MOS 8111-2
A.C. Characteristics
READ CYCLE T, =0°Cto 70°C, Vee = DV 15%, unless otherwise specified.
Symbol Parameter Min. Typ. Max. Unit Test Conditions
‘АСУ Read Cycle 850 ns
ta Access Time 850 ns
tco Chip Enable To Output 65D ns {See below)
tan Output Disable To Dutput 550 ns
tne [1] Data Output to High Z State 0 200 ns
ton Previous Data Read Valid ns
after change of Address
WRITE CYCLE
Symbol Parameter Min. Typ. Max. Unit Test Conditions
two Write Cycie 850 ns
ТАМ Write Delay 150 ns
Tow Chip Enable To Write 750 ns (See below)
tow Data Setup 500 ns
toH Data Hotd 100 ns
twp Write Pulse 630 ns
twa Write Recovery 50 ns
A. C. CONDITIONS OF TEST Capacitance 7, = 25°С, 1 = 1 МН:
Input Pulse Levels: +0.65 Volt to 2.2 Voit Limits {pF}
Symbol Test
Input Pulse Rise and Fall Times: 20nsec Typ. | Max.
Timing Measurement Reference Level: 1.5 Volt Cin Input Capacitance 4 8
(All Input Ping) Vy = OV
Output Load: 1TTL Gate and CL = 100pF Cour Output Capacitance Vout = OV 10 15
Waveforms
READ CYCLE WRITE CYCLE
tray — "== dre
|
ADDRESS X X
1
ENABLES CHIP
(EE, CED) / ENABLES
= top—+—
OUTPUT
QUTFUT ow el [== DISABLE
DISABLE
le. by——— —— = ' or ow
DATA 1/5 X Ата oT DATA 119 CABLE
READ
WRITE
NOTE: 1. tpg is with respect to the trailing edge of CET, CEZ, or OD, whichever occurs first,
>73
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