DRAM Design Guide For 5 Years Compliance

DRAM Design Guide
For
5+ Years Compliance
December 1999
Micron Confidential
DRAM Trends
RDRAM
Intel-based
high-end
PC
64Mb
EDO
December 1999
New
FPM/EDO
Design-ins
Micron Confidential
DRAM Design Guidelines
Options
Package
SSTL_2 512K x 32
December 1999
16 Meg x 8 32 Meg x 8
Clock (MHz)
Micron Confidential
December 1999
Micron Confidential
DRAM Design Guidelines
Options
Package
Clock (MHz)
• Medium to large memory arrays
tWR
= 2 clocks
• 512Mb uses same package/
pinout, per se
• 512Mb refresh - 64ms period
- tRFC = 1.6 x tRC
December 1999
• PC main memory chief user
•
54-pin
TSOP
NC on 64Mb
& 128Mb
Micron Confidential
DRAM Design Guidelines
Options
Package
Clock (MHz)
q 50 and/or 86 TSOP
• SDR (Single Data Rate)
• Minimum memory arrays
• PC graphics chief user
•
December 1999
= 2 clocks
2 Meg x 32 4 Meg x 32
50-pin
TSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18 NC on 64Mb/128Mb
19
20
21 NC on 64Mb
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
Micron Confidential
SDRAM Addressing
SDRAM Addressing
a
Row
Column
Row
Column
Column
54-pin TSOP (x4, x8, x16) and 86-pin TSOP (x32)
Refresh goes from 15.625µs per row to 7.8µs per row
Pin 36 goes from NC to A12
Pin 21 goes from NC to A11
Pin 69 goes from NC to A12
December 1999
Micron Confidential
Clock (MHz)
q 66 TSOP
• DDR (Double Data Rate)
provides data at 2x the
clock rate
• Medium to large memory
arrays
• Mainframe, servers,
workstations and routers
will be chief users
• tWR = 2.5 clocks
• 512Mb refresh
– 64ms period
– tRFC = 2 x tRC
December 1999
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19 -QFC#
20
21
22
23
24
NC on 64Mb
25
& 128Mb
26
27
28
29
30
31
32
33
66-pin
TSOP
Micron Confidential
DRAM Design Guidelines
Package
Clock (MHz)
Options
• DDR (Double Data Rate)
provides data at two times
the clock rate
• Minimum memory arrays
• High-end graphics and
routers will be chief users
tWR
= 2.5 clocks
100-pin
TQFP
10099 98 97 96 95 94 93 92 9190 89 88 87 86 8584 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
NC on 16Mb SGRAM,
23
58
64Mb and 128Mb SDRAM
24
57
25
56
LOW for non-SGRAM
26
55
27
54
NC on
NC on
A12
28
53
16Mb SGRAM
16Mb SGRAM
29
52
30
51
31 32 33 34 35 36 37 38 3940 41 42 43 44 45 4647 48 49 50
December 1999
Micron Confidential
DDR SDRAM Addressing
SDRAM Addressing
Row
Column
Row
Column
Row
Column
Row
Column
100-pin TQFP (x32), SGRAM only
66-pin TSOP (x4, x8, x16) and 100-pin TQFP (x32; SDRAM only with pin 52 = low)
Pin 42 goes from NC to A12
Pin 45 goes from NC to A9; pin 36 goes from NC to A10
Refresh goes from 15.625µs per row to 7.8µs per row
Addressing not finalized, pin 37 goes from NC to A11
Addressing not finalized, pin 44 goes from NC to A12
December 1999
Micron Confidential