2.12 Dr. Debug. ASROCK P55 PRO

Dr. Debug is used to provide code information, which makes troubleshooting even easier. Please see the diagrams below for reading the Dr. Debug codes.

The Bootblock initialization code sets up the chipset, memory and other components before system memory is available. The following table describes the type of checkpoints that may occur during the bootblock initialization portion of the

BIOS:

D4

D5

D6

D0

D2

D3

Checkpoint

Before D1

D1

D7

D8

D9

DA

Description

Early chipset initialization is done. Early super I/O initialization is done including RTC and keyboard controller. NMI is disabled.

Perform keyboard controller BAT test. Check if waking up from power management suspend state. Save power-on CPUID value in scratch

CMOS.

Go to flat mode with 4GB limit and GA20 enabled. Verify the bootblock checksum.

Disable CACHE before memory detection. Execute full memory sizing module. Verify that flat mode is enabled.

If memory sizing module not executed, start memory refresh and do memory sizing in Bootblock code. Do additional chipset initialization.

Re-enable CACHE. Verify that flat mode is enabled.

Test base 512KB memory. Adjust policies and cache first 8MB. Set stack.

Bootblock code is copied from ROM to lower system memory and control is given to it. BIOS now executes out of RAM.

Both key sequence and OEM specific method is checked to determine if

BIOS recovery is forced. Main BIOS checksum is tested. If BIOS recovery is necessary, control flows to checkpoint E0.

Restore CPUID value back into register. The Bootblock-Runtime interface module is moved to system memory and control is given to it. Determine whether to execute serial flash.

The Runtime module is uncompressed into memory. CPUID information is stored in memory.

Store the Uncompressed pointer for future use in PMM. Copying Main BIOS into memory. Leaves all RAM below 1MB Read-Write including E000 and

F000 shadow areas but closing SMRAM.

Restore CPUID value back into register. Give control to BIOS POST

(ExecutePOSTKernel).

05

06

C0

C1

C2

C5

C6

C7

0A

0B

0C

0E

13

24

30

2A

2C

2E

31

The POST code checkpoints are the largest set of checkpoints during the BIOS pre-boot process. The following table describes the type of checkpoints that may occur during the POST portion of the BIOS:

Checkpoint

03

04

08

Description

Disable NMI, Parity, video for EGA, and DMA controllers. Initialize BIOS,

POST, Runtime data area. Also initialize BIOS modules on POST entry and

GPNV area. Initialized CMOS as mentioned in the Kernel Variable

“wCMOSFlags.”

Check CMOS diagnostic byte to determine if battery power is OK and

CMOS checksum is OK. Verify CMOS checksum manually by reading storage area. If the CMOS checksum is bad, update CMOS with power-on default values and clear passwords. Initialize status register A.

Initializes data variables that are based on CMOS setup questions.

Initializes both the 8259 compatible PICs in the system

Initializes the interrupt controlling hardware (generally PIC) and interrupt vector table.

Do R/W test to CH-2 count reg. Initialize CH-0 as system timer. Install the

POSTINT1Ch handler. Enable IRQ-0 in PIC for system timer interrupt.

Traps INT1Ch vector to “POSTINT1ChHandlerBlock.”

Initializes the CPU. The BAT test is being done on KBC. Program the keyboard controller command byte is being done after Auto detection of

KB/MS using AMI KB-5.

Early CPU Init Start — Disable Cache - Init Local APIC

Set up boot strap proccessor Information

Set up boot strap proccessor for POST

Enumerate and set up application proccessors

Re-enable cache for boot strap proccessor

Early CPU Init Exit

Initializes the 8042 compatible Key Board Controller.

Detects the presence of PS/2 mouse.

Detects the presence of Keyboard in KBC port.

Testing and initialization of different Input Devices. Also, update the Kernel

Variables. Traps the INT09h vector, so that the POST INT09h handler gets control for IRQ1. Uncompress all available language, BIOS logo, and Silent logo modules.

Early POST initialization of chipset registers.

Uncompress and initialize any platform specific BIOS modules.

Initialize System Management Interrupt.

Initializes different devices through DIM.

See DIM Code Checkpoints section of document for more information.

Initializes different devices. Detects and initializes the video adapter installed in the system that have optional ROMs.

Initializes all the output devices.

Allocate memory for ADM module and uncompress it. Give control to ADM module for initialization. Initialize language and font modules for ADM.

Activate ADM module.

33

37

38

39

3A

3B

3C

40

50

52

85

87

8C

8D

60

75

78

7A

7C

84

8E

90

A0

A1

A2

A4

A7

A8

A9

AA

AB

AC

B1

00

Initializes the silent boot module. Set the window for displaying text information.

Displaying sign-on message, CPU information, setup key message, and any OEM specific information.

Initializes different devices through DIM.

Initializes DMAC-1 & DMAC-2.

Initialize RTC date/time.

Test for total memory installed in the system. Also, Check for DEL or ESC keys to limit memory test. Display total memory in the system.

Mid POST initialization of chipset registers.

Detect different devices (Parallel ports, serial ports, and coprocessor in

CPU, etc.) successfully installed in the system and update the BDA,

EBDA, etc.

Programming the memory hole or any kind of implementation that needs an adjustment in system RAM size if needed.

Updates CMOS memory size from memory found in memory test.

Allocates memory for Extended BIOS Data Area from base memory.

Initializes NUM-LOCK status and programs the KBD typematic rate.

Initialize Int-13 and prepare for IPL detection.

Initializes IPL devices controlled by BIOS and option ROMs.

Initializes remaining option ROMs.

Generate and write contents of ESCD in NVRam.

Log errors encountered during POST.

Display errors to the user and gets the user response for error.

Execute BIOS setup if needed / requested.

Late POST initialization of chipset registers.

Build ACPI tables (if ACPI is supported)

Program the peripheral parameters. Enable/Disable NMI as selected

Late POST initialization of system management interrupt.

Check boot password if installed.

Clean-up work needed before booting to OS.

Takes care of runtime image preparation for different BIOS modules. Fill the free area in F000h segment with 0FFh. Initializes the Microsoft IRQ

Routing Table. Prepares the runtime language module. Disables the system configuration display if needed.

Initialize runtime language module.

Displays the system configuration screen if enabled. Initialize the CPU’s before boot, which includes the programming of the MTRR’s.

Prepare CPU for OS boot including final MTRR values.

Wait for user input at config display if needed.

Uninstall POST INT1Ch vector and INT09h vector. Deinitializes the ADM module.

Prepare BBS for Int 19 boot.

End of POST initialization of chipset registers.

Save system context for ACPI.

Passes control to OS Loader (typically INT19h).