Specification Changes. Intel LF80537NF0411M, RH80532NC056256, LF80537NE0411M, LF80537NF0281MN, LF80537NF0481M, LF80537NE0361M, RH80536NC0251M

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Specification Changes

V1.

The Specification Changes listed in this section apply to the following documents:

• Mobile Intel ®

Celeron

®

Processor on .13 Micron Process in Micro-FCPGA Package Datasheet

(Document Number 251308)

All Specification Changes will be incorporated into a future version of the appropriate mobile Intel

Celeron processor on 0.13 micron process in Micro-FCPGA package documentation.

Context ID Feature Added to the CPUID Instruction Feature

Flags/IA32_MISC_Enable Registers

IA32_MISC_ENABLE register, bit 24 status has changed from Reserved to the following definition:

IA32_MISC_ENABLE – Miscellaneous Enables Register, bit # 24

MSR Address:

Default Value:

Access:

Type:

01A0h Accessed as a Qword

High Dword XXXX XXXXh

Low Dword XXXX XXXX XXXX XXXX XXXX XX00 X0X0 0001b

Read/Write

Shared

IA32_MISC_ENABLE is a 64-bit register accessed only when referenced as a Qword through a

RDMSR or WRMSR instruction.

Bit 24 of the IA32_MISC_ENABLE status has changed from Reserved to the following:

Bit Descriptions

24 L1 Data Cache Context Mode (R/W). When set to a ‘1’ this bit places the L1 Data Cache into shared mode. When set to a ‘0’ (default) this bit places the L1 Data Cache into adaptive mode.

When this bit is set to a ‘0’, adaptive mode, the Page Directory Base Register contained in CR3 must be identical across all logical processors.

Note: If the Context ID feature flag, ECX[10], is not set to a ‘1’ after executing the CPUID instruction with EAX = 1, then this feature is not supported and BIOS must not alter the contents of this bit location.

In the CPUID instruction function 1 feature information, bit 10 of ECX register (ECX[10]) has been assigned flag to identify “Context ID feature” . The status has changed from Reserved to the following:

ECX [Bits] Descriptions of Feature Flag Value

10 Context ID. A value of 1 indicates the L1 data cache mode can be set to either adaptive mode or shared mode. A value of 0 indicates this feature is not supported.

See definition of the IA32_MISC_ENABLE MSR Bit 24 (L1 Data Cache Context Mode) for more details.

Specification Update 37

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V2. BR0# Maximum Hold Time Specification Change

The BR0# maximum hold time has changed to 2 BCLKs. This change will be shown in the “System

Bus AC Specifications (Reset Conditions)” table and “System Bus Reset and Configuration Timings” figure of the Mobile Intel

®

Celeron

®

Processor on .13 Micron Process in Micro-FCPGA Package

Datasheet. This change will be incorporated in the next revision of the datasheet.

Currently it states:

Table 21. System Bus AC Specifications (Reset Conditions)

T# Parameter Min

T45: Reset Configuration Signals (A[31:3]#, BR0# INIT#, SMI#)

Setup Time

T46: Reset Configuration Signals (A[31:3]#, BR0# INIT#, SMI#)

Hold Time

NOTES:

1. Before the deassertion of RESET#.

2. After clock that deasserts RESET#.

Max Unit Figure Notes

2 20 2

It should state:

Table 21. System Bus AC Specifications (Reset Conditions)

Min Max Unit Figure Notes

T45: Reset Configuration Signals (A[31:3]#, BR0# INIT#,

SMI#) Setup Time

T46:Reset Configuration Signals (A[31:3]#,INIT#, SMI#)

Hold Time

T47: Reset Configuration Signal BR0# Hold Time

NOTES:

1. Before the deassertion of RESET#.

2. After clock that deasserts RESET#.

2 20 2

2 2 BCLKs 13 2

38 Specification Update

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The following figure will be modified to reflect this change:

Figure 12. System Bus Reset and Configuration Timings

BCLK

Reset

Configuration

A[31:3], SMI#,

INIT#

Configuration

BR0#

Tt

Tv

Tw

Valid

Valid

Tv = T13 (RESET# Pulse Width)

Tw = T45 (Reset Configuration Signals Setup Time)

Tx = T46 (Reset Configuration Signals A[31:3], SMI#, and INIT# Hold Time)

Ty = T47 (Reset Configuration signal BR0# Hold Time)

Ty

Tx

§

Specification Update 39