Introduction. Opal-RT OP5700

Introduction

INTRODUCTION

The OP5700 is a complete simulation system. It contains a powerful target computer, a high-end reconfigurable FPGA, signal conditioning for up to 256 I/O lines and 16 high-speed fiber-optic SFP ports. The design makes it easy to use with standard connectors (DB37, RJ45 and mini-BNC) without the need for input/output adaptors and allows quick connections for monitoring I/O signals. It is designed to be used either as a desktop, shelf top, or mounted in a standard 19’’ rack.

The front of the chassis provides access to monitoring interfaces and connectors and the SFP sockets, while the back of the chassis provides access to the target computer’s standard connectors, I/O connectors, power cable and main power switch.

Inside, the main housing is divided into two sections, each with a specific purpose:

Features

The lower part of the chassis contains the target computer that can be added to a network of simulators or can run standalone. The target computer, used to run simulations built with OPAL-RT’s RT-LAB or

HYPERSIM tools, includes the following features:

• ATX motherboard

• Linux-based real-time operating system

• Intel® Xeon® E5 CPU with 4, 8, 16 and 32 processor cores, up to 3.2GHz

• 10MB Cache Memory per 4 cores

• up to 32GB of DRAM,

• 512GB SSD disk,

• 6 PCIe slots 1 , used to connect the internal FPGA board and PCIe or PCI third party I/O and communication cards.

The upper section contains the FPGA and the I/O conditioning modules. The main features include:

• Xilinx® Virtex®7 FPGA programmable from the target computer via PCIe. The FPGA is used to execute models designed with the OPAL-RT RT-XSG tool, manage the I/O lines and execute embedded FPGA-based simulations. It exchanges data with the real-time simulations running on the target computer CPUs via the PCIe link.

• Flat carrier board capable of connecting any combination of up to 8 digital and analog conditioning modules. Each module controls 16 or 32 lines for a total of up to 256 I/0 lines.

• 16 SFP multi-mode fiber optic ports for high speed communication with other FPGA-based systems or with external devices.

1 The CPU configuration and the use of riser boards for PCI cards may limit the number of available slots, as described in the Hardware configuration section

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Introduction

The figure below illustrates the simulator architecture.

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Figure 1: OP5700 simulator architecture

The image shown above is used to illustrate the layered and flexible product architecture. Customers should not open the chassis unless under the strick guidance of Technical Support.

OPAL-RT Technologies OP5700 User Manual

Signal conditioning modules

Carrier Board

Upper section interfaces

Lower section target computer

Introduction

Configuration Options

The OP5700 is available in a number of CPU configurations that are factory configured according to the customer’s processing requirement.

Product

OP5707-4

OP5707-8

OP5707-16

OP5707-32

Configuration Description

OP5700 RCP/HIL Virtex7 FPGA-based Real-Time Simulator - 4 cores (5U, Xeon E5, 4 Cores, 3.0 GHz,

10M, 16GB, 512GB SSD)

OP5700 RCP/HIL Virtex7 FPGA-based Real-Time Simulator - 8 cores (5U, Xeon E5, 8 Cores, 3.2 GHz,

20M, 16GB, 512GB SSD)

OP5700 RCP/HIL Virtex7 FPGA-based Real-Time Simulator - 16 cores (5U, Xeon E5, 2x8 Cores, 3.2

GHz, 2x20M, 2x16GB, 512GB SSD)

OP5700 RCP/HIL Virtex7 FPGA-based Real-Time Simulator - 32 cores (5U, Xeon E5, 2x16 Cores, 2.3

GHz, 2x40M, 2x16GB, 512GB SSD)

The OP5700 is built with the same FPGA and I/O architecture as the OP5607 I/O expansion chassis (OP5600 family of products), therefore the FPGA programming files (bitstreams) are fully compatible.

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