CPU INTERRUPT PROCESSING. NXP 68HC05J5A, 68HC705J5A

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3.6.5 Carry/Borrow Bit (C-Bit)

The carry/borrow bit is set when a carry out of bit 7 of the accumulator occurred during the last arithmetic operation, logical operation, or data manipulation. The carry/borrow bit is also set or cleared during bit test and branch instructions and during shifts and rotates. This bit is neither set by an INC nor by a DEC instruction.

3-4

CENTRAL PROCESSING UNIT

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SECTION 4

INTERRUPTS

The MCU can be interrupted in six different ways:

• Non-maskable Software Interrupt Instruction (SWI)

• External Asynchronous Interrupt (IRQ)

• Optional External Interrupt via IRQ on PA0-PA3 (by a mask option)

• External Interrupt via IRQ on PA7

• Multi-Function Timer (MFT)

• 16-Bit Timer Interrupt (Timer1)

4.1

CPU INTERRUPT PROCESSING

Interrupts cause the processor to save register contents on the stack and to set the interrupt mask (I-bit) to prevent additional interrupts. Unlike RESET, hardware interrupts do not cause the current instruction execution to be halted, but are considered pending until the current instruction is complete.

If interrupts are not masked (I-bit in the CCR is clear) and the corresponding interrupt enable bit is set the processor will proceed with interrupt processing. Otherwise, the next instruction is fetched and executed. If an interrupt occurs the processor completes the current instruction, then stacks the current CPU register states, sets the I-bit to inhibit further interrupts, and finally checks the pending hardware interrupts. If more than one interrupt is pending following the stacking

operation, the interrupt with the highest vector location shown in Table 4-1 will be

serviced first. The SWI is executed the same as any other instruction, regardless of the I-bit state.

When an interrupt is to be processed the CPU fetches the address of the appropriate interrupt software service routine from the vector table at locations $0FF6

thru $0FFF as defined in Table 4-1.

Table 4-1. Vector Address for Interrupts and Reset

Register

N/A

N/A

ICSR

TCSR

TCSR

T1SR

Flag

Name

N/A

N/A

IRQF/IRQF1

TOF

RTIF

T1OF, ICF

Interrupts

Reset

Software

External Interrupt

MFT Overflow

Real Time Interrupt

Timer1 Interrupt

CPU

Interrupt

RESET

SWI

IRQ

MFT

MFT

TIMER1

Vector Address

$0FFE-$0FFF

$0FFC-$0FFD

$0FFA-$0FFB

$0FF8-$0FF9

$0FF8-$0FF9

$0FF6-$0FF7

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An RTI instruction is used to signify when the interrupt software service routine is completed. The RTI instruction causes the register contents to be recovered from the stack and normal processing to resume at the next instruction that was to be

executed when the interrupt took place. Figure 4-1 shows the sequence of events

that occur during interrupt processing.

From

RESET

Y

Is

I-Bit

Set?

N

IRQ

External

Interrupt?

N

TIMER

Internal

Interrupt?

N

Y

Y

Clear IRQ

Request

Latch if IRQE1 is cleared

Stack PC, X, A, CC

Fetch Next

Instruction

Set I-Bit in CCR

SWI

Instruction

?

N

RTI

Instruction

?

N

Execute

Instruction

Y

Y

Load PC From:

SWI: $0FFC, $0FFD

IRQ: $0FFA-$0FFB

TIMER: $0FF8-$0FF9

TIMER1: $0FF6-$0FF7

Restore Registers from stack

CC, A, X, PC

Figure 4-1. Interrupt Processing Flowchart

4.2

RESET INTERRUPT SEQUENCE

The RESET function is not in the strictest sense an interrupt; however, it is acted

upon in a similar manner as shown in Figure 4-1. A low level input on the RESET

pin or an internally generated RST signal causes the program to vector to its starting address which is specified by the contents of memory locations $0FFE and

$0FFF. The I-bit in the condition code register is also set.

4-2

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4.3

SOFTWARE INTERRUPT (SWI)

The SWI is an executable instruction and a non-maskable interrupt since it is executed regardless of the state of the I-bit in the CCR. As with any instruction, interrupts pending during the previous instruction will be serviced before the SWI opcode is fetched. The interrupt service routine address is specified by the contents of memory locations $0FFC and $0FFD.

4.4

HARDWARE INTERRUPTS

All hardware interrupts except RESET are maskable by the I-bit in the CCR. If the

I-bit is set, all hardware interrupts (internal and external) are disabled. Clearing the I-bit enables the hardware interrupts. There are two types of hardware interrupts which are explained in the following sections.

4.5

EXTERNAL INTERRUPT (IRQ)

The IRQ pin provides an asynchronous interrupt to the CPU. A block diagram of

the IRQ function is shown in Figure 4-2.

IRQ Pin

PA0

PA1

PA2

PA3

Mask Option

(Port A External Int.)

RST

IRQR

Mask Option

(IRQ Level)

IRQ Fetch Vector

IRQE1

IRQE

IRQE1

V

DD

IRQ

LATCH

R to BIH & BIL instruction sensing

IRQF to IRQ processing in CPU

PA7

RST

IRQR1

V

DD

IRQ1

LATCH

R

IRQF1

Figure 4-2. IRQ Function Block Diagram

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4-4

The IRQ pin is a source of IRQ interrupts and a mask option can also enable the other four lower Port A pins (PA0 thru PA3) to act as other IRQ interrupt sources.

The last source of IRQ interrupt comes from PA7 whenever there is a falling edge on PA7 and IRQE1 is enabled. There is no mask option associated with PA7 interrupt.

Refer to Figure 4-2 for the following descriptions. IRQ interrupt source comes

from IRQ and IRQ1 latches. The IRQ latch will be set on the falling edge of the

IRQ pin or on any rising edge of PA0-3 pins if PA0-3 interrupts have been enabled.

The IRQ1 latch will be set on the falling edge of PA7 if PA7 interrupt has been enabled. If "edge-only" sensitivity is chosen by a mask option, only the IRQ latch output can activate an IRQF flag which creates a request to the CPU to generate the IRQ interrupt sequence. This makes the IRQ interrupt sensitive to the following cases:

1.

Falling edge on the IRQ pin.

2.

Rising edge on any PA0-PA3 pin with IRQ enabled (via mask option).

If level sensitivity is chosen, the rising edge signal on the clock input of the IRQ latch can also activate an IRQF flag which creates an IRQ request to the CPU to generate the IRQ interrupt sequence. This makes the IRQ interrupt sensitive to the following cases:

1.

Low level on the IRQ pin.

2.

Falling edge on the IRQ pin.

3.

High level on any PA0- PA3 pin with IRQ enabled (via mask option).

4.

Rising edge on any PA0- PA3 pin with IRQ enabled (via mask option).

The IRQE enable bit controls whether an active IRQF flag can generate an IRQ interrupt sequence. This interrupt is serviced by the interrupt service routine located at the address specified by the contents of $0FFA and $0FFB.

The IRQ latch is automatically cleared by entering the interrupt service routine IF

IRQE1 enable bit is cleared. If IRQE1 enable bit is also set, the only way of clearing IRQF is by writing a logic one to the IRQR acknowledge bit. Writing a logic one to the IRQR acknowledge bit in the ICSR is the other way of clearing IRQF flag, regardless of the status of the IRQE1 bit, besides IRQ vector fetch. This conditional reset of IRQF flag provides a way for the user to differentiate the interrupt sources from IRQ and IRQ1 latches and also to make it J1A compatible if PA7 interrupt is not used. As long as the output state of the IRQF flag bit is active the

CPU will continuously re-enter the IRQ interrupt sequence until the active state is removed or the IRQE enable bit is cleared.

PA7 interrupt source, if enabled by IRQE1 enable bit, triggers IRQ interrupt on

PA7 falling edge only. The IRQ1 latch (IRQF1 flag) can ONLY be cleared by writing a logic one to the IRQR1 acknowledge bit in the ICSR. IRQ vector fetch can NOT clear IRQF1 flag. IRQ interrupt caused by PA7 falling edge also vectors to $0FFA and $0FFB.

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4.5.1 IRQ CONTROL/STATUS REGISTER (ICSR) $0A

The IRQ interrupt function is controlled by the ICSR located at $000A. All unused bits in the ICSR will read as logic zeros. The IRQF, IRQF1, IRQE1 bits are cleared and IRQE bit is set by reset.

7

R

ICSR

$000A

W reset

⇒

IRQE

1

6

IRQE1

0

5

0

0

4

0

R

0

3

IRQF

0

2

IRQF1

0

1

0

IRQR

0

0

0

IRQR1

0

RESERVED FOR TEST

R

UNIMPLEMENTED

Figure 4-3. IRQ Status & Control Register

IRQR 1 - PA7 Interrupt Acknowledge

The IRQR1 acknowledge bit clears an IRQ interrupt triggered by a falling edge on PA7 by clearing the IRQ1 latch. The IRQR1 acknowledge bit will always read as a logic zero.

1 = Writing a logic one to the IRQR1 acknowledge bit will clear the IRQ1 latch.

0 = Writing a logic zero to the IRQR1 acknowledge bit will have no effect on the IRQ1 latch.

IRQR - IRQ Interrupt Acknowledge

The IRQR acknowledge bit clears an IRQ interrupt by clearing the IRQ latch.

The IRQR acknowledge bit will always read as a logic zero.

1 = Writing a logic one to the IRQR acknowledge bit will clear the IRQ latch.

0 = Writing a logic zero to the IRQR acknowledge bit will have no effect on the IRQ latch.

IRQF1 - PA7 Interrupt Request Flag

Writing to the IRQF1 flag bit will have no effect on it. If the additional setting of

IRQF1 flag bit is not cleared in the IRQ service routine and the IRQE1 enable bit remains set the CPU will re-enter the IRQ interrupt sequence continuously until either the IRQF1 flag bit or the IRQE1 enable bit is cleared. The IRQF1 latch is cleared by reset.

1 = Indicates that an IRQ request triggered by a falling edge on PA7 is pending.

0 = Indicates that no IRQ request triggered by a falling edge on PA7 is pending. The IRQF1 flag bit can ONLY be cleared by writing a logic one to the IRQR1 acknowledge bit. Doing so before exiting the service routine will mask out additional occurrences of the IRQF1.

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IRQF - IRQ Interrupt Request Flag

Writing to the IRQF flag bit will have no effect on it. If the additional setting of IRQF flag bit is not cleared in the IRQ service routine and the IRQE enable bit remains set the CPU will re-enter the IRQ interrupt sequence continuously until either the

IRQF flag bit or the IRQE enable bit is clear. The IRQF latch is cleared by reset.

1 = Indicates that an IRQ request is pending.

0 = Indicates that no IRQ request triggered by pins PA0-3 or IRQ is pending. The IRQF flag bit is cleared once the IRQ vector is fetched

AND if IRQE1 is also cleared. If IRQE1 is set, then the only way of clearing IRQF flag is by writing a logic one to IRQR bit. The IRQF flag bit can be cleared, regardless of the status of the IRQE1 bit, by writing a logic one to the IRQR acknowledge bit to clear the IRQ latch and also conditioning the external IRQ sources to be inactive

(if the level sensitive interrupts are enabled via mask option). Doing so before exiting the service routine will mask out additional occurrences of the IRQF.

IRQE1 - PA7 Interrupt Enable

The IRQE1 bit enables/disables the IRQF1 flag bit to initiate an IRQ interrupt sequence.

1 = Enables IRQF1 interrupt, that is, the IRQF1 flag bit can generate an interrupt sequence. Execution of the STOP or WAIT instructions will leave the IRQE1 bit to be UNAFFECTED.

0 = The IRQF1 flag bit cannot generate an interrupt sequence. Reset clears the IRQE1 enable bit, thereby disabling PA7 interrupts.

IRQE - IRQ Interrupt Enable

The IRQE bit enables/disables the IRQF flag bit to initiate an IRQ interrupt sequence.

1 = Enables IRQF interrupt, that is, the IRQF flag bit can generate an interrupt sequence. Reset sets the IRQE enable bit, thereby enabling IRQ interrupts once the I-bit is cleared. Execution of the

STOP or WAIT instructions causes the IRQE bit to be set in order to allow the external IRQ to exit these modes.

0 = The IRQF flag bit cannot generate an interrupt sequence.

4.5.2 OPTIONAL EXTERNAL INTERRUPTS (PA0-PA3)

The IRQ interrupt can also be triggered by the inputs on the PA0 thru PA3 port pins if enabled by a single mask option. If enabled, the lower four bits of Port A can activate the IRQ interrupt function, and the interrupt operation will be the same as for inputs to the IRQ pin. This mask option of PA0-3 interrupt allow all of these input pins to be OR’ed with the input present on the IRQ pin. All PA0 thru

PA3 pins must be selected as a group as an additional IRQ interrupt. All the PA0-3 interrupt sources are also controlled by the IRQE enable bit.

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NOTE

The BIH and BIL instructions will only apply to the level on the IRQ pin itself, and not to the output of the logic OR function with the PA0 thru PA3 pins. The state of the individual Port A pins can be checked by reading the appropriate Port A pins as inputs.

NOTE

If enabled, the PA0 thru PA3 and PA7 pins will cause an IRQ interrupt regardless of whether these pins are configured as inputs or outputs.

4.5.3 TIMER INTERRUPT (MFT)

The TIMER interrupt is generated by the multi-function timer when either a timer

overflow or a real time interrupt has occurred as described in Section 8. The inter-

rupt flags and enable bits for the Timer interrupts are located in the Timer Control

& Status Register (TCSR) located at $0008. The I-bit in the CCR must be clear in order for the TIMER interrupt to be enabled. Either of these two interrupts will vector to the same interrupt service routine located at the address specified by the contents of memory locations $0FF8 and $0FF9.

4.5.4 TIMER1 INTERRUPT (16-BIT TIMER)

The Timer1 interrupt is generated by the 16-bit Timer when either a timer1 over-

flow or a input capture has occurred as described in Section 9. The interrupt flags

and enable bits for the Timer1 interrupt are located in the Timer1 Control & Status

Register (T1CR & T1SR) located at $0012, $0013. The I-bit in the CCR must be cleared in order to enable the Timer1. Either of these two interrupts will vector to the same interrupt service routine located at the address specified by the contents of memory locations $0FF6 and $0FF7.

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SECTION 5

RESETS

The MCU can be reset from five sources: one external input and four internal restart conditions.

• Initial power up of device (power on reset)

• A logic zero applied to the RESET pin (external reset)

• Timeout of the COP watchdog (COP reset)

• Low voltage applied to the device (LVR reset)

• Fetch of an opcode from an address not in the memory map (illegal address reset)

Figure 5-1 shows a block diagram of the reset sources and their interaction.

IRQ

RESET

OSC

Data

Address

V

DD

R

COP Watchdog

(COPR)

Address

V

DD

Illegal Address

(ILADR)

Power-On Reset

(POR)

To Interrupt logic

Mode

Select

LATCH

R

PH2

CPU

S

LATCH

RST

To other peripherals

REV 2.1

Low Voltage Reset

(LVR)

Figure 5-1. Reset Block Diagram

RESETS

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5.1

EXTERNAL RESET (RESET)

The RESET pin is the only external source of a reset. This pin is connected to a

Schmitt trigger input gate to provide an upper and lower threshold voltage separated by a minimum amount of hysteresis. This external reset occurs whenever the RESET pin is pulled below the lower threshold and remains in reset until the

RESET pin rises above the upper threshold. This active low input will generate the

RST signal and reset the CPU and peripherals. This pin is also an output pin whenever the LVR triggers an internal reset. Termination of the external RESET input or the internal COP Watchdog reset or LVR are the only reset sources that can alter the operating mode of the MCU.

NOTE

Activation of the RST signal is generally referred to as reset of the device, unless otherwise specified.

5.2

INTERNAL RESETS

The four internally generated resets are the initial power-on reset function, the

COP Watchdog Timer reset, the illegal address detector reset and the low voltage reset (LVR). Termination of the external RESET input or the internal COP Watchdog Timer or LVR are the only reset sources that can alter the operating mode of the MCU. The other internal resets will not have any effect on the mode of operation when their reset state ends.

5.2.1 POWER-ON RESET (POR)

The internal POR is generated on power-up to allow the clock oscillator to stabilize. The POR is strictly for power turn-on conditions and is not able to detect a drop in the power supply voltage (brown-out). There is an oscillator stabilizing delay after the oscillator becomes active. The delay time could be 224 or 4064 of internal processor bus clock cycles (PH2) which is a mask option.

The POR will generate the RST signal which will reset the CPU. If any other reset function is active at the end of this delay time, the RST signal will remain in the reset condition until the other reset condition(s) end.

5.2.2 COMPUTER OPERATING PROPERLY RESET (COPR)

The internal COPR reset is generated automatically (if the COP is enabled) by a time-out of the COP Watchdog Timer. This time-out occurs if the counter in the

COP Watchdog Timer is not reset (cleared) within a specific time by a software reset sequence. The COP Watchdog Timer can be disabled by a mask option.

Refer to Section 8.2 for more information on this time-out feature. COP reset also

forces the RESET pin low

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The COPR will generate the RST signal which will reset the CPU and other peripherals. Also, the COPR will establish the mode of operation based on the state of the IRQ pin at the time the COPR signal ends. If the voltage on the IRQ pin is at the V

TST level, the state of the PB0 pin during the last rising edge of the

RESET pin will determine which Test Mode (Internal or Expanded) the MCU will be in. If the voltage at the IRQ pin is in the normal operating range (V

SS

to V

DD

), the MCU will enter Single-Chip Mode when the COPR signal ends. If any other reset function is active at the end of the COPR reset signal, the RST signal will remain in the reset condition until the other reset condition(s) end.

5.2.3 LOW VOLTAGE RESET (LVR)

The internal LVR reset is generated when V

DD

falls below the specified LVR trigger value V

LVR

for at least one t

CYC

. In typical applications, the power supply decoupling circuit will eliminate negative-going voltage glitches of less than one t

CYC

. This reset will hold the MCU in the reset state until V

DD

rises above V

LVR

.

Whenever V

DD

is above V

LVR and below 4.5V, the MCU is guaranteed to operate although not within specification. The output from the LVR is connected directly to the internal reset circuitry and also forces the RESET pin low. The internal reset will be removed once the power supply voltage rises above V

LVR normal power-on-reset sequence occurs.

, at which time a

5.2.4 ILLEGAL ADDRESS RESET (ILADR)

The internal ILADR reset is generated when an instruction opcode fetch occurs from an address which is not implemented in the RAM ($0080 - $00FF) nor ROM

($0300-$0CFF, $0E00-$0FFF). The ILADR will generate the RST signal which will reset the CPU and other peripherals. If any other reset function is active at the end of the ILADR reset signal, the RST signal will remain in the reset condition until the other reset condition(s) end. Notice that ILADR also forces the RESET pin low.

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SECTION 6

LOW POWER MODES

There are three modes of operation that reduce power consumption:

• Stop mode

• Wait mode

• Halt mode

The WAIT and STOP instructions provide two power saving modes by stopping various internal modules and/or the on-chip oscillator. The STOP and WAIT instructions are not normally used if the COP Watchdog Timer is enabled. A mask option is provided to convert the STOP instruction to a HALT, which is a WAIT-like instruction that does not halt the COP Watchdog Timer but has a recovery delay.

The flow of the STOP, HALT, and WAIT modes are shown in Figure 6-1.

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STOP HALT WAIT

Stop

Conversion to

Halt?

N

Y

Stop External Oscillator,

Stop Internal Timer Clock,

Reset Startup Delay

External Oscillator Active and

Internal Timer Clock Active

Stop Internal Processor Clock,

Clear I-Bit in CCR, and set IRQE in ICSR

Stop Internal Processor Clock,

Clear I-Bit in CCR, and set IRQE in ICSR

External

RESET?

N

IRQ

External

Interrupt?

N

Y

External

RESET?

N

Y Y

IRQ

External

Interrupt?

N

Y Y

TIMER

Internal

Interrupt?

Restart External Oscillator, start Stabilization Delay

N

Y

End of Stabilization

Delay?

N

Y

Restart

Internal Processor Clock

COP

Internal

RESET?

N

External Oscillator Active and

Internal Timer Clock Active

Stop Internal Processor Clock,

Clear I-Bit in CCR, and set IRQE in ICSR

Y

Y

Y

Y

External

RESET?

N

IRQ

External

Interrupt?

N

TIMER

Internal

Interrupt?

N

COP

Internal

RESET?

N

1.

Fetch Reset Vector or

2.

Service Interrupt a.

Stack b.

Set I-Bit c.

Vector to Interrupt Routine

Figure 6-1. STOP/HALT/WAIT Flowcharts

6.1

STOP INSTRUCTION

The STOP instruction can result in one of two modes of operation depending on the STOP mask option chosen. One option is for the STOP instruction to operate like the STOP in normal MC68HC05 family members and place the device in the

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STOP Mode. The other option is for the STOP instruction to behave like a WAIT instruction (except that the restart time will involve a delay) and place the device in the HALT Mode.

6.1.1 STOP Mode

Execution of the STOP instruction in this mode (selected by a mask option) places the MCU in its lowest power consumption mode. In the STOP Mode the internal oscillator is turned off, halting all internal processing, including the COP Watchdog

Timer.

When the CPU enters STOP Mode the interrupt flags (TOF and RTIF) and the interrupt enable bits (TOFE and RTIE) in the TCSR are cleared by internal hardware to remove any pending timer interrupt requests and to disable any further timer interrupts. Execution of the STOP instruction automatically clears the I-bit in the Condition Code Register and sets the IRQE enable bit in the IRQ Control/Status Register so that the IRQ external interrupt is enabled. All other registers, including the other bits in the TCSR, and memory remain unaltered. All input/output lines remain unchanged.

The MCU can be brought out of the STOP Mode only by an IRQ external interrupt or an externally generated RESET or an LVR reset. When exiting the STOP Mode the internal oscillator will resume after a 224 or 4064 internal processor clock cycle oscillator stabilizing delay which is selected by a mask option.

NOTE

Execution of the STOP instruction with the STOP Mode Mask Option will cause the oscillator to stop and therefore disable the COP Watchdog Timer. If the COP

Watchdog Timer is to be used, the STOP Mode should be changed to the HALT

Mode by choosing the appropriate mask option. See Section 6.4 for more details.

6.1.2 HALT Mode

Execution of the STOP instruction in this mode (selected by a mask option) places the MCU in a low-power mode, which consumes more power than the STOP

Mode. In the HALT Mode the internal processor clock is halted, suspending all processor and internal bus activity. Internal timer clocks remain active, permitting interrupts to be generated from the timer (MFT or Timer 1) or a reset to be generated from the COP Watchdog Timer. Execution of the STOP instruction automatically clears the I-bit in the Condition Code Register and sets the IRQE enable bit in the IRQ Control/Status Register so that the IRQ external interrupt is enabled.

All other registers, memory, and input/output lines remain in their previous states.

The HALT Mode may be terminated by a Timer interrupt, an external IRQ, an LVR reset, or external RESET occurs. Since the internal timer is still running in the

HALT mode, the wake up delay timer (oscillator stabilizing delay timer) may start counting from an unknown value. So, the internal processor clock will resume

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6.2

WAIT INSTRUCTION

The WAIT instruction places the MCU in a low-power mode, which consumes more power than the STOP Mode. In the WAIT Mode the internal processor clock is halted, suspending all processor and internal bus activity. Internal timer clocks remain active, permitting interrupts to be generated from the timer or a reset to be generated from the COP Watchdog Timer. Execution of the WAIT instruction automatically clears the I-bit in the Condition Code Register and sets the IRQE enable bit in the IRQ Control/Status Register so that the IRQ external interrupt is enabled.

All other registers, memory, and input/output lines remain in their previous states.

If timer (MFT or Timer 1) interrupts are enabled, a TIMER interrupt will cause the processor to exit the WAIT Mode and resume normal operation. The Timer may be used to generate a periodic exit from the WAIT Mode. The WAIT Mode may also be exited when an external IRQ or an LVR reset or an external RESET occurs.

6.3

DATA-RETENTION MODE

If the LVR mask option is selected and since LVR kicks in whenever V

DD

is below the specified LVR trigger voltage which is higher than that required of the Data

Retention mode, the Data Retention mode will not exist. Data Retention Mode is only meaningful if LVR mask option is not selected.

The contents of RAM and CPU registers are retained at supply voltage as low as

2.0 VDC. This is called the data-retention mode where the data is held, but the device is not guaranteed to operate. The RESET pin must be held low during data-retention mode.

6.4

COP WATCHDOG TIMER CONSIDERATIONS

The COP Watchdog Timer is active in all modes of operation if enabled by a mask option. Thus, emulation of applications that do not service the COP should only be done with devices that have the COP Mask Option disabled.

If the COP Watchdog Timer is selected by the mask option, any execution of the

STOP instruction (either intentional or inadvertent due to the CPU being disturbed) will cause the oscillator to halt and prevent the COP Watchdog Timer from timing out unless the STOP to HALT conversion feature is enabled. Therefore, it is recommended that the STOP instruction should be converted to a HALT instruction if the COP Watchdog Timer is enabled.

If the COP Watchdog Timer is selected by the mask option, the COP will reset the

MCU when it times out. Therefore, it is recommended that the COP Watchdog should be disabled for a system that must have intentional uses of the WAIT Mode for periods longer than the COP time-out period.

6-4

LOW POWER MODES

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MC68HC05J5A

Freescale Semiconductor, Inc.

July 16, 1999 GENERAL RELEASE SPECIFICATION

The recommended interactions and considerations for the COP Watchdog Timer,

STOP instruction, and WAIT instruction are summarized in Table 6-1.

Table 6-1. COP Watchdog Timer Recommendations

IF the following conditions exist:

STOP Instruction converted to HALT by mask option converted to HALT by mask option

Acts as STOP

WAIT Time

WAIT Time less than

COP Time-Out

WAIT Time more than

COP Time-Out any length

WAIT Time

THEN the

COP Watchdog Timer should be as follows:

Enable or disable COP by mask option

Disable COP by mask option

Disable COP by mask option

REV 2.1

LOW POWER MODES

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6-5

Freescale Semiconductor, Inc.

GENERAL RELEASE SPECIFICATION July 16, 1999

6-6

LOW POWER MODES

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MC68HC05J5A

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July 16, 1999 GENERAL RELEASE SPECIFICATION

SECTION 7

INPUT/OUTPUT PORTS

In the normal operating mode there are 14 usable bidirectional I/O lines arranged as one 8-bit I/O port (Port A), and one 6-bit I/O port (Port B). The individual bits in these ports are programmable as either inputs or outputs under software control by the data direction registers (DDR’s). Also, if enabled by a single mask option all

Port A and Port B I/O pins may have individual software programmable pull-down or pull-up devices. Also, PA4-PA7 and PB1-PB2 pins have high current sink capability; PA0-PA3 may function as additional IRQ interrupt input sources. Note that both PA6 and PA7 pins have Schmitt trigger input for better noise immunity. V

IH and V

IL

specified at 2.4V and 0.8V, respectively.

The four port pins, PB2-PB5 are only available on the 20-pin version of the device.

7.1

SLOW OUTPUT FALLING-EDGE TRANSITION

7

R

DDRB

$0005

W reset

⇒

SLOWE

0

6

0

0

5

DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0

0

4

0

3

0

2

0

1

0

0

0

Figure 7-1. Port B Data Direction Register

SLOWE - Slow Transition Enable

The slow transition feature is controlled by the SLOWE bit of DDRB (Port B

Data Direction Register).

1 = Enables the slow falling-edge output transition feature on the four I/

O lines: PA6, PA7, PB1, and PB2. If the pin is configured as an output pin.

0 = Disables slow falling-edge output transition feature on the four I/O lines: PA6, PA7, PB1, and PB2. Default value of SLOWE bit is cleared.

7.2

PORT A

Port A is a 8-bit bidirectional port which shares five of its pins with the IRQ inter-

rupt system as shown in Figure 7-2. Note that both PA6 and PA7 pins have

Schmitt trigger input for better noise immunity. Only the PA6 and PA7 pins are open-drained type with slow output transition feature.

REV 2.1

INPUT/OUTPUT PORTS

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7-1

Freescale Semiconductor, Inc.

GENERAL RELEASE SPECIFICATION July 16, 1999

Each Port A pin is controlled by the corresponding bits in a data direction register, a data register and a pulldown/up register. The Port A Data Register is located at address $0000. The Port A Data Direction Register (DDRA) is located at address

$0004. The Port A Pulldown/up Register (PDURA) is located at address $0010.

Reset operation will clear the DDRA and the PDURA. The Port A Data Register is unaffected by reset.

Read $0004

Write $0004

VDD

5K

Pullup

Data Direction

Register Bit

Write $0000

Read $0000

Write $0010

Data

Register Bit

Output

100

µ

A

Pulldown

I/O

Pin

8 mA Sink

Capability

(Bits 4-7 Only)

Pulldown/up

Register Bit

Internal HC05

Data Bus

Reset

(RST)

Mask Option

(Software Pulldown/up Inhibit)

Note1: All the I/O port pins may have either pullup or pulldown device.

Note2: PA6 and PA7 output drivers are the open-drained type

PA0-PA3 and PA7 only: to IRQ interrupt system

Figure 7-2. Port A I/O Circuitry

7.2.1 Port A Data Register

Each Port A I/O pin has a corresponding bit in the Port A Data Register. When a

Port A pin is programmed as output, the corresponding data register bit determines the logic state of that pin. When a Port A pin is programmed as input, any read from the Port A Data Register will return the logic state of the corresponding

I/O pin. The Port A data register is unaffected by reset.

7.2.2 Port A Data Direction Register

Each Port A I/O pin may be programmed as input by clearing the corresponding bit in the DDRA, or programmed as output by setting the corresponding bit in the

DDRA. The DDRA can be accessed at address $0004. The DDRA is cleared by reset.

If configured as output pins, PA6 and PA7 have slow output falling-edge transition feature. The slow transition feature is controlled by the SLOWE bit of DDRB.

SLOWE bit, if set and if the pin is configured as an output pin, enables the slow falling-edge output transition feature of all four I/O lines, PA6, PA7, PB1, and PB2.

7-2

INPUT/OUTPUT PORTS

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MC68HC05J5A