HiFi 3 DSP User's Guide
2.4.3
Load and Store Naming Scheme
The mnemonic of most load and store operations contains a size indicating the size of operands it will load or store. The sizes are listed in the following table.
Table 2-10 Load/Store Operation Sizes
Size
16
Definition
16-bit scalar
Description
This operation accesses an aligned 16 bit quantity.
24
32
32F24
24-bit scalar
32-bit scalar
Left-justified 24bit fraction
This operation accesses a 24-bit quantity that is packed into memory so as to occupy only 24 bits in memory.
This operation accesses an aligned 32-bit quantity.
This size is also used for legacy 24-bit integers which are stored in a 32-bit memory location right-justified and with 8 bits of sign extension.
This operation accesses a 24-bit fraction, which is stored left-justified in a 32-bit memory location. It shifts the value right by 8 bits and sign extends on the left by
8 bits. The address must be 32-bit aligned.
This operation accesses an aligned 64-bit quantity. 64 64-bit scalar
24X2
32X2
32X2F24
16X4
Vector of 24-bit This operation accesses two of the size “24” above, occupying 48 bits in memory.
Vector of 32-bit This operation accesses two of the size “32” above.
Some instructions need the pair to be 64-bit aligned while others do not.
Vector of leftjustified 24-bit fraction
Vector of 16 bit
This operation accesses two of the size “32F24” above. Some instructions need the pair to be 64-bit aligned, while others do not.
This operation accesses four of the size “16” above.
Some instructions need the quartet to be 64-bit aligned, while others do not.
The mnemonic of most load and store operations contains a suffix indicating how the effective address is computed and whether the base address register is updated. The suffixes are listed in the following table.
Operations with suffix IP , XP , IC , or XC follow a “post-increment” convention where the effective address is the base AR register, and the base address register is updated by adding an immediate, constant or register offset. Operations with suffix IU or XU follow a “preincrement” convention where the effective address is the result of adding the immediate or register offset to the base address register’s contents and the base address register is updated with the effective address. Operations with suffix I or X do not increment, but create an effective address which is the sum of the base address register and an immediate or offset register.
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HiFi 3 DSP User's Guide
Table 2-11 Load/Store Operation Suffixes
I
Suffix &
Definition
Immediate
X
Indexed
IP
Post Update
Immediate
Effective
Address
Reg + immed
Reg +
Reg
Reg
Reg
Base Reg
Update
[none]
Description
[none]
The effective address is a base AR register plus an immediate value. The base AR register is not updated.
The effective address is a base AR register plus an index AR register value. The base AR register is not updated.
Reg +
Immed
The effective address is a base AR register.
The base AR register is updated with the base
AR register plus an immediate or constant value.
Reg + Reg The effective address is a base AR register.
The base AR register is updated with the base
AR register plus an offset AR register value.
XP
Post Update
Indexed
IC
Post Update
Implied
Immediate with Circular buffer
Reg
XC
Post Update
Indexed with
Circular
Buffer
Reg
RIP
Reverse
Post Update
Reg
RIC
Reverse
Post Update
Implied
Immediate with Circular buffer
Reg
Reg +
Const folded back into circular buffer
Reg + Reg folded back into circular buffer
Reg
Reg +
Const folded back into circular buffer
The effective address is base AR register. The base AR register is updated with the base AR register plus a positive constant value equal to one element. If the address is less than AE_
CEND0 and the updated value is greater than or equal to AE_CEND0 , then AE_CEND0-
AE_CBEGIN0 is subtracted from it.
The effective address is base AR register. The base AR register is updated with the base AR register plus an offset AR register value. For positive updates, if the address is less than
AE_CEND0 and the updated value is greater than or equal to AE_CEND0 , then
AE_CEND0-AE_CBEGIN0 is subtracted from it. For negative updates, if the address is greater than or equal to AE_CBEGIN0 and the updated value is less than AE_CBEGIN0 , then AE_CEND0-AE_CBEGIN0 is added to it.
The effective address is a base AR register.
The base AR register is updated with the base
AR register minus the size of the element being loaded or stored. The vector elements in the result register are also swapped.
The effective address is base AR register. The base AR register is updated with the base AR register minus a positive constant value equal to one element. If the address is greater than or equal to AE_CBEGIN0 and the updated value is less than AE_CBEGIN0 , then
AE_CEND0-AE_CBEGIN0 is added to it. The
C ADENCE D ESIGN S YSTEMS , I NC .
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HiFi 3 DSP User's Guide
Suffix &
Definition
PP
Prime
See
Instruction
PC
Circular
Prime
FP
Flush
IU
Immediate with Update
See
Instruction
See
Instruction
Reg +
Immed
XU
Indexed with
Update
Effective
Address
Base Reg
Update
Description
See
Instruc-tion
See
Instruc-tion
See
Instruc-tion vector elements in the result register are also swapped.
This addressing mode is used for priming instructions which set up the beginning of an unaligned load sequence
This addressing mode is used for priming instructions which set up the beginning of an unaligned load sequence in a circular buffer
This addressing mode is used for flushing the last part of an unaligned store sequence
Reg +
Reg
Reg +
Immed
The effective address is a base AR register plus an immediate value. The base AR register is updated with the effective address. These instructions are used for legacy HiFi 2/EP operations only.
Reg + Reg
The effective address is a base AR register plus an offset AR register value. The base AR register is updated with the effective address.
These instructions are used for legacy HiFi
2/EP operations only.
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C ADENCE D ESIGN S YSTEMS , I NC .