RM0468
8.5.8
Reset and clock control (RCC)
Kernel clock selection
Some peripherals are designed to work with two different clock domains that operate asynchronously:
• a clock domain synchronous with the register and bus interface ( ckg_bus_perx clock)
• and a clock domain generally synchronous with the peripheral (kernel clock).
The benefit of having peripherals supporting these two clock domains is that the user application has more freedom to choose optimized clock frequency for the CPU, bus matrix and for the kernel part of the peripheral.
As a consequence, the user application can change the bus frequency without reprogramming the peripherals. As an example an on-going transfer with UART will not be disturbed if its APB clock is changed on-the-fly.
Table 56 shows the kernel clock that the RCC can deliver to the peripherals. Each row of
Table 56 represents a MUX and the peripherals connected to its output. The columns
starting from number 5 represents the clock sources. Column 3 gives the maximum allowed frequency at each MUX output. It is up to the user to respect these requirements.
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Peripherals
Table 56. Kernel clock distribution overview
Maximum allowed frequency
[MHz]
Clock mux control bits
VOS0 VOS1 VOS2 VOS3
Clock sources
LTDC
FMC
OCTOSPI
SDMMC1
SDMMC2
DFSDM1 Aclk
DFSDM1 clk
FDCAN
HDMI-CEC
I2C1,2,3, 5
LPTIM1
TIM[8:1][17:12]
RNG
SAI1
SPDIFRX
SPI(I2S)1,2,3
-
FMCSEL
OCTOSPISEL
SDMMCSEL
SAI1SEL
DFSDM1SEL
FDCANSEL
CECSEL
I2C1235SEL
LPTIM1SEL
-
RNGSEL
SAI1SEL
SPDIFRXSEL
SPI123SEL
200
200
100
1
100
100
200
200
200
(4)
200
100
200
200
150
200
180
250
275
125
1
137.5
166
275
333
250
(4)
250
137.5
275
250
166
250
250
150
150
75
1
75
75
150
150
150
(4)
150
75
150
150
113
150
125
50
100
100
100
(4)
100
43
85
100
75
100
75
100
85
50
1
43
D1
D2
1
1
0
0
1
1
1
1
0 1
0
0 1
2
2
2
1
1
2
2
2 x
0
0
3
3
4 3
1
2
1 0
0
0 x
0
2
(3)
2 3
0
3
1
4 5
0 2 3
4 3
2 3
4 3
Peripherals
Table 56. Kernel clock distribution overview (continued)
Maximum allowed frequency
[MHz]
Clock sources
Clock mux control bits
VOS0 VOS1 VOS2 VOS3
SPI4,5
SWPMI
USART1,6, 10
UART9
USART2,3
UART4,5,7,8
SPI45SEL
SWPMISEL
USART16910SEL
USART234578SEL
250
137.5
137.5
137.5
180
100
100
100
125
75
75
75
75
43
43
43
D2
1
1
1
2
2
2
0
0
0
0
5 3
1
3
3
4
4
4
5
5
USB1OTG USBSEL 125 100 50 50 1 2 3
USB1ULPI
ADC1,2, 3
I2C4
LPTIM2
-
ADCSEL
I2C4SEL
LPTIM2SEL
60
160
(4)
137.5
137.5
60
160 (4)
100
100
45
60
75
75
40
40 (4)
43
43
0
1
1
1
2
0
0
2 3
3 4
2
5
LPTIM3,4,5
LPUART1
LPTIM345SEL
LPUART1SEL
137.5
137.5
100
100
75
75
43
43 D3
1
1 2
2 0
0 3 4
3
5
4
SAI4_A
SAI4_B
SPI(I2S)6
RTC/AWU
SAI4ASEL
SAI4BSEL
SPI6SEL
RTCSEL
166
166
250
150
150
180
1
113
113
125
75
75
75
VSW
0
0
1
1
1
2
2
2 0 5 3 4
3
(5)
1. The bus clocks are the bus interface clocks to which the peripherals are connected, it can be APB, AHB or AXI clocks.
2. The per_ck clock could be hse_ck, hsi_ker_ck or csi_ker_ck according to CKPERSEL selection.
3. Clock CSI divided by 122.
4. With a duty cycle close to 50%, meaning that DIV[P/Q/R]x values shall be even. For SDMMCx, the duty cycle shall be 50% when supporting DDR.
5. Clock HSE divided by RTCPRE.
1 2
5
4
4
3
3
6 x
5
5
0
0
Reset and clock control (RCC)
Note:
RM0468
Figure 50
to Figure 60
provide a more detailed description of kernel clock distribution. To simplify the drawings, the bus interface clocks (pclk, hclk) are not represented, even if they
are gated with enable signals. Refer to Section 8.5.11: Peripheral clock gating control for
more details.
To reduce the amount of switches, some peripherals share the same kernel clock source.
Nevertheless, all peripherals have their dedicated enable signal.
Peripherals dedicated to audio applications
The audio peripherals generally need specific accurate frequencies, except for SPDIFRX.
As shown in
Figure 50
and
Figure 51 , the kernel clock of the SAIs or SPI(I2S)s can be
generated by:
• The PLL1 when the amount of active PLLs has to be reduced
• The PLL2 or 3 for optimal flexibility in frequency generation
• HSE, HSI or CSI for use-cases where the current consumption is critical
• I2S_CKIN when an external clock reference need to be used.
The SPDIFRX does not require a specific frequency, but only a kernel clock frequency high enough to make the peripheral work properly. Refer to the SPDIFRX description for more details.
DFSDM1 can use the same clock as SAI1A. This is useful when DFSDM1 is used for audio applications.
To improve the flexibility, SAI4 can use different clock for each sub-block.
The SPI/I2S1, 2, and 3 share the same kernel clock source (see
Figure 52
) .
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RM0468 Reset and clock control (RCC)
Figure 50. Kernel clock distribution for SAIs and SPDIFRX
RCC
SPDIFRXSEL pll1_q_ck pll2_r_ck pll3_r_ck hsi_ker_ck
SAI4SELA pll1_q_ck pll2_p_ck pll3_p_ck
I2S_CKIN per_ck spdifrx_symb_ck
SAI4SELB pll1_q_ck pll2_p_ck pll3_p_ck
I2S_CKIN per_ck spdifrx_symb_ck
2
3
0
1
D
0
3
4
1
2
5
D
0
1
2
3
4
D
5
SPDIFRXEN
SPDIFRXLPEN
Logic
SAI4EN
SAI4LPEN
Logic
SPDIFRX spdifrx_ker_ck sai_a_ker_ck
SAI4 sai_b_ker_ck
D
The switch is dynamic: the transition between two inputs is glitch-free
MSv63809V3
1.
X represents the selected MUX input after a system reset.
2. This figure does not show the connection of the bus interface clock to the peripherals. For details on each enable cell,
please refer to Section 8.5.11: Peripheral clock gating control
.
Figure 51. Kernel clock distribution for DFSDM
RCC
DFSDM1SEL rcc_pclk2 sys_ck
SAI1SEL pll1_q_ck pll2_p_ck pll3_p_ck
I2S_CKIN per_ck
0
D
1
2
3
0
1
4
D
DFSDMEN
DFSDMLPEN
Logic clk
DFSDM
SAI1EN
SAI1LPEN
Logic
PKEU
Aclk sai_a_ker_ck
SAI1 sai_b_ker_ck
PKSU
D The switch is dynamic: the transition between two inputs is glitch-free
MSv63806V2
1.
X represents the selected MUX input after a system reset.
2. This figure does not show the connection of the bus interface clock to the peripherals. For details on each enable cell,
please refer to Section 8.5.11: Peripheral clock gating control
.
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Reset and clock control (RCC)
Note:
RM0468
Peripherals dedicated to control and data transfer
Peripherals such as SPIs, I2Cs, UARTs do not need a specific kernel clock frequency but a clock fast enough to generate the correct baud rate, or the required bit clock on the serial interface. For that purpose the source can be selected among:
• PLL1 when the amount of active PLLs has to be reduced
• PLL2 or PLL3 if better flexibility is required. As an example, this solution allows changing the frequency bus via PLL1 without affecting the speed of some serial interfaces.
• HSI or CSI for low-power use-cases or when the peripheral has to quickly wake up from Stop mode (i.e. UART, I2C...).
UARTs also need the LSE clock when high baud rates are not required.
Figure 52. Kernel clock distribution for SPIs and SPI/I2S
SPDIFRXSEL pll1_q_ck pll2_r_ck pll3_r_ck hsi_ker_ck
SPI123SEL
2
3
0
1
D
SPDIFRXLPEN
SPDIF-RX spdifrx_ker_ck pll1_q_ck pll2_p_ck pll3_p_ck
I2S_CKIN per_ck
SPI45SEL
0
1
2
3
4
D
SPI[3:1]EN
SPI[3:1]LPEN
Logic
RCC rcc_pclk2 pll2_q_ck pll3_q_ck hsi_ker_ck csi_ker_ck hse_ck
SPI6SEL
0
1
2
D
3
4
5
SPI[5:4]EN
SPI[5:4]LPEN
Logic rcc_pclk4 pll2_q_ck pll3_q_ck hsi_ker_ck csi_ker_ck hse_ck
I2c_ckin
4
5
6
0
1
2
D
3
PKSU
SPI6AMEN
SPI6EN
SPI6LPEN
Logic
PKEU
D
The switch is dynamic: the transition between two inputs is glitch-free
SPI/I2S[3:1] spi_ker_ck
SPI[5:4] spi_ker_ck
SPI/I2S6 spi_ker_ck
MSv63807V5
1.
X represents the selected MUX input after a system reset.
2. This figure does not show the connection of the bus interface clock to the peripheral. or details on each enable cell, please refer to
Section 8.5.11: Peripheral clock gating control .
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Figure 53. Kernel clock distribution for I2Cs
RCC
I2C4SEL rcc_pclk4 pll3_r_ck hsi_ker_ck csi_ker_ck
I2C123SEL
0
1
2
3
D rcc_pclk1 pll3_r_ck hsi_ker_ck csi_ker_ck
0
1
D
2
3
PKSU
I2C4AMEN
I2C4EN
I2C4LPEN
I2C[5,3:1]EN
I2C[5,3:1]LPEN
Logic
Logic
PKEU
D The switch is dynamic: the transition between two inputs is glitch-free
I2C4 i2c_ker_ck_req i2c_ker_ck
I2C[5,3:1] i2c_ker_ck_req i2c_ker_ck
MSv63810V1
1.
X represents the selected MUX input after a system reset
2. This figure does not show the connection of the bus interface clock to the peripheral, for details on each enable cell, please refer to
Section 8.5.11: Peripheral clock gating control .
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Reset and clock control (RCC)
Figure 54. Kernel clock distribution for UARTs, USARTs and LPUART1
RM0468
USART16910SEL
USART234578910SEL
RCC rcc_pclk2 pll2_q_ck pll3_q_ck hsi_ker_ck csi_ker_ck lse_ck rcc_pclk1 pll2_q_ck pll3_q_ck hsi_ker_ck csi_ker_ck lse_ck
4
5
0
1
2
3
D
0
1
2
3
D
4
5
PKSU
USART1EN
USART1LPEN
USART6EN
USART6LPEN
UART9LPEN
USART10LPEN
USART[3:2]EN
USART[3:2]LPEN
UART[5:4]EN
UART[5:4]LPEN
UART[8:7]EN
UART[8:7]LPEN
Logic
Logic
Logic
Logic
Logic
Logic
Logic
USART1 usart_ker_ck_req usart_ker_ck
USART6 usart_ker_ck_req usart_ker_ck
UART9 uart_ker_ck_req uart_ker_ck
USART10 usart_ker_ck_req usart_ker_ck
USART[3:2] usart_ker_ck_req usart_ker_ck
UART[5:4] uart_ker_ck_req uart_ker_ck
UART[8:7] uart_ker_ck_req uart_ker_ck
LPUART1SEL rcc_pclk4 pll2_q_ck pll3_q_ck hsi_ker_ck csi_ker_ck lse_ck
0
1
4
5
2
3
D
LPUART1AMEN
LPUART1EN
LPUART1PLEN
Logic
LPUART1 lpuart_ker_ck_req lpuart_ker_ck
PKEU
D The switch is dynamic: the transition between two inputs is glitch-free
MSv63811V2
1.
X represents the selected MUX input after a system reset.
2. This figure does not show the connection of the bus interface clock to the peripheral, for details on each enable cell, please refer to
Section 8.5.11: Peripheral clock gating control .
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RM0468 Reset and clock control (RCC)
Figure 55. Kernel clock distribution for LTDC
RCC pll3_r_ck
PKSU
LTDCEN
LTDCLPEN
PKEU
Logic ltdc_ker_ck
LTDC
MSv41935V2
1.
X represents the selected MUX input after a system reset.
2. This figure does not show the connection of the bus interface clock to the peripheral. For details on each enable cell, please refer to
Section 8.5.11: Peripheral clock gating control .
The FMC, OCTOSPI and SDMMC1/2 can also use a clock different from the bus interface clock for more flexibility.
Figure 56. Kernel clock distribution for SDMMC, OCTOSPI and FMC
SDMMCSEL pll1_q_ck pll2_r_ck
0
1
D
SDMMC[2:1]EN
SDMMC[2:1]LPEN
Logic
SDMMC1/2 sdmmc_ker_ck
RCC OCTOSPISEL rcc_hclk3 pll1_q_ck pll2_r_ck per_ck
0
1
D
2
3
OCTOSPI[2:1]EN
OCTOSPI[2:1]LPEN
Logic
OCTOSPI1/2 octospi_ker_ck
FMCSEL rcc_hclk3 pll1_q_ck pll2_r_ck per_ck
FMCEN
FMCLPEN
FMC
0
1
D
2
3
PKSU
Logic fmc_ker_ck
PKEU
D
The switch is dynamic: the transition between two inputs is glitch-free.
MSv48160V2
1.
X represents the selected MUX input after a system reset.
2. This figure does not show the connection of the bus interface clock to the peripheral. For details on each enable cell, please refer to
Section 8.5.11: Peripheral clock gating control .
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Reset and clock control (RCC) RM0468
Figure 57
shows the clock distribution for the USB blocks. The USB1ULPI block receives its clock from the external PHY.
The USB1OTG block receives the clock for USB communications which can be selected among different sources thanks to the MUX controlled by USBSEL.
Figure 57. Kernel clock distribution for USB
(2)
USBSEL
0 pll1_q_ck pll3_q_ck hsi48_ck
0
1
2
D
3
USB1OTGEN
USB1OTGLPEN
Logic
USB1OTG usb_ker_ck
RCC
USB_PHY1
USB1ULPIEN
USB1ULPILPEN
Logic
USB1ULPI ulpi_ck
PKSU PKEU
D The switch is dynamic: the transition between two inputs is glitch-free.
1.
X represents the selected MUX input after a system reset.
2. This figure does not show the connection of the bus interface clock to the peripheral. For details on each enable cell, please refer to
Section 8.5.11: Peripheral clock gating control .
The Ethernet transmit and receive clocks shall be provided from an external Ethernet PHY.
The clock selection for the RX and TX path is controlled via the SYSCFG block.
Figure 58. Kernel clock distribution for Ethernet
MSv48161V3
RCC
PKSU
ETH1TXEN
ETH1TXLPEN
PKEU
Logic
ETH_MII_TX_CLK
ETH_MII_RX_CLK/
ETH_RMII_REF_CLK
÷ 2, 20
0
1
D
1
0
D
ETH1RXEN
ETH1RXLPEN
Logic
ETH1 eth_mii_tx_clk
FES
EPIS[2] eth_mii_rx_clk
ETH1TXEN or ETH1RXEN
ETH1TXLPEN or ETH1RXLPEN
Logic
ETH1MACEN
ETH1MACLPEN
Logic eth_rmii_ref_clk hclk_i rcc_hclk1
D The switch is dynamic: the transition between two inputs is glitch-free
MSv41938V2
1.
X represents the selected MUX input after a system reset.
2. This figure does not show the connection of the bus interface clock to the peripheral. For details on each enable cell, please refer to
Section 8.5.11: Peripheral clock gating control .
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RM0468 Reset and clock control (RCC)
Figure 59. Kernel clock distribution for ADCs, SWPMI, RNG and FDCAN
(2)
ADCSEL pll2_p_ck pll3_r_ck per_ck
0
1 D
2
ADC3AMEN
ADC3EN
ADC3LPEN
Logic ADC3 adc_ker_ck_input
ADC12EN
ADC12LPEN
Logic ADC12 adc_ker_ck_input
RCC
SWPSEL rcc_pclk1 hsi_ker_ck
0
1
D
SWPEN
SWPLPEN
Logic SWPMI swpmi_ker_ck
RNGSEL hsi48_ck pll1_q_ck lse_ck lsi_ck
FDCANSEL hse_ck pll1_q_ck pll2_q_ck
0
1 D
2
3
0
1 D
2
PKSU
RNGEN
RNGLPEN
FDCANEN
FDCANLPEN
Logic
Logic
PKEU
RNG rng_ker_ck
FDCAN fdcan_ker_ck
D The switch is dynamic: the transition between two inputs is glitch-free
MSv41939V3
1.
X represents the selected MUX input after a system reset.
2. This figure does not show the connection of the bus interface clock to the peripheral. For details on each enable cell, please refer to
Section 8.5.11: Peripheral clock gating control .
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Reset and clock control (RCC)
Figure 60. Kernel clock distribution for LPTIMs and HDMI-CEC (2)
RM0468
RCC lse_ck lsi_ck csi_ker_ck ÷ 122
LPTIM1SEL rcc_pclk1 pll2_p_ck pll3_r_ck lse_ck lsi_ck per_ck
LPTIM2SEL rcc_pclk4 pll2_p_ck pll3_r_ck lse_ck lsi_ck per_ck
LPTIM345SEL rcc_pclk4 pll2_p_ck pll3_r_ck lse_ck lsi_ck per_ck
0
1
2
3
4
5
0
1
2
3
D
4
5
0
1
2
3
4
5
D
D
PKSU
CECSEL
0
1
D
2
CECEN
CECLPEN
Logic
LPTIM1EN
LPTIM1LPEN
Logic
LPTIM2AMEN
LPTIM2EN
LPTIM2LPEN
Logic
LPTIM[5:3]AMEN
LPTIM[5:3]EN
LPTIM[5:3]LPEN
Logic
HDMI-CEC cec_ker_ck (im)
LPTIM1 lptim_ker_ck
LPTIM2 lptim_ker_ck
LPTIM[5:3] lptim_ker_ck
PKEU
D
The switch is dynamic: the transition between two inputs is glitch-free
MSv41940V3
1.
X represents the selected MUX input after a system reset
2. This figure does not show the connection of the bus interface clock to the peripheral. For details on each enable cell, please refer to
Section 8.5.11: Peripheral clock gating control .
RTC/AWU clock
The rtc_ck clock source can be:
• the hse_1M_ck ( hse_ck divided by a programmable prescaler)
• the lse_ck
• or the lsi_ck clock
The source clock is selected by programming the RTCSEL[1:0] bits in the RCC backup domain control register (RCC_BDCR)
and the RTCPRE[5:0] bits in the RCC clock configuration register (RCC_CFGR)
.
This selection cannot be modified without resetting the Backup domain.
If the LSE is selected as RTC clock, the RTC will work normally even if the backup or the
V
DD
supply disappears.
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RM0468 Reset and clock control (RCC)
Note:
The LSE clock is in the Backup domain, whereas the other oscillators are not. As a consequence:
• If LSE is selected as RTC clock, the RTC continues working even if the V
DD switched OFF, provided the V
BAT
supply is maintained.
supply is
• If LSI is selected as the RTC clock, the AWU state is not guaranteed if the V
DD is powered off.
supply
• If the HSE clock is used as RTC clock, the RTC state is not guaranteed if the V
DD supply is powered off or if the V
CORE
supply is powered off.
The rtc_ck clock is enabled through RTCEN bit located in the
RCC backup domain control register (RCC_BDCR)
.
The RTC bus interface clock (APB clock) is enabled through RTCAPBEN and
RTCAPBLPEN bits located in RCC_APB4ENR/LPENR registers.
To read the RTC calendar register when the APB clock frequency is less than seven times the RTC clock frequency (F
APB
< 7 x F
RTCLCK
), the software must read the calendar time and date registers twice. The data are correct if the second read access to RTC_TR gives the same result than the first one. Otherwise a third read access must be performed.
Watchdog clocks
The RCC provides the clock for the four watchdog blocks available on the circuit. The independent watchdog (IWDG1) is connected to the LSI. The window watchdog (WWDG1) are connected to the APB clock.
If an independent watchdog is started by either hardware option or software access, the LSI is forced ON and cannot be disabled. After the LSI oscillator setup delay, the clock is provided to the IWDG.
Caution: Before enabling the WWDG1, the application must set the WW1RSC bit to 1. If the
WW1RSC remains to 0, when the WWDG1 is enabled, its the behavior is not guaranteed.
The WW1RSC bit is located in
RCC global control register (RCC_GCR) .
Clock frequency measurement using TIMx
Most of the clock source generator frequencies can be measured by means of the input capture of TIMx.
• Calibrating the HSI or CSI with the LSE
The primary purpose of having the LSE connected to a TIMx input capture is to be able to accurately measure the HSI or CSI. This requires to use the HSI or CSI as system clock source either directly or via PLL1. The number of system clock counts between consecutive edges of the LSE signal gives a measurement of the internal clock period.
Taking advantage of the high precision of LSE crystals (typically a few tens of ppm) we can determine the internal clock frequency with the same resolution, and trim the source to compensate for manufacturing-process and/or temperature- and voltagerelated frequency deviations.
The basic concept consists in providing a relative measurement (e.g. HSI/LSE ratio): the precision is therefore tightly linked to the ratio between the two clock sources. The greater the ratio is, the more accurate the measurement is.
The HSI and CSI oscillators have dedicated user-accessible calibration bits for this
purpose (see RCC CSI configuration register (RCC_CSICFGR) ) for revision Y devices
and RCC HSI configuration register (RCC_HSICFGR)
/ RCC CSI configuration register
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