Functional check. STMicroelectronics 170 W power supply with PFC and standby supply for flat TV using the L6564, L6599A, and Viper27LN EVL, EVL170W-FTV
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AN3329 Functional check
Standby supply
Some salient waveforms of the standby supply during full load operation are reported in
and
. This converter is based on the Viper27LN, a device integrating the controller and the MOSFET in a single DIP-7 package. The Viper27LN version operates in fixed frequency mode at about 60 kHz, and frequency jitter technique is implemented to reduce EMI noise. In order to obtain good efficiency as well as reduced transformer size the converter has been designed to operate at full load in continuous conduction mode at low
mains voltage ( Figure 13 ) and discontinuous conduction mode at high mains voltage
(
), once the PFC and resonant stages are off. It can be noted from the drain waveforms that the typical ringing at turn-off is limited, thanks to the small value of the transformer's primary leakage inductance, allowing limited power dissipation on the Transil diode D19 and therefore enhancing the efficiency at rated load. D19 acts as a clamper and allows to limit the drain peak voltage below the Viper27LN maximum rating even with maximum input voltage and full load operation.
Figure 13.
Standby supply waveforms at
115 Vac - 60 Hz, full load
Figure 14.
Standby supply waveforms at
230 Vac - 50 Hz, full load
CH1: DRAIN (pin #8)
CH3: CONT (pin #3)
CH2: V
DD
(pin #2)
CH4: FB (pin #4)
CH1: DRAIN (pin #8)
CH3: CONT (pin #3)
CH2: V
DD
(pin #2)
CH4: FB (pin #4)
In
Figure 15 the converter waveforms are captured while the PFC is working and the
standby supply is powered with 400 V. The margin with respect to the Viper27LN maximum drain voltage can be noted on the sidebar on the right.
In
Figure 16 typical waveforms relevant to the secondary side have been captured; the
maximum reverse voltages applied to the rectifier at 400 V during full load operation with
PFC working are, even in this case, well below the component's maximum ratings, ensuring long term reliability.
Doc ID 18376 Rev 1 13/47
Functional check AN3329
Figure 15.
Standby supply waveforms at
400 Vdc, full load
Figure 16.
Standby supply output rectifiers
PIV at 400 Vdc, full load
CH1: DRAIN (pin #8)
CH3: CONT (pin #3)
CH2: V
DD
(pin #2)
CH4: FB (pin #4)
CH3: PIV D22 CH4: PIV D18
In
Figure 17 the 5 V standby output voltage ripple has been captured during operation at
115 Vac of the standby converter only. Ripple and noise measured at full load are very limited.
shows the waveforms during the startup of the standby converter only, at 115 Vac and full load. At Viper27LN power-on the Vcc capacitor is charged by the internal startup current source until its voltage reaches the turn-on threshold. At this point the Viper27LN starts operating and the output voltage rises to reach the nominal value. During the converter startup, the Viper27LN internal digital fixed time-based (8.5 ms) soft-start gradually increases the drain current to its maximum value. In this way the stress on the secondary diode is considerably reduced and transformer saturation is prevented. The brownout circuit prevents the Viper27LN from starting up during abnormal mains conditions.
Figure 17.
Standby supply 5 V ripple at
115 Vac - 60 Hz, full load
Figure 18.
Standby supply startup at 115 Vac -
60 Hz, full load
CH3: + 5 V standby ripple voltage
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CH1: DRAIN (pin #8)
CH3: BO (pin #5)
CH2: +5 V standby
CH4: V
DD
(pin #2)
Doc ID 18376 Rev 1
AN3329 Functional check
and
Figure 20 illustrate the waveforms during light load operation. Viper27LN
operates in burst-mode, with just a few pulses per burst, minimizing switching losses and therefore improving efficiency under light load operation, making it suitable for equipment with low standby consumption requirements.
Figure 19.
Standby supply burst mode operation at 230 Vac - 50 Hz - 10 mA load
Figure 20.
Standby supply burst mode operation at 230 Vac - 50 Hz - 10 mA load-detail
CH1: DRAIN (pin #8)
CH3: +5 V standby
CH2: V
DD
(pin #2)
CH4: FB (pin #4)
CH1: DRAIN (pin #8)
CH3: +5 V standby
CH2: V
DD
(pin #2)
CH4: FB (pin #4)
Figure 21.
Standby supply OVP at 115 Vac -
60 Hz, full load
Figure 22.
Standby supply OVP at 230 Vac -
50 Hz - 0.5 A
CH1: DRAIN (pin #8)
CH3: CONT (pin #3)
CH2: +5 V standby
CH4: FB (pin #4)
CH1: DRAIN (pin #8)
CH3: +5 V standby
CH2: V
DD
(pin #2)
shows the OVP response, observed opening the Viper27LN feedback loop. If the output voltage value exceeds the internal threshold set by the resistor divider connected to the CONT pin (#3), the Viper27LN stops working, providing protection against dangerous voltages which may damage the system. It remains latched until the V
DD
has dropped down to V
DD_RESTART
(4.5 V). At this point the auto-restart process takes place like any startup; the internal current source charges the V
DD
capacitor until it reaches the V
DDon
threshold
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Functional check AN3329 and switching starts again. This protection and restart sequence lasts as long as the OVP condition is removed. It is important to highlight that the Viper27LN OVP protection, thanks to the internal logic, ensures a stable OVP intervention point, independent of the output load, even if the voltage sensing is done on auxiliary winding at primary side. It can be noted, by comparing
which report some OVP intervention with different loads and input voltage conditions, that the maximum output voltage peak has a negligible variation.
Figure 23.
Standby supply OVP at 115 Vac -
60 Hz - PFC on - 1 A
Figure 24.
Standby supply OVP at 115 Vac -
60 Hz - PFC on - 1 A
CH1: DRAIN (pin #8)
CH3: CONT (pin #3)
CH2: +5 V standby
CH4: FB (pin #4)
CH1: DRAIN (pin #8)
CH3: CONT (pin #3)
CH2: 5 V standby
CH4: FB (pin #4)
Figure 25.
Standby supply output short-circuit at 230 Vac - 50 Hz, full load
Figure 26.
Standby supply output short-circuit at 230 Vac - 50 Hz, full load - detail
CH1: DRAIN (pin #8)
CH3: V
DD
(pin #2)
CH2: +5 V standby
CH4: FB (pin #4)
CH1: DRAIN (pin #8)
CH3: V
DD
(pin #2)
CH2: 5 V standby
CH4: FB (pin #4)
Figure 24 shows, in detail, the OVP intervention at 115 Vac. In Figure 25 a short-circuit
event on the standby supply output has been captured. In this situation the Viper27LN enters a safe hiccup mode, providing protection against overheating of the auxiliary converter power components.
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AN3329 Functional check
In
details of Viper27LN operation at short detection is captured; once an output short-circuit is detected, an internal current source charges the device internal circuitry and stops the auxiliary converter operation until the V
DD
voltage drops down to V
DD_RESTART
(4.5 V). At that time the internal HV current source is activated and charges the V
DD capacitor until it reaches the V
DDon
threshold, then the Viper27LN restarts switching via a soft-start cycle. Hiccup cycles are repeated as long as the short-circuit condition lasts.
Viper27LN is resumed back to normal operation only when the short-circuit condition is removed.
and
show the load regulation for the 5 V standby output. The standby supply has been tested in the most critical situation, the transition from full load to no load and vice versa. In fact, when a flyback converter is operating at full load, typically the self supply voltage V
DD
spike is quite high, due to the effect of the leakage inductance. Once the load is decreased or removed, V
DD
tends to reduce. Since the circuit works in burst-mode during no load operation, at high mains the burst pulses have a low repetition rate due to the almost negligible residual load. In this condition the V
DD
might drop below V
DD_RESTART
(4.5 V), causing the auto-restart cycles activation by the controller and consequent reset by the microprocessor powered by the 5 V standby. As can be seen in
transitions are clean and there is no output voltage or Vcc dip.
Figure 27.
Standby supply dynamic load at
115 Vac - 60 Hz - PFC off
Figure 28.
Standby supply dynamic load at
115 Vac - 60 Hz - PFC on
CH1: FB (pin #4)
CH3: +5 V standby
CH2: V
DD
(pin #2)
CH4: 5 V stby current
CH1: FB (pin #4)
CH3: 5 V standby
CH2: V
DD
(pin #2)
CH4: 5 V stby current
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Functional check AN3329
Power factor corrector stage
shows the PFC MOSFET's drain voltage, inductor current, and voltages on the
CS (#4) and MULT (#3) pins along a line half-period at 115Vac. Low current distortion and high power factor are achieved as the peak inductor current waveform follows the MULT pin.
THD (total harmonic distortion) is considerably reduced by the L6564 THD optimizer.
In
Figure 30 the same signals are captured at the top of the input sine wave. Transition
mode control makes the inductor work on the boundary between continuous and discontinuous conduction mode. When the PFC MOSFET turns on, the inductor current ramps up, until the voltage on the current sense input reaches the reference level programmed by the internal multiplier block. At that point, the PWM comparator changes state, turning off the power switch. During the MOSFET off-time, the current ramps down until it reaches zero, so the inductor is demagnetized. The zero current detection (ZCD) circuit detects that point by monitoring the voltage across the inductor auxiliary winding, which falls to zero when the current reaches zero, due to the resonance between the inductor and the drain capacitance. Once the demagnetization point is detected by the
L6564 internal logic, the signal on ZCD drives the MOSFET on again and another switching cycle begins. A significant advantage of TM operation is the possibility to work in ZVS: if the instantaneous input voltage of the converter is lower than the inductor voltage, the ZVS
(zero voltage switching) condition is achieved, decreasing MOSFET commutation losses.
However, if the instantaneous input voltage is higher than the inductor voltage the MOSFET is turned on at the minimum voltage, on the valley point of the resonance, still minimizing the transition losses, as seen in
.
Figure 29.
PFC Vds and inductor current at
115 Vac - 60 Hz, full load
Figure 30.
PFC Vds and inductor current at
115 Vac - 60 Hz, full load - detail
CH1: Q1 drain voltage
CH3: CS (pin #4)
CH2: MULT (pin #3)
CH4: L1 inductor current
CH1: Q1 drain voltage CH2: MULT (pin #3)
CH3: CS (pin #4) CH4: L1 inductor current
and
Figure 32 show the same waveforms at 230 Vac. As the input voltage is
higher than the inductor voltage, it is possible to observe the boost inductor resonating with the total drain capacitance with an amplitude of twice the inductor voltage on the offset of the input voltage. In order to maximize efficiency the RC network connected to the ZCD (#7) pin is tuned to make the turn-on of the MOSFET occur just on the valley of the drain voltage.
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AN3329 Functional check
Figure 31.
PFC Vds and inductor current at
230 Vac - 50 Hz, full load
Figure 32.
PFC Vds and inductor current at
230 Vac - 50 Hz, full load - detail
CH1: Q1 drain voltage
CH3: CS (pin #4)
CH2: MULT (pin #3)
CH4: L1 inductor current
CH1: Q1 drain voltage CH2: MULT (pin #3)
CH3: CS (pin #4) CH4: L1 inductor current
L6564 signals are shown in
Figure 33 and 34 for reference.
Figure 33.
L6564 signals-1 at 115 Vac - 60 Hz, full load
Figure 34.
L6564 signals-2 at 115 Vac - 60 Hz, full load
CH1: GD (pin #9)
CH3: MULT (pin #3)
CH2: ZCD (pin #7)
CH4: CS (pin #4)
CH1: GD (pin #9)
CH3: MULT (pin #3)
CH2: ZCD (pin #7)
CH4: CS (pin #4)
shows voltages on the VFF (#5), CS (#4), COMP (#2), and MULT (#3) pins along a line half-period at 115 Vac and 230 Vac respectively. Voltage feed-forward compensates for the gain and crossover frequency variation with the line voltage, since the power stage gain of PFC pre-regulators varies with the square of the RMS input voltage. Therefore, a DC voltage equal to the peak of the MULT (#3) pin is derived on the VFF (#5) pin and fed into a square/divider circuit making the COMP signal almost line-independent and improving the
dynamic behavior. That is emphasized in Figure 36 , which illustrates voltage on the MULT
(#3) pin at the peak of the line voltage matching that on the VFF pin.
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Functional check AN3329
Figure 35.
PFC signals-1 at 115 Vac - 60 Hz, full load
Figure 36.
PFC signals-2 at 115 Vac - 60 Hz, full load
CH1: COMP (pin #9)
CH3: MULT (pin #3)
CH2: VFF (pin #7)
CH4: CS (pin #4)
CH1: COMP (pin #9)
CH3: MULT (pin #3)
CH2: VFF (pin #7)
CH4: CS (pin #4)
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AN3329 Functional check
Resonant stage
Some waveforms relevant to the resonant stage during steady-state operation are reported in
, and
. The switching frequency at full load and nominal input voltage is around 75 kHz, in order to achieve a good trade-off between transformer losses and size.
shows the resonant ZVS operation. The converter operates slightly below resonance, therefore, the resonant current lags the voltage applied, as input impedance of the resonant network is inductive. The current is negative during the rising edge of half bridge voltage and positive during the falling-edge, providing, in both cases, the energy to allow the node HB swinging. Because of the dead time, the MOSFETs are turned on when resonant current is flowing through their body diodes and drain-source voltage is almost zero. In
Figure 38 voltages on the L6599A LINE (#7), RFmin (#4), CF (#3), and LVG
(#11) pins are observed. The switching frequency is programmed by the resistors connected to the RFmin (#4) pin, which provides an accurate 2 V reference. The current flowing out from the RFmin (#4) pin is internally mirrored and alternately charges and discharges the capacitor connected to CF (#3). LINE (#7) pin voltage enables and disables the resonant stage, preventing operation in capacitive mode.
Figure 37.
Resonant stage waveforms at 115 V
- 60 Hz, full load
Figure 38.
Resonant stage waveforms at 115 V
- 60 Hz, full load
CH1: HB voltage
CH3: HVG
CH2: LVG
CH4: C39 current
CH1: LVG (pin #11)
CH3: RFmin (pin #4)
CH2: CF (pin #3)
CH4: LINE (pin #7)
In
Figure 39 the reverse voltages across secondary rectifiers are represented. The system
operates slightly below resonance and therefore the output rectifiers are working in discontinuous conduction mode, as energy transfer ends before each node HB voltage swinging. Therefore, at primary side there are some short intervals where both diodes are reverse-biased and the magnetizing inductance Lp, being no longer shunted by the output capacitance reflected to the primary, becomes part of resonance. This corresponds to the primary side current waveform to the portion circled in blue.
In the same image, it can be noted that the rectifiers PIV are operating within their voltage rating and well below the BV, so ensuring long term reliability.
Doc ID 18376 Rev 1 21/47
Functional check
Figure 39.
Output rectifiers PIV waveforms
AN3329
CH1: D4 anode voltage
CH3: D9A anode voltage
CH2: D11 anode voltage
CH4: D9B anode voltage
No load operation
In
Figure 40 and 41 operation at no load is shown. This check has been done for reference
only, as typically a TV SMPS never works in such conditions. As seen, PFC is working in burst-mode, while the resonant stage is operating in continuous switching. This is possible by connecting the standby pin to the RFmin pin and it has been done to avoid any possible interference between the resonant stage and the TV circuitry. In
the half bridge maximum operating switching frequency is measured.
Figure 40.
No load operation at 115 Vac - 60 Hz Figure 41.
No load operation at 115 Vac - 60 Hz
- L6599A signals
CH1: HB voltage CH4: PFC drain voltage CH1: HB voltage
CH3: Standby (pin #5)
CH2: CF (pin #3)
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AN3329 Functional check
Dynamic load operation and output voltage regulation
and
show the output voltage regulation in the case of load transients on both the resonant stage outputs. The waveforms have been captured applying a load transient from 0 to full load to one output while the other is delivering full load. The period of load steps has been selected very long (1 s), to allow the output voltage to reach the steady-state condition and output voltage waveforms have been captured using the DC coupling of the scope to avoid waveform distortions caused by the AC coupling. A suitable offset has been also added to waveforms in order to get the maximum resolution.
reports the output voltage regulation with a dynamic load on 24 V output while the 12 V output is delivering the 2 A rated load. It can be noted that the 24 V output voltage has a tight variation, because even considering the spikes at the current edges, it is within
+/- 4 %.
it is possible to see the output voltage regulation with a dynamic load on the 12 V output, while the 24 V output is delivering the 6 A rated load. It can be noted that the 12 V output has a very tight variation - within +/- 3 %.
Figure 42.
12 V - 2 A; 24 V 0 ÷ 6 A transition at
115 Vac - 60 Hz
Figure 43.
24 V - 6 A; 12 V 0 ÷ 2 A transition at
115 Vac - 60 Hz
CH1: +24 V O/P voltage CH2: +24 V O/P current CH1: +12 V O/P voltage CH2: +12 V O/P current
Cross regulation
and
show the output voltage cross regulation similar to previous tests but at
300 Hz load step frequency on one output, with the other delivering the rated load.
shows the simulation of the backlight and audio amplifier connected to the 24 V output. Load is varying from minimum to maximum and vice versa, as typically happens in a flat-TV because of backlight dimming and audio power amplifiers. Even in this condition, the
24 V output has a maximum deviation of
±
4 %, mainly due to the series filter inductor L4.
The 12 V output variation due to the dynamic load on 24 V (cross-regulation) is
±
2 %, therefore very tight and suitable to power properly the internal logic of the LCD panel.
In Figure 45 cross regulation between the 12 V and 24 V has been measured. In this image
the 12 V load is changing from 1 to 2 A, as may happen when powering the LCD panel, and the variation of 24 V at rated load is measured. It can be noted in the image that the 12 V output has a deviation less than
± load on 12 V (cross-regulation) is
1.2 %, while the 24 V output variation due to the dynamic
±
0.5 %.
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Functional check
Figure 44.
12 V - 2 A; 24 V 0 ÷ 6 A - 300 Hz transition at 115 Vac - 60 Hz
AN3329
Figure 45.
24 V - 6 A; 12 V 1 ÷ 2 A - 300 Hz transition at 115 Vac - 60 Hz
CH2: +12 V O/P voltage CH3: +24 V O/P voltage
CH4: +24 V O/P current
CH2: +12 V O/P voltage CH3: +24 V O/P voltage
CH4: +12 V O/P current
24/47
Overcurrent and short-circuit protection
The L6599A is provided with a current sensing input (pin #6, ISEN) and a dedicated overcurrent management system. Current flowing in the resonant tank is detected and the signal is fed into the ISEN pin, which is internally connected to a first comparator, referenced to 0.8 V, and to a second comparator referenced to 1.5 V. If the voltage externally applied to the pin exceeds 0.8 V, the first comparator is tripped causing an internal switch to be turned on and discharge the soft-start capacitor CSS, increasing the switching frequency and so limiting the output power, while the second, referenced to 1.5 V, latches the L6599A, protecting the circuit against dead short-circuit. These two comparators, together with the
DELAY pin (#2) are dedicated to offering the possibility of implementing the overload protection in either auto-restart or latch mode, according to the whole equipment needs. In this case, being a flat TV, the final application to which this demonstration board is dedicated, the desired overload and short protection is latched.
If the 12 V output is failing short-circuit as in Figure 46 , the ISEN pin (#6) voltage rapidly
rises over 1.5 V, triggering the second comparator of the overcurrent protection. In this case, as shown, the protection intervention is very quick, protecting properly the circuit. Then, the
L6599A shuts down and operation can be resumed after an off-on signal or a mains voltage
details of half bridge voltage and current during the higher current peaks have been captured, showing the correct ZVS operation by the circuit.
If the 24 V output is failing shorts (
), the L6599A ISEN pin reaches 0.8 V, triggers the first comparator, and the capacitor C10 connected to the DELAY and DIS pins, starts being charged by an internal 150 µA current generator while the soft-start capacitor C21 is discharged, increasing the switching frequency to limit the output power. When the voltage on the DELAY and DIS pins reaches 1.85 V, an internal comparator is triggered, then the
L6599A is shut down and its consumption is reduced. The PFC_STOP pin is pulled down.
The capacitor C10 is discharged by the external resistor R12. The latch condition is kept until the L6599A Vcc drops below the UVLO. Therefore, to resume the operation an off-on
signal or a mains voltage recycling is necessary. Figure 48
details HB switching transitions as soon as the short is detected, where the borderline between inductive and capacitive mode could be critical. As can be seen, the resonant current has the correct polarity during both HB transitions and the converter is properly working in the inductive region even in this case.
Doc ID 18376 Rev 1
AN3329 Functional check
Figure 46.
12 V short-circuit at full load and
115 Vac - 60 Hz
Figure 47.
12 V short-circuit at full load and
115 Vac - 60 Hz - detail
CH1: HB voltage
CH3: ISEN (pin #6)
CH2: DELAY (pin #2)
CH4: 12 V O/P current
CH1: HB voltage
CH4: C39 current
CH3: ISEN (pin #6)
Figure 48.
24 V short-circuit at full load and
115 Vac - 60 Hz
Figure 49.
24 V short-circuit at full load and
115 Vac - 60 Hz - detail
CH1: HB voltage
CH3: ISEN (pin #6)
CH2: DELAY (pin #2)
CH4: 12 V O/P current
CH1: HB voltage
CH4: C39 current
CH3: ISEN (pin #6)
Doc ID 18376 Rev 1 25/47
Functional check AN3329
Startup
shows waveforms during startup at 115 Vac and full load of PFC and resonant stages. It is possible to note the sequence of the two stages; once the on/off signal is asserted high, voltage on C44 increases up to the Vcc turn-on thresholds of the L6564 and
L6599A. The PFC starts first and its output voltage starts increasing from the mains rectified voltage to its nominal value. In the meantime, the L6599A is kept inactive by the LINE pin
(#7) until the PFC voltage reaches the nominal output voltage, corresponding to 1.24 V on
the LINE pin, then the resonant converter is enabled and starts switching. Figure 53 reports
details of initial operation by the half bridge. It can be noted that the initial HB pulses are shorter than the following ones, and the resonant tank current has the correct polarity. This is achieved by means of the circuit R29, D8, C23, and R23, connected to the L6599A CF pin
(#3). The purpose of this circuit is to provide an asymmetric operation by the half bridge
MOSFETs during the initial pulses to prevent hard switching operation that may occur because the resonant capacitor C39 is discharged, and could damage the half bridge
MOSFETs.
Figure 50.
Startup by on-off signal at full load and 115 Vac - 60 Hz
Figure 51.
Startup by on-off signal at full load and 115 Vac - 60 Hz - L6599A signals
CH1: HB voltage
CH3: V_C44
CH2: PFC drain
CH4: On/off signal
CH1: HB voltage
CH3: LVG (pin #11)
CH2: LINE (pin #7)
CH4: C39 current
In
Figure 52 the rising of the output voltages at startup has been captured. Note that the
output voltages are reaching the steady-state level after ~90 ms when the on/off signal has been asserted high. The rising of the output voltages, controlled by C21 (CSS capacitor), is monotonic, regular, and without overshoots.
details the PFC and resonant converter turn-off. Note that after the on/off signal has been asserted low, the V_C44 decreases down to the L6564 and L6599A respective
Vcc UVLO voltages and both converters stops switching correctly, without restarting attempts.
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AN3329 Functional check
Figure 52.
Startup by on/off signal at full load and 115 Vac - 60 Hz O/P voltage rising
Figure 53.
Turn-off at full load and 115 Vac - 60
Hz by on/off signal
CH1: On/off signal
CH3: 24 V output
CH2: CSS (pin #1)
CH4: 12 V output
CH1: HB voltage
CH3: V_C44
CH2: PFC drain
CH4: On/off signal
Overvoltage protection
and
show the OVP response, observed opening the resonant stage feedback loop. Upon an overvoltage condition of either 24 V or 12 V output, the Zener diodes D16 and
D17 are reverse-biased and conduct respectively, forcing Q10 on by the resulting base current, which causes Q9 to conduct shorting to ground the anode of the U5 optocoupler and the disappearance of V_C44. Therefore, the L6564 and the L6599A are not powered.
The two transistors mentioned form a pnp-npn SCR structure that force the PFC and resonant converter to be latched off until the 5 V standby is removed by a mains voltage recycling. In the case of an open loop event, the 12 V and 24 V outputs reach 14.16 V and
28.26 V respectively.
Figure 54.
OVP at full load and 115 Vac - 60 Hz on 12 V - 24 V
Figure 55.
OVP at full load and 115 Vac - 60 Hz on 12 V - 24 V - outputs detail
CH1: HB voltage
CH3: V_C53
CH2: PFC drain
CH4: V_C44
CH1: 24 V output
CH3: V_C53
CH2: 12 V output
CH4: V_C44
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Functional check AN3329
Mains sags/dips
and
show the converter behavior in the case of half-cycle (8.3 ms) or a complete cycle (16.6 ms) mains dip. As can be noted, in both cases the PFC output voltage drops but the L6599A still works correctly, and output voltages do not show any disturbance, therefore demonstrating a good immunity of the circuit against mains dips.
Figure 56.
Half cycle mains dip at full load and
115 Vac - 60 Hz
Figure 57.
Full cycle mains dip at full load and
115 Vac - 60 Hz
CH1: HB voltage
CH3: 24 V output
CH2: PFC drain
CH4: PFC gate
CH1: HB voltage
CH3: 24 V output
CH2: PFC drain
CH4: PFC gate
28/47 Doc ID 18376 Rev 1
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