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Appendix A ICS board support package
ICS board support package
A.1 Introduction
The ICS BSP is used to configure SoC specific information such as Mailbox addresses and reset registers in order for ICS to function. It also contains the CPU mapping table that is used to map CPU names onto their logical CPU numbers.
Currently ICS is supplied with BSPs for a limited set of SoCs, see the Release notes for further details.
However, it is fairly simple to create a BSP for other SoCs. The BSP code can be found in source/src/bsp
.
Taking the STi7200 as an example, we have: stx7200/cores.c
stx7200/st40/mbox.c
stx7200/st40/name.c
stx7200/st40/reset.c
stx7200/st40/sti7200reg.h
stx7200/st231/audio0/mbox.c
stx7200/st231/audio0/name.c
stx7200/st231/audio1/mbox.c
stx7200/st231/audio1/name.c
stx7200/st231/video0/mbox.c
stx7200/st231/video0/name.c
stx7200/st231/video1/mbox.c
stx7200/st231/video1/name.c
The format and content of these BSP files is straight forward and the supplied BSPs can be used as a template for creating new ones. The SoC specific header file sti7200reg.h can be copied directly from the ST40 Micro Toolset, example directory.
In order for the OS21 BSP to be built by Multicom then the new SoC and core names must be added to the relevant makefiles in the BSP directory, for example: makebspst40.inc
makebspst231.inc
For the Linux kernel module build, the new BSP files need to be added to: source/src/ics/Makefile
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Note:
A.2
Note:
The Multicom 4 library can also be built using the external BSP source directory specified by the BSP_SRCDIR make environment variable. This directory should have exactly the same directory hierarchy and file locations as the one in the Multicom 4 source tree. The included files makebspst40.inc and makebspst231.inc can then be modified to specify the new SoC BSPs.
The BSP_INCDIR environment variable can also be used to supply an external include directory, during compilation of the external BSP.
Under the Linux kernel the original Multicom 4 source/src/ics/Makefile directory still needs to be modified to specify the new SoC. All the BSP files can be located in the external
BSP directory.
The BSP_SRCDIR and BSP_INCDIR paths supplied during the building of the ICS Linux kernel module must be relative to the Multicom 4 source tree source/src/ics directory.
BSP data structures
This section describes each of the BSP data structures for CPU, mailbox, reset and boot addresses.
The data structures for the reset and boot addresses are defined for each CPU. It is important therefore that the order of the entries defined for the table of CPUs (described in
Section A.2.1
) are synchronized with the order of entries for the reset and boot address
structures (defined in reset.c) and listed in
Section A.2.3
.
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This data structure defines an entry in the CPU name table. The CPU table is used to map
CPU core names onto their logical CPU numbers.
struct bsp_cpu_info
{
char *name;
char *type;
int num;
unsigned int flags;
}; name type num flags
Table 28. CPU name table structure
Structure member name Description
CPU core name, for example, “estb” or “audio”
CPU architecture, for example, “st40 or “st231”
Logical CPU number for this core (-ve to disable)
Various flag bits
The order of the CPU definitions in this table must match that used in the CPU boot and
reset tables in reset.c.
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The BSP declaration of this table are normally found in the top level cores.c file so that they are shared across all the CPU cores.
The following declarations need to be made in the BSP (normally found in cores.c); extern unsigned int bsp_cpu_count; extern struct bsp_cpu_info bsp_cpus[];
Where bsp_cpus is the array of CPU definitions and bsp_cpu_count is set to the number of entries in that array.
Note:
A.2.3
This structure defines an individual Mailbox entry. Each mailbox entry defines a set of 4 x
32-bit mailbox registers. For local mailboxes, an interrupt request number (or address on
OS21) should be provided so that interrupts can be accepted on that set of mailboxes. For non-local mailboxes (that is, mailboxes owned by other CPUs) then this should be set to 0.
Each Mailbox IP on the SoC actually provides two independent sets of 4 x 32-bit mailbox registers. The second set is at offset 0x100 from the base address of the Mailbox IP.
struct bsp_mbox_regs
{
void *base;
unsigned int interrupt;
unsigned int flags;
}; base flags
Table 29. Mailbox table structure
Structure member name Description
interrupt
Physical base address of the mailbox set
Interrupt request number (or address on OS21) associated with this mailbox, if local. Set to 0 for remote mailboxes
Various flag bits
The following declarations need to be made in the BSP (normally found in mbox.c); extern unsigned int bsp_mailbox_count; extern struct bsp_mbox_regs bsp_mailboxes[];
Where bsp_mailboxes is the array of mailbox definitions and bsp_mailbox_count is set to the number of entries in that array.
Reset and boot addresses
These data structures are used to define, for each CPU, the core reset and boot information so that ICS can load and start each CPU. The entries in these tables must be synchronized
with entries in the CPU table, described in
Section A.2.1 on page 202
.
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Boot address
/* Boot address info */
struct bsp_boot_address_reg
{
volatile unsigned int *address;
int leftshift;
unsigned int mask;
}; mask
Table 30. Boot address structure
Structure member name Description
address leftshift
For each CPU, SYSCONF boot register address
Left-shift to be applied to boot address
Mask to be applied to boot address
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Reset address
struct bsp_reg_mask
{
volatile unsigned int *address;
unsigned int mask;
unsigned int value;
}; mask value
Table 31. Register address structure
Structure member name Description
address
Register SYSCONF address
Mask to be applied to register
Data value to be applied to the register
The following declarations need to be made in the BSP (normally found in reset.c); extern struct bsp_boot_address_reg bsp_sys_boot_registers[]; extern struct bsp_reg_mask bsp_sys_reset_bypass; extern unsigned int bsp_sys_reset_bypass_count; extern struct bsp_reg_mask bsp_sys_boot_enable[]; extern struct bsp_reg_mask bsp_sys_reset_registers[];
Where bsp_boot_address_registers is an array of boot address definitions for each
CPU core in the SoC.
The bsp_sys_reset_bypass array defines all the SYSCONF boot reset bypass registers and bit patterns necessary to allow individual CPUs to be reset. The bsp_sys_reset_bypass_count
variable should be set to the number of entries in this array.
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A.2.4
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The bsp_sys_boot_enable table defines for each CPU, the SYSCONF boot enable registers and bit pattern to cause each CPU to boot.
The bsp_sys_reset_registers table defines for each CPU, the SYSCONF reset registers and bit patterns to cause each CPU to be reset. By setting an array entry value member to 0, the reset logic applies mask followed by ~mask to the register.
Normally these BSP declarations are only supplied in the ST40/sh4 BSPs as they are usually responsible for the reset and loading of the other CPU cores.
These tables and the associated macro header file are normally copied directly from the
ST40 Micro Toolset examples directory.
CPU core name
extern const char * bsp_cpu_name;
This is a CPU core declaration and is usually found in the name.c BSP file for each CPU core. It should be set to the ASCII CPU core name of the corresponding CPU and must match one of the CPU names found in the bsp_cpus[] table.
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A.3
Note:
Example BSP template
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The following example BSP template is for the MB628/STx7141 based platform/SoC.
Only the templates for the estb and audio CPUs are included.
/* Filename: stx7141/cores.c */
struct bsp_cpu_info bsp_cpus[] =
{
{
.name = "estb",/* eSTB */
.type = "st40",
.num= 0, /* MASTER */
.flags= 0,
},
{
.name = "ecm",/* eCM */
.type = "st40",
.num= 3,
.flags= 0,
},
{
.name = "audio",/* audio */
.type = "st231",
.num= 2,
.flags= 0,
},
{
.name = "video",/* video */
.type = "st231",
.num= 1,
.flags= 0,
},
}; unsigned int bsp_cpu_count = sizeof(bsp_cpus)/sizeof(bsp_cpus[0]);
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/* Filename stx7141/st40/estb/mbox.c */
#define MBOX0_ADDR 0xfe211000
#define MBOX1_ADDR 0xfe212000
#define MBOX2_ADDR 0xfe211800
#define MBOX3_ADDR 0xfe212800
#ifdef __os21__
#include <os21/st40/sti7141.h>
#define VIDEO_MBOX_IRQ((unsigned int) &OS21_INTERRUPT_MBOX0_SH4_IRQ)/* MBOX0 SET2 */
#define ECM_MBOX_IRQ ((unsigned int) &OS21_INTERRUPT_MBOX2_SH4_IRQ)/* MBOX2 SET2 */
#define AUDIO_MBOX_IRQ((unsigned int) &OS21_INTERRUPT_MBOX1_SH4_IRQ)/* MBOX1 SET2 */
#define ESTB_MBOX_IRQ((unsigned int) &OS21_INTERRUPT_MBOX3_LX_DH_IRQ)/* MBOX3 SET1 */
#endif
#ifdef __KERNEL__
/* Based on a ILC3 base of 65 + offsets in ADCS 8071978 (Table 10) */
#define VIDEO_MBOX_IRQ(65 + 9)/* MBOX0 SET2 */
#define ECM_MBOX_IRQ (65 + 13)/* MBOX2 SET2 */
#define AUDIO_MBOX_IRQ(65 + 11)/* MBOX1 SET2 */
#define ESTB_MBOX_IRQ (65 + 14)/* MBOX3 SET1 */
#endif struct bsp_mbox_regs bsp_mailboxes[] =
{
{
.base= (void *) (MBOX0_ADDR), /* Video LX Mailbox (MBOX0.1) */
.interrupt= 0,/* Video owns SET1 */
.flags = 0
},
{
.base= (void *) (MBOX0_ADDR+0x100), /* Video LX Mailbox (MBOX0.2) */
.interrupt= VIDEO_MBOX_IRQ,/* *WE* own SET2 */
.flags = 0
},
{
.base= (void *) (MBOX2_ADDR), /* ST40 ECM Mailbox (MBOX2.1) */
.interrupt= 0,/* ECM owns SET1 */
.flags = 0
},
{
.base= (void *) (MBOX2_ADDR+0x100),/* ST40 ECM Mailbox (MBOX2.2) */
.interrupt= ECM_MBOX_IRQ,/* *WE* own SET2 */
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.flags = 0
},
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{
.base= (void *) (MBOX1_ADDR),/* Audio LX Mailbox (MBOX1.1) */
.interrupt = 0,/* Audio owns SET1 */
.flags = 0
},
{
.base= (void *) (MBOX1_ADDR+0x100),/* Audio LX Mailbox (MBOX1.2) */
.interrupt = AUDIO_MBOX_IRQ,/* *WE* own SET2 */
.flags = 0
},
{
.base= (void *) (MBOX3_ADDR),/* ST40 ESTB Mailbox (MBOX3.1) */
.interrupt = ESTB_MBOX_IRQ,/* *WE* own SET1 */
.flags = 0
},
{
.base= (void *) (MBOX3_ADDR+0x100),/* ST40 ESTB Mailbox (MBOX3.2) */
.interrupt = 0,/* ECM owns SET2 */
.flags = 0
},
}; unsigned int bsp_mailbox_count = sizeof(bsp_mailboxes)/sizeof(bsp_mailboxes[0]);
/* Filename: stx7141/st231/audio/mbox.c
#include <bsp/_bsp.h>
#define MBOX0_ADDR 0xfe211000
#define MBOX1_ADDR 0xfe212000
#define MBOX2_ADDR 0xfe211800
#define MBOX3_ADDR 0xfe212800
#include <os21/st200/sti7141.h> struct bsp_mbox_regs bsp_mailboxes[] =
{
{
.base= (void *) (MBOX0_ADDR), /* Video LX Mailbox (MBOX0.1) */
.interrupt= 0,
.flags = 0
},
{
.base= (void *) (MBOX0_ADDR+0x100), /* Video LX Mailbox (MBOX0.2) */
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.interrupt= 0,
.flags = 0
},
{
.base= (void *) (MBOX2_ADDR), /* ST40 ECM Mailbox (MBOX2.1) */
.interrupt= 0,
.flags = 0
},
{
.base= (void *) (MBOX2_ADDR+0x100), /* ST40 ECM Mailbox (MBOX2.2) */
.interrupt= 0,
.flags = 0
},
{ .base= (void *) (MBOX1_ADDR),/* Audio LX Mailbox (MBOX1.1) */
.interrupt = (unsigned int) &OS21_INTERRUPT_MAILBOX,/* *WE* own this one */
.flags = 0
},
{ .base= (void *) (MBOX1_ADDR+0x100),/* Audio LX Mailbox (MBOX1.2) */
.interrupt = 0,
.flags = 0
},
A.3.3
{ .base= (void *) (MBOX3_ADDR),/* ST40 ESTB Mailbox (MBOX3.1) */
.interrupt = 0,
.flags = 0
},
{ .base= (void *) (MBOX3_ADDR+0x100),/* ST40 ESTB Mailbox (MBOX3.1) */
.interrupt = 0,
.flags = 0
},
}; unsigned int bsp_mailbox_count = sizeof(bsp_mailboxes)/sizeof(bsp_mailboxes[0]);
Reset and boot addresses
/* Filename: stx7141/st40/reset.c /*
#include <bsp/_bsp.h>
#include "sti7141reg.h"
/* Reset bypass mask must not unset masked eCM reset as reset will be asserted. */ struct bsp_reg_mask bsp_sys_reset_bypass[] = {
{STI7141_SYSCONF_SYS_CFG08, ~(1 << 3), (1 << 4) | (1 << 3)},
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{STI7141_SYSCONF_SYS_CFG09, ~((1 << 28) | (1 << 27)), (1 << 27)}
};
/* Size of the above array */ unsigned int bsp_sys_reset_bypass_count = sizeof(bsp_sys_reset_bypass)/sizeof(bsp_sys_reset_bypass[0]); struct bsp_boot_address_reg bsp_sys_boot_registers[] = {
{STI7141_SYSCONF_SYS_CFG08, 3, 0xFFFF0000}, /* eSTB */
{STI7141_SYSCONF_SYS_CFG04, 3, 0xFFFF8000}, /* eCM */
{STI7141_SYSCONF_SYS_CFG26, 0, 0xFFFFFF00}, /* audio */
{STI7141_SYSCONF_SYS_CFG28, 0, 0xFFFFFF00} /* video */
}; struct bsp_reg_mask bsp_sys_boot_enable[] = {
{STI7141_SYSCONF_SYS_CFG08, ~1, 1},/* eSTB */
{STI7141_SYSCONF_SYS_CFG08, ~2, 2},/* eCM */
{STI7141_SYSCONF_SYS_CFG26, ~1, 1},/* audio */
{STI7141_SYSCONF_SYS_CFG28, ~1, 1}/* video */
}; struct bsp_reg_mask bsp_sys_reset_registers[] = {
{STI7141_SYSCONF_SYS_CFG08, ~(1 << 6), 1 << 6},/* eSTB */
{STI7141_SYSCONF_SYS_CFG08, ~(1 << 7), 1 << 7},/* eCM */
{STI7141_SYSCONF_SYS_CFG27, ~1, 1}, /* audio */
{STI7141_SYSCONF_SYS_CFG29, ~1, 1} /* video */
};
A.3.4 CPU core name
/* Filename: stx7141/st40/estb/name.c /*
#include <bsp/_bsp.h> const char * bsp_cpu_name = "estb";
Filename: stx7141/st231/audio/name.c
#include <bsp/_bsp.h> const char * bsp_cpu_name = "audio";
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