STMicroelectronics ST200-TOOLSET User Manual
The STMicroelectronics ST200-TOOLSET provides a comprehensive suite of development tools for the ST200 microcontroller, enabling efficient software creation and debugging. With this toolset, you can harness the capabilities of the ST200, a powerful 32-bit processor, to develop embedded applications with ease.
تبلیغات
تبلیغات
UM1428
User manual
OS21 for ST200
Note:
Introduction
The API defined in the OS21 User manual (7358306) encapsulates the generic facilities offered by OS21 on all target platforms. However each processor implements certain features in different ways, and some processors offer facilities appropriate to their own specific API.
ST200 specific APIs can be accessed by a single #include :
#include <os21/st200.h>
This include file is automatically included from <os21.h> when __ST200__ is defined.
The ST200 compiler always defines __ST200__; therefore #include <os21.h> is normally all that is necessary to include both the generic OS21 API and the ST200 specific
API.
The only variant of the ST200 currently supported is the ST231.
January 2015 7410372 Rev 12
www.st.com
1
Contents
Contents
UM1428
Memory access overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Initializing the SCU support system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Managing the SCU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
SCU header files: os21/st200/scu.h . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Mailbox overview and definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Board support packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Board support packages overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
BSP interrupt system description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Interrupt system initialization flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7410372 Rev 12
UM1428
Preface
Preface
Document identification and control
Each book carries a unique identifier of the form: nnnnnnn Rev x where nnnnnnn is the document number, and x is the revision.
Whenever making comments on a document, the complete identification Doc ID nnnnnnn
Rev x should be quoted.
Conventions used in this guide
General notation
The notation in this document uses the following conventions:
sample code , keyboard input and file names ,
variables and code variables
,
code comments
,
screens , windows and dialog boxes,
instructions .
Hardware notation
The following conventions are used for hardware notation:
REGISTER NAMES and FIELD NAMES,
PIN NAMES and SIGNAL NAMES.
Software notation
Syntax definitions are presented in a modified Backus-Naur Form (BNF). Briefly:
1.
Terminal strings of the language, that is, strings not built up by rules of the language are printed in teletype font. For example, void .
2. Nonterminal strings of the language, that is, strings built up by rules of the language are printed in italic teletype font. For example, name
.
3. If a nonterminal string of the language starts with a nonitalicized part, it is equivalent to the same nonterminal string without that nonitalicized part. For example, vspacename
.
4. Each phrase definition is built up using a double colon and an equals sign to separate the two sides (‘ ::= ’).
5. Alternatives are separated by vertical bars (‘ | ’).
6. Optional sequences are enclosed in square brackets (‘ [ ’ and ‘ ] ’).
7. Items which may be repeated appear in braces (‘ { ’ and ‘ } ’).
7410372 Rev 12
3
Memory access UM1428
1.1
1.2
Memory access overview
On the ST231, memory regions can be given various characteristics such as cacheability, protection modes and speculation behavior. Memory region characteristics are controlled by a Memory Management Unit (MMU) and a Speculative Control Unit (SCU).
Exact details of the MMU and SCU hardware can be found in the appropriate hardware manuals.
OS21 provides three areas of memory access support.
Cache support functions are available. Details are given in the OS21 User Manual
(7358306).
MMU support functions are provided using the Virtual Memory API. Details are given in the OS21 User Manual (7358306).
SCU support functions are available. Details are provided in this manual; see
SCU support functions
The ST231 includes a Speculative Control Unit (SCU) which holds the physical address ranges from which speculative (dismissable) loads and prefetches are allowed to proceed.
Dismissable loads to addresses outside those ranges are aborted and return zero, whilst prefetches to addresses outside those ranges are canceled.
There are no entries in the SCU when the ST231 first comes out of reset. The C run-time boot sequence programs the SCU with a "default" programming that is appropriate for the given hardware.
OS21 does not change this default programming, but it does provide an API that enables the user to change it if necessary.
7410372 Rev 12
UM1428 Memory access
1.2.3
OS21 provides three functions to add, remove and examine the entries. These are: int scu_enable_range (void * startAddr, unsigned int length); int scu_disable_range (void * startAddr); int scu_data (scu_data_t * sdp);
SCU header files: os21/st200/scu.h
All the definitions relating to the SCU are in the header file os21/st200/scu.h
provides a list of the functions and
a list of the types defined in this header file.
Function
Table 1. Functions defined in os21/st200/scu.h
Description scu_enable_range() scu_disable_range() scu_data()
Adds a new address range into the SCU.
Removes an existing address range from the SCU.
Provides a list of the current SCU entries.
Type scu_entry_t scu_data_t
Table 2. Types defined in os21/st200/scu.h
Description
An SCU entry.
A collection of SCU entries.
7410372 Rev 12
8
Memory access UM1428
1.3 scu_data
Alphabetical list of functions
Definition:
Return details of the current SCU entries
#include <os21/st200/scu.h> int scu_data (scu_data_t * sdp);
Arguments:
Returns:
Errors:
Context:
Description: sdp A pointer to a structure of type scu_data_t . The returned data is stored in this structure.
OS21_SUCCESS on success, OS21_FAILURE on failure.
Returns OS21_FAILURE if a NULL pointer is passed.
Callable from task only.
This function fills in the struct pointed to by sdp with details of the current SCU entries. On successful return from the function:
– sdp->numEntries gives the number of valid SCU entries
– sdp->scuEntries[n] contains data for each of the entries
– sdp->scuEntries[n].startAddress
contains the start address of the entry
– sdp->scuEntries[n].length
contains the length of the entry
7410372 Rev 12
UM1428 Memory access
scu_disable_range
Remove an address range from the SCU
Definition: #include <os21/st200/scu.h> int scu_disable_range (void * startAddr);
Arguments: startAddr The start address of the address range.
Returns:
Errors:
Context:
Description:
OS21_SUCCESS on success, OS21_FAILURE on failure.
Returns OS21_FAILURE if the address range defined by startAddr is not found in the SCU.
Callable from task only.
This function removes the entry in the SCU that matches the given start address. The start address only has to match the significant bits stored in the SCU.
7410372 Rev 12
8
Memory access UM1428
scu_enable_range
Add a new address range into the SCU
Definition: #include <os21/st200/scu.h> int scu_enable_range (void * startAddr, unsigned int length);
Arguments: startAddr The start address of the address range.
length The length of the address range.
Returns:
Errors:
Context:
Description:
OS21_SUCCESS on success, OS21_FAILURE on failure.
Returns OS21_FAILURE if:
– an invalid address range is supplied
– if the address range overlaps with another SCU entry
– if there are no free entries in the SCU
Callable from task only.
This function attempts to add the address range specified by startAddr and length to the SCU. If the address range is successfully added, the SCU enables speculation on this range. There are no mandatory address alignment requirements for this function, although in order to satisfy the request a larger range than actually specified may be added to the SCU. This is due to the fact that the SCU only holds the most significant bits of the address instead of the whole address.
7410372 Rev 12
UM1428
2 Timers
Timers
2.2
2.3
2.4
The ST200 has three independent timers. Each is capable of running as a free running auto-reload 32-bit counter, with interrupt on underflow. Each can be programmed to count some fraction of the input clock. The greatest accuracy is obtained by counting based on a large fraction of the input clock, and running that clock at high frequency.
Input clock frequency
The precise speed of the input clock is determined by the end user; it is a function of the board design and boot software. OS21 is not responsible for setting the input speed, therefore it has to be made aware of what it is.
This is done with the Board Support Package (BSP), using a function called bsp_timer_input_clock_frequency_hz() . Full details of this function can be found in OS21 User manual (7358306), chapter 16.
OS21 tick duration
OS21 establishes the period of one tick when it boots. Based on the input clock frequency it selects an appropriate divisor to yield a tick which is approximately 10 microseconds.
ST200 timer assignments
OS21 uses all three ST200 timers, as shown in
.
Timer name
Table 3. ST200 timer assignments
OS21 usage
Timer0
Timer1
Timer2
System timer
Timeslice and profiling timer
Timeout timer
The system timer is left free running and is used by time_now() to return the system time.
On ST200, the system time ( osclock_t ) is a 64-bit value. OS21 maintains the top 32 bits of the 64-bit time via an interrupt handler which is called each time the 32-bit timer reaches zero. The lower 32 bits of the system time are the value in the system timer.
The timeslice timer is programmed to run for the timeslice period before generating an interrupt and reloading. This is used to drive timeslice events into the task scheduler.
The timeout timer is programmed on demand to interrupt when the required number of ticks have elapsed. When multiple timeouts are requested OS21 orders which timeout should occur next, and programs the timeout timer appropriately.
7410372 Rev 12
9
Mailbox
3 Mailbox
3.1
UM1428
Mailbox overview and definition
Since the support of OS21U (several virtual OS21 User instance running on a single st231), communications between VMs throught software irq is implemented. Moreover the available APIs are useable to set up communication between processor (i.e cortex A9 ) and an OS21u instance through an hardware Mailbox.
A mailbox handle sets up full duplex notification capabilities between an os21u instance and a remote processor.
The following section describes the mailbox API to set up such communication.
The APIs listed in
are available in os21/mailbox.h
.
Table 4. Functions defined in os21/mailbox.h
Function Description mailbox_t * mailbox_handle(char
*name)
Obtain an mailbox handle given an mailbox name.
int mailbox_install (mailbox_t *mbx, mailbox_handler_t callback, void * param)
Install a call back handler for a mailbox .
int mailbox_uninstall
(mailbox_tmailbox_t *mbx)
Remove a handler for a mailbox .
int mailbox_enable (mailbox_t *mbx) Enable notification on local mailbox .
int mailbox_disable (mailbox_t *mbx) Disable notification on local mailbox .
int mailbox_poll (mailbox_t *mbx, int
* valuep)
Poll local mailbox .
int mailbox_clear (mailbox_t *mbx) Clear local mailbox .
int mailbox_raise (mailbox_t *mbx) Notify local mailbox .
int mailbox_kick (mailbox_t *mbx) Notify remote mailbox .
10/10 7410372 Rev 12
UM1428
Table 5. Types defined in os21/mailbox.h
Type Description mailbox hande mailbox_t typedef int (*mailbox_handler_t)
(void * param )
Mailbox call back handler
Mailbox
7410372 Rev 12 11/10
11
Board support packages
4 Board support packages
4.1
UM1428
Board support packages overview
OS21 Board Support Packages (BSPs) are supplied for all supported platforms as both prebuilt libraries, and accompanying sources. Details of the generic features of the BSPs can be found in the OS21 User manual (7358306), chapter 16.
This section describes the platform specific features of the BSP, which for the ST200 consists of only the interrupt system description.
The BSP is responsible for describing the interrupt system to OS21. This coupled with the platform specific interrupt code implements OS21's generic interrupt API. On the ST200 this comprises the following elements:
interrupt names
interrupt table
ILC table
ILC base address
interrupt system initialization flags
A type is provided by OS21 called interrupt_name_t . Each interrupt is assigned a unique name ( interrupt_name_t ) which allows it to be identified both in the BSP interrupt tables that follow, and in the interrupt API. The BSP need only contain those interrupts that are used by other OS21 or the application code.
If any interrupts are missing then a linker error occurs. If interrupts are declared in the BSP but are subsequently not used, then this does no harm other than use memory. For example:
/* Define a DMA interrupt in the BSP */
interrupt_name_t OS21_INTERRUPT_DMA_0 = 21;
Header files are provided with OS21 which complement the interrupt description in the BSP.
By including the appropriate header file, all the relevant external interrupt_name_t declarations are obtained. User code is also free to declare only those interrupt names that it requires. For example:
/* How to access the DMA interrupt in user code */
extern interrupt_name_t OS21_INTERRUPT_DMA_0;
The interrupt_handle() function takes an interrupt_name_t parameter and returns a handle to the given interrupt.
7410372 Rev 12
UM1428 Board support packages
These tables are expected by the OS21 platform specific interrupt API implementation code, and describe the interrupt system. For the ST200, two tables are required. One is for the interrupt controller and the other is for an optional interrupt level controller. The complete specification for the interrupt system BSP is as follows:
/* An entry in the interrupt table. */ typedef struct interrupt_table_entry_t
{
interrupt_name_t * namep;
unsigned int controller;
unsigned int reg_set;
unsigned int bit_set;
} interrupt_table_entry_t;
This describes interrupts which are routed to interrupt controllers. It is a list of interrupts that arrive to a given controller.
namep is a pointer to the name of the interrupt. controller specifies the interrupt controller that the interrupt arrives on (only OS21_CTRL_INTC is supported on the ST200). reg_set is the number of the register set to which the interrupt is routed. Currently interrupts are routed to two registers on the interrupt controller. OS21 numbers these 0 or 2
(which refers to an offset in memory). 1 is currently unused. bit_set is the bit number within this register.
This table allows OS21 to locate an appropriate bit in the INTC which maps to the named interrupt. For example: interrupt_name_t OS21_MY_INTERRUPT = 21; interrupt_table_entry_t my_interrupt = { &OS21_MY_INTERRUPT,
OS21_CTRL_INTC, 2, 15 };
This describes an interrupt called OS21_MY_INTERRUPT which is routed into bit 15 of register 2 of each bank of registers of the interrupt controller INTC.
interrupt_table_entry_t bsp_interrupt_table [];
7410372 Rev 12
16
Board support packages UM1428
This describes the set of interrupts that arrive at the INTC. It comprises a list of interrupt_table_entry_t types. For example: interrupt_table_entry_t bsp_interrupt_table[] =
{
{ &OS21_INTERRUPT_TIMER_0, OS21_CTRL_INTC, 0, 0 },
{ &OS21_INTERRUPT_TIMER_1, OS21_CTRL_INTC, 0, 1 },
{ &OS21_INTERRUPT_TIMER_2, OS21_CTRL_INTC, 0, 2 },
{ &OS21_INTERRUPT_ILC_0, OS21_CTRL_INTC, 2, 4 },
{ &OS21_INTERRUPT_ILC_1, OS21_CTRL_INTC, 2, 5 },
{ &OS21_INTERRUPT_ILC_2, OS21_CTRL_INTC, 2, 6 },
{ &OS21_INTERRUPT_ILC_3, OS21_CTRL_INTC, 2, 7 },
{ &OS21_INTERRUPT_ILC_4, OS21_CTRL_INTC, 2, 8 },
{ &OS21_INTERRUPT_ILC_5, OS21_CTRL_INTC, 2, 9 },
{ &OS21_INTERRUPT_ILC_6, OS21_CTRL_INTC, 2, 10 },
{ &OS21_INTERRUPT_ILC_7, OS21_CTRL_INTC, 2, 11 },
{ &OS21_INTERRUPT_ILC_8, OS21_CTRL_INTC, 2, 12 },
{ &OS21_INTERRUPT_ILC_9, OS21_CTRL_INTC, 2, 13 },
{ &OS21_INTERRUPT_ILC_10, OS21_CTRL_INTC, 2, 14 },
{ &OS21_INTERRUPT_ILC_11, OS21_CTRL_INTC, 2, 15 },
{ &OS21_INTERRUPT_ILC_12, OS21_CTRL_INTC, 2, 16 },
{ &OS21_INTERRUPT_ILC_13, OS21_CTRL_INTC, 2, 17 },
{ &OS21_INTERRUPT_ILC_14, OS21_CTRL_INTC, 2, 18 },
{ &OS21_INTERRUPT_ILC_15, OS21_CTRL_INTC, 2, 19 }
};
This describes a basic system with three timer interrupts, and sixteen ILC interrupts. The
ILC interrupts arrive from the Interrupt Level Controller.
unsigned int bsp_interrupt_table_entries;
This specifies the number of entries in bsp_interrupt_table . It is usually set as follows: unsigned int bsp_interrupt_table_entries = sizeof
(bsp_interrupt_table) / sizeof (interrupt_table_entry_t);
/* ILC modes. */ typedef enum
{
OS21_ILC_NO_TRIGGER_0,
OS21_ILC_TRIGGER_HIGH_LEVEL,
OS21_ILC_TRIGGER_LOW_LEVEL,
OS21_ILC_TRIGGER_RISING_EDGE,
OS21_ILC_TRIGGER_FALLING_EDGE,
OS21_ILC_TRIGGER_ANY_EDGE,
OS21_ILC_NO_TRIGGER_1,
OS21_ILC_NO_TRIGGER_2,
OS21_ILC_TRIGGER_MAX
} ilc_mode_t;
7410372 Rev 12
UM1428
Note:
Note:
Board support packages
/* An entry in the ILC table. */
typedef struct ilc_table_entry_s
{
interrupt_name_t * namep;
unsigned int input : 16;
unsigned int output : 16;
ilc_mode_t mode;
} ilc_table_entry_t;
This describes interrupts that are routed through an interrupt level controller.
namep is a pointer to the name of the interrupt. input is the number of the input into the
ILC that the interrupt arrives on. output is the number of the output to which the interrupt is routed. mode describes how the interrupt is triggered. This table allows OS21 to locate the appropriate state in the INTC which maps to the named interrupt.
Output 0 of the ILC must map to OS21_INTERRUPT_ILC_0 in the INTC and so on.
For example: interrupt_name_t OS21_MY_INTERRUPT = 21; ilc_table_entry_t my_interrupt = { &OS21_MY_INTERRUPT, 1, 15,
OS21_ILC_TRIGGER_RISING_EDGE };
This describes an interrupt called OS21_MY_INTERRUPT which is routed into input 1 of the
ILC and out on output 15. Line 15 out of the ILC is asserted on the rising edge of input 1.
ilc_table_entry_t bsp_ilc_table [];
This describes the set of interrupts that arrive at the ILC. It comprises a list of ilc_table_entry_t types. For example: ilc_table_entry_t bsp_ilc_table[] =
{
{ &OS21_INTERRUPT_PIO_0, 0, 0, OS21_ILC_TRIGGER_HIGH_LEVEL },
{ &OS21_INTERRUPT_SSC_0, 7, 1, OS21_ILC_TRIGGER_HIGH_LEVEL },
{ &OS21_INTERRUPT_DMA_0, 24, 10, OS21_ILC_TRIGGER_HIGH_LEVEL },
{ &OS21_INTERRUPT_DMA_1, 25, 10, OS21_ILC_TRIGGER_HIGH_LEVEL },
{ &OS21_INTERRUPT_DMA_2, 26, 10, OS21_ILC_TRIGGER_HIGH_LEVEL },
{ &OS21_INTERRUPT_DMA_3, 27, 10, OS21_ILC_TRIGGER_HIGH_LEVEL },
{ &OS21_INTERRUPT_DMA_4, 28, 10, OS21_ILC_TRIGGER_HIGH_LEVEL },
{ &OS21_INTERRUPT_DMA_ERR, 29, 10, OS21_ILC_TRIGGER_HIGH_LEVEL }
}; unsigned int bsp_ilc_table_entries;
This variable specifies the number of entries in bsp_ilc_table . It is usually set as follows: unsigned int bsp_ilc_table_entries = sizeof (bsp_ilc_table) / sizeof
(ilc_table_entry_t);
If an ILC is not present on a given target then the bsp_ilc_table and the bsp_ilc_table_entries should be removed.
7410372 Rev 12
16
Board support packages UM1428
4.2.5 void * bsp_ilc_base_address;
This tells OS21 the base address of the ILC memory mapped registers. For example: void * bsp_ilc_base_address = (void *)(0x18300000);
If no ILC is present, this should be removed.
Interrupt system initialization flags interrupt_init_flags_t bsp_interrupt_init_flags;
This is a set of flags which are used to control how OS21 initializes the interrupt subsystem.
These may be combined by logically ORing the appropriate flags. Current ST200 flags are:
OS21_INTERRUPT_INIT_ILC_MASTER
This tells OS21 that this CPU is responsible for the programming of the interrupt level controller. When OS21 initializes the interrupt subsystem it programs the ILC as given in the table. This is used where multiple CPUs share the same ILC (only one CPU should program the ILC).
OS21_INTERRUPT_INIT_ILC_SLAVE
This tells OS21 that this CPU is not responsible for the programming of the interrupt level controller. When OS21 initializes the interrupt sub-system it does not program the
ILC as given in the table. This is used where multiple CPUs share the same ILC (only one CPU should program the ILC).
7410372 Rev 12
UM1428 Revision history
Date
Jul 2002
Mar 2003
May 2003
Oct 2003
May 2005
Jul 2006
27-Nov-2006
05-Sept-2007
13-Nov-2007
01-Oct-2009
04-Sep-2013
8-Jan-2014
Revision
Table 6. Document revision history
Changes
A
B
C
D
E
F
G
H
I
J
11
12
Initial release.
Interrupts chapter: Removed chapter.
Board support package chapter: Chapter has been rewritten.
Timers chapter: Overview, Input clock frequency and ST200 timer assignments have been rewritten.
Throughout: Updated the titles of the overview sections to make chapter specific.
Caches and memory areas chapter: Renamed as a Memory access chapter, restructured existing information and added details of memory mapping for more recent cores.
Memory access chapter: Added details of the mmap_create_identity() and mmap_translate_virtual() functions.
Memory access chapter: Added context information to all function definitions. Added details of the cache_status() function. Added the types and macros defined in os21/st200/cache.h.
Exceptions chapter: Removed chapter.
No technical changes.
Moved cache API functions to OS21 User manual (7358306), as these are now generic.
Removed the MMAP section.
Added
Section 1.2: SCU support functions on page 4 and three new
functions to
Section 1.3: Alphabetical list of functions on page 6
Moved the generic elements of the board support package to the
OS21 User manual (7358306).
Changes made to
Chapter 4: Board support packages on page 12 .
Corrected “SH4” to “ST200” in
Throughout: Changed “ST230 or later” to ST231 (as ST231 is the only variant currently supported).
In
Chapter 1 on page 4 , removed all references to ST200 variants
that are no longer supported.
Removed the chapter entitled “Register context”.
Added
7410372 Rev 12
17
Index
Index
UM1428
A access memory
. . . . . . . . . . . . . . . . . . . . . . . . .4
B
Backus-Naur Form
. . . . . . . . . . . . . . . . . . . . . . .3
base address
. . . . . . . . . . . . . . . . . . . . . . . . . .16
BSP interrupt system
. . . . . . . . . . . . . . . . . . . . . . .12
interrupt tables
. . . . . . . . . . . . . . . . . . . . . . .12
I
ILC base address
. . . . . . . . . . . . . . . . . . . . . . .16
ILC table
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
initialization flags
. . . . . . . . . . . . . . . . . . . . . . .16
input clock
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
determining speed
. . . . . . . . . . . . . . . . . . . . . .9
interrupt controller
. . . . . . . . . . . . . . . . . . . . . .13
interrupt level controller
. . . . . . . . . . . . . . .13
interrupt names
. . . . . . . . . . . . . . . . . . . . . . . .12
interrupt system
. . . . . . . . . . . . . . . . . . . . . . . .12
interrupt system initialization flags
interrupt tables
. . . . . . . . . . . . . . . . . . . . . . . . .13
L linker error
. . . . . . . . . . . . . . . . . . . . . . . . . . . .12
M memory access
. . . . . . . . . . . . . . . . . . . . . . . . .4
memory management unit
. . . . . . . . . . . . . . . . .4
MMU
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
MMU support
. . . . . . . . . . . . . . . . . . . . . . . . . . .4
O
OS21 tick duration
. . . . . . . . . . . . . . . . . . . . . . .9
S
SCU
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
speculative control unit
. . . . . . . . . . . . . . . . . . . .4
system timer
. . . . . . . . . . . . . . . . . . . . . . . . . . . .9
T timeout timer
. . . . . . . . . . . . . . . . . . . . . . . . . . .9
timer assignments
. . . . . . . . . . . . . . . . . . . . . . . 9
Timer0
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Timer1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Timer2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
timers
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
timeslice timer
. . . . . . . . . . . . . . . . . . . . . . . . . . 9
7410372 Rev 12
UM1428
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2015 STMicroelectronics – All rights reserved
7410372 Rev 12 19/19
19
دانلود
پیوند عمومی به روز شد
پیوند عمومی به چت شما به روز شده است. You may view and manage your chat links after registration here.
پیوند عمومی سند
تبلیغات
