UM1021 - STMicroelectronics

USB device library UM1021

6.3.6

6.3.7

Using the multi-packet feature

To transmit data, the DCD_EP_Tx () function is called and to receive data

DCD_EP_PrepareRx()

is called, an with unlimited data length. Internally, the USB OTG core checks the available space in the FIFO and processes the transfer, respecting the endpoint size. For example, if the endpoint size is configured to work with 64 bytes of data and the user wants to transmit / receive N bytes of data, the USB core sends / receives several packets of 64 bytes each.

USB control functions

User applications can benefit from a few other USB functions included in a USB device.

Device reset

When the device receives a reset signal from the USB, the library resets and initializes the application on both software and hardware.

This function is part of the interrupt routine. Interrupt routine restrictions apply.

Device suspend

When the device detects a suspend condition on the USB, the library stops all the operations and puts the system to suspend state (if low power mode is enabled by in the

usb_conf.h file).

Device resume

When the device detects a resume signal on the USB, the library restores the USB core clock and puts the system to idle state (if low power mode is enabled by in the usb_conf.h file).

6.3.8 FIFO customization

In order to use a new endpoint or change the endpoint already used in the application, the user has to take care of two things:

1.

Endpoint initialization: this phase is done generally in the usbd_class_core layer through the following function: uint32_t DCD_EP_Open (USB_OTG_CORE_HANDLE *pdev , uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)

The ep_addr should hold the endpoint address, note the endpoint direction is identified by the MSB bit (ie "0x80| ep" index for ep IN endpoint) and the ep_mps holds the max packet size of the endpoints.

2. The FIFO configuration done in the usb_core.c file in the usb low level driver , the FIFO configuration could be modified by the user through the usb_conf.h file.

#ifdef USB_OTG_FS_CORE

#define RX_FIFO_FS_SIZE128

#define TX0_FIFO_FS_SIZE64

#define TX1_FIFO_FS_SIZE128

#define TX2_FIFO_FS_SIZE0

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UM1021

Note:

USB device library

#define TX3_FIFO_FS_SIZE0

#endif

#ifdef USB_OTG_HS_CORE

#define RX_FIFO_HS_SIZE512

#define TX0_FIFO_HS_SIZE128

#define TX1_FIFO_HS_SIZE384

#define TX2_FIFO_HS_SIZE0

#define TX3_FIFO_HS_SIZE0

#define TX4_FIFO_HS_SIZE0

#define TX5_FIFO_HS_SIZE0

#endif

The configuration of the FIFO is described in detail in reference manuals RM0033 and

RM0008. The Rx and the TXs FIFOs can be calculated as follows:

1.

Receive data FIFO size = RAM for setup packets + Data Out endpoint control information + Data Out packets + Miscellaneous

Space = ONE 32-bit word

– RAM for setup packets = 10

– Data Out endpoint control information = 1 space (one space for status information written to the FIFO along with each received packet).

– Data Out packets = (largest packet size / 4) + 1 space (MINIMUM to receive packets) OR Data Out packets = at least 2*(largest packet size / 4) + 1 space (if high-bandwidth endpoint is enabled or multiple isochronous endpoints)

– Miscellaneous = 1 space per Data Out endpoint (one space for transfer complete status information also pushed to the FIFO with each endpoint's last packet)

2. MINIMUM RAM space required for each Data In endpoint Tx FIFO = MAX packet size for that particular Data In endpoint. More space allocated in the Data In endpoint Tx

FIFO results in a better performance on the USB and can hide latencies on the AHB.

3. Txn minimum size = 16 words. (where, n is the Transmit FIFO index).

4. When a Tx FIFO is not used, the Configuration should be as follows:

Case 1: n > m and Txn is not used (where, n,m are the Transmit FIFO indexes)

– Txm can use the space allocated for Txn.

Case 2: n < m and Txn is not used (where, n,m are the Transmit FIFO indexes)

– Txn should be configured with the minimum space of 16 words

5. The FIFO is used optimally when used TxFIFOs are allocated in the top of the FIFO.

For example, use EP1 and EP2 as IN instead of EP1 and EP3 as the IN ones.

The total FIFO size for the used USB OTG core: for the USB OTG FS core, the total

FIFO size is 320 * 32 bits while for the USB OTG HS core, the total FIFO size is 1024 *

32 bits.

Example

If the application uses 1 IN endpoint for control with MPS = 64 Bytes, 1 OUT Endpoint for

Control with MPS = 64 Bytes and 1 IN Bulk endpoint for the class with MPS = 512 Bytes.

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