Trace infrastructure components. STMicroelectronics STM2, STM3

Below you will find brief information for STM2, STM3. This user manual describes the trace infrastructure for capturing, decoding, and displaying system trace data for SOCs with heterogeneous cores. It provides a consistent and easy-to-use trace environment, working with any core or platform. The infrastructure supports STM2 and STM3 IPs associated with STPv1 and STPv2 data protocols.

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STMicroelectronics STM2, STM3 User Manual | AI Chat | Manualzz

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Key features

  • Consistent core traces on a SoC

  • Works with any core or platform

  • Trace data for firmware stack

  • Supports STM2 and STM3 IPs

  • Support STPv1 and STPv2

  • Coupled to Multi Target Trace API

Frequently asked questions

It provides a mechanism for capturing, decoding, and displaying system trace data for SOCs that have embedded heterogeneous cores.

The Trace Infrastructure supports STM2 and STM3 IPs associated with STPv1 and STPv2 data protocols respectively.

It is coupled to the Multi Target Trace API and data protocol

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