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Interface Signals
2015.11.02
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Interface Signals
The following sections describe the Triple-Speed Ethernet MegaCore function interface signals:
•
10/100/1000 Ethernet MAC Signals
on page 7-2
•
10/100/1000 Multiport Ethernet MAC Signals
on page 7-13
•
10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS Signals
•
10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS Signals
on page 7-22
•
10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA Signals
24
•
10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA
on page
7-27
•
on page 7-36
•
1000BASE-X/SGMII PCS and PMA Signals
on page 7-41
Note: To view all the interface signal names, turn on Show Signals in the Block Diagram tab in the
Triple-Speed Ethernet parameter editor interface. Otherwise, only the connection signal names are shown.
7
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7-2
10/100/1000 Ethernet MAC Signals
10/100/1000 Ethernet MAC Signals
Figure 7-1: 10/100/1000 Ethernet MAC Function with Internal FIFO Buffers Signals
MAC Transmit
Interface Signals
MAC Receive
Interface Signals
Pause and Magic
Packet Signals
MAC Control
Interface
Signals
n
2
n
2
8
32
32
6
18
4
10/100/1000 Ethernet MAC
ff_tx_clk ff_tx_data [DATAWIDTH-1:0] ff_tx_mod [1:0] ff_tx_sop ff_tx_eop ff_tx_err ff_tx_wren ff_tx_crc _fwd tx_ff_uflow ff_tx_rdy ff_tx_septy ff_tx_a_full ff_tx_a_empty ff_rx_clk ff_rx_rdy ff_rx_data [DATAWIDTH-1:0] ff_rx_mod[1:0] ff_rx_sop ff_rx_eop rx_err[5:0] rx_err_stat[17:0] rx_frm_type[3:0] ff_rx_dsav ff_rx_dval ff_rx_a_full ff_rx_a_empty xon _gen xoff_gen magic _sleep _n magic _wakeup clk reg _addr [7:0] reg _wr reg _rd reg _data _in[31:0] reg _data _out[31:0] reg _busy reset rx_clk tx_clk rx_clkena tx_clkena gm_rx_d[7:0] gm_rx_dv gm_rx_err gm_tx_d[7:0] gm_tx_en gm_tx_err rgmii_in[3:0] rx_control rgmii_out[3:0] tx_control m_rx_d[3:0] m_rx_en m_rx_err m_rx_col m_rx_crs m_tx_d[3:0] m_tx_en m_tx_err mdio_in mdc mdio_oen mdio_out mac _eccstatus [1:0] set_10_n set_1000_n ena_10_n eth_mode_n
8
8
4
4
4
4
Reset
Signal
Clock
Signals
GMII
Signals
RGMII
Signals
MII
Signals
PHY
Management
Signals
ECC
Status
Signal
MAC
Status
Signals
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Clock and Reset Signal
Data transfers on the MAC Ethernet-side interface are synchronous to the receive and transmit clocks.
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Table 7-1: GMII/RGMII/MII Clock Signal
I/O Name
tx_clk
(In Qsys: pcs_ mac_tx_clock_ connection
)
I
I rx_clk
(In Qsys: pcs_ mac_rx_clock_ connection
) tx_clkena
I
MAC Control Interface Signals
Description
GMII / RGMII/ MII transmit clock. Provides the timing reference for all GMII / MII transmit signals. The values of gm_tx_d[7:0], gm_tx_en, gm_tx_err
, and of m_tx_d[3:0]
, m_tx_en
, m_tx_err are valid on the rising edge of tx_clk
.
GMII /RGMII/ MII receive clock. Provides the timing reference for all rx related signals. The values of gm_rx_err
, and of m_rx_d[3:0]
, m_rx_en, m_rx_err
are valid on the rising edge of rx_clk
.
gm_rx_d[7:0]
, gm_rx_dv
, rx_clkena
I
Clock enable from the PHY IP. When you turn on the Use clock
enable for MAC parameter, this signal is used together with tx_ clk
and rx_clk
to generate 125 MHz, 25 MHz, and 2.5 MHz clocks. (2)
Clock enable from the PHY IP. When you turn on the Use clock
enable for MAC parameter, this signal is used together with tx_ clk
and rx_clk
to generate 125 MHz, 25 MHz, and 2.5 MHz clocks.
(3)
Table 7-2: Reset Signal
Name
reset
I
I/O Description
Assert this signal to reset all logic in the MAC and PCS control interface. The signal must be asserted for at least three clock cycles.
MAC Control Interface Signals
The MAC control interface is an Avalon-MM slave port that provides access to the register space.
Table 7-3: MAC Control Interface Signals
Name I/O Description
clk clk
Avalon-MM
Signal Type
I reg_wr reg_rd reg_addr[7:0] reg_data_in[31:0] write read address writedata
I
I
I
I
Register access reference clock. Set the signal to a value less than or equal to 125 MHz.
Register write enable.
Register read enable.
32-bit word-aligned register address.
Register write data. Bit 0 is the least signifi‐ cant bit.
7-3
(2)
(3)
For configurations without internal FIFO, this signal is called tx_clkena_<n>
For configurations without internal FIFO, this signal is called rx_clkena_<n>
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MAC Status Signals
Name Avalon-MM
Signal Type
reg_data_out[31:0] readdata
I/O Description
reg_busy waitrequest
O
O
Register read data. Bit 0 is the least significant bit.
Register interface busy. Asserted during register read or register write access; deasserted when the current register access completes.
MAC Status Signals
The MAC status signals which allow you to set the transfer mode of the Ethernet-side interface.
Table 7-4: MAC Status Signals
Name
eth_mode ena_10 set_1000 set_10
I/O Description
I
O Ethernet mode. This signal is set to 1 when the MAC function is configured to operate at 1000 Mbps; set to 0 when it is configured to operate at 10/100 Mbps.
I
O 10 Mbps enable. This signal is set to 1 to indicate that the PHY interface should operate at 10 Mbps. Valid only when the eth_ mode
signal is set to 0.
Gigabit mode selection. Can be driven to 1 by an external device, for example a PHY device, to set the MAC function to operate in gigabit. When set to 0, the MAC is set to operate in 10/100 Mbps.
This signal is ignored when the
ETH_SPEED
bit in the command_ config
register is set to 1.
10 Mbps selection. Can be driven to 1 by an external device, for example a PHY device, to indicate that the MAC function is connected to a 10-Mbps PHY device. When set to 0, the MAC function is set to operate in 100-Mbps or gigabit mode. This signal is ignored when the
ETH_SPEED
or
ENA_10
bit in the command_config
register is set to 1. The priority than this signal.
ENA_10
bit has a higher
MAC Receive Interface Signals
Table 7-5: MAC Receive Interface Signals
Name Avalon-ST
Signal Type
Avalon-ST Signals
ff_rx_clk
(In Qsys: receive_ clock_connection
) clk
I
I/O Description
Receive clock. All signals on the Avalon-ST receive interface are synchronized on the rising edge of this clock. Set this clock to the frequency required to get the desired bandwidth on this interface. This clock can be completely independent from rx_clk
.
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Name
ff_rx_dval ff_rx_data
[(DATAWIDTH-1):0] ff_rx_mod[1:0] ff_rx_sop ff_rx_eop ff_rx_rdy rx_err[5:0]
Avalon-ST
Signal Type
valid data empty startofpacket endofpacket ready error
I
O
I/O
O
O
O
O
O
MAC Receive Interface Signals
Description
Receive data valid. When asserted, this signal indicates that the data on the following signals are valid: ff_rx_data[(DATAWIDTH -1):0]
, ff_rx_sop
, ff_rx_eop
,
rx_err[5:0]
, rx_ frm_type[3:0]
, and
rx_err_stat[17:0]
.
Receive data. When
DATAWIDTH
is 32, the first byte received is ff_rx_data[31:24]
followed by ff_rx_data[23:16]
and so forth.
Receive data modulo. Indicates invalid bytes in the final frame word:
• 11:
ff_rx_data[23:0]
is not valid
• 10: ff_rx_data[15:0]
is not valid
• 01: ff_rx_data[7:0]
is not valid
• 00: ff_rx_data[31:0]
is valid
This signal applies only when
DATAWIDTH
is set to 32.
Receive start of packet. Asserted when the first byte or word of a frame is driven on ff_rx_ data[(DATAWIDTH-1):0]
.
Receive end of packet. Asserted when the last byte or word of frame data is driven on ff_ rx_data[(DATAWIDTH-1):0]
.
Receive application ready. Assert this signal on the rising edge of ff_rx_clk
when the user application is ready to receive data from the
MAC function.
Receive error. Asserted with the final byte in the frame to indicate that an error was detected when receiving the frame. See
for the bit description.
Component-Specific Signals
ff_rx_dsav
— O Receive frame available. When asserted, this signal indicates that the internal receive FIFO buffer contains some data to be read but not necessarily a complete frame. The user application may want to start reading from the FIFO buffer.
This signal remains deasserted in the store and forward mode.
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MAC Receive Interface Signals
Name
rx_frm_type[3:0]
—
Avalon-ST
Signal Type
I/O Description
ff_rx_a_full ff_rx_a_empty rx_err_stat[17:0]
—
—
—
O
O
O
O
Frame type. See
tion.
Asserted when the FIFO buffer reaches the almost-full threshold.
Asserted when the FIFO buffer goes below the almost-empty threshold.
rx_err_stat[17]
: One indicates that the receive frame is a stacked VLAN frame.
rx_err_stat[16]
: One indicates that the receive frame is either a VLAN or stacked
VLAN frame.
rx_err_stat[15:0]
: The value of the length/ type field of the receive frame.
Table 7-6: rx_frm_type Bit Description
Bit
3
2
1
0
Description
Indicates VLAN frames. Asserted with ff_rx_sop
and remains asserted until the end of the frame.
Indicates broadcast frames. Asserted with ff_rx_sop
and remains asserted until the end of the frame.
Indicates multicast frames. Asserted with ff_rx_sop
and remains asserted until the end of the frame.
Indicates unicast frames. Asserted with ff_rx_sop
and remains asserted until the end of the frame.
Table 7-7: rx_err Bit Description
Bit
5
4
3
2
1
Description
Collision error. Asserted when the frame was received with a collision.
Corrupted receive frame caused by PHY or PCS error. Asserted when the error is detected on the MII/GMII/RGMII.
Truncated receive frame. Asserted when the receive frame is truncated due to an overflow in the receive FIFO buffer.
CRC error. Asserted when the frame is received with a CRC-32 error. This error bit applies only to frames with a valid length. Refer to
on page 4-11.
Invalid length error. Asserted when the receive frame has an invalid length as defined by the IEEE Standard 802.3. For more information on the frame length, refer to
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MAC Transmit Interface Signals
Bit Description
0
Receive frame error. Indicates that an error has occurred. It is the logical OR of rx_ err
[5:1].
Note to
:
1. Bits 1 and 2 are not mutually exclusive. Ignore CRC error rx_err[2]
signal if it is asserted at the same time as the invalid length error rx_err[1]
signal.
MAC Transmit Interface Signals
Table 7-8: MAC Transmit Interface Signals
Name Avalon-ST Signal
Type
Avalon-ST Signals
ff_tx_clk
(In Qsys: transmit_ clock_connection
) clk
I
I/O
ff_tx_wren ff_tx_data
[(DATAWIDTH-1):0] valid data
I
I
Description
Transmit clock. All transmit signals are synchronized on the rising edge of this clock.
Set this clock to the required frequency to get the desired bandwidth on the Avalon-ST transmit interface. This clock can be completely independent from tx_clk
.
Transmit data write enable. Assert this signal to indicate that the data on the following signals are valid: ff_tx_data[(DATAWIDTH-
1):0]
, ff_tx_sop
, and ff_tx_eop
.
In cut-through mode, keep this signal asserted throughout the frame transmission.
Otherwise, the frame is truncated and forwarded to the Ethernet-side interface with an error.
Transmit data.
DATAWIDTH
can be either 8 or
32 depending on the FIFO data width configured. When
DATAWIDTH
is 32, the first byte transmitted is ff_tx_data[31:24] followed by ff_tx_data[23:16]
and so forth.
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MAC Transmit Interface Signals
Name
ff_tx_mod[1:0]
Avalon-ST Signal
empty
Type
I
I/O
ff_tx_sop ff_tx_eop ff_tx_err ff_tx_rdy startofpacket endofpacket error ready
I
I
I
O
Description
Transmit data modulo. Indicates invalid bytes in the final frame word:
• 11: ff_tx_data[23:0]
is not valid
• 10: ff_tx_data[15:0]
is not valid
• 01: ff_tx_data[7:0]
is not valid
• 00: ff_tx_data[31:0]
is valid
This signal applies only when
DATAWIDTH
is set to 32.
Transmit start of packet. Assert this signal when the first byte in the frame (the first byte of the destination address) is driven on ff_ tx_data
.
Transmit end of packet. Assert this signal when the last byte in the frame (the last byte of the FCS field) is driven on ff_tx_data
.
Transmit frame error. Assert this signal with the final byte in the frame to indicate that the transmit frame is invalid. The MAC function forwards the invalid frame to the GMII with an error.
MAC ready. When asserted, the MAC function is ready to accept data from the user application.
Component-Specific Signals
ff_tx_crc_fwd
— I tx_ff_uflow ff_tx_septy ff_tx_a_full
—
—
—
O
O
O
Transmit CRC insertion. Set this signal to 0 when ff_tx_eop
is set to 1 to instruct the
MAC function to compute a CRC and insert it into the frame. If this signal is set to 1, the user application is expected to provide the
CRC.
Asserted when an underflow occurs on the transmit FIFO buffer.
Deasserted when the FIFO buffer is filled to or above the section-empty threshold defined in the tx_section_empty
register. User applications can use this signal to indicate when to stop writing to the FIFO buffer and initiate backpressure.
Asserted when the transmit FIFO buffer reaches the almost- full threshold.
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Name
ff_tx_a_empty
Avalon-ST Signal
Type
— O
I/O
Pause and Magic Packet Signals
Description
Asserted when the transmit FIFO buffer goes below the almost-empty threshold.
Pause and Magic Packet Signals
The pause and magic packet signals are component-specific signals.
Table 7-9: Pause and Magic Packet Signals
Name
xon_gen xoff_gen magic_slee p_n magic_wakeup
I
I
I
I/O
0
Description
Assert this signal for at least 1 tx_clk
clock cycle to trigger the generation of a pause frame with a 0 pause quanta. The MAC function generates the pause frame independent of the status of the receive FIFO buffer.
This signal is not in use in the following conditions:
• Ignored when the xon_gen
bit in the command_config
register is set to 1.
• Absent when the Enable full duplex flow control option is turned off.
Assert this signal for at least one tx_clk
clock cycle to trigger the generation of a pause frame with a pause quanta configured in the pause_quant
register. The MAC function generates the pause frame independent of the status of the receive FIFO buffer.
This signal is not in use in the following conditions:
• Ignored if the xoff_gen
bit in the command_config register is set to 1.
• Absent when the Enable full duplex flow control option is turned off.
Assert this active-low signal to put the node into a power-down state.
If magic packets are supported (the
MAGIC_ENA
bit in the command_config register is set to 1), the receiver logic stops writing data to the receive FIFO buffer and the magic packet detection logic is enabled. Setting this signal to 1 restores the normal frame reception mode.
This signal is present only if the Enable magic packet detection option is turned on.
If the MAC function is in the power-down state, the MAC function asserts this signal to indicate that a magic packet has been detected and the node is requested to restore its normal frame reception mode.
This signal is present only if the Enable magic packet detection option is turned on.
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MII/GMII/RGMII Signals
MII/GMII/RGMII Signals
Table 7-10: GMII/RGMII/MII Signals
I/O Name
GMII Transmit
gm_tx_d[7:0] gm_tx_en
I
O
O
Description
GMII transmit data bus.
Asserted to indicate that the data on the GMII transmit data bus is valid.
Asserted to indicate to the PHY that the frame sent is invalid.
gm_tx_err
GMII Receive
gm_rx_d[7:0] gm_rx_dv gm_rx_err
I
I
I GMII receive data bus.
Assert this signal to indicate that the data on the GMII receive data bus is valid. Keep this signal asserted during frame reception, from the first preamble byte until the last byte of the CRC field is received.
The PHY asserts this signal to indicate that the receive frame contains errors.
RGMII Transmit
rgmii_out[3:0]
O tx_control
O
RGMII transmit data bus. Drives gm_tx_d[3:0]
on the positive edge of tx_clk
and gm_tx_d[7:4]
on the negative edge of tx_ clk
.
Control output signal. Drives gm_tx_en
on the positive edge of tx_clk
and a logical derivative of ( gm_tx_en XOR gm_tx_err)
on the negative edge of tx_clk
.
RGMII Receive
rgmii_in[3:0]
I rx_control
I
RGMII receive data bus. Expects gm_rx_d[3:0]
on the positive edge of rx_clk
and gm_rx_d[7:4]
on the negative edge of rx_ clk
.
RGMII control input signal. Expects gm_rx_dv
on the positive edge of rx_clk
and a logical derivative of ( gm_rx_dv XOR gm_rx_ err)
on the negative edge of rx_clk
.
MII Transmit
m_tx_d[3:0] m_tx_en m_tx_err
O
O
O
MII transmit data bus.
Asserted to indicate that the data on the MII transmit data bus is valid.
Asserted to indicate to the PHY device that the frame sent is invalid.
MII Receive
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Name
m_rx_d[3:0] m_rx_en m_rx_err
PHY Management Signals
I
I
I
I/O Description
MII receive data bus.
Assert this signal to indicate that the data on the MII receive data bus is valid. Keep this signal asserted during frame reception, from the first preamble byte until the last byte of the CRC field is received.
The PHY asserts this signal to Indicate that the receive frame contains errors.
MII PHY Status
m_rx_col m_rx_crs
I
I Collision detection. The PHY asserts this signal to indicate a collision during frame transmission. This signal is not used in fullduplex or gigabit mode.
Carrier sense detection. The PHY asserts this signal to indicate that it has detected transmit or receive activity on the Ethernet line. This signal is not used in full-duplex or gigabit mode.
PHY Management Signals
Table 7-11: PHY Management Interface Signals
Name
mdio_in mdio_out mdio_oen mdc
I
O
O
I/O
O
Description
Management data input.
Management data output.
An active-low signal that enables mdio_in
or mdio_out
. For more information about the MDIO connection, refer to
Management data clock. Generated from the Avalon-MM interface clock signal, clk
. Specify the division factor using the
Host clock divisor parameter such that the frequency of this clock does not exceed 2.5 MHz. For more information about the
A data bit is shifted in/out on each rising edge of this clock. All fields are shifted in and out starting from the most significant bit.
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ECC Status Signals
ECC Status Signals
Table 7-12: ECC Status Signals
Name
mac_eccstatus[1:0]
O
I/O Description
Indicates the ECC status. This signal is synchronized to the reg_ clk
clock domain.
• 11: An uncorrectable error occurred and the error data appears at the output.
• 10: A correctable error occurred and the error has been corrected at the output. However, the memory array has not been updated.
• 01: Not valid.
• 00: No error.
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10/100/1000 Multiport Ethernet MAC Signals
10/100/1000 Multiport Ethernet MAC Signals
Figure 7-2: 10/100/1000 Multiport Ethernet MAC Function without Internal FIFO Buffers Signals
7-13
Clock
Signals
MAC Receive
Interface Signals
Classification
Signals
Pause and Magic
Packet Signals
MAC Control
Signals n
2
5
8
8
8
5
32
32
Multi-Port MAC
mac_tx_clk_n mac_rx_clk_n data_tx_data_n[7:0] data_tx_sop_n data_tx_eop_n data_tx_error_n data_tx_valid_n data_tx_ready_n tx_crc_fwd_n tx_ff_uflow_n data_rx_data_n[7:0] data_rx_sop_n data_rx_eop_n data_rx_error_n[4:0] data_rx_ready_n data_rx_valid_n pkt_class _valid_n pkt_class _data_n[4:0] rx_afull_channel[CHANNEL _WIDTH -1:0] rx_afull_data[1:0] rx_afull_valid rx_afull_clk xon_gen_n xoff_gen_n magic_sleep_n_n magic_wakeup_n clk reg_addr[7:0] reg_wr reg_rd reg_data_in[31:0] reg_data_out[31:0] reg_busy reset rx_clk_n tx_clk_n rx_clkena_n tx_clkena_n gm_rx_d_n[7:0] gm_rx_dv_n gm_rx_err_n gm_tx_d_n[7:0] gm_tx_en_n gm_tx_err_n
8
8 rgmii_in_n[3:0] rx_control_n rgmii_out_n[3:0] tx_control_n m
_rx_d_n[3:0] m_rx_dv_n m_rx_err_n m_col_n m_crs_n m_tx_d_n[3:0] m_tx_en_n m_tx_err_n mdio_in mdc mdio_oen mdio_out
4
4
4
4 set_10_n set_1000_n ena_10_n eth_mode_n mac_eccstatus[1:0]
Clock
Signals
MII
Signals
PHY
Signals
MAC
Signals
ECC Status
Signal
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Multiport MAC Clock and Reset Signals
Multiport MAC Clock and Reset Signals
Table 7-13: Clock Signals
Name
mac_rx_clk clk
Avalon-ST
Signal Type
O
I/O
mac_tx_clk clk
O
Description
Receive MAC clock (2.5/25/125 MHz) for the
Avalon-ST receive data and receive packet classification interfaces.
Transmit MAC clock (2.5/25/125 MHz) for the Avalon-ST transmit data interface.
Multiport MAC Receive Interface Signals
Table 7-14: MAC Receive Interface Signals
Name
data_rx_valid
_n
Avalon-ST
Signal Type
valid
O
I/O
data_rx_data_ n
[7:0] data data_rx_sop_ n startofpacket
O
O data_rx_eop_ n data_rx_ready_ n data_rx_error_ n
[4:0] endofpacket ready error
I
O
O
Description
Receive data valid. When asserted, this signal indicates that the data on the following signals are valid: data_rx_data
_n, data_rx_sop
_n, data_rx_eop
_n, and data_rx_error
_n.
Receive data.
Receive start of packet. Asserted when the first byte or word of a frame is driven on data_rx_ data
_n.
Receive end of packet. Asserted when the last byte or word of frame data is driven on data_ rx_data
_n.
Receive application ready. Assert this signal on the rising edge of data_rx_clk
_n when the user application is ready to receive data from the MAC function.
If the user application is not ready to receive data, the packet is dropped or truncated with an error.
Receive error. Asserted with the final byte in the frame to indicate that an error was detected when receiving the frame. For the description of each bit, refer to the description
on page 7-4 . Bit 4 of this signal maps to bit 5 in the table and so forth.
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Multiport MAC Transmit Interface Signals
Table 7-15: MAC Transmit Interface Signals
Name Avalon-ST
Signal Type
I/O
Avalon-ST Signals
data_tx_valid_ n valid I data_tx_data
_n[7:0] data data_tx_sop
_n startofpacket
I
I data_tx_eop
_n data_tx_error
_n data_tx_ready
_n endofpacket error ready
I
I
O
Multiport MAC Transmit Interface Signals
Description
Transmit data valid. Assert this signal to indicate that the data on the following signals are valid: data_tx_data
_n, data_tx_sop
_n, data_tx_eop
_n, and data_tx_error
_n.
Transmit data.
Transmit start of packet. Assert this signal when the first byte in the frame is driven on data_tx_data
_n.
Transmit end of packet. Assert this signal when the last byte in the frame (the last byte of the FCS field) is driven on data_tx_data
_n.
Transmit frame error. Assert this signal with the final byte in the frame to indicate that the transmit frame is invalid. The MAC function then forwards the frame to the GMII with error.
MAC ready. When asserted, this signal indicates that the MAC function is ready to accept data from the user application.
Component-Specific Signal
tx_crc_fwd
_n
—
I Transmit CRC insertion. Assert this active-low signal when data_tx_eop
_n is asserted for the
MAC function to compute the CRC and insert it into the frame. Otherwise, the user applica‐ tion is expected to provide the CRC.
7-15
Multiport MAC Packet Classification Signals
The MAC packet classification interface is an Avalon-ST source port which streams out receive packet classifications.
Table 7-16: MAC Packet Classification Signals
Name Avalon-ST
Signal Type
pkt_class_valid_ n valid
O
I/O Description
When asserted, this signal indicates that classifi‐ cation data is valid.
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Multiport MAC FIFO Status Signals
Name
pkt_class_data n[4:0]
_
Avalon-ST
Signal Type
data
O
I/O Description
Classification presented at the beginning of each packet:
Bit 4—Set to 1 for unicast frames.
Bit 3—Set to 1 for broadcast frames.
Bit 2—Set to 1 for multicast frames.
Bit 1—Set to 1 for VLAN frames.
Bit 0—Set to 1 for stacked VLAN frames.
UG-01008
2015.11.02
Multiport MAC FIFO Status Signals
The MAC FIFO status interface is an Avalon-ST sink port which streams in information on the fill level of the external FIFO buffer to the MAC function.
Table 7-17: MAC FIFO Status Signals
Signal Name
rx_afull_valid_ n
Avalon-ST
Signal Type
valid I
I/O Description
rx_afull_data
_n[1:0] data
I
I
Assert this signal to indicate that the fill level of the external FIFO buffer, rx_afull_data
_ n[1:0],is valid.
Carries the fill level of the external FIFO buffer: rx_afull_data
_n[1]—Set to 1 if the external receive FIFO buffer reaches the initial warning level indicating that it is almost full. Upon detecting this, the MAC function generates pause frames.
rx_afull_data
_n[0]—Set to 1 if the external receive FIFO buffer reaches the critical level before it overflows. The FIFO buffer can be considered overflow if this bit is set to 1 in the middle of a packet transfer.
The port number the status applies to.
rx_afull_channel
[(CHANNEL_WIDTH-1):
0] rx_afull_clk channel clk I The clock that drives the MAC FIFO status interface.
Table 7-18: References
Interface Signal
Clock and reset signals
MAC control interface
Section
on page 7-3
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Multiport MAC FIFO Status Signals
Interface Signal Section
MAC transmit interface
MAC Transmit Interface Signals
MAC receive interface
Status signals
on page 7-4
Pause and Magic Packet Signals
Pause and magic packet signals
MII/GMII/RGMII interface
PHY management signals
ECC status signals
7-17
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10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS Signals
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10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS Signals
Figure 7-3: 10/100/1000 Ethernet MAC Function with Internal FIFO Buffers, with 1000BASE-X/SGMII
PCS Signals
MAC Transmit
Interface Signals
MAC Receive
Interface Signals
Pause and Magic
Packet Signals
8
MAC Control
Interface
Signals
32
32
6
18
4 n
2 n
2
10/100/1000 Ethernet MAC with 1000 Base-X PCS/SGMII
ff_tx_clk ff_tx_data[DATAWIDTH-1:0] ff_tx_mod[1:0] ff_tx_sop ff_tx_eop ff_tx_err ff_tx_wren ff_tx_crc_fwd tx_ff_uflow ff_tx_rdy ff_tx_septy ff_tx_a_full ff_tx_a_empty reset tbi_rx_clk tbi_rx_d[9:0] tbi_tx_clk tbi_tx_d[9:0] led_an led_crs led_col led_char_err led_link led_panel_link led_disp_err ff_rx_clk ff_rx_rdy ff_rx_data[DATAWIDTH-1:0] ff_rx_mod[1:0] ff_rx_sop ff_rx_eop rx_err[5:0] rx_err_stat[17:0] rx_frm_type[3:0] ff_rx_dsav ff_rx_dval ff_rx_a_full ff_rx_a_empty xon_gen xoff_gen magic_sleep_n magic_wakeup mdio_in mdc mdio_oen mdio_out tx_serial_clk rx_cdr_refclk tx_analogreset tx_digitalreset rx_analogreset rx_digitalreset tx_cal_busy rx_cal_busy rx_set_locktodata rx_set_locktoref rx_is_locktodata rx_is_locktoref clk address [7:0] write read writedata[31:0] readdata[31:0] waitrequest pcs_eccstatus [1:0] sd_loopback powerdown
10
10
Reset
Signal
Ten Bit
Interface
Signals
Status
LED
Signals
PHY
Signals
Arria 10
Transceiver
Native PHY
Signals
ECC
Status
Signal
SERDES
Control
Signals
TBI Interface Signals
If the core variation does not include an embedded PMA, the PCS block provides a 125-MHz ten-bit interface (TBI) to an external SERDES chip.
Table 7-19: TBI Interface Signals for External SERDES Chip
Name
tbi_tx_d(9:0)
O
I/O Description
TBI transmit data. The PCS function transmits data on this bus synchronous to tbi_tx_clk
.
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Name
tbi_tx_clk tbi_rx_clk tbi_rx_d[9:0]
I
I
I
I/O
Status LED Control Signals
Description
125-MHz TBI transmit clock from external SERDES, typically sourced by the local reference clock oscillator.
125-MHz TBI receive clock from external SERDES, typically sourced by the line clock recovered from the encoded line stream.
TBI receive data. This bus carries the data from the external
SERDES. Synchronize the bus with tbi_rx_clk
. The data can be arbitrary aligned.
Status LED Control Signals
Table 7-20: Status LED Interface Signals
Name
led_link led_panel_link
O
I/O
O
Description
When asserted, this signal indicates a successful link synchroni‐ zation.
When asserted, this signal indicates the following behavior:
Mode
1000 Base-X without auto negotiation
SGMII mode without auto negotiation
1000 Base-X with auto negotia‐ tion
SGMII mode with MAC mode auto negotiation
SGMII mode with PHY mode auto negotiation
Signal Behavior
Similar to led_link
Similar to
Similar to
Similar to led_link led_an partner_ability
[15] led_an
and
Similar to led_an
and dev_ability [15] led_crs led_col led_an led_char_err
O
O
O
O
When asserted, this signal indicates some activities on the transmit and receive paths. When deasserted, it indicates no traffic on the paths.
When asserted, this signal indicates that a collision was detected during frame transmission. This signal is always deasserted when the PCS function operates in standard 1000BASE-X mode or in full-duplex mode when SGMII is enabled.
Auto-negotiation status. The PCS function asserts this signal when an auto-negotiation completes.
10-bit character error. Asserted for one tbi_rx_clk
cycle when an erroneous 10-bit character is detected.
7-19
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SERDES Control Signals
Name
led_disp_err
O
I/O Description
10-bit running disparity error. Asserted for one tbi_rx_clk cycle when a disparity error is detected. A running disparity error indicates that more than the previous and perhaps the current received group had an error.
SERDES Control Signals
Table 7-21: SERDES Control Signal
Name
powerdown
O
I/O
sd_loopback
O
Description
Power-down enable. Asserted when the PCS function is in power-down mode; deasserted when the PCS function is operating in normal mode. This signal is implemented only when an external SERDES is used.
SERDES Loopback Control. Asserted when the PCS function operates in loopback mode. You can use this signal to configure an external SERDES device to operate in loopback mode.
Arria 10 Transceiver Native PHY Signals
Table 7-22: Arria 10 Transceiver Native PHY Signals
Name
tx_serial_clk rx_cdr_refclk tx_analogreset tx_digitalreset rx_analogreset rx_digitalreset tx_cal_busy rx_cal_busy rx_set_locktodata rx_set_locktoref rx_is_lockedtodata
I
I
I
I
I
I
O
I
I
I/O
O
O
Description
Serial clock input from the transceiver PLL. The frequency of this clock is 1250 MHz and the division factor is fixed to divide by 2.
Reference clock input to the receive clock data recovery (CDR) circuitry. The frequency of this clock is 125 MHz.
Resets the analog transmit portion of the transceiver PHY.
Resets the digital transmit portion of the transceiver PHY.
Resets the analog receive portion of the transceiver PHY.
Resets the digital receive portion of the transceiver PHY.
When asserted, this signal indicates that the transmit channel is being calibrated.
When asserted, this signal indicates that the receive channel is being calibrated.
Force the receiver CDR to lock to the incoming data.
Force the receiver CDR to lock to the phase and frequency of the input reference clock.
When asserted, this signal indicates that the CDR PLL is locked to the incoming data rx_serial_data
.
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Name
rx_is_lockedtoref
O
I/O
ECC Status Signals
Description
When asserted, this signal indicates that the CDR PLL is locked to the incoming reference clock, rx_cdr_refclk
.
7-21
Related Information
Arria 10 Transceiver PHY User Guide
More information about Gigabit Ethernet (GbE) and GbE with 1588, the connection guidelines for a PHY design, and how to implement GbE/GbE with 1588 in Arria 10 Transceivers
ECC Status Signals
Table 7-23: ECC Status Signals
Name
pcs_eccstatus[1:0]
O
I/O Description
Indicates the ECC status. This signal is synchronized to the reg_ clk
clock domain.
11: An uncorrectable error occurred and the error data appears at the output.
10: A correctable error occurred and the error has been corrected at the output. However, the memory array has not been updated.
01: Not valid.
00: No error.
For more information on the signals, refer to the respective sections shown in
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10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS Signals
10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS Signals
Figure 7-4: 10/100/1000 Multiport Ethernet MAC Function without Internal FIFO Buffers with
1000BASE-X/SGMII PCS Signals
UG-01008
2015.11.02
Clock
Signals
MAC Transmit
Interface Signals
MAC Receive
Interface Signals
MAC Packet
Signals
MAC FIFO
Status Signals
MAC Control
Interface
Signals
8
8
8
5
5 n
32
32
Multi-Port MAC with 1000BASE-X/SGMII PCS
mac_tx_clk_n mac_rx_clk_n reset data_tx_data_n[7:0] data_tx_sop_n data_tx_eop_n data_tx_error_n data_tx_valid_n data_tx_ready_n tx_crc_fwd_n tx_ff_uflow_n data_rx_data_n[7:0] data_rx_sop_n data_rx_eop_n data_rx_error_n[4:0] data_rx_ready_n data_rx_valid_n pkt_class _valid_n pkt_class _data_n[4:0] tbi_rx_clk_n tbi_rx_d_n[9:0] tbi_tx_clk_n tbi_tx_d_n[9:0] led_an_n led_crs_n led_col_n led_char_err_n led_link_n led_panel_link_n led_disp_err_n rx_afull_channel[CHANNEL_WIDTH-1:0] rx_afull_data[1:0] rx_afull_valid rx_afull_clk xon_gen_n xoff_gen_n magic_sleep_n_n magic_wakeup_n clk reg_addr[(log2 MAX_CHANNELS+7):0][7:0] reg_wr reg_rd reg_data_in[31:0] reg_data_out[31:0] reg_busy mdio_in mdc mdio_oen mdio_out sd_loopback_n powerdown_n pcs_eccstatus[1:0]
10
10
Ten Bit
Interface
Signals
Status
LED
Signals
PHY
Management
Signals
Control
Signals
ECC Status
Signal
Table 7-24: References
Interface Signal
Clock and reset signals
MAC control interface
Section
on page 7-2
Altera Corporation
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Interface Signal
MAC transmit interface
MAC receive interface
MAC packet classification signals
MAC FIFO status signals
Pause and magic packet signals
PHY management signals
Ten-bit interface
Status LED signals
SERDES control signals
10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS Signals
Section
MAC Transmit Interface Signals
on page 7-7
on page 7-4
Multiport MAC Packet Classification Signals
on page 7-15
Multiport MAC FIFO Status Signals
Pause and Magic Packet Signals
on page 7-9
on page 7-11
on page 7-18
7-23
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7-24
10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA...
UG-01008
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10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA
Signals
Figure 7-5: 10/100/1000 Ethernet MAC Function with Internal FIFO Buffers, and 1000BASE-X/SGMII PCS
With Embedded PMA Signals
MAC Transmit
Interface Signals
MAC Receive
Interface Signals
Pause and Magic
Packet Signals
MAC Control
Interface
Signals n
2 n
2
8
6
18
4
32
32
10/100/1000 Ethernet MAC and 1000BASE-X/SGMII PCS
ff_tx_clk ff_tx_data[DATAWIDTH -1:0] ff_tx_mod[1:0] ff_tx_sop ff_tx_eop ff_tx_err ff_tx_wren ff_tx_crc_fwd tx_ff_uflow ff_tx_rdy
with Embedded PMA
reset ref_clk rx_p tx_p ff_tx_septy ff_tx_a_full ff_tx_a_empty ff_rx_clk ff_rx_rdy ff_rx_data[DATAWIDTH -1:0] ff_rx_mod[1:0] ff_rx_sop ff_rx_eop rx_err[5:0] rx_err_stat[17:0] rx_frm_type[3:0] ff_rx_dsav ff_rx_dval ff_tx_a_full ff_tx_a_empty led_an led_crs led_col led_char_err led_link led_panel_link led_disp_err mdio_in mdc mdio_oen mdio_out cdr_ref_clk_n xon_gen xoff_gen magic_sleep_n magic_wakeup mac_eccstatus[1:0] clk reg_addr[7:0] reg_wr reg_rd reg_data_in[31:0] reg_data_out[31:0] reg_busy rx_recovclkout gxb_cal_blk_clk pcs_pwrdn_out gxb_pwrdn_in reconfig_clk reconfig_togxb reconfig_fromgxb
Reset
Signal
1.25 Gbps
Serial Signals
LED
Signals
PHY
Management
Signals
Transceiver
Native PHY
Signal
ECC Status
Signal
Control
Signals
Note to
:
1. The SERDES control signals are present in variations targeting devices with GX transceivers. For
Stratix II GX and Arria GX devices, the reconfiguration signals— reconfig_clk
,
reconfig_togxb
, and reconfig_fromgxb
—are included only when the option, Enable transceiver dynamic reconfigu‐
ration, is turned on. The reconfiguration signals— gxb_cal_blk_clk
, pcs_pwrdwn_out
,
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1.25 Gbps Serial Interface
7-25
gxb_pwrdn_in
, reconfig_clk
, and reconfig_busy
—are not present in variations targeting Arria 10,
Stratix V, Arria V, and Cyclone V devices with GX transceivers.
1.25 Gbps Serial Interface
If the variant includes an embedded PMA, the PMA provides a 1.25-GHz serial interface.
Table 7-25: 1.25 Gbps MDI Interface Signals
Name
ref_clk rx_p tx_p
I
I
O
I/O Description
125 MHz local reference clock oscillator.
Serial Differential Receive Interface.
Serial Differential Transmit Interface.
Transceiver Native PHY Signal
Table 7-26: Transceiver Native PHY Signal
Name
cdr_ref_clk_n
I
I/O Description
Port to connect the RX PLL reference clock with a frequency of
125 MHz when you enable SyncE support.
SERDES Control Signals
These signals apply only to PMA blocks implemented in devices with GX transceivers.
Table 7-27: SERDES Control Signal
Name
rx_recovclkout pcs_pwrdn_out gxb_pwrdn_in
I
O
O
I/O Description
Recovered clock from the PMA block.
Power-down status. Asserted when the PCS function is in power-down mode; deasserted when the PCS function is operating in normal mode. This signal is implemented only when an internal SERDES is used with the option to export the power-down signal.
This signal is not present in PMA blocks implemented in Arria
10, Stratix V, Arria V, and Cyclone V devices with GX transceivers.
Power-down enable. Assert this signal to power down the transceiver quad block. This signal is implemented only when an internal SERDES is used with the option to export the power-down signal.
This signal is not present in PMA blocks implemented in Arria
10, Stratix V, Arria V, and Cyclone V devices with GX transceivers.
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SERDES Control Signals
Name
gxb_cal_blk_clk reconfig_clk reconfig_togxb[n:0] reconfig_fromgxb[n:0] reconfig_busy I
I
I
I
I/O
O
Description
Calibration block clock for the ALT2GXB module (SERDES).
This clock is typically tied to the 125 MHz ref_clk
. Only implemented when an internal SERDES is used.
This signal is not present in PMA blocks implemented in Arria
10, Stratix V, Arria V, and Cyclone V devices with GX transceivers.
Reference clock for the dynamic reconfiguration controller. If you use a dynamic reconfiguration controller in your design to dynamically control the transceiver, both the reconfiguration controller and the MegaCore function require this clock. This clock must operate between 37.5–50 MHz. Tie this clock low if you are not using an external reconfiguration controller.
This signal is not present in PMA blocks implemented in Arria
10, Stratix V, Arria V, and Cyclone V devices with GX transceivers.
Driven from an external dynamic reconfiguration controller.
Supports the selection of multiple transceiver channels for dynamic reconfiguration.
For PMA blocks implemented in Stratix V devices with GX transceivers, the bus width is [139:0]. For more information about the bus width for PMA blocks implemented in each device, refer to the Dynamic Reconfiguration chapter of the respective device handbook.
Connects to an external dynamic reconfiguration controller.
The bus identifies the transceiver channel whose settings are being transmitted to the reconfiguration controller. Leave this bus disconnected if you are not using an external reconfigura‐ tion controller.
For more information about the bus width for PMA blocks implemented in each device, refer to the Dynamic Reconfigura‐ tion chapter of the respective device handbook.
Driven from an external dynamic reconfiguration controller.
This signal will indicate the busy status of the dynamic reconfi‐ guration controller during offset cancellation. Tie this signal to
1'b0 if you are not using an external reconfiguration controller.
This signal is not present in PMA blocks implemented in Arria
10, Stratix V, Arria V, and Cyclone V devices with GX transceivers.
For more information on the signals, refer to the respective sections shown in
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10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS and...
7-27
10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded
PMA
Figure 7-6: 10/100/1000 Multiport Ethernet MAC Function without Internal FIFO Buffers, with IEEE
1588v2, 1000BASE-X/SGMII PCS and Embedded PMA Signals
Transceiver
Native PHY
Signal n
5 n
8
8
5
32
32
Multi-Port MAC and 1000BASE-X/SGMII PCS with Embedded PMA
mac_tx_clk_n mac_rx_clk_n reset ref_clk_n rx_p_n tx_p_n data_tx_data_n[7:0] data_tx_sop_n data_tx_eop_n data_tx_error_n data_tx_valid_n data_tx_ready_n tx_crc_fwd_n tx_ff_uflow_n led_an_n led_crs_n led_col_n led_char_err_n led_link_n led_panel_link_n led_disp_err_n data_rx_data_n[7:0] data_rx_sop_n data_rx_eop_n data_rx_error_n[4:0] data_rx_ready_n data_rx_valid_n xon_gen_n xoff_gen_n magic_sleep_n_n magic_wakeup_n pkt_class_valid_n pkt_class_data_n[4:0] mdio_in mdc mdio_oen mdio_out rx_afull_channel(CHANNEL_WIDTH-1:0) rx_afull_data[1:0] rx_afull_valid rx_afull_clk clk reg_addr[(log2 MAX_CHANNELS+7):0] reg_wr reg_rd reg_data_in[31:0] reg_data_out[31:0] reg_busy cdr_ref_clk_n gxb_cal_blk_clk pcs_pwrdn_out gxb_pwrdn_in_n reconfig_clk_n reconfig_togxb_n reconfig_fromgxb_n rx_recovclkout reconfig_busy tx_egress_timestamp_96b_n tx_egress_timestamp_64b_n rx_ingress_timestamp_96b_n rx_ingress_timestamp_64b_n tx_egress_timestamp_request_n tx_etstamp_ins_ctrl_n tx_time_of_day_96b_n tx_time_of_day_64b_n rx_time_of_day_96b_n rx_time_of_day_64b_n pcs_phase_measure_clk pcs_eccstatus[1:0]
IEEE 1588v2
Signals
ECC Status
Signal
Note to
:
1. The SERDES control signals are present in variations targeting devices with GX transceivers. For
Stratix II GX and Arria GX devices, the reconfiguration signals—reconfig_clk, reconfig_togxb, and reconfig_fromgxb—are included only when the Enable transceiver dynamic reconfiguration option is turned on. The reconfiguration signals— gxb_cal_blk_clk
, pcs_pwrdwn_out
, gxb_pwrdn_in
,
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IEEE 1588v2 RX Timestamp Signals
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reconfig_clk
, and reconfig_busy
—are not present in variations targeting Arria 10, Stratix V, Arria
V, and Cyclone V devices with GX transceivers.
Table 7-28: References
Interface Signal
Clock and reset signals
MAC control interface
MAC transmit interface
MAC receive interface
MAC packet classification signals
MAC FIFO status signals
Pause and magic packet signals
PHY management signals
1.25 Gbps Serial Signals
Status LED signals
SERDES control signals
Transceiver Native PHY signal
IEEE 1588v2 RX Timestamp Signals
IEEE 1588v2 TX Timestamp Signals
IEEE 1588v2 TX Timestamp Request
Signals
IEEE 1588v2 TX Insert Control
Timestamp Signals
IEEE 1588v2 ToD Clock Interface
Signals
Section
on page 7-2
MAC Transmit Interface Signals
on page 7-7
on page 7-4
Multiport MAC Packet Classification Signals
on page 7-15
Multiport MAC FIFO Status Signals
Pause and Magic Packet Signals
on page 7-9
on page 7-11
IEEE 1588v2 RX Timestamp Signals
on page 7-28
IEEE 1588v2 TX Timestamp Signals
IEEE 1588v2 TX Timestamp Request Signals
IEEE 1588v2 TX Insert Control Timestamp Signals
7-31 page 7-34
on page
IEEE 1588v2 Time-of-Day (ToD) Clock Interface Signals
on
IEEE 1588v2 RX Timestamp Signals
Table 7-29: IEEE 1588v2 RX Timestamp Interface Signals
I/O Signal
rx_ingress_timestamp_96b_ data_n
O
Width
96
Description
Carries the ingress timestamp on the receive datapath. Consists of 48-bit seconds field, 32-bit nanoseconds field, and 16-bit fractional nanoseconds field.
The MAC presents the timestamp for all receive frames and asserts this signal in the same clock cycle it asserts rx_ ingress_timestamp_96b_valid
.
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Signal
rx_ingress_timestamp_96b_ valid
O
I/O
rx_ingress_timestamp_64b_data
O rx_ingress_timestamp_64b_ valid
O
IEEE 1588v2 TX Timestamp Signals
1
Width
64
1
Description
When asserted, this signal indicates that rx_ingress_timestamp_96b_ data
contains valid timestamp.
For all receive frame, the MAC asserts this signal in the same clock cycle it receives the start of packet ( avalon_ st_rx_startofpacket
is asserted).
Carries the ingress timestamp on the receive datapath. Consists of 48-bit nanoseconds field and 16-bit fractional nanoseconds field.
The MAC presents the timestamp for all receive frames and asserts this signal in the same clock cycle it asserts rx_ ingress_timestamp_64b_valid
.
When asserted, this signal indicates that rx_ingress_timestamp_64b_ data
contains valid timestamp.
For all receive frame, the MAC asserts this signal in the same clock cycle it receives the start of packet ( avalon_ st_rx_startofpacket
is asserted).
IEEE 1588v2 TX Timestamp Signals
Table 7-30: IEEE 1588v2 TX Timestamp Interface Signals
Signal
tx_egress_timestamp_96b_data_ n
O
I/O Width
96
Description
A transmit interface signal. This signal requests timestamp of frames on the
TX path. The timestamp is used to calculate the residence time.
Consists of 48-bit seconds field, 32-bit nanoseconds field, and 16-bit fractional nanoseconds field.
7-29
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IEEE 1588v2 TX Timestamp Signals
Signal
tx_egress_timestamp_96b_valid
O
I/O
tx_egress_timestamp_96b_ fingerprint tx_egress_timestamp_64b_data tx_egress_timestamp_64b_valid tx_egress_timestamp_64b_ fingerprint
O
O
O
O
1
Width
n
64
1
n
Description
A transmit interface signal. Assert this signal to indicate that a timestamp is obtained and a timestamp request is valid for the particular frame.
Assert this signal in the same clock cycle as the start of packet ( avalon_ st_tx_startofpacket
is asserted).
Configurable width fingerprint that returns with correlated timestamps.
The signal width is determined by the
TSTAMP_FP_WIDTH parameter
(default parameter value is 4).
A transmit interface signal. This signal requests timestamp of frames on the
TX path. The timestamp is used to calculate the residence time.
Consists of 48-bit nanoseconds field and 16-bit fractional nanoseconds field.
A transmit interface signal. Assert this signal to indicate that a timestamp is obtained and a timestamp request is valid for the particular frame.
Assert this signal in the same clock cycle as the start of packet ( avalon_ st_tx_startofpacket
or avalon_st_ tx_startofpacket_n
is asserted).
Configurable width fingerprint that returns with correlated timestamps.
The signal width is determined by the
TSTAMP_FP_WIDTH parameter
(default parameter value is 4).
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IEEE 1588v2 TX Timestamp Request Signals
Table 7-31: IEEE 1588v2 TX Timestamp Request Signals
I/O Signal
tx_egress_timestamp_request_ valid_n tx_egress_timestamp_request_ fingerprint
I
I
IEEE 1588v2 TX Timestamp Request Signals
1
Width
n
Description
Assert this signal when a user-defined tx_egress_timestamp
is required for a transmit frame.
Assert this signal in the same clock cycle as the start of packet ( avalon_ st_tx_startofpacket
or avalon_st_ tx_startofpacket_n
is asserted).
Use this bus to specify fingerprint for the user-defined tx_egress_ timestamp
. The fingerprint is used to identify the user-defined timestamp.
The signal width is determined by the
TSTAMP_FP_WIDTH parameter
(default parameter value is 4).
The value of this signal is mapped to user_fingerprint
.
This signal is only valid when you assert tx_egress_timestamp_ request_valid
.
IEEE 1588v2 TX Insert Control Timestamp Signals
Table 7-32: IEEE 1588v2 TX Insert Control Timestamp Interface Signals
Signal
tx_etstamp_ins_ctrl_timestamp_ insert_n
I
I/O
1
Width Description
Assert this signal to insert egress timestamp into the associated frame.
Assert this signal in the same clock cycle as the start of packet ( avalon_st_ tx_startofpacket
is asserted).
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IEEE 1588v2 TX Insert Control Timestamp Signals
Signal
tx_etstamp_ins_ctrl_timestamp_ format
I
I/O
tx_etstamp_ins_ctrl_residence_ time_update tx_etstamp_ins_ctrl_ingress_ timestamp_96b[] tx_etstamp_ins_ ctrl_ingress_ timestamp_64b[]
I
I
I
1
Width Description
Timestamp format of the frame, which the timestamp inserts.
0: 1588v2 format (48-bits second field +
32-bits nanosecond field + 16-bits correction field for fractional nanosecond)
Required offset location of timestamp and correction field.
1: 1588v1 format (32-bits second field +
32-bits nanosecond field)
Required offset location of timestamp.
Assert this signal in the same clock cycle as the start of packet ( avalon_st_ tx_startofpacket
is asserted).
1
96
64
Assert this signal to add residence time
(egress timestamp –ingress timestamp) into correction field of PTP frame.
Required offset location of correction field.
Assert this signal in the same clock cycle as the start of packet ( avalon_st_ tx_startofpacket
is asserted).
96-bit format of ingress timestamp.
(48 bits second + 32 bits nanosecond +
16 bits fractional nanosecond).
Assert this signal in the same clock cycle as the start of packet ( avalon_st_ tx_startofpacket
is asserted).
64-bit format of ingress timestamp.
(48-bits nanosecond + 16-bits fractional nanosecond).
Assert this signal in the same clock cycle as the start of packet ( avalon_st_ tx_startofpacket
is asserted).
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Signal
tx_etstamp_ins_ctrl_residence_ time_calc_format
I
I/O
tx_etstamp_ins_ctrl_checksum_ zero tx_etstamp_ins_ctrl_checksum_ correct tx_etstamp_ins_ctrl_offset_ timestamp tx_etstamp_ins_ctrl_offset_ correction_field[]
I
I
I
I
IEEE 1588v2 TX Insert Control Timestamp Signals
1
Width Description
Format of timestamp to be used for residence time calculation.
0: 96-bits (96-bits egress timestamp -
96-bits ingress timestamp).
1: 64-bits (64-bits egress timestamp -
64-bits ingress timestamp).
Assert this signal in the same clock cycle as the start of packet ( avalon_st_ tx_startofpacket
is asserted).
1
1
1
16
Assert this signal to set the checksum field of UDP/IPv4 to zero.
Required offset location of checksum field.
Assert this signal in the same clock cycle as the start of packet ( avalon_st_ tx_startofpacket
is asserted).
Assert this signal to correct UDP/IPv6 packet checksum, by updating the checksum correction, which is specified by checksum correction offset.
Required offset location of checksum correction.
Assert this signal in the same clock cycle as the start of packet ( avalon_st_ tx_startofpacket
is asserted).
The location of the timestamp field, relative to the first byte of the packet.
Assert this signal in the same clock cycle as the start of packet ( avalon_st_ tx_startofpacket
is asserted).
The location of the correction field, relative to the first byte of the packet.
Assert this signal in the same clock cycle as the start of packet ( avalon_st_ tx_startofpacket
is asserted).
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IEEE 1588v2 Time-of-Day (ToD) Clock Interface Signals
Signal
tx_etstamp_ins_ctrl_offset_ checksum_field[]
I
I/O
tx_etstamp_ins_ctrl_offset_ checksum_correction[]
I
Width
16
16
Description
The location of the checksum field, relative to the first byte of the packet.
Assert this signal in the same clock cycle as the start of packet ( avalon_st_ tx_startofpacket
is asserted).
The location of the checksum correction field, relative to the first byte of the packet.
Assert this signal in the same clock cycle as the start of packet ( avalon_st_ tx_startofpacket
is asserted).
IEEE 1588v2 Time-of-Day (ToD) Clock Interface Signals
Table 7-33: IEEE 1588v2 ToD Clock Interface Signals
Signal
tx_time_of_day_96b_data_n rx_time_of_day_96b_data tx_time_of_day_64b_data rx_time_of_day_64b_data
I
I
I
I
I/O Width
96
96
64
64
Description
Use this bus to carry the time-of-day from external ToD module to 96-bit
MAC TX clock.
Consists of 48 bits seconds field, 32 bits nanoseconds field, and 16 bits fractional nanoseconds field
Use this bus to carry the time-of-day from external ToD module to 96-bit
MAC RX clock.
Consists of 48 bits seconds field, 32 bits nanoseconds field, and 16 bits fractional nanoseconds field
Use this bus to carry the time-of-day from external ToD module to 64-bit
MAC TX clock.
Consists of 48-bit nanoseconds field and 16-bit fractional nanoseconds field
Use this bus to carry the time-of-day from external ToD module to 64-bit
MAC RX clock.
Consists of 48-bit nanoseconds field and 16-bit fractional nanoseconds field
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IEEE 1588v2 PCS Phase Measurement Clock Signal
IEEE 1588v2 PCS Phase Measurement Clock Signal
Table 7-34: IEEE 1588v2 PCS Phase Measurement Clock Signal
Signal
pcs_phase_measure_clk
I
I/O
1
Width Description
Sampling clock to measure the latency through the PCS FIFO buffer. The recommended frequency is 80 MHz.
IEEE 1588v2 PHY Path Delay Interface Signals
Table 7-35: IEEE 1588v2 PHY Path Delay Interface Signals
Signal
tx_path_delay_data rx_path_delay_data
I
I
I/O Width
22
22
Description
Use this bus to carry the path delay on the transmit datapath. The delay is measured between the physical network and MII/GMII to adjust the egress timestamp.
Bits 0 to 9—Fractional number of clock cycles
Bits 10 to 21—Number of clock cycles
Use this bus to carry the path delay on the receive datapath. The delay is measured between the physical network and MII/GMII to adjust the ingress timestamp.
Bits 0 to 9—Fractional number of clock cycles
Bits 10 to 21—Number of clock cycles
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1000BASE-X/SGMII PCS Signals
1000BASE-X/SGMII PCS Signals
Figure 7-7: 1000BASE-X/SGMII PCS Function Signals
MII/GMII
Signals
SGMII
Signals
4
4
8
8 gmii_tx_d[7:0] gmii_tx_en gmii_tx_err gmii_rx_d[7:0] gmii_rx_dv gmii_rx_err
1000 BASE-X/SGMII PCS Function
reset_rx_clk reset_tx_clk reset_reg_clk tbi_rx_clk tbi_rx_d[9:0] tbi_tx_clk tbi_tx_d[9:0] mii_tx_d[3:0] mii_tx_en mii_tx_err mii_rx_d[3:0] mii_rx_dv mii_rx_err mii_col mii_crs led_an led_crs led_col led_char_err led_link led_panel_link led_disp_err sd_loopback powerdown rx_clkena tx_clkena
10
10 rx_clk tx_clk reg_clk reg_addr[4:0] reg_wr reg_rd reg_data_in[15:0] reg_data_out[15:0] reg_busy
5
16
16 set_10 set_100 set_1000 hd_ena tx_serial_clk rx_cdr_refclk tx_analogreset tx_digitalreset rx_analogreset rx_digitalreset tx_cal_busy rx_cal_busy rx_set_locktodata rx_set_locktoref rx_is_locktodata rx_is_locktoref
Note to
:
1. The clock enabler signals are present only in SGMII mode.
Status
Signals
PCS
Control
Arria 10
Transceiver
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PCS Control Interface Signals
Table 7-36: Register Interface Signals
Name
reg_clk
Avalon-MM
Signal Type
clk
I
I/O
reset_reg_clk reg_wr reg_rd reg_addr[4:0] reg_data_in[15:0] reg_busy reset write read address writedata reg_data_out[15:0] readdata
I
I
I
I
I
O waitrequest
O
PCS Control Interface Signals
Description
Register access reference clock. Set the signal to a value less than or equal to 125-MHz.
Active-high reset signal for reg_clk
clock domain.
Register write enable.
Register read enable.
16-bit word-aligned register address.
Register write data. Bit 0 is the least significant bit.
Register read data. Bit 0 is the least significant bit.
Register interface busy. Asserted during register read or register write. A value of 0 indicates that the read or write is complete.
PCS Reset Signals
Table 7-37: Reset Signals
Name
reset_rx_clk reset_tx_clk
I
I
I/O Description
Active-high reset signal for PCS rx_clk
clock domain. Assert this signal to reset the logic synchronized by rx_clk
.
Active-high reset signal for PCS tx_clk
clock domain. Assert this signal to reset the logic synchronized by tx_clk
.
MII/GMII Clocks and Clock Enablers
Data transfers on the MII/GMII interface are synchronous to the receive and transmit clocks.
Table 7-38: MAC Clock Signals
rx_clk
Name
tx_clk rx_clkena
O
I/O
O
O
Description
Receive clock. This clock is derived from the TBI clock tbi_rx_ clk and set to 125 MHz.
Transmit clock. This clock is derived from the TBI clock tbi_tx_ clk
and set to 125 MHz.
Receive clock enabler. In SGMII mode, this signal enables rx_clk
.
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GMII
Name
tx_clkena
O
I/O Description
Transmit clock enabler. In SGMII mode, this signal enables tx_ clk
.
Figure 7-8: Clock Enabler Signal Behavior
125 MHz Clock
25 MHz Clock Enable
Input Data
Output Data
0xAA
0xAA
0xBB
0xBB
0xCC
0xCC
0xDD
0xDD
GMII
Table 7-39: GMII Signals
Name
GMII Transmit Interface
gmii_tx_d[7:0]
I gmii_tx_en
I
I/O
gmii_tx_err
I
Description
GMII transmit data bus.
Assert this signal to indicate that the data on gmii_tx_d[7:0] is valid.
Assert this signal to indicate to the PHY device that the current frame sent is invalid.
GMII Receive Interface
gmii_rx_d[7:0] gmii_rx_dv
O
O gmii_rx_err
O
GMII receive data bus.
Asserted to indicate that the data on gmii_rx_d[7:0]
is valid.
Stays asserted during frame reception, from the first preamble byte until the last byte in the CRC field is received.
Asserted by the PHY to indicate that the current frame contains errors.
MII
Table 7-40: MII Signals
Name
MII Transmit Interface
mii_tx_d[3:0] mii_tx_en
I
I
I/O Description
MII transmit data bus.
Assert this signal to indicate that the data on mii_tx_d[3:0] is valid.
0xEE
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SGMII Status Signals
Name
mii_tx_err
I
I/O Description
Assert this signal to indicate to the PHY device that the frame sent is invalid.
MII Receive Interface
mii_rx_d[3:0] mii_rx_dv mii_rx_err mii_col mii_crs
O
O
MII receive data bus.
Asserted to indicate that the data on mii_rx_d[3:0] is valid. The signal stays asserted during frame reception, from the first preamble byte until the last byte of the CRC field is received.
O Asserted by the PHY to indicate that the current frame contains errors.
Out Collision detection. Asserted by the PCS function to indicate that a collision was detected during frame transmission.
Out Carrier sense detection. Asserted by the PCS function to indicate that a transmit or receive activity is detected on the Ethernet line.
SGMII Status Signals
The SGMII status signals provide status information to the PCS block. When the PCS is instantiated standalone, these signals are inputs to the MAC and serve as interface control signals for that block.
Table 7-41: SGMII Status Signals
Name
set_1000 set_100
O
I/O
O
Description
Gigabit mode enabled. In 1000BASE-X, this signal is always set to
1. In SGMII, this signal is set to 1 if one of the following conditions is met: the
USE_SGMII_AN
bit is set to 1 and a gigabit link is established with the link partner, as decoded from the partner_ability register the
USE_SGMII_AN
bit is set to 0 and the
SGMII_SPEED
bit is set to
10
100 -Mbps mode enabled. In 1000BASE-X, this signal is always set to 0. In SGMII, this signal is set to 1 if one of the following conditions is met: the
USE_SGMII_AN
bit is set to 1 and a 100Mbps link is established with the link partner, as decoded from the partner_ ability register the
USE_SGMII_AN
bit is set to 0 and the
SGMII_SPEED
bit is set to
01
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SGMII Status Signals
set_10
Name
O
I/O
hd_ena
O
Description
10 -Mbps mode enabled. In 1000BASE-X, this signal is always set to 0. In SGMII, this signal is set to 1 if one of the following conditions is met: the
USE_SGMII_AN
bit is set to 1 and a 10Mbps link is established with the link partner, as decoded from the partner_ability register the
USE_SGMII_AN
bit is set to 0 and the
SGMII_SPEED
bit is set to
00
Half-duplex mode enabled. In 1000BASE-X, this signal is always set to 0. In SGMII, this signal is set to 1 if one of the following conditions is met: the
USE_SGMII_AN
bit is set to 1 and a half-duplex link is established with the link partner, as decoded from the partner_ ability register the
USE_SGMII_AN
bit is set to 0 and the
SGMII_DUPLEX
bit is set to 1
Table 7-42: References
Interface Signal Section
Ten-bit interface
Status LED signals
on page 7-19
SERDES control signals
on page 7-20
Arria 10 Transceiver
Native PHY signals
Arria 10 Transceiver Native PHY Signals
page 7-20
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1000BASE-X/SGMII PCS and PMA Signals
1000BASE-X/SGMII PCS and PMA Signals
Figure 7-9: 1000BASE-X/SGMII PCS Function and PMA Signals
GMII
Signals
MII
Signals
Clock
Enabler
Signals
MII/GMII
Clock
Signals
SGMII
Status
Signals
8
8
4
4
1000BASE-X/SGMII PCS Function With Embedded PMA
gmii_tx_d[7:0] gmii_tx_en gmii_tx_err gmii_rx_d[7:0] gmii_rx_dv gmii_rx_err reset _rx_clk reset _tx_clk reset ref_clk rx_p tx_p mii_tx_d[3:0] mii_tx_en mii_tx_err mii_rx_d[3:0] mii_rx_dv mii_rx_err mii_col mii_crs led_crs led_col led_char _err led_link led_panel_link led_disp _err rx_clkena tx_clkena rx_clk tx_clk gxb_cal_blk_clk pcs_pwrdn_out gxb_pwrdn_in reconfig_clk reconfig_togxb reconfig_fromgxb rx_recovclkout reconfig_busy set _10 set _100 set _1000 hd_ena clk address [4:0] write read writedata [15:0] readdata [15:0] waitrequest
5
16
16
Reset
Signals
1.25 Gbps
Serial Signals
Status
LED
Signals
SERDES
Control
Signals
PCS
Control
Interface
Signals
7-41
Notes to
:
1. The clock enabler signals are present only in SGMII mode.
2. The SERDES control signals are present in variations targeting devices with GX transceivers. For
Stratix II GX and Arria GX devices, the reconfiguration signals— reconfig_clk
,
reconfig_togxb
, and reconfig_fromgxb
—are included only when the option, Enable transceiver dynamic reconfigu‐
ration, is turned on. The reconfiguration signals— gxb_cal_blk_clk
,
pcs_pwrdwn_out
, gxb_pwrdn_in
,
reconfig_clk
, and reconfig_busy
—are not present in variations targeting Stratix V devices with GX transceivers.
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