Download datasheet for ML9059E by LAPIS Semiconductor

FEDL9059E-01

ML9059E

LAPIS Semiconductor

FUNCTIONAL DESCRIPTION

MPU Interface

Pin WR = “L”

Pin R/W = “H” Pin R/W = “L”

68-Series

Pin E = “H” Pin E = “H”

In the case of the 80-series MPU interface, a command is started by applying a low pulse to the RD pin or the WR pin.

In the case of the 68-series MPU interface, a command is started by applying a high pulse to the E pin.

 Selection of interface type

The ML9059E carries out data transfer using either the 8-bit bi-directional data bus (DB0 to DB7) or the serial data input line (SI). Either the 8-bit parallel data input or serial data input can be selected as shown in Table 2 by setting the P/S pin to the “H” or the “L” level.

Table 2 Selection of interface type (parallel/serial)

P/S

CS1 CS2 A0 RD WR C86

D7 D6 DB0 to DB5

H: Parallel input

CS1

CS2 A0

RD WR

C86

L: Serial input

CS1

CS2 A0 — — —

A hyphen (—) indicates that the pin can be tied to the “H” or the “L” level.

 Parallel interface

D7

SI

D6

SCL

DB0 to DB5

—

When the parallel interface is selected, (P/S = “H”), it is possible to connect this LSI directly to the MPU bus of either an 80-series MPU or a 68-series MPU as shown in Table 3. depending on whether the pin C86 is set to “H” or “L”.

Table 3 Selection of MPU during parallel interface (80–/68–series)

C86

H: 68-Series MPU bus

L: 80-Series MPU bus

CS1

CS1

CS2

CS2

A0

A0

E

RD

R/W

WR

DB0 to DB7

DB0 to DB7

The data bus signals are identified as shown in Table 4 below depending on the combination of the signals A0, RD

(E), and WR (R/W) of Table 3.

Table 4 Identification of data bus signals during parallel interface

Common 68-Series 80-Series

A0 R/W RD WR

Display data read

Display data write

Status read

Control data write (command)

1

1

0

0

1

0

1

0

0

1

0

1

1

0

1

0

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FEDL9059E-01

ML9059E

LAPIS Semiconductor

Serial Interface

When the serial interface is selected (P/S = “L”), the serial data input (SI) and the serial clock input (SCL) can be accepted if the chip is in the active state (CS1 = “L” and CS2 = “H”). The serial interface consists of an 8-bit shift register and a 3-bit counter. The serial data is read in from the serial data input pin in the sequence DB7, DB6, ... ,

DB0 at the rising edge of the serial clock input, and is converted into parallel data at the rising edge of the 8th serial clock pulse and processed further. The identification of whether the serial data is display data or command is judged based on the A0 input, and the data is treated as display data when A0 is “H” and as command when A0 is

“L”. The A0 input is read in and identified at the rising edge of the (8

 n) th serial clock pulse after the chip has become active. Fig. 1 shows the signal chart of the serial interface. (When the chip is not active, the shift register and the counter are reset to their initial states. No data read out is possible in the case of the serial interface. It is necessary to take sufficient care about wiring termination reflection and external noise in the case of the SCL signal. We recommend verification of operation in an actual unit.)

CS1

CS2

SI

SCL

A0

DB7

1

DB6 DB5 DB4

2 3 4

DB3

5

DB2

6

DB1

7

DB0

8

DB7

9

DB6

10

DB5

11

DB4 DB3 DB2

12 13 14

Fig. 1 Signal chart during serial interface

 Chip select

The ML9059E has the two chip select pins CS1and CS2, and the MPU interface or the serial interface is enabled only when CS1 = “L” and CS2 = “H”. When the chip select signals are in the inactive state, the DB0 to DB7 lines will be in the high impedance state and the inputs A0, RD, and WR will not be effective. When the serial interface has been selected, the shift register and the counter are reset when the chip select signals are in the inactive state.

 Accessing the display data RAM and the internal registers

Accessing the ML9059E from the MPU side requires merely that the cycle time (t

CYC

) be satisfied, and high speed data transfer without requiring any wait time is possible. Also, during the data transfer with the MPU, the

ML9059E carries out a type of pipeline processing between LSIs via a bus holder associated with the internal data bus. For example, when the MPU writes data in the display data RAM, the data is temporarily stored in the bus holder, and is then written into the display data RAM before the next data read cycle. Further, when the MPU reads out data in the display data RAM, first a dummy data read cycle is carried out to temporarily store the data in the bus holder which is then placed on the system bus and is read out during the next read cycle. There is a restriction on the read sequence of the display data RAM, which is that the read instruction immediately after setting the address does not read out the data of that address, but that data is output as the data of the address specified during the second data read sequence, and hence care should be taken about this during reading.

Therefore, always one dummy read is necessary immediately after setting the address or after a write cycle: (The status read cannot use dummy read cycles.) This relationship is shown in Figs 2(a) and 2(b).

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FEDL9059E-01

ML9059E

LAPIS Semiconductor

 Data write

WR

DATA

BUS Holder

Write Signal

Dn

Latch

Dn

Dn + 1

Dn + 1

Dn + 2

Dn + 2

Dn + 3

Dn + 3

Fig. 2(a) Write sequence of display data RAM

 Data read

WR

RD

DATA

Address

Preset

Read Signal

Column

Address

BUS Holder

N

Address Set

N unknown

Preset N unknown

Data Read

(Dummy)

Dn

Increment N + 1

Dn

Data Read

Dn

Fig. 2(b) Read sequence of display data RAM

N + 2

Dn + 1

Dn + 1

Dn + 2

Data Read

Dn + 1

Dn = Data

N = Address data

 Busy flag

The busy flag being “1” indicates that the ML9059E is carrying out reset operations, and hence no instruction other than a status read instruction is accepted during this period. The busy flag is output at pin DB7 when a status read instruction is executed.

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FEDL9059E-01

ML9059E

LAPIS Semiconductor

Display Data RAM

 Display data RAM

This is the RAM storing the dot data for display and has an organization of 65 (8 pages

 8 bits +1)  132 bits. It is possible to access any required bit by specifying the page address and the column address. Since the display data

DB7 to DB0 from the MPU corresponds to the LCD display in the direction of the common lines as shown in Fig.

3, there are fewer restrictions during display data transfer when the ML9059E is used in a multiple chip configuration, thereby making it easily possible to realize a display with a high degree of freedom. Also, since the display data RAM read/write from the MPU side is carried out via an I/O buffer, it is done independent of the signal read operation for the LCD drive. Consequently, the display is not affected by flickering, etc., even when the display data RAM is accessed asynchronously during the LCD display operation.

DB0 0 1 1



0 COM0



DB1 1 0 0



DB2 0 0 0



DB3 0 1 1



DB4 1 0 0



0

0

0

0

COM1

COM2

COM3

COM4









Display data RAM LCD Display

Fig. 3 Relationship between display data RAM and LCD display

 Page address circuit

The page address of the display data RAM is specified using the page address set command as shown in Fig. 4.

Specify the page address again when accessing after changing the page. The page address 8 (DB3, DB2, DB1,

DB0

 1, 0, 0, 0) is the RAM area dedicated to the indicator, and only the display data DB0 is valid in this page.

 Column address circuit

The column address of the display data RAM is specified using the column address set command as shown in Fig.

4. Since the specified column address is incremented (by +1) every time a display data read/write command is issued, the MPU can access the display data continuously. Further, the incrementing of the column address is stopped at the column address of 83(H). Since the column address and the page address are independent of each other, it is necessary, for example, to specify separately the new page address and the new column address when changing from column 83(H) of page 0 to column 00(H) of page 1. Also, as is shown in Table 5, it is possible to reverse the correspondence relationship between the display data RAM column address and the segment output using the ADC command (the segment driver direction select command). This reduces the IC placement restrictions at the time of assembling LCD modules.

Table 5 Correspondence relationship between the display data RAM column address and the segment output

SEGMENT Output

ADC

DB0 = “0”

DB0 = “1”

SEG0

0(H)

83(H)





Column Address

Column Address

SEG131

 83(H)

 0(H)

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FEDL9059E-01

ML9059E

LAPIS Semiconductor

 Line address circuit

The line address circuit is used for specifying the line address corresponding to the common output when displaying the contents of the display data RAM as is shown in Fig. 4. Normally, the topmost line in the display is specified using the display start line address set command (COM0 output in the forward display state of the common output, and COM47 output in the reverse display state). The display area is 48 lines in the direction of increasing line address from the specified display start line address. When the indicator–dedicated common output pin (COMS) is selected, data in Line Address 40 H = page 8 and bit 0 is displayed irrespective of the display start line address. COMS selection is 49th in order.

It is possible to carry out screen scrolling by dynamically changing the line address using the display start line address set command.

 Display data latch circuit

The display data latch circuit is a latch for temporarily storing the data from the display data RAM before being output to the LCD drive circuits. Since the commands for selecting forward/reverse display and turning the display ON/OFF control the data in this latch, the data in the display data RAM will not be changed.

Oscillator Circuit

This is an RC oscillator that generates the display clock. The oscillator circuit is effective only when M/S = “H” and also CLS = “H”. The oscillations will be stopped when CLS = “L”, and the display clock has to be input to the

CL pin.

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LAPIS Semiconductor

Page Address

Data

0 0

0 0

0 0

0 0

0 1

0 1

0 1

0 1

1 0

0

0

1

1

0

0

1

1

0

0

1

0

1

0

1

0

1

0

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DB0

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

FEDL9059E-01

ML9059E

Page0

Page1

Page2

Page3

Page4

Page5

Page6

Page7

Page8

Line

Address

When the common output state is normal display

38H

39H

3AH

3BH

3CH

3DH

3EH

3FH

40H

31H

32H

33H

34H

35H

36H

37H

25H

26H

27H

28H

29H

2AH

2BH

2CH

1DH

1EH

1FH

20H

21H

22H

23H

24H

2DH

2EH

2FH

30H

0EH

0FH

10H

11H

12H

13H

14H

15H

16H

17H

18H

19H

1AH

1BH

1CH

00H

01H

02H

03H

04H

05H

06H

07H

08H

09H

0AH

0BH

0CH

0DH

(Start)

COM

Output

COM0

COM1

COM2

COM3

COM4

COM5

COM6

COM7

COM8

COM9

COM10

COM11

COM12

COM13

COM14

COM15

COM16

COM17

COM18

COM19

COM20

COM21

COM22

COM23

COM24

COM25

COM26

COM27

COM28

COM29

COM30

COM31

COM32

COM33

COM34

COM35

COM36

COM37

COM38

COM39

COM40

COM41

COM42

COM43

COM44

COM45

COM46

COM47

COMS

The 40(H) is displayed irrespective of the display start line address.

Fig. 4 Display data RAM address map

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FEDL9059E-01

ML9059E

LAPIS Semiconductor

Display Timing Generator Circuit

This circuit generates the timing signals for the line address circuit and the display data latch circuit from the display clock. The display data is latched in the display data latch circuit and is output to the segment drive output pins in synchronization with the display clock. This circuit generates the timing signals for the line address circuit and the display data latch circuit from the display clock. The display data is latched in the display data latch circuit and is output to the segment drive output pins in synchronization with the display clock. The read out of the display data to the LCD drive circuits is completely independent of the display data RAM access from the MPU.

As a result, there is no bad influence such as flickering on the display even when the display data RAM is accessed asynchronously during the LCD display. Also, the internal common timing and LCD frame reversal (FR) signals are generated by this circuit from the display clock. The drive waveforms of the frame reversal drive method shown in Fig. 5(a) for the LCD drive circuits are generated by this circuit. The drive waveforms of the line reversal drive method shown in Fig. 5(b) are also generated by the command.

48 49 1 2 3 4 5 6 44 45 46 47 48 49 1 2 3 4 5 6

LCDCK

(display clock)

FR

V1

V2

COM0

V5

V

SS

V1

V2

COM1

V5

V

SS

RAM

DATA

SEGn

V1

V3

V4

V

SS

Fig. 5(a) Waveforms in the frame reversal drive method

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FEDL9059E-01

ML9059E

LAPIS Semiconductor

LCDCK

(display clock)

FR

48 1 2 3 4 5 6

44 45 46 47 48 49

1 2 3 4 5 6

COM0

V1

V2

V5

V

SS

V1

V2

COM1

V5

V

SS

RAM

DATA

V1

SEGn

V3

V4

V

SS

Fig. 5(b) Waveforms in the line reversal drive method

When the ML9059E is used in a multiple chip configuration, it is necessary to supply the slave side display timing signals (FR, CL, and DOF) from the master side. However, when the line reversal drive is set, the ML9059E is not used in a multiple chip configuration.

The statuses of the signals FR, CL, and

DOF

are shown in Table 6.

Table 6 Display timing signals in master mode and slave mode

Operating mode FR CL

DOF

Internal oscillator circuit enabled (CLS = H) Output Output Output

Master mode (M/S = “H”)

Internal oscillator circuit disabled (CLS = L) Output Input Output

Internal oscillator circuit disabled (CLS = H) Input Input Input

Slave mode (M/S = “L”)

Internal oscillator circuit disabled (CLS = L) Input Input Input

Note: During master mode, the oscillator circuit operates from the time the power is applied. The oscillator circuit can be stopped only in the sleep state.

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FEDL9059E-01

ML9059E

LAPIS Semiconductor

Common Output State Selection Circuit (See Table 7)

Since the common output scanning directions can be set using the common output state selection command in the

ML9059E, it is possible to reduce the IC placement restrictions at the time of assembling LCD modules.

Table 7 Common output state settings

Forward Display

Reverse Display

COM0

 COM47

COM47

 COM0

LCD Drive Circuit

This LSI incorporates 181 sets of multiplexers for the ML9059E, that generate 4-level outputs for driving the LCD.

These output the LCD drive voltage in accordance with the combination of the display data, common scanning signals, and the FR signal. Fig. 6 shows examples of the segment and common output waveforms in the frame reversal drive method.

Static Indicator Circuit

The FR pin is connected to one side of the LCD drive electrode of the static indicator and the FRS pin is connected to the other side.

The static indicator display is controlled by a command only independently of other display control commands.

The electrode of the static indicator should has a wiring pattern that is distant from the dynamic drive electrode.

If the wiring pattern is placed too near to the dynamic drive electrode, the LCD and electrode may be degraded.

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LAPIS Semiconductor

C O M 0

C O M 1

C O M 2

C O M 3

C O M 4

C O M 5

C O M 6

C O M 7

C O M 8

C O M 9

C O M 1 0

C O M 1 1

C O M 1 2

C O M 1 3

C O M 1 4

C O M 1 5

F R

C O M 0

C O M 1

C O M 2

S E G 0

S E G 1

S E G 2

C O M 0 -S E G 0

C O M 0 -S E G 1

FEDL9059E-01

ML9059E

V

D D

V

S S

V 1

V 2

V 3

V 4

V 5

0 V

-V 5

-V 4

-V 3

-V 2

-V 1

V 1

V 2

V 3

V 4

V 5

0 V

-V 5

-V 4

-V 3

-V 2

-V 1

V 1

V 2

V 3

V 4

V 5

V

S S

V 1

V 2

V 3

V 4

V 5

V

S S

V 1

V 2

V 3

V 4

V 5

V

S S

V 1

V 2

V 3

V 4

V 5

V

S S

V 1

V 2

V 3

V 4

V 5

V

S S

V 1

V 2

V 3

V 4

V 5

V

S S

Fig. 6 Output waveforms in the frame reversal drive method (FR waveform/common waveform/segment waveform/voltage difference between common and segment)

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FEDL9059E-01

ML9059E

LAPIS Semiconductor

Power Supply Circuit

This is the low power consumption type power supply circuit for generating the voltages necessary for driving

LCD devices, and consists of voltage multiplier circuits, voltage adjustment circuits, and voltage follower circuits.

In the power supply circuit, it is possible to control the ON/OFF of each of the circuits of the voltage multiplier, voltage adjustment circuits, and voltage follower circuits using the power control set command. As a result, it is also possible to use parts of the functions of both the external power supply and the internal power supply. Table

8 shows the functions controlled by the 3-bit data of the power control set command and Table 9 shows a sample combination.

Table 8 Details of functions controlled by the bits of the power control set command

Control bit Function controlled by the bit

DB2

DB1

DB0

Voltage multiplier circuit control bit

Voltage adjustment circuit (V1 voltage adjustment circuit) control bit

Voltage follower circuit (V/F circuit) control bit

Table 9 Sample combination for reference

Circuit

V

Adjustment

V/F

External voltage input

Voltage multiplier pins *1

Only the internal power supply is used

DB2 DB1 DB0

1 1 1

Voltage multiplier



V

IN

Used

Only V adjustment and

V/F circuits are used

0 1 1

Only V/F circuits are used 0 0 1





V

OUT

OPEN

Only the external power supply is used

0 0 0

  

V1 to V5 OPEN

*1: The voltage multiplier pins are the pins VS1–, VS2–, VC3+, VC4+, VC5+, and VC6+.

If combinations other than the above are used, normal operation is not guaranteed.

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 Voltage multiplier circuits

The connections for 2- to 4-time voltage multiplier circuits are shown below.

V

IN

V

IN

+

+

V

SS

V

OUT

VC6+

+

+

V

SS

V

OUT

VC6+

+

+

+

OPEN

VC4+ VC4+

VS2–

VC5+

VC3+

VS2–

VC5+

VC3+

OPEN OPEN

+

+

VS1–

2-time voltage multiplier circuit

VS1–

3-time voltage multiplier circuit

V

IN

V

SS

V

OUT

VC6+

VC4+

VS2–

VC5+

VC3+

VS1–

4-time voltage multiplier circuit

FEDL9059E-01

ML9059E

Fig. 7 Connection examples for voltage multiplier circuits

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FEDL9059E-01

ML9059E

LAPIS Semiconductor

The voltage relationships in voltage multiplication are shown in Fig. 8.

V

OUT

= 3

 V

IN

= 15.0 V

V

OUT

= 4

 V

IN

= 18 V

*1 V

IN

= 5.0 V

V

SS

= 0 V

*1 V

IN

= 4.5 V

V

SS

= 0 V

Voltage relationship in 3-time multiplication Voltage relationship in 4-time multiplication

Fig. 8 Voltage relationships in voltage multiplication

*1: The voltage range of V

IN

should be set from 6V to 18.33V so that the voltage at the pin V

OUT

does not exceed the voltage multiplier output voltage operating range.



Voltage adjustment circuit

The voltage multiplier output V

OUT

produces the LCD drive voltage V1 via the voltage adjustment circuit. Since the ML9059E incorporates a high accuracy constant voltage generator, a 64-level electronic potentiometer function, and also resistors for voltage V1 adjustment, it is possible to build a high accuracy voltage adjustment circuit with very few components. In addition, the ML9059E is available with the temperature gradients of a

VREG - about –0.05%/°C.

(a) When the internal resistors for voltage V1 adjustment are used

It is possible to control the LCD power supply voltage V1 and adjust the intensity of LCD display using commands and without needing any external resistors, if the internal voltage V1 adjustment resistors and the electronic potentiometer function are used. The voltage V1 can be obtained by the following equation A-1 in the range of V1<VOUT.

V1 = (1 + (Rb/Ra))

 VEV = (1 + (Rb/Ra))  (1 – (/324))  VREG (Eqn. A-1)

VEV (Constant voltage supply +

+ electronic potentiometer)

V1

VRS

–

(VREG)

VR

Internal Ra

Internal Rb

Fig. 9 V1 voltage adjustment circuit (equivalent circuit)

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FEDL9059E-01

ML9059E

LAPIS Semiconductor

VREG is a constant voltage generated inside the IC and VRS pin output voltage.

Here,

 is the electronic potentiometer function which allows one level among 64 levels to be selected by merely setting the data in the 6-bit electronic potentiometer register. The values of

 set by the electronic potentiometer register are shown in Table 10.

Table 10 Relationship between electronic potentiometer register and





DB5 DB4 DB3 DB2 DB1 DB0

63 0 0 0 0 0 0

62 0 0 0 0 0 1

61 0 0 0 0 1 0

1 1 1 1 1 1 0

0 1 1 1 1 1 1

Rb/Ra is the voltage V1 adjustment internal resistor ratio and can be adjusted to one of 7 levels by the voltage V1 adjustment internal resistor ratio set command. The reference values of the ratio (1 + Rb/Ra) according to the 3-bit data set in the voltage V1 adjustment internal resistor ratio setting register are listed in Table 11.

Table 11 Voltage V1 adjustment internal resistor ratio setting register values and the ratio (1+Rb/Ra) (Nominal)

Register

(1 + Rb/Ra)

DB2 DB1 DB0

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

3.0

3.5

4.0

4.5

5.0

5.5

1 1 0 6.0

Note: Use V1 gain in the range from 3 to 6 times. Because this LSI has temperature gradient, V1 voltage rises at lower temperatures. When using V1 gain of 6 times, adjust the built-in electronic potentiometer so that V1 voltage does not exceed 18 V.

When V1 is set using the built-in resistance ratio, the accuracies are shown in Table 12.

Table 12 Relation between V1 Output Voltage Accuracy and V1 Gain Using Built-in Resistor

Parameter

V1 gain

3 times 3.5 times 4 times 4.5 times 5 times 5.5 times 6 times

Unit

V1 output voltage accuracy

2.5 2.5 2.5 2.5 2.5 2.5 2.5 %

V1 maximum output voltage

9 10.5 12 13.5 15 16.5 18 V

Note: The V1 maximum output voltages in Table 12 are nominal values when Tj = 25°C and electronic potentiometer

 = 0. The V1 output voltage accuracy in Table 12 are values when V1 load current

I = 0

A, 20 V is externally input to V

OUT

, and display is turned OFF.

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FEDL9059E-01

ML9059E

LAPIS Semiconductor

(b) When external resistors are used (voltage V1 adjustment internal resistors are not used)

It is also possible to set the LCD drive power supply voltage V1 without using the internal resistors for voltage V1 adjustment but connecting external resistors (Ra' and Rb') between V

SS

& VR and between VR & V1. Even in this case, it is possible to control the LCD power supply voltage V1 and adjust the intensity of LCD display using commands if the electronic potentiometer function is used.

The voltage V1 can be obtained by the following equation B-1 in the range of V1<V

OUT

by setting the external resistors Ra' and Rb' appropriately.

V1 = (1 + (Rb'/Ra'))

 VEV = (1 + (Rb'/Ra'))  (1 – (/324))  VREG (Eqn. B-1)

External Rb'

VR

External Ra'

V

SS

–

+

V1

VEV (Constant voltage supply + electronic potentiometer)

Fig. 10 V1 voltage adjustment circuit (equivalent circuit)

Setting example: Setting V1 = 7 V at Tj = 25°C

When the electronic potentiometer register value is set to the middle value of (DB5, DB4, DB3, DB2, DB1, DB0)

= (1, 0, 0, 0, 0, 0), the value of

 will be 31 and that of VREG will be 3.0 V, and hence the equation B-1 becomes as follows:

V1 = (1 + (Rb'/Ra'))

 (1 – (/324))  VREG

7 = (1 + (Rb'/Ra'))

 (1 – (31/324))  3.0 (Eqn. B-2)

Further, if the current flowing through Ra' and Rb' is set as 5 µA, the value of Ra' + Rb' will be - Ra' + Rb' = 1.4

M

 (Eqn. B-3) and hence,

Rb'/Ra' = 1.58, Ra' = 543 k

, Rb' = 857 k.

In this case, the variability range of voltage V1 using the electronic potentiometer function will be as given in

Table 13.

Table 13 Example 1 of V1 variable-voltage range using electronic potentiometer function

Variable-voltage range 6.24 (

 = 63)

7.0 (

 = 31)

7.74 (

 = 0)

[V]

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(c) When external resistors are used (voltage V1 adjustment internal resistors are not used) and a variable resistor is also used

It is possible to set the LCD drive power supply voltage V1 using fine adjustment of Ra' and Rb' by adding a variable resistor to the case of using external resistors in the above case. Even in this case, it is possible to control the LCD power supply voltage V1 and adjust the intensity of LCD display using commands if the electronic potentiometer function is used.

The voltage V1 can be obtained by the following equation C-1 in the range of V1<V

OUT

by setting the external resistors R

1

, R

2

(variable resistor), and R

3

appropriately and making fine adjustment of R

2

(

R

2

).

V1 = (1 + (R

3

+ R

2

–

R

= (1 + (R

3

+ R

2

2

)/(R

1

+

–

R

2

)/(R

1

+

R

2

R

2

))

 VEV

))

 (1 – (/324))  VREG (Eqn. C-1)

Rb'

External R

3

External R

2

VR

 R

2

–

Ra'

External R

1

+

V1

VEV (Constant voltage supply + electronic potentiometer)

V

SS

Fig. 11 V1 voltage adjustment circuit (equivalent circuit)

Setting example: Setting V1 in the range 5 V to 9 V using R

2

at Tj = 25°C .

When the electronic potentiometer register value is set to (DB5, DB4, DB3, DB2, DB1, DB0) = (1, 0, 0, 0, 0, 0), the value of

 will be 31 and that of VREG will be 3.0 V, and hence in order to make V1 = 9 V when R

2

= 0

, the equation C-1 becomes as follows:

9 = (1 + (R

3

+ R

2

)/R

1

)

 (1 – (31/324))  (3.0) (Eqn. C-2)

In order to make V1 = 5 V when

5 = (1 + R

3

/(R

1

+R

2

))

R

2

= R

2

,

 (1 – (31/324))  (3.0) (Eqn. C-3)

Further, if the current flowing between V

SS

and V1 is set as 5 µA, the value of R

1

R

1

+ R

2

+ R

3

= 1.8 M

 (Eqn. C-4)

+ R

2

+ R

3

becomes- and hence,

R

1

= 542 k

, R

2

= 436 k

, R

3

= 822 k

.

In this case, the variability range of voltage V1 using the electronic potentiometer function and the increment size will be as given in Table 13.

Table 14 Example 2 of V1 variable-voltage range using electronic potentiometer function and variable resistor

Variable-voltage range 4.45 (

 = 63)

7.0 (

 = 31)

9.96 (

 = 0)

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In Figures 10 and 11, the voltage VEV is obtained by the following equation by setting the electronic potentiometer between 0 and 63.

VEV = (1 - (

/324))  VREG

 = 0: VEV = (1 – (0/324))  3.0 V = 3.0 V

 = 31: VEV = (1 – (31/324))  3.0 V = 2.712 V

 = 63: VEV = (1 – (63/324))  3.0 V = 2.416 V

The increment size of the electronic potentiometer at VEV when VREG = 3.0 is :

 =

2.416

= 9.27 mV (Nominal)

63

When VREG = 3.069 V,

 = 0 : VEV = 3.069 V,  = 63 : VEV = 2.472 V

The increment size is :

 =

3.069 V – 2.472 V

= 9.476 mV

63

When VREG = 2.931 V,

 = 0 : VEV = 2.931 V,  = 63 : VEV = 2.361 V

The increment size is :

2.931 V – 2.361 V

 =

= 9.047 mV

63

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* When using the voltage V1 adjustment internal resistors or the electronic potentiometer function, it is necessary to set at least the voltage adjustment circuit and the voltage follower circuits both in the operating state using the power control setting command. Also, when the voltage multiplier circuit is OFF, it is necessary to supply a voltage externally to the V

OUT

pin.

* The pin VR is effective only when the voltage V1 adjustment internal resistors are not used (pin IRS = “L”).

Leave this pin open when the voltage V1 adjustment internal resistors are being used (pin IRS = “H”).

* Since the input impedance of the pin VR is high, it is necessary to take noise countermeasures such as using short wiring length or a shielded wire .

* The supply current increases in proportion to the panel capacitance. When power consumption increases, the

V

OUT

level may fall. The voltage (V

OUT

– V1) should be more than 3 V.

 LCD Drive voltage generator circuits

The voltage V1 is divided using resistors inside the IC to generate the voltages V2, V3, V4, and V5 that are necessary for driving the LCD. In addition, these voltages V2, V3, V4, and V5 are impedance transformed using voltage follower circuits and fed to the LCD drive circuits. The bias ratio of 1/8 or 1/6 can be selected using the

LCD bias setting command.

 At built-in power-on, and transition from power save state to display mode

After built-in power-on, at the command "2F(H)" input, or on transition from power save state to display mode, the display does not operate for a maximum period of 300 ms until the built-in power is stabilized. This period of no display is not influenced by display ON/OFF command. Despite input of display ON command during this period, the display does not operate for this period. However, the command is valid. After the wait time is finished, the display operates. (During this period of no display, all commands are acceptable.)

 Command sequence for shutting off the internal power supply

When shutting off the internal power supply, it is recommended to use the procedure given in Fig. 12 of switching

OFF the power after putting the LSI in the power save state using the following command sequence.

Procedure Description Commands

OFF 0 1 0 1 1 1 0 Power save commands



Step2





Display all ON



1 0 1 0 0 1 0 1

(multiple

End Internal supply

Fig. 12 Command sequence for shutting off the internal power supply

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 Application circuits

(Two V1 pins are described in the following examples for explanation, but they are the same.)

(1) When the voltage multiplier circuit, voltage adjustment circuit, and V/F circuits are all used

When using the internal voltage V1 adjustment resistors

V

IN

= V

DD

3-time voltage multiplication

(2) When the voltage multiplier circuit, voltage adjustment circuit, and V/F circuits are all used

When not using the internal voltage V1 adjustment resistors

V

IN

= V

DD

3-time voltage multiplication

V

DD

V

DD

C1

+

IRS

V

IN

VC6+

VC4+

M/S

C1

+

IRS

V

IN

VC6+

VC4+

M/S

VS2– VS2–

+

C1

OPEN

OPEN

VC5+

VC3+

VS1–

V1

VR

V

SS

C1

OPEN

+

R

1

R

2

R

3

VC5+

VC3+

VS1–

V1

VR

V

SS

V

SS

V

SS

C1: *1

C2: *2

C1

C1

C2

C2

C2

C2

+

+

+

+

+

+

V

OUT

V1

V2

V3

V4

V5

Rall=R1+R2+R3

Rall: *3

C1:*1

C1

C1

C2

C2

C2

C2

+

+

+

+

+

+

V

OUT

V1

V2

V3

V4

V5

C2: *2

(3) When only the voltage adjustment circuit and V/F circuits are used

(4) When only the voltage adjustment circuit and V/F circuits are used

When not using the internal voltage V1 adjustment resistors When using the internal voltage V1 adjustment resistors

V

DD

V

DD

V

SS

External power supply

Rall=R1+R2+R3

Rall: *3

C1: *1

C2: *2

OPEN

OPEN

OPEN

IRS

V

IN

VC6+

VC4+

VS2–

OPEN

OPEN

OPEN

R

1

R

2

R

3

VC5+

VC3+

VS1–

V1

VR

V

SS

M/S

C1

C2

C2

C2

C2

+

+

+

+

+

V

OUT

V1

V2

V3

V4

V5

V

SS

External power supply

C1: *1

C2: *2

OPEN

OPEN

OPEN

OPEN

OPEN

OPEN

OPEN

C1

C2

C2

C2

C2

+

+

+

+

+

IRS

V

IN

VC6+

VC4+

M/S

VS2–

VC5+

VC3+

VS1–

V1

VR

V

SS

V

OUT

V1

V2

V3

V4

V5

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LAPIS Semiconductor

(5) When only the V/F circuits are used (6) When not using the internal power supply

V

DD

V

DD

OPEN

OPEN

IRS

V

IN

VC6+

VC4+

M/S

OPEN

OPEN

IRS

V

IN

VC6+

VC4+

M/S

OPEN

VS2–

OPEN

VS2–

V

SS

OPEN

OPEN

OPEN

OPEN

VC5+

VC3+

VS1–

V1

VR

V

SS

V

SS

OPEN

OPEN

OPEN

OPEN

VC5+

VC3+

VS1–

V1

VR

V

SS

External power supply

OPEN

C2

C2

C2

C2

+

+

+

+

V

OUT

V1

V2

V3

V4

V5

OPEN

External power supply

V

OUT

V1

V2

V3

V4

V5

C2: *2

Note: When trace resistance external to COG-mounted chip does not exist,

 when C1 (*1) = 0.9

F to 5.7 F, C2 (*2) = 0.42 F to 1.2 F, use in the range Rall (*3) = 1 M

 to 5 M.

 when C1 (*1) = 1.8

F to 5.7 F, C2 (*2) = 0.42 F to 1.2 F, use in the range Rall (*3) = 500 k

 to 1 M.

Make sure that voltage multiplier output voltage, and V1 output voltage have enough margin before using this LSI.

 Initial setting

Note: If electric charge remains in smoothing capacitor connected between the LCD driver voltage output pins (V1 to V5) and the V

SS

pin, a malfunction might occur: the display screen gets dark for an instant when powered on.

To avoid a malfunction at power-on, it is recommended to follow the flowchart in the “EXAMPLES OF

SETTINGS FOR THE INSTRUCTIONS” section in page 54.

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