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C8051F060/1/2/3/4/5/6/7

1.1.

CIP-51™ Microcontroller Core

1.1.1. Fully 8051 Compatible

The C8051F06x family of devices utilizes Silicon Labs' proprietary CIP-51 microcontroller core. The CIP-

51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop software. The core has all the peripherals included with a standard 8052, including five 16-bit counter/timers, two full-duplex UARTs, 256 bytes of internal RAM, 128 byte Special Function

Register (SFR) address space, and bit-addressable I/O Ports.

1.1.2. Improved Throughput

The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system clock cycles to execute with a maximum system clock of 12-to-24 MHz. By contrast, the CIP-51 core executes 70% of its instructions in one or two system clock cycles, with only four instructions taking more than four system clock cycles.

The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that require each execution time.

Clocks to Execute

Number of Instructions

1

26

2

50

2/3

5

3

14

3/4

7

4

3

4/5

1

5

2

8

1

With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. Figure 1.5

shows a comparison of peak throughputs of various 8-bit microcontroller cores with their maximum system clocks.

25

20

15

10

5

Silicon Labs

CIP-51

(25 MHz clk)

Microchip

PIC17C75x

(33 MHz clk)

Philips

80C51

(33 MHz clk)

ADuC812

8051

(16 MHz clk)

Figure 1.5. Comparison of Peak MCU Execution Speeds

Rev. 1.2

25