Intel® 82801EB I/O Controller Hub 5 (ICH5) / Intel® 82801ER I/O

Documentation Changes

Documentation Changes

1.

2.

PCI Device Revision ID

PCI Revision ID Register Values (PCI Offset 08h) for all ICH5/ICH5R functions are shown below.

This information is not found in the datasheet. This is the standard reference document.

Device

Function

D30, F0

D31, F0

D31, F1

D31, F2

D31, F3

D31, F5

D31, F6

D8, F0

D29, F0

D29, F1

D29, F2

D29, F3

D29, F7

Description

PCI-to-PCI Bridge

PCI-to-LPC Bridge

IDE

SATA

SMBus

AC97 Audio

AC97 Modem

LAN

USB UHCI #1

USB UHCI #2

USB UHCI #3

USB UHCI #4

USB EHCI

Intel

®

ICH5

Dev ID

244Eh

24D0h

24DBh

24D1h

24DFh

24D3h

24D5h

24D6h

1051h

24D2h

24D4h

24D7h

24DEh

24DDh

ICH5 A2/A3

Rev ID

C2h

02h

02h

02h

02h

02h

02h

02h

82h

02h

02h

02h

02h

02h

Comments

ICH5 and ICH5R

ICH5 and ICH5R

ICH5 and ICH5R

ICH5 only

ICH5R only

ICH5 and ICH5R

ICH5 and ICH5R

ICH5 and ICH5R

ICH5 and ICH5R,

Note 1

ICH5 and ICH5R

ICH5 and ICH5R

ICH5 and ICH5R

ICH5 and ICH5R

ICH5 and ICH5R

NOTE:

1. Loaded from EEPROM. If EEPROM contains either 0000h or FFFFh in the device ID location, then 1051h is used. Refer to the ICH5 EEPROM Map and Programming Guide for LAN Device IDs.

Figure 2 Note Addition

The following note is added below Figure 2 for consistency with other requirements:

Note: Diodes must be Schottky

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82801EB ICH5/82801ER ICH5R Specification Update 25

Documentation Changes

3.

Table 177 Correction

Table 177 is replaced as follows:

4.

Table 177. DC Current Characteristics

Power Plane

Vcc1_5 Core

Vcc3_3 I/O

VccSus3_3

(3)

VccRTC

V_CPU_IO

V5REF

V5REF_Sus

S0

770 mA

480 mA

360 mA

N/A

2.5 mA

250 µA

200 µA

Maximum Power Consumption

(4)

S1 S3 S4/S5

201 mA

1 mA

73 mA

N/A

2.5 mA

250 µA

200 µA

N/A

N/A

73 mA

N/A

N/A

N/A

200 µA

N/A

N/A

73 mA

N/A

N/A

N/A

200 µA

G3

N/A

N/A

N/A

6 µA

(1,2)

N/A

N/A

N/A

NOTES:

1. Only the G3 state for this power well is shown to provide an estimate of battery life.

2. Icc(RTC) data is taken with VccRTC at 3.0V while the system is in a mechanical off (G3) state at room temperature.

3. Due to the integrated voltage regulator, VccSus1_5 is part of the VccSus3_3 power rail.

4. Icc data for Sx states is taken while the system is at nominal Vcc and at room temperature.

LAN_RST# Correction

The description for LAN_RST# in Section 2.11, Power Management Interface, Table 13 is being updated as follows:

Table 13. Power Management Interface Signals (partial)

Name

LAN_RST#

Type

I

Description

LAN Reset: When asserted, the internal LAN controller will be put into reset. This signal must be asserted at least 10 mS after the resume well power (VccSus3_3) is valid. When deasserted, this signal is an indication that the resume well power is stable.

5.

T173 Correction

The parameter of T173 in Table 194 of Section 19.3 is being corrected as follows:

Table 194. Power Sequencing and Reset Signal Timings (partial)

Sym

t173

Parameter

VccSus supplies active to LAN_RST# HIGH, RSMRST# HIGH

Min Max Units Notes Fig

10 mS

20

21

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82801EB ICH5/82801ER ICH5R Specification Update

Documentation Changes

6.

PME Wake Doc Change

The following changes are made to Section 5.13.7.3: Table 64.

Note 1 is changed to “This is a wake event from S5 only if the sleep state was entered by setting the

SLP_EN and SLP_TYP bits via software or from a power failure.”

Note 3 is added: “This is a wake event from S5 only if the sleep state was entered by setting the

SLP_EN and SLP_TYP bits via software.”

The note associated with GPI:[0:n] is changed from Note 1 to Note 3.

The following changes are made to Section 5.13.7.4:

The last sentence of the third paragraph is changed to read: “There are four possible events that will wake the system after a power failure.

Add a fourth item: PME: PME_STS or PME_B0_STS, if enabled, will wake the system from S5 if

S5 is entered from an AC power failure or if entered by a write to the SLP_TYP and SLP_EN registers.

7.

8.

The following changes are made to Section 9.10.6:

The third sentence of the description for PME_B0_STS is changed to: “If the PME_B0_STS bit is set, and the system is in an S1-S4 state (or S5 state due to SLP_TYP and SLP_EN or due to return from AC power failure), then the setting of the PME_B0_STS will generate a wake event, and an

SCI (or SMI# if SCI_EN is not set) will be generated.”

The third sentence of the description for PME_STS is changed to: “If the PME_STS bit is set, and the system is in an S1-S4 state (or S5 state due to SLP_TYP and SLP_EN or due to return from AC power failure), then the setting of the PME_STS will generate a wake event, and an SCI will be generated.”

The following changes are made to Section 9.10.7:

The second sentence of the description for PME_EN is changed to: “PME can be a wake event from the S1-S4 state or from S5 (if entered via SLP_EN or from AC power recovery, but not power button override).

PCIRST# Description Change

In Table 7 of Section 2.5, this sentence in the description for PCIRST# is changed.

“The ICH5 drives PCIRST# inactive a minimum of 1 mS after PWROK is driven active.” is changed to read

“The ICH5 drives PCIRST# inactive a minimum of 1 mS after PWROK and VRMPWRGD are driven active.”

APM I/O Decode Correction

The second sentence of Section 9.9 (APM I/O Decode) is being changed to “This register space cannot be moved (fixed I/O location).”

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82801EB ICH5/82801ER ICH5R Specification Update 27

Documentation Changes

9.

10.

11.

12.

SATA PCS Register Changes

Section 11.1.33 (PCS - Port Control and Status Register) is changed as indicated for the following bits:

Bits

1

0

Description

Port 1 Enabled (P1E) - R/W

0 = Disabled. The port is in the “off” state and cannot detect any devices.

1 = Enabled. The port is in the “on” state and can detect devices.

Port 0 Enabled (P0E) - R/W

0 = Disabled. The port is in the “off” state and cannot detect any devices.

1 = Enabled. The port is in the “on” state and can detect devices.

Memory Map Table Change

The last row of Table 133 of Section 6.4 (Memory Map) is being replaced as follows:

Memory Range Target

All other PCI

Dependency/Comments

Any memory range access that makes it to the ICH5’s PCI bus and is not specified in one of the D31:F0 0xE0 - 0xEF registers or below 16MB will be master aborted on PCI.

SMBus Host_Busy Bit Correction

Section 14.2.1 HST_STS - Host Status Register is being corrected. Specifically, bit-0 Host_Busy is corrected to read as follows:

0 = Cleared by the ICH5 when the current transaction is completed.

1 = Indicates that the ICH5 is running a command from the host interface. No SMB registers should be accessed while this bit is set, except the BLOCK DATA BYTE or LAST BYTE

Registers. The BLOCK DATA BYTE and LAST BYTE registers can be accessed when this bit is set only when the SMB_CMD bits in the Host Control Register are programmed for Block command or I2C Read command. This is necessary in order to check the DONE_STS bit.

GEN_CNTL Register Correction

Section 9.1.22, D31:F0;GEN_CNTL has an inaccurate description for System Bus Message

Disable (bit-7). It is replaced as follows:

Bit

7

Description

System Bus Message Disable - R/W

1 = Has no effect. (Default)

0 = Disables the ICH5 IOAPIC controller from generating any more system bus interrupt messages.

Note: It is possible for the ICH5 to deliver up to 1 system bus interrupt message from the time this configuration bit is set to 0.

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82801EB ICH5/82801ER ICH5R Specification Update

13.

Documentation Changes

Assorted Corrections

Section 9.6.3, RTC_REGB has an inaccurate description for the AIE bit. It is replaced as follows:

Bit

5

Description

Alarm Interrupt Enable (AIE) - R/W. This bit is cleared by RTCRST#, but not on any other reset.

0= Disable

1= Enable. Allows an interrupt to occur when the AF is set by an alarm match from the update cycle.

An alarm can occur once a second, once an hour, once a day, or once a month.

Table-53 in Section 5.11.5 (Clearing Battery-Backed RTC RAM) is inaccurate and is replaced as follows:

Bit Name Register Location Register Location Bit Location Default

FREQ_STRAP:[3:0]

AIE

AF

PWR_FLR

AFTERG3_EN

RTC_PWR_STS

PRBTNOR_STS

PME_EN

BACK_CNTL

RTC REG B

RTC REG C

GEN_PMCON_3

GEN_PMCON_3

GEN_PMCON_3

PM1_STS

GPE0_EN

RI_EN GPE0_EN

NEW_CENTURY_STS TCO1_STS

INTRD_DET

TOP_SWAP

RTC_EN

TCO2_STS

BACK_CNTL

PM1_EN

D31:F0;D5h

I/O Space

I/O Space

D31:F0;A4h

D31:F0;A4h

D31:F0;A4h

PMBase + 00h

PMBase + 2Ch

PMBase + 2Ch

TCOBase + 04h

TCOBase + 06h

D31:F0;D5h

PMBase + 02h

3:0

5

5

1

0

2

11

11

8

7

0

5

10

0

0

0

1

1111b

0

0

0

0

0

0

0

0

Section 9.10.9, SMI_STS has an inaccurate attribute for the TCO_STS bit (bit-13). It is incorrectly listed as RO. It is actually R/WC.

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82801EB ICH5/82801ER ICH5R Specification Update 29

Documentation Changes

14.

GPIO SMI/SCI Mapping

The notes associated with selected rows of Table 74 (GPIO Implementation) are corrected as follows. Other rows remain unchanged.

GPIO

GPI0

GPI1

Type

Alternate

Function

(Note 1)

Input

Only

REQA#

Input

Only

REQB# or

REQ55#

GPI:[5:2]

Input

Only

GPI6

GPI7

GPI8

Input

Only

Input

Only

Input

Only

GPI:[10:9]

Input

Only

PIRQ:[E:H]#

N/A

Unmuxed

Unmuxed

OC:[4:5]#

Core

Core

Core

Resume

Resume

GPI11

GPI12

GPI13

Input

Only

Input

Only

Input

Only

GPI:[15:14]

Input

Only

SMBAlert#

Unmuxed

Unmuxed

OC:[6:7]#

Power

Well

Tolerant

Core

Core

Resume

Resume

Resume

Resume

5.0 V

5.0 V

5.0 V

5.0 V

5.0 V

3.3 V

5.0 V

3.3 V

3.3 V

3.3 V

5.0 V

Notes

• GPIO_USE_SEL bit 0 enables REQ/GNTA# pair.

• Input active status read from GPE0_STS bit 16.

• Input active high/low set through GPI_INV bit 0.

• GPIO_USE_SEL bit 1 enables REQ/GNTB# pair (see Note

4).

• Input active status read from GPE0_STS bit 17.

• Input active high/low set through GPI_INV bit 1.

• GPIO_USE_SEL bits {2:5] enable PIRQ:[E:H]#.

• Input active status read from GPE0_STS bits [18:21].

• Input active high/low set through GPI_INV bits [2:5].

• Input active status read from GPE0_STS bit 22.

• Input active high/low set through GPI_INV bit 6.

• Input active status read from GPE0_STS bit 23.

• Input active high/low set through GPI_INV bit 7.

• Input active status read from GPE0_STS bit 24.

• Input active high/low set through GPI_INV bit 8.

• GPIO_USE_SEL bits [9:10] enable OC:[4:5]#.

• Input active status read from GPE0_STS bits [25:26].

• Input active high/low set through GPI_INV bits [9:10].

• GPIO_USE_SEL bit 11 enables SMBAlert#.

• Input active status read from GPE0_STS bit 27.

• Input active high/low set through GPI_INV bit 11.

• Input active status read from GPE0_STS bit 28.

• Input active high/low set through GPI_INV bit 12.

• Input active status read from GPE0_STS bit 29.

• Input active high/low set through GPI_INV bit 13.

• GPIO_USE_SEL bits [14:15] enable OC:[6:7]#.

• Input active status read from GPE0_STS bits [30:31].

• Input active high/low set through GPI_INV bits [14:15].

15.

16.

TCO_STS Correction

The TCO_STS bit, bit-13 in D31:F0;SMI_STS, is incorrectly listed as RO in the bit description

(Section 9.10.9). This bit is R/WC.

SRS/PRS Bit Reference Correction

The SRS and PRS are incorrectly referenced to D31:F0;Offset D0h in fields SEC_SIG_MODE and

PRI_SIG_MODE of both IDE_CONFIG registers (D31:F1 and F2 at offset 54h). The correct reference is to D31:F0.

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82801EB ICH5/82801ER ICH5R Specification Update

17.

18.

19.

20.

21.

Documentation Changes

GEN2_DEC Correction

The description for Generic I/O Decode Range 2 Base Address (GEN2_BASE) in section 9.1.32, changes to “This address is aligned on a 16-byte boundary and must have address lines 31:16 as 0.”

The note remains unchanged.

GPIO_USE_SEL2 Correction

The following note is added to the Description for GPIO_USE_SEL2 (Section 9.12.6):

4. Bit-16 is not implemented because GPIO selection is controlled by bit-8.

GP_LVL Default

Table 153 (Registers to Control GPIO Address Map) incorrectly identifies the default value of the

GP_LVL register. The correct default value is 1B3F 0000h. This is correctly identified in the register description.

IDE MSE Bit

In section 10.1.3 (PCI Command Register) the description for bit-1 is incorrect and is changed to the following:

Bit

1 Memory Space Enable (MSE) - RO

Description

USB Port Number Documentation Corrections

In section 5.20.10.1.3, the description of bits 20:23 of the EHCI Host Controller Structural

Parameters register indicates an incorrect value for these bits. The sentence is changed to:

“This 4-bit field represents the numeric value assigned to the debug port (i.e., 000 1 = port 0).”

The PWAKE_CAP.Port Wake Up Capability Mask (section 13.1.25) bit description is changed to the following:

Bit Description

8:1

Port Wake Up Capability Mask — R/W. Bit positions 1 through 8 correspond to a physical port implemented on this host controller. For example, bit position 1 corresponds to port 0 , bit position 2 corresponds to port 1 , etc.

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82801EB ICH5/82801ER ICH5R Specification Update 31