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PGA Input
PGA Output
PGA Gain
Figure 7: ALC Normal Mode Operation
3.9.2 ALC Parameter Definitions
Automatic level and volume control features are complex and have difficult to understand traditional names for many features and controls. This section defines some terms so that the explanations of this subsystem are more clear.
ALC Maximum Gain: Register 32 (ALCMXGAIN) This sets the maximum allowed gain in the PGA during normal mode ALC operation. In the Limiter mode of ALC operation, the ALCMXGAIN value is not used. In the Limiter mode, the maximum gain allowed for the PGA is set equal to the pre-existing PGA gain value that was in effect at the moment in time that the Limiter mode is enabled.
ALC Minimum Gain: Register 32 (ALCMNGAIN) This sets the minimum allowed gain in the PGA during all modes of ALC operation. This is useful to keep the AGC operating range close to the desired range for a given application scenario.
ALC Target Value: Register 33 (ALCSL) Determines the value used by the ALC logic decisions comparing this fixed value with the output of the ADC. This value is expressed as a fraction of Full Scale (FS) output from the ADC. Depending on the logic conditions, the output value used in the comparison may be either the instantaneous value of the ADC, or otherwise a time weighted average of the ADC peak output level.
ALC Attack Time: Register 34 (ALCATK) Attack time refers to how quickly a system responds to an increasing volume level that is greater than some defined threshold. Typically, attack time is much faster than decay time. In the NAU88C22, when the absolute value of the ADC output exceeds the ALC Target Value, the
PGA gain will be reduced at a step size and rate determined by this parameter. When the peak ADC output is at least 1.5dB lower than the ALC Target Value, the stepped gain reduction will halt.
ALC Decay Time: Register 34 (ALCDCY) Decay time refers to how quickly a system responds to a decreasing volume level. Typically, decay time is much slower than attack time. When the ADC output level is below the
ALC Target value by at least 1.5dB, the PGA gain will increase at a rate determined by this parameter. The decay time constant is determined by the setting in register 34, bits 4 to 7 (ALCDCY), which sets the delay between increases in gain. In Limiter mode, the time constants are faster than in ALC mode. (See Detailed
Register Map.)
ALC Hold Time Register 33 (ALCHLD) Hold time refers to a duration of time when no action is taken. This is typically to avoid undesirable sounds that can happen when an ALC responds too quickly to a changing input signal. The use and amount of hold time is very application specific. In the NAU88C22, the hold time value is the duration of time that the ADC output peak value must be less than the target value before there is an actual gain increase.
NAU88C22 Datasheet Rev 0.6 Page 24 of 101 June, 2016
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Table of contents
- 12 GENERAL DESCRIPTION
- 12 Analog Inputs
- 12 Analog Outputs
- 13 ADC, DAC, and Digital Signal Processing
- 13 Realtime Signal Level Readout and DSP Status
- 13 Digital Interfaces
- 13 Clock Requirements
- 14 POWER SUPPLY
- 14 Power-On Reset
- 14 Power Related Software Considerations
- 14 Software Reset
- 16 INPUT PATH DETAILED DESCRIPTIONS
- 16 Programmable Gain Amplifier (PGA)
- 17 Zero Crossing Example
- 17 Positive Microphone Input (MICP)
- 18 Negative Microphone Input (MICN)
- 19 Microphone biasing
- 19 Line/Aux Input Impedance and Variable Gain Stage Topology
- 22 Left and Right Line Inputs (LLIN and RLIN)
- 22 Auxiliary inputs (LAUXIN, RAUXIN)
- 22 ADC Mix/Boost Stage
- 23 Input Limiter / Automatic Level Control (ALC)
- 23 Normal Mode Example Operation
- 24 ALC Parameter Definitions
- 25 ALC Peak Limiter Function
- 25 ALC Normal Mode Example Using ALC Hold Time Feature
- 25 Noise Gate (Normal Mode Only)
- 27 ALC Example with ALC Min/Max Limits and Noise Gate Operation
- 27 ALC Register Map Overview
- 28 Limiter Mode
- 29 ADC DIGITAL BLOCK
- 29 Sampling / Oversampling Rate, Polarity Control, Digital Passthrough
- 30 ADC Digital Volume Control and Update Bit Functionality
- 30 ADC Programmable High Pass Filter
- 30 Programmable Notch Filter
- 32 DAC DIGITAL BLOCK
- 32 DAC Soft Mute
- 32 DAC AutoMute
- 32 DAC Sampling / Oversampling Rate, Polarity Control, Digital Passthrough
- 33 DAC Digital Volume Control and Update Bit Functionality
- 33 DAC Automatic Output Peak Limiter / Volume Boost
- 34 5-Band Equalizer
- 35 3D Stereo Enhancement
- 35 Companding
- 35 µ-law
- 35 A-law
- 36 8-bit Word Length
- 37 ANALOG OUTPUTS
- 37 Main Mixers (LMAIN MIX and RMAIN MIX)
- 37 Auxiliary Mixers (AUX1 MIXER and AUX2 MIXER)
- 38 Right Speaker Submixer
- 38 Headphone Outputs (LHP and RHP)
- 39 Speaker Outputs
- 41 Auxiliary Outputs
- 41 MISCELLANEOUS FUNCTIONS
- 41 Slow Timer Clock
- 42 General Purpose Inputs and Outputs (GPIO1, GPIO2, GPIO3) and Jack Detection
- 42 Automated Features Linked to Jack Detection
- 43 CLOCK SELECTION AND GENERATION
- 44 Phase Locked Loop (PLL) General Description
- 45 Phase Locked Loop (PLL) Design Example
- 45 CSB/GPIO1 as PLL output
- 47 CONTROL INTERFACES
- 47 Selection of Control Mode
- 47 C Style Interface)
- 47 2-Wire Protocol Convention
- 48 2-Wire Write Operation
- 49 2-Wire Read Operation
- 49 SPI Control Interface Modes
- 50 SPI 3-Wire Write Operation
- 50 SPI 4-Wire 24-bit Write and 32-bit Read Operation
- 50 SPI 4-Wire Write Operation
- 51 SPI 4-Wire Read Operation
- 52 Software Reset
- 53 DIGITAL AUDIO INTERFACES
- 53 Right-Justified Audio Data
- 53 Left-Justified Audio Data
- 54 S Audio Data
- 54 PCM A Audio Data
- 55 PCM B Audio Data
- 55 PCM Time Slot Audio Data
- 57 Control Interface Timing
- 59 Audio Interface Timing
- 61 APPLICATION INFORMATION
- 61 Typical Application Schematic
- 62 Recommended power up and power down sequences
- 62 Power Up (and after a software generated register reset) Procedure Guidance
- 62 Power Down
- 63 Unused Input/Output Tie-Off Information
- 65 Power Consumption
- 66 Supply Currents of Specific Blocks
- 67 APPENDIX A: DIGITAL FILTER CHARACTERISTICS
- 73 APPENDIX B: COMPANDING TABLES
- 73 µ-Law / A-Law Codes for Zero and Full Scale
- 73 µ-Law / A-Law Output Codes (Digital mW)
- 74 APPENDIX C: DETAILS OF REGISTER OPERATION
- 94 APPENDIX D: REGISTER OVERVIEW
- 96 PACKAGE DIMENSIONS
- 99 ORDERING INFORMATION