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CHAPTER 5
MOTHERBOARD LAYOUT AND ROUTING GUIDELINES
5. Motherboard Layout and Routing Guidelines
This section describes layout and routing recommendations that should be followed to insure a robust design. These guidelines should be followed as closely as possible. Any deviations from the guidelines listed here should be simulated to insure adequate margin is still maintained in the design.
5.1 Placement
The pins on the 440LX AGPset components have been assigned in order to simplify routing and keep board reduce fabrication cost by enabling a 4-layer “UP” motherboard design. Figure 5-1 shows the signal quadrants of the 82443LX. The component placement on the motherboard with this in mind. This will simplify routing and minimize the number of signals that cross. The individual signals within the respective groups have also been placed in order to simply route with only 2 PCB layers.
A complete list of signals and ball assignment can be found in the 82443LX PAC Data Sheet.
440LX
Top View
Pin #1 Corner
A.G.P.
Quadrant
U
V
R
T
N
P
L
M
G
H
J
K
E
F
C
D
A
B
AC
AD
AE
AF
W
Y
AA
AB
PCI
Quadrant
GTL+
Quadrant
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
DRAM
Quadrant
Figure 5-1. Signal Quadrants
Examples of the proposed component placement for single Pentium II processor designs are shown in
Figure 5-2 and 5-3 for both an ATX and NLX form factor design.
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ATX Form Factor:
1. The ATX placement and layout Figure 5-2 is recommended for single (UP) Pentium II processor
440LX system design.
2. The example placement Figure 5-2 shows 4 PCI slots, 2 ISA slots, 3 DIMM sockets, and one A.G.P.
connector.
3. For an ATX form factor design, the A.G.P. compliant graphics device can be on the motherboard
(device down option) or on an A.G.P. connector (device up option).
4. The trace length limitation between critical connections will be addressed later in this document.
5. The Figure 5-2 is for reference only and the trade-off between the number of PCI and ISA slots, number of DIMM sockets, and other motherboard peripherals needs to be evaluated for each design.
5-2
Figure 5-2. Example ATX Layout for a UP Pentium
®
II/440LX Design
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NLX Form Factor:
MOTHERBOARD LAYOUT AND ROUTING GUIDELINES
1. The NLX placement and layout below is recommended for a single (UP) Pentium II/440LX system design.
2. The example placement below shows one Slot 1 connector, 3 DIMM sockets, and A.G.P. compliant device down.
3. For an NLX form factor design, the A.G.P. compliant graphics device may readily be integrated on the motherboard (device down option).
4. The trace length limitation between critical connections will be addressed later in this document.
5. The figure below is for reference only and the trade-off between the number of DIMM socket, and other motherboard peripherals need to be evaluated for each design.
SDRAM DIMMs
AGP
x x x
CKBF
443LX
x
Pentium
(R)
II/Slot 1 Processor
PIIX4
PCI/ISA Riser Card
Figure 5-3. Example NLX Placement for a UP Pentium
®
II processor/440LX Design
Note:
AGP can also be on the riser card.
I/O Ports
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5.2 Board Description
For a single Pentium II processor/440LX AGPset motherboard design, a 4 layer stack-up arrangement is recommended. The stack up of the board is shown in Figure 5-4. The impedance of all the signal layers must be between 50 and 80 ohms. Lower trace impedance will reduce signal edge rates, reduce over & undershoot, and will create less crosstalk. Higher trace impedance will increase edge rates and may slightly decrease signal flight times.
Z = 60
Ω
5 mils
47 mils
5 mils
Primary Signal Layer (1/2 oz. cu.)
PREPREG
Ground Plane (1 oz. cu.)
CORE
Power Plane (1 oz. cu.)
PREPREG
Secondary Signal Layer (1/2 oz. cu.)
Z = 60
Ω
Total board width = 62.6 mils
Figure 5-4. Four Layer Board Stack-up
Note that the top and bottom routing layers specify 1/2 oz. cu. However, after plating, the traces will be
1 oz. cu. Please check with your fab vendor on the exact value and insure that any signal simulation is performed.
Note:
A thicker core helps reduce board warpage.
The Intel 440LX Uni-Processor reference design has been successfully routed on a 4 layer board. If more signal layers are necessary one of the six layer stack-up should be used. For DP designs a six layer stack-up is recommended. Two examples are shown below. The first example has 4 signal layers, 1 power plane and 1 ground plane. The second example shows 3 signal plane layers, 2 power planes and 1 ground plane. The second option makes it easier to accommodate all of the power planes required in a 440LX design.
If a 6 layer stack-up is used, route the GTL+ bus signals on the inner layers. The primary and secondary signal layer can be used for GTL+ signals where needed. On the two inner layers (Figure 5-5) route orthogonally to reduce crosstalk.
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Z = 66
Ω
MOTHERBOARD LAYOUT AND ROUTING GUIDELINES
Z = 73
Ω
Z = 66
Ω
6 mils
18 mils
6 mils
18 mils
6 mils
Primary Signal Layer (1/2 oz. cu.)
PREPREG
Ground Plane (1 oz. cu.)
CORE
Inner Layer #1 (1 oz. cu.)
PREPREG
Inner Layer #2 (1 oz. cu.)
CORE
Power Plane (1 oz. cu.)
PREPREG
Secondary Signal Layer (1/2 oz. cu.)
Total board width = 62.4 mils
Z = 60
Ω
Z = 59
Ω
Z = 60
Ω
Figure 5-5. Six Layer Board Stack-up with 4 signal planes, 2 power planes
5 mils
18 mils
8 mils
18 mils
5 mils
Primary Signal Layer (1/2 oz. cu.)
PREPREG
Ground Plane (1 oz. cu.)
CORE
Inner Layer #1 (1 oz. cu.)
PREPREG
Power Plane #1 (1 oz. cu.)
CORE
Power Plane #2 (1 oz. cu.)
PREPREG
Secondary Signal Layer (1/2 oz. cu.)
Total board width = 62.4 mils
Figure 5-6. Six Layer Board Stack-up with 3 signal planes, 3 power planes
Additional guidelines on board buildup, placement and layout include:
•
Dual ended termination is recommended for GTL+ signals. One set of termination resistor is present on the
Pentium II processor, and the other set of termination resistors are on the motherboard. For single end termination please see appendix F.
•
For a 6-layer dual processors design, no termination is required on the motherboard, as each end of the GTL+ bus is terminated on each Pentium II processors. If a single Slot 1 is populated in a DP design, the second Slot
1 must be populated with a termination card.
•
The termination resistors on the GTL+ bus should be 56 ohms.
•
The board impedance (Z) should be 65 ohms ± 20%.
•
FR-4 material should be used for the board fabrication.
•
The ground plane should not be split. If necessary, it is acceptable to route a signal on the power plane, but only for very short distance.
•
Place vias for decoupling capacitors as close to the capacitor pads as possible.
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MOTHERBOARD LAYOUT AND ROUTING GUIDELINES
5.3 Ball Grid Array (BGA) Component
This section addresses the breakout of the 492 BGA PAC.
5.3.1 BGA Pad Size
The PAC contains 6 rows of balls. To break out from the package route two traces between pads to achieve a 4 layer motherboard design. Figure 5-7 shows routing examples for 24 mil and 20 mil ball pads. To route two traces between 24 mil pads, 5 mil traces and 5 mil spaces are required for a 24 mil pad size. To route two traces between 20 mil pads, 6 mil traces and 6 mil spacing can be used. Either pad size is acceptable, so the pad size tradeoff should be determined by the manufacture. If larger trace widths are desired, another alternative is to route 5/5 or 6/6 within the BGA pads, and then “neck up” to the larger trace widths once you have cleared the BGA component area.
28 mil diameter mask
24 mil diameter pad
5 mil SPACE 5 mil TRACE
24 mil diameter mask
24 mil diameter pad
6 mil SPACE
6 mil TRACE
Figure 5-7. Routing Example for 24 mil and 20 mil Ball Pads
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MOTHERBOARD LAYOUT AND ROUTING GUIDELINES
R6
COMPONENT SIDE ROUTING FOR 6 ROWS OF BALL PADS
R5 R4 R3 R2
R1
24 mil diameter pad
12 mil diameter via plated
24 mil diameter mask
20 mil diameter pad
6 mil spacing
6 mil traces
Figure 5-8. BGA Routing Example
Using the routing examples shown in Figure 5-7 and Figure 5-8, the first 3 rows of balls can be routed on the top signal layer. The inner two rows (R4 & R5) must be routed on the bottom side or the inner layers of a 6-layer board. As a result, vias are required in between the BGA pads. The vias will be discussed in the next section. NOTE: The inner most row of balls on the PAC (R6 in the figure above) are power balls or ground balls. These balls will require vias to connect them to their proper plane layer.
5.3.2 BGA Vias
Figure 5-9 shows the connection between the BGA pad and a via. All vias located between the BGA
pads must be covered with solder mask! This prevents solder from wicking to the vias pad. A 24 mil via pad size is recommended.
30 mil diameter solder ball
20 or 24 mil diameter pad
24 or 28 mil diameter solder mask
10 mil trace
16 to 10 mil diameter via plated
32 or 24 mil diameter pad
Typical Vias - PAD = 25 - 32
Drill = 15 -
16
Figure 5-9. BGA Pads and Vias
NOTE:
Solder Mask must cover the Via
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5.3.3 BGA Routing
Figure 5-10 and Figure 5-11 show routing example for the component and solder sides of a 4 layer board. The first three rows are routed on the component side, while the inner three rows are routed on the solder side. The examples shows 6 mil trace widths.
COMPONENT SIDE ROUTING FOR 6 ROWS OF BALL PADS
R6 R5 R4 R3 R2
R1
50 mil
PITCH
24 mil diameter pad
12 mil diameter via plated
24 mil diameter mask
20 mil diameter pad
6 mil SPACE
Figure 5-10. BGA Component Side Routing Example
6 mil TRACE
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MOTHERBOARD LAYOUT AND ROUTING GUIDELINES
R6
BACK SIDE ROUTING FOR 6 ROWS OF BALL PADS
R5 R4 R3 R2
R1
50 mil
PITCH
24 mil diameter pad
12 mil diameter via plated
10 mil space 6 mil trace
Figure 5-11. BGA Solder Side/Inner Layer Routing Example
5.4 Routing Guidelines
If the guidelines are not followed then it is imperative that you simulate your design. If the guidelines are followed, simulation is still recommended. Contact your Intel Field Representative for
IBIS Models.
5.4.1 Host Bus Layout and Routing Guidelines
The GTL+ routing guidelines were developed through simulation of the Pentium II processor/440LX interconnect.
Single Processor (UP) Layout Guidelines:
•
Slot 1 connector to the beginning of the GTL+ termination stub: 1.5” min and 10” max.
•
The GTL+ termination stub is not a critical trace and can be as much as 6”.
•
PAC to the beginning of the GTL+ termination stub: 1.5” max.
•
For single end termination designs see appendix F.
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Dual Processor Layout Guidelines:
•
Slot 1 to Slot 1: 3” min to 14” max.
•
PAC Stub Length: 1.5” max.
Figure 5-12. “UP” Layout
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Figure 5-13. “DP” Layout
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5.4.2 A.G.P. Layout and Routing Guidelines
MOTHERBOARD LAYOUT AND ROUTING GUIDELINES
For the definition of the A.G.P. Interface functionality (protocols, rules and signaling mechanisms, as well as the platform level aspects of A.G.P. functionality), refer to the latest A.G.P. Interface
Specification. This section describes 440LX platform recommendations for the A.G.P. interface. Refer to AGP Interface Specification revision 1.0 for more information.
The PAC A.G.P. implementation is compliant with the Accelerated Graphics Port Interface
Specification Rev. 1.0. The PAC supports only synchronous A.G.P. interface, coupling to the host bus frequency. The A.G.P. interface can reach a theoretical 532-Mbytes/sec transfer rate. The actual bandwidth will be limited by the capability of the PAC memory subsystem.
Throughout this section the term “data” refers to AD[31:0], C/BE[3:0]# and SBA [7:0]. The term
“strobe” refers to AD_STB[1:0] and SB_STB.
Associate Data
AD[15:0] and C/BE[1:0]#
AD[31:16] and C/BE[3:2]#
SBA[7:0]
Table 5-1A. Associated Data and Strobe
AD_STB0
AD_STB1
SB_STB
Strobe
A.G.P. Connector (“Up Option”) Layout Guidelines:
The maximum line length is dependent on the routing rules used on the motherboard. These routing rules were created to give design freedom by making tradeoffs between signal coupling (trace spacing) and line lengths. These routing rules are divided by trace spacing. In 1:1 spacing, the distance between the traces (air gap) is the same as the width of traces. In 1:2 spacing, the distance between the traces is twice the width of the traces.
A.G.P.
Compliant
Graphics
Device
Always 1:2 Strobe Routing
A.G.P.
Signal Bundle
440LX
PCI/A.G.P.
Controller
1:1 (Data) Routing
4.5”-9.5”
1:2 (Data) Routing
A.G.P.
CONNECTOR
Figure 5-14. A.G.P. Connector Layout Guidelines
For trace lengths that are between 1.0” and 4.5”, a 1:1 trace spacing is recommended for data lines. The strobe requires a 1:2 trace spacing. This is for designs that require less than 4.5 inches between the
A.G.P. connector and the A.G.P. target.
Longer lines have more crosstalk. Therefore in order to maintain skew, longer line lengths require a greater amount of spacing between traces. For line lengths greater than 4.5” and less than 9.5”, 1:2 routing is recommended for all data lines and strobes. For all designs, the line length mismatch must be less than 0.5”, and the strobe must be the longest signal of the group.
Reduce line length mismatch to insure added margin. In order to reduce trace to trace coupling
(crosstalk), separate the traces by as much as possible.
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Table 5-1B. Source Synchronous Routing Recommendations
Width:Space
1:1(Data) / 1:2 (Strobe)
1:2
Trace Line Length
Data / Strobe 1.0” < line length < 4.5”
Data / Strobe 1.0” < line length < 9.5”
Line Length Matching
-0.5”, strobe longest trace
-0.5”, strobe longest trace
The clock lines on the motherboard can couple with other traces. It is recommended that the clock spacing (air gap) be at least twice the trace width to any other traces. It is also strongly recommended that the clock spacing be at least four times its trace width to any strobes.
The clock lines on the motherboard need to be simulated to determine the proper line length. The motherboard needs to be designed to the characteristics of clock driver that is being used and motherboard trace topology. These clocks need to meet the loading of the receiving device as well as the add-in trace length.
Additionally, control signals less than 8.5 inches can be routed 1:1. Control signals (non-data signals) greater than 8.5 inches should be routed 1:2.
Width:Space
1:1
1:2
1:2 (1:4 to Strobe)
Table 5-1C. Control Signal Routing Recommendations
Board
Motherboard
Motherboard
Motherboard
Control signals
Control signals
Clock
Trace Line Length Pull-up Stub Length
1.0” < line length < 8.5” < 0.5” (Strobes < 0.1”)
1.0” < line length < 10.0” < 0.5” (Strobes < 0.1”)
Some of the control signals require pull-up resistors to be placed on the motherboard. A.G.P. signals must be pulled up to V
CC
3.3
using 8.2 kohm to 10 kohm pull-up resistors (refer to section 7.2.6 A.G.P.
Signals Checklist). Pull-up resistors should be discrete resistors, as resistor packs will need longer stub lengths and may break timings. The maximum stub length on a strobe trace is 0.1 inch. The maximum stub trace length on all other traces is 0.5.”
On-board A.G.P. Compliant Device (“Down Option”) Layout Guidelines:
Routing guidelines for the device ‘down’ option are very similar to those when using a connector.
Always 1:2 Strobe Routing
A.G.P.
Compliant
Graphics
Device
1”-12” 1:2 (Data) Routing
440LX
PCI/A.G.P.
Controller
Figure 5-15. On-board A.G.P. Compliant Device Layout Guidelines
For trace lengths that are between 1.0” and 4.5”, a 1:1 trace spacing is recommended for data lines. The strobe requires a 1:2 trace spacing. This is for designs that require less than 4.5 inches between the
A.G.P. connector and the A.G.P. target.
Longer lines have more crosstalk. Therefore in order to maintain skew, longer line lengths require a greater amount of spacing between traces. For line lengths greater than 4.5” and less than 9.5”, 1:2 routing is recommended for all data lines and strobes. For all designs, the line length mismatch must be less than 0.5”, and the strobe must be the longest signal of the group.
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MOTHERBOARD LAYOUT AND ROUTING GUIDELINES
Table 5-1D. Source Synchronous Routing Recommendations
Width:Space
1:1(Data) / 1:2 (Strobe)
1:2
Trace Line Length
Data / Strobe 1.0” < line length < 4.5”
Data / Strobe 1.0” < line length < 12.0”
Line Length Matching
-0.5”, strobe longest trace
-0.5”, strobe longest trace
The clock lines on the motherboard can couple with other traces. It is recommended that the clock spacing (air gap) be at least twice the trace width to any other traces. It is also strongly recommended that the clock spacing be at least four times its trace width to any strobes.
The clock lines on the motherboard need to be simulated to determine the proper line length. The motherboard needs to be designed to the characteristics of clock driver that is being used and motherboard trace topology. These clocks need to meet the loading of the receiving device as well as the add-in trace length.
Additionally, control signals less than 8.5 inches can be routed 1:1. Control signals greater than
8.5 inches should be routed 1:2.
Table 5-1E. Control Signal Line Length Recommendations
Width:Space
1:1
1:2
1:2 (1:4 to
Strobe)
Board Trace Line Length Pull-up Stub Length
Motherboard Control signals 1.0” < line length < 8.5” < 0.5” (Strobes < 0.1”)
Motherboard Control signals 1.0” < line length < 12.5” < 0.5” (Strobes < 0.1”)
Motherboard Clock
Some of the control signals require pull-up resistors to be installed on the motherboard. A.G.P. signals must be pulled up to V
CC
3.3
using 8.2 kohm to 10 kohm pull-up resistors (refer to section 4.2.6 A.G.P.
Signals Checklist). Pull-up resistors should be discrete resistors, as resistor packs will need longer stub lengths and may break timings. The maximum stub length on a strobe trace is 0.1”. The maximum stub trace length on all other traces is 0.5.”
5.4.3 440LX Memory Subsystem Layout and Routing Guidelines
The 440LX integrates a fully configurable main memory DRAM controller that supports a 72-bit memory data interface (64-bit memory data plus 8 ECC bits). The PAC supports Extended Data Out
(EDO) DRAM, and Synchronous DRAM (SDRAM). The PAC generates the Row Address Strobe/Chip
Selects (RCSA# and RCSB#), Column Address Strobe/Data Mask (CDQA# and CDQB#), SCAS#,
SRAS#, CKE, WE#, and Memory Addresses (MA) for the DRAM array. For CPU/PCI/A.G.P.-to-
DRAM cycles the address and data flows through the PAC. The PAC generates data on the MD and
MECC buses for writes and accepts data on these buses during reads. The PAC asserts ECCERR#, if enabled, in the event of a single-bit correctable or multi-bit uncorrectable error. The 440LX DRAM interface operates synchronously to the CPU clock.
Fourteen memory address signals allow the PAC to support a wide variety of DIMMs. Both symmetrical and asymmetrical addressing are supported. Eight RCS# lines permit a maximum of eight
64-bit wide rows of DRAM. For write operations of less than a quad word, the PAC will either perform a byte-wise write (non ECC protected configuration) or a read-modify-write cycle by merging the write data on a byte basis with the previously read data (ECC configurations). The PAC supports 50 ns and
60 ns EDO DRAM and 66-MHz SDRAM with CL2 and CL3. Both single and double-sided DIMMs are supported.
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Possible DRAM and system options supported by the 440LX AGPset include:
DRAM Type:
DRAM Module Type:
DRAM Voltage:
Number of rows of memory:
DRAM Speed:
DRAM Component Width:
Table 5-2. Memory Types Supported by the 440LX
EDO, SDRAM
168-pin DIMM: 64-bit, 72-bit ECC, unbuffered
3.3V
8 rows (Configuration #1), 6 rows (Configuration #2).
50 ns & 60 ns EDO DRAM, 66-MHz SDRAM x4, x8, x16
In the following discussion the term row refers to a set of memory devices that are simultaneously selected by a RCSA&B#/CS# signal. The PAC supports a maximum of 8 rows of memory in configuration #1, or 6 rows in memory configuration #2.
The PAC supports “4-Clock 66-MHz 64/72-bit unbuffered SDRAM DIMM” Specification and the
“60 ns 64-bit 3.3V unbuffered EDO DIMM” specification. Ask your local Intel Field Sales Engineer for these documents.
Populating a 440LX Memory Array:
•
DIMM sockets can be populated in any order. However, to take advantage of potentially faster MA timing, it is recommended to populate sockets in order.
•
SDRAM and EDO DIMMs can be mixed within the memory array.
•
The DRAM Timing register, which provides the DRAM speed grade control for the entire memory array, must be programmed to use the timings of the slowest DRAMs installed.
440LX Memory Array Configurations:
•
Large Memory Array (Configuration #1)
•
512 Megabytes SDRAM/EDO
•
1 Gigabyte Buffered EDO
•
8 Rows
•
Small Memory Array (Configuration #2)
•
384 Megabytes SDRAM/EDO
•
6 Rows
Each memory configuration offers a different set of signals. This memory configuration is selectable upon Boot/RESET by a strapping option on the CKE signal (please refer to the CKE signal description in the Intel 82443LX PAC Data Sheet.
Configuration #1: Enables large memory arrays (up to 8 rows) with two copies of Row Address
Strobe/Chip Selects (RCSAx# & RCSBx#) and an extra copy of the Column Address Strobe/Data Mask
5 & 1, (CDQB[5 & 1]# are the most loaded CAS#/DQM signals when using ECC DIMMs). Four
SRAS#, SCAS# and WE# signals are also provided. This configuration supports Single-Sided and
Double-Sided x8, x16 and x32 DIMMs, and Single-Sided x4 DIMMs.
Configuration #1 interface signals:
In memory configuration #1, a buffered copy of MA[13:2] will go to all 4 DIMM sockets. MAA[1:0] will go to DIMM socket 0 and DIMM socket 1, and MAB[1:0] will go to DIMM socket 2 and DIMM socket 3. CDQA[7:0]# will go to DIMM socket 2 and DIMM socket 3. CDQA[7, 6, 4-2, 0]# will go to
DIMM socket 0 and DIMM socket 1. CDQB[5&1]# will go to DIMM 0 and DIMM 1.
One CKE signal, provided by the PAC, is buffered and connected to each DIMM socket. Use a CMOS buffer to provide copies of the CKE signal. Four copies of the WE# signal are provided by the PAC, and one is connected to each DIMM socket.
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RCSA&B[1:0]#
RCSA&B[3:2]#
RCSA&B[5:4]#
RCSA&B[7:6]#
SRAS0#/SCAS0#
SRAS1#/SCAS1#
SRAS2#/SCAS2#
SRAS3#/SCAS3#
CKE
CDQA[7:0]#
CDQB[5&1]#
MD[63:0]
MECC[7:0]
WE3#
WE2#
WE1#
WE0#
MAA[13:2]
DIMM 0
DIMM 1 DIMM 2 DIMM 3
FCT3245
MAB[1:0]
MAA[1:0]
Figure 5-16. DIMM Sockets (Single or Double Sided, Unbuffered)
Figure 5-16 shows a typical 440LX memory array using Configuration #1. The maximum size of this memory array is 512 MB, using x4 single sided EDO DIMMs or 512 MB using x4 SDRAM. (1G is supported by using 4 double sided buffered EDO DIMMs.)
Copies of RCSA#[7:0], CDQA[5]&[1], and WE# are provided to the most heavily loaded control signals in this array. A buffered copy of MAA[13:2] must go to each DIMM socket. MAA[1:0] and
MAB[1:0] are copies of the first two memory address signals. Copies of these signals are needed to ensure a fast memory read burst rate.
Layout Guidelines: Minimum trace length (from the PAC to the closest DIMM) is 1.0”. Maximum trace length (from the PAC to the furthest DIMM) is 5.0”.
Critical Signals: CDQA[7:0]#: “T” in the middle of the array.
CDQB[5],[1]#: “T” to the last 2 DIMMs.
MD[63:0]: “T” in the middle of the array. MECC[7:0]: “T” in the middle of the array.
Configuration #2: Enables small memory arrays (up to 6 rows) with two copies of Memory Address signals. Three SRAS#, SCAS# and WE# signals are provided to support 3 DS DIMM sockets. This configuration supports Single-Sided and Double-Sided x8 and x16 DIMMs.
Configuration #2 interface signals:
In memory configuration #2, connect MAB[13:0] to the DIMM socket closest to the PAC. Connect
MAA[13:0] to DIMM sockets 1 and 2. No external buffering is needed on the memory control and address signals.
One CKE signal, provided by the PAC, is buffered and connected to each DIMM socket. Use a CMOS buffer to provide copies of the CKE signal. Three copies of the WE# signal are provided by the PAC, and one is connected to each DIMM socket.
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RCSA[1:0]#
RCSA[3:2]#
RCSA[5:4]#
SRAS0#/SCAS0#
SRAS1#/SCAS1#
SRAS2#/SCAS2#
CKE
CDQA[7,6,4:2,0]#
CDQB[5&1]#
CDQA[5&1]#
MECC[7:0]
MD[63:0]
WE2#
WE1#
WE0#
DIMM 0 DIMM 1
DIMM 2
MAB[13:0]
MAA[13:0]
Figure 5-17. DIMM Sockets (Single or Double Sided, Unbuffered)
Figure 5-17 shows a typical 440LX memory array using Configuration #2. Connect MAB[13:0] to the closest DIMM socket to the PAC. Connect MAA[13:0] to DIMM sockets 1 and 2. No external buffering is needed on the memory control and address signals.
Layout Guidelines: Minimum trace length (from the PAC to the closest DIMM) is 1.0.” Maximum trace length (from the PAC to the furthest DIMM) is 5.0”.
Critical Signals: CDQB[5],[1]#: Must be routed to the closest DIMM, with MAB[13:0].
CDQA[7:0]#: Must be “T” between DIMMs #3 and #2.
MD[63:0]: Must be “T” from the middle of the array.
Termination: Series termination is not required for DRAM interface signals in a 440LX memory array.
Adding series termination may cause difficulty in routing to the memory array.
5.4.4 PCI Bus Routing Guidelines
The 440LX provides a PCI Bus interface compliant with the PCI Local Bus Specification 2.1. The implementation is optimized for high-performance data streaming when the PAC is acting as either the target or the initiator of a transaction. For more information on the PAC PCI Bus interface, please refer to the 82443LX PAC Data Sheet.
A 440LX platform PCI Bus design is basically the same as the 440FX PCIset. The 440LX supports
5 PCI Bus masters (excluding the PAC and PIIX4), by the support of 5 REQ# and 5 GNT# lines (4 PCI
Connectors and one on-board PCI Device). Thus a system should only have 4 PCI “add-in” connectors.
Because of the specifics of an ATX layout, see Figure 5-2, it is recommended that the PIIX4 is at the
“END” of the PCI bus, as shown in Figure 5-18. This insures proper “termination” of the PCI Bus signals. This is recommended but not required.
E
MOTHERBOARD LAYOUT AND ROUTING GUIDELINES
440LX
PCI/A.G.P.
Controller
On-board
PCI
Device
PiiX4
324BGA
Figure 5-18. PCI Bus layout guidelines
5.4.5 Decoupling Guidelines for a 440LX Platform
Decoupling capacitors should be placed at the corners of the PAC. 0.1 µF and 0.01 µF are recommended at each corner. The host, A.G.P., PCI and DRAM interface can “break-out” from the BGA package on all four sides.
0.1 µF
0.01 µF
0.1 µF
0.01 µF
440LX
PCI/A.G.P.
Controller
492 BGA
0.1 µF
0.01 µF
0.1 µF
0.01 µF
Figure 5-19. PAC Decoupling
Clock Routing Guidelines
A Pentium II/440LX platform will require a different clock synthesizer for different memory configurations. For a dual processor design with 4 DIMM sockets, the system will require 5 CPU clocks
(2 CPU clocks, A.G.P., PAC, & ITP), 16 SDRAM clocks, and 6 PCI clocks. For a single processor design with 3 DIMM sockets, the system will require 4 CPU clocks (1 clock for the CPU, the AGP subsystem, the PAC, and the ITP), 12 SDRAM clocks, and 6 PCI clocks. The following figure and table indicates the relative skew requirement for each clock. Each skew requirement may require pin to pin
(from the clock synthesizer chip), relative trace length on the motherboard, and the measurement point difference.
5-17
5-18
MOTHERBOARD LAYOUT AND ROUTING GUIDELINES
E
A
Symbol
B
C
D
E
F
Description
Pentium
®
II(HCLK) to
PAC(HCLK) skew
PAC(HCLK) to
A.G.P. skew
PAC(HCLK) to
PCI(PCLK) skew
SDRAM(HCLK) to
PAC(HCLK) skew
PAC(HCLK) to
APIC(PCLK) skew
PCI(PCLK) to
PCI(PCLK) skew
pin to pin
250 ps (max)
-250 ps (min)
250 ps (max)
-250 ps (min)
4.0 ns (max)
1.0 ns (min)
4.0 ns (max)
1.0 ns (min)
500 ps (max)
-500 ps (min)
boards
250 ps (max)
0 ps (min)
250 ps (max)
0 ps (min)
1.5 ns (max)
0 ns (min)
500 ps (max)
0 ps (min)
1.5 ns (max)
0 ns (min)
1.5 ns (max)
-1.5 ns (min)
2.5V - 3.3V
500 ps (max)
-500 ps (min)
500 ps (max)
-500 ps (min)
500 ps (max)
-500 ps (min)
Total
500 ps (max)
-250 ps (min)
500 ps (max)
-250 ps (min)
6.0 ns (max)
0.5 ns (min)
1.2 ns (max)
-0.7 ns (min)
6.0 ns (max)
0.5 ns (min)
2.0 ns (max)
-2.0 ns (min)
PAC
PCI Slot #1
PCI Slot #2
Clock
Device
I/O APIC
Figure 5-20. Clock skew guidelines.
Slot 1 (Processor)
Slot 1 (Processor)
AGP
DIMM Socket
E
Design Checklists
6
