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APPENDIX D
SYSTEM POWER CONTROL
The PIIX4 power management model was designed for use in mobile and desktop systems. Desktop systems are not fully optimized for the PIIX4 power management model. The main concern is circuit control when AC power is lost.
This document will describe a model for desktop power sequencing and an external hardware solution to allow PIIX4 based desktop systems to fit this model.
D.1 Desktop Power Environment
The current desktop power environment can be characterized by the following:
Power is supplied via 110/120V AC line current to a switching power supply. The current standard is the ATX power supply. One of its power outputs consist of a 5V trickle supply at a 10 mA minimum, which is always supplied when AC power is available. A mechanical switch may be optionally used with the power supply to disconnect the power supply from the AC power. Most ATX power supplies do not have this mechanical switch. The main power is a 3.3V supply voltage and other supply voltages controlled by an input signal called “PSON.” If PSON is asserted, these voltages are available from the power supply. If PSON is deasserted, these voltages are not available.
In the case of an ATX power supply with no mechanical switch, all power can be removed from the system in only two ways. The line cord can be removed from the wall or a power outage can occur causing AC power to be lost.
D.2 Desktop Power Sequencing Model
The desktop power sequencing describes how the desktop PC should function as its power is applied and removed from a varying number of scenarios.
The terminology “system context” describes general system context or state. It refers to the state of the operating system, software applications, general hardware registers (processor, chipset and other controllers, peripheral devices, etc.) and other general devices used by the system to perform its intended function. For a system to return to a condition such that the user perceives that the system was never turned off, the system must retain this system state. How this is performed in various power managed modes is described below.
The standard power states of a PC are described here using states potentially available with PIIX4 based systems. These states are:
1. Full On
2. Stop Grant/Sleep
3. Stop Clock/Deep Sleep
4. Suspended—Power on Suspend (POS)
5. Suspended—Suspend to RAM (STR)
6. Suspended—Suspend to Disk (STD)
7. Soft Off (SOFF)
8. Mechanical Off (MOFF)
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D-2
SYSTEM POWER CONTROL
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For purposes of this discussion, the Full On, Stop Grant/Sleep, and Stop Clock/Deep Sleep states will be considered together as On states since typically no power is removed from the system in these states.
Only the CPU clock is stopped in varying degrees. System events or user events can cause the system to return to Full On state with system context unchanged. It appears to the user that the system was always turned on. Latency to resume system is less than 1 ms. The Full On state is identified by the processor executing cycles at full speed. The Stop Grant/Sleep states are characterized by the processor stopping clocks in its internal core to a varying degree. In the Stop Clock/Deep Sleep state, the host clocks are stopped going into the processor.
The POS state maintains system context required for recovery in system registers and main memory.
This state gets its power savings from stopping the high speed system clocks. DRAM refresh is performed with a low speed suspend clock or with self-refreshing DRAMs. No power is typically removed from system board. This state is primarily used in mobile computers. Desktop systems today seldom take advantage of this power savings mode due to additional cost of implementation. System events or user events can cause the system to return to Full On state with system context unchanged. It appears to the user that the system was always turned on with only the monitor screen off. Latency to resume system is approximately 20 ms.
The STR state maintains system context required for recovery in main memory. This state gets it power savings by removing power from all components except for DRAM, circuitry used to perform DRAM refresh and circuitry for monitoring resume events. An ATX power supply main power would not be switched off in this state. This state is primarily used in mobile computers. Desktop systems today seldom take advantage of this power savings mode due to additional cost of implementation. System events or user events can cause the system to return to Full On state with system context unchanged. It appears to the user that the system was always turned on with only the monitor screen off. Latency to resume system is approximately 1 second.
The STD state stores the system context onto a permanent storage device such as IDE hard disk. All power except trickle power can be removed from the system. The trickle power is used by the circuitry monitoring system resume events. When the system is resumed, the system context is restored from the hard disk. From a hardware viewpoint, the STD state is identical to Soft Off. System events or user events can cause the system to return to Full On state with system context unchanged. It appears to the user that the system was off, but returns to the condition it was in when suspended. Latency to resume system is less than 30 seconds.
The Soft Off state saves no system context. All power except trickle power can be removed from the system. The trickle power is used by the circuitry monitoring system resume events. When the system is resumed, it performs a normal startup (OS boot). From a hardware viewpoint, the Soft Off state is identical to the STD state. System events or user events can cause the system to return to Full On state.
It appears to the user that the system was turned completely off and then turned on and booted. Latency to resume system is less than 30 seconds.
The Mechanical Off state may or may not save system context. If the system was in the STD state when it transitions to MOFF state, the system context can be recovered. If in any other state prior to transition to MOFF, all system context will be lost and the system must reboot the OS once power is restored. All power including trickle power is removed from the system. The only power on the system board comes from the RTC battery. This state is reached by the use of a mechanical switch on the power supply, unplugging of the AC wall cord, or from a loss of AC wall power. The system can be resumed only after
AC power has been restored to the power supply. What the desired system functionality is when power is reapplied varies depending on the situation (see below).
The normal system transitions occur from the Full On state into one of the other Power States. This transition is all handled via program control, thus the system cannot transition from one power managed state directly to another (such as from POS to STD). It must transition from Full On to a particular power managed state and from that power managed state back to Full On. The only exception to this rule is the transition to Mechanical Off. This cannot be controlled via program control, since it is characterized by an external event (such as loss of AC wall power or unplugging of the power cord).
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D.3 Recovery from Mechanical Off Condition
SYSTEM POWER CONTROL
One of the primary concerns for desktop systems occurs when a system transitions from Mechanical Off state (i.e. AC power is reapplied to system). There are various scenarios which are desirable dependent on the state of the system prior to going to Mechanical Off. These are described in the following table:
System State before transition to MOFF
1 Full On, Stop Grant,
Stop Clock
2 Full On, Stop Grant,
Stop Clock
3 Power On Suspend
4 Power On Suspend
5 Suspend to RAM
6 Suspend to RAM
7 Suspend to Disk
8 Suspend to Disk
9 Soft Off
System
Context
Lost
Lost
Lost
Lost
Lost
Lost
Maintained
Maintained
No System
Context
System State After
Power Returned
Full On
Soft Off
Full On
Soft Off
Full On
Soft Off
Full On
STD
Soft Off
Miscellaneous
System can then transition into
Stop Grant or Stop Clock if desired. System Boot required.
See Note 1.
System does not power on. User or system event required for transition to Full On. System Boot required.
See Note 2.
System can then transition into
Power On Suspend if desired.
System Boot required.
See Note 1.
System does not power on. User or system event required for transition to Full On. System Boot required.
See Note 2.
System can then transition into
Suspend to RAM if desired.
System Boot required.
See Note 1.
System does not power on. User or system event required for transition to Full On. System Boot required.
See Note 2.
System can then transition into
Suspend to Disk if desired. System
Boot not required.
See Note 1.
System does not power on. User or system event required for transition to Full On. System Boot not required.
See Note 2.
System does not power on. User or system event required for transition to Full On.
NOTES:
1. Used for system which must return to original state after power returns without user intervention. This is required by critical systems at remote sites for which user intervention to return to operation is not available.
2. Used when it is desired to not allow system to restart immediately after power returns. This may be needed at sites with large numbers of computers in order to limit power surge upon restoration of AC power.
A PIIX4 based system without external logic will in all cases above cause the system to restore to a Full
On condition.
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D-4
SYSTEM POWER CONTROL
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D.4 PIIX4 External Logic to handle power loss condition
This section presents an external hardware design which will allow a PIIX4 based system to operate similarly to the previously described model. The primary difference is that instead of placing the system into a true “Soft Off” state, the system will be placed into a “pseudo Off” state which requires the assertion of an active low signal to return to On. We will use the PWRBTN# signal attached to external push button, but any active low signal would be sufficient.
A General Purpose Output (GPO[x]) from PIIX4 is programmed to determine whether the user would like to come back to an ON state or whether the user would like to come back to a pseudo OFF state
(described below as PWR_ON_OVERRIDE state) after restoration of AC power. The state is termed
PWR_ON_OVERRIDE because it externally controls the assertion of the power supply “PSON” signal.
This prevents the power supply from supplying the main or core power to the system board and thus holds the PWROK signal inactive.
The GPO value can be changed at any time by the system BIOS. This allows the BIOS to control this functionality for various system states. The truth table for this is shown below.
Note:
Do not use GPO[14] in this external logic because it defaults to a logical ‘0’ while all other GPO’s default to a logical ‘1.’
GPO=1
(System comes up as on and software may set it back to where it was before power failure)
ON
GPO=0
(System comes up as off and user has to push the button to turn on the system)
Full on,
Stop Grant,
Stop Clock
POS
STR
STD
Soft Off
ON
ON
ON
ON
PWR_ON OVERRIDE
PWR_ON OVERRIDE
PWR_ON OVERRIDE
PWR_ON OVERRIDE
PWR_ON OVERRIDE
The external circuitry is shown below. The PIIX4 GPO signal is connected to the D input of the
74HC74 flip flop. It will be stored into the flip flop when the Power OK signal (PWROK) goes inactive.
This may be during a normal system shutdown or during a power failure. The D flip flop is powered by the V
BAT
power plane, which is supplied by RTC battery when all system power is removed. The
CMOS isolation transistor is used to isolate the flip flop from NAND gate when 5V Standby (5VSB) is not available and serves to eliminate any potential leakage current from the flip flop to the NAND gate when 5VSB power is not available.
The Q output of the flip flop is applied to the NAND gate along with the SUSC# signal from the PIIX4
(shown here as PX4_SUSC#). This controls the PSON# signal to the power supply. When Q=1, the
PX4_SUSC# signal will flow through the NAND gate and directly control the power supply. When
Q=0, the PX4_SUSC# signal will be blocked by the NAND gate (i.e. PSON# held inactive). In order to turn the system on in this case, an external, active low signal needs to be applied to the asynchronous
PRESET (PRE#) input of the flip flop. This then allows the PX4_SUSC# signal to again directly control the power supply.
The logic connected to the flip flop asynchronous CLEAR (CLR#) is used during replacement of RTC battery with all system power removed. The RC delay associated with this circuit forces the Q output to
0 upon reinstallation of the RTC battery. This forces the requirement of asserting the PRE# circuit logic to turn the system back on.
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SYSTEM POWER CONTROL
Figure D-1 differs from the schematic in Appendix H. The functionality is the same, but the implementation is different. Neither Figure D-1 nor the circuit in the schematics support waking from a suspend state. To support suspend wake up, additional logic is needed.
VBAT
5VSB
GPO
PX4_SUSC#
PSON# to
ATX Power Supply
D Q
PWROK
5VSB
74HC74
VBAT
PWRBTN#
VBAT
8.2K
8.2K
CLR#
PRE#
0.1 µf
GPO PWROK
Figure D-1. External Logic to Handle Power Loss
PRE# CLR# Q PSON# Comments
x x
0
1 x x x
Falling
Falling
H
0
1
1
1
1
1
0
1
1
1
1
0
0
1
Qo
1
!PX4_SUSC#
!PX4_SUSC#
1
OFF
ON
ON
OFF
HOLD
OFF = Main power supply is off, but standby (or trickle) current is on.
ON = Main power supply is on. Software then takes over to place the system into the desired sleep or working state.
Note:
In Appendix H a J-K Flip-Flop is used, while here we use a D Flip-Flop. Neither solution will support wake events other than the power button. To support additional wake events, other logic would be needed.
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System Management
Bus (SMBus)
Overview
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