Embedded Peripherals IP User Guide

UG-01085

2016.12.19

Table 41-1: Mailbox Register Map

Word Address Offset

0x0

0x1

0x2

0x3

Register/ Queue Name

Command register

Pointer register

Status register

Interrupt Masking register

Command Register

Attribute

R/W for sender, RO for receiver

R/W for sender, RO for receiver

RO

Read (R) for both sender and receiver.

Sender can only write to Message Space

Interrupt Mask bit, Receiver can only write to Message Pending Interrupt bit.

41-3

Command Register

The Command register is a 32-bit register which contains a user defined command to be passed between processors. This register is read-writeable via Avalon-MM Slave (sender). However it is only readable by the Avalon-MM Slave (receiver) interface.

Pointer Register

Instead of passing huge data via the Mailbox, a Pointer register is introduced. The Pointer register contains the 32-bit address to the payload of the message. A payload could be the raw data to be passed to the receiving processor for further processing. However, a message could contain zero payload or data for processing. A write to the Pointer may not be necessary for a message passing.

This register is read-writeable via Avalon-MM Slave (sender). However it is only readable by Avalon-MM

Slave (receiver) interface.

Status Register

The Status register presents the full or empty status of the Mailbox. As the Mailbox can only contain one message at a time, the full bit status also indicates if there is message pending in the Mailbox. This register is read only by both Avalon-MM Slave interfaces.

Table 41-2: status Register Field

31 ...

...

...

Reserved

...

Bit Fields

...

2 1

Mailbox full

0

Message pending

Table 41-3: Mailbox status Register Descriptions

Filed Name

Message pending

Description

Value ‘0’ indicates the Mailbox has no message. Value ‘1’ indicates the Mailbox has message pending for retrieval.

Reset Value

0

Altera Avalon Mailbox (simple) Core

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