Code generation Pragmas. NXP CodeWarrior Development Studio
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Code generation Pragmas
NOTE
The #pragma pop does not restore any changes to the access permissions of sections that exist before or after the corresponding #pragma push.
36.4 Code generation Pragmas
This section describes the code generation pragmas.
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Chapter 36 Pragmas for Power Architecture Compiler
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z4_16bit_cond_branch_errata_5116
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36.4.1 alignment_metrowerks
Determines which structure alignment policy to use.
Syntax
#pragma alignment_metrowerks on | off | reset
Remarks
This pragmas specifies which policy that
#pragma options align=power
will use for aligning data in structures. When this pragma is on, then the directive
#pragma options align=power
is equivalent to this directive
#pragma options align=power_mw
When this pragma is off, then the directive
#pragma options align=power
is equivalent to this directive
#pragma options align=power_gcc
36.4.2 altivec_codegen
Controls the use Power Architecture AltiVec™ instructions during optimization.
Syntax
#pragma altivec_codegen on | off | reset
Remarks
If this pragma is on
, the compiler uses Power Architecture AltiVec instructions, if possible, during optimization. When this pragma is off
, the pragma altivec_model
is also set to off
.
36.4.3 altivec_model
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Controls the use Power Architecture AltiVec™ language extensions.
Syntax
#pragma altivec_model on | off | reset
Remarks
If you enable this pragma, the compiler allows language extensions to take advantage of the AltiVec instructions available on some Power Architecture processors. When this pragma is on
the compiler sets
#pragma altivec_codegen
to on
and defines the
__VEC__ preprocessor directive.
36.4.4 altivec_pim_warnings
Controls how the compiler translates literal values for AltiVec vectors.
Syntax
#pragma altivec_pim_warnings on | off | reset
Remarks
When this pragma is on
, the compiler follows the syntax rules described in AltiVec™
Technology Programming Interface Manual
("PIM") to specify literal values for vector objects. This syntax specifies these requirements:
• vector values must be enclosed in parentheses
• vector values must be preceded by a type specifier
When this pragma is off
, the compiler expects a style more consistent with C source code conventions:
• vector values must be enclosed in braces
• vector values do not need to be preceded by a type specifier
shows an example.
Listing 36-1. Example of using altivec_pim_warnings
#pragma altivec_pim_warnings on vector signed int vsi1 = (__vector signed int)(1, 2, 3, 4);
#pragma altivec_pim_warnings off vector signed int vsi2 = {1, 2, 3, 4};
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36.4.5 altivec_vrsave
Controls which AltiVec™ registers to save to the stack between function calls.
Syntax
#pragma altivec_vrsave on | off | reset | allon
Parameter
allon
Tells the compiler to set all bits in the
VRSAVE
register.
Remarks
When generating instructions to call a function, the compiler uses the
VRSAVE
register's contents to determine which AltiVec registers should be saved to and restored from the stack.
When this pragma is on
, the compiler determines which AltiVec registers a function uses.
It generates instructions to record this information in the
VRSAVE
register.
When this pragma is off
, the compiler clears the
VRSAVE
register and consequently does not save AltiVec registers on the stack.
When this pragma is set to allon
, the compiler sets the
VRSAVE
register to specify that all
AltiVec registers should be saved and restored on the stack.
36.4.6 cats
Controls the generation of relative
.rela.*
sections in the
.elf file
Syntax
#pragma cats on | off | reset
Remarks
The default for this pragma is off
for Freescale Power Architecture processors.
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NOTE
Standard libraries should be rebuild using
#pragma cats off
in order to get rid of all
.rela.*
symbols in the internal_FLASH.elf
file.
36.4.7 disable_registers
Controls compatibility for the ISO/IEC standard library function setjmp()
.
Syntax
#pragma disable_registers on | off | reset
Remarks
If this pragma is on
, the compiler disables certain optimizations for any function that calls setjmp()
. It also disables global optimization and does not store local variables and arguments in registers. These changes ensure that all local variables have correct values when the setjmp()
function saves the processor state.
Use this pragma only if you are porting code that relies on this feature because it makes your program much larger and slower. In new code, declare a variable to be volatile
if you expect its value to persist across setjmp() calls.
36.4.8 e500_floatingpoint
Generates single-precision floating point instructions for the Power Architecture e500
SPE (Signal Processing Unit) APU (Auxiliary Processing Unit).
Syntax
#pragma e500_floatingpoint on | off | reset
36.4.9 e500v2_floatingpoint
Generates double-precision floating point instructions for the Power Architecture e500v2
SPE (Signal Processing Unit) APU (Auxiliary Processing Unit).
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Syntax
#pragma e500v2_floatingpoint on | off | reset
36.4.10 function_align
Aligns the executable object code of functions on a specified byte boundary.
Syntax
#pragma function_align 4 | 8 | 16 | 32 | 64 | 128 | reset
36.4.11 gen_fsel
Controls the use of the floating-point select instruction, fsel
.
Syntax
#pragma gen_fsel on | off |
number | always where number is a value from 1 to 255.
Remarks
The compiler uses this pragma to determine how often it generates the fsel
instruction.
The number argument specifies how aggressively the compiler should use this instruction, 1 is equivalent to "rarely" and 255 is equivalent to always
. The on
choice is equivalent to a value of 10.
36.4.12 gen_isel
Controls the use of the integer select instruction, isel
.
Syntax
#pragma gen_isel on | off |
number | always
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where number is a value from 1 to 255.
Remarks
The compiler uses this pragma to determine how often it generates the isel
instruction.
The number argument specifies how aggressively the compiler should use this instruction, 1 is equivalent to "rarely" and 255 is equivalent to always
. The on
choice is equivalent to a value of 10.
36.4.13 gprfloatcopy
Takes advantage of simpler alignment restrictions for copying floating point data.
Syntax
#pragma gprfloatcopy on | off | reset
Remarks
When this pragma is on
, the compiler uses integer load and store instructions for memory-to-memory assignments for objects of type double
and float
, which improves the speed of memory-to-memory assignments of unaligned floating-point data. When this pragma is off
, the compiler issues floating-point load and store instructions instead.
36.4.14 has8bytebitfields
Controls the use of bitfields that fit in the long long
data type.
Syntax
#pragma has8bytebitfields on | off | reset
Remarks
When this pragma is on
, the compiler allows bitfields in the long long
data type. Such bitfields may occupy up to 64 bits (8 bytes). When this pragma is off
, the compiler allows bitfields only in integer types of the same size or smaller than the long
type.
Listing 36-2. Example for pragma has8bytebitfields
#pragma has8bytebitfields on struct X {
long long fielda : 12;
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long long fieldb : 18;
long long fieldc : 32;
long long fieldd : 2;
};
36.4.15 interrupt
Deprecated. To avoid C++ parsing ambiguities and other possible inadvertent errors, use
__declspec(interrupt)
instead.
36.4.16 legacy_struct_alignment
Avoids the possibility of misaligned load or store instructions caused by promoting the alignment of global and local data objects to a minimum of 4 bytes.
Syntax
#pragma legacy_struct_alignment on | off | reset
Remarks
The default for this pragma is off
for Freescale Power Architecture processors as the big endian systems do not crash and misalignment is rare.
36.4.17 merge_float_consts
Each floating point constant is placed in a unique variable such that the linker will merge floating point constants which have the same value. (The variable names are not legal C/
C++ and are not accessible by the user). This option works with either small data in TOC on or off. This option minimizes TOC entry usage for programs which frequently use the same floating point constant in many different source files.
Syntax
#pragma merge_float_consts on|off
Remarks
The default for this pragma is off
for Freescale Power Architecture processors.
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36.4.18 min_struct_align
Increases aggregate alignments for better memory access.
Syntax
#pragma min_struct_align 4 | 8 | 16 | 32 | 64 | 128 | on | off
| reset
Remarks
When this pragma is off
, the compiler aligns objects to their regular alignments. The default alignment is 4.
NOTE
This pragma only applies if the optimization level is greater than 0.
36.4.19 misaligned_mem_access
Controls how the compiler copies structures that are not aligned to 4-byte boundaries.
Syntax
#pragma misaligned_mem_access on | off | reset
Remarks
When this pragma is on
, the compiler uses 4-byte load and store instructions to copy structures that are not aligned to 4-byte boundaries. By using these misaligned load and store instructions, the compiler improves runtime performance and reduces code size.
When this pragma is off
, the compiler uses 1-, 2-, and 4-byte load and store instructions to copy structures that are aligned on corresponding boundaries.
However, misaligned load and store instructions on some Power Architecture processors give poor performance or even generate processor exceptions. For these processors, turn this pragma off. Desktop variants of the Power Architecture processor family do not have this limitation.
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Consult the processor manufacturer's documentation for information on the processor's behavior when loading and storing 4-byte values that are not aligned to 4-byte boundaries.
The default for this pragma is on
for processors that allow misaligned memory access.
The default is off
for processors that have limited misaligned memory access performance or generate an exception.
36.4.20 no_register_save_helpers
Controls the save and restore registers without calling helper functions
Syntax
#pragma no_register_save_helpers on | off | reset
36.4.21 options
Specifies how to align structure and class data.
Syntax
#pragma options align=
alignment
Parameter
alignment
Specifies the boundary on which structure and class data is aligned in memory. Values for alignment range from 1 to 16, or use one of the following preset values: mac68k mac68k4byte power
Table 36-1. Structs and Classes Alignment
If alignment is ...
The compiler ...
Aligns every field on a 2-byte boundaries, unless a field is only 1 byte long. This is the standard alignment for 68K Mac
OS alignment.
Aligns every field on 4-byte boundaries.
Aligns every field on its natural boundary. For example, it aligns a character on a 1-byte boundary and a 16-bit integer on a 2-byte boundary. The compiler applies this alignment
Table continues on the next page...
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Table 36-1. Structs and Classes Alignment (continued)
native packed reset
If alignment is ...
The compiler ...
recursively to structured data and arrays containing structured data. So, for example, it aligns an array of structured types containing an 4-byte floating point member on an 4-byte boundary.
Aligns every field using the standard alignment.
Aligns every field on a 1-byte boundary. It is not available in any panel. This alignment causes your code to crash or run slowly on many platforms. Use it with caution.
Resets to the value in the previous #pragmaoptionsalign statement.
NOTE
There is a space between options
and align
.
36.4.22 pool_data
Controls whether data larger than the small data threshold is grouped into a single data structure.
Syntax
#pragma pool_data on | off | reset
Remarks
When this pragma is on
the compiler optimizes pooled data. You must use this pragma before the function to which you apply it.
NOTE
Even if this pragma is on
, the compiler will only pool the data if there is a performance improvement.
This pragma corresponds to the CodeWarrior IDE's Pool Data setting in the PowerPC
ProcessorProperties > C/C++ Build > Settings > Tool Settings > PowerPC Compiler
> Processor panel.
36.4.23 ppc_lvxl_stvxl_errata
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Controls the instruction encoding for the lvxl
and stvxl
instructions on the Power
Architecture 745 x processors to correct a bug in the processors.
Syntax
#pragma ppc_lvxl_stvxl_errata on | off | reset
36.4.24 profile
Controls the generation of extra object code for use with the CodeWarrior profiler.
Syntax
#pragma profile on | off | reset
Remarks
If you enable this pragma, the compiler generates code for each function that lets the
CodeWarrior Profiler collect information on it.
This pragma corresponds to the CodeWarrior IDE's Profiler Information setting in the
PPC ProcessorProperties > C/C++ Build > Settings > Tool Settings > PowerPC
Compiler > Processor panel.
36.4.25 read_only_switch_tables
Controls where tables for switch
statements are placed in object code.
Syntax
#pragma read_only_switch_tables on | off | reset
Remarks
This option specifies where the compiler places executable code addresses for switch statements. When this option is on
, the compiler places these tables in a read-only section
(
.rodata
), allowing the linker to place this object code in a ROM area instead of RAM.
When this option is off
, the compiler places these switch
tables in an object code section that is readable and writable (
.data
). Putting these tables in a read/write section allows relocation at runtime. The System V ABI, SuSE, YellowDog, and SDA PIC/PID application binary interfaces (ABIs) allow relocatable object code at runtime.
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36.4.26 strict_ieee_fp
Controls generation of executable code that conforms to the IEEE floating point standard.
Syntax
#pragma strict_ieee_fp on | off | reset
Remarks
Disabling this option may improve performance but may change the results generated.
• Use Fused Mult-Add/Sub
Uses a single instruction to do a multiply accumulate. This runs faster and generates slightly more accurate results than specified by IEEE, as it has an extra rounding bit between the multiply and the add/subtract).
• Generate fsel
instruction
The fsel
instruction is not accurate for denormalized numbers, and may have issues related to unordered compares, but generally runs faster.
• Assume Ordered Compares
Ignore the unordered issues when comparing floating point which allows converting:
if (a <= b) into
if (!(a > b))
36.4.27 read_only_vtable_RTTI
Controls placing vtable and RTTI in a ready-only section.
Syntax
#pragma read_only_vtable_RTTI on | off | reset
Remarks
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If you enable this pragma, compiler places vtable
and
RTTI
in a read-only section
(
.rodata/.sdata2
), allowing the linker to place this object code in a ROM area instead of
RAM. If you disable this pragma, the compiler places vtable
and
RTTI
in an object code section that is readable and writable (
.data/.sdata
).
This pragma does not correspond to any panel setting. By default, this pragma is disabled.
36.4.28 switch_tables
Controls the generation of switch tables.
Syntax
#pragma switch_tables on | off | reset
Remarks
When on
, the compiler translates switch
statements into tables of addresses where each address in the list corresponds to a case
statement. Using tables improves the performance of switch
statements but may increase the size of the executable code if there are many case
statements or if the case
label values are not contiguous.
When off
, the compiler translates switch
statements into a series of comparisons, one comparison for each case
statement.
36.4.29 uchar_bool
Controls the size of the
_Bool
and bool
data types.
Syntax
#pragma uchar_bool on | off | reset
Remarks
When on
, the compiler translates the
_Bool
data type in C99 (ISO/IEC 9899-1999) source code and the bool
data type in C++ source code to 8 bit values. When off
, these data types are 32 bits. Use this pragma only before any declarations.
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When this pragma is off (boolean values are 32-bits), use bitfields to ensure that a
boolean value is 8 bits. Listing 36-3 on page 548
shows an example.
Listing 36-3. Example of overriding uchar_bool in a structure in C++
#pragma uchar_bool off /* Boolean values are 32 bits */ typedef struct
{
bool sockclean:8 /* This value will only occupy 8 bits. */
} sockrec;
36.4.30 use_lmw_stmw
Controls the use of lmw
and stmw
instructions.
Syntax
#pragma use_lmw_stmw on | off | reset
Remarks
Use of lmw
and stmw
may be slower on some processors.
36.4.31 ushort_wchar_t
Controls the size of wchar_t
.
Syntax
#pragma ushort_wchar_t on | off | reset
Remarks
When this pragma is on
, wchar_t
changes from 4-bytes to 2-bytes.
36.4.32 vec2x32float_align_4
Controls the alignment of type
__vec2x32float__
.
Syntax
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#pragma vec2x32float_align_4 on | off | reset
Remarks
When the pragma is on
, type
__vec2x32float__
is aligned on
4byte
boundary.
The default value for this pragma is off
.
36.4.33 z4_16bit_cond_branch_errata_5116
Controls the use of
16-bit
conditional instructions.
Syntax
#pragma z4_16bit_cond_branch_errata_5116 on | off | reset
Remarks
When the pragma is on
,
32-bit
conditional instructions are used instead of
16-bit
.
The default value for this pragma is off
.
36.4.34 z4_mtlr_se_rfi_errata_26553
Ensures that there are at least three instructions between the mtlr
and the se_rfi
.
Syntax
#pragma z4_mtlr_se_rfi_errata_26553 on | off | reset
Remarks
When the pragma is on
and you are using either
__declspec(interrupt)
or
#pragma interrupt
, the compiler ensures that there are at least three instructions between the mtlr
and the se_rfi
.
If your interrupt handler is written in function level assembler, compiler support only happens if you do not use the nofralloc
directive. Standalone assembler does not include this support.
The default value for this pragma is off
.
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