NI NAT7210 Reference
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Pages: 254 NI NAT7210 Reference User manual
Brand: NI Category: Networking Size: 580 KB
Languages: English
Table of contents
- 1 NAT7210 Reference Manual
- 3 Limited Warranty
- 4 Copyright
- 4 Trademarks
- 4 WARNING REGARDING MEDICAL AND CLINICAL USE OF NATIONAL INSTRUMENTS PRODUCTS
- 5 Contents
- 13 About This Manual
- 13 Organization of This Manual
- 14 Conventions Used in This Manual
- 14 Related Documentation
- 15 Customer Communication
- 16 Chapter 1 Introduction and General Description
- 16 IEEE 488 Capabilities
- 18 CPU Interface Capabilities
- 19 Typical System Interface
- 20 Chapter 2 NAT7210 Architecture
- 22 NAT7210 Modes
- 22 Changing the NAT7210 Mode
- 23 Chapter 3 7210-Mode Interface Registers
- 23 7210 Register Map
- 25 The Page-In State
- 25 How to Page-In
- 25 Hidden Registers
- 25 Address Register Map
- 26 Auxiliary Mode Register Map
- 26 Register Bit Descriptions
- 27 Address Mode Register (ADMR)
- 30 Address Register (ADR)
- 31 Address Register 0 (ADR0)
- 32 Address Register 1 (ADR1)
- 33 Address Status Register (ADSR)
- 36 Auxiliary Mode Register (AUXMR)
- 49 Auxiliary Register A (AUXRA)
- 51 Auxiliary Register B (AUXRB)
- 53 Auxiliary Register E (AUXRE)
- 54 Auxiliary Register F (AUXRF)
- 55 Auxiliary Register G (AUXRG)
- 57 Auxiliary Register I (AUXRI)
- 59 Bus Control Register (BCR)/Bus Status Register (BSR)
- 61 Command/Data Out Register (CDOR)
- 62 Command Pass Through Register (CPTR)
- 63 Data In Register (DIR)
- 64 End-of-String Register (EOSR)
- 65 Internal Count Register (ICR)
- 66 Internal Count Register 2 (ICR2)
- 67 Interrupt Mask Register 0 (IMR0)
- 67 Interrupt Status Register 0 (ISR0)
- 71 Interrupt Mask Register 1 (IMR1)
- 71 Interrupt Status Register 1 (ISR1)
- 76 Interrupt Mask Register 2 (IMR2)
- 76 Interrupt Status Register 2 (ISR2)
- 80 Parallel Poll Register (PPR)
- 82 Source/Acceptor Status Register (SASR)
- 84 Serial Poll Mode Register (SPMR)
- 84 Serial Poll Status Register (SPSR)
- 86 Version Status Register (VSR)
- 87 Chapter 4 9914-Mode Interface Registers
- 87 9914 Register Map
- 89 The Page-In Condition
- 89 Hidden Registers
- 89 Accessory Read Register Map
- 90 Register Bit Descriptions
- 91 Accessory Register A (ACCRA)
- 92 Accessory Register B (ACCRB)
- 94 Accessory Register E (ACCRE)
- 95 Accessory Register F (ACCRF)
- 96 Accessory Register I (ACCRI)
- 97 Address Register (ADR)
- 98 Address Status Register (ADSR)
- 101 Auxiliary Command Register (AUXCR)
- 114 Bus Control Register (BCR)/Bus Status Register (BSR)
- 116 Command/Data Out Register (CDOR)
- 117 Command Pass Through Register (CPTR)
- 118 Data In Register (DIR)
- 119 End-of-String Register (EOSR)
- 120 Internal Count Register (ICR)
- 121 Interrupt Mask Register 0 (IMR0)
- 121 Interrupt Status Register 0 (ISR0)
- 125 Interrupt Mask Register 1 (IMR1)
- 125 Interrupt Status Register 1 (ISR1)
- 130 Interrupt Mask Register 2 (IMR2)
- 130 Interrupt Status Register 2 (ISR2)
- 134 Parallel Poll Register (PPR)
- 135 Serial Poll Mode Register (SPMR)
- 135 Serial Poll Status Register (SPSR)
- 137 Chapter 5 Software Considerations
- 137 Chip Initialization Sequence
- 137 1. Place the NAT7210 in 7210 Mode
- 137 2. Make Sure the Local pon Message Is Asserted
- 137 3. Set the Clock Frequency
- 138 4. Configure the Chip for GPIB Operation
- 138 A. Set the GPIB Address(es)
- 138 B. Write the Initial Serial Poll Response
- 138 C. Configure Initial Parallel Response
- 138 D. Set GPIB Handshake Parameters
- 138 5. Enable Interrupts
- 139 6. Clear the Local pon Message
- 139 GPIB Talker or Listener Considerations
- 139 GPIB Addressing
- 139 Logical and Physical Devices
- 139 Normal and Extended Addressing
- 139 Implementing One Logical Device: Normal Addressing
- 140 Implementing One Logical Device: Extended Addressing
- 140 Implementing Two Logical Devices: Normal Addressing
- 141 Implementing Two Logical Devices: Extended Addressing
- 141 Implementing Three or More Logical Devices: Normal Addressing
- 142 Implementing Three or More Logical Devices: Extended Addressing
- 143 Programmed Implementation of a Talker and Listener
- 143 Detecting a GPIB Listener
- 143 Sending GPIB Data Messages
- 143 Basic Flow
- 144 Sending EOI or EOS
- 144 Using DMA
- 144 T1 Delay Generation
- 144 The T1 Delay
- 145 HSTS Definition
- 145 IEEE 488.1 Standard Requirements
- 146 T1 Delay: 7210 Mode
- 146 T1 Delay: 9914 Mode
- 147 Using nbaf
- 147 Receiving GPIB Data Messages
- 147 Basic Flow
- 147 Receiving END or EOS
- 148 Performing an RFD Holdoff on the Last Data Byte
- 148 Using DMA
- 148 Acceptor Handshake Holdoffs
- 148 The GPIB rdy Message and RFD Holdoffs
- 149 Generating the rdy Message
- 149 Immediate RFD Holdoff
- 149 Data-Receiving Modes
- 150 Choosing a Data-Receiving Mode
- 150 DAC Holdoffs
- 151 Determining When DAC Holdoffs Occur
- 151 Device Status Reporting (Polling)
- 151 Requesting Service
- 151 Asserting the SRQ Signal
- 152 IEEE 488.2 Service Requesting
- 152 7210-Style Service Requesting
- 152 Responding to Serial Polls
- 153 Responding to Parallel Polls
- 153 The ist Message
- 153 Remote Configuration
- 153 Local Configuration
- 154 Disabling the Parallel Poll Response
- 154 Generating Hardware Interrupts
- 154 Remote/Local State Considerations
- 155 Device Triggering
- 155 Device Clearing
- 156 Chapter 6 Controller Software Considerations
- 156 System Controller Considerations
- 156 Becoming System Controller
- 157 Other System Controller Capabilities: Setting and Clearing REN
- 157 Disabling System Controller Capabilities
- 157 GPIB Controller Considerations
- 157 Three Basic Controller States
- 157 Idle Controller State
- 158 Active Controller State
- 158 Standby Controller State
- 158 Determining the Basic Controller State
- 158 Changing Controller States
- 158 Idle State to Active State: Becoming CIC
- 159 Active State to Standby State
- 159 Standby State to Active State
- 160 Active State to Idle State: Passing Control
- 160 Sending Remote Multiline Messages (Commands)
- 160 Polling: Obtaining Status from Devices
- 161 Conducting Serial Polls
- 161 Configuring Devices for Parallel Polls
- 162 Conducting Parallel Polls
- 163 Chapter 7 Hardware Considerations
- 163 Pin Descriptions
- 163 GPIB Transceiver Controls
- 163 T/R1
- 163 T/R2 and T/R3
- 164 GPIB Signal Pins
- 165 GPIB Data Bus Pins
- 165 CPU Register Control Pins
- 165 CS* and the CPU Address Bus
- 165 RD*/WR*
- 165 CPU Data Bus
- 165 DMA Pins
- 165 DRQ
- 166 DACK*
- 166 Other Pins
- 166 INT
- 166 RESET
- 167 CLK
- 168 Interfacing to Common GPIB Transceivers
- 169 Appendix A Common Questions
- 171 Appendix B Introduction to the GPIB
- 171 History of the GPIB
- 172 The IEEE 488.1 Specification
- 172 IEEE 488.2 and SCPI Specifications
- 172 Problems with IEEE 488.1 Compatible Devices
- 172 The IEEE 488.2 Solution
- 173 SCPI Specification
- 174 GPIB Hardware Configuration
- 177 GPIB Signals and Lines
- 177 Data Lines
- 178 Interface Management Lines
- 178 Interface Clear (IFC)
- 179 Attention (ATN)
- 180 Remote Enable (REN)
- 180 End-or-Identify (EOI)
- 181 Service Request (SRQ)
- 181 Handshake Lines
- 181 Not Ready For Data (NRFD)
- 182 Not Data Accepted (NDAC)
- 182 Data Valid (DAV)
- 183 Three-Wire Handshake Process
- 183 Physical and Electrical Specifications
- 184 Controllers, Talkers, and Listeners
- 184 Controllers
- 185 Talkers and Listeners
- 187 Data and Command Messages
- 187 GPIB Addressing Protocol
- 189 Reading the Multiline Interface Command Messages Table
- 189 Secondary Addressing
- 189 Unaddressing Command Messages
- 189 Termination Methods
- 190 EOS Method
- 190 EOI Method
- 190 Count Method
- 191 Combinations of Termination Methods
- 191 Serial Polling
- 191 Servicing SRQs
- 191 Serial Polling Devices
- 193 Status Byte Model for IEEE 488.1
- 193 ESR and SRE Registers
- 193 Status Byte Model for IEEE 488.2
- 195 Parallel Polling
- 195 Overview of Parallel Polls
- 196 Determining the Value of the PPR Message
- 196 Configuring a Device for Parallel Polls
- 197 Determining the PPE Message
- 197 Physical Representation of the PPR Message
- 198 Clearing and Triggering Devices
- 199 Appendix C Standard Commands for Programmable Instruments (SCPI)
- 200 IEEE 488.2 Common Commands Required by SCPI
- 201 SCPI Required Commands
- 201 SCPI Optional Commands
- 202 Programming with SCPI
- 203 Constructing SCPI Commands by Using the Hierarchical Command Structure
- 205 Parsing SCPI Commands
- 206 Appendix D Multiline Interface Command Messages
- 209 Appendix E Mnemonics Key
- 220 Appendix F Customer Communication
- 225 Glossary
- 226 Index
- 11 Figures
- 19 Figure 1-1. NAT7210 Implementation Block Diagram
- 21 Figure 2-1. NAT7210 Block Diagram
- 22 Figure 2-2. Changing the NAT7210 Mode
- 60 Figure 3-1. GPIB I/O Hardware Configuration
- 115 Figure 4-1. GPIB I/O Hardware Configuration
- 157 Figure 6-1. Basic Controller States
- 167 Figure 7-1. CLK Signal Timing Diagram
- 168 Figure 7-2. Interfacing the NAT7210 to the 75160 and 75162 Transceivers
- 173 Figure B-1. Structure of the GPIB Standards
- 175 Figure B-2. Linear Configuration
- 176 Figure B-3. Star Configuration
- 177 Figure B-4. GPIB Connector and Pin Assignments
- 182 Figure B-5. Three-Wire Handshake Process
- 186 Figure B-6. System Setup Example
- 192 Figure B-7. Events During a Serial Poll
- 194 Figure B-8. IEEE 488.2 Standard Status Structures
- 195 Figure B-9. Example Exchange of Messages During a Parallel Poll
- 202 Figure C-1. Partial Command Categories
- 202 Figure C-2. Simple Command Tree for the SENSe Command Subsystem
- 203 Figure C-3. Partial Command Tree for the SENSe Command Subsystem
- 204 Figure C-4. Partial Command Tree for the SOURce Command Subsystem
- 204 Figure C-5. Partial Command Tree for the TRIGger Command Subsystem
- 12 Tables
- 16 Table 1-1. NAT7210 IEEE 488 Interface Capabilities
- 24 Table 3-1. 7210-Mode Register Map
- 25 Table 3-2. Hidden Registers at Offset 6 (ADR)
- 26 Table 3-3. Hidden Registers at Offset 5 (AUXMR)
- 27 Table 3-4. Valid ADMR Patterns
- 37 Table 3-5. Auxiliary Command Summary
- 40 Table 3-6. Auxiliary Command Description
- 58 Table 3-7. Clear Conditions for SISB Bit
- 88 Table 4-1. 9914-Mode Interface Registers
- 89 Table 4-2. Hidden Registers at the ACCR Offset
- 101 Table 4-3. Auxiliary Command Summary
- 104 Table 4-4. Auxiliary Command Description
- 145 Table 5-1. IEEE 488.1 Minimum T1 Delay Requirements
- 146 Table 5-2. T1 Delay Settings in 7210 Mode
- 146 Table 5-3. T1 Delay Settings in 9914 Mode
- 154 Table 5-4. Parallel Poll Register Example
- 158 Table 6-1. Basic Controller State
- 193 Table B-1. IEEE 488.1 Standard Status Data Structure
- 196 Table B-2. PPR Message Value
- 197 Table B-3. Determining the PPE Message
- 200 Table C-1. IEEE 488.2 Common Commands Required by SCPI
- 201 Table C-2. SCPI Required Commands
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