STMicroelectronics STM32L010F4
Manuals and User Guides for STMicroelectronics STM32L010F4. We found 2 manuals for free downloads Reference manual, Data Sheet
STMicroelectronics STM32L010F4 is an advanced Arm®-based 32-bit MCU with ultra-low-power consumption. It is part of the STM32L0x0 line of microcontrollers, which offer a range of memory sizes, packages, and peripherals. The STM32L010F4 is ideal for applications that require low power consumption, high performance, and a wide range of features.
Key Features
Ultra-low-power consumption
Arm®-based 32-bit Cortex®-M0+ core
Up to 32KB of Flash memory
Up to 6KB of SRAM
Wide range of peripherals, including Timers, GPIOs, I2C, SPI, and USART
Flexible power management options
Compact package size
Pages: 784 STMicroelectronics STM32L010F4 Reference manual
Brand: STMicroelectronics Category: Processors Size: 8 MB
Languages: English
Table of contents
- 33 Documentation conventions
- 33 General information
- 33 List of abbreviations for registers
- 34 Glossary
- 34 Availability of peripherals
- 34 Product category definition
- 37 System and memory overview
- 37 System architecture
- 38 S0: Cortex®-bus
- 38 S1: DMA-bus
- 38 BusMatrix
- 39 Memory organization
- 39 Introduction
- 40 Memory map and register boundary addresses
- 43 Embedded SRAM
- 44 Boot configuration
- 46 Flash program memory and data EEPROM (FLASH)
- 46 Introduction
- 46 NVM main features
- 46 NVM functional description
- 46 NVM organization
- 50 Reading the NVM
- 58 Writing/erasing the NVM
- 72 Memory protection
- 73 RDP (Read Out Protection)
- 74 PcROP (Proprietary Code Read-Out Protection)
- 76 Protections against unwanted write/erase operations
- 77 Write/erase protection management
- 78 Protection errors
- 78 NVM interrupts
- 79 Hard fault
- 79 Memory interface management
- 79 Operation priority and evolution
- 80 Sequence of operations
- 81 Change the number of wait states while reading
- 81 Power-down
- 82 Flash register description
- 83 Access control register (FLASH_ACR)
- 84 Program and erase control register (FLASH_PECR)
- 87 Power-down key register (FLASH_PDKEYR)
- 87 PECR unlock key register (FLASH_PEKEYR)
- 87 Program and erase key register (FLASH_PRGKEYR)
- 88 Option bytes unlock key register (FLASH_OPTKEYR)
- 89 Status register (FLASH_SR)
- 91 Option bytes register (FLASH_OPTR)
- 93 Write protection register 1 (FLASH_WRPROT1)
- 94 Write protection register 2 (FLASH_WRPROT2)
- 95 Flash register map
- 96 Option bytes
- 96 Option bytes description
- 97 Mismatch when loading protection flags
- 97 Reloading Option bytes by software
- 98 Cyclic redundancy check calculation unit (CRC)
- 98 Introduction
- 98 CRC main features
- 99 CRC functional description
- 99 CRC block diagram
- 99 CRC internal signals
- 99 CRC operation
- 101 CRC registers
- 101 CRC data register (CRC_DR)
- 101 CRC independent data register (CRC_IDR)
- 102 CRC control register (CRC_CR)
- 103 CRC initial value (CRC_INIT)
- 103 CRC polynomial (CRC_POL)
- 104 CRC register map
- 105 Firewall (FW)
- 105 Introduction
- 105 Firewall main features
- 106 Firewall functional description
- 106 Firewall AMBA bus snoop
- 106 Functional requirements
- 107 Firewall segments
- 108 Segment accesses and properties
- 109 Firewall initialization
- 110 Firewall states
- 112 Firewall registers
- 112 Code segment start address (FW_CSSA)
- 112 Code segment length (FW_CSL)
- 113 Non-volatile data segment start address (FW_NVDSSA)
- 113 Non-volatile data segment length (FW_NVDSL)
- 114 Volatile data segment start address (FW_VDSSA)
- 114 Volatile data segment length (FW_VDSL)
- 115 Configuration register (FW_CR)
- 116 Firewall register map
- 117 Power control (PWR)
- 117 Power supplies
- 118 Independent A/D converter supply
- 118 RTC and RTC backup registers
- 118 Voltage regulator
- 119 Dynamic voltage scaling management
- 120 Dynamic voltage scaling configuration
- 120 VCORE range
- 121 Power supply supervisor
- 122 Power-on reset (POR)/power-down reset (PDR)
- 123 Brownout reset (BOR)
- 124 Internal voltage reference (VREFINT)
- 125 Low-power modes
- 126 Behavior of clocks in low-power modes
- 127 Slowing down system clocks
- 127 Peripheral clock gating
- 127 Low-power run mode (LP run)
- 128 Entering low-power mode
- 128 Exiting low-power mode
- 129 Sleep mode
- 130 Low-power sleep mode (LP sleep)
- 132 Stop mode
- 135 Standby mode
- 138 Power control registers
- 138 PWR power control register (PWR_CR)
- 141 PWR power control/status register (PWR_CSR)
- 143 PWR register map
- 144 Reset and clock control (RCC)
- 144 Reset
- 144 System reset
- 145 Power reset
- 145 RTC and backup registers reset
- 146 Clocks
- 149 HSE clock
- 151 HSI16 clock
- 151 MSI clock
- 153 LSE clock
- 153 LSI clock
- 154 System clock (SYSCLK) selection
- 154 System clock source frequency versus voltage range
- 154 HSE clock security system (CSS)
- 155 LSE Clock Security System
- 155 RTC clock
- 156 Watchdog clock
- 156 Clock-out capability
- 156 Internal/external clock measurement using TIM
- 157 Clock-independent system clock sources for TIM2/TIM21/TIM
- 158 RCC registers
- 158 Clock control register (RCC_CR)
- 161 Internal clock sources calibration register (RCC_ICSCR)
- 162 Clock configuration register (RCC_CFGR)
- 164 Clock interrupt enable register (RCC_CIER)
- 166 Clock interrupt flag register (RCC_CIFR)
- 167 Clock interrupt clear register (RCC_CICR)
- 168 GPIO reset register (RCC_IOPRSTR)
- 169 AHB peripheral reset register (RCC_AHBRSTR)
- 170 APB2 peripheral reset register (RCC_APB2RSTR)
- 171 APB1 peripheral reset register (RCC_APB1RSTR)
- 172 GPIO clock enable register (RCC_IOPENR)
- 174 AHB peripheral clock enable register (RCC_AHBENR)
- 175 APB2 peripheral clock enable register (RCC_APB2ENR)
- 177 APB1 peripheral clock enable register (RCC_APB1ENR)
- 179 GPIO clock enable in Sleep mode register (RCC_IOPSMENR)
- 180 register (RCC_AHBSMENR)
- 181 register (RCC_APB2SMENR)
- 182 register (RCC_APB1SMENR)
- 183 Clock configuration register (RCC_CCIPR)
- 184 Control/status register (RCC_CSR)
- 188 RCC register map
- 191 General-purpose I/Os (GPIO)
- 191 Introduction
- 191 GPIO main features
- 191 GPIO functional description
- 193 General-purpose I/O (GPIO)
- 194 I/O pin alternate function multiplexer and mapping
- 195 I/O port control registers
- 195 I/O port data registers
- 195 I/O data bitwise handling
- 195 GPIO locking mechanism
- 196 I/O alternate function input/output
- 196 External interrupt/wakeup lines
- 196 Input configuration
- 197 Output configuration
- 198 Alternate function configuration
- 199 Analog configuration
- 199 Using the HSE or LSE oscillator pins as GPIOs
- 199 Using the GPIO pins in the RTC supply domain
- 200 BOOT0/GPIO pin sharing
- 200 GPIO registers
- 200 (x =A to E and H)
- 200 (x = A to E and H)
- 205 GPIO port bit reset register (GPIOx_BRR) (x = A to E and H)
- 206 GPIO register map
- 208 System configuration controller (SYSCFG)
- 208 Introduction
- 209 SYSCFG registers
- 209 SYSCFG memory remap register (SYSCFG_CFGR1)
- 210 Reference control and status register (SYSCFG_CFGR3)
- 211 (SYSCFG_EXTICR1)
- 213 (SYSCFG_EXTICR2)
- 213 (SYSCFG_EXTICR3)
- 214 (SYSCFG_EXTICR4)
- 215 SYSCFG register map
- 216 Direct memory access controller (DMA)
- 216 Introduction
- 216 DMA main features
- 217 DMA implementation
- 217 DMA request mapping
- 219 DMA functional description
- 219 DMA block diagram
- 220 DMA transfers
- 220 DMA arbitration
- 221 DMA channels
- 224 DMA data width, alignment and endianness
- 226 DMA error management
- 226 DMA interrupts
- 226 DMA registers
- 227 DMA interrupt status register (DMA_ISR)
- 229 DMA interrupt flag clear register (DMA_IFCR)
- 230 DMA channel x configuration register (DMA_CCRx)
- 234 DMA channel x peripheral address register (DMA_CPARx)
- 234 DMA channel x memory address register (DMA_CMARx)
- 236 DMA channel selection register (DMA_CSELR)
- 236 DMA register map
- 239 Nested vectored interrupt controller (NVIC)
- 239 Main features
- 239 SysTick calibration value register
- 239 Interrupt and exception vectors
- 242 Extended interrupt and event controller (EXTI)
- 242 Introduction
- 242 EXTI main features
- 242 EXTI functional description
- 243 EXTI block diagram
- 243 Wakeup event management
- 244 Peripherals asynchronous interrupts
- 244 Hardware interrupt selection
- 244 Hardware event selection
- 244 Software interrupt/event selection
- 245 EXTI interrupt/event line mapping
- 247 EXTI registers
- 247 EXTI interrupt mask register (EXTI_IMR)
- 247 EXTI event mask register (EXTI_EMR)
- 248 EXTI rising edge trigger selection register (EXTI_RTSR)
- 249 Falling edge trigger selection register (EXTI_FTSR)
- 249 EXTI software interrupt event register (EXTI_SWIER)
- 250 EXTI pending register (EXTI_PR)
- 251 EXTI register map
- 252 Analog-to-digital converter (ADC)
- 252 Introduction
- 253 ADC main features
- 254 ADC functional description
- 254 ADC pins and internal signals
- 255 ADC voltage regulator (ADVREGEN)
- 256 Calibration (ADCAL)
- 258 ADC on-off control (ADEN, ADDIS, ADRDY)
- 259 ADC clock (CKMODE, PRESC[3:0], LFMEN)
- 261 ADC connectivity
- 262 Configuring the ADC
- 262 Channel selection (CHSEL, SCANDIR)
- 262 Programmable sampling time (SMP)
- 263 13.3.10 Single conversion mode (CONT = 0)
- 263 13.3.11 Continuous conversion mode (CONT = 1)
- 264 13.3.12 Starting conversions (ADSTART)
- 265 13.3.13 Timings
- 266 13.3.14 Stopping an ongoing conversion (ADSTP)
Other manuals and documents
Frequently Answers and Questions
What is the maximum operating frequency of the STM32L010F4?
The maximum operating frequency of the STM32L010F4 is 32MHz.
What is the power consumption of the STM32L010F4 in standby mode?
The power consumption of the STM32L010F4 in standby mode is typically 1.2µA.
What is the package size of the STM32L010F4?
The package size of the STM32L010F4 is 3x3mm.
advertisement