STMicroelectronics STM32L010F4 Reference Manual

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Dokument

Oglas

RM0451

Reference manual

Ultra-low-power STM32L0x0 advanced Arm

-based

32-bit MCUs

Introduction

This reference manual targets application developers. It provides complete information on how to use the STM32L0x0 microcontroller memory and peripherals.

The STM32L0x0 is a line of microcontrollers with different memory sizes, packages and peripherals. It includes STM32L010xx part numbers.

For ordering information, mechanical, and electrical device characteristics please refer to the corresponding datasheets.

For information on the Arm

Cortex ® -M0+ core, please refer to the Cortex ® -M0+ Technical

Reference Manual .

The STM32L0x0 microcontrollers include state-of-the-art patented technology.

List of tables

List of tables

STM32L010 memory density . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Overview of features per category . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

STM32L010xx peripheral register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Boot modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

NVM organization (category 1 devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

NVM organization (category 2 devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

NVM organization (category 3 devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 9.

NVM organization (category 5 devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 10.

Link between master clock power range and frequencies . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 11.

Delays to memory access and number of wait states. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 12.

Internal buffer management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 13.

Configurations for buffers and speculative reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 14.

Dhrystone performances in all memory interface configurations . . . . . . . . . . . . . . . . . . . . 57

Table 15.

NVM write/erase timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 16.

NVM write/erase duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 17.

Protection level and content of RDP Option bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Table 18.

Link between protection bits of FLASH_WRPROTx register

and protected address in Flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 19.

Memory access vs mode, protection and Flash program memory sectors. . . . . . . . . . . . . 76

Table 20.

Flash interrupt request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Table 21.

Flash interface - register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Table 22.

Option byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Table 23.

Option byte organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Table 24.

CRC internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Table 25.

CRC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Table 26.

Segment accesses according to the Firewall state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Table 27.

Segment granularity and area ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Table 28.

Firewall register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Table 29.

Performance versus VCORE ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Table 30.

Summary of low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Table 31.

Sleep-now. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Table 32.

Sleep-on-exit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Table 33.

Sleep-now (Low-power sleep) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Table 34.

Sleep-on-exit (Low-power sleep) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Table 35.

Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Table 36.

Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Table 37.

PWR - register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

Table 38.

HSE/LSE clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Table 39.

System clock source frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

Table 40.

RCC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

Table 41.

Port bit configuration table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

Table 42.

GPIO register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

Table 43.

SYSCFG register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

Table 44.

DMA implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

Table 45.

DMA requests for each channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

Table 46.

Programmable data width and endian behavior (when PINC = MINC = 1) . . . . . . . . . . . 225

Table 47.

DMA interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

RM0451 Rev 3 25/784

List of tables RM0451

Table 48.

DMA register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

Table 49.

List of vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

Table 50.

EXTI lines connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

Table 51.

Extended interrupt/event controller register map and reset values. . . . . . . . . . . . . . . . . . 251

Table 52.

ADC input/output pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254

Table 53.

ADC internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

Table 54.

External triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

Table 55.

Latency between trigger and start of conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

Table 56.

Configuring the trigger polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266

Table 57.

tSAR timings depending on resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268

Table 58.

Analog watchdog comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277

Table 59.

Analog watchdog channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277

Table 60.

Maximum output results vs N and M. Grayed values indicates truncation . . . . . . . . . . . . 281

Table 61.

ADC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285

Table 62.

ADC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300

Table 63.

Counting direction versus encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333

Table 64.

TIM2/TIM3 internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350

Table 65.

Output control bit for standard OCx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360

Table 66.

TIM2 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367

Table 67.

Counting direction versus encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400

Table 68.

Output control bit for standard OCx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418

Table 69.

TIM21/22 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422

Table 70.

STM32L010xx LPTIM features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425

Table 71.

LPTIM1 external trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426

Table 72.

Prescaler division ratios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427

Table 73.

Encoder counting scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433

Table 74.

Effect of low-power modes on the LPTIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434

Table 75.

Interrupt events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435

Table 76.

LPTIM register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444

Table 77.

IWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453

Table 78.

WWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459

Table 79.

RTC implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461

Table 80.

RTC pin PC13 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463

Table 81.

RTC_OUT mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464

Table 82.

Effect of low-power modes on RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477

Table 83.

Interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477

Table 84.

RTC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502

Table 85.

STM32L010xx I2C features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506

Table 86.

I2C input/output pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508

Table 87.

I2C internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508

Table 88.

Comparison of analog vs. digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510

Table 89.

I2C-SMBUS specification data setup and hold times . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513

Table 90.

I2C configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517

Table 91.

I2C-SMBUS specification clock timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528

Table 92.

Examples of timing settings for fI2CCLK = 8 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538

Table 93.

Examples of timings settings for fI2CCLK = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538

Table 94.

SMBus timeout specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540

Table 95.

SMBus with PEC configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543

Table 96.

Examples of TIMEOUTA settings for various I2CCLK frequencies

(max t

TIMEOUT

= 25 ms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544

Table 97.

Examples of TIMEOUTB settings for various I2CCLK frequencies . . . . . . . . . . . . . . . . . 544

Table 98.

Examples of TIMEOUTA settings for various I2CCLK frequencies

26/784 RM0451 Rev 3

RM0451 List of tables

(max t

IDLE

= 50 µs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544

Table 99.

Effect of low-power modes on the I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555

Table 100. I2C Interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556

Table 101. I2C register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571

Table 102. STM32L010x USART/LPUART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575

Table 103. Noise detection from sampled data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587

Table 104. Error calculation for programmed baud rates at f

= 32 MHz in both cases of oversampling by 16 or by 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590

Table 105. Tolerance of the USART receiver when BRR [3:0] = 0000. . . . . . . . . . . . . . . . . . . . . . . . 591

Table 106. Tolerance of the USART receiver when BRR [3:0] is different from 0000 . . . . . . . . . . . . 591

Table 107. Frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596

Table 108. Effect of low-power modes on the USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615

Table 109. USART interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615

Table 110. USART register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639

Table 111. STM32L010x USART/LPUART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643

Table 112. Error calculation for programmed baud rates at fck = 32.768 kHz . . . . . . . . . . . . . . . . . . 654

Table 113. Error calculation for programmed baud rates at fck = 32 MHz . . . . . . . . . . . . . . . . . . . . . 654

Table 114. Tolerance of the LPUART receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655

Table 115. Frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658

Table 116. Effect of low-power modes on the LPUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667

Table 117. LPUART interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667

Table 118. LPUART register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683

Table 119. STM32L010xx SPI implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685

Table 120. SPI interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706

Table 121. SPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714

Table 122. SW debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 716

Table 123. REV_ID values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 718

Table 124. Packet request (8-bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 718

Table 125. ACK response (3 bits). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719

Table 126. DATA transfer (33 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719

Table 127. SW-DP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720

Table 128. 32-bit debug port registers addressed through the shifted value A[3:2] . . . . . . . . . . . . . . 721

Table 129. Core debug registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722

Table 130. DBG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 729

Table 131. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777

RM0451 Rev 3 27/784

List of figures

List of figures

RM0451

Figure 1.

System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 2.

Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 3.

Structure of one internal buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 4.

Timing to fetch and execute instructions with prefetch disabled. . . . . . . . . . . . . . . . . . . . . 54

Figure 5.

Timing to fetch and execute instructions with prefetch enabled . . . . . . . . . . . . . . . . . . . . . 56

Figure 6.

RDP levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Figure 7.

CRC calculation unit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Figure 8.

STM32L010xx firewall connection schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Figure 9.

Firewall functional states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Figure 10.

Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Figure 11.

Performance versus VDD and VCORE range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Figure 12.

Power supply supervisors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Figure 13.

Power-on reset/power-down reset waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Figure 14.

BOR thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Figure 15.

Simplified diagram of the reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Figure 16.

Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Figure 17.

Using TIM21 channel 1 input capture to measure frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

Figure 18.

Basic structure of an I/O port bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

Figure 19.

Basic structure of a 5-Volt tolerant I/O port bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

Figure 20.

Input floating / pull up / pull down configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

Figure 21.

Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

Figure 22.

Alternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

Figure 23.

High impedance-analog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

Figure 24.

DMA request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

Figure 25.

DMA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

Figure 26.

Extended interrupts and events controller (EXTI) block diagram . . . . . . . . . . . . . . . . . . . 243

Figure 27.

Extended interrupt/event GPIO mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

Figure 28.

ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254

Figure 29.

ADC calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

Figure 30.

Calibration factor forcing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

Figure 31.

Enabling/disabling the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259

Figure 32.

ADC clock scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259

Figure 33.

ADC connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

Figure 34.

Analog to digital conversion time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

Figure 35.

ADC conversion timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

Figure 36.

Stopping an ongoing conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266

Figure 37.

Single conversions of a sequence, software trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269

Figure 38.

Continuous conversion of a sequence, software trigger . . . . . . . . . . . . . . . . . . . . . . . . . . 269

Figure 39.

Single conversions of a sequence, hardware trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270

Figure 40.

Continuous conversions of a sequence, hardware trigger . . . . . . . . . . . . . . . . . . . . . . . . 270

Figure 41.

Data alignment and resolution (oversampling disabled: OVSE = 0). . . . . . . . . . . . . . . . . 271

Figure 42.

Example of overrun (OVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272

Figure 43.

Wait mode conversion (continuous mode, software trigger). . . . . . . . . . . . . . . . . . . . . . . 274

Figure 44.

Behavior with WAIT = 0, AUTOFF = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

Figure 45.

Behavior with WAIT = 1, AUTOFF = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276

Figure 46.

Analog watchdog guarded area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277

Figure 47.

ADC_AWD1_OUT signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278

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Figure 48.

ADC_AWD1_OUT signal generation (AWD flag not cleared by software) . . . . . . . . . . . . 279

Figure 49.

ADC1_AWD_OUT signal generation (on a single channel) . . . . . . . . . . . . . . . . . . . . . . . 279

Figure 50.

Analog watchdog threshold update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280

Figure 51.

20-bit to 16-bit result truncation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281

Figure 52.

Numerical example with 5-bits shift and rounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281

Figure 53.

Triggered oversampling mode (TOVS bit = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283

Figure 54.

VREFINT channel block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283

Figure 55.

General-purpose timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303

Figure 56.

Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 305

Figure 57.

Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 305

Figure 58.

Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306

Figure 59.

Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307

Figure 60.

Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307

Figure 61.

Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308

Figure 62.

Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded). . . . . 308

Figure 63.

Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . . . . . 309

Figure 64.

Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310

Figure 65.

Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310

Figure 66.

Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311

Figure 67.

Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311

Figure 68.

Counter timing diagram, Update event when repetition counter is not used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312

Figure 69.

Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . . . . . . . . . . . . 313

Figure 70.

Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314

Figure 71.

Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . . 314

Figure 72.

Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315

Figure 73.

Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . . . . . . . . . 315

Figure 74.

Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . . . . . . . . . . 316

Figure 75.

Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 317

Figure 76.

TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317

Figure 77.

Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318

Figure 78.

External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319

Figure 79.

Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320

Figure 80.

Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 321

Figure 81.

Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321

Figure 82.

Output stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 322

Figure 83.

PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324

Figure 84.

Output compare mode, toggle on OC1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326

Figure 85.

Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327

Figure 86.

Center-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329

Figure 87.

Example of one-pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330

Figure 88.

Clearing TIMx OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332

Figure 89.

Example of counter operation in encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . 334

Figure 90.

Example of encoder interface mode with TI1FP1 polarity inverted . . . . . . . . . . . . . . . . . 334

Figure 91.

Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335

Figure 92.

Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336

Figure 93.

Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337

Figure 94.

Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . 339

Figure 95.

Master/Slave timer example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339

Figure 96.

Gating timer y with OC1REF of timer x. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341

Figure 97.

Gating timer y with Enable of timer x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342

Figure 98.

Triggering timer y with update of timer x. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343

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List of figures RM0451

Figure 99.

Triggering timer y with Enable of timer x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343

Figure 100. Triggering timer x and y with timer x TI1 input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344

Figure 101. General-purpose timer block diagram (TIM21/22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370

Figure 102. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 372

Figure 103. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 373

Figure 104. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374

Figure 105. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375

Figure 106. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375

Figure 107. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376

Figure 108. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376

Figure 109. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377

Figure 110. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378

Figure 111. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378

Figure 112. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379

Figure 113. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379

Figure 114. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . . . . . . . . . . . . 381

Figure 115. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381

Figure 116. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . . 382

Figure 117. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382

Figure 118. Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . . . . . . . . . 383

Figure 119. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . . . . . . . . . . 383

Figure 120. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 384

Figure 121. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385

Figure 122. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386

Figure 123. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386

Figure 124. Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387

Figure 125. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 388

Figure 126. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388

Figure 127. Output stage of capture/compare channel (channel 1 and 2). . . . . . . . . . . . . . . . . . . . . . 389

Figure 128. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391

Figure 129. Output compare mode, toggle on OC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393

Figure 130. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394

Figure 131. Center-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395

Figure 132. Clearing TIMx OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397

Figure 133. Example of one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398

Figure 134. Example of counter operation in encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . 400

Figure 135. Example of encoder interface mode with TI1FP1 polarity inverted . . . . . . . . . . . . . . . . . 401

Figure 136. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402

Figure 137. Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403

Figure 138. Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404

Figure 139. Low-power timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425

Figure 140. Glitch filter timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427

Figure 141. LPTIM output waveform, single counting mode configuration . . . . . . . . . . . . . . . . . . . . . 429

Figure 142. LPTIM output waveform, Single counting mode configuration and Set-once mode activated (WAVE bit is set) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429

Figure 143. LPTIM output waveform, Continuous counting mode configuration . . . . . . . . . . . . . . . . . 430

Figure 144. Waveform generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431

Figure 145. Encoder mode counting sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434

Figure 146. Independent watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445

Figure 147. Watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455

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Figure 148. Window watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456

Figure 149. RTC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462

Figure 150. I2C1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507

Figure 151. I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509

Figure 152. Setup and hold timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511

Figure 153. I2C initialization flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514

Figure 154. Data reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515

Figure 155. Data transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516

Figure 156. Slave initialization flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519

Figure 157. Transfer sequence flow for I2C slave transmitter, NOSTRETCH = 0. . . . . . . . . . . . . . . . 521

Figure 158. Transfer sequence flow for I2C slave transmitter, NOSTRETCH = 1. . . . . . . . . . . . . . . . 522

Figure 159. Transfer bus diagrams for I2C slave transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523

Figure 160. Transfer sequence flow for slave receiver with NOSTRETCH = 0 . . . . . . . . . . . . . . . . . 524

Figure 161. Transfer sequence flow for slave receiver with NOSTRETCH = 1 . . . . . . . . . . . . . . . . . 525

Figure 162. Transfer bus diagrams for I2C slave receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525

Figure 163. Master clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527

Figure 164. Master initialization flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529

Figure 165. 10-bit address read access with HEAD10R = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529

Figure 166. 10-bit address read access with HEAD10R = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530

Figure 167. Transfer sequence flow for I2C master transmitter for N ≤ 255 bytes . . . . . . . . . . . . . . . . 531

Figure 168. Transfer sequence flow for I2C master transmitter for N>255 bytes . . . . . . . . . . . . . . . . 532

Figure 169. Transfer bus diagrams for I2C master transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533

Figure 170. Transfer sequence flow for I2C master receiver for N ≤ 255 bytes . . . . . . . . . . . . . . . . . . 535

Figure 171. Transfer sequence flow for I2C master receiver for N >255 bytes . . . . . . . . . . . . . . . . . . 536

Figure 172. Transfer bus diagrams for I2C master receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537

Figure 173. Timeout intervals for t

LOW:SEXT

, t

LOW:MEXT

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541

Figure 174. Transfer sequence flow for SMBus slave transmitter N bytes + PEC. . . . . . . . . . . . . . . . 545

Figure 175. Transfer bus diagrams for SMBus slave transmitter (SBC=1) . . . . . . . . . . . . . . . . . . . . . 546

Figure 176. Transfer sequence flow for SMBus slave receiver N Bytes + PEC . . . . . . . . . . . . . . . . . 547

Figure 177. Bus transfer diagrams for SMBus slave receiver (SBC=1). . . . . . . . . . . . . . . . . . . . . . . . 548

Figure 178. Bus transfer diagrams for SMBus master transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549

Figure 179. Bus transfer diagrams for SMBus master receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551

Figure 180. USART block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577

Figure 181. Word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579

Figure 182. Configurable stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581

Figure 183. TC/TXE behavior when transmitting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582

Figure 184. Start bit detection when oversampling by 16 or 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583

Figure 185. Data sampling when oversampling by 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586

Figure 186. Data sampling when oversampling by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587

Figure 187. Mute mode using Idle line detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594

Figure 188. Mute mode using address mark detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595

Figure 189. Break detection in LIN mode (11-bit break length - LBDL bit is set) . . . . . . . . . . . . . . . . . 598

Figure 190. Break detection in LIN mode vs. Framing error detection. . . . . . . . . . . . . . . . . . . . . . . . . 599

Figure 191. USART example of synchronous transmission. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600

Figure 192. USART data clock timing diagram (M bits = 00). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600

Figure 193. USART data clock timing diagram (M bits = 01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601

Figure 194. RX data setup/hold time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601

Figure 195. ISO 7816-3 asynchronous protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603

Figure 196. Parity error detection using the 1.5 stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604

Figure 197. IrDA SIR ENDEC- block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608

Figure 198. IrDA data modulation (3/16) -Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609

Figure 199. Transmission using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610

RM0451 Rev 3 31/784

List of figures RM0451

Figure 200. Reception using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611

Figure 201. Hardware flow control between 2 USARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611

Figure 202. RS232 RTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612

Figure 203. RS232 CTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613

Figure 204. USART interrupt mapping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616

Figure 205. LPUART block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645

Figure 206. Word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647

Figure 207. Configurable stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648

Figure 208. TC/TXE behavior when transmitting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650

Figure 209. Mute mode using Idle line detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657

Figure 210. Mute mode using address mark detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658

Figure 211. Transmission using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661

Figure 212. Reception using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 662

Figure 213. Hardware flow control between 2 LPUARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 662

Figure 214. RS232 RTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663

Figure 215. RS232 CTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664

Figure 216. LPUART interrupt mapping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668

Figure 217. SPI block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686

Figure 218. Full-duplex single master/ single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687

Figure 219. Half-duplex single master/ single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688

Figure 220. Simplex single master/single slave application (master in transmit-only/ slave in receive-only mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689

Figure 221. Master and three independent slaves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690

Figure 222. Multi-master application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691

Figure 223. Hardware/software slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 692

Figure 224. Data clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694

Figure 225. TXE/RXNE/BSY behavior in master / full-duplex mode (BIDIMODE=0,

RXONLY=0) in the case of continuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 697

Figure 226. TXE/RXNE/BSY behavior in slave / full-duplex mode (BIDIMODE=0,

RXONLY=0) in the case of continuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 698

Figure 227. Transmission using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700

Figure 228. Reception using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 701

Figure 229. TI mode transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704

Figure 230. Block diagram of STM32L010xx MCU and Cortex

® -M0+-level debug support . . . . . . . . 715

32/784 RM0451 Rev 3

RM0451 Documentation conventions

The STM32L010xx devices have an Arm

®(a)

Cortex

-M0+ core.

1.2 List of abbreviations for registers

The following abbreviations (b) are used in register descriptions: read-only (r) write-only (w) read/write (rw) read/clear write0 (rc_w0) read/clear write1 (rc_w1) read/clear write (rc_w) read/clear by read (rc_r) read/set by read (rs_r)

Software can read and write to this bit.

Software can only read this bit.

Software can only write to this bit. Reading this bit returns the reset value.

Software can read as well as clear this bit by writing 0. Writing 1 has no effect on the bit value.

Software can read as well as clear this bit by writing 1. Writing 0 has no effect on the bit value.

Software can read as well as clear this bit by writing to the register. The value written to this bit is not important.

Software can read this bit. Reading this bit automatically clears it to 0.

Writing this bit has no effect on the bit value.

Software can read this bit. Reading this bit automatically sets it to 1.

Writing this bit has no effect on the bit value.

read/set (rs) read/write once (rwo)

Software can read as well as set this bit. Writing 0 has no effect on the bit value.

Software can only write once to this bit and can also read it at any time.

Only a reset can return the bit to its reset value.

The software can toggle this bit by writing 1. Writing 0 has no effect.

toggle (t) read-only write trigger (rt_w1) Software can read this bit. Writing 1 triggers an event but has no effect on the bit value.

Reserved (Res.) Reserved bit, must be kept at reset value.

a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

b. This is an exhaustive list of all abbreviations applicable to STMicroelectronics microcontrollers, some of them may not be used in the current document.

RM0451 Rev 3 33/784

Documentation conventions RM0451

1.3 Glossary

This section gives a brief definition of acronyms and abbreviations used in this document:

• Word : data of 32-bit length.

• Half-word : data of 16-bit length.

• Byte : data of 8-bit length.

• Option bytes : product configuration bits stored in the Flash memory.

• AHB : advanced high-performance bus.

For availability of peripherals and their number across all sales types, refer to the particular device datasheet.

1.5 Product category definition

Table 1 gives an overview of memory density versus product line.

The present reference manual describes the superset of features for each product category.

Refer to Table 2

for the list of features per category.

Memory density

8 Kbytes

16 Kbytes

32 Kbytes

64 Kbytes

128 Kbytes

Table 1. STM32L010 memory density

Category 1 Category 2 Category 3

STM32L010x3

STM32L010x4

STM32L010x6

STM32L010x8

Category 5

STM32L010xB

Feature

Table 2. Overview of features per category

Category 1

NVM full-featured, single bank

Cyclic redundancy check calculation unit

(CRC)

Firewall (FW)

Power control (PWR)

Reset and clock control (RCC)

GPIOA full-featured

full-featured

HSE supports bypass only, no CSS on HSE full-featured

Category 2 full-featured, single bank full-featured

full-featured full-featured full-featured

Category 3 full-featured, single bank full-featured full-featured full-featured full-featured full-featured

Category 5 full-featured, single bank full-featured full-featured full-featured full-featured full-featured

34/784 RM0451 Rev 3

RM0451 Documentation conventions

Feature

Table 2. Overview of features per category (continued)

Category 1 Category 2 Category 3

GPIOB

GPIOC

GPIOD

GPIOE

GPIOH

System configuration controller (SYSCFG)

Direct memory access controller (DMA1)

Nested vectored interrupt controller

(NVIC)

Extended interrupt and event controller

(EXTI)

Analog-to-digital converter (ADC1)

General-purpose timers (TIM2)

General-purpose timers (TIM21)

General-purpose timers (TIM22)

Low power timer

(LPTIM1)

Independent watchdog (IWDG)

System window watchdog (WWDG)

Real-time clock (RTC)

Inter-integrated circuit

(I2C1) interface

[0:9], BOOT0/PB9 sharing the same pin

[14:15]

full-featured full-featured full-featured full-featured full-featured full-featured full-featured

full-featured full-featured full-featured

Universal synchronous asynchronous receiver transmitter

(USART2) full-featured up to 400 kHz, no

Fast-mode Plus no synchronous mode, no LIN mode, no dual clock, no receiver timeout, no ModBus, no autobaudrate, no Smartcard mode full-featured

[0][13:15]

[0:1] full-featured full-featured full-featured full-featured full-featured full-featured full-featured

full-featured full-featured full-featured full-featured up to 400 kHz, no

Fast-mode Plus no synchronous mode, no LIN mode, no dual clock, no receiver timeout, no ModBus, no autobaudrate, no Smartcard mode full-featured full-featured

[2]

[0:1] full-featured full-featured full-featured full-featured full-featured full-featured full-featured

full-featured full-featured full-featured full-featured up to 400 kHz, no

Fast-mode Plus no LIN mode

Category 5 full-featured full-featured full-featured full-featured

[0:1][9:10] full-featured full-featured full-featured full-featured full-featured full-featured full-featured full-featured full-featured full-featured full-featured full-featured up to 400 kHz, no

Fast-mode Plus no LIN mode

RM0451 Rev 3 35/784

Documentation conventions

Feature

Low-power universal asynchronous receiver transmitter

(LPUART1)

Serial peripheral interface(SPI1)

Debug support (DBG)

Device electronic signature

Table 2. Overview of features per category (continued)

Category 1 Category 2 Category 3 full-featured no I2S full-featured full-featured full-featured no I2S full-featured full-featured full-featured no I2S full-featured full-featured

RM0451

Category 5 full-featured no I2S full-featured full-featured

36/784 RM0451 Rev 3

RM0451

2 System and memory overview

System and memory overview

The main system consists of:

• Two masters:

– Cortex

-M0+ core (AHB-lite bus)

– GP-DMA (general-purpose DMA)

• Three slaves:

– Internal SRAM

– Internal Non-volatile memory

– AHB to APB, which connects all the APB peripherals

These are interconnected using a multilayer AHB bus architecture as shown in Figure 1

Figure 1. System architecture

GPIO ports

A,B,C,D,E,H

IOPORT

Cortex

M0+

System bus

MIF

Memory interface

SRAM

NVM memory

Busmatrix

DMA

Controller

(Channels

1 to 7)

DMA

AHB2APB

Bridges

Reset and clock controller

(RCC)

APB buses

CRC

SYSCFG

FIREWALL

PWR

EXTI

ADC

TIM2/21/22

LPTIM1

IWDG

WWDG

RTC

DBGMCU

I2C1

USART2/LPUART1

SPI1

DMA request

MS46192V1

1. Refer to

Table 1: STM32L010 memory density

, to

Table 2: Overview of features per category and to the device datasheets

for the GPIO ports and peripherals available on your device.

RM0451 Rev 3 37/784

System and memory overview RM0451

Cortex

-bus

This bus connects the DCode/ICode bus of the Cortex ® -M0+ core to the BusMatrix. This bus is used by the core to fetch instructions, get data and access the AHB/APB resources.

This bus connects the AHB master interface of the DMA to the BusMatrix which manages the access of the different masters to Flash memory and data EEPROM, the SRAM and the

AHB/APB peripherals.

2.1.3 BusMatrix

The BusMatrix manages the access arbitration between masters. The arbitration uses a

Round Robin algorithm. The BusMatrix is composed of two masters (CPU, DMA) and three slaves (NVM interface, SRAM, AHB2APB1/2 bridges).

Note:

AHB/APB bridges

The AHB/APB bridge provide full synchronous connections between the AHB and the 2

APB buses. APB1 and APB2 operate at a maximum frequency of 32 MHz.

Refer to Section 2.2.2: Memory map and register boundary addresses on page 40

for the address mapping of the peripherals connected to this bridge.

After each device reset, all peripheral clocks are disabled (except for the SRAM and MIF).

Before using a peripheral you have to enable its clock in the RCC_AHBENR,

RCC_APB2ENR, RCC_APB1ENR or RCC_IOPENR register.

When a 16- or 8-bit access is performed on an APB register, the access is transformed into a 32-bit access: the bridge duplicates the 16- or 8-bit data to feed the 32-bit vector.

38/784 RM0451 Rev 3

RM0451

2.2.1 Introduction

Program memory, data memory, registers and I/O ports are organized within the same linear

4-Gbyte address space.

The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word is considered the word’s least significant byte and the highest numbered byte the most significant.

The addressable memory space is divided into eight main blocks, of 512 Mbytes each.

RM0451 Rev 3 39/784

2.2.2

RM0451

Memory map and register boundary addresses

Figure 2. Memory map

0xFFFF FFFF

0xE010 0000

0xE000 0000

Cortex-M0+ peripherals

0xC000 0000

0xA000 0000

0x8000 0000

0x6000 0000

0x4000 0000

Peripherals

0x1FFF FFFF

Option bytes

System memory reserved

0x5000 1FFF

0x5000 0000

IOPORT reserved

0x4002 63FF

0x4002 0000

AHB reserved

0x4001 8000

APB2

0x4001 0000 reserved

0x4000 8000

0x4000 0000

APB1

0x2000 0000

0x0000 0000

SRAM

CODE

Flash system memory

0x0800 0000

0x0000 0000 reserved

Flash, system memory or

SRAM, depending on

BOOT configuration

Reserved

MS34761V2

All the memory map areas that are not allocated to on-chip memories and peripherals are considered “Reserved”. For the detailed mapping of available memory and register areas, refer to the following table.

40/784 RM0451 Rev 3

RM0451

The following table gives the boundary addresses of the peripherals available in the devices.

Bus

IOPORT

AHB

Table 3. STM32L010xx peripheral register boundary addresses (1)

Boundary address Size (bytes) Peripheral Peripheral register map

0X5000 1C00 - 0X5000 1FFF

0X5000 1400 - 0X5000 1BFF

0X5000 1000 - 0X5000 13FF

0X5000 0C00 - 0X5000 0FFF

0X5000 0800 - 0X5000 0BFF

0X5000 0400 - 0X5000 07FF

0X5000 0000 - 0X5000 03FF

0X4002 3400 - 0x4002 FFFF

0X4002 3000 - 0X4002 33FF

0X4002 2400 - 0X4002 2FFF

0X4002 2000 - 0X4002 23FF

0X4002 1400 - 0X4002 1FFF

0X4002 1000 - 0X4002 13FF

0X4002 0400 - 0X4002 0FFF

0X4002 0000 - 0X4002 03FF

2 K

59 K

1 K

3 K

1 K

3 K

1 K

3 K

1 K

GPIOH

Reserved

GPIOE

GPIOD

GPIO C

GPIOB

GPIOA

Reserved

CRC

Reserved

FLASH

Reserved

RCC

Reserved

DMA1

Section 8.4.12: GPIO register map

Section 4.4.6: CRC register map

Section 3.7.11: Flash register map

Section 7.3.21: RCC register map

Section 10.6: DMA registers

RM0451 Rev 3 41/784

RM0451

Bus

APB2

APB1

Table 3. STM32L010xx peripheral register boundary addresses (1) (continued)

Boundary address Size (bytes) Peripheral Peripheral register map

0X4001 5C00 - 0X4001 FFFF 42 K Reserved

0X4001 5800 - 0X4001 5BFF

0X4001 3400 - 0X4001 57FF

0X4001 3000 - 0X4001 33FF

0X4001 2800 - 0X4001 2FFF

0X4001 2400 - 0X4001 27FF

0X4001 2000 - 0X4001 23FF

0X4001 1C00 - 0X4001 1FFF

0X4001 18000 - 0X4001 1BFF

0X4001 1400 - 0X4001 17FF

0X4000 0C000 - 0X4001 13FF

0X4001 0800 - 0X4001 0BFF

0X4001 0400 - 0X4001 07FF

0X4001 0000 - 0X4001 03FF

0X4000 8000 - 0X4000 FFFF

0X4000 7C00 - 0X4000 7FFF

0X4000 7800 - 0X4000 7BFF

0X4000 7000 - 0X4000 73FF

0X4000 5800 - 0x4000 6FFF

0X4000 5400 - 0X4000 57FF

0X4000 4C00- 0X4000 53FF

0X4000 4800 - 0X4000 4BFF

0X4000 4400 - 0X4000 47FF

0X4000 3400 - 0X4000 43FF

0X4000 3000 - 0X4000 33FF

1 K

9 K

1 K

2 K

1 K

4 K

1 K

4 K

1 K

32 K

1 K

2 K

1 K

4 K

1 K

DBG

Reserved

SPI1

Reserved

ADC1

Reserved

Firewall

Reserved

TIM22

Reserved

TIM21

EXTI

SYSCFG

Reserved

LPTIM1

Reserved

PWR

Reserved

I2C1

Reserved

LPUART1

USART2

Reserved

IWDG

Section 24.10: DBG register map

Section 23.6.8: SPI register map

Section 13.12: ADC register map

Section 5.4.8: Firewall register map

Section 15.4.16: TIM21/22 register map

Section 12.5.7: EXTI register map

Section 9.2.8: SYSCFG register map

Section 16.7.9: LPTIM register map

Section 6.4.3: PWR register map

Section 20.7: I2C registers

Section 22.7.10: LPUART register map

Section 21.8.12: USART register map

Section 17.4.6: IWDG register map

42/784 RM0451 Rev 3

RM0451

Bus

APB1

SRAM

Table 3. STM32L010xx peripheral register boundary addresses (1) (continued)

Boundary address Size (bytes) Peripheral Peripheral register map

0X4000 2C00 - 0X4000 2FFF

0X4000 2800 - 0X4000 2BFF

0X4000 0400 - 0x4000 27FF

0X4000 0000 - 0X4000 03FF

0X2000 2000 - 0X3FFF FFFF

1 K

7 K

1 K

~524 M

WWDG

RTC +

BKP_REG

Reserved

TIMER2

Reserved

Section 18.5.4: WWDG register map

Section 19.7.21: RTC register map

Section 14.5: TIMx register map

0X2000 0000 - 0X2000 4FFF 20 K -

0X0800 0000 - 0X0801 FFFF

0x0808 0000 - 0x0808 01FF up to 128 K up to 512

SRAM

Flash program memory

Data EEPROM -

NVM 0x1FF0 0000 - 0x1FF0 1FFF

0x1FF8 0020 - 0x1FF8 007F

0x1FF8 0000 - 0x1FF8 001F

8 K

System memory

Factory option bytes

User option bytes

1. Refer to Table 1: STM32L010 memory density

, to

Table 2: Overview of features per category and to the device datasheets

for the GPIO ports and peripherals available on your device. The memory area corresponding to unavailable GPIO ports or peripherals are reserved.

STM32L010xx devices feature up to 20 Kbytes of static SRAM.

This RAM can be accessed as bytes, half-words (16 bits) or full words (32 bits). This memory can be addressed at maximum system clock frequency without wait state and thus by both CPU and DMA.

The SRAM start address is 0x2000 0000.

The CPU can access the SRAM from address 0x0000 0000 when physical remap is selected through boot pin or MEM_MODE (see

Section 9.2.1: SYSCFG memory remap register (SYSCFG_CFGR1) ).

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In the STM32L010xx, three different boot modes can be selected through the BOOT0 pin and boot configuration bits in the User option byte, as shown in the following table.

Table 4. Boot modes

(1)

Boot mode selection

Boot mode Aliasing

BOOT1 pin BOOT0 pin

Flash program memory

System memory

Embedded SRAM

Flash program memory is selected as boot area

System memory is selected as boot area

Embedded SRAM is selected as boot area

1. BOOT1 value is the opposite of nBOOT1 option bit.

Table 5. Boot modes (1)

Boot mode configuration nBOOT1 bit

BOOT0 pin nBOOT_SEL bit nBOOT0 bit

Aliasing

Flash program memory is selected as boot area

System memory is selected as boot area

Embedded SRAM is selected as boot area

Flash program memory is selected as boot area

System memory is selected as boot area

Embedded SRAM is selected as boot area

1. Grayed options are available on category 1 devices only.

The boot mode configuration is latched on the 2nd rising edge of SYSCLK after reset. For category 1 devices, the value present on BOOT0 pin is latched on NRST rising edge. It is up to the user to set nBOOT1 and BOOT0 to select the required boot mode.

The boot mode configuration is also re-sampled when exiting from Standby mode, except for category 1 devices where BOOT0 pin is latched on NRST rising edge. Consequently the boot mode configuration must not be modified in Standby mode (except for category 1 devices). After this startup delay has elapsed, the CPU fetches the top-of-stack value from address 0x0000 0000, then starts code execution from the boot memory at 0x0000 0004.

Depending on the selected boot mode, Flash program memory, system memory or SRAM is accessible as follows:

• Boot from Flash program memory: the Flash program memory is aliased in the boot memory space (0x0000 0000), but still accessible from its original memory space

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Note:

(0x0800 0000). In other words, the Flash memory contents can be accessed starting from address 0x0000 0000 or 0x0800 0000.

• Boot from system memory: the system memory is aliased in the boot memory space

(0x0000 0000), but still accessible from its original memory space (0x 1FF0 0000 ).

• Boot from the embedded SRAM: the SRAM is aliased in the boot memory space

(0x0000 0000), but it is still accessible from its original memory space (0x2000 0000).

BOOT0/GPIO pin sharing (category 1 devices only)

On category 1 devices, the BOOT0 pin is shared with a GPIO pin. The pin state is latched on NRST rising edge as BOOT0 state. The pin logic level can then be read as an input value on the shared GPIO pin. This pin feature specific input voltage characteristics (refer to the corresponding datasheets for details).

Empty check (category 1 devices only)

On category 1 devices, an internal empty check flag is implemented to allow easy programming of virgin devices by the bootloader. This flag is used when BOOT0 pin is configured to select Flash program memory as target boot area. When this flag is set, the device is considered as unprogrammed and the system memory (bootloader) is selected as boot area instead of the Flash program memory to allow the application to program the

Flash memory.

The empty check flag is updated only when the option bytes are loaded: it is set when the content of address 0x0800 0000 is read as 0x0000 0000 and cleared otherwise. As a result, only a power-on reset or setting OBL_LAUNCH bit in FLASH_CR register can clear this flag after programming a virgin device to execute user code after system reset.

If the device is programmed for the first time but the option bytes are not reloaded, the system memory will still be selected as boot area after system reset. In this case, the bootloader code switches the boot memory mapping to Flash program memory and performs a jump to the user code it hosts.

Physical remap

Once the boot pin and bit are selected, the application software can modify the memory accessible in the code area. This modification is performed by programming the

MEM_MODE bits in the SYSCFG memory remap register (SYSCFG_CFGR1).

Embedded bootloader

The embedded bootloader is located in the System memory, programmed by ST during production. It is used to reprogram the Flash memory using one of the following serial interfaces:

• For device categories 1, 2 and 3: USART2 or SPI1.

• For device category 5: USART2, SPI1 or I2C1.

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3

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Flash program memory and data EEPROM (FLASH)

3.1 Introduction

The non-volatile memory (NVM) is composed of:

• Up to 128 Kbytes of Flash program memory. This area is used to store the application code.

• Up to 512 bytes of data EEPROM

• An information block:

– Up to 8 Kbytes of System memory

– Up to 8x4 bytes of user Option bytes

– Up to 96 bytes of factory Option bytes

3.2

3.3 NVM main features

The NVM interface features:

• Read interface organized by word, half-word or byte in every area

• Programming in the Flash memory performed by word or half-page

• Programming in the Option bytes area performed by word

• Programming in the data EEPROM performed by word, half-word or byte (granularity of the data EEPROM is one word, erase/write endurance cycles are linked to one word granularity)

• Erase operation performed by page (in Flash memory, data EEPROM and Option bytes)

• Option byte Loader

• ECC (Error Correction Code): 6 bits stored for every word to recognize and correct just one error

• Mass erase operation

• Read / Write protection

• PCROP protection

• Low-power mode

NVM functional description

The NVM is organized as 32-bit memory cells that can be used to store code, data, boot code or Option bytes.

The memory array is divided into pages. A page is composed of 32 words (or 128 bytes) in

Flash program memory and System memory, and 1 single word (or 4 bytes) in data

EEPROM and Option bytes areas (user and factory). The erase/write endurance cycles are

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NVM linked to one page granularity for Flash program memory and one single word granularity for data EEPROM.

A Flash sector is made of 32 pages (or 4 Kbytes). The sector is the granularity of the write protection.

Table 6. NVM organization (category 1 devices)

NVM addresses

Size

(bytes)

Name Description

Flash program memory

Data EEPROM

Information block

0x0800 0000 - 0x0800 007F

0x0800 0080 - 0x0800 00FF

0x0800 0F80 - 0x0800 0FFF

0x0800 3000 - 0x0800 307F

0x0800 3080 - 0x0800 30FF

0x0800 3F80 - 0x0800 3FFF

0x0808 0000 - 0x0808 007F

0x1FF0 0000 - 0x1FF0 0FFF

0x1FF8 0020 - 0x1FF8 007F

0x1FF8 0000 - 0x1FF8 001F

128 bytes

4 Kbytes

96 bytes

32 bytes

Page 0

Page 1

Page 31

Page 96

Page 97

Page 127 sector 0

sector 3

Data EEPROM

System memory

Factory Options

User Option bytes

NVM

Flash program memory

Data EEPROM

Table 7. NVM organization (category 2 devices)

NVM addresses

Size

(bytes)

Name

0x0800 0000 - 0x0800 007F

0x0800 0080 - 0x0800 00FF

0x0800 0F80 - 0x0800 0FFF

0x0800 7000 - 0x0800 707F

0x0800 7080 - 0x0800 70FF

0x0800 7F80 - 0x0800 7FFF

0x0808 0000 - 0x0808 00FF

128 bytes

256 bytes

Page 0

Page 1

Page 31

Page 224

Page 225

Page 255

Description sector 0

sector 7

Data EEPROM

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NVM

Information block

Table 7. NVM organization (category 2 devices) (continued)

NVM addresses

Size

(bytes)

Name

0x1FF0 0000 - 0x1FF0 0FFF

0x1FF8 0020 - 0x1FF8 007F

0x1FF8 0000 - 0x1FF8 001F

4 Kbytes

96 bytes

32 bytes

Description

System memory

Factory Options

User Option bytes

NVM

Table 8. NVM organization (category 3 devices)

NVM addresses

Size

(bytes)

Name Description

Flash program memory

(1)

0x0800 0000 - 0x0800 007F

0x0800 0080 - 0x0800 00FF

0x0800 0F80 - 0x0800 0FFF

0x0800 7000 - 0x0800 707F

0x0800 7080 - 0x0800 70FF

0x0800 7F80 - 0x0800 7FFF

128 bytes

Page 0

Page 1

Page 31

Page 224

Page 225

Page 255 sector 0

sector 7

0x0800 F000 - 0x0800 F07F

0x0800 F080 - 0x0800 F0FF

128 bytes

Page 480

Page 481

Data EEPROM sector 15

0x0800 FF80 - 0x0800 FFFF

0x0808 0000 - 0x0808 00FF

0x1FF0 0000 - 0x1FF0 0FFF

0x1FF8 0020 - 0x1FF8 007F

128 bytes

256 bytes

4 Kbytes

96 bytes

Page 511

Data EEPROM

System memory

Factory Options Information block

0x1FF8 0000 - 0x1FF8 001F 32 bytes User Option bytes

1. For 32 Kbyte category 3 devices, the Flash program memory is divided into 256 pages of 128 bytes each.

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Flash program memory

Data EEPROM

Information block

Flash program memory and data EEPROM (FLASH)

Table 9. NVM organization (category 5 devices)

NVM addresses Size (bytes)

0x0800 0000 - 0x0800 007F

0x0800 0080 - 0x0800 00FF

0x0800 0F80 - 0x0800 0FFF

0x0800 7000 - 0x0800 707F

0x0800 7080 - 0x0800 70FF

0x0800 7F80 - 0x0800 7FFF

0x0800 FF80- 0x0800 FFFF

0x0801 0000 - 0x0801 007F

0x0801 F000 - 0x0801 F07F

128 bytes

Name

Page 0

Page 1

Page 31

Page 224

Page 225

Page 255

Page 511

Page 512

Page 992

0x0801 FF80 - 0x0801 FFFF

0x0808 0000 - 0x0808 01FF

0x1FF0 0000 - 0x1FF0 1FFF

0x1FF8 0020 - 0x1FF8 007F

0x1FF8 0000 - 0x1FF8 001F

128 bytes

512 Kbytes

8 Kbytes

96 bytes

32 bytes

Description sector 0

sector 7

sector 15 sector 16

sector 31

Page 1023

Data

EEPROM

System memory

Factory

Options

User Option bytes

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Protocol to read

To read the NVM content, take any address from

Section 3.3.1: NVM organization . The

clock of the memory interface must be running. (see MIFEN bit in

Section 7.3.12: AHB peripheral clock enable register (RCC_AHBENR) ).

Depending on the clock frequency, a 0 or a 1 wait state can be necessary to read the NVM.

The user must set the correct number of wait states (LATENCY bit in the FLASH_ACR register). No control is done to verify if the frequency or the power used is correct, with respect to the number of wait states. A wrong number of wait states can generate wrong read values (high frequency and 0 wait states) or a long time to execute a code (low frequency with 1 wait state).

You can read the NVM by word (4 bytes), half-word (2 bytes) or byte.

It is not possible to read the NVM during a write/erase operation. If a write/erase operation is ongoing, the reading will be in a wait state until the write/erase operation completes, stalling the master that requested the read operation, except when the address is read-protected. In this case, the error is sent to the master by a hard fault or a memory interface flag; no stall is generated and no read is waiting.

Relation between CPU frequency/Operation mode/NVM read time

The device (and the NVM) can work at different power ranges. For every range, some

master clock frequencies can be set. Table 10

resumes the link between the power range and the frequencies to ensure a correct time access to the NVM.

Table 10. Link between master clock power range and frequencies

Name Power range

Maximum frequency

(with 1 wait state)

Maximum frequency

(without wait states)

Range 1

Range 2

Range 3

1.65 V - 1.95 V

1.35 V - 1.65 V

1.05 V - 1.35 V

32 MHz

16 MHz

4.2 MHz

16 MHz

8 MHz

4.2 MHz

Table 11 shows the delays to read a word in the NVM. Comparing the complete time to read

a word (Ttotal) with the clock period, you can see that in Range 3 no wait state is necessary, also with the maximum frequency (4.2 MHz) allowed by the device. Ttotal is the time that the

NVM needs to return a value, and not the complete time to read it (from memory to Core through the memory interface); all remaining time is lost.

Name

Table 11. Delays to memory access and number of wait states

Ttotal Frequency Period

Number of wait state required

Range 1

Range 2

46.1 ns

86.8 ns

32 MHz

16 MHz

8 MHz

31.25

62.5

125

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Table 11. Delays to memory access and number of wait states (continued)

Name Ttotal Frequency Period

Number of wait state required

Range 3 184.6 ns

4 MHz

2 MHz

250

500

Change the CPU Frequency

After reset, the clock used is the MSI (2.1 MHz) and 0 wait state is configured in the

FLASH_ACR register. The following software sequences have to be respected to tune the number of wait states needed to access the NVM with the CPU frequency.

A CPU clock or a number of wait state configuration changes may take some time before being effective. Checking the AHB prescaler factor and the clock source status values is a way to ensure that the correct CPU clock frequency is the configured one. Similarly, the read of FLASH_ACR is a way to ensure that the number of programmed wait states is effective.

Increasing the CPU frequency (in the same voltage range)

Program 1 wait state in LATENCY bit of FLASH_ACR register, if necessary.

2. Check that the new number of wait states is taken into account by reading the

FLASH_ACR register. When the number of wait states changes, the memory interface modifies the way the read access is done to the NVM. The number of wait states cannot be modified when a read operation is ongoing, so the memory interface waits until no read is done on the NVM. If the master reads back the content of the

FLASH_ACR register, this reading is stopped (and also the master which requested the reading) until the number of wait states is really changed. If the user does not read back the register, the following access to the NVM may be done with 0 wait states, even if the clock frequency has been increased, and consequently the values are wrong.

3. Modify the CPU clock source and/or the AHB clock prescaler in the Reset & Clock

Controller (RCC).

4. Check that the new CPU clock source and/or the new CPU clock prescaler value is taken into account by reading respectively the clock source status and/or the AHB prescaler value in the Reset & Clock Controller (RCC). This check is important as some clocks may take time to get available.

For code example, refer to

A.2.1: Increasing the CPU frequency preparation sequence code

, A.2.3: Switch from PLL to HSI16 sequence code and A.2.3: Switch from PLL to HSI16 sequence code .

Decreasing the CPU frequency (in the same voltage range)

Modify the CPU clock source and/or the AHB clock prescaler in the Reset & Clock

Controller (RCC).

2. Check that the new CPU clock source and/or the new CPU clock prescaler value is taken into account by reading respectively the clock source status and/or the AHB prescaler value in the Reset and Clock Controller (RCC).

3. Program 0 wait state in LATENCY bit of the FLASH_ACR register, if needed.

4. Check that the new number of wait states is taken into account by reading

FLASH_ACR. It is necessary to read back the register for the reasons explained in the previous paragraph.

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Data buffering

In the NVM, six buffers can impact the performance (and in some conditions help to reduce the power consumption) during read operations, both for fetch and data. The structure of one buffer is shown on

Figure 3 .

Figure 3. Structure of one internal buffer

Address

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History

MS32395V1

Each buffer stores 3 different types of information: address, data and history. In a read operation, if the address is found, the memory interface can return data without accessing the NVM. Data in the buffer is 32 bit wide (even if the master only reads 8 or 16 bits), so that a value can be returned whatever the size used in a previous reading. The history is used to know if the content of a buffer is valid and to delete (with a new value) the older one.

The buffers are used to store the value received by the NVM during normal read operations, and for speculative readings. Disabling the speculative reading makes that only the data requested by masters is stored in buffers, if enabled (default). This can increase the performance as no wait state is necessary if the value is already available in buffers, and reduce the power consumption as the number of reads in memory is reduced and all combinatorial paths from memory are stable.

The buffers are divided in groups to manage different tasks. The number of buffers in every

group can change starting from the configuration selected by the user (see Table 12

). The total number of buffers used is always 6 (if enabled). The history is always managed by group.

The memory interface always searches if a particular address is available in all buffers without checking the group of buffers and if the read is fetch or data.

At reset or after a write/erase operation that changes several addresses, all buffers are empty and the history is set to EMPTY. After a program by word, half-word or byte, only the buffer with the concerned address is cleaned.

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Table 12. Internal buffer management

Buffers for fetch

DISAB_BUF PREFTEN PRE_READ

Buffers for jumps

Buffers for prefetch

Buffers for last value

Buffers for data

Buffers for pre-read

Buffers for last value

If a value in a buffer is not empty, the history shows the time elapsed between the moment it has been read or written. The history is organized as a list of values from the latest to the oldest one. At a given instant, only one buffer in a group can have a particular value of history (except the empty value). Moving a buffer to the latest position, all other buffers in the group move one step further, thus maintaining the order. The history is changed to the latest position when the buffer is read (the master requests for the buffer content) or written

(with a new value from the NVM). The memory interface always writes the oldest buffer (or one empty buffer, if any) of the right group when a new address is required in memory.

Three configuration bits of the FLASH_ACR register are used to manage the buffering:

• DISAB_BUF

Setting this bit disables all buffers. When this bit is 1, the prefetch or the pre-read operations cannot be enabled and if, for example, the master requests the same address twice, two readings are generated in the NVM.

• PRFTEN

Setting this bit to 1 (with DISAB_BUF to 0) enables the prefetch. When the memory interface does not have any operation in progress, the address following the last address fetched is read and stored in a buffer.

• PRE_READ

Setting this bit to 1 (with DISAB_BUF to 0) enables the pre-read. When the memory interface does not have any operation in progress or prefetch to execute, the address following the last data address is read and stored in a buffer.

Fetch and prefetch

A memory interface fetch is a read from the NVM to execute the operation that has been read. The memory interface does not check the master who performs the read operation, or the location it reads from, but it only verifies if the read operation is done to execute what has been read. It means that a fetch can be performed:

• in all areas,

• with any size (16 or 32 bits).

The memory interface stores in the buffers:

• The address of jumps so that, in a loop, it is only necessary to access the NVM the first time, because then the jump address is already available.

• The last read address so that, when performing a fetching on 16 bits, the other 16 bits are already available.

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To manage the fetch, the memory interface uses 4 buffers: at reset (DISAB_BUF = 0,

PRFTEN = 0, PRE_READ = 0). 3 buffers are used to manage the jumps and 1 buffer to store the last value fetched. With this configuration, the 4 buffers for fetch are organized in 2 groups with separate histories: the group for loops and the group for the last value fetched.

Setting the PRFTEN bit to 1 enables the prefetch. The prefetch is a speculative read in the

NVM, which is executed when no read is requested by masters, and where the memory interface reads from the last address fetched increased by 4 (one word). This read is with a lower priority and it is aborted if a master requests a read (data or fetch) to a different address than the prefetch one. When the prefetch is enabled, one buffer for loops is moved to a new group (of only one buffer) to store the prefetched value: 2 buffers continue to store the jumps, 1 buffer is used for prefetch and 1 buffer is used for the last value.

The memory interface can only prefetch one address, so the function is temporarily disabled when no fetch is done and the prefetch is already completed. After a prefetch, if the master requests the prefetched value, the content of the prefetch buffer is copied to the last value buffer and a new prefetch is enabled. If, instead, the master requests a different address, the content of the prefetch buffer is lost, a read in the NVM is started (if necessary) and, when it is complete, a new prefetch is enabled at the new address fetched increased by 4.

The prefetch can only increase the performance when reading with 1 wait state and for mostly linear codes: the user must evaluate the pros and cons to enable or not the prefetch in every situation. The prefetch increases the consumption because many more readings are done in the NVM (and not all of them will be used by the master). To see the advantages of prefetch on Dhrystone code, refer to the Dhrystone performances section.

Figure 4 shows the timing to fetch a linear code in the NVM when the prefetch is disabled,

both for 0 wait state (a) and 1 wait state (b). You can compare these two sequences with the ones in

Figure 5

, when the prefetch is enabled, to have an idea of the advantages of a prefetch on a linear code with 0 and 1 wait states.

cycle

Figure 4. Timing to fetch and execute instructions with prefetch disabled cycle

2 cycle

3 cycle

4 cycle

5 cycle

6 cycle

7 cycle

8 cycle

9 cycle

10 cycle

Addr

1 & 2

Fetch

1 & 2

Exec.

Addr

3 & 4

Exec.

Fetch

3 & 4

Exec.

Addr

5 & 6

Exec.

Fetch

5 & 6

Exec.

(a)

Addr

1 & 2

Fetch

1 & 2

Wait

Exec.

Addr

3 & 4

Exec.

Fetch

3 & 4

Wait

(b)

Exec.

Addr

5 & 6

Exec.

Fetch

5 & 6

Wait

Exec.

MS32396V1

1. (a) corresponds to 0 wait state.

2. (b) corresponds to 1 wait state.

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Figure 5 shows the timing to fetch and execute instructions from the NVM with 0 wait states

(a) and 1 wait state (b) when the prefetch is enabled. The read executed by the prefetch appears in green.

Read as data and pre-read

A data read from the memory interface, corresponds to any read operation that is not a fetch. The master reads operation constants and parameters as data. All reads done by

DMA (to copy from one address to another) are read as data. No check is done on the location of the data read (can be in every area of the NVM).

At reset, (DISAB_BUF = 0, PRFTEN = 0, PRE_READ = 0), the memory interface uses 2 buffers organized in one group to store the last two values read as data.

In some particular cases (for example when the DMA is reading a lot of consecutive words in the NVM), it can be useful to enable the pre-read (PRE_READ = 1 with DISAB_BUF = 0).

The pre-read works exactly like the prefetch: it is a speculative reading at the last data address increased by 4 (one word). With this configuration, one buffer of data is moved to a new group to store the pre-read value, while the second buffer continues to store the last value read. For a prefetch, the pre-read value is copied in the last read value if the master requests it, or is lost if the master requests a different address.

The pre-read has a lower priority than a normal read or a prefetch operation: this means that it will be launched only when no other type of read is ongoing. Pay attention to the fact that a pre-read used in a wrong situation can be harmful: in a code where a data read is not done linearly, reducing the number of buffers (from 2 to 1) used for the last read value can increase the number of accesses to the NVM (and the time to read the value). Moreover, this can generate a delay on prefetch. An example of this situation is the code Dhrystone, whose results are shown in the corresponding section.

As for a prefetch operation, the user must select the right moment to enable and disable the pre-read.

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Figure 5. Timing to fetch and execute instructions with prefetch enabled cycle

Addr

1 & 2 cycle

Fetch

1 & 2

Addr

3 & 4 cycle

Exec.

Addr

3 & 4

Read

3 & 4 cycle

Exec.

Fetch

3 & 4

Addr

5 & 6 cycle

5 cycle

Exec.

Addr

5 & 6

Read

5 & 6

Exec.

Fetch

5 & 6 cycle

7 cycle

Exec.

6 cycle

(a)

Addr

1 & 2

Fetch

1 & 2

Wait

Addr

3 & 4

Exec.

Addr

3 & 4

Read

3 & 4

Exec.

Fetch

3 & 4

Wait

Addr

5 & 6

Exec.

Addr

5 & 6

Read

5 & 6

Exec.

Fetch

5 & 6

Wait

(b)

Exec.

MS32397V1

Table 13 is a summary of the possible configurations.

Table 13. Configurations for buffers and speculative reading

DISAB_BUF PRFTEN PRE_READ Description

Buffers disabled

Buffer enabled: no speculative reading is done

Prefetch enabled: speculative reading on fetch enabled pre-read enabled: speculative reading on data enabled

Prefetch and pre-read enabled: speculative reading on fetch and data enabled

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Dhrystone performances

The Dhrystone test is used to evaluate the memory interface performances. The test has been executed in all memory interface configurations. Refer to

Table 14 for a summary of

the results.

Common parameters are:

• the matrix size is 20 x 20

• the loop is executed 1757 times

• the version of Arm

compiler is 4.1 [Build 561]

Here is some explanation about the results:

Table 14. Dhrystone performances in all memory interface configurations

Number of wait states

DISAB_BUF PRFTEN PRE_READ

Number of

DMIPS (x1000)

DMIPS x MHz

677

690

823

691

816

953

21.66

22.08

26.34

22.11

26.11

15.25

• The pre-read is not useful for this test: when enabled with the prefetch, it reduces the memory interface performance because only one buffer is used to store the last data read and, in this code, the master rarely reads the data linearly. This justifies the very small increase of performance when enabled without a prefetch.

• The buffers (without speculative readings) with 1 wait state give a little advantage that can be considered without any costs.

• At a 0 wait state, the best performance (as certified by Arm ® code alignment during the compilation.

) may be due to a different

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There are many ways to change the NVM content. The memory interface helps to reduce the possibility of unwanted changes and to implement by hardware all sequences necessary to erase or write in the different memory areas.

Write/erase protocol

To write/erase memory content when the protections have been removed, the user needs to:

configure the operation to execute,

2. send to the memory interface the right number of data, writing one or several addresses in the NVM,

3. wait for the operation to complete.

During the waiting time, the user can prepare the next operation (except in very particular cases) writing the new configuration and starting to write data for the next write/erase operation.

The waiting time depends on the type of operation. A write/erase can last from Tprog (3.2 ms) to 2 x Tglob (3.7 ms) + Tprog (3.2 ms). The memory interface can be configured to write a half-page (16 words in the Flash program memory) with only one waiting time. This can reduce the time to program a big amount of data.

Two different protocols can be used: single programming and multiple programming operation.

Single programming operation

With this protocol, the software has to write a value in a not-protected address of the NVM.

When the memory interface receives this writing request, it stalls the master for some

pulses of clock (for more details, see Table 15

) while it checks the protections and the previous value and it latches the new value inside the NVM. The software can then start to configure the next operation. The operation will complete when the EOP bit of FLASH_SR register rises (if it was 0 at the operation start). The operation time is resumed in

Table 17

for all operations.

Multiple programming operation (half page)

You can write a half-page (16 words) in Flash program memory, To execute this protocol, follow the next conditions:

• PGAERR bit in the FLASH_SR register has to be zero (no previous alignment errors).

• The first address has to be half-page aligned (the 6 lower bits of the address have to be at zero).

• All 16 words must be in the same half-page (address bits 7 to 31 must be the same for all 16 words). This means that the first address sets the half-page and the next ones must be inside this half-page. The written data will be stored sequentially in the next addresses. It is not important that the addresses increase or change (for example, the same address can be used 16 times), as the memory interface will automatically increase the address internally.

• Only words (32 bits) can be written.

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When the memory interface receives the first address, it stalls the master for some pulses of clock while it checks the protections and the previous value and it latches the new value inside the NVM (for more details, see

Table 15 ). Then, the memory interface waits for the

second address. No read is accepted: only a fetch will be executed, but it aborts the ongoing write operation. After the second address, the memory interface stalls the core for a short time (less than the previous one) to perform a check and to latch it in the NVM before waiting for the next one. This sequence continues until all 16 words have been latched inside the NVM. A wrong alignment or size will abort the write operation. If the 16 addresses are correctly latched, the memory interface starts the write operation. The operation will complete when EOP bit of FLASH_SR register rises (if it was 0 at the operation start). The

operation time is resumed in Table 17

This protocol can be used either through application code running from RAM or through

DMA with application code running from RAM or core sleeping.

Unlocking/locking operations

Before performing a write/erase operation, it is necessary to enable it. The user can write into the Flash program memory, data EEPROM and Option bytes areas.

To perform a write/erase operation, unlock PELOCK bit of the FLASH_PECR register. When this bit is unlocked (its value is 0), the other bits of the same register can be modified. When

PELOCK is 0, the write/erase operations can be executed in the data EEPROM.

To write/erase the Flash program memory, unlock PRGLOCK bit of the FLASH_PECR register. The bit can only be unlocked when PELOCK is 0.

To write/erase the user Option bytes, unlock OPTLOCK bit of the FLASH_PECR register.

The bit can only be unlocked when PELOCK is 0. No relation exists between PRGLOCK and OPTLOCK: the first one can be unlocked when the second one is locked and vice versa.

Unlocking the data EEPROM and the FLASH_PECR register

After a reset, the data EEPROM and the FLASH_PECR register are not accessible in write mode because PELOCK bit in the FLASH_PECR register is set. The same unlocking sequence unprotects both of them at the same time.

The following sequence is used to unlock the data EEPROM and the FLASH_PECR register:

• Write PEKEY1 = 0x89ABCDEF to the FLASH_PEKEYR register

• Write PEKEY2 = 0x02030405 to the FLASH_PEKEYR register

For code example, refer to

A.3.1: Unlocking the data EEPROM and FLASH_PECR register code example

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Any wrong key sequence will lock up FLASH_PECR until the next reset and generate a hard fault. Idem if the master tries to write another register between the two key sequences or if it uses the wrong key. A reading access does not generate an error and does not interrupt the sequence. A hard fault is returned in any of the four cases below:

• After the first write access if the PEKEY1 value entered is erroneous.

• During the second write access if PEKEY1 is correctly entered but the value of

PEKEY2 does not match.

• If there is any attempt to write a third value to PEKEYR (pay attention: this is also true for the debugger).

• If there is any attempt to write a different register of the memory interface between

PEKEY1 and PEKEY2.

When properly executed, the unlocking sequence clears PELOCK bit in the FLASH_PECR register.

To lock FLASH_PECR and the data EEPROM again, the software only needs to set

PELOCK bit in FLASH_PECR. When locked again, PELOCK bit needs a new sequence to return to 0.

For code example, refer to

A.3.2: Locking data EEPROM and FLASH_PECR register code example .

Unlocking the Flash program memory

An additional protection is implemented to write/erase the Flash program memory.

After a reset, the Flash program memory is no more accessible in write mode: PRGLOCK bit is set in the FLASH_PECR register. A write access to the Flash program memory is granted by clearing PRGLOCK bit.

The following sequence is used to unlock the Flash program memory:

• Unlock the FLASH_PECR register (see the Unlocking the data EEPROM and the

FLASH_PECR register section).

• Write PRGKEY1 = 0x8C9DAEBF to the FLASH_PRGKEYR register.

• Write PRGKEY2 = 0x13141516 to the FLASH_PRGKEYR register.

For code example, refer to

A.3.3: Unlocking the NVM program memory code example

If the keys are written with PELOCK set to 1, no error is generated and PRGLOCK remains at 1. It will be unlocked while re-executing the sequence with PELOCK = 0.

Any wrong key sequence will lock up PRGLOCK in FLASH_PECR until the next reset, and return a hard fault. A hard fault is returned in any of the four cases below:

• After the first write access if the entered PRGKEY1 value is erroneous.

• During the second write access if PRGKEY1 is correctly entered but the PRGKEY2 value does not match.

• If there is any attempt to write a third value to PRGKEYR (this is also true for the debugger).

• If there is any attempt to write a different register of the memory interface between

PRGKEY1 and PRGKEY2.

When properly executed, the unlocking sequence clears the PRGLOCK bit and the Flash program memory is write-accessible.

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To lock the Flash program memory again, the software only needs to set PRGLOCK bit in

FLASH_PECR. When locked again, PRGLOCK bit needs a new sequence to return to 0. If

PELOCK returns to 1 (locked), PRGLOCK is automatically locked, too.

Unlocking the Option bytes area

An additional write protection is implemented on the Option bytes area. It is necessary to unlock OPTLOCK to reload or write/erase the Option bytes area.

After a reset, the Option bytes area is not accessible in write mode: OPTLOCK bit in the

FLASH_PECR register is set. A write access to the Option bytes area is granted by clearing

OPTLOCK.

The following sequence is used to unlock the Option bytes area:

Unlock the FLASH_PECR register (see the Unlocking the data EEPROM and the

FLASH_PECR register section).

2. Write OPTKEY1 = 0xFBEAD9C8 to the FLASH_OPTKEYR register.

OPTKEY2 0x24252627 to the FLASH_OPTKEYR register.

For code example, refer to

A.3.4: Unlocking the option bytes area code example .

If the keys are written with PELOCK = 1, no error is generated, OPTLOCK remains at 1 and it will be unlocked when re-executing the sequence with PELOCK to 0.

Any wrong key sequence will lock up OPTLOCK in FLASH_PECR until the next reset, and return a hard fault. A hard fault is returned in any of the four cases below:

• After the first write access if the OPTKEY1 value entered is erroneous.

• During the second write access if OPTKEY1 is correctly entered but the OPTKEY2 value does not match.

• If there is any attempt to write a third value to OPTKEYR (this is also true for the debugger).

• If there is any attempt to write a different register of the memory interface between

OPTKEY1 and OPTKEY2.

When properly executed, the unlocking sequence clears the OPTLOCK bit and the Option bytes area is write-accessible.

To lock the Option bytes area again, the software only needs to set OPTLOCK bit in

FLASH_PECR. When relocked, OPTLOCK bit needs a new sequence to return to 0. If

PELOCK returns to 1 (locked), OPTLOCK is automatically locked, too.

Select between different types of operations

When the necessary unlock sequence has been executed (PELOCK, PRGLOCK and

OPTLOCK), the user can enable different types of write and erase operations, writing the right configuration in the FLASH_PECR register. The bits involved are:

• PRG

• DATA

• FIX

• ERASE

• FPRG

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Detailed description of NVM write/erase operations

This section details the different types of write and erase operations, showing the necessary bits for each one.

Write to data EEPROM

• Purpose

Write one word in the data EEPROM with a specific value.

• Size

Write by byte, half-word or word.

• Address

Select a valid address in the data EEPROM.

• Protocol

Single programming operation.

• Requests

PELOCK = 0, ERASE = 0.

• Errors

WRPERR is set to 1 (and the write operation is not executed) if PELOCK = 1 or if the memory is read-out protected.

• Description

This operation aims at writing a word or a part of a word in the data EEPROM. The user must write the right value at the right address and with the right size. The memory interface automatically executes an erase operation when necessary (if all bits are currently set to 0, there is no need to delete the old content before writing). Similarly, if the data to write is at 0, only the erase operation is executed. When only a write operation or an erase operation is executed, the duration is Tprog (3.2 ms); if both are executed, the duration is 2 x Tprog (6.4 ms). It is possible to force the memory interface to execute every time both erase and write operations set the FIX flag to 1.

• Duration

Tprog (3.2 ms) or 2 x Tprog (6.4 ms).

• Options

Set the FIX bit to force the memory interface to execute every time an erase (to delete the old content) and a write operation (to write new data) occur. This gives a fix time for the operation for any data value and for previous data.

• Erase/write endurance cycles in data EEPROM are linked to one single word granularity (one erase/write cycle degrades only one programmed word area in data

EEPROM).

For code example, refer to

A.3.5: Write to data EEPROM code example .

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Erase data EEPROM

• Purpose

Delete one row in data EEPROM. This operation performs the same function as Write a word which size is null to data EEPROM. It is available for compatibility purpose only.

• Size

Erase only by word.

• Address

Select one valid address in the data EEPROM.

• Protocol

Single programming operation.

• Requests

PELOCK = 0, ERASE = 1 (optional DATA = 1).

• Errors

WRPERR is set to 1 if PELOCK = 1 or if the memory is read-out protected.

SIZERR is set to 1 if the size is not a word.

• Description

This operation aims at deleting the content of a row in the data EEPROM. A row contains only 1 word. The user must write a value at the right address with a word size.

The data is not important: only an erase is executed (also with data different from zero).

• Duration

Tprog (3.2 ms).

For code example, refer to

A.3.6: Erase to data EEPROM code example

Write Option bytes

• Purpose

Write one word in the Option bytes area with a specific value.

• Size

Write only by word.

• Address

Select a valid address in the Option bytes area.

• Protocol

Single programming operation.

• Requests

PELOCK = 0, OPTLOCK = 0, ERASE = 0.

• Errors

WRPERR is set to 1 if PELOCK = 1 or OPTLOCK = 1.

WRPERR is set to 1 if the actual read-out protection level is 2 (the Option bytes area cannot be written at Level 2).

SIZERR is set to 1 if the size is not the word

• Description

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This operation aims at writing a word in the Option bytes area. The Option bytes area can only be written in Level 0 or Level 1.

The user must consider that, in a word, the 16 higher bits (from 16 to 31) have to be the complement of the 16 lower bits (from 0 to 15): a mismatch between the higher and lower parts of data would generate an error during the Option bytes loading (see

Section 3.8: Option bytes

) and force the memory interface to load the default values.

The memory interface does not check at the write time if the data is correctly complemented. The user must write the desired value at the right address with a word size.

As for data EEPROM, the memory interface deletes the previous content before writing, if necessary. If the data to write is at 0, the memory interface does not execute the useless write operation. When only a write operation or only an erase operation is executed, the duration is Tprog (3.2 ms). If both are executed, the duration is 2 x Tprog

(6.4 ms). The memory interface can be forced to execute every time both erase and write operations set the FIX flag to 1.

Some configurations need a closer attention because they change the protections. The memory interface can change the Option bytes write in a Mass Erase or force some bits not to reduce the protections: for more details, see

Section 3.4.4: Write/erase protection management

• Duration

Tprog (3.2 ms) or 2 x Tprog (6.4 ms).

• Options

FIX bit can be set to force the memory interface to execute every time an erase (to delete the old content) and a write operation (to write the new data) occur. This gives a fix time to program for every data value and for previous data.

For code example, refer to

A.3.7: Program Option byte code example

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Erase Option bytes

• Purpose

Delete one row in the Option bytes area. This operation performs the same function as

Write Option Byte with a zero value. It is available for compatibility purpose only.

• Size

Erase only by word.

• Address

Select a valid address in the Option bytes area.

• Protocol

Single programming operation.

• Requests

PELOCK = 0, OPTLOCK = 0, ERASE = 1 (optional OPT = 1).

• Errors

WRPERR is set to 1 if PELOCK = 1 or OPTLOCK = 1.

WRPERR is set to 1 if the actual protection level is 2 (the Option bytes area cannot be erased at Level 2).

SIZERR is set to 1 if the size is not the word.

• Description

This operation aims at deleting the content of a row in the Option bytes area. A row contains only 1 word. The use must write zero at the right address with a word size.

Refer to Section : Write Option bytes

for additional information.

Since all bits are set to 0 after an erase operation, there will be a mismatch during the

Option bytes loading and the default values will be loaded.

• Duration

Tprog (3.2 ms).

For code example, refer to

A.3.8: Erase Option byte code example .

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Program a single word to Flash program memory

• Purpose

Write one word in the Flash program memory with a specific value.

• Size

Write only by word.

• Address

Select an address in the Flash program memory.

• Protocol

Single programming operation.

• Requests

PELOCK = 0, PRGLOCK = 0.

• Errors

WRPERR is set to 1 if PELOCK = 1 or PRGLOCK = 1.

WRPERR is set to 1 if the user tries to write in a write-protected sector (see the

PcROP

(Proprietary Code Read-Out Protection) section).

NOTZEROERR is set to 1 if the user tries to write a value in a word which is not zero.

This error does not stop the write operation on category 3 devices while the operation is stopped on other categories.

SIZERR is set to 1 if the size is not a word.

• Description

This operation allows writing a word in Flash program memory. The user must write the right value at the right address with a word size. The memory interface cannot execute an erase to delete the previous content before the write operation is performed.

If the previous content is not null:

– Category 3 devices

NOTZEROERR is set to 1.

The real value written in the memory is the OR of the previous value and the new value (the memory interface writes 1 when there was 0 before). This is done both for data and ECC. Reading back the data might not return the old value, the new one or the ORed values. The ECC is not compatible with the data any more.

– Other categories

NOTZEROERR is set to 1. Writing a word to an address containing a non-null value is not performed.

• Duration

Tprog (3.2 ms).

• The erase/write endurance cycles in Flash program memory are linked to one page granularity (one erase/write cycle will degrade one programmed page in word area in

Flash program memory).

For code example, refer to

A.3.9: Program a single word to Flash program memory code example .

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Program half-page in Flash program memory

• Purpose

Write one half page (16 words) in the Flash program memory.

• Size

Write only by word.

• Address

Select one address in the Flash program memory aligned to a half-page (for the first address) and inside the same half-page selected by the second address for the next 15 addresses.

• Protocol

Multiple programming operation.

• Requests

PELOCK = 0, PRGLOCK = 0, FPRG = 1, PRG = 1.

• Errors

WRPERR is set to 1 if PELOCK = 1 or PRGLOCK = 1. WRPERR is set to 1 if the user tries to write in a write-protected sector (see the

PcROP (Proprietary Code Read-Out

Protection)

section).

NOTZEROERR is set to 1 if the user tries to write a value in a word which is not zero.

This error does not stop the write operation on category 3 devices while the operation is stopped on other categories. The check is done when all 16 addresses have been received, before the current write phase in Flash memory. The error flags are set only when all checks are performed.

SIZERR is set to 1 if the size is not the word.

PGAERR is set to 1 if the first address is not aligned to a half-page and if one of the following addresses (address from 2 to 16) is outside the half-page determined by the first address. No check is done to verify if the address has increased or if it has changed: this is done automatically by the memory interface. What is important is that the first address is aligned to the half-page, and that the next addresses are in the same half-page.

FWWERR is set to 1 if the write is aborted because the master fetched in the NVM.

The read as data does not stop the write operation.

• Description

This operation allows writing a half-page in Flash program memory. The user must write the 16 desired values at the right address with a word size (as explained in the multiple programming operation). The memory interface cannot execute an erase to delete the previous content before writing (the user must delete the page before writing).

As for the single programming operation, if the previous content is not null:

– Category 3 devices

NOTZEROERR is set to 1.

The written value is the OR of previous and new data. This means that reading back the written address may return a value which is different from the written one.

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– Other categories

NOTZEROERR is set to 1. Writing a word to an address containing a non-null value is not performed.

When a half-page operation starts, the memory interface waits for 16 addresses/data, aborting (with a hard fault) all read accesses that are not a fetch (refer to Fetch and prefetch ). A fetch stops the half-page operation. The memory content remains unchanged, the FWWERR error is set in the FLASH_SR register. To complete the halfpage programming operation, all the desired values should be written again.

• Duration

Tprog (3.2 ms).

For code example, refer to

A.3.10: Program half-page to Flash program memory code example .

Erase a page in Flash program memory

• Purpose

Delete one page (32 words) in the Flash program memory.

• Size

Erase only by word (it deletes a page of the Flash program memory writing with a word size)

• Address

Select a valid address in the Flash program memory.

• Protocol

Single programming operation.

• Requests

PELOCK = 0, PRGLOCK = 0, ERASE = 1, PRG = 1.

• Errors

WRPERR is set to 1 if PELOCK = 1 or PRGLOCK = 1.

WRPERR is set to 1 if the row is in a protected sector (see PcROP (Proprietary Code

Read-Out Protection)

SIZERR is set to 1 if the size is not the word.

• Description

This operation aims at deleting the content of a row in the Flash program memory. The user must write a value in the right address with a word size. The data is not important: only an erase is executed (also with data not at zero). The address does not need to be aligned to the page: the memory interface will delete the page which contents the address.

• Duration

Tprog (3.2 ms).

For code example, refer to

A.3.11: Erase a page in Flash program memory code example

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Mass erase

• Purpose

Remove the read and write protection on the Flash program memory and data

EEPROM.

• Size

Erase only by word.

• Address

To generate a mass erase, it is necessary to write 0x015500AA to the first Option bytes address (bits 31 to 25 and 15 to 9 are not complemented because they are not used, and not checked) with Level 1 as the actual level.

• Protocol

Single programming operation.

• Requests

PELOCK = 0, OPTLOCK = 0, Protection Level = 1, the lower nibble of data has to be

0xAA (Level 0), with 0x55 as the third nibble.

• Errors

WRPERR is set to 1 if PELOCK = 1 or OPTLOCK = 1.

WRPERR is set to 1 if the actual protection level is 2 (the Option bytes area cannot be written in Level 2).

SIZERR is set to 1 if the size is not the word.

• Description

This operation is similar to the write user Option byte operation: the memory interface changes it in a mass erase when the actual Protection Level is 1 and the requested

Protection Level is 0. The user must write the desired value in the first address of the

Option bytes area with a word size.

A mass erase deletes the content of the Flash program memory and data EEPROM, changes the protection level to Level 0 and disables PcROP. (WPRMOD = 0). The bits write protection and BOR_LEVEL remain unchanged.

Unlike all other operations, the software cannot request new writing operations while a mass erase is ongoing. To be sure that a mass erase has completed, the software can reset the EOP bit of FLASH_SR register before the write operation and check when

EOP goes to 1 (End Of Program). If this limitation is not respected, a wrong value may be written in the Flash program memory and data EEPROM when the Protection Level is written, thus adding unwanted protections (also for mismatch) that could make the device useless.

• Duration

2 x Tprog (6.4 ms) + Tglob (3.7 ms)

For code example, refer to

A.3.12: Mass erase code example .

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Timing tables

Operation

Write to data EEPROM

Erase data EEPROM

Write Option bytes

Erase Option bytes

Program a single word in Flash program memory

Program half-page in Flash program memory

Erase a page in Flash program memory

Table 15. NVM write/erase timings

Delay to latch the first address/data

(in AHB clock pulses)

Delay to latch the next address/data

(in AHB clock pulses)

76 -

Operation

Write to data EEPROM

Erase data EEPROM

Write Option bytes

Erase Option bytes

Program a single word in

Flash program memory

Program a half-page in

Flash program memory

Erase a page in Flash program memory

Mass erase

Table 16. NVM write/erase duration

Parameters/Conditions

Previous data = 0

FIX = 0

Previous data /= 0

New data = 0

Size = word

FIX = 0

Other situations

Previous data = 0

FIX = 0

Previous data /= 0

New data = 0

FIX = 0

Other situations

Duration

Tprog (3.2 ms)

2 x Tprog (6.4 ms)

Tprog (3.2 ms)

2 x Tprog (6.4 ms)

Tprog (3.2 ms)

2 x Tprog (6.4 ms) + Tglob (3.7 ms)

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Status register

The FLASH_SR Status Register gives some information on the memory interface or the

NVM status (operation(s) ongoing) and about errors that happened.

BSY

This flags is set and reset by hardware. It is set to 1 every time the memory interface executes a write/erase operation, and it informs that no other operation can be executed. If a new operation is requested, different behaviors can occur:

• Waiting for read, or waiting for write/erase, or waiting for option loading:

If the software requests a write operation while a write/erase operation is executing

(HVOFF = 0), the memory interface stalls the master and has the pending operation execute as soon as the write/erase operation is complete.

• Hard fault:

If the software requests a data read in a half-page operation when the memory interface is waiting for the next address/data (BSY is already 1 but HVOFF = 0), the memory interface generates a hard fault (because it cannot execute the read) and continues to wait for missing addresses.

• RDERR error:

If the software requests a read operation while a write/erase operation is executing

(HVOFF = 0) but the address is protected, the memory interface rises the flag and continues to wait for the end of the write/erase operation.

• Write abort:

If the software fetches in the NVM when the memory interface is waiting for an address/data in a half-page operation, the write/erase operation is aborted, the

FWWERR flag is raised and the fetch is executed.

EOP

This flag is set by hardware and reset by software. The software can reset it writing 1 in the status register. This bit is set when the write/erase operation is completed and the memory interface can work on other operations (or start to work on pending operations).

It is useful to clear it before starting a new write/erase operation, in order to know when the actual operation is complete. It is very important to wait for this flag to rise when a mass erase is ongoing, before requesting a new operation.

HVOFF

This flag is set and reset by hardware and it is a memory interface information copy coming from the NVM: it informs when the High-Voltage Regulators are on (= 0) or off (= 1).

PGAERR

This flag is set by hardware and reset by software. It informs when an alignment error happened. It is raised when:

• The first address in a half-page operation is not aligned to a half-page (lower 6 bits equal to zero).

• A half-page change happened in a half-page operation (the addresses from 2 to 16 in a half-page operation are not in the same half-page, selected by the first address).

An alignment error aborts the write/erase operation and an interrupt can be generated (if

ERRIE = 1 in the FLASH_PECR register). The content of the NVM is not changed.

If this flag is set, the memory interface blocks all other half-page operations.

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Note:

RM0451

To reset this flag, the software need to write it to 1.

SIZERR

This flag is set by hardware and reset by software. It informs when a size error happened. It is raised when:

• A write by byte and half-word occurs in the Flash program memory and Option bytes.

• An erase (with bit ERASE = 1 in FLASH_PECR register) by byte or half-word occurs in all areas.

A size error aborts the write/erase operation and an interrupt can be generated (if

ERRIE = 1 in the FLASH_PECR register). The content of the NVM is not changed.

To reset this flag, the software needs to write it to 1.

NOTZEROERR

This flag is set by hardware and reset by software. It indicates that the application software is attempting to write to one or more NVM addresses that contain a non-zero value.

Except for category 3 devices, the modify operation is always aborted when this condition is met. For category 3 devices, a not-zero error does not abort the write/erase operation but the value might be corrupted.

In a write by half-page, all 16 words are checked between the first address/value and the second one, and the flag is only set when all words are checked. If the flag is set, it means that at least one word has an actual value not at zero.

In a write by word, only the targeted word is checked and the flag is immediately set if the content is not zero.

An interrupt is generated if ERRIE = 1 in FLASH_PECR register. To reset this flag, the application software needs to program it to 1.

Notification of a not-zero error condition (i.e. NOTZEROERR flag and the associated interrupt) can be disabled by the application software via the NZDISABLE bit in

FLASH_PECR register. However, for all device except category 3 devices, the condition is still checked internally and modify operation is anyway blocked

Note:

The user can protect part of the NVM (Flash program memory, data EEPROM and Option bytes areas) from unwanted write and against code hacking (unwanted read).

The read protection is activated by setting the RDP option byte and then applying a system reset to reload the new RDP option byte.

If the read protection is set while the debugger has been active (through SWD) after last

POR (power-on reset), apply a POR (power-on reset) or wakeup from Standby mode instead of a system reset (the option bytes loading is not sufficient).

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3.4.1

Note:

Flash program memory and data EEPROM (FLASH)

Three types of protections are implemented.

RDP (Read Out Protection)

This type of protection aims at protecting against unwanted read (hacking) of the NVM content. This protection is managed by RDPROT bitfield in the FLASH_OPTR register. The value is loaded from the Option bytes area during a boot and copied in the read-only register.

Three protection levels are defined:

• Level 0: no protection

Level 0 is set when RDPROT is set to 0xAA. When this level is enabled, and if no other protection is enabled, read and write can be done in the Flash program memory, data

EEPROM and Option bytes areas without restrictions. It is also possible to read and write the backup registers freely.

• Level 1: memory read protection

Level 1 is set when RDPROT is set to any value except 0xAA and 0xCC, respectively used for Level 0 and Level 2. This is the default protection level after an Option bytes erase or when there is a mismatch in the RDPROT field.

Level 1 protects the Flash program memory and data EEPROM. When protection Level

1 is set through boot from RAM, bootloader or debugger, a power-down or a standby is required to execute the user code.

When this level is enabled:

– No access to the Flash program memory and data EEPROM (read both for fetch and data and write) and no backup register reading is performed if the debug features (single-wire), or the device boot in the RAM, or the System memory is connected. If the user tries to read the Flash memory or data EEPROM, a hard fault is generated. No restriction is present on other areas: it is possible to read and write/erase the Option bytes area and to execute or read in the System

Memory.

– All operations are possible when the boot is done in the Flash program memory.

– Writing the first Option byte with a value that changes the protection level to Level

0 (it is necessary that byte 0 is 0xAA and byte 2 is 0x55), a mass erase is generated. The mass erase deletes the Flash program memory and data

EEPROM, deletes the first Option byte and then rewrites it to enable Level 0 and disable PCROP (WPRMOD = 0), and deletes the backup registers content.

• Level 2: disable debug and chip read protection

Level 2 is set when RDPROT is set to 0xCC. When this level is enabled, it is only possible to boot from the Flash program memory, and the debug features (single-wire) are disabled. The Option bytes are protected against write/erase and the protection level can no longer be changed. The application can write/erase to the Flash program memory and data EEPROM (it is only possible to boot from the Flash program memory and execute the customer code) and access the backup registers. When an Option bytes loading is executed and Level 2 is enabled, old information on debug or boot in the RAM or System memory are deleted.

The debug feature is also disabled under reset. STMicroelectronics is not able to perform analysis on defective parts on which level 2 protection has been set.

Figure 6 resumes the way the protection level can be changed and Table 17 the link

between the values read in the Option bytes and the protection level.

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Figure 6. RDP levels

Write

RDP = 0xCC

Level 2

RDP = 0xCC

RM0451

Level 1

RDP /= 0xAA

RDP /= 0xCC

(default)

Write

RDP /= 0xAA and

RDP /= 0xCC

Write

RDP /= 0xCC and

RDP /= 0xAA

Write

RDP = 0xCC

Level 0

RDP = 0xAA

Write

RDP = 0xAA

Mass erase

Write

RDP = 0xAA

RDP decrease

RDP increase

RDP unchanged

MS34776V1

RDP byte value

Table 17. Protection level and content of RDP Option bytes

RDP complementary value Read Protection status

0xAA

0xCC

Any other value

Any value

0x55

0x33

Complement of RDP byte

Not the complement value of RDP byte

Level 0

Level 2

Level 1

The Flash program memory can be protected from being read by a hacking code: the read data are blocked (not for a fetch). The protected code must not access data in the protected zone, including the literal pool.

The Flash program memory can be protected against a hacking code read: this blocks the data read (not for a fetch), assuming that the native code is compiled according to the

PcROP option. This mode is activated setting WPRMOD = 1 in the FLASH_OPTR register.

The protection granularity is the sector (1 sector = 32 pages = 4 KB). To protect a sector, set to 0 the right bit in the WRPROT configuration: 0 means read and write protection, 1 means no protection.

Table 18

shows the link between the bits of the WRPROT configuration and the address of the Flash memory sectors.

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RM0451 Flash program memory and data EEPROM (FLASH)

Any read access performed as data (see Read as data and pre-read

) in a protected sector will trigger the RDERR flag in the FLASH_SR register. Any read-protected sector is also write-protected and any write access to one of these sectors will trigger the WRPERR flag in the FLASH_SR register.

Table 18. Link between protection bits of FLASH_WRPROTx register and protected address in Flash program memory (1)

Start address End address Bit Start address End address Bit

0x0800 0000

0x0800 1000

0x0800 2000

0x0800 3000

0x0800 4000

0x0800 5000

0x0800 6000

0x0800 7000

0x0800 8000

0x0800 9000

0x0800 A000

0x0800 B000

0x0800 C000

0x0800 D000

0x0800 E000

0x0800 F000

0x0801 0000

0x0801 1000

0x0801 2000

0x0801 3000

0x0801 4000

0x0801 5000

0x0801 6000

0x0801 7000

0x0800 0FFF

0x0800 1FFF

0x0800 2FFF

0x0800 3FFF

0x0800 4FFF

0x0800 5FFF

0x0800 6FFF

0x0800 7FFF

0x0800 8FFF

0x0800 9FFF

0x0800 AFFF

0x0800 BFFF

0x0800 CFFF

0x0800 DFFF

0x0800 EFFF

0x0800 FFFF

0x0801 0FFF

0x0801 1FFF

0x0801 2FFF

0x0801 3FFF

0x0801 4FFF

0x0801 5FFF

0x0801 6FFF

0x0801 7FFF

0x0801 8000

0x0801 9000

0x0801 A000

0x0801 B000

0x0801 C000

0x0801 D000

0x0801 E000

0x0801 F000

0x0802 0000

0x0802 1000

0x0802 2000

0x0802 3000

0x0802 4000

0x0802 5000

0x0802 6000

0x0802 7000

0x0802 8000

0x0802 9000

0x0802 A000

0x0802 B000

0x0802 C000

0x0802 D000

0x0802 E000

0x0802 F000

1. Bits 0 to 3 apply to category 1 devices only, bits 0 to 7 apply to category 2, and bits 0 to 15 to category 3.

0x0801 8FFF

0x0801 9FFF

0x0801 AFFF

0x0801 BFFF

0x0801 CFFF

0x0801 DFFF

0x0801 EFFF

0x0801 FFFF

0x0802 0FFF

0x0802 1FFF

0x0802 2FFF

0x0802 3FFF

0x0802 4FFF

0x0802 5FFF

0x0802 6FFF

0x0802 7FFF

0x0802 8FFF

0x0802 9FFF

0x0802 AFFF

0x0802 BFFF

0x0802 CFFF

0x0802 DFFF

0x0802 EFFF

0x0802 FFFF

When WPRMOD = 1 (PcROP enabled), it is not possible to reduce the protection on a sector: new zeros (to protect new sectors) can be set, but new ones (to remove the protection from sectors) cannot be added. This is valid regardless of the protection level

(RDPROT configuration). When WPRMOD is active, if the user tries to reset WPRMOD or to remove the protection from a sector, the programming is launched but WPRMOD or protected sectors remain unchanged.

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The only way to remove a protection from a sector is to request a mass erase (which changes the protection level to 0 and disables PcROP): when PcROP is disabled, the protection on sectors can be changed freely.

The memory interface implements two ways to protect against unwanted write/erase operations which are valid for all matrix or only for specific sectors of the Flash program memory.

As explained in the

Unlocking/locking operations section, the user can:

• Write/erase to the data EEPROM only when PELOCK = 0 in the FLASH_PECR register.

• Write/erase to the Option bytes area only when PELOCK = 0 and OPTLOCK = 0 in the

FLASH_PECR register.

• Write/erase to the Flash program memory only when PELOCK = 0 and PRGLOCK = 0 in the FLASH_PECR register.

To see the sequences to set PELOCK, PRGLOCK and OPTLOCK, refer to the Unlocking the data EEPROM and the FLASH_PECR register

, Unlocking the Flash program memory

and Unlocking the Option bytes area sections.

In the Flash program memory, it is possible to add another write protection with the sector granularity. When PcROP is disabled (WPRMODE = 0), the bits of WRPROT are used to enable the write protection on the sectors. The polarity is opposed relatively to PcROP: to protect a sector, it is necessary to set the bit to 1; to remove the protection, it is necessary to

set the bit to 0. Table 18

is valid for a write protection as well. As explained, when PcROP is enabled, the sectors protected against read are also protected against write/erase. It is always possible to change the write protection on sectors both in Level 0 and Level 1

(provided that it is possible to write/erase to Option bytes and that PcROP is disabled).

Table 19 resumes the protections.

Table 19. Memory access vs mode, protection and Flash program memory sectors

Mode

Flash program memory sectors

RDP

User

(including In Application

Programming) no Debug, or no Boot in RAM, or no Boot in System memory

Level 1

Level 0

Level 2

User in Debug, or with Boot in RAM, or with Boot in System memory

Level 0 Level 1 Level 2

Flash program memory

(FLASH_PRGLOCK = 1)

Flash memory

(FLASH_PRLOCK = 0)

Flash program memory in WRP pages

R / W

Protected

(no access)

Protected

(no access)

Protected

(no access)

(1)

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Table 19. Memory access vs mode, protection and Flash program memory sectors (continued)

Mode

Flash program memory sectors

User

(including In Application

Programming) no Debug, or no Boot in RAM, or no Boot in System memory

RDP

Level 1

Level 0

Flash program memory in PCROP pages

Data EEPROM

(FLASH_PELOCK = 1)

Data EEPROM

(FLASH_PELOCK = 0)

Option bytes

(FLASH_OPTLOCK = 1)

Option bytes

(FLASH_OPTLOCK = 0)

1. NA stands for “not applicable”.

Fetch

R / W

Level 2

Fetch

R / W

User in Debug, or with Boot in RAM, or with Boot in System memory

Level 0

Fetch

R / W

Level 1

Protected

(no access)

Protected

(no access)

Protected

(no access)

R / W

Level 2

(1)

3.4.4 Write/erase protection management

Here is a summary of the rules to change all previous protections:

• When the protection Level is 2, no protection change can be done.

• When in Level 0 or 1, it is always possible to move to Level 2, writing xx33xxCC (the x are the hexadecimal digits that can have any value) in the first Option byte word.

• When in Level 0, it is possible to move to Level 1, writing any value in the first Option byte word that is not xx33xxCC (Level 2) or xx55xxAA (Level 0).

• when in Level 1, the protection can be reduced to Level 0, writing xx55xxAA in the first

Option byte word. This generates a mass erase and deletes the PcROP field too.

• It is always possible to enable PcROP (except in Level 2), writing x0xxx1xx in the first

Option byte word. If there is a mismatch during an Option byte loading on this flag,

PcROP is enabled.

• PcROP can be removed on requesting a mass erase (move from Level 1 to Level 0).

• When PcROP is disabled, a write protection can be added on sectors (writing 1) or removed (writing 0) in the third word of the Option bytes. A mismatch concerns all write-protected sectors (if PcROP is disabled).

• When PcROP is enabled, protected sectors can be added (writing 0) but cannot be removed. A mismatch concerns all read- and write-protected sectors (if PcROP is enabled).

• A mass erase does not delete the third word of the Option bytes: the user must write it correctly.

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Write protection error flag (WRPERR)

If an erase/program operation to a write-protected page of the Flash program memory and data EEPROM is launched, the Write Protection Error flag (WRPERR) is set in the

FLASH_SR register. Consequently, the WRPERR flag is set when the software tries to:

• Write to a WRP page.

• Write to a System memory page or to factory option bytes.

• Write to the Flash program memory, data EEPROM or Option bytes if they are not unlocked by PEKEY, PRGKEY or OPTKEY.

• Write to the Flash program memory, data EEPROM or Option bytes when the RDP

Option byte is set and the device is in debug mode or is booting from the RAM or from the System memory.

A write-protection error aborts the write/erase operation and an interrupt can be generated

(if ERRIE = 1 in the FLASH_PECR register).

To reset this flag, the software needs to write it to 1.

Read error (RDERR)

If the software tries to read a sector protected by PcROP, the RDERR flag of FLASH_SR is raised. The data received on the bus is at 0.

If the error interrupt is enabled (ERRIE = 1 in the FLASH_PECR register), an interrupt is generated.

To reset this flag, the software needs to write it to 1.

Setting the End of programming interrupt enable bit (EOPIE) in the FLASH_PECR register enables an interrupt generation when an erase or a programming operation ends successfully. In this case, the End of programming (EOP) bit in the FLASH_SR register is set. To reset it, the software needs to write it to 1.

Setting the Error interrupt enable bit (ERRIE) in the FLASH_PECR register enables an interrupt generation if an error occurs during a programming or an erase operation request.

In this case, one or several error flags are set in the FLASH_SR register:

• RDERR (PCROP Read protection error flags)

• WRPERR (Write protection error flags)

• PGAERR (Programming alignment error flag)

• OPTVERR (Option validity error flag)

• SIZERR (Size error flag)

• FWWERR (Fetch while write error flag)

• NOTZEROERR (Write a not zero word error flag)

To reset the error flag, the software needs to write the right flag to 1.

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RM0451

Interrupt event

End of operation

Error

Flash program memory and data EEPROM (FLASH)

Table 20. Flash interrupt request

Event flag

EOP

RDERR

WRPERR

PGAERR

OPTVERR

SIZERR

FWWERR

NOTZEROERR

Enable control bit

EOPIE

ERRIE

3.6

3.6.1

A hard fault is generated on:

• The memory bus if a read access is attempted when RDP is set.

• The memory bus if a read as data is received; then, the memory interface is waiting for a data/address during a half-page write (after the 1 st

address and before the 16 th address).

• The register bus if an incorrect value is written in PEKEYR, PRGKEYR, or OPTKEYR.

Memory interface management

The purpose of this section is to clarify what happens when one operation is requested while another is ongoing: the way the different operations work together and are managed by the memory interface.

Operation priority and evolution

There are three types of operations and each of them has different flows:

Read

• If no operation is ongoing and the read address is not protected, the read is executed without delays and with the actual configurations.

• If the read address is protected, the operation is filtered (the read requested is never sent to the memory) and an error is raised.

• If the read address is not protected but the memory interface is busy and cannot perform the operation, the read is put on hold to be executed as soon as possible.

Write/erase

• If no operation is ongoing and the write address is not protected, the write/erase will start immediately; after some clock pulses (see

Table 15 ) during which the bus and the

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3.6.2

RM0451 master are blocked, the memory interface continues the operation freeing the bus and the master.

• If the address is protected, the write/erase is filtered (the write/erase requested is never sent to the memory) and an error is raised.

• If the address is not protected but one or several conditions are not met, the operation is aborted (the abort needs more time to be executed because the NVM and data

EEPROM need to return to default configuration) and an error is raised.

• If the address to write/erase is not protected and all rules are respected, and if the memory interface is busy, the operation is put on hold to be executed as soon as possible.

Option byte loading

• If a write/erase is ongoing, the Option byte loading waits for the end of operation then it is executed: no other write/erase is accepted, even if waiting.

• If no write/erase is ongoing, the Option byte is executed directly (the read operation is executed until the system reset goes to 0 as a result of the Option byte request).

This means that the Option byte loading has a bigger priority than the read and write/erase operations. All other operations are executed in the order of request.

Sequence of operations

Read as data while write

If the master requests a read as data (see Read as data and pre-read ) while a write

operation is ongoing, there are three different cases:

If the read is in a protected area, the RDERR flag is raised and the write operation continues.

2. If the write operation uses a Single programming operation or a Multiple programming operation (half page)

and all addresses/data have been sent to the memory interface, any read operation is put on hold and will be executed when the write operation is complete. It is important to emphasize that, during all the time spent when the read waits to be executed, the master is blocked and no other operation can be executed until the write and read operations are complete.

3. if the write operation uses a Multiple programming operation (half page)

and not all addresses/data have been sent to the memory interface, the read operation is not accepted, a hard fault is generated and the memory interface continues to wait for the missing addresses/data to complete the write operation.

Fetch while write

If the master fetches an instruction while a write is ongoing, the situation is similar to a read as data (see step 1 and 2 above), but the last case is as follows:

•

If the write operation uses a Multiple programming operation (half page) and not all

addresses/data have been sent to the memory interface, the write is aborted and it is as it had never happened: the read operation is accepted, and the value is sent to the master.

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3.6.3 Write while another write operation is ongoing

If the master requests a write operation while another one is ongoing, there are different cases:

•

If the previous write uses a Single programming operation or a Multiple programming operation (half page)

and all addresses/data have been sent to the memory interface, and if the new write is in a protected area, the WRPERR flag is raised, the previous write continues and the new write is deleted.

•

If the previous write uses a Single programming operation or a Multiple programming operation (half page)

and all addresses/data have been sent to the memory interface,

and if the new Single programming operation

Multiple programming operation (half page)

is not in a protected area, the new write is put on hold and will be executed when the first write operation is complete. It is important to emphasize that the master who requested the second write is blocked until the first write completes and the second has stored the address and data internally.

• It is forbidden to request a new write when a mass erase is ongoing: during all the steps of the mass erase, the data is not stored internally and the new data can change the value stored as a protection, adding unwanted protections.

• It is possible to change configurations to prepare a new write operation when the first operation uses a

Single programming operation or a Multiple programming operation

(half page) and all addresses/data have been sent to the memory interface.

Change the number of wait states while reading

To change the number of wait states, it is necessary to write to the FLASH_ACR register.

The read/write of a register uses a different interface than the memory read/write. The number of wait states cannot be changed while the memory interface is reading and the memory interface cannot be stopped if a request is sent to the register interface. For this reason, while a master is reading the memory and another master changes the wait state number, the register interface will be locked until the change takes effect (until the readings stop). To stop the master which is changing the number of wait states, it is important to read back the content of the FLASH_ACR register: it is not possible to know the number of clock cycles that will be necessary to change the number of wait states as it depends on the customer code.

3.6.4 Power-down

To put the NVM in power-down, it is necessary to execute an unlocking sequence.

The following sequence is used to unlock RUN_PD bit of the FLASH_ACR register:

• Write PDKEY1 = 0x04152637 to the FLASH_PDKEYR register.

• Write PEKEY2 = 0xFAFBFCFD to the FLASH_PDKEYR register.

It is necessary to write the two keys without constraints about other read or write. No error is generated if the wrong key is used: when both have been written, RUN_PD bit is unlocked and can be written to 1, putting the NVM in power-down mode.

Resetting the RUN_PD flag to 0 (making the NVM available) automatically resets the sequence and the two keys are requested to re-enable RUN_PD.

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Read registers

To read all internal registers of the memory interface, the user must read at the register addresses. The content is available immediately (no wait state is necessary to read registers). If the user tries to read the FLASH_ACR register after modifying the number of wait states, the content will be available when the change takes effect (when no read is done in the NVM memory, so the number of wait states is changed).

When no register is selected or when a wrong address is sent to the memory interface, a zero value is sent as an answer. No error is generated.

When the master sends a request to read 8 or 16 bits, the memory interface returns the corresponding part of the register on the data output bus. For example, if a register content is 0x12345678 and the master sends a request to read the second byte, the output will be

0x34343434 (because 0x34 is the content of the second register byte when starting to count bytes from zero). Similarly, if the master sends a request to read half-word zero of the previous register, the output will be 0x56785678.

Write to registers

In the configuration registers of the memory interface, there are two types of bits:

• the bits that can be written to directly

• the bits needing a particular sequence to unlock.

To know which category a bit belongs to, see the next sections where every bit is explained in details.

When it is possible to write directly to a register or a key-register, the user must write the expected value at the register address. If the address is not correct, no error is generated. If the user tries to modify a read-only register, no error is generated and the modify operation does not take any effect. It is possible to write registers by byte, half-word and word.

When an unlock sequence is necessary, the correct values to use are given.

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Res.

Address offset: 0x00

Res.

Reset value: 0x0000 0000

Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res.

rw rw rw rw rw rw

Bits 31:7 Reserved, must be kept at reset value

Bit 6 PRE_READ

This bit enables the pre-read.

0: The pre-read is disabled

1: The pre-read is enabled. The memory interface stores the last address read as data and tries to read the next one when no other read or write or prefetch operation is ongoing.

Note: It is automatically reset every time the DISAB_BUF bit (in this register) is set to 1.

Bit 5 DISAB_BUF

This bit disables the buffers used as a cache during a read. This means that every read will access the NVM even for an address already read (for example, the previous address). When this bit is reset, the PRFTEN and PRE_READ bits are automatically reset, too.

0: The buffers are enabled

1: The buffers are disabled. Every time one NVM value is necessary, one new memory read sequence has do be done.

Bit 4 RUN_PD

This bit determines if the NVM is in power-down mode or in idle mode when the device is in run mode. It is possible to write this bit only when there is an unlocked writing of the

FLASH_PDKEYR register.

The correct sequence is explained in Section 3.6.4: Power-down

. When writing this bit to 0, the keys are automatically lost and a new unlock sequence is necessary to re-write it to 1.

0: When the device is in Run mode, the NVM is in Idle mode.

1: When the device is in Run mode, the NVM is in power-down mode.

Bit 3 SLEEP_PD

This bit allows to have the Flash program memory and data EEPROM in power-down mode or in idle mode when the device is in Sleep mode.

0: When the device is in Sleep mode, the NVM is in Idle mode.

1: When the device is in Sleep mode, the NVM is in power-down mode.

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Bit 2 Reserved, must be kept at reset value

Bit 1 PRFTEN

This bit enables the prefetch. It is automatically reset every time the DISAB_BUF bit (in this register) is set to 1. To know how the prefetch works, see the Fetch and prefetch section.

0: The prefetch is disabled.

1: The prefetch is enabled. The memory interface stores the last address fetched and tries to read the next one when no other read or write operation is ongoing.

Bit 0 LATENCY

The value of this bit specifies if a 0 or 1 wait-state is necessary to read the NVM. The user must write the correct value relative to the core frequency and the operation mode (power). The

correct value to use can be found in Table 11

No check is done to verify if the configuration is correct.

To increase the clock frequency, the user has to change this bit to ‘1’, then to increase the frequency. To reduce the clock frequency, the user has to decrease the frequency, then to change this bit to ‘0’.

0: Zero wait state is used to read a word in the NVM.

1: One wait state is used to read a word in the NVM.

3.7.2

31 30

Program and erase control register (FLASH_PECR)

Address offset: 0x04

Reset value: 0x0000 0007

This register can only be written after a good write sequence done in FLASH_PEKEYR, resetting the PELOCK bit.

29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res.

15 14 13 12 11

Res.

10 9 8 rw

7 6 5

Res.

4 3 rw

2 rw

1 rw

0 rw rw rw rw rw rs rs rs

Bits 31:24 Reserved, must be kept at reset value

Bit 23 NZDISABLE: Non-Zero check notification disable

When this bit is set, the application software does not check if the previous NVM content is zero before programming a word or an half-page in the program or boot area. As a result, the NOTZEROERR flag will always remain at 0 and no interrupt will be generated if the above condition is met. By default, NZDISABLE is set to 0. It can be modified only when

PELOCK is 0.

0: error interrupt disabled

1: error interrupt enabled

On category 3 devices, this bit is not available and the behavior corresponds to

NZDISABLE=0.

Bits 22:19 Reserved, must be kept at reset value

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Bit 18 OBL_LAUNCH

Setting this bit, the software requests the reloading of Option byte. The Option byte reloading does not stop an ongoing modify operation, but it blocks new ones. The Option byte reloading generates a system reset.

0: Option byte loading completed.

1: Option byte loading to be done.

Note: This bit can only be modified when OPTLOCK is 0. Locking OPTLOCK (or other lock bits) does not reset this bit.

Bit 17 ERRIE: Error interrupt enable

0: Error interrupt disable.

1: Error interrupt enable.

Note: This bit can only be modified when PELOCK is 0. Locking PELOCK does not reset this bit; the interrupt remains enabled.

Bit 16 EOPIE: End of programming interrupt enable

0: End of program interrupt disable.

1: End of program interrupt enable.

Note: This bit can only be modified when PELOCK is 0. Locking PELOCK does not reset this bit; the interrupt remains enabled.

Bits 15:11 Reserved, must be kept at reset value

Bit 10 FPRG: Half Page programming mode

0: Half Page programming disabled.

1: Half Page programming enabled.

Note: This bit can be modified when PELOCK is 0. It is reset when PELOCK is set.

Bit 9 ERASE

0: No erase operation requested.

1: Erase operation requested.

Note: This bit can be modified when PELOCK is 0. It is reset when PELOCK is set.

Bit 8 FIX

0: An erase phase is automatically performed, when necessary, before a program operation in the data EEPROM and the Option bytes areas. The programming time can be:

Tprog (program operation) or 2 * Tprog (erase + program operations).

1: The program operation is always performed with a preliminary erase and the programming time is: 2 * Tprog.

Note: This bit can be modified when PELOCK is 0. It is reset when PELOCK is set.

Bits 7:5 Reserved, must be kept at reset value

Bit 4 DATA

0: Data EEPROM not selected.

1: Data memory selected.

Note: This bit can be modified when PELOCK is 0. It is reset when PELOCK is set.This bit is not very useful as the page and word have the same size in the data EEPROM, but it is used to identify an erase operation (by page) from a word operation .

Bit 3 PROG

This bit is used for half-page program operations and for page erase operations in the Flash program memory.

0: The Flash program memory is not selected.

1: The Flash program memory is selected.

Note: This bit can be modified when PELOCK is 0. It is reset when PELOCK is set.

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Bit 2 OPTLOCK: Option bytes lock

This bit blocks the write/erase operations to the user Option bytes area and the

OBL_LAUNCH bit (in this register). It can only be written to 1 to re-lock. To reset to 0, a correct sequence of unlock with OPTKEYR register is necessary (see Unlocking the Option bytes area ), with PELOCK bit at 0. If the sequence is not correct, the bit will be locked until the next system reset and a hard fault is generated. If the sequence is executed when PELOCK = 1, the bit remains locked and no hard fault is generated. The keys to unlock are:

– First key:0xFBEAD9C8

– Second key: 0x24252627

0: The write and erase operations in the Option bytes area are disabled.

1: The write and erase operations in the Option bytes area are enabled.

Note: This bit is set when PELOCK is set.

Bit 1 PRGLOCK: Program memory lock

This bit blocks the write/erase operations to the Flash program memory. It can only be written to 1 to re-lock. To reset to 0, a correct sequence of unlock with PRGKEYR register is

necessary (see Unlocking the Flash program memory

), with PELOCK bit at 0. If the sequence is not correct, the bit will be locked until the next system reset and a hard fault is generated. If the sequence is executed when PELOCK = 1, the bit remains locked and no hard fault is generated. The keys to unlock are:

– First key:0x8C9DAEBF

– Second key: 0x13141516

0: The write and erase operations in the Flash program memory are disabled.

1: The write and erase operations in the Flash program memory are enabled.

Note: This bit is set when PELOCK is set.

Bit 0 PELOCK: FLASH_PECR lock

This bit locks the FLASH_PECR register. It can only be written to 1 to re-lock. To reset to 0, a correct sequence of unlock with PEKEYR register (see Unlocking the data EEPROM and the

FLASH_PECR register ) is necessary. If the sequence is not correct, the bit will be locked until the next system reset and one hard fault is generated. The keys to unlock are:

– First key: 0x89ABCDEF

– Second key: 0x02030405

0: The FLASH_PECR register is unlocked; it can be modified and the other bits unlocked.

Data write/erase operations are enabled.

1: The FLASH_PECR register is locked and no write/erase operation can start.

86/784 RM0451 Rev 3

RM0451 Flash program memory and data EEPROM (FLASH)

3.7.3

31 w

15 w

30 w

14 w

Power-down key register (FLASH_PDKEYR)

Address offset: 0x08

Reset value: 0x0000 0000

29 28 27 26 21 w

13 w w

12 w w

11 w w

10 w

25 24 23

FLASH_PDKEYR[31:16]

22 w

9 w

8 w

7 w

6 w

FLASH_PDKEYR15:0] w w w w

5 w

20 w

19 w

18 w

17 w

16 w

0 w w w w w

Bits 31:0 This is a write-only register. With a sequence of two write operations (the first one with

0x04152637 and the second one with 0xFAFBFCFD), the write size being that of a word, it is possible to unlock the RUN_PD bit of the FLASH_ACR register. For more details, refer to

Section 3.6.4: Power-down

3.7.4

31 w

15 w

30 w

14 w

PECR unlock key register (FLASH_PEKEYR)

Address offset: 0x0C

Reset value: 0x0000 0000

29 28 27 26 w

13 w w

12 w w

11 w w

10 w

25 24 23 22 w

FLASH_PEKEYR[31:16] w w w

9 w

8 7

FLASH_PEKEYR15:0] w w

6 w

21 w

5 w

20 w

19 w

18 w

17 w

16 w

0 w w w w w

Bits 31:0 This is a write-only register. With a sequence of two write operations (the first one with

0x89ABCDEF and the second one with 0x02030405), the write size being that of a word, it is possible to unlock the FLASH_PECR register. For more details, refer to Unlocking the data

EEPROM and the FLASH_PECR register .

3.7.5

31 w

15 w

30 w

14 w

Program and erase key register (FLASH_PRGKEYR)

Address offset: 0x10

Reset value: 0x0000 0000

29 28 27 26 w

13 w w

12 w w

11 w w

10 w

25 24 23 22

FLASH_PRGKEYR[31:16] w

9 w

8 w

7 w

6 w

FLASH_PRGKEYR15:0] w w w

21 w

5 w

20 w

4 w

19 w

3 w

18 w

17 w

16 w

0 w w w

Bits 31:0 This is a write-only register. With a sequence of two write operations (the first one with

0x8C9DAEBF and the second one with 0x13141516), the write size being that of a word, it is possible to unlock the Flash program memory. The sequence can only be executed when

PELOCK is already unlocked. For more details, refer to Unlocking the Flash program memory

RM0451 Rev 3 87/784

Flash program memory and data EEPROM (FLASH) RM0451

3.7.6

31 w

15 w

Option bytes unlock key register (FLASH_OPTKEYR)

Address offset: 0x14

Reset value: 0x0000 0000

30 29 w

14 w

28 w

27 w

26 w

25 24 23

FLASH_OPTKEYR[31:16]

22 w

9 w

8 w

7 w

6 w

FLASH_OPTKEYR[15:0] w w w

21 w

20 w

19 w

18 w

17 w

16 w

0 w w w w w w w w w w w

Bits 31:0 This is a write-only register. With a sequence of two write operations (the first one with

0xFBEAD9C8 and the second one with 0x24252627), the write size being that of a word, it is possible to unlock the Option bytes area and the OBL_LAUNCH bit. The sequence can only be executed when PELOCK is already unlocked. For more details, refer to Unlocking the Option bytes area .

88/784 RM0451 Rev 3

RM0451 Flash program memory and data EEPROM (FLASH)

Address offset: 0x018

Reset value: 0x0000 000C

30 29 28 27 26 25 31 24 23 22 21 20 19 18

Res.

17 16

15 14 13 12 11 10 9 8 7 6 5 4 3 2 rc_w1 rc_w1

1 0

Res.

rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 r r rc_w1 r

Bits 31:18 Reserved, must be kept at reset value

Bit 17 FWWERR

This bit is set by hardware when a write/erase operation is aborted to perform a fetch. This is not a real error, but it is used to inform that the write/erase operation did not execute. To reset this flag, write 1.

0: No write/erase operation aborted to perform a fetch.

1: A write/erase operation aborted to perform a fetch.

Bit 16 NOTZEROERR

This bit is set by hardware when a program in the Flash program or System Memory tries to overwrite a not-zero area. In category 3 devices, this flag does not stop the program operation: it is possible that the value found when reading back is not what the user wrote. To reset this flag, write 1.

0: The write operation is done in an erased region or the memory interface can apply an erase before a write.

1: The write operation is attempting to write to a not-erased region and the memory interface cannot apply an erase before a write. Except for category 3 devices, the modify operation is aborted. For category 3 devices a not-zero error does not abort the write/erase operation.

Bits 15:14 Reserved, must be kept at reset value

Bit 13 RDERR

This bit is set by hardware when the user tries to read an area protected by PcROP. It is cleared by writing 1.

0: No read protection error happened.

1: One read protection error happened.

Bit 12 Reserved, must be kept at reset value

Bit 11 OPTVERR : Option valid error

This bit is set by hardware when, during an Option byte loading, there was a mismatch for one or more configurations. It means that the configurations loaded may be different from what the user wrote in the memory. It is cleared by writing 1.

If an error happens while loading the protections (WPRMOD, RDPROT, WRPROT), the source code in the Flash program memory may not execute correctly.

0: No error happened during the Option bytes loading.

1: One or more errors happened during the Option bytes loading.

RM0451 Rev 3 89/784

Flash program memory and data EEPROM (FLASH) RM0451

Bit 10 SIZERR : Size error

This bit is set by hardware when the size of data to program is not correct. It is cleared by writing 1.

0: No size error happened.

1: One size error happened.

Bit 9 PGAERR : Programming alignment error

This bit is set by hardware when an alignment error has happened: the first word of a half-page operation is not aligned to a half-page, or one of the following words in a half-page operation does not belong to the same half-page as the first word. When this bit is set, it has to be cleared before writing 1, and no half-page operation is accepted.

0: No alignment error happened.

1: One alignment error happened.

Bit 8 WRPERR : Write protection error

This bit is set by hardware when an address to be programmed or erased is write-protected. It is cleared by writing 1.

0: No protection error happened.

1: One protection error happened.

Bits 7:4 Reserved, must be kept at reset value

Bit 3 READY

When this bit is set, the NVM is ready for read and write/erase operations.

0: The NVM is not ready. No read or write/erase operation can be done.

1: The NVM is ready.

Bit 2 ENDHV

This bit is set and reset by hardware.

0: High voltage is executing a write/erase operation in the NVM.

1: High voltage is off, no write/erase operation is ongoing.

Bit 1 EOP : End of program

This bit is set by hardware at the end of a write or erase operation when the operation has not been aborted. It is reset by software (writing 1).

0: No EOP operation occurred

1: An EOP event occurred. An interrupt is generated if EOPIE bit is set.

Bit 0 BSY: Memory interface busy

Write/erase operations are in progress.

0: No write/erase operation is in progress.

1: A write/erase operation is in progress.

90/784 RM0451 Rev 3

RM0451 Flash program memory and data EEPROM (FLASH)

3.7.8 Option bytes register (FLASH_OPTR)

Address offset 0x1C

Reset value: 0xX0XX 0XXX. It depends on the value programmed in the option bytes.

During production, it is set to 0x8070 00AA.

30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res.

15 r

14 r

13 12 11 10 9

Res.

8 7 r

6 r

5 r

4 r

3 r

2 r

1 r

0 r r r r r r r r r

Bit 31 nBOOT1

This bit is used in conjunction with BOOT0 signal to configure the device boot mode (see

Section 2.4: Boot configuration ).

If there is a mismatch on this configuration during the Option bytes loading, it is loaded with 1.

If the device is protected at Level 2, BOOT0 and nBOOT1 lose their meaning: the boot is always forced in the Flash program memory.

Bit 30 nBOOT0

This bit is available on category 1 devices only.

When nBOOT_SEL is set, nBOOT0 bit defines the value of BOOT0 signal that is used to select the device boot mode (see

Section 2.4: Boot configuration

Bit 29 nBOOT_SEL

0: BOOT0 signal is defined by BOOT0 pin value (default mode)

1: BOOT0 signal is defined by nBOOT0 option bit

This bit is available on category 1 devices only. It is held at ‘0’ on other devices.

Bits 28:23 Reserved, must be kept at reset value

Bit 22 nRST_STDBY

If there is a mismatch on this configuration during the Option bytes loading, it is loaded with 1.

0: Reset generated when entering the Standby mode.

1: No reset generated.

Bit 21 nRST_STOP

If there is a mismatch on this configuration during the Option bytes loading, it is loaded with 1.

0: Reset generated when entering the Stop mode.

1: No reset generated.

Bit 20 WDG_SW

If there is a mismatch on this configuration during the Option bytes loading, it is loaded with 1.

0: Hardware watchdog.

1: Software watchdog.

RM0451 Rev 3 91/784

Flash program memory and data EEPROM (FLASH) RM0451

Bits 19:16 BOR_LEV : Brownout reset threshold level

These bits reset the threshold level for a 1.45 V to 1.55 V voltage range (power-down only). In this particular case, V

must have been above V

BOR0

to start the device OBL sequence, in order to disable the BOR. The power-down is then monitored by the PDR. If the BOR is disabled, a “grey zone” exists between 1.8 V and the VPDR threshold (this means V

can be below the minimum operating voltage (1.8 V) without any reset until the VPDR threshold).

If there is a mismatch on this configuration during the Option bytes loading, it is loaded with

0x8.

0xxx: BOR OFF . This is the reset threshold level for the 1.45 V - 1.55 V voltage range

(power-down only).

In this particular case, V

DD must have been above BOR LEVEL 1 to start the device OBL sequence in order to disable the BOR. The power-down is then monitored by the PDR.

Note: If the BOR is disabled, a "grey zone" exists between 1.8 V and the VPDR threshold

(this means that V

may be below the minimum operating voltage (1.8 V) without causing a reset until it crosses the VPDR threshold)

1000:

1001:

1010:

1100:

BOR LEVEL 1

BOR LEVEL 2

BOR LEVEL 3

BOR LEVEL 5

is the reset threshold level for V

BOR0

(around 1.8 V)

BOR1

(around 2.0 V)

BOR2

(around 2.5 V)

1011: BOR LEVEL 4 is the reset threshold level for V

BOR3

BOR4

(around 2.7 V).

(around 3.0 V)

Note: Refer to the device datasheets for the exact definition of BOR levels.

Bits 15:9 Reserved, must be kept at reset value

Bit 8 WPRMOD

This bit selects between write and read protection of Flash program memory sectors. If there is a mismatch on this configuration during the Option bytes loading, it is loaded with 1.

0: PCROP disabled. The WRPROT bits are used as a write protection on a sector.

1: PCROP enabled. The WRPROT bits are used as a read protection on a sector.

Bits 7:0 RDPROT : Read protection

These bits contain the protection level loaded during the Option byte loading. If there is a mismatch on this configuration during the Option bytes loading, it is loaded with 0x00.

0xAA: Level 0

0xCC: Level 2

Others: Level 1

92/784 RM0451 Rev 3

RM0451 Flash program memory and data EEPROM (FLASH)

3.7.9

31 r

15 r

Write protection register 1 (FLASH_WRPROT1)

Address offset: 0x20

Reset value: 0xXXXX XXXX. It depends on the value programmed in the option bytes.

During production, it is set to 0x0000 0000.

30 29 28 27 26 21 20 19 18 17 r

14 r r

13 r r

12 r r

11 r r

10 r r

25 r

24 23

WRPROT1[31:16] r

8 r

WRPROT1[15:0] r r

22 r r

6 r

5 r r

4 r r

3 r r

2 r r

1 r

16 r r

Bits 31:0 WRPROT1: Write protection

– If WPRMOD = 0 in the FLASH_OPTR register, these bits contain the write protection configuration for the Flash memory (every bit protects a 4-Kbyte sector: the first bit protects the first sector, the second bit protects the second page and so on). In this case, 1 = sector protected, 0 = no protection.

– If WPRMOD = 1, these bits are used to protect from reading as data (see Read as data and pre-read ), and then also from writing, with the same granularity and with the same

combination of bits and sectors. The read protection does not protect against a fetch. In this case, 1 = no protection, 0 = sector protected.

When WPRMOD = 0, it is possible to set or reset these bits without any limitation changing the relative Option bytes.

When WPRMOD = 1, it is only possible to increase the protection, which means that the user can add zeros but cannot add ones.

The mass erase deletes the WPRMOD bits but does not delete the content of this register.

After a mass erase, the user must write the relative Option bytes with zeros to remove completely the write protections.

If there is a mismatch on this configuration during the Option bytes loading, and the content of

WPRMOD in the FLASH_OPTR register is:

1, this configuration is loaded with 0x0000.

0, this configuration is loaded with 0xFFFF.

If there was a mismatch when WPRMOD was loaded in the FLASH_OPTR register (thus loaded with ones), the register is loaded with 0x0000.

RM0451 Rev 3 93/784

Flash program memory and data EEPROM (FLASH) RM0451

3.7.10 Write protection register 2 (FLASH_WRPROT2)

Address offset: 0x80

Reset value: 0x 0000 XXXX. It depends on the value programmed in the option bytes.

During production, it is set to 0x0000 0000.

Res.

15 r

14 r

13 r

12 r

11 r

10 r

9 r

8 7

WRPROT2 [15:0] r r

6 r

5 r

4 r

3 r

2 r

1 r

0 r

Bits 31:16 Reserved, must be kept at reset value

Bits 15:0 WRPROT2 : Write protection

– If WPRMOD = 1, these bits are used to protect from reading as data (see Read as data and pre-read ), and then also from writing, with the same granularity and with the same

combination of bits and sectors. The read protection does not protect against a fetch. In this case, 1 = no protection, 0 = sector protected.

When WPRMOD = 0, it is possible to set or reset these bits without any limitation changing the relative Option bytes.

When WPRMOD = 1, it is only possible to increase the protection, which means that the user can add zeros but cannot add ones.

The mass erase deletes the WPRMOD bits but does not delete the content of this register.

After a mass erase, the user must write the relative Option bytes with zeros to remove completely the write protections.

If there is a mismatch on this configuration during the Option bytes loading, and the content of

WPRMOD in the FLASH_OPTR register is:

1, this configuration is loaded with 0x0000.

0, this configuration is loaded with 0xFFFF.

If there was a mismatch when WPRMOD was loaded in the FLASH_OPTR register (thus loaded with ones), the register is loaded with 0x0000.

94/784 RM0451 Rev 3

RM0451 Flash program memory and data EEPROM (FLASH)

3.7.11 Flash register map

Table 21. Flash interface - register map and reset values

Offset

Register

0x00

FLASH_ACR

0x00000000 0 0 0 0 0 0

0x004

FLASH_PECR

0x008

0x00C

0x010

0x014

0x00000007

FLASH_

PDKEYR

0x00000000

FLASH_

PKEYR

0x00000000

FLASH_

PRGKEYR

0x00000000

FLASH_

OPTKEYR

0x00000000

0 0 0 0

PDKEYR[31:0]

0 0 0 0 0 1 1 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PKEYR[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PRGKEYR[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OPTKEYR[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x018

FLASH_SR

0x0000000C 0 0 0 0 0 0 0 1 1 0 0

0x01C

FLASH_OPTR BOR_LEV:0] RDPROT[7:0]

0x020

0x080

0xXXXX0XXX X X X X X X X X X X X X X X X X X X X

FLASH_

WRPROT1

WRPROT1[31:0]

0x0000XXXX X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X

FLASH_

WRPROT2

0xXXX 0000

WRPROT2[15:0]

X X X X X X X X X X X X X X X X

Refer to Section 2.2 on page 39 for the register boundary addresses.

RM0451 Rev 3 95/784

Flash program memory and data EEPROM (FLASH) RM0451

3.8.1

On the NVM, an area is reserved to store a set of Option bytes which are used to configure the product. Some option bytes are written in factory while others can be configured by the end user.

The configuration managed by an end user is stored the Option bytes area (32 bytes). To be taken into account, a boot sequence must be executed. This boot sequence occurs after a power-on reset when exiting from Standby mode, or by reloading the option bytes by software (

Section 3.8.3: Reloading Option bytes by software

). The Option bytes are automatically loaded during the boot. They are used to set the content of the FLASH_OPTR and FLASH_WRPROTx registers.

Every word, when read during the boot, is interpreted as explained in Table 22

: the lower 16 bits contain the data to copy in the memory interface registers and the higher 16 bits contain the complemented value used to check that the data read are correct. If there is an error during loading operation (the higher part is not the complement of the lower one), the default

value is stored in the registers. The check is done by configuration. Section 3.8.2

explains

what happens when there is a mismatch on protection configurations.

During a write, no control is done to check if the higher part of a word is the complement of the lower part: this check must be performed by the user application.

31-24

Complemented

Option byte 1

Table 22. Option byte format

23-16 15-8

Complemented

Option byte 0

Option byte 1

7-0

Option byte 0

Option bytes description

The Option bytes can be read from the memory locations listed in Table 23

Address

0x1FF8 0000

0x1FF8 0004

0x1FF8 0008

0x1FF8 000C

0x1FF8 0010

Table 23. Option byte organization

[31:16] nFLASH_OPTR[15:0] nFLASH_OPTR[31:16] nFLASH_WRPROT1[15:0] nFLASH_WRPROT1[31:16] nFLASH_WRPROT2[15:0]

[15:0]

FLASH_OPTR[15:0]

FLASH_OPTR[31:16]

FLASH_WRPROT1[15:0]

FLASH_WRPROT1[31:16]

FLASH_WRPROT2[15:0]

Refer to Section 3.7.8: Option bytes register (FLASH_OPTR)

and Section 3.7.9: Write protection register 1 (FLASH_WRPROT1)

for the meaning of each bit.

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RM0451

3.8.2

3.8.3

Flash program memory and data EEPROM (FLASH)

Mismatch when loading protection flags

When there is a mismatch during an Option byte loading, the memory interface sets the default value in registers.

In the Option byte area, there are three kinds of protection information:

• RDPROT

This configuration sets the Protection Level. As explained in the next section, changing this level changes the possibility to access the NVM and the product. The default value is Level 1. It is possible to return to Level 0 from Level 1 but all content of the data

EEPROM and Flash program memory will be deleted (mass erase). It is always possible to move to Level 2, but not to change protection levels when Level 2 is loaded

(if the user writes in Option bytes a Level 2 but never reloads the Option bytes, the memory interface continues to works in the previous level and it is possible to write again a different protection level in the Option bytes area).

• WPRMOD

This flag is independent from RDPROT and set if the Flash program memory is protected from read or write. When this flag is 1 (read protection), the only way to reset it is to request a mass erase (also returning to Level 0). This means that there is no way to remove the read protection when the device is in Level 2. The default value is 1

(read protection) and a mismatch on this bit also generates the default value for the

WRPROT configuration.

• WRPROT

This configuration sets which sectors of the Flash program memory are read- or writeprotected. If the read protection is disabled (WPRMOD = 0), 1 must be set in the right bit to protect a sector. If the read protection is enabled (WPRMOD = 1), 0 must be in the right bit to protect a sector. If during boot there is a mismatch on WPRMOD, this configuration is loaded with zeros so that all sectors of the Flash program memory are protected from read. If WPRMOD has been read correctly but there is a mismatch reading WRPROT, the register will be loaded with zeros if WPRMOD = 1, and with ones if WPRMOD = 0.

Thus, a mismatch on a protection can have a serious impact on the normal execution of code (if it is in the Flash program memory): when there is a read protection, only a fetch is possible. In the Flash program memory, some values are read as data (the constants, for example) during a code execution; protecting all sectors from read prevents the execution of the application code from the Flash program memory.

Reloading Option bytes by software

It is possible to request an Option byte reloading by setting the OBL_LAUNCH flag to 1 in the FLASH_PECR register. This bit can be set only when OPTLOCK = 0 (and PELOCK =

0). Setting this bit, the ongoing write/erase is completed, but no new write/erase or read operation is executed.

The reload of Option bytes generates a reset of the device but without a power-down. The options must be reloaded after every change of the Option bytes in the NVM, so that the changes can apply. It is possible to reload by setting OBL_LAUNCH, or with a power-on of the V18 domain (i.e. after a power-on reset or after a standby).

RM0451 Rev 3 97/784

Cyclic redundancy check calculation unit (CRC)

4 Cyclic redundancy check calculation unit (CRC)

RM0451

4.1 Introduction

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from 8-, 16- or 32-bit data word and a generator polynomial.

Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the functional safety standards, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at link time and stored at a given memory location.

4.2 CRC main features

• Uses CRC-32 (Ethernet) polynomial: 0x4C11DB7

+ X

+ X +1

• Alternatively, uses fully programmable polynomial with programmable size (7, 8, 16, 32 bits)

• Handles 8-,16-, 32-bit data size

• Programmable CRC initial value

• Single input/output 32-bit data register

• Input buffer to avoid bus stall during calculation

• CRC computation done in 4 AHB clock cycles (HCLK) for the 32-bit data size

• General-purpose 8-bit register (can be used for temporary storage)

• Reversibility option on I/O data

• Accessed through AHB slave peripheral by 32-bit words only, with the exception of

CRC_DR register that can be accessed by words, right-aligned half-words and rightaligned bytes

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RM0451

4.3 CRC functional description

Cyclic redundancy check calculation unit (CRC) crc_hclk

Figure 7. CRC calculation unit block diagram read access

32-bit AHB bus write access 32-bit accesses

Data register

(output)

Data register

(input)

CRC computation

CRC_INIT

CRC_CR

CRC_POL

CRC_IDR

MS19882V3

Signal name crc_hclk

Table 24. CRC internal input/output signals

Signal type Description

Digital input AHB clock

The CRC calculation unit has a single 32-bit read/write data register (CRC_DR). It is used to input new data (write access), and holds the result of the previous CRC calculation (read access).

Each write operation to the data register creates a combination of the previous CRC value

(stored in CRC_DR) and the new one. CRC computation is done on the whole 32-bit data word or byte by byte depending on the format of the data being written.

The CRC_DR register can be accessed by word, right-aligned half-word and right-aligned byte. For the other registers only 32-bit access is allowed.

The duration of the computation depends on data width:

• 4 AHB clock cycles for 32 bits

• 2 AHB clock cycles for 16 bits

• 1 AHB clock cycles for 8 bits

An input buffer allows a second data to be immediately written without waiting for any wait states due to the previous CRC calculation.

RM0451 Rev 3 99/784

104

Cyclic redundancy check calculation unit (CRC)

Note:

RM0451

The data size can be dynamically adjusted to minimize the number of write accesses for a given number of bytes. For instance, a CRC for 5 bytes can be computed with a word write followed by a byte write.

The input data can be reversed, to manage the various endianness schemes. The reversing operation can be performed on 8 bits, 16 bits and 32 bits depending on the REV_IN[1:0] bits in the CRC_CR register.

For example: input data 0x1A2B3C4D is used for CRC calculation as:

• 0x58D43CB2 with bit-reversal done by byte

• 0xD458B23C with bit-reversal done by half-word

• 0xB23CD458 with bit-reversal done on the full word

The output data can also be reversed by setting the REV_OUT bit in the CRC_CR register.

The operation is done at bit level: for example, output data 0x11223344 is converted into

0x22CC4488.

The CRC calculator can be initialized to a programmable value using the RESET control bit in the CRC_CR register (the default value is 0xFFFFFFFF).

The initial CRC value can be programmed with the CRC_INIT register. The CRC_DR register is automatically initialized upon CRC_INIT register write access.

The CRC_IDR register can be used to hold a temporary value related to CRC calculation. It is not affected by the RESET bit in the CRC_CR register.

Polynomial programmability

The polynomial coefficients are fully programmable through the CRC_POL register, and the polynomial size can be configured to be 7, 8, 16 or 32 bits by programming the

POLYSIZE[1:0] bits in the CRC_CR register. Even polynomials are not supported.

The type of an even polynomial is X+X

+..+X n

, while the type of an odd polynomial is

1+X+X

+..+X n

If the CRC data is less than 32-bit, its value can be read from the least significant bits of the

CRC_DR register.

To obtain a reliable CRC calculation, the change on-fly of the polynomial value or size can not be performed during a CRC calculation. As a result, if a CRC calculation is ongoing, the application must either reset it or perform a CRC_DR read before changing the polynomial.

The default polynomial value is the CRC-32 (Ethernet) polynomial: 0x4C11DB7.

100/784 RM0451 Rev 3

RM0451 Cyclic redundancy check calculation unit (CRC)

The CRC_DR register can be accessed by words, right-aligned half-words and right-aligned bytes. For the other registers only 32-bit accesses are allowed.

4.4.1

31 rw

15 rw

CRC data register (CRC_DR)

Address offset: 0x00

Reset value: 0xFFFF FFFF

30 29 rw

14 rw

28 rw

27 rw

26 rw

25 rw

24 23

DR[31:16] rw

8 rw

DR[15:0] rw rw

22 rw

21 rw

20 rw

19 rw

18 rw

17 rw

16 rw

0 rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 DR[31:0]: Data register bits

This register is used to write new data to the CRC calculator.

It holds the previous CRC calculation result when it is read.

If the data size is less than 32 bits, the least significant bits are used to write/read the correct value.

4.4.2

Res.

CRC independent data register (CRC_IDR)

Address offset: 0x04

Reset value: 0x0000 0000

Res.

7 6 5 4

IDR[7:0]

3 rw rw

2 1 0 rw rw rw rw rw

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 IDR[7:0] : General-purpose 8-bit data register bits

These bits can be used as a temporary storage location for one byte.

This register is not affected by CRC resets generated by the RESET bit in the CRC_CR register rw

RM0451 Rev 3 101/784

104

Cyclic redundancy check calculation unit (CRC) RM0451

4.4.3

Res.

CRC control register (CRC_CR)

Address offset: 0x08

Reset value: 0x0000 0000

Res.

REV_

OUT rw

6 5

REV_IN[1:0] rw rw

4 3

POLYSIZE[1:0] rw rw

Res.

1 0

Res.

RESET rs

Bits 31:8 Reserved, must be kept at reset value.

Bit 7 REV_OUT : Reverse output data

This bit controls the reversal of the bit order of the output data.

0: Bit order not affected

1: Bit-reversed output format

Bits 6:5 REV_IN[1:0] : Reverse input data

These bits control the reversal of the bit order of the input data

00: Bit order not affected

01: Bit reversal done by byte

10: Bit reversal done by half-word

11: Bit reversal done by word

Bits 4:3 POLYSIZE[1:0] : Polynomial size

These bits control the size of the polynomial.

00: 32 bit polynomial

01: 16 bit polynomial

10: 8 bit polynomial

11: 7 bit polynomial

Bits 2:1 Reserved, must be kept at reset value.

Bit 0 RESET : RESET bit

This bit is set by software to reset the CRC calculation unit and set the data register to the value stored in the CRC_INIT register. This bit can only be set, it is automatically cleared by hardware

102/784 RM0451 Rev 3

RM0451 Cyclic redundancy check calculation unit (CRC)

4.4.4

31 rw

15 rw

CRC initial value (CRC_INIT)

Address offset: 0x10

Reset value: 0xFFFF FFFF

30 29 rw

14 rw

28 rw

27 rw

26 rw

25 rw

24 23

CRC_INIT[31:16] rw

8 rw

CRC_INIT[15:0] rw rw

22 rw

6 rw rw rw rw rw rw rw

Bits 31:0 CRC_INIT[31:0] : Programmable initial CRC value

This register is used to write the CRC initial value.

21 rw

5 rw

20 rw

4 rw

19 rw

3 rw

18 rw

2 rw

17 rw

1 rw

16 rw

0 rw

4.4.5

31 rw

15 rw

CRC polynomial (CRC_POL)

Address offset: 0x14

Reset value: 0x04C1 1DB7

30 29 rw

14 rw

28 rw

27 rw

26 rw

25 rw

24 23

POL[31:16] rw

8 rw

POL[15:0] rw rw

22 rw

21 rw

20 rw

19 rw

18 rw

17 rw

16 rw

0 rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 POL[31:0] : Programmable polynomial

This register is used to write the coefficients of the polynomial to be used for CRC calculation.

If the polynomial size is less than 32 bits, the least significant bits have to be used to program the correct value.

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Cyclic redundancy check calculation unit (CRC) RM0451

4.4.6

Offset

0x00

0x04

CRC register map

Table 25. CRC register map and reset values

Register name

CRC_DR

Reset value

CRC_IDR

DR[31:0]

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

IDR[7:0]

Reset value 0 0 0 0 0 0 0 0

CRC_CR

0x08

0x10

0x14

Reset value

CRC_INIT

Reset value

CRC_POL

Reset value

0 0 0 0 0 0

CRC_INIT[31:0]

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

POL[31:0]

0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 1 0 0 0 1 1 1 0 1 1 0 1 1 0 1 1 1

Refer to Section 2.2 on page 39 for the register boundary addresses.

104/784 RM0451 Rev 3

RM0451 Firewall (FW)

5.1 Introduction

The Firewall is made to protect a specific part of code or data into the Non-Volatile Memory, and/or to protect the Volatile data into the SRAM from the rest of the code executed outside the protected area.

5.2 Firewall main features

• The code to protect by the Firewall (Code Segment) may be located in:

– The Flash program memory map

– The SRAM memory, if declared as an executable protected area during the

Firewall configuration step.

• The data to protect can be located either

– in the Flash program or the Data EEPROM memory (non-volatile data segment)

– in the SRAM memory (volatile data segment)

The software can access these protected areas once the Firewall is opened. The Firewall can be opened or closed using a mechanism based on “call gate” (Refer to

Opening the

Firewall ).

The start address of each segment and its respective length must be configured before

enabling the Firewall (Refer to Section 5.3.5: Firewall initialization

Each illegal access into these protected segments (if the Firewall is enabled) generates a reset which immediately kills the detected intrusion.

Any DMA access to protected segments is forbidden whatever the Firewall state (opened or closed). It is considered as an illegal access and generates a reset.

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Firewall (FW) RM0451

5.3.1 Firewall AMBA bus snoop

The Firewall peripheral is snooping the AMBA buses on which the memories (volatile and non-volatile) are connected. A global architecture view is illustrated in

Figure 8 .

Figure 8. STM32L010xx firewall connection schematics

CORTEX M0+

AHB Master 1

DMA

AHB Master 2 M

A

T

R

B

U

S

I

X

AHB Slave

FIREWALL

E Flash program memory and data

EEPROM

SRAM

AHB Slave

MS32388V3

106/784

There are several requirements to guaranty the highest security level by the application code/data which needs to be protected by the Firewall and to avoid unwanted Firewall alarm

(reset generation).

Debug consideration

In debug mode, if the Firewall is opened, the accesses by the debugger to the protected segments are not blocked. For this reason, the Read out level 2 protection must be active in conjunction with the Firewall implementation.

If the debug is needed, it is possible to proceed in the following way:

• A dummy code having the same API as the protected code may be developed during the development phase of the final user code. This dummy code may send back coherent answers (in terms of function and potentially timing if needed), as the protected code should do in production phase.

• In the development phase, the protected code can be given to the customer-end under

NDA agreement and its software can be developed in level 0 protection. The customerend code needs to embed an IAP located in a write protected segment in order to allow future code updates when the production parts will be Level 2 ROP.

RM0451 Rev 3

RM0451 Firewall (FW)

Write protection

In order to offer a maximum security level, the following points need to be respected:

• It is mandatory to keep a write protection on the part of the code enabling the Firewall.

This activation code should be located outside the segments protected by the Firewall.

• The write protection is also mandatory on the code segment protected by the Firewall.

• The page including the reset vector must be write-protected.

Interrupts management

The code protected by the Firewall must not be interruptible. It is up to the user code to disable any interrupt source before executing the code protected by the Firewall. If this constraint is not respected, if an interrupt comes while the protected code is executed

(Firewall opened), the Firewall will be closed as soon as the interrupt subroutine is executed. When the code returns back to the protected code area, a Firewall alarm will raise since the “call gate” sequence will not be applied and a reset will be generated.

Concerning the interrupt vectors and the first user page in the Flash program memory:

• If the first user page (including the reset vector) is protected by the Firewall, the NVIC vector should be reprogrammed outside the protected segment.

• If the first user page is not protected by the Firewall, the interrupt vectors may be kept at this location.

There is no interrupt generated by the Firewall.

The Firewall has been designed to protect three different segment areas:

Code segment

This segment is located into the Flash program memory. It should contain the code to execute which requires the Firewall protection. The segment must be reached using the

“call gate” entry sequence to open the Firewall. A system reset is generated if the “call gate” entry sequence is not respected (refer to

Opening the Firewall

) and if the Firewall is enabled using the FWDIS bit in the system configuration register. The length of the segment and the segment base address must be configured before enabling the Firewall (refer to

Section 5.3.5: Firewall initialization

Non-volatile data segment

This segment contains non-volatile data used by the protected code which must be

protected by the Firewall. The access to this segment is defined into Section 5.3.4: Segment accesses and properties

. The Firewall must be opened before accessing the data in this area. The Non-Volatile data segment should be located into the Flash program or 512-byte

Data EEPROM memory. The segment length and the base address of the segment must be configured before enabling the Firewall (refer to

Section 5.3.5: Firewall initialization

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Firewall (FW) RM0451

Volatile data segment

Volatile data used by the protected code located into the code segment must be defined into the SRAM memory. The access to this segment is defined into the

Section 5.3.4: Segment accesses and properties

. Depending on the Volatile data segment configuration, the

Firewall must be opened or not before accessing this segment area. The segment length and the base address of the segment as well as the segment options must be configured before enabling the Firewall (refer to

Section 5.3.5: Firewall initialization

The Volatile data segment can also be defined as executable (for the code execution) or shared using two bit of the Firewall configuration register (bit VDS for the volatile data sharing option and bit VDE for the volatile data execution capability). For more details, refer to

Table 26 .

All DMA accesses to the protected segments are forbidden, whatever the Firewall state, and generate a system reset.

Segment access depending on the Firewall state

Each of the three segments has specific properties which are presented in

Table 26 .

Segment

Code segment

Non-volatile data segment

Volatile data segment

Table 26. Segment accesses according to the Firewall state

Firewall opened access allowed

Firewall closed access allowed

Firewall disabled access allowed

Read and execute

Read and write

Read and Write

Execute if VDE = 1 and

VDS = 0 into the Firewall configuration register

No access allowed.

Any access to the segment

(except the “call gate” entry) generates a system reset

All accesses are allowed

(according to the EEPROM protection properties in which the code is located)

No access allowed

All accesses are allowed

(according to the EEPROM protection properties in which the code is located)

No access allowed if VDS = 0 and VDE = 0 into the Firewall configuration register

Read/write/execute accesses allowed if VDS = 1 (whatever

VDE bit value)

Execute if VDE = 1 and VDS = 0 but with a “call gate” entry to open the Firewall at first.

All accesses are allowed

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RM0451 Firewall (FW)

The Volatile data segment is a bit different from the two others. The segment can be:

• Shared (VDS bit in the register)

It means that the area and the data located into this segment can be shared between the protected code and the user code executed in a non-protected area. The access is allowed whether the Firewall is opened or closed or disabled.

The VDS bit gets priority over the VDE bit, this last bit value being ignored in such a case. It means that the Volatile data segment can execute parts of code located there without any need to open the Firewall before executing the code.

• Execute

The VDE bit is considered as soon as the VDS bit = 0 in the FW_CR register. If the

VDS bit = 1, refer to the description above on the Volatile data segment sharing. If VDS

= 0 and VDE = 1, the Volatile data segment is executable. To avoid a system reset generation from the Firewall, the “call gate” sequence should be applied on the Volatile data segment to open the Firewall as an entry point for the code execution.

Segments properties

Each segment has a specific length register to define the segment size to be protected by the Firewall: CSL register for the Code segment length register, NVDSL for the Non-volatile data segment length register, and VDSL register for the Volatile data segment length register. Granularity and area ranges for each of the segments are presented in

Table 27 .

Segment

Table 27. Segment granularity and area ranges

Granularity Area range

Code segment

Non-volatile data segment

Volatile data segment

256 byte up to 64 Kbytes - 256 bytes

64 byte 8 Kbytes - 64 bytes

The initialization phase should take place at the beginning of the user code execution (refer to the

Write protection ).

The initialization phase consists of setting up the addresses and the lengths of each segment which needs to be protected by the Firewall. It must be done before enabling the

Firewall, because the enabling bit can be written once. Thus, when the Firewall is enabled, it cannot be disabled anymore until the next system reset.

Once the Firewall is enabled, the accesses to the address and length segments are no longer possible. All write attempts are discarded.

A segment defined with a length equal to 0 is not considered as protected by the Firewall.

As a consequence, there is no reset generation from the Firewall when an access to the base address of this segment is performed.

After a reset, the Firewall is disabled by default (FWDIS bit in the SYSCFG register is set). It has to be cleared to enable the Firewall feature.

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Firewall (FW) RM0451

Below is the initialization procedure to follow:

Configure the RCC to enable the clock to the Firewall module

2. Configure the RCC to enable the clock of the system configuration registers

3. Set the base address and length of each segment (CSSA, CSL, NVDSSA, NVDSL,

VDSSA, VDSL registers)

4. Set the configuration register of the Firewall (FW_CR register)

5. Enable the Firewall clearing the FWDIS bit in the system configuration register.

The Firewall configuration register (FW_CR register) is the only one which can be managed in a dynamic way even if the Firewall is enabled:

• when the Non-Volatile data segment is undefined (meaning the NVDSL register is equal to 0), the accesses to this register are possible whatever the Firewall state

(opened or closed).

• when the Non-Volatile data segment is defined (meaning the NVDSL register is different from 0), the accesses to this register are only possible when the Firewall is opened.

The Firewall has three different states as shown in

Figure 9 :

• Disabled: The FWDIS bit is set by default after the reset. The Firewall is not active.

• Closed: The Firewall protects the accesses to the three segments (Code, Non-volatile data, and Volatile data segments).

• Opened: The Firewall allows access to the protected segments as defined in

Section 5.3.4: Segment accesses and properties

Figure 9. Firewall functional states

Firewall disable

(reset)

Illegal accesses to the protected segments

Enable the firewall

(FWDIS = 0)

Protected code jumps to an unprotected segment and FPA = 0

‘‘call gate’’ entry

Firewall

closed

Firewall opened

Code protected jumps

to unprotected segments

MS32390V4

110/784 RM0451 Rev 3

RM0451 Firewall (FW)

Opening the Firewall

As soon as the Firewall is enabled, it is closed. It means that most of the accesses to the protected segments are forbidden (refer to

Section 5.3.4: Segment accesses and properties ). In order to open the Firewall to interact with the protected segments, it is

mandatory to apply the “call gate” sequence described hereafter.

“call gate” sequence

The “call gate” is composed of 3 words located on the first three 32-bit addresses of the base address of the code segment and of the Volatile data segment if it is declared as not shared (VDS = 0) and executable (VDE = 1).

– 1st word: Dummy 32-bit words always closed in order to protect the “call gate” opening from an access due to a prefetch buffer.

– 2nd and 3rd words: 2 specific 32-bit words called “call gate” and always opened.

To open the Firewall, the code currently executed must jump to the 2 nd word of the “call gate” and execute the code from this point. The 2nd word and 3rd word execution must not be interrupted by any intermediate instruction fetch; otherwise, the Firewall is not considered open and comes back to a close state. Then, executing the 3 rd word after receiving the intermediate instruction fetch would generate a system reset as a consequence.

As soon as the Firewall is opened, the protected segments can be accessed as described in

Section 5.3.4: Segment accesses and properties .

Closing the Firewall

The Firewall is closed immediately after it is enabled (clearing the FWDIS bit in the system configuration register).

To close the Firewall, the protected code must:

• Write the correct value in the Firewall Pre Arm Flag into the FW_CR register.

• Jump to any executable location outside the Firewall segments.

If the Firewall Pre Arm Flag is not set when the protected code jumps to a non protected segment, a reset is generated. This control bit is an additional protection to avoid an undesired attempt to close the Firewall with the private information not yet cleaned (see the note below).

For security reasons, following the application for which the Firewall is used, it is advised to clean all private information from CPU registers and hardware cells.

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Firewall (FW) RM0451

Res.

Address offset: 0x00

Reset value: 0x0000 0000

29 28 27 26 25

Res.

15 14 13 12

ADD[15:8]

11 rw

10 9 8

Res.

22 21

Res.

20 19

ADD[23:16]

Res.

18 17 16

Res.

5.4.2

31 30

Code segment length (FW_CSL)

Address offset: 0x04

Reset value: 0x0000 0000

29 28 27 26 25 24 23

Res.

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:8 ADD[23:8]: code segment start address

The LSB bits of the start address (bit 7:0) are reserved and forced to 0 in order to allow a

256-byte granularity.

Note: These bits can be written only before enabling the Firewall. Refer to

Section 5.3.5:

Firewall initialization .

Bits 7:0 Reserved, must be kept at the reset value.

14 13 12 11

LENG15:8] rw

10 9 8

Res.

21 20

Res.

19 18

LENG[21:16] rw

Res.

17 16

Res.

Bits 31:22 Reserved, must be kept at the reset value.

Bits 21:8 LENG[21:8] : code segment length

LENG[21:8] selects the size of the code segment expressed in bytes but is a multiple of

256 bytes.

The segment area is defined from {ADD[23:8],0x00} to {ADD[23:8]+LENG[21:8], 0x00} - 0x01

Note: If LENG[21:8] = 0 after enabling the Firewall, this segment is not defined, thus not protected by the Firewall.

These bits can only be written before enabling the Firewall. Refer to Section 5.3.5:

Firewall initialization

Bits 7:0 Reserved, must be kept at the reset value.

112/784 RM0451 Rev 3

RM0451 Firewall (FW)

Res.

Address offset: 0x08

Reset value: 0x0000 0000

29 28 27 26 25

Res.

15 14 13 12

ADD[15:8]

11 rw

10 9 8

Res.

22 21

Res.

20 19

ADD[23:16]

Res.

18 17 16

Res.

Bits 31:24 Reserved, must be kept at the reset value.

Bits 23:8 ADD[23:8]: Non-volatile data segment start address

The LSB bits of the start address (bit 7:0) are reserved and forced to 0 in order to allow a

256-byte granularity.

Note: These bits can only be written before enabling the Firewall. Refer to

Section 5.3.5:

Firewall initialization .

Bits 7:0 Reserved, must be kept at the reset value.

Res.

Address offset: 0x0C

Reset value: 0x0000 0000

29 28 27 26

Res.

15 14 13 12 11

LENG[15:8] rw

10 9

Res.

8 7

Res.

21 20

Res.

19 18

LENG[21:16] rw

3 2

Res.

17 16

Res.

Bits 31:22 Reserved, must be kept at the reset value.

Bits 21:8 LENG[21:8] : Non-volatile data segment length

LENG[21:8] selects the size of the Non-volatile data segment expressed in bytes but is a multiple of 256 bytes.

The segment area is defined from {ADD[23:8],0x00} to {ADD[23:8]+LENG[21:8], 0x00} - 0x01

Note: If LENG[21:8] = 0 after enabling the Firewall, this segment is not defined, thus not protected by the Firewall.

These bits can only be written before enabling the Firewall. Refer to Section 5.3.5:

Firewall initialization

Bits 7:0 Reserved, must be kept at the reset value.

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Firewall (FW) RM0451

Res.

Address offset: 0x10

Reset value: 0x0000 0000

29 28 27 26 25

Res.

15 14 13 12 11 10

ADD[15:6] rw

9 8 7 6 5

Res.

Bits 31:16 Reserved, must be kept at the reset value.

Bits 15:6 ADD[15:6]: Volatile data segment start address

The LSB bit of the start address (bits 5:0) are reserved and forced to 0 in order to allow a

64-byte granularity.

Note: These bits can only be written before enabling the Firewall. Refer to

Section 5.3.5:

Firewall initialization .

Bits 5:0 Reserved, must be kept at the reset value.

5.4.6

31 30

Volatile data segment length (FW_VDSL)

Address offset: 0x14

Reset value: 0x0000 0000

29 28 27 26 25 24 23 22

Res.

15 14 13 12 11 10

LENG[15:6] rw

9 8 7 6 5

Res.

Bits 31:16 Reserved, must be kept at the reset value.

Bits 15:6 LENG[15:6] : Volatile data segment length

LENG[15:6] selects the size of the volatile data segment expressed in bytes but is a multiple of 64 bytes.

The segment area is defined from {ADD[15:6],0x00} to {ADD[15:6]+LENG[15:6], 0x00} - 0x01

Note: If LENG[15:6] = 0 after enabling the Firewall, this segment is not defined, thus not protected by the Firewall.

These bits can only be written before enabling the Firewall. Refer to Section 5.3.5:

Firewall initialization

Bits 5:0 Reserved, must be kept at the reset value.

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RM0451 Firewall (FW)

Res.

Address offset: 0x20

Reset value: 0x0000 0000

29 28 27 26

Res.

VDE rw

VDS rw

FPA rw

Bits 31:3 Reserved, must be kept at the reset value.

Bit 2 VDE : Volatile data execution

0: Volatile data segment cannot be executed if VDS = 0

1: Volatile data segment is declared executable whatever VDS bit value

When VDS = 1, this bit has no meaning. The Volatile data segment can be executed whatever the VDE bit value.

If VDS = 1, the code can be executed whatever the Firewall state (opened or closed)

If VDS = 0, the code can only be executed if the Firewall is opened or applying the “call gate” entry sequence if the Firewall is closed.

Refer to Segment access depending on the Firewall state

Bit 1 VDS : Volatile data shared

0: Volatile data segment is not shared and cannot be hit by a non protected executable code when the Firewall is closed. If it is accessed in such a condition, a system reset will be generated by the Firewall.

1: Volatile data segment is shared with non protected application code. It can be accessed whatever the Firewall state (opened or closed).

Refer to Segment access depending on the Firewall state

Bit 0 FPA : Firewall prearm

0: any code executed outside the protected segment when the Firewall is opened will generate a system reset.

1: any code executed outside the protected segment will close the Firewall.

Refer to Closing the Firewall .

This register is protected in the same way as the Non-volatile data segment (refer to

Section 5.3.5: Firewall initialization

) .

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5.4.8

Offset

Firewall register map

The table below provides the Firewall register map and reset values.

Table 28. Firewall register map and reset values

Register

0x0

0x4

0x8

0xC

0x10

0x14

FW_CSSA

Reset Value

FW_CSL

Reset Value

FW_NVDSSA

Reset Value

FW_NVDSL

Reset Value

FW_VDSSA

Reset Value

FW_VDSL

ADD

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

LENG

0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADD

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

LENG

0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADD

0 0 0 0 0 0 0 0 0 0

0x18

Reset Value

0x1C

0x20

Reset Value

FW_CR

Reset Value

Refer to Section 2.2 on page 39 for the register boundary addresses.

RM0451

0 0 0

116/784 RM0451 Rev 3

RM0451

6 Power control (PWR)

Power control (PWR)

The device requires a 1.8-to-3.6 V V

DD operating voltage supply.

An embedded linear voltage regulator is used to supply the internal digital power, ranging from 1.2 to 1.8 V.

• V

= 1.8 to 3.6 V

is the external power supply for I/Os and internal regulator. It is provided externally through V

pins

• V

CORE

= 1.2 to 1.8 V

CORE is the power supply for digital peripherals, SRAM and Flash memory. It is generated by a internal voltage regulator. Three V

CORE software depending on V

(refer Figure 11

ranges can be selected by

• V

SSA

, V

DDA

= 1.8 to 3.6 V

DDA is the external analog power supply for ADC, reset blocks, RC oscillators and

PLL. For category 1 devices in low-pin count packages, V

DDA the corresponding datasheets for more details). is bonded to V

(refer to

Figure 10. Power supply overview

(VDD) VDDA

(VSS) VSSA

VSS

VDD

VDDA domain

ADC

Temp. Sensor

Reset block

PLL

VDD domain

Flash memory

IO supply

Standby circuitry(Wakeup logic, IWDG, RTC,

LSE crystal 32K osc., RCC)

Voltage regulator

Dynamic voltage scaling

VCore domain

Core memories

Digital peripherals

MSv46193V1

1. V

DDA

and V

SSA must be connected to V

and V

, respectively.

2. Depending on the operating power supply range used, some peripherals may be used with limited features or performance. For more details, please refer to section "General operating conditions" in STM32L010xx datasheets.

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Power control (PWR) RM0451

6.1.1 Independent supply

Note:

To improve conversion accuracy, the ADC has an independent power supply that can be filtered separately, and shielded from noise on the PCB.

• The ADC voltage supply input is available on a separate V

DDA

• An isolated supply ground connection is provided on the V

SSA

For category 1 devices in 14-pin package, V

DDA

is internally connected to V

6.1.2 RTC and RTC backup registers

The real-time clock (RTC) is an independent BCD timer/counter. The RTC provides a timeof-day clock/calendar, two programmable alarm interrupts, and a periodic programmable wakeup flag with interrupt capability. The RTC contains 5 backup data registers (20 bytes).

These backup registers are reset when a tamper detection event occurs. For more details refer to Real-time clock (RTC) section.

RTC registers access

After reset, the RTC Registers (RTC registers and RTC backup registers) are protected against possible stray write accesses. To enable access to the RTC Registers, proceed as follows:

Enable the power interface clock by setting the PWREN bits in the RCC_APB1ENR register.

2. Set the DBP bit in the PWR_CR register (see

Section 6.4.1

3. Select the RTC clock source through RTCSEL[1:0] bits in RCC_CSR register.

4. Enable the RTC clock by programming the RTCEN bit in the RCC_CSR register.

An embedded linear voltage regulator supplies all the digital circuitries except for the

Standby circuitry. The regulator output voltage (V

CORE

) can be programmed by software to

three different ranges within 1.2 - 1.8 V (typical) (see Section 6.1.4

The voltage regulator is always enabled after Reset. It works in three different modes: main

(MR), low-power (LPR) and power-down, depending on the application modes.

• In Run mode, the regulator is main (MR) mode and supplies full power to the V

CORE domain (core, memories and digital peripherals).

• In Low-power run mode, the regulator is in low-power (LPR) mode and supplies lowpower to the V

CORE

domain, preserving the contents of the registers and internal

SRAM.

• In Sleep mode, the regulator is main (MR) mode and supplies full power to the V

CORE domain, preserving the contents of the registers and internal SRAM.

• In Low-power sleep mode, the regulator is in low-power (LPR) mode and supplies lowpower to the V

CORE

domain, preserving the contents of the registers and internal

SRAM.

• In Stop mode the regulator supplies low power to the V

CORE content of registers and internal SRAM.

domain, preserving the

• In Standby mode, the regulator is powered off. The content of the registers and SRAM are lost except for the Standby circuitry.

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The dynamic voltage scaling is a power management technique which consists in increasing or decreasing the voltage used for the digital peripherals (V

CORE the circumstances.

), according to

Dynamic voltage scaling to increase V

CORE

is known as overvolting. It allows improving the

device performance. Refer to Figure 11 for a description of the device operating conditions

versus CPU performance and to the datasheet electrical characteristics for ADC clock frequency versus dynamic range.

Dynamic voltage scaling to decrease V

CORE

is known as undervolting. It is performed to save power, particularly in laptops and other mobile devices where the energy comes from a battery and is thus limited.

Range 1

Range 1 is the “high performance” range.

The voltage regulator outputs a 1.8 V voltage (typical). Flash program and erase operations can be performed in this range.

When V

is below 2.0 V, the CPU frequency changes from initial to final state must respect the following conditions:

• f

CPUfinal

< 4xf

CPUinitial

• In addition, a 5 μ s delay must be respected between two changes. For example to switch from 4.2 to 32 MHz, switch from 4.2 to 16 MHz, wait for 5 μ s, then switch from

16 to 32 MHz.

Range 2 and 3

The regulator can also be programmed to output a regulated 1.5 V (typical, range 2) or a

1.2 V (typical, range 3) without any limitations on V

(1.8 to 3.6 V).

• At 1.5 V, the Flash memory is still functional but with medium read access time. This is the “medium performance” range. Program and erase operations on the Flash memory are still possible.

• At 1.2 V, the Flash memory is still functional but with slow read access time. This is the

“low performance” range. Program and erase operations on the Flash memory are not possible under these conditions.

Refer to Table 29

for details on the performance for each range.

CPU performance

High

Medium

Low

Table 29. Performance versus V

CORE

ranges

Power performance

CORE range

Typical

Value (V)

Max frequency

(MHz)

1 WS 0 WS

Low

Medium

High

1.8

1.5

1.2

4.2

range

1.8 - 3.6

RM0451 Rev 3 119/784

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Power control (PWR) RM0451

Figure 11. Performance versus V

and V

CORE

range

MH z

VCORE

4.2 MHz

0WS

1.2 V

16 MHz

CPU

> 8 MHz

1WS

8 MHz

0WS

1.5 V

32 MHz

CPU

> 16 MHz

16 MHz

1WS

1.8 V

0WS

Range 1

Range 2

Range 3

MSv46196V1

Note:

6.1.6

The following sequence is required to program the voltage regulator ranges:

Check V

to identify which ranges are allowed (see Figure 11: Performance versus

VDD and VCORE range ).

2. Poll VOSF bit of in PWR_CSR. Wait until it is reset to 0.

3. Configure the voltage scaling range by setting the VOS[1:0] bits in the PWR_CR register.

4. Poll VOSF bit of in PWR_CSR register. Wait until it is reset to 0.

During voltage scaling configuration, the system clock is stopped until the regulator is stabilized (VOSF=0). This must be taken into account during application development, in case a critical reaction time to interrupt is needed, and depending on peripheral used (timer, communication,...).

Voltage regulator and clock management when modifying the

V

CORE

range

When V

is above 1.8 V, any of the 3 voltage ranges can be selected:

• When the voltage range is above the targeted voltage range (e.g. from range 1 to 2): a) Adapt the clock frequency to the lower voltage range that will be selected at next step.

b) Select the required voltage range.

• When the voltage range is below the targeted voltage range (e.g. from range 3 to 1): a) Select the required voltage range.

b) Tune the clock frequency if needed.

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and limitations when V

ranges from 1.8 V to 2.0 V

The STM32L010xx voltage regulator is based on an architecture designed for Ultra-lowpower. It does not use any external capacitor. Such regulator is sensitive to fast changes of load. In this case, the output voltage is reduced for a short period of time. Considering that the core voltage must be higher than 1.8 V to ensure a 32 MHz operation, this phenomenon is critical for very low V

voltages (e.g. 1.8 V V

DD minimum value).

To guarantee 32 MHz operation at V

= 1.8 V ± 5%, with 1 wait state, and V

CORE

range 1, the CPU frequency in run mode must be managed to prevent any changes exceeding a ratio of 4 in one shot. A delay of 5 μ s must be respected between 2 changes. There is no limitation when waking up from low-power mode.

The device has an integrated zeropower power-on reset (POR)/power-down reset (PDR), coupled with a brownout reset (BOR) circuitry. The BOR is always active at power-on and ensures proper operation starting from 1.8 V. After the 1.8 V BOR threshold is reached, the option byte loading process starts, either to confirm or modify default thresholds, or to disable BOR permanently (in which case, the V

min value at power-down is set to V

PDR

Five BOR thresholds can be configured by option bytes, starting from 1.8 to 3 V. To reduce the power consumption in Stop mode, the internal voltage reference, V

REFINT automatically switch off. The device remains in reset mode when V

DD threshold, V

POR

, V

PDR

or V

BOR

, can be

is below a specified

, without the need for any external reset circuit.

The different power supply supervisor (POR, PDR, BOR) are illustrated in Figure 12 .

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Power control (PWR)

Figure 12. Power supply supervisors

DD A

BOR

100 mV hysteresis

POR

PDR

RM0451

122/784

BOR reset

(NRST)

BOR/PDR reset

(NRST)

BOR always active

BOR disabled by option byte

1. When the BOR is disabled by option byte, the reset is asserted when V

goes below PDR level

MSv46197V2

The device has an integrated POR/PDR circuitry that allows operation down to 1.5 V.

During power-on, the device remains in Reset mode when V

DD threshold, V

POR enabled and the POR threshold is 1.5 V.

DDA is below a specified

, without the need for an external reset circuit. The POR feature is always

During power-down, the PDR keeps the device under reset when the supply voltage (V

DD drops below the V

PDR is 1.5 V.

)

threshold. The PDR feature is always enabled and the PDR threshold

The POR and PDR are used only when the BOR is disabled (see

Section 6.2.2: Brownout reset (BOR))

). To insure the minimum operating voltage (1.8 V), the BOR should be configured to BOR Level 1. When the BOR is disabled, a “gray zone” exist between the minimum operating voltage (1.8 V) and the V

POR

PDR be lower than 1.8 V without device reset until the V

PDR

threshold. This means that V

threshold is reached.

can

For more details concerning the power-on/power-down reset threshold, refer to the electrical characteristics of the datasheet.

RM0451 Rev 3

RM0451 Power control (PWR)

Figure 13. Power-on reset/power-down reset waveform

VDD/VDDA

POR

PDR

Temporization tRSTTEMPO

Reset

MS32793V1

During power-on, the Brownout reset (BOR) keeps the device under reset until the supply voltage reaches the specified V

BOR threshold.

The BOR is always active at power-on and it's threshold is 1.8 V.

Then when the system reset is released, the BOR level can be reconfigured or disabled by option byte loading.

If the BOR level is kept at the lowest level (1.8 V), the system reset is fully managed by the

BOR and the product operating voltages are within safe ranges.

And when the BOR option is disabled by option byte, the power-down reset is controlled by the PDR and a “gray zone” exists between the 1.8 V and V

PDR

BOR

is configured through device option bytes. By default, the Level 4 threshold is activated. 5 programmable V

BOR

thresholds can be selected.

• BOR Level 1 (V

BOR0

): reset threshold level for 1.69 to 1.80 V voltage range

• BOR Level 2 (V

BOR1

): reset threshold level for 1.94 to 2.1 V voltage range

• BOR Level 3 (V

BOR2

): reset threshold level for 2.3 to 2.49 V voltage range

• BOR Level 4 (V

BOR3

): reset threshold level for 2.54 to 2.74 V voltage range

• BOR Level 5 (V

BOR4

): reset threshold level for 2.77 to 3.0 V voltage range

When the supply voltage (V generated. When the V

DD system can start.

) drops below the selected V

BOR is above the V

BOR

threshold, a device reset is upper limit the device reset is released and the

BOR can be disabled by programming the device option bytes. To disable the BOR function,

must have been higher than V

BOR0

to start the device option byte programming sequence. The power-on and power-down is then monitored by the POR and PDR (see

Section 6.2.1: Power-on reset (POR)/power-down reset (PDR) )

The BOR threshold hysteresis is ~100 mV (between the rising and the falling edge of the supply voltage).

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VDD/VDDA

Figure 14. BOR thresholds

BOR threshold

100mV hysteresis

RM0451

6.2.3

Reset

MS32794V1

Internal voltage reference (V

REFINT

)

The internal reference (V

REFINT

) provides stable voltage for analog peripherals. The functions managed through the internal voltage reference (V

REFINT comparators. The internal voltage reference (V features is used.

REFINT

) are BOR, ADC and

) is always enabled when one of these

The internal voltage reference consumption is not negligible, in particular in Stop and

Standby mode. To reduce power consumption, the ULP bit (ultra-low-power) in the

PWR_CR register can be set to disable the internal voltage reference. However, in this case, when exiting from the Stop/Standby mode, the functions managed through the internal voltage reference are not reliable during the internal voltage reference startup time (up to

3 ms).

To reduce the wakeup time, the device can exit from Stop/Standby mode without waiting for the internal voltage reference startup time. This is performed by setting the FWU bit (Fast wakeup) in the PWR_CR register before entering Stop/Standby mode.

If the ULP bit is set, the functions that were enabled before entering Stop/Standby mode will be disabled during these modes, and enabled again only after the end of the internal voltage reference startup time whatever FWU value. The VREFINTRDYF flag in the PWR_CSR register indicates that the internal voltage reference is ready.

When the device exits from low-power mode on an NRST pulse, it does not wait for internal voltage reference startup (even if ULP=1 and FWU=0). The application should check the

VREFINTRDYF flag if necessary.

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RM0451 Power control (PWR)

By default, the microcontroller is in Run mode after a system or a power-on reset. In Run mode the CPU is clocked by HCLK and the program code is executed. Several low-power modes are available to save power when the CPU does not need to be kept running, for example when waiting for an external event. It is up to the user to select the mode that gives the best compromise between low-power consumption, performance, short startup time and available wakeup sources.

The devices feature five low-power modes:

• Low-power run mode: regulator in low-power mode, limited clock frequency, limited number of peripherals running (refer to

Section 6.3.4

)

• Sleep mode: Cortex

Section 6.3.7

)

-M0+ core stopped, peripherals kept running (refer to

• Low-power sleep mode: Cortex ® -M0+core stopped, limited clock frequency, limited number of peripherals running, regulator in low-power mode, Flash stopped ((refer to

Section 6.3.8

))

• Stop mode (all clocks are stopped, regulator running, regulator in low-power mode

(refer to

Section 6.3.9

)

• Standby mode: V

CORE

domain powered off ((refer to

Section 6.3.10

))

In addition, the power consumption in Run mode can be reduced by one of the following means:

• Slowing down the system clocks

• Gating the clocks to the APBx and AHBx peripherals when they are unused.

Mode name

Low-power run

Sleep

(Sleep now or

Sleep-on-exit)

Low-power sleep (Sleep now or Sleepon-exit)

Entry

LPSDSR and

LPRUN bits +

Clock setting

WFI or Return from ISR

WFE

LPSDSR bits +

WFI or Return from ISR

LPSDSR bits +

WFE

Table 30. Summary of low-power modes

Wakeup

Effect on V

CORE domain clocks

Effect on V

DD domain clocks

Voltage regulator

The regulator is forced in Main regulator (1.8

None None

In low-power mode

Any interrupt

Wakeup event

Any interrupt

Wakeup event

CPU CLK OFF no effect on other clocks or analog clock sources

CPU CLK OFF no effect on other clocks or analog clock sources,

Flash CLK OFF

None

In low-power mode

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Power control (PWR) RM0451

Mode name

Table 30. Summary of low-power modes (continued)

Entry Wakeup

Effect on V

CORE domain clocks

Effect on V

DD domain clocks

Voltage regulator

Stop

Standby

Stop

Standby

PDDS, LPSDSR or LPDS bits +

SLEEPDEEP bit +

WFI, Return from

ISR or WFE

Any EXTI line

(configured in the EXTI registers, internal and external lines)

PDDS bit +

SLEEPDEEP bit +

WFI, Return from

ISR or WFE

WKUP pin rising edge,

RTC alarm (Alarm A or

Alarm B), RTC Wakeup event, RTC tamper event, RTC timestamp event, external reset in

NRST pin, IWDG reset

PDDS, LPSDS and LPDSR bits +

SLEEPDEEP bit +

WFI, Return from

ISR or WFE

Any EXTI line

(configured in the EXTI registers, internal and external lines)

PDDS bit +

SLEEPDEEP bit +

WFI, Return from

ISR or WFE

WKUP pin rising edge,

RTC alarm (Alarm A or

Alarm B), RTC Wakeup event, RTC tamper event, RTC timestamp event, external reset in

NRST pin, IWDG reset

All V

CORE domain clocks

OFF

All V

CORE domain clocks

OFF

HSI16

(1)

, HSE and MSI oscillators

OFF

HSI16

(1)

, HSE

and MSI oscillators

OFF

1. HSI16 can run in Stop mode provided HSI16KERON is set in

Clock control register (RCC_CR) .

In low-power mode

OFF

In low-power mode

OFF

6.3.1 Behavior of clocks in low-power modes

APB peripheral and DMA clocks can be disabled by software.

Sleep and Low-power sleep modes

The CPU clock is stopped in Sleep and Low-power sleep mode. The memory interface clocks (Flash memory and RAM interfaces) and all peripherals clocks can be stopped by software during Sleep. The memory interface clock is stopped and the RAM is in powerdown when in Low-power sleep mode. The AHB to APB bridge clocks are disabled by hardware during Sleep/Low-power sleep mode when all the clocks of the peripherals connected to them are disabled.

Stop and Standby modes

The system clock and all high speed clocks are stopped in Stop and Standby modes:

• PLL is disabled

• Internal RC 16 MHz (HSI16) oscillator is disabled, except if HSI16KERON is set in Stop mode (see

Section 7.3.1: Clock control register (RCC_CR)

)

• External 1-24 MHz (HSE) oscillator is disabled

• Internal 65 kHz - 4.2 MHz (MSI) oscillator is disabled

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When exiting this mode by an interrupt (Stop mode), the internal MSI or HSI16 can be selected as system clock. For both oscillators, their respective configuration (range and trimming) value is kept on Stop mode exit.

When exiting this mode by a reset (Standby mode), the internal MSI oscillator is selected as system clock. The range and the trimming value are reset to the default 2.1 MHz.

If a Flash program operation or an access to APB domain is ongoing, the Stop/Standby mode entry is delayed until the Flash memory or the APB access has completed.

6.3.3

In Run mode the speed of the system clocks (SYSCLK, HCLK, PCLK1, PCLK2) can be reduced by programming the prescaler registers. These prescalers can also be used to slow down peripherals before entering Sleep mode.

For more details refer to Section 7.3.3: Clock configuration register (RCC_CFGR)

Peripheral clock gating

In Run mode, the HCLK and PCLKx for individual peripherals and memories can be stopped at any time to reduce power consumption.

To further reduce power consumption in Sleep mode the peripheral clocks can be disabled prior to executing the WFI or WFE instructions.

Peripheral clock gating is controlled by the AHB peripheral clock enable register

(RCC_AHBENR), APB2 peripheral clock enable register (RCC_APB2ENR), APB1 peripheral clock enable register (RCC_APB1ENR) (see

Section 7.3.12: AHB peripheral clock enable register (RCC_AHBENR) ,

Section 7.3.14: APB1 peripheral clock enable register (RCC_APB1ENR)

and Section 7.3.13: APB2 peripheral clock enable register

(RCC_APB2ENR) ).

Disabling the peripherals clocks in Sleep mode can be performed automatically by resetting the corresponding bit in RCC_AHBLPENR and RCC_APBxLPENR registers (x can 1 or 2).

Note:

To further reduce the consumption when the system is in Run mode, the regulator can be configured in low-power mode. In this mode, the system frequency should not exceed f_MSI range1.

Please refer to the product datasheet for more details on voltage regulator and peripherals operating conditions.

To be able to read the RTC calendar register when the APB1 clock frequency is less than seven times the RTC clock frequency (7*RTCLCK), the software must read the calendar time and date registers twice.

If the second read of the RTC_TR gives the same result as the first read, this ensures that the data is correct. Otherwise a third read access must be done.

Low-power run mode can only be entered when V

CORE

is in range 2. In addition, the dynamic voltage scaling must not be used when Low-power run mode is selected. Only Stop and Sleep modes with regulator configured in low-power mode is allowed when Low-power run mode is selected.

In Low-power run mode, all I/O pins keep the same state as in Run mode.

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Power control (PWR)

6.3.5

6.3.6

RM0451

Entering Low-power run mode

To enter Low-power run mode proceed as follows:

Each digital IP clock must be enabled or disabled by using the RCC_APBxENR and

RCC_AHBENR registers.

2. The frequency of the system clock must be decreased to not exceed the frequency of f_MSI range1.

3. The regulator is forced in low-power mode by software (LPRUN and LPSDSR bits set)

Exiting Low-power run mode

To exit Low-power run mode proceed as follows:

The regulator is forced in Main regulator mode by software.

2. The Flash memory is switched on, if needed.

3. The frequency of the clock system can be increased.

Entering low-power mode

Low-power modes (except for Low-power run mode) are entered by executing the WFI

(Wait For Interrupt) or WFE (Wait for Event) instructions, or when the SLEEPONEXIT bit in

Cortex

-M0+ System Control register is set on Return from ISR.

Entering low-power mode through WFI or WFE will be executed only is no interrupt and no event is pending.

Exiting low-power mode

The microcontroller exists from Sleep and Stop mode depending on the way the mode was entered:

• If the WFI instruction or Return from ISR was used to enter the low-power mode, any peripheral interrupt acknowledged by the NVIC can wake up the device. This includes

EXTI lines and any GPIO toggle.

• If the WFE instruction was used to enter low-power mode, the microcontroller exits the low-power mode as soon as an event occurs. The wakeup event can be generated either by:

– An NVIC IRQ interrupt:

This is done by enabling an interrupt in the peripheral control register but not in the

NVIC, and by enabling the SEVONPEND bit in the Cortex ® -M0+ System Control register. When the microcontroller resumes from WFE, the peripheral interrupt pending bit and the peripheral NVIC IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be cleared.

– An event:

This is done by configuring an external or internal EXTI line in event mode. When the CPU resumes from WFE, it is not necessary to clear the peripheral interrupt pending bit or the NVIC IRQ channel pending bit as the pending bit corresponding to the event line is not set.

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I/O states in Sleep mode

In Sleep mode, all I/O pins keep the same state as in Run mode.

Entering Sleep mode

The Sleep mode is entered according to

Section 6.3.5: Entering low-power mode .

Refer to Table 31: Sleep-now and

Table 32: Sleep-on-exit for details on how to enter Sleep

mode.

Exiting Sleep mode

The Sleep mode is exited according to

Section 6.3.6: Exiting low-power mode

Refer to Table 31: Sleep-now and

Table 32: Sleep-on-exit for more details on how to exit

Sleep mode.

Sleep-now mode

Mode entry

Mode exit

Wakeup latency

Table 31. Sleep-now

Description

WFI (Wait for Interrupt) or WFE (Wait for Event) while:

– SLEEPDEEP = 0 and

– No interrupt (for WFI) or event (for WFE) is pending

Refer to the Cortex ® -M0+ System Control register (see PM0223 programming manual).

On return from ISR while:

– SLEEPDEEP = 0 and

– SLEEPONEXIT = 1 and

– No interrupt is pending

Refer to the Cortex

-M0+ System Control register (see PM0223 programming manual).

If WFI or return from ISR was used for entry:

Interrupt: refer to Table 49: List of vectors

If WFE was used for entry and SVONPEND = 0

Wakeup event: refer to

Section 12.3.2: Wakeup event management

If WFE was used for entry and SVONPEND = 1

Interrupt event when disabled in NVIC (refer to

Table 49: List of vectors)

or wakeup event (refer to

Section 12.3.2: Wakeup event management )

None

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6.3.8

RM0451

Sleep-on-exit

Mode entry

Mode exit

Wakeup latency

Table 32. Sleep-on-exit

Description

WFI (wait for interrupt) while:

– SLEEPDEEP = 0 and

– No interrupt (for WFI) or event (for WFE) is pending

Refer to the Cortex ® -M0+ System Control register (see PM0223 programming manual).

On return from ISR while:

– SLEEPDEEP = 0 and

– SLEEPONEXIT = 1 and

– No interrupt is pending

Refer to the Cortex

-M0+ System Control register (see PM0223 programming manual).

Interrupt: refer to Table 49: List of vectors

None

Low-power sleep mode (LP sleep)

I/O states in Low-power sleep mode

In Low-power sleep mode, all I/O pins keep the same state as in Run mode.

Entering Low-power sleep mode

To enter Low-power sleep mode, proceed as follows:

The Flash memory can be switched off by using the control bits (SLEEP_PD in the

FLASH_ACR register. This reduces power consumption but increases the wake-up time.

2. Each digital IP clock must be enabled or disabled by using the RCC_APBxENR and

RCC_AHBENR registers.

3. The frequency of the system clock must be decreased.

4. The regulator is forced in low-power mode by software (LPSDSR bits set).

5. Follow the steps described in Section 6.3.5: Entering low-power mode

Refer to Table 33: Sleep-now (Low-power sleep)

and Table 34: Sleep-on-exit (Low-power sleep) for details on how to enter Low-power sleep mode.

In Low-power sleep mode, the Flash memory can be switched off and the RAM memory remains available.

In this mode, the system frequency should not exceed f_MSI range1.

Please refer to product datasheet for more details on voltage regulator and peripherals operating conditions.

Low-power sleep mode can only be entered when V

CORE

is in range 2.

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Note:

Power control (PWR)

If the second read of the RTC_TR gives the same result as the first read, this ensures that the data is correct. Otherwise a third read access must be done.

Exiting Low-power sleep mode

The Low-power sleep mode is exited according to Section 6.3.6: Exiting low-power mode

When exiting Low-power sleep mode by issuing an interrupt or a wakeup event, the regulator is configured in Main regulator mode, the Flash memory is switched on (if necessary), and the system clock can be increased.

When the voltage regulator operates in low-power mode, an additional startup delay is incurred when waking up from Low-power sleep mode.

Refer to Table 33: Sleep-now (Low-power sleep)

and Table 34: Sleep-on-exit (Low-power sleep) for more details on how to exit Sleep low-power mode.

Sleep-now mode

Mode entry

Mode exit

Wakeup latency

Table 33. Sleep-now (Low-power sleep)

Description

Voltage regulator in low-power mode and the Flash memory switched off

WFI (Wait for Interrupt) or WFE (wait for event) while:

– SLEEPDEEP = 0 and

– No interrupt (for WFI) or event (for WFE) is pending

Refer to the Cortex

-M0+ System Control register (see PM0223 programming manual).

On return from ISR while:

– SLEEPDEEP = 0 and

– SLEEPONEXIT = 1 and

– No interrupt is pending

Refer to the Cortex

-M0+ System Control register (see PM0223 programming manual).

Voltage regulator in Main regulator mode and the Flash memory switched on

If WFI or Return from ISR was used for entry:

Interrupt: Refer to Table 49: List of vectors

If WFE was used for entry and SEVONPEND = 0

Wakeup event: Refer to Section 12.3.2: Wakeup event management

If WFE was used for entry and SVONPEND = 1

Interrupt event when disabled in NVIC (refer to Table 49: List of vectors)

wakeup event (refer to Section 12.3.2: Wakeup event management

)

Regulator wakeup time from low-power mode

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Sleep-on-exit

Mode entry

Mode exit

Wakeup latency

Table 34. Sleep-on-exit (Low-power sleep)

Description

WFI (wait for interrupt) while:

– SLEEPDEEP = 0 and

– No interrupt (for WFI) or event (for WFE) is pending

Refer to the Cortex ® -M0+ System Control register (see PM0223 programming manual).

On return from ISR while:

– SLEEPDEEP = 0 and

– SLEEPONEXIT = 1 and

– No interrupt is pending

Refer to the Cortex

-M0+ System Control register (see PM0223 programming manual).

Interrupt: refer to Table 49: List of vectors

regulator wakeup time from low-power mode

RM0451

The Stop mode is based on the Cortex ® -M0+ Deepsleep mode combined with peripheral clock gating. The voltage regulator can be configured either in normal or low-power mode.

In Stop mode, all clocks in the V

CORE

domain are stopped, the PLL, the MSI, the HSI16

(except if HSI16KERON is set in Stop mode, see Section 7.3.1: Clock control register

(RCC_CR)

) and the HSE RC oscillators are disabled. Internal SRAM and register contents are preserved.

To get the lowest consumption in Stop mode, the internal Flash memory also enters lowpower mode. When the Flash memory is in power-down mode, an additional startup delay is incurred when waking up from Stop mode.

To minimize the consumption In Stop mode, V

REFINT

and BOR can be switched off before entering Stop mode. This functionality is controlled by the ULP bit in the PWR_CR register.

If the ULP bit is set, the reference is switched off on Stop mode entry and enabled again on wakeup. .

I/O states in Low-power sleep mode

In Stop mode, all I/O pins keep the same state as in Run mode.

Entering Stop mode

Refer to

Section 6.3.5: Entering low-power mode

and to Table 35

for details on how to enter the Stop mode.

If the application needs to disable the external clock before entering Stop mode, the HSEON bit must be first disabled and the system clock switched to HSI16.

Otherwise, if the HSEON bit is kept enabled while external clock (external oscillator) can be removed before entering Stop mode, the clock security system (CSS) feature must be enabled to detect any external oscillator failure and avoid a malfunction behavior when entering Stop mode.

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RM0451 Power control (PWR)

To further reduce power consumption in Stop mode, the internal voltage regulator can be put in low-power mode. This is configured by the LPSDSR or LPDS bit in the PWR_CR register

(see Section 6.4.1

). The internal voltage regulator can also be kept in Main mode but the

consumption will be much higher. As a result, it is always implicitly assumed that the regulator is in low-power mode during Stop mode. The only advantage of keeping the regulator in Main mode is that the wakeup time from Stop mode is shorter.

If Flash memory programming or an access to the APB domain is ongoing, the Stop mode entry is delayed until the memory or APB access has completed.

In Stop mode, the following features can be selected by programming individual control bits:

• Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by hardware option. Once started it cannot be stopped except by a Reset. Refer to

Section 17.3: IWDG functional description in Section 17: Independent watchdog

(IWDG) .

• Real-time clock (RTC): this is configured by the RTCEN bit in the RCC_CSR register

(see Section 7.3.20

• Internal RC oscillator (LSI RC): this is configured by the LSION bit in the RCC_CSR register.

• External 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the

RCC_CSR register.

The ADC can also consume power in Stop mode, unless they are disabled before entering it. To disable them, the ADDIS bit in the ADC_CR register must be set to 1.

Exiting Stop mode

Refer to Section 6.3.6: Exiting low-power mode

and to Table 35

for details on how to exit

Stop mode.

When exiting Stop mode by issuing an interrupt or a wakeup event, the MSI or HSI16 RC oscillator is selected as system clock depending the bit STOPWUCK in the RCC_CFGR register.

When the voltage regulator operates in low-power mode, an additional startup delay is incurred when waking up from Stop mode. By keeping the internal regulator ON during Stop mode, the consumption is higher although the startup time is reduced.

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Power control (PWR)

Stop mode

Mode entry

Mode exit

Wakeup latency

RM0451

Table 35. Stop mode

Description

WFI (Wait for Interrupt) or WFE (Wait for Event) while:

– No interrupt (for WFI) or event (for WFE) is pending.

– SLEEPDEEP bit is set in Cortex

-M0+ System Control register

– PDDS bit = 0 in Power Control register (PWR_CR)

– WUF bit = 0 in Power Control/Status register (PWR_CSR)

– MSI or HSI16 RC oscillator are selected as system clock for Stop mode exit by configuring the STOPWUCK bit in the RCC_CFGR register.

Note: To enter the Stop mode, all EXTI Line pending bits (in

Section 12.5.6: EXTI pending register (EXTI_PR) ), all peripherals

interrupt pending bits, the RTC Alarm (Alarm A and Alarm B), RTC wakeup, RTC tamper, and RTC time-stamp flags, must be reset.

Otherwise, the Stop mode entry procedure is ignored and program execution continues.

On return from ISR while:

– No interrupt is pending.

– SLEEPDEEP bit is set in Cortex

-M0+ System Control register

– SLEEPONEXIT = 1

– PDDS bit = 0 in Power Control register (PWR_CR)

– WUF bit = 0 in Power Control/Status register (PWR_CSR)

– MSI or HSI16 RC oscillator are selected as system clock for Stop mode exit by configuring the STOPWUCK bit in the RCC_CFGR register.

Note: To enter the Stop mode, all EXTI Line pending bits (in

Section 12.5.6: EXTI pending register (EXTI_PR) ), all peripherals

interrupt pending bits, the RTC Alarm (Alarm A and Alarm B), RTC wakeup, RTC tamper, and RTC time-stamp flags, must be reset.

Otherwise, the Stop mode entry procedure is ignored and program execution continues.

If WFI or return from ISR was used for entry:

Any EXTI Line configured in Interrupt mode (the corresponding EXTI

Interrupt vector must be enabled in the NVIC). Refer to Table 49: List of vectors.

If WFE was used for entry and SEVONPEND = 0

Any EXTI Line configured in event mode. Refer to Section 12.3.2:

Wakeup event management on page 243

If WFE was used for entry and SEVONPEND = 1

– Any EXTI Line configured in event mode (even if the corresponding EXTI interrupt is disabled in the NVIC). The interrupt source can be an external

interrupt or a peripheral with wakeup capability (refer to Table 49: List of vectors

– A wakeup event (refer to

Section 12.3.2: Wakeup event management on page 243 )

MSI or HSI16 RC wakeup time + regulator wakeup time from Low-power mode + FLASH wakeup time

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RM0451 Power control (PWR)

The Standby mode allows to achieve the lowest power consumption. It is based on the

Cortex

-M0+ Deepsleep mode, with the voltage regulator disabled. The V

CORE

domain is consequently powered off. The PLL, the MSI, the HSI16 oscillator and the HSE oscillator are also switched off. SRAM and register contents are lost except for the RTC registers,

RTC backup registers and Standby circuitry (see Figure 10 ).

I/O states in Standby mode

In Standby mode, all I/O pins are high impedance except for:

• Reset pad

• Wakeup pins (WKUP1, WKUP2, WKUP3)

• RTC functions (tamper, time-stamp, RTC Alarm out, RTC clock calibration out) on the following I/Os:

– Category 1: PA0, PA2

– Category 2: PC13, PA0, PA2

– Category 3: PC13, PA0

– Category 5: PC13, PA0, PE6

Entering Standby mode

Refer to

Section 6.3.5: Entering low-power mode

and to Table 36

for details on how to enter

Standby mode.

In Standby mode, the following features can be selected by programming individual control bits:

• Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by hardware option. Once started it cannot be stopped except by a reset. Refer to

Section 17.3: IWDG functional description on page 445 .

• Real-time clock (RTC): this is configured by the RTCEN bit in the RCC_CSR register

(see Section 7.3.20

• Internal RC oscillator (LSI RC): this is configured by the LSION bit in the RCC_CSR register.

• External 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the

RCC_CSR register.

Exiting Standby mode

The microcontroller exits Standby mode when an external Reset (NRST pin), an IWDG

Reset, a rising edge on WKUP pins (WUKP1, WKUP2 or WKUP3), an RTC alarm, a tamper event, or a time-stamp event is detected.

After waking up from Standby mode, program execution restarts in the same way as after a

Reset (boot pins sampling, vector reset is fetched, etc.). The SBF status flag in the

PWR_CSR register (see

Section 6.4.2

) indicates that the MCU was in Standby mode. All registers are reset to their default value after a system reset except for the register bits in the

RTC domain (see Section 19.7: RTC registers

, SBF status flag in the PWR power control/status register (PWR_CSR)

Control/status register (RCC_CSR)

and Clock control register (RCC_CR) ).

Refer to Section 6.3.6: Exiting low-power mode

and to Table 36

for more details on how to exit Standby mode.

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Standby mode

Mode entry

Mode exit

Wakeup latency

Table 36. Standby mode

Description

WFI (Wait for Interrupt) or WFE (Wait for Event) while:

– SLEEPDEEP = 1 in Cortex

-M0+ System Control register

– PDDS = 1 bit in Power Control register (PWR_CR)

– No interrupt (for WFI) or event (for WFE) is pending.

– WUF = 0 bit in Power Control/Status register (PWR_CSR)

– the RTC flag corresponding to the chosen wakeup source (RTC Alarm A,

RTC Alarm B, RTC wakeup, Tamper or Time-stamp flags) is cleared

On return from ISR while:

– SLEEPDEEP = 1 in Cortex

-M0+ System Control register

– SLEEPONEXIT = 1

– PDDS bit = 1 in Power Control register (PWR_CR)

– No interrupt is pending.

– WUF bit = 0 in Power Control/Status register (PWR_CSR)

– the RTC flag corresponding to the chosen wakeup source (RTC Alarm A,

RTC Alarm B, RTC wakeup, Tamper or Time-stamp flags) is cleared.

WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup, tamper event, time-stamp event, external reset in NRST pin, IWDG reset.

Reset phase

Debug mode

By default, the debug connection is lost if the application puts the MCU in Stop or Standby mode while the debug features are used. This is due to the fact that the Cortex ® -M0+ core is no longer clocked.

However, by setting some configuration bits in the DBG_CR register, the software can be debugged even when using the low-power modes extensively. For more details, refer to

Section 24.9.1: Debug support for low-power modes .

6.3.11 Waking up the device from Stop and Standby modes using the RTC

The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC Wakeup event, a tamper event or a time-stamp event, without depending on an external interrupt

(Auto-wakeup mode).

These RTC alternate functions can wake up the system from Stop and Standby low-power modes.

The system can also wake up from low-power modes without depending on an external interrupt (Auto-wakeup mode) by using the RTC alarm or the RTC wakeup events.

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RM0451 Power control (PWR)

The RTC provides a programmable time base for waking up from Stop or Standby mode at regular intervals. For this purpose, two of the three alternative RTC clock sources can be selected by programming the RTCSEL[1:0] bits in the RCC_CSR register (see

Section 7.3.20

• Low-power 32.768 kHz external crystal oscillator (LSE OSC).

This clock source provides a precise time base with very low-power consumption (less than 1 µA added consumption in typical conditions)

• Low-power internal RC oscillator (LSI RC)

This clock source has the advantage of saving the cost of the 32.768 kHz crystal. This internal RC Oscillator is designed to use minimum power consumption.

RTC auto-wakeup (AWU) from the Stop mode

• To wake up from the Stop mode with an RTC alarm event, it is necessary to: a) Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt or Event modes) b) Enable the RTC Alarm interrupt in the RTC_CR register c) Configure the RTC to generate the RTC alarm

• To wake up from the Stop mode with an RTC Tamper or time stamp event, it is necessary to: a) Configure the EXTI Line 19 to be sensitive to rising edges (Interrupt or Event modes) b) Enable the RTC TimeStamp Interrupt in the RTC_CR register or the RTC Tamper

Interrupt in the RTC_TCR register c) Configure the RTC to detect the tamper or time stamp event

• To wake up from the Stop mode with an RTC Wakeup event, it is necessary to: a) Configure the EXTI Line 20 to be sensitive to rising edges (Interrupt or Event modes) b) Enable the RTC Wakeup Interrupt in the RTC_CR register c) Configure the RTC to generate the RTC Wakeup event

RTC auto-wakeup (AWU) from the Standby mode

• To wake up from the Standby mode with an RTC alarm event, it is necessary to: a) Enable the RTC Alarm interrupt in the RTC_CR register b) Configure the RTC to generate the RTC alarm

• To wake up from the Stop mode with an RTC Tamper or time stamp event, it is necessary to: a) Enable the RTC TimeStamp Interrupt in the RTC_CR register or the RTC Tamper

Interrupt in the RTC_TCR register b) Configure the RTC to detect the tamper or time stamp event

• To wake up from the Stop mode with an RTC Wakeup event, it is necessary to: a) Enable the RTC Wakeup Interrupt in the RTC_CR register b) Configure the RTC to generate the RTC Wakeup event

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The peripheral registers have to be accessed by half-words (16-bit) or words (32-bit).

6.4.1 PWR power control register (PWR_CR)

Address offset: 0x00

Reset value: 0x0000 1000 (reset by wakeup from Standby mode)

Res.

15 14

Res.

LPRUN

DS_EE

_KOFF rw rw

Res.

12 11

VOS[1:0] rw rw

Res.

FWU rw

ULP rw

Res.

DBP rw

Res.

LPDS rw

CSBF CWUF PDDS LPSDSR rc_w1 rc_w1 rw rw

Bits 31:17 Reserved, always read as 0.

Bit 16 LPDS : Regulator in Low-power deepsleep mode

This bit allows switching the regulator to low-power mode when the CPU enters Stop mode. Its behavior depends on LPSDSR bit.

– if LPSDSR = 1: bit has no effect.

– if LPSDSR = 0:

0: Voltage regulator in Main mode during Deepsleep mode (Stop mode)

1: Voltage regulator switches to low-power mode when the CPU enters Deepsleep mode

(Stop mode).

The regulator goes back to Main mode when the CPU exits from Deepsleep mode.

Note: The LPDS bit is available on category 1 devices only.

Bit 15 Reserved, always read as 0.

Bit 14 LPRUN: Low-power run mode

When LPRUN bit is set together with the LPSDSR bit, the regulator is switched from Main mode to low-power mode. Otherwise, it remains in Main mode. The regulator goes back to operate in Main mode when LPRUN is reset.

If this bit is set (with LPSDSR bit set) and the CPU enters sleep or Deepsleep mode (LP sleep or Stop mode), then, when the CPU wakes up from these modes, it enters Run mode but with LPRUN bit set. To enter again Low-power run mode, it is necessary to perform a reset and set LPRUN bit again.

It is forbidden to reset LPSDSR when the MCU is in Low-power run mode. LPSDSR is used as a prepositioning for the entry into low-power mode, indicating to the system which configuration of the regulator will be selected when entering low-power mode. The

LPSDSR bit must be set before the LPRUN bit is set. LPSDSR can be reset only when

LPRUN bit=0.

0: Voltage regulator in Main mode in Low-power run mode

1: Voltage regulator in low-power mode in Low-power run mode

Bit 13 DS_EE_KOFF : Deepsleep mode with non-volatile memory kept off

When entering low-power mode (Stop or Standby only), if DS_EE_KOFF and RUN_PD bits are both set in FLASH_ACR register (refer to

Section 3.7.1: Access control register

(FLASH_ACR)

, the non-volatile memory (Flash program memory and data EEPROM) will not be woken up when exiting from Deepsleep mode.

0: NVM woken up when exiting from Deepsleep mode even if the bit RUN_PD is set

1: NVM not woken up when exiting from low-power mode (if the bit RUN_PD is set)

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RM0451 Power control (PWR)

Bits 12:11 VOS[1:0]: Voltage scaling range selection

These bits are used to select the internal regulator voltage range.

Before resetting the power interface by resetting the PWRRST bit in the

RCC_APB1RSTR register, these bits have to be set to ‘10’ and the frequency of the system has to be configured accordingly.

00: forbidden (bits are unchanged and keep the previous value, no voltage change occurs)

01: 1.8 V (range 1)

10: 1.5 V (range 2)

11: 1.2 V (range 3)

Bit 10 FWU : Fast wakeup

This bit works in conjunction with ULP bit.

If ULP = 0, FWU is ignored

If ULP = 1 and FWU = 1: V

REFINT startup time is ignored when exiting from low-power mode. The VREFINTRDYF flag in the PWR_CSR register indicates when the V

REFINT ready again.

If ULP=1 and FWU = 0: Exiting from low-power mode occurs only when the V

REFINT ready (after its startup time). This bit is not reset by resetting the PWRRST bit in the

RCC_APB1RSTR register.

0: Low-power modes exit occurs only when V

REFINT

1: V

REFINT is ready start up time is ignored when exiting low-power modes

Bit 9 ULP : Ultra-low-power mode

When set, the V

REFINT

is switched off in low-power mode. The BOR also relies on the voltage reference. This bit is not reset by resetting the PWRRST bit in the

RCC_APB1RSTR register.

0: V

REFINT

1: V

REFINT

is on in low-power mode

is off in low-power mode

Bit 8 DBP : Disable backup write protection

In reset state, the RTC, RTC backup registers and RCC CSR register are protected against parasitic write access. This bit must be set to enable write access to these registers.

0: Access to RTC, RTC Backup and RCC CSR registers disabled

1: Access to RTC, RTC Backup and RCC CSR registers enabled

Note: If the HSE divided by 2, 4, 8 or 16 is used as the RTC clock, this bit must remain set to 1.

Bits 7:4 Reserved, always read as 0.

Bit 3 CSBF : Clear standby flag

This bit is always read as 0.

0: No effect

1: Clear the SBF Standby flag (write).

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Power control (PWR) RM0451

Bit 2 CWUF: Clear wakeup flag

This bit is always read as 0.

0: No effect

1: Clear the WUF Wakeup flag after 2 system clock cycles

Bit 1 PDDS : Power-down deepsleep

This bit is set and cleared by software.

0: Enter Stop mode when the CPU enters Deepsleep.

1: Enter Standby mode when the CPU enters Deepsleep.

Bit 0 LPSDSR: Low-power deepsleep/Sleep/Low-power run

– DeepSleep/Sleep modes

When this bit is set, the regulator switches in low-power mode when the CPU enters sleep or Deepsleep mode. The regulator goes back to Main mode when the CPU exits from these modes.

– Low-power run mode

When this bit is set, the regulator switches in low-power mode when the bit LPRUN is set.

The regulator goes back to Main mode when the bit LPRUN is reset.

This bit is set and cleared by software.

0: Voltage regulator on during Deepsleep/Sleep/Low-power run mode

1: Voltage regulator in low-power mode during Deepsleep/Sleep/Low-power run mode

Note: If the sequence below is executed:

1) Low-power run

2) Low-power sleep

3) Run

4) Low-power run after returning from Low-power deepsleep/Sleep mode (step 2), the regulator goes back to Main mode (step 3). Then to switch to Low-power run mode (step 4), it is necessary to perform a reset and set LPSDSR bit again.

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RM0451 Power control (PWR)

6.4.2

Res.

PWR power control/status register (PWR_CSR)

Address offset: 0x04

Reset value: 0x0000 0008 (not reset by wakeup from Standby mode)

Additional APB cycles are needed to read this register versus a standard APB read.

Res.

EWUP

3 rw

EWUP

2 rw

EWUP

1 rw

Res.

REG

LPF r

VOSF r

VREFIN

TRDYF r

Res.

SBF r

WUF r

Bits 31:11 Reserved, must be kept at reset value.

Bit 10 EWUP3 : Enable WKUP pin 3

This bit is set and cleared by software.

0: WKUP pin 3 is used for general purpose I/Os. An event on the WKUP pin 3 does not wakeup the device from Standby mode.

1: WKUP pin 3 is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin 3wakes-up the system from Standby mode).

Note: This bit is reset by a system reset.

Bit 9 EWUP2 : Enable WKUP pin 2

This bit is set and cleared by software.

0: WKUP pin 2 is used for general purpose I/Os. An event on the WKUP pin 2 does not wakeup the device from Standby mode.

1: WKUP pin 2 is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin 2 wakes-up the system from Standby mode).

Note: This bit is reset by a system reset.

Bit 8 EWUP1 : Enable WKUP pin 1

This bit is set and cleared by software.

0: WKUP pin 1 is used for general purpose I/Os. An event on the WKUP pin 1 does not wakeup the device from Standby mode.

1: WKUP pin 1 is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin 1 wakes-up the system from Standby mode).

Note: This bit is reset by a system reset.

Bits 7:6 Reserved, must be kept at reset value.

Bit 5 REGLPF : Regulator LP flag

This bit is set by hardware when the MCU is in Low-power run mode.

When the MCU exits from Low-power run mode, this bit stays at 1 until the regulator is ready in Main mode. A polling on this bit is recommended to wait for the regulator Main mode. This bit is reset by hardware when the regulator is ready.

0: Regulator is ready in Main mode

1: Regulator voltage is in low-power mode

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Bit 4 VOSF : Voltage Scaling select flag

A delay is required for the internal regulator to be ready after the voltage range is changed.

The VOSF bit indicates that the regulator has reached the voltage level defined with bits

VOS of PWR_CR register.

This bit is set when VOS[1:0] in PWR_CR register change.

It is reset once the regulator is ready.

0: Regulator is ready in the selected voltage range

1: Regulator voltage output is changing to the required VOS level.

Bit 3 VREFINTRDYF : Internal voltage reference (V

REFINT

) ready flag

This bit indicates the state of the internal voltage reference, V

REFINT

0: V

REFINT

1: V

REFINT

is OFF

is ready

Bit 2 Reserved, must be kept at reset value.

Bit 1 SBF: Standby flag

This bit is set by hardware and cleared only by a POR/PDR (power-on reset/power-down reset) or by setting the CSBF bit in the PWR power control register (PWR_CR)

0: Device has not been in Standby mode

1: Device has been in Standby mode

Bit 0 WUF: Wakeup flag

This bit is set by hardware and cleared by a system reset or by setting the CWUF bit in the

PWR power control register (PWR_CR)

0: No wakeup event occurred

1: A wakeup event was received from the WKUP pin or from the RTC alarm (Alarm A or

Alarm B), RTC Tamper event, RTC Timestamp event or RTC Wakeup).

Note: An additional wakeup event is detected if the WKUP pins are enabled (by setting the

EWUPx (x=1, 2, 3) bits) when the WKUP pin levels are already high.

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RM0451

The following table summarizes the PWR registers.

Table 37. PWR - register map and reset values

Offset Register

Power control (PWR)

0x000

PWR_CR

Reset value

VOS

[1:0]

0 0 1 0 0 0 0

0x004

PWR_CSR

Reset value 0 0 0

Refer to Section 2.2 on page 39 for the register boundary addresses.

0 0 0 0

0 0 1 0 0

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7 Reset and clock control (RCC)

RM0451

7.1 Reset

There are three types of reset, defined as system reset, power reset and RTC domain reset.

A system reset sets all registers to their reset values unless specified otherwise in the register description.

A system reset is generated when one of the following events occurs:

• A low level on the NRST pin (external reset)

• Window watchdog end-of-count condition (WWDG reset)

• Independent watchdog end-of-count condition (IWDG reset)

• A software reset (SW reset) (see

Software reset

)

• Low-power management reset (see

Low-power management reset

)

•

Option byte loader reset (see Option byte loader reset

)

• Exit from Standby mode

•

Firewall protection (see Section 5: Firewall (FW) )

The reset source can be identified by checking the reset flags in the control/status register,

RCC_CSR (see

Section 7.3.20

Software reset

The SYSRESETREQ bit in Cortex ® -M0+ AIRCR register (Application Interrupt and Reset

Control Register) must be set to force a software reset on the device. Refer to Arm

Cortex ® -M0+ Technical Reference Manual for more details.

Low-power management reset

There are two ways to generate a low-power management reset:

• Reset generated when entering Standby mode:

This type of reset is enabled by resetting nRST_STDBY bit in user option bytes. In this case, whenever a Standby mode entry sequence is successfully executed, the device is reset instead of entering Standby mode.

• Reset when entering Stop mode:

This type of reset is enabled by resetting nRST_STOP bit in user option bytes. In this case, whenever a Stop mode entry sequence is successfully executed, the device is reset instead of entering Stop mode.

Option byte loader reset

The Option byte loader reset is generated when the OBL_LAUNCH bit (bit 18) is set in the

FLASH_PECR register. This bit is used to launch by software the option byte loading.

For further information on the user option bytes, refer to Section 3: Flash program memory and data EEPROM (FLASH) .

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RM0451 Reset and clock control (RCC)

A power reset is generated when one of the following events occurs:

• Power-on/power-down reset (POR/PDR reset)

• BOR reset

A power reset sets all registers to their reset values including for the RTC domain (see

Figure 15

)

These sources act on the NRST pin and it is always kept low during the delay phase. The

RESET service routine vector is fixed at address 0x0000_0004 in the memory map. For more details, refer to

Table 49: List of vectors

The system reset signal provided to the device is output on the NRST pin (except the Exit from Standby reset which is not output on the NRST pin but generates system reset).

The pulse generator guarantees a minimum reset pulse duration of 20 µs for each internal reset source. In case of an external reset, the reset pulse is generated while the NRST pin is asserted low.

When an internal reset occurs, the internal pull-up resistor (RPU) is deactivated in order to save the power consumption through the pull-up resistor.

Figure 15. Simplified diagram of the reset circuit

7.1.3

PU System reset

External reset

NRST

Filter

Pulse generator

(min 20 μs)

WWDG reset

IWDG reset

Firewall reset

Software reset

Low-power manager reset

Option byte loader reset

BOR reset

MSv41924V2

RTC and backup registers reset

The RTC peripheral, RTC clock source selection (in RCC_CSR) and the backup registers are reset only when one of the following events occurs:

• A software reset, triggered by setting the RTCRST bit in the RCC_CSR register (see

Section 7.3.20

)

• Power reset (BOR/POR/PDR).

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7.2 Clocks

Four different clock sources can be used to drive the system clock (SYSCLK):

• HSI16 (high-speed internal) oscillator clock

• HSE (high-speed external) oscillator clock

The HSE external quartz connexion is available only on cat. 2 devices in LQFP48 package.

• PLL clock

• MSI (multispeed internal) oscillator clock

The MSI at 2.1MHz is used as system clock source after startup from power reset, system or RTC domain reset, and after wake-up from Standby mode.

The HSI16, HSI16 divided by 4, or the MSI at any of its possible frequency can be used to wake up from Stop mode.

The devices have two secondary clock sources:

• 37 kHz low speed internal RC (LSI RC) which drives the independent watchdog and optionally the RTC used for Auto-wakeup from Stop/Standby mode and the LPTIMER.

• 32.768 kHz low speed external crystal (LSE crystal) which optionally drives the realtime clock (RTCCLK), the LPTIMER and USARTs.

Each clock source can be switched on or off independently when it is not used to optimize power consumption.

Several prescalers can be used to configure the AHB frequency and the two APBs (APB1 and APB2) domains. The maximum frequency of AHB, APB1 and the APB2 domains is

32 MHz. It depends on the device voltage range. For more details refer to Section 6.1.4:

Dynamic voltage scaling management .

All the peripheral clocks are derived from the system clock (SYSCLK) except:

• The ADC can be derived either from the APB clock or the HSI16 clock.

• The LPUART1 and USART2 clock which is derived (selected by software) from one of the four following sources:

– system clock

– HSI16 clock

– LSE clock

– APB clock (PCLK)

• The I2C1 clock which is derived (selected by software) from one of the three following sources:

– system clock

– HSI16 clock

– APB clock (PCLK)

• The LPTIMER clock which is derived (selected by software) from one of the four following sources:

– HSI16 clock

– LSE clock

– LSI clock

– APB clock (PCLK)

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• The RTC clock which is derived from the following clock sources:

– LSE clock,

– LSI clock,

– 4 MHz HSE_RTC (HSE divided by a programmable prescaler).

• IWDG clock which is always the LSI clock.

The system clock (SYSCLK) frequency must be higher or equal to the RTC clock frequency.

The RCC feeds the Cortex ® System Timer (SysTick) external clock with the AHB clock

(HCLK) divided by 8. The SysTick can work either with this clock or with the Cortex

clock

(HCLK), configurable in the SysTick Control and Status Register.

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@V33

LSI RC

LSE OSC

Figure 16. Clock tree

Enable Watchdog

LSI tempo

LSE tempo

Watchdog LS

RTCSEL

RTC2 enable

RTC

RM0451

Legend:

HSE = High-speed external clock signal

HSI = High-speed internal clock signal

LSI = Low-speed internal clock signal

LSE = Low-speed external clock signal

MSI = Multispeed internal clock signal

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@V18

LSU LSD LSD

@V33

MSI RC

Level shifters

@V18

MSI

/ 2,4,8,16

@V33

HSI16 RC

Level shifters

@V18 ck_rchs

/ 1,4

HSI16

@V33

HSE OSC

Level shifters

@V18

4 MHz

@V33

1 MHz Clock

Detector

LSU

LSD

LSI

LSE

MSI

HSI16

HSE

PLLSRC

@V33 ck_pllin

PLLCLK

PLL

3,4,6,8,12,16,

24,32,48

/ 2,3,4

Level shifters

DDCORE

HSE present or not

MCOSEL

ADC enable

ADCCLK

/ 1,2,4,8,16

MCO not deepsleep

CK_PWR not deepsleep

System

Clock not (sleep or deepsleep) not (sleep or deepsleep)

/ 8

FCLK

HCLK

TIMxCLK

Clock

Source

Control

AHB

PRESC

/ 1,2,…, 512

PCLK1 to APB1 peripherals

APB1

PRESC

/ 1,2,4,8,16

Peripheral clock enable

If (APB1 presc=1) x1 else x2) to TIMx

Peripheral clock enable

PCLK2 to APB2

32 MHz peripherals max.

APB2

PRESC

/ 1,2,4,8,16

Peripheral clock enable

If (APB2 presc=1) x1 else x2) to TIMx

LSI

Peripherals enable

LSE

HSI16

SYSCLK

PCLK

Peripherals

LPTIMCLK enable

Peripherals enable

LPUART/

UARTCLK

I2C1CLK

MSv34747V2

1. For full details about the internal and external clock source characteristics, please refer to the “Electrical characteristics” section in your device datasheet.

RM0451 Rev 3

RM0451 Reset and clock control (RCC)

The timer clock frequencies are automatically fixed by hardware. There are two cases:

If the APB prescaler is 1, the timer clock frequencies are set to the same frequency as that of the APB domain to which the timers are connected.

2. Otherwise, they are set to twice (×2) the frequency of the APB domain to which the timers are connected.

CLK

acts as Cortex ® -M0+ free running clock. For more details refer to the

Section 24:

Debug support (DBG) .

The high speed external clock signal (HSE) can be generated from two possible clock sources:

• HSE external crystal/ceramic resonator

• HSE user external clock

The resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. The loading capacitance values must be adjusted according to the selected oscillator.

Clock source

Table 38. HSE/LSE clock sources

Hardware configuration

External clock for category 2, category

3 (LQFP48 only) and category 5 devices

OSC_IN

External source

OSC_OUT

GPIO

MSv31915V1

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Clock source

Table 38. HSE/LSE clock sources (continued)

Hardware configuration

RM0451

Note:

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CK_IN

External source

GPIO

MSv36151V1

OSC_IN OSC_OUT

Crystal/Ceramic resonators for category 2, category

3 (LQFP48 only) and category 5 devices

C

Load capacitors

C

External source (HSE bypass)

In this mode, an external clock source must be provided. It can have a frequency of up to

32 MHz. This mode is selected by setting the HSEBYP and HSEON bits in the RCC_CR register

(see Section 7.3.1: Clock control register (RCC_CR))

. The external clock signal

with ~50% duty cycle has to drive the following pin (see Figure 38 ):

• On devices where OSC_IN and OSC_OUT pins are available: the OSC_IN pin must be driven while the OSC_OUT pin should be left hi-Z.

• Otherwise, the CK_IN pin must be driven.

For details on pin availability, refers to the pinout section in your device datasheet.

The external clock signal can be square, sinus or triangle. To minimize the consumption, it is recommended to use the square signal.

External crystal/ceramic resonator (HSE crystal)

The 1 to 24 MHz external oscillator has the advantage of producing a very accurate rate on the main clock.

The associated hardware configuration is shown in

Figure 38

. Refer to the electrical characteristics section of the datasheet for more details.

The HSERDY flag of the RCC_CR register

(see Section 7.3.1)

indicates whether the HSE oscillator is stable or not. At startup, the HSE clock is not released until this bit is set by hardware. An interrupt can be generated if enabled in the RCC_CR register .

The HSE Crystal can be switched on and off using the HSEON bit in the RCC_CR register .

For code example, refer to

A.4.1: HSE start sequence code example

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MSv31916V1

RM0451 Reset and clock control (RCC)

The HSI16 clock signal is generated from an internal 16 MHz RC oscillator. It can be used directly as a system clock or as PLL input.

The HSI16 clock can be used after wake-up from the Stop low-power mode, this ensure a smaller wake-up time than a wake-up using MSI clock.

The HSI16 RC oscillator has the advantage of providing a clock source at low cost (no external components). It also has a faster startup time than the HSE crystal oscillator however, even with calibration the frequency is less accurate than an external crystal oscillator or ceramic resonator.

The HSI16 clock can be kept running in Stop mode by setting HSI16KERON bit in RCC_CR

can be used for dedicated peripherals which can run in Stop mode.

Calibration

RC oscillator frequencies can vary from one chip to another due to manufacturing process variations, this is why each device is factory calibrated by ST for 1% accuracy at an ambient temperature, T

, of 25 °C.

After reset, the factory calibration value is loaded in the HSI16CAL[7:0] bits in the Internal

Clock Sources Calibration Register (RCC_ICSCR)

(see Section 7.3.2

If the application is subject to voltage or temperature variations, this may affect the RC oscillator speed. You can trim the HSI16 frequency in the application by using the

HSI16TRIM[4:0] bits in the RCC_ICSCR register. For more details on how to measure the

HSI16 frequency variation please refer to

Section 7.2.14: Internal/external clock measurement using TIM21

The HSI16RDY flag in the RCC_CR register indicates whether the HSI16 oscillator is stable or not. At startup, the HSI16 RC output clock is not released until this bit is set by hardware.

The HSI16 RC oscillator can be switched on and off using the HSI16ON bit in the RCC_CR register.

The MSI clock signal is generated from an internal RC oscillator. Its frequency range can be adjusted by software by using the MSIRANGE[2:0] bits in the RCC_ICSCR register (see

Section 7.3.2: Internal clock sources calibration register (RCC_ICSCR)

). Seven frequency ranges are available: 65.536 kHz, 131.072 kHz, 262.144 kHz, 524.288 kHz, 1.048 MHz,

2.097 MHz (default value) and 4.194 MHz.

The MSI clock is always used as system clock after restart from Reset and wake-up from

Standby. After wake-up from Stop mode, the MSI clock can be selected as system clock instead of HSI16 (or HSI16/4).

When the device restarts after a reset or a wake-up from Standby, the MSI frequency is set to its default value. The MSI frequency does not change after waking up from Stop.

The MSI RC oscillator has the advantage of providing a low-cost (no external components) low-power clock source. It is used as wake-up clock in low-power modes to reduce power consumption.

The MSIRDY flag in the RCC_CR register indicates whether the MSI RC is stable or not. At startup, the MSI RC output clock is not released until this bit is set by hardware.

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The MSI RC can be switched on and off by using the MSION bit in the RCC_CR register

(see Section 7.3.1

It can also be used as a backup clock source (auxiliary clock) if the HSE crystal oscillator

fails. Refer to Section 7.2.9: HSE clock security system (CSS) on page 154

Calibration

The MSI RC oscillator frequency can vary from one chip to another due to manufacturing process variations, this is why each device is factory calibrated by ST for 1% accuracy at an ambient temperature, T

, of 25 °C.

After reset, the factory calibration value is loaded in the MSICAL[7:0] bits in the

RCC_ICSCR register. If the application is subject to voltage or temperature variations, this may affect the RC oscillator speed. You can trim the MSI frequency in the application by using the MSITRIM[7:0] bits in the RCC_ICSCR register. For more details on how to

measure the MSI frequency variation please refer to Section 7.2.14: Internal/external clock measurement using TIM21

7.2.4 PLL

Note:

The internal PLL can be clocked by the HSI16 RC or HSE clocks.

The PLL input clock frequency must range between 2 and 24 MHz.

The desired frequency is obtained by using the multiplication factor and output division embedded in the PLL:

• The system clock is derived from the PLL VCO divided by the output division factor.

The application software must set correctly the PLL multiplication factor to avoid exceeding

96 MHz as PLLVCO when the product is in range 1,

48 MHz as PLLVCO when the product is in range 2,

24 MHz when the product is in range 3.

It must also set correctly the output division to avoid exceeding 32 MHz as SYSCLK.

The minimum input clock frequency for PLL is 2 MHz (when using HSE as PLL source).

The PLL configuration (selection of the source clock, multiplication factor and output division factor) must be performed before enabling the PLL. Once the PLL is enabled, these parameters cannot be changed.

To modify the PLL configuration, proceed as follows:

Disable the PLL by setting PLLON to 0.

2. Wait until PLLRDY is cleared. The PLL is now fully stopped.

3. Change the desired parameter.

4. Enable the PLL again by setting PLLON to 1.

An interrupt can be generated when the PLL is ready if enabled in the RCC_CIER register

(see Section 7.3.4

For code example, refer to

A.4.2: PLL configuration modification code example

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The LSE crystal is a 32.768 kHz low speed external crystal or ceramic resonator. It has the advantage of providing a low-power but highly accurate clock source to the real-time clock peripheral (RTC) for clock/calendar or other timing functions.

The LSE crystal is switched on and off through the LSEON bit in the RCC_CSR register

(see Section 7.3.20

The crystal oscillator driving strength can be changed at runtime through the LSEDRV[1:0] bits of the RCC_CSR register to obtain the best compromise between robustness and short start-up time on one hand and low power consumption on the other hand. The driving capability should be changed dynamically to determine the driving level that best matches the used crystal. In the final application, it is then recommended to program this value in

LSEDRV[1:0] bits.

The LSERDY flag in the RCC_CSR register indicates whether the LSE crystal is stable or not. At startup, the LSE crystal output clock signal is not released until this bit is set by hardware. An interrupt can be generated if enabled in the RCC_CIER register (see

Section 7.3.4

External source (LSE bypass)

In this mode, an external clock source must be provided. It can have a frequency of up to

1 MHz. This mode is selected by setting the LSEBYP and LSEON bits in the RCC_CSR

(see Section 7.3.1

). The external clock signal (square, sinus or triangle) with ~50% duty

cycle has to drive the OSC32_IN pin while the OSC32_OUT pin should be left Hi-Z (see

Figure 38

The LSI RC acts as an low-power clock source that can be kept running in Stop and

Standby mode for the independent watchdog (IWDG). The clock frequency is around

37 kHz.

The LSI RC oscillator can be switched on and off using the LSION bit in the RCC_CSR

register (see Section 7.3.20

The LSIRDY flag in RCC_CSR indicates whether the low-speed internal oscillator is stable or not. At startup, the clock is not released until this bit is set by hardware. An interrupt can be generated if enabled in the RCC_CIER (see

Section 7.3.4

Since the IWDG is activated, the LSI oscillator cannot be stopped by LSION=0. The LSI oscillator is stopped by system reset (except if IWDG is enabled by hardware option through

WDG_SW option bit in FLASH_OPTR register). If the IWDG was enabled by software, then the LSI oscillator must be enabled again after system reset to ensure correct IWDG and/or

RTC operation.

LSI measurement

The frequency dispersion of the LSI oscillator can be measured to have accurate RTC time base and/or IWDG timeout (when LSI is used as clock source for these peripherals) with an acceptable accuracy. For more details, refer to the electrical characteristics section of the datasheets. For more details on how to measure the LSI frequency, please refer to

Section 7.2.14: Internal/external clock measurement using TIM21

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7.2.7 System clock (SYSCLK) selection

Four different clock sources can be used to drive the system clock (SYSCLK):

• The HSI16 oscillator

• The HSE oscillator

• The PLL

• The MSI oscillator clock (default after reset)

When a clock source is used directly or through the PLL as system clock, it is not possible to stop it.

A switch from one clock source to another occurs only if the target clock source is ready

(clock stable after startup delay or PLL locked). If a clock source which is not yet ready is selected, the switch will occur when the clock source will be ready. Status bits in the

RCC_CR register indicate which clock(s) is (are) ready and which clock is currently used as system clock.

7.2.8 System clock source frequency versus voltage range

The following table gives the different clock source maximum frequencies depending on the product voltage range.

Product voltage range

MSI

Table 39. System clock source frequency

Clock frequency

HSI16

Range 1 (1.8 V) 4.2 MHz 16 MHz

HSE

HSE 32 MHz (external clock) or 24 MHz (crystal)

Range 2 (1.5 V) 4.2 MHz 16 MHz

Range 3 (1.2 V) 4.2 MHz NA

16 MHz

8 MHz

PLL

32 MHz

(PLLVCO max = 96 MHz)

16 MHz

(PLLVCO max = 48 MHz)

4 MHz

(PLLVCO max = 24 MHz)

Note:

The Clock security system can be activated on the HSE by software. In this case, the clock detector is enabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped.

If an HSE clock failure is detected, this oscillator is automatically disabled and an CSSHSEI interrupt (Clock Security System Interrupt) is generated to inform the software of the failure, thus allowing the MCU to perform rescue operations. The CSSHSEI is linked to the

Cortex ® -M0+ NMI (Non-Maskable Interrupt) exception vector.

Once the CSSHSE is enabled, if the HSE clock fails, the CSSHSE interrupt occurs and an

NMI is automatically generated. The NMI is executed indefinitely unless the CSSHSE interrupt pending bit is cleared. As a consequence, the NMI interrupt service routine (ISR) must clear the CSSHSE interrupt by setting the CSSHSEC bit in the RCC_CICR register.

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Note:

Reset and clock control (RCC)

If the HSE oscillator is used directly or indirectly as the system clock (indirectly means: it is used as PLL input clock, and the PLL clock is used as system clock), a detected failure causes a switch of the system clock and the disabling of the HSE oscillator. If the HSE oscillator clock is the clock entry of the PLL used as system clock when the failure occurs, the PLL is disabled too.

When an HSE failure occurs, the system clock can be switched to the MSI or to the internal

16-MHz HSI clock depending on the value of STOPWUCK bit in the RCC_CFGR register.

Category 1 devices do not feature HSE clock security system. The HSE clock is available only in bypass mode.

Clock Security System can be activated on the LSE by software. This is done by writing the

CSSLSEON bit in the RCC_CSR register. This bit can be disabled by a hardware reset, an

RTC software reset, or after an LSE clock failure detection. CSSLSEON bit must be written after the LSE and LSI clocks are enabled (LSEON and LSION set) and ready (LSERDY and

LSIRDY bits set by hardware), and after the RTC clock has been selected through the

RTCSEL bit.

The LSE CSS works in all modes: run, Sleep, Stop and Standby.

If a failure is detected on the external 32 kHz oscillator, the LSE clock is no longer supplied to the RTC but the content of the registers does not change.

A wakeup is generated in Standby mode. In any other modes, an interrupt can be sent to wake-up the software (see

Section 7.3.4

The software MUST then reset the CSSLSEON bit and stop the defective 32 kHz oscillator by resetting LSEON bit. It can change the RTC clock source (LSI, HSE or no clock) through the RTCSEL bit, or take any required action to secure the application.

The frequency of LSE oscillator must be higher than 30 kHz to avoid false positive CSS detection.

Note:

The RTC has the same clock source which can be either the LSE, the LSI, or the HSE

4 MHz clock (HSE divided by a programmable prescaler). It is selected by programming the

RTCSEL[1:0] bits in the RCC_CSR register (see

Section 7.3.20

) and the RTCPRE[1:0] bits

in the RCC_CR register (see Section 7.3.1

Once the RTC clock source have been selected, the only possible way of modifying the selection is to set the RTCRST bit in the RCC_CSR register, or by a POR.

If the LSE or LSI is used as RTC clock source, the RTC continues to work in Stop and

Standby low-power modes, and can be used as wakeup source. However, when the HSE is the RTC clock source, the RTC cannot be used in the Stop and Standby low-power modes.

When the RTC is clocked by the LSE, the RTC remains clocked and functional under system reset.

If the second read of the RTC_TR gives the same result as the first read, this ensures that the data is correct. Otherwise a third read access must be done.

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If the Independent watchdog (IWDG) is started by either hardware option or software access, the LSI oscillator is forced ON and cannot be disabled. After the LSI oscillator temporization, the clock is provided to the IWDG.

If the IWDG was enabled by software, the LSI clock is disabled after system reset. The LSI oscillator must then be enabled again to ensure correct IWDG operation.

The microcontroller clock output (MCO) capability allows the clock to be output onto the external MCO pin using a configurable prescaler (1, 2, 4, 8, or 16). The configuration registers of the corresponding GPIO port must be programmed in alternate function mode.

One of 7 clock signals can be selected as the MCO clock:

• SYSCLK

• HSI16

• MSI

• HSE

• PLL

• LSI

• LSE

The selection is controlled by the MCOSEL[3:0] bits of the RCC_CFGR register (see

Section 7.3.19

For code example, refer to

A.4.3: MCO selection code example

It is possible to indirectly measure the frequency of all on-board clock source generators by

means of the TIM21 channel 1 input capture, as represented on Figure 17 .

Figure 17. Using TIM21 channel 1 input capture to measure frequencies

GPIO

MSI

LSI

HSE_RTC

LSE

TI1_RMP[2:0]

TI(1)

TIM21

GPIO

ETR

LSE

TI(2)

MS32913V1

TIM21 has an input multiplexer that selects which of the I/O or the internal clock is to trigger the input capture. This selection is performed through the TI1_RMP [2:0] bits in the

TIM21_OR register.

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The primary purpose of connecting the LSE to the channel 1 input capture is to be able to accurately measure the HSI16 and MSI system clocks (for this, either the HSI16 or MSI should be used as the system clock source). The number of HSI16 (MSI, respectively) clock counts between consecutive edges of the LSE signal provides a measure of the internal clock period. Taking advantage of the high precision of LSE crystals (typically a few tens of ppm’s), it is possible to determine the internal clock frequency with the same resolution, and trim the source to compensate for manufacturing-process- and/or temperature- and voltagerelated frequency deviations.

The MSI and HSI16 oscillators both have dedicated user-accessible calibration bits for this purpose.

The basic concept consists in providing a relative measurement (e.g. the HSI16/LSE ratio): the precision is therefore closely related to the ratio between the two clock sources. The higher the ratio, the better the measurement.

It is however not possible to have a good enough resolution when the MSI clock is low

(typically below 1 MHz). In this case, it is advised to:

• accumulate the results of several captures in a row

• use the timer’s input capture prescaler (up to 1 capture every 8 periods)

• use the RTC_OUT signal at 512 Hz (when the RTC is clocked by the LSE) as the input for the channel1 input capture. This improves the measurement precision

TIM21 can also be used to measure the LSI, MSI, or HSE_RTC: this is useful for applications with no crystal. The ultra-low-power LSI oscillator has a wide manufacturing process deviation: by measuring it as a function of the HSI16 clock source, its frequency can be determined with the precision of the HSI16.The HSE_RTC frequency (HSE divided by a programmable prescaler) being relatively high (4 MHz), the relative frequency measurement is not very accurate. Its main purpose is consequently to obtain a rough indication of the external crystal frequency. This can be useful to meet the requirements of the IEC 60730/IEC 61335 standards, which require to be able to determine harmonic or subharmonic frequencies (–50/+100% deviations).

7.2.15 Clock-independent system clock sources for TIM2/TIM21/TIM22

Note:

In a number of applications using the 32.768 kHz clock as RTC timebase, timebases completely independently from the system clock are useful. This allows to schedule tasks without having to take into account the processor state (the processor may be stopped or executing at low, medium or full speed).

For this purpose, the LSE clock is internally redirected to the 3 timers’ ETR inputs, which are used as additional clock sources. This gives up to three independent time bases (using the auto-reload feature) with 1 or 2 compare additional channels for fractional events. For instance, the TIM21 auto-reload interrupt can be programmed for a 1 second tick interrupt with an additional interrupt occurring 250 ms after the main tick.

In this configuration, make sure that you have at least a ratio of 2 between the external clock

(LSE) and the APB clock. If the application uses an APB clock frequency lower than twice the LSE clock frequency (typically LSE = 32.768 kHz, so twice LSE = 65.536 kHz), it is mandatory to use the external trigger prescaler feature of the timer: it can divide the ETR clock by up to 8.

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Refer to Section 1.2

for a list of abbreviations used in register descriptions.

Res.

Address offset: 0x00

System Reset value: 0b0000 0000 00XX 0X00 0000 0011 0000 0000 where X is undefined

Power-on reset value: 0x0000 0300

Access: no wait state, word, half-word and byte access

Res.

PLL

RDY r

MSI

RDY r

24 23

PLLON Res.

8 7

MSION Res.

Res.

21 rw

HSI16

OUTEN rw

RTCPRE[1:0] rw

HSI16

DIVF r

CSSHS

EON.

HSI16

DIVEN rw

HSE

BYP rw

HSI16

RDYF r

HSE

RDY r

HSI16K

ERON rw

HSE

ON rw

HSI16

ON rw

Bits 31:26 Reserved, must be kept at reset value.

Bit 25 PLLRDY: PLL clock ready flag

This bit is set by hardware to indicate that the PLL is locked.

0: PLL unlocked

1: PLL locked

Bit 24 PLLON: PLL enable bit

This bit is set and cleared by software to enable PLL.

Cleared by hardware when entering Stop or Standby mode. This bit can not be reset if the

PLL clock is used as system clock or is selected to become the system clock.

0: PLL OFF

1: PLL ON

Bits 23:22 Reserved, must be kept at reset value.

Bits 21:20 RTCPRE[1:0] RTC prescaler

These bits are set and reset by software to obtain a 4 MHz clock from HSE. This prescaler cannot be modified if HSE is enabled (HSEON = 1).These bits are reset by a power -on reset,. Their value is not modified by a system reset.

00: HSE is divided by 2 for RTC clock

01: HSE is divided by 4 for RTC clock

10: HSE is divided by 8 for RTC clock

11: HSE is divided by 16 for RTC clock

Bit 19 CSSHSEON : Clock security system on HSE enable bit

This bit is set by software to enable the clock security system (CSS) on HSE. This bit is "set only" (disabled by system reset). When CSSHSEON is set, the clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if an oscillator failure is detected.

0: Clock security system OFF (clock detector OFF)

1: Clock security system ON (clock detector ON if HSE oscillator is stable, OFF otherwise)

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Bit 18 HSEBYP : HSE clock bypass bit

This bit is set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit, to be used by the device.

The HSEBYP bit can be written only if the HSE oscillator is disabled. This bit is reset by power-on reset. Its value is not modified by system reset

0: HSE oscillator not bypassed

1: HSE oscillator bypassed with an external clock

Bit 17 HSERDY : HSE clock ready flag

This bit is set by hardware to indicate that the HSE oscillator is stable. After the HSEON bit is cleared, HSERDY goes low after 6 HSE oscillator clock cycles.

0: HSE oscillator not ready

1: HSE oscillator ready

Bit 16 HSEON : HSE clock enable bit

This bit is set and cleared by software.

Cleared by hardware to stop the HSE oscillator when entering Stop or Standby mode. This bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock.

0: HSE oscillator OFF

1: HSE oscillator ON

Bits 15:10 Reserved, must be kept at reset value.

Bit 9 MSIRDY : MSI clock ready flag

This bit is set by hardware to indicate that the MSI oscillator is stable.

0: MSI oscillator not ready

1: MSI oscillator ready

Note: Once the MSION bit is cleared, MSIRDY goes low after 6 MSI clock cycles.

Bit 8 MSION : MSI clock enable bit

This bit is set and cleared by software.

Set by hardware to force the MSI oscillator ON when exiting from Stop or Standby mode, or in case of a failure of the HSE oscillator used directly or indirectly as system clock. This bit cannot be cleared if the MSI is used as system clock.

0: MSI oscillator OFF

1: MSI oscillator ON

Bits 7:6 Reserved, must be kept at reset value.

Bit 5 HSI16OUTEN : 16 MHz high-speed internal clock output enable

This bit is set and cleared by software. When this bit is set, TIM2 ETR input is connected to the 16 MHz HSI output clock (HSI16) provided ETR_RMP is set to 011 in

TIM2 option register (TIM2_OR) . This bit can be written anytime by the application.

0: HSI16 output clock disabled

1: HSI16 output clock enabled

Bit 4 HSI16DIVF HSI16 divider flag

This bit is set and reset by hardware. As a write in HSI16DIVEN has not an immediate effect on the frequency, this flag indicates the current status of the HSI16 divider.

0: 16 MHz HSI clock not divided

1: 16 MHz HSI clock divided by 4

Bit 3 HSI16DIVEN HSI16 divider enable bit

This bit is set and reset by software to enable/disable the 16 MHz HSI divider by 4. It can be written anytime.

0: no 16 MHz HSI division requested

1: 16 MHz HSI division by 4 requested

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Bit 2 HSI16RDYF : Internal high-speed clock ready flag

This bit is set by hardware to indicate that the HSI 16 MHz oscillator is stable. After the

HSI16ON bit is cleared, HSI16RDY goes low after 6 HSI16 clock cycles.

0: HSI 16 MHz oscillator not ready

1: HSI 16 MHz oscillator ready

Bit 1 HSI16KERON : High-speed internal clock enable bit for some IP kernels

This bit is set and reset by software to force the HSI 16 MHz oscillator ON, even in Stop mode, so that it can be quickly available as kernel clock for USARTs or I2C1. This bit has no effect on the value of HSI16ON.

0: HSI 16 MHz oscillator not forced ON

1: HSI 16 MHz oscillator forced ON even in Stop mode

Bit 0 HSI16ON : 16 MHz high-speed internal clock enable

This bit is set and cleared by software. It cannot be cleared if the 16 MHz HSI is used directly or indirectly as system clock.

0: HSI16 oscillator OFF

1: HSI16 oscillator ON

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RM0451 Reset and clock control (RCC)

7.3.2 Internal clock sources calibration register (RCC_ICSCR)

Address offset: 0x04

Reset value: 0x00XX B0XX where X is undefined.

Access: no wait state, word, half-word and byte access

31 30 29 rw

15 rw

14 rw

13 rw

MSIRANGE[2:0] rw rw

28 27

MSITRIM[7:0] rw

12 rw

11 rw

26 25 rw

10 rw

9 rw

HSI16TRIM[4:0] rw rw

24 rw

8 rw

23 r

7 r

22 r

6 r

21 r

5 r r

20 19

MSICAL[7:0] r

HSI16CAL[7:0] r r

18 r

2 r

17 r

1 r

16 r

0 r

Bits 31:24 MSITRIM[7:0] : MSI clock trimming

These bits are set by software to adjust MSI calibration.

These bits provide an additional user-programmable trimming value that is added to the

MSICAL[7:0] bits. They can be programmed to compensate for the variations in voltage and temperature that influence the frequency of the internal MSI RC.

Bits 23:16 MSICAL[7:0] : MSI clock calibration

These bits are automatically initialized at startup.

Bits 15:13 MSIRANGE[2:0] : MSI clock ranges

These bits are set by software to choose the frequency range of MSI.7 frequency ranges are available:

000: range 0 around 65.536 kHz

001: range 1 around 131.072 kHz

010: range 2 around 262.144 kHz

011: range 3 around 524.288 kHz

100: range 4 around 1.048 MHz

101: range 5 around 2.097 MHz (reset value)

110: range 6 around 4.194 MHz

111: not allowed

Bits 12:8 HSI16TRIM[4:0] : High speed internal clock trimming

These bits provide an additional user-programmable trimming value that is added to the

HSI16CAL[7:0] bits. They can be programmed to compensated for the variations in voltage and temperature that influence the frequency of the internal HSI16 RC.

Bits 7:0 HSI16CAL[7:0] Internal high speed clock calibration

These bits are initialized automatically at startup.

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Reset and clock control (RCC) RM0451

Address offset: 0x0C

Reset value: 0x0000 0000

Access: 0 ≤ wait state ≤ 2, word, half-word and byte access

1 or 2 wait states inserted only if the access occurs during clock source switch.

Res.

30 29

MCOPRE[2:0]

STOP

WUCK.

rw rw

Res.

13 rw rw

PPRE2[2:0] rw

27 rw

11 rw

26 25

MCOSEL[3:0]

24 rw

10 rw

PPRE1[2:0] rw

8 rw rw rw

23 22

PLLDIV[1:0] rw

7 rw

21 rw

6 rw

HPRE[3:0] rw rw

20 19

PLLMUL[3:0] rw

4 rw

18 rw

SWS[1:0] rw

2 r r

Res.

PLL

SRC rw

SW[1:0] rw rw

Bit 31 Reserved, must be kept at reset value.

Bits 30:28 MCOPRE[2:0]: Microcontroller clock output prescaler

These bits are set and cleared by software.

It is highly recommended to change this prescaler before MCO output is enabled.

000: MCO is divided by 1

001: MCO is divided by 2

010: MCO is divided by 4

011: MCO is divided by 8

100: MCO is divided by 16

Others: not allowed

Bits 27:24 MCOSEL[3:0]: Microcontroller clock output selection

These bits are set and cleared by software.

0000: MCO output disabled, no clock on MCO

0001: SYSCLK clock selected

0010: HSI16 oscillator clock selected

0011: MSI oscillator clock selected

0100: HSE oscillator clock selected

0101: PLL clock selected

0110: LSI oscillator clock selected

0111: LSE oscillator clock selected

1000: Reserved

Others: reserved

Note: This clock output may have some truncated cycles at startup or during MCO clock source switching.

Bits 23:22 PLLDIV[1:0] : PLL output division

These bits are set and cleared by software to control PLL output clock division from PLL VCO clock. These bits can be written only when the PLL is disabled.

00: not allowed

01: PLL clock output = PLLVCO / 2

10: PLL clock output = PLLVCO / 3

11: PLL clock output = PLLVCO / 4

162/784 RM0451 Rev 3

RM0451 Reset and clock control (RCC)

Bits 21:18 PLLMUL[3:0]: PLL multiplication factor

These bits are written by software to define the PLL multiplication factor to generate the PLL

VCO clock. These bits can be written only when the PLL is disabled.

0000: PLLVCO = PLL clock entry x 3

0001: PLLVCO = PLL clock entry x 4

0010: PLLVCO = PLL clock entry x 6

0011: PLLVCO = PLL clock entry x 8

0100: PLLVCO = PLL clock entry x 12

0101: PLLVCO = PLL clock entry x 16

0110: PLLVCO = PLL clock entry x 24

0111: PLLVCO = PLL clock entry x 32

1000: PLLVCO = PLL clock entry x 48 others: not allowed

Caution: The PLL VCO clock frequency must not exceed 96 MHz when the product is in

Range 1, 48 MHz when the product is in Range 2 and 24 MHz when the product is in

Range 3.

Bit 17 Reserved, must be kept at reset value.

Bit 16 PLLSRC: PLL entry clock source

This bit is set and cleared by software to select PLL clock source. This bit can be written only when PLL is disabled.

0: HSI16 oscillator clock selected as PLL input clock

1: HSE oscillator clock selected as PLL input clock

Note: The PLL minimum input clock frequency is 2 MHz.

Bit 15 STOPWUCK : Wake-up from Stop clock selection

This bit is set and cleared by software to select the wake-up from Stop clock.

0: internal 64 KHz to 4 MHz (MSI) oscillator selected as wake-up from Stop clock

1: internal 16 MHz (HSI16) oscillator selected as wake-up from Stop clock (or HSI16/4 if

HSI16DIVEN=1)

Bit 14 Reserved, must be kept at reset value.

Bits 13:11 PPRE2[2:0] : APB high-speed prescaler (APB2)

These bits are set and cleared by software to control the division factor of the APB highspeed clock (PCLK2).

0xx: HCLK not divided

100: HCLK divided by 2

101: HCLK divided by 4

110: HCLK divided by 8

111: HCLK divided by 16

Bits 10:8 PPRE1[2:0] : APB low-speed prescaler (APB1)

These bits are set and cleared by software to control the division factor of the APB low-speed clock (PCLK1).

0xx: HCLK not divided

100: HCLK divided by 2

101: HCLK divided by 4

110: HCLK divided by 8

111: HCLK divided by 16

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7.3.4

Clock interrupt enable register (

RCC_CIER)

Address: 0x10

Reset value: 0x0000 0000

Access: no wait state, word, half-word and byte access

Res.

Bits 7:4 HPRE[3:0]: AHB prescaler

These bits are set and cleared by software to control the division factor of the AHB clock.

Caution: Depending on the device voltage range, the software has to set correctly these bits to ensure that the system frequency does not exceed the maximum allowed frequency (for more details please refer to the Dynamic voltage scaling management section in the PWR chapter.) After a write operation to these bits and before decreasing the voltage range, this register must be read to be sure that the new value has been taken into account.

0xxx: SYSCLK not divided

1000: SYSCLK divided by 2

1001: SYSCLK divided by 4

1010: SYSCLK divided by 8

1011: SYSCLK divided by 16

1100: SYSCLK divided by 64

1101: SYSCLK divided by 128

1110: SYSCLK divided by 256

1111: SYSCLK divided by 512

Bits 3:2 SWS[1:0] : System clock switch status

These bits are set and cleared by hardware to indicate which clock source is used as system clock.

00: MSI oscillator used as system clock

01: HSI16 oscillator used as system clock

10: HSE oscillator used as system clock

11: PLL used as system clock

Bits 1:0 SW[1:0] : System clock switch

These bits are set and cleared by software to select SYSCLK source.

Set by hardware to force MSI selection when leaving Standby mode or in case of failure of the HSE oscillator used directly or indirectly as system clock (if the Clock Security System is enabled).

00: MSI oscillator used as system clock

01: HSI16 oscillator used as system clock

10: HSE oscillator used as system clock

11: PLL used as system clock

Res.

CSS

LSE rw

Res.

MSI

RDYIE rw

PLL

RDYIE rw

HSE

RDYIE rw

HSI16

RDYIE rw

LSE

RDYIE rw

LSI

RDYIE rw

164/784 RM0451 Rev 3

RM0451 Reset and clock control (RCC)

Bits 31:8 Reserved, must be kept at reset value.

Bit 7 CSSLSE: LSE CSS interrupt flag

This bit is set and reset by software to enable/disable the interrupt caused by the Clock

Security System on external 32 kHz oscillator.

0: LSE CSS interrupt disabled

1: LSE CSS interrupt enabled

Bit 6 Reserved, must be kept at reset value.

Bit 5 MSIRDYIE: MSI ready interrupt flag

This bit is set and reset by software to enable/disable the interrupt caused by the MSI oscillator stabilization.

0: MSI ready interrupt disabled

1: MSI ready interrupt enabled

Bit 4 PLLRDYIE: PLL ready interrupt flag

This bit is set and reset by software to enable/disable the interrupt caused by the PLL lock.

0: PLL lock interrupt disabled

1: PLL lock interrupt enabled

Bit 3 HSERDYIE: HSE ready interrupt flag

This bit is set and reset by software to enable/disable the interrupt caused by the HSE oscillator stabilization.

0: HSE ready interrupt disabled

1: HSE ready interrupt enabled

Bit 2 HSI16RDYIE: HSI16 ready interrupt flag

This bit is set and reset by software to enable/disable the interrupt caused by the HSI16 oscillator stabilization.

0: HSI16 ready interrupt disabled

1: HSI16 ready interrupt enabled

Bit 1 LSERDYIE: LSE ready interrupt flag

This bit is set and reset by software to enable/disable the interrupt caused by the LSE oscillator stabilization.

0: LSE ready interrupt disabled

1: LSE ready interrupt enabled

Bit 0 LSIRDYIE: LSI ready interrupt flag

This bit is set and reset by software to enable/disable the interrupt caused by the LSI oscillator stabilization.

0: LSI ready interrupt disabled

1: LSI ready interrupt enabled

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Reset and clock control (RCC) RM0451

7.3.5

Clock interrupt flag register (

RCC_CIFR)

Address: 0x14

Reset value: 0x0000 0000

Access: no wait state, word, half-word and byte access

Res.

CSS

HSEF r

CSS

LSEF r

Res.

MSI

RDYF r

PLL

RDYF r

HSE

RDYF r

HSI16

RDYF r

LSE

RDYF r

LSI

RDYF r

Bits 31:9 Reserved, must be kept at reset value.

Bit 8 CSSHSEF: Clock Security System Interrupt flag

This bit is reset by software by writing the CSSHSEC bit. It is set by hardware in case of HSE clock failure.

0: No clock security interrupt caused by HSE clock failure

1: Clock security interrupt caused by HSE clock failure

Bit 7 CSSLSEF: LSE Clock Security System Interrupt flag

This bit is reset by software by writing the CSSLSEC bit. It is set by hardware in case of LSE clock failure and the CSSLSE is set.

0: No failure detected on LSE clock failure

1: Failure detected on LSE clock failure

Bit:6 Reserved, must be kept at reset value.

Bit 5 MSIRDYF: MSI ready interrupt flag

This bit is reset by software by writing the MSIRDYC bit. It is set by hardware when the MSI clock becomes stable and the MSIRDYIE is set.

0: No clock ready interrupt caused by MSI clock failure

1: Clock ready interrupt caused by MSI clock failure

Bit 4 PLLRDYF: PLL ready interrupt flag

This bit is reset by software by writing the PLLRDYC bit. It is set by hardware when the PLL clock becomes stable and the PLLRDYIE is set.

0: No clock ready interrupt caused by PLL clock failure

1: Clock ready interrupt caused by PLL clock failure

Bit 3 HSERDYF: HSE ready interrupt flag

This bit is reset by software by writing the HSERDYC bit. It is set by hardware when the HSE clock becomes stable and the HSERDYIE is set.

0: No clock ready interrupt caused by HSE clock failure

1: Clock ready interrupt caused by HSE clock failure

166/784 RM0451 Rev 3

RM0451 Reset and clock control (RCC)

Bit 2 HSI16RDYF: HSI16 ready interrupt flag

This bit is reset by software by writing the HSI16RDYC bit. It is set by hardware when the

HSE clock becomes stable and the HSI16RDYIE is set.

0: No clock ready interrupt caused by HSI16 clock failure

1: Clock ready interrupt caused by HSI16 clock failure

Bit 1 LSERDYF: LSE ready interrupt flag

This bit is reset by software by writing the LSERDYC bit. It is set by hardware when the LSE clock becomes stable and the LSERDYIE is set.

0: No clock ready interrupt caused by LSE clock failure

1: Clock ready interrupt caused by LSE clock failure

Bit 0 LSIRDYF: LSI ready interrupt flag

This bit is reset by software by writing the LSIRDYC bit. It is set by hardware when the LSI clock becomes stable and the LSIRDYIE is set.

0: No clock ready interrupt caused by LSI clock failure

1: Clock ready interrupt caused by LSI clock failure

7.3.6

Clock interrupt clear register (

RCC_CICR)

Address: 0x18

Reset value: 0x0000 0000

Access: no wait state, word, half-word and byte access

Res.

CSS

HSEC w

CSS

LSEC w

Res.

MSI

RDYC w

PLL

RDYC w

HSE

RDYC w

HSI16

RDYC w

LSE

RDYIC w

LSI

RDYC w

Bits 31:9 Reserved, must be kept at reset value.

Bit 8 CSSHSEC: Clock Security System Interrupt clear

This bit is set by software to clear the CSSHSEF flag. It is reset by hardware.

0: No effect

1: CSSHSEF flag cleared

Bit 7 CSSLSEC: LSE Clock Security System Interrupt clear

This bit is set by software to clear the CSSLSEF flag. It is reset by hardware.

0: No effect

1: CSSLSEF flag cleared

Bit:6 Reserved, must be kept at reset value.

Bit 5 MSIRDYC: MSI ready Interrupt clear

This bit is set by software to clear the MSIRDYF flag. It is reset by hardware.

0: No effect

1: MSIRDYF flag cleared

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Reset and clock control (RCC)

Bit 4 PLLRDYC: PLL ready Interrupt clear

This bit is set by software to clear the PLLRDYF flag. It is reset by hardware.

0: No effect

1: PLLRDYF flag cleared

Bit 3 HSERDYC: HSE ready Interrupt clear

This bit is set by software to clear the HSERDYF flag. It is reset by hardware.

0: No effect

1: HSERDYF flag cleared

Bit 2 HSI16RDYC: HSI16 ready Interrupt clear

This bit is set by software to clear the HSI16RDYF flag. It is reset by hardware.

0: No effect

1: HSI16RDYF flag cleared

Bit 1 LSERDYC: LSE ready Interrupt clear

This bit is set by software to clear the LSERDYF flag. It is reset by hardware.

0: No effect

1: LSERDYF flag cleared

Bit 0 LSIRDYC: LSI ready Interrupt clear

This bit is set by software to clear the LSIRDYF flag. It is reset by hardware.

0: No effect

1: LSIRDYF flag cleared

RM0451

Res.

Address: 0x1C

Reset value: 0x0000 0000

Access: no wait state, word, half-word and byte access

Res.

IOPH

RST rw

Res.

Bits 31:8 Reserved, must be kept at reset value.

Bit 7 IOPHRST: I/O port H reset

This bit is set and cleared by software.

0: no effect

1: resets I/O port H

Bits 6:5 Reserved, must be kept at reset value.

Bit 4 IOPERST: I/O port E reset

This bit is set and cleared by software.

0: no effect

1: resets I/O port E

Res.

IOPER

ST rw

IOPD

RST rw

IOPC

RST rw

IOPB

RST rw

IOPA

RST rw

168/784 RM0451 Rev 3

RM0451 Reset and clock control (RCC)

Bit 3 IOPDRST: I/O port D reset

This bit is set and cleared by software.

0: no effect

1: resets I/O port D

Bit 2 IOPCRST: I/O port C reset

This bit is set and cleared by software.

0: no effect

1: resets I/O port C

Bit 1 IOPBRST: I/O port B reset

This bit is set and cleared by software.

0: no effect

1: resets I/O port B

Bit 0 IOPARST: I/O port A reset

This bit is set and cleared by software.

0: no effect

1: resets I/O port A

7.3.8

Res.

AHB peripheral reset register (RCC_AHBRSTR)

Address offset: 0x20

Reset value: 0x0000 0000

Access: no wait state, word, half-word and byte access.

Res.

CRC

RST rw

Res.

MIF

RST rw

Res.

Bits 31:25 Reserved, must be kept at reset value.

Bits 24:20 Reserved, must be kept at reset value.

Bits 19:16 Reserved, must be kept at reset value.

Bits 15: 13 Reserved, must be kept at reset value.

Bit 12 CRCRST: Test integration module reset

This bit is set and reset by software.

0: no effect

1: resets test integration module

Bits 11:9 Reserved, must be kept at reset value.

Res.

DMA

RST rw

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Reset and clock control (RCC)

Bit 8 MIFRST: Memory interface reset

This bit is set and reset by software.

This reset can be activated only when the E2 is in I

DDQ

0: no effect

mode.

1: resets memory interface

Bits 7:1 Reserved, must be kept at reset value.

Bit 0 DMARST: DMA reset

This bit is set and reset by software.

0: no effect

1: resets DMA

RM0451

Res.

Address offset: 0x24

Reset value: 0x00000 0000

Access: no wait state, word, half-word and byte access

Res.

DBG

RST rw

Res.

SPI1

RST rw

Res.

ADC

RST rw

Res.

Bits 31:23 Reserved, must be kept at reset value.

Bit 22 DBGRST: DBG reset

This bit is set and cleared by software.

0: No effect

1: Resets DBG

Bits 21:14 Reserved, must be kept at reset value.

Bit 13 Reserved, must be kept at reset value.

Bit 12 SPI1RST: SPI 1 reset

This bit is set and cleared by software.

0: No effect

1: Reset SPI 1

Bits 11:10 Reserved, must be kept at reset value.

Bit 9 ADCRST: ADC interface reset

This bit is set and cleared by software.

0: No effect

1: Reset ADC interface

Bits 8:6 Reserved, must be kept at reset value.

Res.

TIM22

RST rw

Res.

TIM21

RST rw

Res.

SYSCF

GRST rw

170/784 RM0451 Rev 3

RM0451 Reset and clock control (RCC)

Bit 5 TIM22RST: TIM22 timer reset

This bit is set and cleared by software.

0: No effect

1: Reset TIM22 timer

Bits 4:3 Reserved, must be kept at reset value.

Bit 2 TIM21RST: TIM21 timer reset

This bit is set and cleared by software.

0: No effect

1: Reset TIM21 timer

Bit 1 Reserved, must be kept at reset value.

Bit 0 SYSCFGRST: System configuration controller reset

This bit is set and cleared by software.

0: No effect

1: Reset System configuration controller

Address offset: 0x28

Reset value: 0x0000 0000

Access: no wait state, word, half-word and byte access

LPTIM1

RST rw

Res.

PWR

RST rw

Res.

WWDG

RST rw

Res.

Bit 31 LPTIM1RST: Low-power timer reset

This bit is set and cleared by software.

0: No effect

1: Resets low-power timer

Bit 30 Reserved, must be kept at reset value.

Bit 29 Reserved, must be kept at reset value.

Bit 28 PWRRST: Power interface reset

This bit is set and cleared by software.

0: No effect

1: Reset power interface

Bit 27 Reserved, must be kept at reset value.

Bits 26:23 Reserved, must be kept at reset value.

Bit 22 Reserved, must be kept at reset value.

Res.

I2C1R

ST rw

Res.

LPUART1

RST rw

Res.

USART2

RST rw

Res.

TIM2

RST rw

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Reset and clock control (RCC)

Bit 21 I2C1RST: I2C1 reset

This bit is set and cleared by software.

0: No effect

1: Resets I2C1

Bits 20:19 Reserved, must be kept at reset value.

Bit 18 LPUART1RST: LPUART1 reset

This bit is set and cleared by software.

0: No effect

1: Resets LPUART1

Bit 17 USART2RST: USART2 reset

This bit is set and cleared by software.

0: No effect

1: Resets USART2

Bits 16:14 Reserved, must be kept at reset value.

Bits 13:12 Reserved, must be kept at reset value.

Bit 11 WWDGRST: Window watchdog reset

This bit is set and cleared by software.

0: No effect

1: Resets window watchdog

Bits 10:9 Reserved, must be kept at reset value.

Bits 8:4 Reserved, must be kept at reset value.

Bits 3:1 Reserved, must be kept at reset value.

Bit 0 TIM2RST: Timer2 reset

Set and cleared by software.

0: No effect

1: Resets timer2

RM0451

Res.

Address: 0x2C

Reset value: 0x0000 0000

Access: no wait state, word, half-word and byte access

Res.

IOPH

EN rw

Res.

IOPE

EN rw

IOPD

EN rw

IOPC

EN rw

IOPB

EN rw

IOPA

EN rw

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RM0451

Bits 31:8 Reserved, must be kept at reset value.

Bit 7 IOPHEN: I/O port H clock enable bit

This bit is set and cleared by software.

0: port H clock disabled

1: port H clock enabled

Bits 6:45 Reserved, must be kept at reset value.

Bit 4 IOPEEN: I/O port E clock enable bit

This bit is set and cleared by software.

0: port E clock disabled

1: port E clock enabled

Bit 3 IOPDEN: I/O port D clock enable bit

This bit is set and cleared by software.

0: port D clock disabled

1: port D clock enabled

Bit 2 IOPCEN: IO port C clock enable bit

This bit is set and cleared by software.

0: port C clock disabled

1: port C clock enabled

Bit 1 IOPBEN: IO port B clock enable bit

This bit is set and cleared by software.

0: port B clock disabled

1: port B clock enabled

Bit 0 IOPAEN: IO port A clock enable bit

This bit is set and cleared by software.

0: port A clock disabled

1: port A clock enabled

Reset and clock control (RCC)

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Reset and clock control (RCC) RM0451

7.3.12 AHB peripheral clock enable register (RCC_AHBENR)

Address offset: 0x30

Reset value: 0x0000 0100

Access: no wait state, word, half-word and byte access

When the peripheral clock is not active, the peripheral register values may not be readable by software and the returned value is always 0x0.

Res.

CRC

EN rw

Res.

MIF

EN rw

Res.

Bits 31:25 Reserved, must be kept at reset value.

Bits 24:20 Reserved, must be kept at reset value.

Bits 19:16 Reserved, must be kept at reset value.

Bits 15:13 Reserved, must be kept at reset value.

Bit 12 CRCEN: CRC clock enable bit

This bit is set and reset by software.

0: Test integration module clock disabled

1: Test integration module clock enabled

Bits 11:9 Reserved, must be kept at reset value.

Bit 8 MIFEN: NVM interface clock enable bit

This bit is set and reset by software.

This reset can be activated only when the NVM is in power-down mode.

0: NVM interface clock disabled

1: NVM interface clock enabled

Bits 7:1 Reserved, must be kept at reset value.

Bit 0 DMAEN: DMA clock enable bit

This bit is set and reset by software.

0: DMA clock disabled

1: DMA clock enabled

Res.

DMA

EN rw

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RM0451 Reset and clock control (RCC)

Note:

Res.

Address: 0x34

Reset value: 0x0000 0000

Access: word, half-word and byte access

No wait states, except if the access occurs while an access to a peripheral in the APB2 domain is on going. In this case, wait states are inserted until the access to APB2 peripheral is finished.

When the peripheral clock is not active, the peripheral register values may not be readable by software and the returned value is always 0x0.

Res.

SPI1

EN rw

Res.

ADC

EN rw

Res.

8 7

Res.

FWEN rs

DBG

EN rw

Res.

TIM22

EN rw

Res.

TIM21

EN rw

Res.

SYSCF

EN rw

Bits 31:23 Reserved, must be kept at reset value.

Bit 22 DBGEN: DBG clock enable bit

This bit is set and cleared by software.

0: DBG clock disabled

1: DBG clock enabled

Bits 21:14 Reserved, must be kept at reset value.

Bit 13 Reserved, must be kept at reset value.

Bit 12 SPI1EN: SPI1 clock enable bit

This bit is set and cleared by software.

0: SPI1 clock disabled

1: SPI1 clock enabled

Bits 11:10 Reserved, must be kept at reset value.

Bit 9 ADCEN: ADC clock enable bit

This bit is set and cleared by software.

0: ADC clock disabled

1: ADC clock enabled

Bit 8 Reserved, must be kept at reset value.

Bit 7 FWEN: Firewall clock enable bit

This bit is set by software and reset by hardware. Software can only program this bit to 1.

Writing 0 has not effect.

0: Firewall disabled

1: Firewall clock enabled

Bit 6 Reserved, must be kept at reset value.

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Reset and clock control (RCC)

Bit 5 TIM22EN: TIM22 timer clock enable bit

This bit is set and cleared by software.

0:TIM22 clock disabled

1: TIM22 clock enabled

Bits 4:3 Reserved, must be kept at reset value.

Bit 2 TIM21EN: TIM21 timer clock enable bit

This bit is set and cleared by software.

0: TIM21 clock disabled

1: TIM21 clock enabled

Bit 1 Reserved, must be kept at reset value.

Bit 0 SYSCFGEN: System configuration controller clock enable bit

This bit is set and cleared by software.

0: System configuration controller clock disabled

1: System configuration controller clock enabled

RM0451

176/784 RM0451 Rev 3

RM0451 Reset and clock control (RCC)

Note:

Address: 0x38

Reset value: 0x0000 0000

Access: word, half-word and byte access

No wait state, except if the access occurs while an access to a peripheral on APB1 domain is on going. In this case, wait states are inserted until this access to APB1 peripheral is finished.

When the peripheral clock is not active, the peripheral register values may not be readable by software and the returned value is always 0x0.

LPTIM1

EN rw

Res.

PWRE

N rw

Res.

Res

WWDG

EN rw

Res.

I2C1E

N rw

Res.

LPUART1

USART2

EN rw

2 rw

Res.

TIM2E

N rw

Bit 31 LPTIM1EN: Low-power timer clock enable bit

This bit is set and cleared by software.

0: Low-power timer clock disabled

1: Low-power timer clock enabled

Bit 30 Reserved, must be kept at reset value.

Bit 28 PWREN: Power interface clock enable bit

This bit is set and cleared by software.

0: Power interface clock disabled

1: Power interface clock enabled

Bit 27 Reserved, must be kept at reset value.

Bits 26:23 Reserved, must be kept at reset value.

Bit 22 Reserved, must be kept at reset value.

Bit 21 I2C1EN: I2C1 clock enable bit

This bit is set and cleared by software.

0: I2C1 clock disabled

1: I2C1 clock enabled

Bits 20:19 Reserved, must be kept at reset value.

Bit 18 LPUART1EN: LPUART1 clock enable bit

This bit is set and cleared by software.

0: LPUART1 clock disabled

1: LPUART1 clock enabled

Bit 17 USART2EN: USART2 clock enable bit

This bit is set and cleared by software.

0: USART2 clock disabled

1: USART2 clock enabled

Bits 16:14 Reserved, must be kept at reset value.

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Bits 13:12 Reserved, must be kept at reset value.

Bit 11 WWDGEN: Window watchdog clock enable bit

This bit is set and cleared by software.

0: Window watchdog clock disabled

1: Window watchdog clock enabled

Bits 10:9 Reserved, must be kept at reset value.

Bits 8:6 Reserved, must be kept at reset value.

Bits 5:1 Reserved, must be kept at reset value.

Bit 0 TIM2EN: Timer2 clock enable bit

Set and cleared by software.

0: Timer2 clock disabled

1: Timer2 clock enabled

RM0451

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RM0451 Reset and clock control (RCC)

Res.

Address: 0x3C

Reset value: the bits corresponding to the available GPIO ports are set

Access: no wait state, word, half-word and byte access

Res.

IOPHS

MEN rw

Res.

IOPES

MEN rw

IOPDS

MEN rw

IOPCS

MEN rw

IOPBS

MEN rw

IOPAS

MEN rw

Bits 31: 8 Reserved, must be kept at reset value.

Bit 7 IOPHSMEN: Port H clock enable during Sleep mode bit

This bit is set and cleared by software.

0: Port H clock is disabled in Sleep mode

1: Port H clock is enabled in Sleep mode (if enabled by IOPHEN)

Bits 6:5 Reserved, must be kept at reset value.

Bit 4 IOPESMEN: Port E clock enable during Sleep mode bit

This bit is set and cleared by software.

0: Port E clock is disabled in Sleep mode

1: Port E clock is enabled in Sleep mode (if enabled by IOPDEN)

Bit 3 IOPDSMEN: Port D clock enable during Sleep mode bit

This bit is set and cleared by software.

0: Port D clock is disabled in Sleep mode

1: Port D clock is enabled in Sleep mode (if enabled by IOPDEN)

Bit 2 IOPCSMEN: Port C clock enable during Sleep mode bit

This bit is set and cleared by software.

0: Port C clock is disabled in Sleep mode

1: Port C clock is enabled in Sleep mode (if enabled by IOPCEN)

Bit 1 IOPBSMEN: Port B clock enable during Sleep mode bit

This bit is set and cleared by software.

0: Port B clock is disabled in Sleep mode

1: Port B clock is enabled in Sleep mode (if enabled by IOPBEN)

Bit 0 IOPASMEN: Port A clock enable during Sleep mode bit

This bit is set and cleared by software.

0: Port A clock is disabled in Sleep mode

1: Port A clock is enabled in Sleep mode (if enabled by IOPAEN)

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7.3.16 AHB peripheral clock enable in Sleep mode register (RCC_AHBSMENR)

Address: 0x40

Reset value: the bits corresponding to the available peripherals are set

Access: no wait state, word, half-word and byte access

Res.

CRC

SMEN rw

Res.

SRAM

SMEN rw

MIF

SMEN rw

Res.

Bits 31:25 Reserved, must be kept at reset value.

Bits 24:20 Reserved, must be kept at reset value.

Bits 19:16 Reserved, must be kept at reset value.

Bits 15: 13 Reserved, must be kept at reset value.

Bit 12 CRCSMEN: CRC clock enable during Sleep mode bit

This bit is set and reset by software.

0: Test integration module clock disabled in Sleep mode

1: Test integration module clock enabled in Sleep mode (if enabled by CRCEN)

Bits 11:10 Reserved, must be kept at reset value.

Bit 9 SRAMSMEN: SRAM interface clock enable during Sleep mode bit

This bit is set and reset by software.

0: NVM interface clock disabled in Sleep mode

1: NVM interface clock enabled in Sleep mode

Bit 8 MIFSMEN: NVM interface clock enable during Sleep mode bit

This bit is set and reset by software.

0: NVM interface clock disabled in Sleep mode

1: NVM interface clock enabled in Sleep mode

Bits 7:1 Reserved, must be kept at reset value.

Bit 0 DMASMEN: DMA clock enable during Sleep mode bit

This bit is set and reset by software.

0: DMA clock disabled in Sleep mode

1: DMA clock enabled in Sleep mode

Res.

DMA

SMEN rw

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RM0451 Reset and clock control (RCC)

Res.

register (RCC_APB2SMENR)

Address: 0x44

Reset value: the bits corresponding to the available peripherals are set.

Access: no wait state, word, half-word and byte access

Res.

SPI1

SMEN rw

Res.

ADC

SMEN rw

Res.

DBG

SMEN rw

Res.

TIM22

SMEN rw

Res.

Bits 31:23 Reserved, must be kept at reset value.

Bit 22 DBGSMEN: DBG clock enable during Sleep mode bit

This bit is set and cleared by software.

0: DBG clock disabled in Sleep mode

1: DBG clock enabled in Sleep mode (if enabled by DBGEN)

Bits 21:14 Reserved, must be kept at reset value.

Bit 13 Reserved, must be kept at reset value.

Bit 12 SPI1SMEN: SPI1 clock enable during Sleep mode bit

This bit is set and cleared by software.

0: SPI1 clock disabled in Sleep mode

1: SPI1 clock enabled in Sleep mode (if enabled by SPI1EN)

Bits 11:10 Reserved, must be kept at reset value.

Bit 9 ADCSMEN: ADC clock enable during Sleep mode bit

This bit is set and cleared by software.

0: ADC clock disabled in Sleep mode

1: ADC clock enabled in Sleep mode (if enabled by ADCEN)

Bits 8:6 Reserved, must be kept at reset value.

Bit 5 TIM22SMEN: TIM22 timer clock enable during Sleep mode bit

This bit is set and cleared by software.

0:TIM22 clock disabled in Sleep mode

1: TIM22 clock enabled in Sleep mode (if enabled by TIM22EN)

Bits 4:3 Reserved, must be kept at reset value.

Res.

TIM21

SMEN rw

Res.

SYSCF

SMEN rw

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Bit 2 TIM21SMEN: TIM21 timer clock enable during Sleep mode bit

This bit is set and cleared by software.

0: TIM21 clock disabled in Sleep mode

1: TIM21 clock enabled in Sleep mode (if enabled by TIM21EN)

Bit 1 Reserved, must be kept at reset value.

Bit 0 SYSCFGSMEN: System configuration controller clock enable during Sleep mode bit

This bit is set and cleared by software.

0: System configuration controller clock disabled in Sleep mode

1: System configuration controller clock enabled in Sleep mode

RM0451

register (RCC_APB1SMENR)

Address: 0x48

Reset value: the bits corresponding to the available peripherals are set

Access: no wait state, word, half-word and byte access Note:

LPTIM1

SMEN rw

Res.

PWRS

MEN rw

Res.

WWDG

SMEN rw

Res.

I2C1S

MEN rw

Res.

LPUART1

SMEN rw

USART2

SMEN rw

Res.

TIM2S

MEN rw

Bit 31 LPTIM1SMEN: Low-power timer clock enable during Sleep mode bit

This bit is set and cleared by software.

0: Low-power timer clock disabled in Sleep mode

1: Low-power timer clock enabled in Sleep mode (if enabled by LPTIM1EN)

Bit 30 Reserved, must be kept at reset value.

Bit 29 Reserved, must be kept at reset value.

Bit 28 PWRSMEN: Power interface clock enable during Sleep mode bit

This bit is set and cleared by software.

0: Power interface clock disabled in Sleep mode

1: Power interface clock enabled in Sleep mode (if enabled by PWREN)

Bit 27 Reserved, must be kept at reset value.

Bits 26:22 Reserved, must be kept at reset value.

Bit 21 I2C1SMEN: I2C1 clock enable during Sleep mode bit

This bit is set and cleared by software.

0: I2C1 clock disabled in Sleep mode

1: I2C1 clock enabled in Sleep mode (if enabled by I2C1EN)

Bits 20:19 Reserved, must be kept at reset value.

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Bit 18 LPUART1SMEN: LPUART1 clock enable during Sleep mode bit

This bit is set and cleared by software.

0: LPUART1 clock disabled in Sleep mode

1: LPUART1 clock enabled in Sleep mode (if enabled by LPUART1EN)

Bit 17 USART2SMEN: USART2 clock enable during Sleep mode bit

This bit is set and cleared by software.

0: USART2 clock disabled in Sleep mode

1: USART2 clock enabled in Sleep mode (if enabled by USART2EN)

Bits 16:14 Reserved, must be kept at reset value.

Bits 13:12 Reserved, must be kept at reset value.

Bit 11 WWDGSMEN: Window watchdog clock enable during Sleep mode bit

This bit is set and cleared by software.

0: Window watchdog clock disabled in Sleep mode

1: Window watchdog clock enabled in Sleep mode (if enabled by WWDGEN)

Bits 10:9 Reserved, must be kept at reset value.

Bits 8:4 Reserved, must be kept at reset value.

Bits 3:1 Reserved, must be kept at reset value.

Bit 0 TIM2SMEN: Timer2 clock enable during Sleep mode bit

Set and cleared by software.

0: Timer2 clock disabled in Sleep mode

1: Timer2 clock enabled in Sleep mode (if enabled by TIM2EN)

Address: 0x4C

Reset value: 0x0000 0000

Access: no wait state, word, half-word and byte access

Res.

I2C1

SEL1 rw

Res.

I2C1

SEL0 rw

LPUART1

SEL1

LPUART1

SEL0 rw rw

Res.

LPTIM1

SEL1 rw

USART2

SEL1 rw

LPTIM1S

EL0 rw

USART2

SEL0 rw

Res.

Bits 31:26 Reserved, must be kept at reset value.

Bits 25:20 Reserved, must be kept at reset value.

Bits 19:18 LPTIM1SEL: Low-power Timer clock source selection bits

This bit is set and cleared by software.

00: APB clock selected as LP Timer clock

01: LSI clock selected as LP Timer clock

10: HSI16 clock selected as LP Timer clock

11: LSE clock selected as LP Timer clock

Bits 17:14 Reserved, must be kept at reset value.

Res.

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Bits 13:12

I2C1SEL: I2C1 clock source selection bits

This bit is set and cleared by software.

00: APB clock selected as I2C1 clock

01: System clock selected as I2C1 clock

10: HSI16 clock selected as I2C1 clock

11: not used

Bits 11:10

LPUART1SEL: LPUART1 clock source selection bits

This bit is set and cleared by software.

00: APB clock selected as LPUART1 clock

01: System clock selected as LPUART1 clock

10: HSI16 clock selected as LPUART1 clock

11: LSE clock selected as LPUART1 clock

Bits 9:4 Reserved, must be kept at reset value.

Bits 3:2 USART2SEL: USART2 clock source selection bits

This bit is set and cleared by software.

00: APB clock selected as USART2 clock

01: System clock selected as USART2 clock

10: HSI16 clock selected as USART2 clock

11: LSE clock selected as USART2 clock

Bits 1:0 Reserved, must be kept at reset value.

7.3.20 Control/status register (RCC_CSR)

Note:

Address: 0x50

Power-on reset value: 0x0C00 0004

Access: 0 ≤ wait state ≤ 3, word, half-word and byte access

Wait states are inserted in case of successive accesses to this register.

The LSEON, LSEBYP, RTCSEL,LSEDRV and RTCEN bits in the RCC control and status register (RCC_CSR) are in the RTC domain. As these bits are write protected after reset, the DBP bit in the Power control register (PWR_CR) has to be set to be able to modify them.

Refer to Section 6.1.2: RTC and RTC backup registers for further information. These bits are only reset after a RTC domain reset (see Section 6.1.2

). Any internal or external reset does not have any effect on them.

LPWR

RSTF r

Res.

WWDG

RSTF r

IWDG

RSTF r

CSSLS

ED r

CSSLS

EON rw

SFT

RSTF r

LSEDRV[1:0] rw

POR

RSTF r

LSE

BYP rw

OBL

RS TF r

9 r

RSTF r

8 rw

RMVF rt_w

LSERDY LSEON Res.

Res.

RTC

RST .

Res.

RTC

EN rw

Res.

17 16

RTCSEL[1:0] rw

LSI

RDY r rw

LSION rw

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Bit 31 LPWRRSTF: Low-power reset flag

This bit is set by hardware when a Low-power management reset occurs.

It is cleared by writing to the RMVF bit, or by a POR.

0: No Low-power management reset occurred

1: Low-power management reset occurred

For further information on Low-power management reset, refer to

Section : Low-power management reset

Bit 30 WWDGRSTF: Window watchdog reset flag

This bit is set by hardware when a window watchdog reset occurs.

It is cleared by writing to the RMVF bit, or by a POR.

0: No window watchdog reset occurred

1: Window watchdog reset occurred

Bit 29 IWDGRSTF : Independent watchdog reset flag

This bit is set by hardware when an independent watchdog reset from V

It is cleared by writing to the RMVF bit, or by a POR.

domain occurs.

0: No watchdog reset occurred

1: Watchdog reset occurred

Bit 28 SFTRSTF: Software reset flag

This bit is set by hardware when a software reset occurs.

It is cleared by writing to the RMVF bit, or by a POR.

0: No software reset occurred

1: Software reset occurred

Bit 27 PORRSTF: POR/PDR reset flag

This bit is set by hardware when a POR/PDR reset occurs.

It is cleared by writing to the RMVF bit.

0: No POR/PDR reset occurred

1: POR/PDR reset occurred

Bit 26 PINRSTF: PIN reset flag

This bit is set by hardware when a reset from the NRST pin occurs.

It is cleared by writing to the RMVF bit, or by a POR.

0: No reset from NRST pin occurred

1: Reset from NRST pin occurred

Bit 25 OBLRSTF Options bytes loading reset flag

This bit is set by hardware when an OBL reset occurs.

It is cleared by writing to the RMVF bit, or by a POR.

0: No OBL reset occurred

1: OBL reset occurred

Bit 24 FWRSTF : Firewall reset flag

This bit is set by hardware when the firewall has generated a reset. It is cleared by writing to the RMVF bit, or by a power-on reset.

0: No firewall reset occurred

1: firewall reset occurred

Bit 23 RMVF: Remove reset flag

This bit is set by software to clear the reset flags.

0: No effect

1: Clear the reset flags

Bits 22:20 Reserved, must be kept at reset value.

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Bit 19 RTCRST: RTC software reset bit

This bit is set and cleared by software.

0: Reset not activated

1: Resets the RTC peripheral, its clock source selection and the backup registers.

Bit 18 RTCEN: RTC clock enable bit

This bit is set and cleared by software.

It is reset by setting the RTCRST bit or by a POR.

0: RTC clock disabled

1: RTC clock enabled

Bits 17:16 RTCSEL[1:0]: RTC clock source selection bits

These bits are set by software to select the clock source for the RTC.

Once the RTC clock source has been selected it cannot be switched until RTCRST is set or a Power On Reset occurred. The only exception is if the LSE oscillator clock was selected, if the LSE clock stops and it is detected by the CSSLSE, in that case the clock can be switched.

00: No clock

01: LSE oscillator clock used as RTC clock

10: LSI oscillator clock used as RTC clock

11: HSE oscillator clock divided by a programmable prescaler (selection through the

RTCPRE[1:0] bits in the RCC clock control register (RCC_CR)) used as the RTC clock

If the LSE or LSI is used as RTC clock source, the RTC continues to work in Stop and

Standby low-power modes, and can be used as wake-up source. However, when the HSE clock is used as RTC clock source, the RTC cannot be used in Stop and Standby low-power modes.

Bit 15 Reserved, must be kept at reset value.

Bit 14 CSSLSED: CSS on LSE failure detection flag

This bit is set by hardware to indicate when a failure has been detected by the clock security system on the external 32 kHz oscillator (LSE).

It is cleared by a power-on reset or by an RTC software reset (RTCRST bit).

0: No failure detected on LSE (32 kHz oscillator)

1: Failure detected on LSE (32 kHz oscillator)

Bit 13 CSSLSEON CSS on LSE enable bit

This bit is set by software to enable the Clock Security System on LSE (32 kHz oscillator).

CSSLSEON must be enabled after the LSE and LSI oscillators are enabled (LSEON and

LSION bits enabled) and ready (LSERDY and LSIRDY flags set by hardware), and after the

RTCSEL bit is selected.

Once enabled this bit cannot be disabled, except after an LSE failure detection (CSSLSED

=1). In that case the software MUST disable the CSSLSEON bit.

Reset by power on reset and RTC software reset (RTCRST bit).

0: CSS on LSE (32 kHz oscillator) OFF

1: CSS on LSE (32 kHz oscillator) ON

Bits 12-11

LSEDRV; LSE oscillator Driving capability bits

These bits are set by software to select the driving capability of the LSE oscillator.

They are cleared by a power-on reset or an RTC reset. Once “00” has been written, the content of LSEDRV cannot be changed by software.

00: Lowest drive

01: Medium low drive

10: Medium high drive

11: Highest drive

RM0451 Rev 3

RM0451 Reset and clock control (RCC)

Bit 10 LSEBYP: External low-speed oscillator bypass bit

This bit is set and cleared by software to bypass oscillator in debug mode. This bit can be written only when the LSE oscillator is disabled.

It is reset by setting the RTCRST bit or by a POR.

0: LSE oscillator not bypassed

1: LSE oscillator bypassed

Bit 9 LSERDY: External low-speed oscillator ready bit

This bit is set and cleared by hardware to indicate when the LSE oscillator is stable. After the

LSEON bit is cleared, LSERDY goes low after 6 LSE oscillator clock cycles.

It is reset by setting the RTCRST bit or by a POR.

0: External 32 kHz oscillator not ready

1: External 32 kHz oscillator ready

Bit 8 LSEON: External low-speed oscillator enable bit

This bit is set and cleared by software.

It is reset by setting the RTCRST bit or by a POR.

0: LSE oscillator OFF

1:LSE oscillator ON

Bits 7:3 Reserved, must be kept at reset value.

Bit 1 LSIRDY: Internal low-speed oscillator ready bit

This bit is set and cleared by hardware to indicate when the LSI oscillator is stable. After the

LSION bit is cleared, LSIRDY goes low after 3 LSI oscillator clock cycles.

This bit is reset by system reset.

0: LSI oscillator not ready

1: LSI oscillator ready

Bit 0 LSION: Internal low-speed oscillator enable bit

This bit is set and cleared by software.

It is reset by system reset.

0: LSI oscillator OFF

1: LSI oscillator ON

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7.3.21 RCC register map

The following table gives the RCC register map and the reset values.

Table 40. RCC register map and reset values

Offset

Register

RM0451

0x00

0x04

0x08

RCC_CR

Reset value

RCC_ICSCR

Reset value

RCC_CFGR

0x0C

Reset value

RCC_CIER

0x10

Reset value

RCC_CIFR

0x14

Reset value

RCC_CICR

0x18

0x1C

0x20

Reset value

RCC_IOPRSTR

Reset value

RCC_AHBRSTR

Reset value

RTC

PRE

[1:0]

0 0 X X 0 X 0 0 1 1

HSI16TRIM[4:0

]

0 0 0 0 0 0

MSITRIM[7:0] MSICAL[7:0]

MSIRAN

GE[2:0]

HSI16CAL[7:0]

0 0 0 0 0 0 0 0 x x x x x x x x 1 0 1 1 0 0 0 0 x x x x x x x x

Reserved

MCOPR

[2:0]

0 0 0

MCOSE

L [3:0]

PLL

DIV

[1:0]

PLLMUL[3:

0 0 0 0 0 0 0 0 0 0 0

PPRE2

[2:0]

PPRE1

[2:0]

HPRE[3:0]

SWS

[1:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0

0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

0 0 0 0 0 0

0x24

RCC_APB2RSTR

Reset value 0 0 0 0 0 0

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RM0451

Offset

Register

Reset and clock control (RCC)

Table 40. RCC register map and reset values (continued)

0x28

RCC_APB1RSTR

0x2C

0x30

Reset value

RCC_IOPENR

Reset value

RCC_AHBENR

Reset value

0x34

RCC_APB2ENR

Reset value

0x38

RCC_APB1ENR

Reset value 0

0x3C

RCC_IOPSMEN

Reset value

0x40

RCC_AHBSMENR

Reset value

0x44

RCC_APB2SMENR

Reset value

0x48

RCC_APB1SMENR

Reset value 1

0 0 0

0 0

0 0 0 0 0 0

0 0 0 0 0

1 1 1 1 1 1

1 1 1

1 1 1 1 1

1 1 1

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Table 40. RCC register map and reset values (continued)

Offset

Register

0x4C

RCC_CCIPR

0x50

Reset value

RCC_CSR

0 0

RTC

SEL

[1:0]

0 0 0 0

LSE

DRV

[1:0]

0 0 0 0 0 0 0 Reset value 0 0 0 0 1 1 0 0 0

Refer to Section 2.2 on page 39 for the register boundary addresses.

RM0451

0 0

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RM0451

8 General-purpose I/Os (GPIO)

General-purpose I/Os (GPIO)

8.1 Introduction

Each general-purpose I/O port has four 32-bit configuration registers (GPIOx_MODER,

GPIOx_OTYPER, GPIOx_OSPEEDR and GPIOx_PUPDR), two 32-bit data registers

(GPIOx_IDR and GPIOx_ODR) and a 32-bit set/reset register (GPIOx_BSRR). In addition all GPIOs have a 32-bit locking register (GPIOx_LCKR) and two 32-bit alternate function selection registers (GPIOx_AFRH and GPIOx_AFRL).

8.2 GPIO main features

• Output states: push-pull or open drain + pull-up/down

• Output data from output data register (GPIOx_ODR) or peripheral (alternate function output)

• Speed selection for each I/O

• Input states: floating, pull-up/down, analog

• Input data to input data register (GPIOx_IDR) or peripheral (alternate function input)

• Bit set and reset register (GPIOx_ BSRR) for bitwise write access to GPIOx_ODR

• Locking mechanism (GPIOx_LCKR) provided to freeze the I/O port configurations

• Analog function

• Alternate function selection registers

• Fast toggle capable of changing every two clock cycles

• Highly flexible pin multiplexing allows the use of I/O pins as GPIOs or as one of several peripheral functions

8.3 GPIO functional description

Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each port bit of the general-purpose I/O (GPIO) ports can be individually configured by software in several modes:

• Input floating

• Input pull-up

• Input-pull-down

• Analog

• Output open-drain with pull-up or pull-down capability

• Output push-pull with pull-up or pull-down capability

• Alternate function push-pull with pull-up or pull-down capability

• Alternate function open-drain with pull-up or pull-down capability

Each I/O port bit is freely programmable, however the I/O port registers have to be accessed as 32-bit words, half-words or bytes. The purpose of the GPIOx_BSRR register is to allow atomic read/modify accesses to any of the GPIOx_ODR registers. In this way, there is no risk of an IRQ occurring between the read and the modify access.

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General-purpose I/Os (GPIO) RM0451

Figure 18

and

Figure 19 show the basic structures of a standard and a 5-Volt tolerant I/O

port bit, respectively.

Table 41

gives the possible port bit configurations.

Figure 18. Basic structure of an I/O port bit

To on-chip peripheral

Analog

Alternate function input on/off

Read

Write

Read/write

From on-chip peripheral

Alternate function output

trigger

Input driver

Output driver

Output control

DDIOx

P-MOS

N-MOS

Push-pull, open-drain or disabled on/off

DDIOx

Pull up

Protection diode

I/O pin on/off

Pull down

Protection diode

Analog

MS31476V1

Figure 19. Basic structure of a 5-Volt tolerant I/O port bit

To on-chip peripheral

Alternate function input on/off

Read

Write

Read/write

From on-chip peripheral Alternate function output

TTL Schmitt

trigger

Input driver

Output driver

Output control

DDIOx

P-MOS

N-MOS

Push-pull, open-drain or disabled on/off

DDIOx

VDD_FT

(1)

Pull up

Protection diode

I/O pin on/off

Pull down

Protection diode ai15939d

1. V

DD_FT is a potential specific to 5-Volt tolerant I/Os and different from V

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RM0451 General-purpose I/Os (GPIO)

MODE(i)

[1:0]

Table 41. Port bit configuration table (1)

OTYPER(i)

OSPEED(i)

[1:0]

PUPD(i)

[1:0]

I/O configuration

11 x x x x x

1 x x x

0 x x x x x x x x

SPEED

[1:0]

SPEED

[1:0] x x x x x x x x

GP output

Reserved

GP output

Reserved

PP + PU

PP + PD

OD + PU

OD + PD

Reserved (GP output OD)

AF PP

AF PP + PU

PP + PD AF

Reserved

AF OD

OD + PU

OD + PD

Input

Floating

Reserved (input floating)

Input/output Analog

Reserved

1. GP = general-purpose, PP = push-pull, PU = pull-up, PD = pull-down, OD = open-drain, AF = alternate function.

During and just after reset, the alternate functions are not active and most of the I/O ports are configured in analog mode.

The debug pins are in AF pull-up/pull-down after reset:

• PA14: SWCLK in pull-down

• PA13: SWDIO in pull-up

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General-purpose I/Os (GPIO)

8.3.2

RM0451

When the pin is configured as output, the value written to the output data register

(GPIOx_ODR) is output on the I/O pin. It is possible to use the output driver in push-pull mode or open-drain mode (only the low level is driven, high level is HI-Z).

The input data register (GPIOx_IDR) captures the data present on the I/O pin at every AHB clock cycle.

All GPIO pins have weak internal pull-up and pull-down resistors, which can be activated or not depending on the value in the GPIOx_PUPDR register.

I/O pin alternate function multiplexer and mapping

The device I/O pins are connected to on-board peripherals/modules through a multiplexer that allows only one peripheral alternate function (AF) connected to an I/O pin at a time. In this way, there can be no conflict between peripherals available on the same I/O pin.

Each I/O pin has a multiplexer with up to sixteen alternate function inputs (AF0 to AF15) that can be configured through the GPIOx_AFRL (for pin 0 to 7) and GPIOx_AFRH (for pin 8 to

15) registers:

• After reset the multiplexer selection is alternate function 0 (AF0). The I/Os are configured in alternate function mode through GPIOx_MODER register.

• The specific alternate function assignments for each pin are detailed in the device datasheet.

In addition to this flexible I/O multiplexing architecture, each peripheral has alternate functions mapped onto different I/O pins to optimize the number of peripherals available in smaller packages.

To use an I/O in a given configuration, the user has to proceed as follows:

• Debug function: after each device reset these pins are assigned as alternate function pins immediately usable by the debugger host

• GPIO: configure the desired I/O as output, input or analog in the GPIOx_MODER register.

• Peripheral alternate function:

– Connect the I/O to the desired AFx in one of the GPIOx_AFRL or GPIOx_AFRH register.

– Select the type, pull-up/pull-down and output speed via the GPIOx_OTYPER,

GPIOx_PUPDR and GPIOx_OSPEEDER registers, respectively.

– Configure the desired I/O as an alternate function in the GPIOx_MODER register.

• Additional functions:

– For the ADC configure the desired I/O in analog mode in the GPIOx_MODER register and configure the required function in the ADC registers.

– For the additional functions like RTC, WKUPx and oscillators, configure the required function in the related RTC, PWR and RCC registers. These functions have priority over the configuration in the standard GPIO registers.

Refer to the “Alternate function mapping” table in the device datasheet for the detailed mapping of the alternate function I/O pins.

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RM0451

8.3.3

8.3.4

8.3.5

General-purpose I/Os (GPIO)

I/O port control registers

Each of the GPIO ports has four 32-bit memory-mapped control registers (GPIOx_MODER,

GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR) to configure up to 16 I/Os. The

GPIOx_MODER register is used to select the I/O mode (input, output, AF, analog). The

GPIOx_OTYPER and GPIOx_OSPEEDR registers are used to select the output type (pushpull or open-drain) and speed. The GPIOx_PUPDR register is used to select the pullup/pull-down whatever the I/O direction.

I/O port data registers

Each GPIO has two 16-bit memory-mapped data registers: input and output data registers

(GPIOx_IDR and GPIOx_ODR). GPIOx_ODR stores the data to be output, it is read/write accessible. The data input through the I/O are stored into the input data register

(GPIOx_IDR), a read-only register.

See

Section 8.4.5: GPIO port input data register (GPIOx_IDR) (x = A to E and H)

and

Section 8.4.6: GPIO port output data register (GPIOx_ODR) (x = A to E and H)

for the register descriptions.

I/O data bitwise handling

The bit set reset register (GPIOx_BSRR) is a 32-bit register which allows the application to set and reset each individual bit in the output data register (GPIOx_ODR). The bit set reset register has twice the size of GPIOx_ODR.

To each bit in GPIOx_ODR, correspond two control bits in GPIOx_BSRR: BS(i) and BR(i).

When written to 1, bit BS(i) sets the corresponding ODR(i) bit. When written to 1, bit BR(i) resets the ODR(i) corresponding bit.

Writing any bit to 0 in GPIOx_BSRR does not have any effect on the corresponding bit in

GPIOx_ODR. If there is an attempt to both set and reset a bit in GPIOx_BSRR, the set action takes priority.

Using the GPIOx_BSRR register to change the values of individual bits in GPIOx_ODR is a

“one-shot” effect that does not lock the GPIOx_ODR bits. The GPIOx_ODR bits can always be accessed directly. The GPIOx_BSRR register provides a way of performing atomic bitwise handling.

There is no need for the software to disable interrupts when programming the GPIOx_ODR at bit level: it is possible to modify one or more bits in a single atomic AHB write access.

It is possible to freeze the GPIO control registers by applying a specific write sequence to the GPIOx_LCKR register. The frozen registers are GPIOx_MODER, GPIOx_OTYPER,

GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.

To write the GPIOx_LCKR register, a specific write / read sequence has to be applied. When the right LOCK sequence is applied to bit 16 in this register, the value of LCKR[15:0] is used to lock the configuration of the I/Os (during the write sequence the LCKR[15:0] value must be the same). When the LOCK sequence has been applied to a port bit, the value of the port bit can no longer be modified until the next MCU reset or peripheral reset. Each

GPIOx_LCKR bit freezes the corresponding bit in the control registers (GPIOx_MODER,

GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.

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General-purpose I/Os (GPIO) RM0451

The LOCK sequence (refer to

Section 8.4.8: GPIO port configuration lock register

(GPIOx_LCKR) (x = A to E and H)

) can only be performed using a word (32-bit long) access to the GPIOx_LCKR register due to the fact that GPIOx_LCKR bit 16 has to be set at the same time as the [15:0] bits.

For code example, refer to

A.5.1: Locking mechanism code example

For more details refer to LCKR register description in Section 8.4.8: GPIO port configuration lock register (GPIOx_LCKR) (x = A to E and H)

8.3.8

Two registers are provided to select one of the alternate function inputs/outputs available for each I/O. With these registers, the user can connect an alternate function to some other pin as required by the application.

This means that a number of possible peripheral functions are multiplexed on each GPIO using the GPIOx_AFRL and GPIOx_AFRH alternate function registers. The application can thus select any one of the possible functions for each I/O. The AF selection signal being common to the alternate function input and alternate function output, a single channel is selected for the alternate function input/output of a given I/O.

To know which functions are multiplexed on each GPIO pin refer to the device datasheet.

For code example, refer to

A.5.2: Alternate function selection sequence code example

External interrupt/wakeup lines

All ports have external interrupt capability. To use external interrupt lines, the port must be configured in input mode.

Refer to Section 12: Extended interrupt and event controller (EXTI)

and to Section 12.3.2:

Wakeup event management.

When the I/O port is programmed as input:

• The output buffer is disabled

• The Schmitt trigger input is activated

• The pull-up and pull-down resistors are activated depending on the value in the

GPIOx_PUPDR register

• The data present on the I/O pin are sampled into the input data register every AHB clock cycle

• A read access to the input data register provides the I/O state

Figure 20

shows the input configuration of the I/O port bit.

196/784 RM0451 Rev 3

RM0451 General-purpose I/Os (GPIO)

Figure 20. Input floating / pull up / pull down configurations

Read

Write

Read/write on input driver output driver

TTL Schmitt

trigger

VDDIOx

VDDIOx on/off pull up protection diode

I/O pin on/off pull down

VSS VSS protection diode

MS31477V1

When the I/O port is programmed as output:

• The output buffer is enabled:

– Open drain mode: A “0” in the Output register activates the N-MOS whereas a “1” in the Output register leaves the port in Hi-Z (the P-MOS is never activated)

– Push-pull mode: A “0” in the Output register activates the N-MOS whereas a “1” in the Output register activates the P-MOS

• The Schmitt trigger input is activated

• The pull-up and pull-down resistors are activated depending on the value in the

GPIOx_PUPDR register

• The data present on the I/O pin are sampled into the input data register every AHB clock cycle

• A read access to the input data register gets the I/O state

• A read access to the output data register gets the last written value

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General-purpose I/Os (GPIO)

Figure 21

shows the output configuration of the I/O port bit.

Figure 21. Output configuration

RM0451 on

Read

Write

Read/write

Input driver

Output driver

TTL Schmitt

trigger

Output control

DDIOx

P-MOS

N-MOS

Push-pull or

Open-drain

DDIOx

DDIOx on/off protection diode pull up

I/O pin on/off

SS pull down

SS protection diode

MS31478V1

8.3.11 Alternate function configuration

When the I/O port is programmed as alternate function:

• The output buffer can be configured in open-drain or push-pull mode

• The output buffer is driven by the signals coming from the peripheral (transmitter enable and data)

• The Schmitt trigger input is activated

• The weak pull-up and pull-down resistors are activated or not depending on the value in the GPIOx_PUPDR register

• The data present on the I/O pin are sampled into the input data register every AHB clock cycle

• A read access to the input data register gets the I/O state

Figure 22

shows the alternate function configuration of the I/O port bit.

Figure 22. Alternate function configuration

To on-chip peripheral

Alternate function input

Read on

Write

Read/write

From on-chip peripheral

Alternate function output

TTL Schmitt trigger

Input driver

Output driver

Output control

P-MOS

N-MOS push-pull or open-drain

VDDIOx VDDIOx on/off

Pull up protection diode

I/O pin on/off

Pull down

SS V

SS protection diode

MSv34756V1

198/784 RM0451 Rev 3

RM0451 General-purpose I/Os (GPIO)

When the I/O port is programmed as analog configuration:

• The output buffer is disabled

• The Schmitt trigger input is deactivated, providing zero consumption for every analog value of the I/O pin. The output of the Schmitt trigger is forced to a constant value (0).

• The weak pull-up and pull-down resistors are disabled by hardware

• Read access to the input data register gets the value “0”

For code example, refer to

A.5.3: Analog GPIO configuration code example .

Figure 23

shows the high-impedance, analog-input configuration of the I/O port bits.

Figure 23. High impedance-analog configuration

To on-chip peripheral

Read

Analog

Write

Read/write

Input driver off

TTL Schmitt

trigger

DDIOx protection diode

I/O pin

SS protection diode

From on-chip peripheral

Analog

MS31480V1

8.3.13 Using the HSE or LSE oscillator pins as GPIOs

When the HSE or LSE oscillator is switched OFF (default state after reset), the related oscillator pins can be used as normal GPIOs.

When the HSE or LSE oscillator is switched ON (by setting the HSEON or LSEON bit in the

RCC_CSR register) the oscillator takes control of its associated pins and the GPIO configuration of these pins has no effect.

When the oscillator is configured in a user external clock mode, only the OSC_IN, CK_IN or

OSC32_IN pin is reserved for clock input and the OSC_OUT or OSC32_OUT pin can still be used as normal GPIO.

8.3.14 Using the GPIO pins in the RTC supply domain

The PC13/PC14/PC15/PA0/PA2 GPIO functionality is lost when the core supply domain is powered off (when the device enters Standby mode). In this case, if their GPIO configuration is not bypassed by the RTC configuration, these pins are set in an analog input mode.

For details about I/O control by the RTC, refer to

Section 19.4: RTC functional description .

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8.3.15 BOOT0/GPIO pin sharing

On category 1 devices, the BOOT0 pin is shared with a GPIO pin. The BOOT0 pin input level can be read as an input value on the shared GPIO pin. This pin features specific input voltage characteristics (refer to the corresponding datasheet for more details).

For a summary of register bits, register address offsets and reset values, refer to Table 42

The peripheral registers can be written in word, half word or byte mode.

8.4.1 GPIO port mode register (GPIOx_MODER)

(x =A to E and H)

Address offset:0x00

Reset value: 0xEBFF FCFF for port A

Reset value: 0xFFFF FFFF for the other ports

31 30

MODE15[1:0] rw

15 rw

MODE7[1:0] rw rw

29 28

MODE14[1:0] rw

13 rw

MODE6[1:0] rw rw

27 26

MODE13[1:0] rw

11 rw

MODE5[1:0] rw rw

25 24

MODE12[1:0] rw

9 rw

MODE4[1:0] rw rw

23 22

MODE11[1:0] rw

7 rw

MODE3[1:0] rw rw

21 20

MODE10[1:0] rw

5 rw

MODE2[1:0] rw rw

Bits 31:0 MODE[15:0][1:0]: Port x configuration I/O pin y (y = 15 to 0)

These bits are written by software to configure the I/O mode.

00: Input mode

01: General purpose output mode

10: Alternate function mode

11: Analog mode (reset state)

19 18

MODE9[1:0] rw

3 rw

MODE1[1:0] rw rw

17 16

MODE8[1:0] rw

1 rw

MODE0[1:0] rw rw

8.4.2

Res.

GPIO port output type register (GPIOx_OTYPER)

(x = A to E and H)

Address offset: 0x04

Reset value: 0x0000 0000

Res.

15 14 13 12 11 10

OT15 OT14 OT13 OT12 OT11 OT10 rw rw rw rw rw rw

OT9 rw

OT8 rw

OT7 rw

OT6 rw

OT5 rw

OT4 rw

OT3 rw

OT2 rw

OT1 rw

OT0 rw

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RM0451 General-purpose I/Os (GPIO)

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 OT[15:0]: Port x configuration I/O pin y (y = 15 to 0)

These bits are written by software to configure the I/O output type.

0: Output push-pull (reset state)

1: Output open-drain

8.4.3 GPIO port output speed register (GPIOx_OSPEEDR)

(x = A to E and H)

Address offset: 0x08

Reset value: 0x0C00 0000 (for port A)

Reset value: 0x0000 0000 (for the other ports)

31 30

OSPEED15

[1:0] rw rw

15 14

OSPEED7

[1:0] rw rw

29 28

OSPEED14

[1:0] rw rw

13 12

OSPEED6

[1:0] rw rw

27 26

OSPEED13

[1:0] rw rw

11 10

OSPEED5

[1:0] rw rw

25 24

OSPEED12

[1:0] rw rw

9 8

OSPEED4

[1:0] rw rw

23 22

OSPEED11

[1:0] rw rw

7 6

OSPEED3

[1:0] rw rw

21 20

OSPEED10

[1:0] rw rw

5 4

OSPEED2

[1:0] rw rw

19 18

OSPEED9

[1:0] rw rw

3 2

OSPEED1

[1:0] rw rw

17 16

OSPEED8

[1:0] rw rw

1 0

OSPEED0

[1:0] rw rw

Bits 31:0 OSPEED[15:0][1:0] : Port x configuration I/O pin y (y = 15 to 0)

These bits are written by software to configure the I/O output speed.

00: Low speed

01: Medium speed

10: High speed

11: Very high speed

Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed..

8.4.4 GPIO port pull-up/pull-down register (GPIOx_PUPDR)

(x = A to E and H)

Address offset: 0x0C

Reset value: 0x2400 0000 (for port A)

Reset value: 0x0000 0000 (for the other ports)

31 30

PUPD15[1:0] rw rw

15 14

PUPD7[1:0] rw rw

29 28

PUPD14[1:0] rw rw

13 12

PUPD6[1:0] rw rw

27 26

PUPD13[1:0] rw rw

11 10

PUPD5[1:0] rw rw

25 24

PUPD12[1:0] rw rw

9 8

PUPD4[1:0] rw rw

23 22

PUPD11[1:0] rw rw

7 6

PUPD3[1:0] rw rw

21 20

PUPD10[1:0] rw rw

5 4

PUPD2[1:0] rw rw

19 18

PUPD9[1:0] rw rw

3 2

PUPD1[1:0] rw rw

17 16

PUPD8[1:0] rw rw

1 0

PUPD0[1:0] rw rw

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General-purpose I/Os (GPIO) RM0451

Bits 31:0 PUPD[15:0][1:0]: Port x configuration I/O pin y (y = 15 to 0)

These bits are written by software to configure the I/O pull-up or pull-down

00: No pull-up, pull-down

01: Pull-up

10: Pull-down

11: Reserved

8.4.5 GPIO input data register (GPIOx_IDR)

(x = A to E and H)

Address offset: 0x10

Reset value: 0x0000 XXXX

Res.

ID15 r

ID14 r

ID13 r

ID12 r

ID11 r

ID10 r

ID9 r

ID8 r

ID7 r

ID6 r

ID5 r

ID4 r

ID3 r

ID2 r

ID1 r

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 ID[15:0]: Port x input data I/O pin y (y = 15 to 0)

These bits are read-only. They contain the input value of the corresponding I/O port.

ID0 r

8.4.6

Res.

GPIO port output data register (GPIOx_ODR)

(x = A to E and H)

Address offset: 0x14

Reset value: 0x0000 0000

Res.

15 14 13 12

OD15 OD14 OD13 OD12 rw rw rw rw

11 10

OD11 OD10 rw rw

OD9 rw

OD8 rw

OD7 rw

OD6 rw

OD5 rw

OD4 rw

OD3 rw

OD2 rw

OD1 rw

OD0 rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 OD[15:0]: Port output data I/O pin y (y = 15 to 0)

These bits can be read and written by software.

Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the

GPIOx_BSRR register (x = A..E and H).

202/784 RM0451 Rev 3

RM0451 General-purpose I/Os (GPIO)

8.4.7 GPIO port bit set/reset register (GPIOx_BSRR)

(x = A to E and H)

Address offset: 0x18

Reset value: 0x0000 0000

BR15 w

BS15 w

BR14 w

BS14 w

BR13 w

BS13 w

BR12 w

BS12 w

BR11 w

BS11 w

BR10 w

BS10 w

BR9 w

BS9 w

BR8 w

BS8 w

BR7 w

BS7 w

BR6 w

BS6 w

BR5 w

BS5 w

BR4 w

BS4 w

Bits 31:16 BR[15:0]: Port x reset I/O pin y (y = 15 to 0)

These bits are write-only. A read to these bits returns the value 0x0000.

0: No action on the corresponding ODx bit

1: Resets the corresponding ODx bit

Note: If both BSx and BRx are set, BSx has priority.

Bits 15:0 BS[15:0]: Port x set I/O pin y (y = 15 to 0)

These bits are write-only. A read to these bits returns the value 0x0000.

0: No action on the corresponding ODx bit

1: Sets the corresponding ODx bit

BR3 w

BS3 w

BR2 w

BS2 w

BR1 w

BS1 w

8.4.8

Note:

GPIO port configuration lock register (GPIOx_LCKR)

(x = A to E and H)

This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the

GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the

LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset.

A specific write sequence is used to write to the GPIOx_LCKR register. Only word access

(32-bit long) is allowed during this locking sequence.

Each lock bit freezes a specific configuration register (control and alternate function registers).

Address offset: 0x1C

Reset value: 0x0000 0000

Res.

LCKK rw

0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

LCK15 LCK14 LCK13 LCK12 LCK11 LCK10 LCK9 LCK8 LCK7 LCK6 LCK5 LCK4 LCK3 LCK2 LCK1 LCK0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

BR0 w

BS0 w

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General-purpose I/Os (GPIO) RM0451

Bits 31:17 Reserved, must be kept at reset value.

Bit 16 LCKK: Lock key

This bit can be read any time. It can only be modified using the lock key write sequence.

0: Port configuration lock key not active

1: Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset.

LOCK key write sequence:

WR LCKR[16] = 1 + LCKR[15:0]

WR LCKR[16] = 0 + LCKR[15:0]

WR LCKR[16] = 1 + LCKR[15:0]

RD LCKR

RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active)

Note: During the LOCK key write sequence, the value of LCK[15:0] must not change.

Any error in the lock sequence aborts the lock.

After the first lock sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset.

Bits 15:0 LCK[15:0]: Port x lock I/O pin y (y = 15 to 0)

These bits are read/write but can only be written when the LCKK bit is 0.

0: Port configuration not locked

1: Port configuration locked

31 rw

15 rw

(x = A to E and H)

Address offset: 0x20

Reset value: 0x0000 0000

30 29

AFSEL7[3:0] rw

14 rw

AFSEL3[3:0] rw rw

28 rw

27 rw

26 25

AFSEL6[3:0] rw

10 rw

AFSEL2[3:0] rw rw

24 rw

23 rw

22 21

AFSEL5[3:0] rw

6 rw

AFSEL1[3:0] rw rw

20 rw

19 rw

3 rw rw rw rw rw rw

Bits 31:0 AFSEL[7:0][3:0]: Alternate function selection for port x I/O pin y (y = 7 to 0)

These bits are written by software to configure alternate function I/Os.

0000: AF0

0001: AF1

0010: AF2

0011: AF3

0100: AF4

0101: AF5

0110: AF6

0111: AF7

Others: Reserved

18 17

AFSEL4[3:0] rw

2 rw

AFSEL0[3:0] rw rw

16 rw

0 rw

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RM0451 General-purpose I/Os (GPIO)

31 rw

15 rw

(x = A to E and H)

Address offset: 0x24

Reset value: 0x0000 0000

30 29

AFSEL15[3:0] rw

14 rw

AFSEL11[3:0] rw rw

28 rw

27 rw

26 25

AFSEL14[3:0] rw

10 rw

AFSEL10[3:0] rw rw

24 rw

23 rw

22 21

AFSEL13[3:0] rw

6 rw

AFSEL9[3:0] rw rw

20 rw

19 rw

3 rw rw rw rw rw rw

Bits 31:0 AFSEL[15:8][3:0]: Alternate function selection for port x I/O pin y (y = 15 to 8)

These bits are written by software to configure alternate function I/Os.

0000: AF0

0001: AF1

0010: AF2

0011: AF3

0100: AF4

0101: AF5

0110: AF6

0111: AF7

Others: Reserved

18 17

AFSEL12[3:0] rw

2 rw

AFSEL8[3:0] rw rw

16 rw

0 rw

8.4.11 GPIO port bit reset register (GPIOx_BRR) (x = A to E and H)

Address offset: 0x28

Reset value: 0x0000 0000

Res.

BR15 w

BR14 w

BR13 w

BR12 w

BR11 w

BR10 w

BR9 w

BR8 w

BR7 w

BR6 w

BR5 w

BR4 w

BR3 w

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 BR[15:0]: Port x reset IO pin y (y = 15 to 0)

These bits are write-only. A read to these bits returns the value 0x0000.

0: No action on the corresponding ODx bit

1: Reset the corresponding ODx bit

BR2 w

BR1 w

BR0 w

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8.4.12 GPIO register map

The following table gives the GPIO register map and reset values.

Table 42. GPIO register map and reset values

Offset Register name

RM0451

0x00

GPIOA_MODER

Reset value 1 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1

0x00

GPIOx_MODER

(where x = B..E, H )

Reset value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

0x00

GPIOx_MODER

(where x = C..K

)

0x04

Reset value

GPIOx_OTYPER

(where x = A..E,H )

Reset value

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x08

GPIOA_OSPEEDR

Reset value 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x08

GPIOx_OSPEEDR

(where x = B..E,H )

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPIOA_PUPDR

0x0C

0x10

0x14

0x18

0x1C

Reset value

GPIOx_IDR

(where x = A..E,H )

Reset value

GPIOx_ODR

(where x = A..E,H )

Reset value

GPIOx_BSRR

(where x = A..E,H )

Reset value

GPIOx_LCKR

(where x = A..E,H )

Reset value

0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x x x x x x x x x

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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RM0451 General-purpose I/Os (GPIO)

Offset Register name

Table 42. GPIO register map and reset values (continued)

0x20

0x24

0x28

GPIOx_AFRL

(where x = A..E,H )

Reset value

GPIOx_AFRH

(where x = A..E,H )

Reset value

GPIOx_BRR

(where x = A..E,H )

Reset value

AFSEL7[3:0] AFSEL6[3:0] AFSEL5[3:0] AFSEL4[3:0] AFSEL3[3:0] AFSEL2[3:0] AFSEL1[3:0] AFSEL0[3:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15[3:0]

AFSEL14[3:0

]

AFSEL13[3:0

]

AFSEL12[3:0

]

AFSEL11[3:0

]

AFSEL10[3:0] AFSEL9[3:0] AFSEL8[3:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Refer to Section 2.2 on page 39 for the register boundary addresses.

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9 System configuration controller (SYSCFG)

RM0451

9.1 Introduction

Note:

The devices feature a set of configuration registers. The main purposes of the system configuration controller are the following:

• Remapping memories

• Remapping some trigger sources to timer input capture channels

• Managing external interrupts line multiplexing to the internal edge detector

• Enabling dedicated functions such as input capture multiplexing or oscillator pin remapping

• Firewall management

• Internal voltage reference management for ADC

The Cortex

-M0+ can wake up from WFE (Wait For Event) when a transition occurs on the eventin input signal. To support semaphore management in multiprocessor environment, the core can also output events on the signal output EVENTOUT, during SEV instruction execution.

In STM32L010xx devices, an event input can be generated by an external interrupt line or by an RTC alarm interrupt. It is also possible to select which output pin is connected to the

EVENTOUT signal of the Cortex

-M0+. The EVENTOUT multiplexing is managed by the

GPIO alternate function capability (see

Section 8.4.9: GPIO alternate function low register

(GPIOx_AFRL) (x = A to E and H) and

Section 8.4.10: GPIO alternate function high register

(GPIOx_AFRH) (x = A to E and H) ).

EVENTOUT is not mapped on all GPIOs (for example PC13, PC14, PC15).

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RM0451 System configuration controller (SYSCFG)

The peripheral registers have to be accessed by words (32-bit).

9.2.1

Res.

SYSCFG memory remap register (SYSCFG_CFGR1)

This register is used for specific configurations related to memory remap.

It is not reset through the SYSCFGRST bit in the RCC_APB2RSTR register.

Address offset: 0x00

Reset value: 0x000x 000x (X is the memory mode selected by the boot configuration).

Res.

)

Res.

9 8

BOOT_MODE r r

Res.

1 0

MEM_MODE rw rw

Bits 31:10 Reserved, must be kept at reset value

Bits 9:8 BOOT_MODE: Boot mode selected by the boot pins status bits

These bits are read-only. They indicate the boot mode selected by the boot configuration

(see Section 2.4: Boot configuration ).

00: Main Flash memory boot mode

01: System Flash memory boot mode

10: Reserved

11: Embedded SRAM boot mode

Bits 7:3 Reserved, must be kept at reset value

Bit 2 Reserved, must be kept at reset value

Bits 1:0 MEM_MODE: Memory mapping selection bits

These bits are set and cleared by software. This bit controls the memory’s internal mapping at address 0x0000 0000. After reset these bits take on the memory mapping selected by the

boot configuration (see Section 2.4: Boot configuration ).

00: Main Flash memory mapped at 0x0000 0000

01: System Flash memory mapped at 0x0000 0000

10: reserved

11: SRAM mapped at 0x0000 0000.

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9.2.2

RM0451

SYSCFG peripheral mode configuration register (SYSCFG_CFGR2)

Address offset: 0x04

Reset value: 0x0000 0001

31 30

Res.

19 18 17 16

Res.

Res. Res.

Res.

15 14

Res.

3 2 1 0

Res.

Res. Res.

FWDIS rw

Bits 31:1 Reserved, must be kept at reset value

Bit 0 FWDIS: Firewall disable bit

This bit is set by default (after reset). It is cleared by software to protect the access to the memory segments according to the Firewall configuration.Once cleared it cannot be set by software. Only a system reset set the bit.

0: Firewall access enabled

1: Firewall access disabled

Note: This bit cannot be set by an APB reset. A system reset is required to set it.

9.2.3

REF_

LOCK rs

VREFINT

_RDYF r

Res.

Reference control and status register (SYSCFG_CFGR3)

The SYSCFG_CFGR3 register is the reference control/status register. It contains all the bits/flags related to VREFINT.

Address offset: 0x20

System reset value: 0x0000 0000

Res.

23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res.

Res.

8 7 6

ENBUF_

VREFINT

_ ADC

Res. Res.

SEL_VREF

_OUT rw

4 rw

3 2 1 0

Res. Res. Res.

EN_VR

EFINT rw

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RM0451 System configuration controller (SYSCFG)

Bit 31 REF_LOCK: SYSCFG_CFGR3 lock bit

This bit is set by software and cleared by a hardware system reset. It locks the whole content of the reference control/Status register, SYSCFG_CFGR3[31:0].

0: SYSCFG_CFGR3[31:0] bits are read/write

1: SYSCFG_CFGR3[31:0] bits are read-only

Bit 30 VREFINT_RDYF: VREFINT ready flag

This bit is read-only. It shows the state of the internal voltage reference, VREFINT. When set, it indicates that VREFINT is available for BOR.

0: VREFINT OFF

1: VREFINT ready

Bits 29:9 Reserved, must be kept at reset value

Bit 8 ENBUF_VREFINT_ADC : VREFINT reference for ADC enable bit

This bit is set and cleared by software (only if REF_LOCK not set).

0: Disables the buffer used to generate VREFINT reference for the ADC.

1: Enables the buffer used to generate VREFINT reference for the ADC.

Bits 7:6 Reserved, must be kept at reset value

Bits 5:4 SEL_VREF_OUT : VREFINT_ADC connection bit

These bits are set and cleared by software (only if REF_LOCK not set). These bits select which pad is connected to VREFINT_ADC when ENBUF_VREFINT_ADC is set.

00: no pad connected

01: PB0 connected

10: PB1 connected

11: PB0 and PB1 connected

Bits 3:1 Reserved, must be kept at reset value

Bit 0 EN_VREFINT : VREFINT enable

This bit is set and cleared by software (only if REF_LOCK not set). It switches on VREFINT internal reference voltage.

0: VREFINT voltage disabled in low-power mode (if ULP=1)

1: VREFINT voltage enabled in low-power mode

Note: It is forbidden to configure both EN_VREFINT=1 and ULP=1 if the device is in Stop mode or in Sleep/Low-power sleep mode (refer to Section 6.4.1: PWR power control register (PWR_CR) for a description of the ULP bit). If the device is not in low-power mode, VREFINT is always enabled whatever the state of EN_VREFINT and ULP. The scaler must be enabled to provide V

REFINT buffering and scaling).

voltage (the scaler performs V

REFINT

9.2.4

15 rw

SYSCFG external interrupt configuration register 1

(SYSCFG_EXTICR1)

Address offset: 0x08

Reset value: 0x0000

30 29 28 27 26 25 22 21 20

12 11

24 23

Reserved

8 7 4 14 13

EXTI3[3:0] rw rw rw rw

10 9

EXTI2[3:0] rw rw rw rw

6 5

EXTI1[3:0] rw rw rw

3 rw

18 17

2 1

EXTI0[3:0] rw rw

0 rw

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System configuration controller (SYSCFG) RM0451

Bits 31:16 Reserved

Bits 15:0 EXTIx[3:0] : EXTI x configuration (x = 0 to 3)

These bits are written by software to select the source input for the EXTIx external interrupt.

0000: PA[x] pin

0001: PB[x] pin

0010: PC[x] pin

0011: PD[x] pin

0100: PE[x] pin

0101: PH[x] (only PH[1:0] and PH[10:9])

Other configurations are reserved

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RM0451 System configuration controller (SYSCFG)

9.2.5

15 rw

SYSCFG external interrupt configuration register 2

(SYSCFG_EXTICR2)

Address offset: 0x0C

Reset value: 0x0000

30 29 28 27 26 25 24 23

Reserved

8 7

22 21 20 19 18 17 16

14 13

EXTI7[3:0] rw rw

12 rw

11 rw

10 9

EXTI6[3:0] rw rw rw rw

6 5

EXTI5[3:0] rw rw

4 rw

3 rw

2 1

EXTI4[3:0] rw rw

0 rw

Bits 31:16 Reserved

Bits 15:0 EXTIx[3:0] : EXTI x configuration (x = 4 to 7)

These bits are written by software to select the source input for the EXTIx external interrupt.

0000: PA[x] pin

0001: PB[x] pin

0010: PC[x] pin

0011: PD[x] pin

0100: PE[x] pin

Other configurations are reserved

9.2.6

15 rw

SYSCFG external interrupt configuration register 3

(SYSCFG_EXTICR3)

Address offset: 0x10

Reset value: 0x0000

30 29 28 27 26 25 24 23

Reserved

8 7

22 21 20 19 18 17 16

14 13

EXTI11[3:0] rw rw

12 rw

11 rw

10 9

EXTI10[3:0] rw rw rw rw

6 5

EXTI9[3:0] rw rw

4 rw

3 rw

2 1

EXTI8[3:0] rw rw

0 rw

Bits 31:16 Reserved

Bits 15:0 EXTIx[3:0] : EXTI x configuration (x = 8 to 11)

These bits are written by software to select the source input for the EXTIx external interrupt.

0000: PA[x] pin

0001: PB[x] pin

0010: PC[x] pin

0011: PD[x] pin

0100: PE[x] pin

0101: PH[x] (only PH[1:0] and PH[10:9])

Other configurations are reserved.

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9.2.7 SYSCFG external interrupt configuration register 4

(SYSCFG_EXTICR4)

Address offset: 0x14

Reset value: 0x0000

31 30 29 28 27 26 25 24 23

Reserved

8 7

22 21 20 19 18 17

15 rw

14 13

EXTI15[3:0] rw rw

12 rw

11 rw

10 9

EXTI14[3:0] rw rw rw rw

6 5

EXTI13[3:0] rw rw

4 rw

3 rw

2 1

EXTI12[3:0] rw rw

Bits 31:16 Reserved

Bits 15:0 EXTIx[3:0] : EXTI x configuration (x = 12 to 15)

These bits are written by software to select the source input for the EXTIx external interrupt.

0000: PA[x] pin

0001: PB[x] pin

0010: PC[x] pin

0011: PD[x] pin

0100: PE[x] pin

Other configurations are reserved.

0 rw

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9.2.8

System configuration controller (SYSCFG)

SYSCFG register map

The following table gives the SYSCFG register map and the reset values.

Table 43. SYSCFG register map and reset values

Offset Register

0x00

SYSCFG_CFGR1

Reset value

0x04 SYSCFG_CFGR2

0x08

0x0C

0x10

0x14

Reset value

SYSCFG_

EXTICR1

Reset value

SYSCFG_

EXTICR2

Reset value

SYSCFG_

EXTICR3

Reset value

SYSCFG_

EXTICR4

Reset value x x

0x20

SYSCFG_CFGR3

Reset value 0 0

Refer to Section 2.2 on page 39 for the register boundary addresses.

0 0 0 x x

EXTI3[3:0] EXTI2[3:0] EXTI1[3:0] EXTI0[3:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EXTI7[3:0] EXTI6[3:0] EXTI5[3:0] EXTI4[3:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EXTI11[3:0] EXTI10[3:0] EXTI9[3:0] EXTI8[3:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EXTI15[3:0] EXTI14[3:0] EXTI13[3:0] EXTI12[3:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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Direct memory access controller (DMA)

10 Direct memory access controller (DMA)

RM0451

10.1 Introduction

The direct memory access (DMA) controller is a bus master and system peripheral.

The DMA is used to perform programmable data transfers between memory-mapped peripherals and/or memories, upon the control of an off-loaded CPU.

The DMA controller features a single AHB master architecture.

There is one instance of DMA with up to 7 channels, except for the category 1 devices that only feature 5 channels.

Each channel is dedicated to managing memory access requests from one or more peripherals. The DMA includes an arbiter for handling the priority between DMA requests.

10.2 DMA main features

• Single AHB master

• Peripheral-to-memory, memory-to-peripheral, memory-to-memory and peripheral-toperipheral data transfers

• Access, as source and destination, to on-chip memory-mapped devices such as Flash memory, SRAM, and AHB and APB peripherals

• All DMA channels independently configurable:

– Each channel is associated either with a DMA request signal coming from a peripheral, or with a software trigger in memory-to-memory transfers. This configuration is done by software.

– Priority between the requests is programmable by software (4 levels per channel: very high, high, medium, low) and by hardware in case of equality (such as request to channel 1 has priority over request to channel 2).

– Transfer size of source and destination are independent (byte, half-word, word), emulating packing and unpacking. Source and destination addresses must be aligned on the data size.

– Support of transfers from/to peripherals to/from memory with circular buffer management

– Programmable number of data to be transferred: 0 to 2 16 - 1

• Generation of an interrupt request per channel. Each interrupt request is caused from any of the three DMA events: transfer complete, half transfer, or transfer error.

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RM0451 Direct memory access controller (DMA)

10.3.1 DMA

DMA is implemented with the hardware configuration parameters shown in the table below.

Table 44. DMA implementation

Feature

Number of channels

1. 7 channels except for category 1 devices that feature 5 channels.

DMA up to7

(1)

DMA controller

The hardware requests from the peripherals (TIM2, ADC, SPI1, I2C1, USART2 and

LPUART1) are mapped to the DMA channels through the DMA_CSELR channel selection registers (see

Figure 24

The peripheral DMA requests can be independently activated/de-activated by programming the DMA control bit in the registers of the corresponding peripheral.

Caution: A same peripheral request can be assigned to two different channels only if the application ensures that these channels are not requested to be served at the same time. In other words, if two different channels receive a same asserted peripheral request at the same time, an unpredictable DMA hardware behavior occurs.

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Direct memory access controller (DMA)

Figure 24. DMA request mapping

Fixed hardware priority

High priority

Peripheral request signals

ADC, TIM2_CH3

SW trigger 1

(MEM2MEM bit)

ADC, SPI1_RX,

LPUART1_TX, I2C1_TX

TIM2_UP, USART2_TX

(1)

SW trigger 2

(MEM2MEM bit) 4

C1S

C2S

DMA

SPI1_TX, LPUART1_RX, I2C1_RX,

TIM2_CH2, USART2_RX

(1)

SW trigger 3

(MEM2MEM bit) 4

ADC

(1)

, SPI_RX

(1)

USART2_TX,

, LPUART1_TX

(1)

I2C1_TX

(1)

, TIM2_CH4

SW trigger 4

(MEM2MEM bit) 4

USART2_RX,

TIM2_CH1, SPI_TX

(1)

LPUART1_RX

(1)

, I2C1_RX

(1)

SW trigger 5

(MEM2MEM bit)

USART2_RX, LPUART1_RX,

I2C1_TX

SW trigger 6

(MEM2MEM bit)

USART2_TX,

LPUART1_TX, I2C1_RX,

TIM2_CH2, TIM2_CH4

SW trigger 7

(MEM2MEM bit)

C3S

C4S

C5S

C6S

C7S

DMA_CSELR

Low priority

Internal DMA request

RM0451

MSv46195V1

1. Only available on category 1 devices.

Table 45. DMA requests for each channel

CxS[3:0] Peripheral Channel 1 Channel 2 Channel 3 Channel 4 Channel 5

0000

0001

0100

0101

ADC

SPI1

USART2

LPUART1

ADC

Channel 6

(1)

Channel 7

(1)

ADC

SPI1_RX

SPI1_TX

ADC

(2)

SPI1_RX

(2)

SPI1_TX

(2)

USART2_

(2)

LPUART1_

USART2_

(2)

LPUART1_

USART2_

LPUART1_

(2)

USART2_

LPUART1_

(2)

USART2_

LPUART1_

USART2_

LPUART1_

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RM0451 Direct memory access controller (DMA)

Table 45. DMA requests for each channel (continued)

CxS[3:0] Peripheral Channel 1 Channel 2 Channel 3 Channel 4 Channel 5

Channel 6

(1)

0110

1000

I2C1

TIM2

TIM2_

CH3

1. Not available on category 1 devices.

2. Available only on category 1 devices.

I2C1_TX I2C1_RX I2C1_TX

(2)

I2C1_RX

(2)

TIM2_UP TIM2_CH2 TIM2_CH4 TIM2_CH1

I2C1_TX

Channel 7

(1)

I2C1_RX

TIM2_CH2

TIM2_CH4

10.4 DMA functional description

The DMA block diagram is shown in the figure below.

Figure 25. DMA block diagram

FLITF Flash

System

Cortex-M0+

SRAM

DMA

Reset &

Clock control

(RCC)

CRC

DMA

Ch.1

Ch.2

Arbiter up to

Ch.7

AHB

Slave

DMA request

Bridge

APB

ADC

SPI1

USART2

LPUART1

I2C1

TIM2

MSv46194V1

The DMA controller performs direct memory transfer by sharing the AHB system bus with other system masters. The bus matrix implements round-robin scheduling. DMA requests may stop the CPU access to the system bus for a number of bus cycles, when CPU and

DMA target the same destination (memory or peripheral).

According to its configuration through the AHB slave interface, the DMA controller arbitrates between the DMA channels and their associated received requests. The DMA controller also schedules the DMA data transfers over the single AHB port master.

The DMA controller generates an interrupt per channel to the interrupt controller.

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Direct memory access controller (DMA) RM0451

Note:

The software configures the DMA controller at channel level, in order to perform a block transfer, composed of a sequence of AHB bus transfers.

A DMA block transfer may be requested from a peripheral, or triggered by the software in case of memory-to-memory transfer.

After an event, the following steps of a single DMA transfer occur:

The peripheral sends a single DMA request signal to the DMA controller.

2. The DMA controller serves the request, depending on the priority of the channel associated to this peripheral request.

3. As soon as the DMA controller grants the peripheral, an acknowledge is sent to the peripheral by the DMA controller.

4. The peripheral releases its request as soon as it gets the acknowledge from the DMA controller.

5. Once the request is de-asserted by the peripheral, the DMA controller releases the acknowledge.

The peripheral may order a further single request and initiate another single DMA transfer.

The request/acknowledge protocol is used when a peripheral is either the source or the destination of the transfer. For example, in case of memory-to-peripheral transfer, the peripheral initiates the transfer by driving its single request signal to the DMA controller. The

DMA controller reads then a single data in the memory and writes this data to the peripheral.

For a given channel x, a DMA block transfer consists of a repeated sequence of:

• a single DMA transfer, encapsulating two AHB transfers of a single data, over the DMA

AHB bus master:

– a single data read (byte, half-word or word) from the peripheral data register or a location in the memory, addressed through an internal current peripheral/memory address register.

The start address used for the first single transfer is the base address of the peripheral or memory, and is programmed in the DMA_CPARx or DMA_CMARx register.

– a single data write (byte, half-word or word) to the peripheral data register or a location in the memory, addressed through an internal current peripheral/memory address register.

The start address used for the first transfer is the base address of the peripheral or memory, and is programmed in the DMA_CPARx or DMA_CMARx register.

• post-decrementing of the programmed DMA_CNDTRx register

This register contains the remaining number of data items to transfer (number of AHB

‘read followed by write’ transfers).

This sequence is repeated until DMA_CNDTRx is null.

The AHB master bus source/destination address must be aligned with the programmed size of the transferred single data to the source/destination.

The DMA arbiter manages the priority between the different channels.

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When an active channel x is granted by the arbiter (hardware requested or software triggered), a single DMA transfer is issued (such as a AHB ‘read followed by write’ transfer of a single data). Then, the arbiter considers again the set of active channels and selects the one with the highest priority.

The priorities are managed in two stages:

• software: priority of each channel is configured in the DMA_CCRx register, to one of the four different levels:

– very high

– high

– medium

– low

• hardware: if two requests have the same software priority level, the channel with the lowest index gets priority. For example, channel 2 gets priority over channel 4.

When a channel x is programmed for a block transfer in memory-to-memory mode, re arbitration is considered between each single DMA transfer of this channel x. Whenever there is another concurrent active requested channel, the DMA arbiter automatically alternates and grants the other highest-priority requested channel, which may be of lower priority than the memory-to-memory channel.

Each channel may handle a DMA transfer between a peripheral register located at a fixed address, and a memory address. The amount of data items to transfer is programmable.

The register that contains the amount of data items to transfer is decremented after each transfer.

A DMA channel is programmed at block transfer level.

Programmable data sizes

The transfer sizes of a single data (byte, half-word, or word) to the peripheral and memory are programmable through, respectively, the PSIZE[1:0] and MSIZE[1:0] fields of the

DMA_CCRx register.

Pointer incrementation

The peripheral and memory pointers may be automatically incremented after each transfer, depending on the PINC and MINC bits of the DMA_CCRx register.

If the incremented mode is enabled (PINC or MINC set to 1), the address of the next transfer is the address of the previous one incremented by 1, 2 or 4, depending on the data size defined in PSIZE[1:0] or MSIZE[1:0]. The first transfer address is the one programmed in the DMA_CPARx or DMA_CMARx register. During transfers, these registers keep the initially programmed value. The current transfer addresses (in the current internal peripheral/memory address register) are not accessible by software.

If the channel x is configured in non-circular mode , no DMA request is served after the last data transfer (once the number of single data to transfer reaches zero). The DMA channel must be disabled in order to reload a new number of data items into the DMA_CNDTRx register.

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Note:

RM0451

If the channel x is disabled, the DMA registers are not reset. The DMA channel registers

(DMA_CCRx, DMA_CPARx and DMA_CMARx) retain the initial values programmed during the channel configuration phase.

In circular mode , after the last data transfer, the DMA_CNDTRx register is automatically reloaded with the initially programmed value. The current internal address registers are reloaded with the base address values from the DMA_CPARx and DMA_CMARx registers.

Channel configuration procedure

The following sequence is needed to configure a DMA channel x:

Set the peripheral register address in the DMA_CPARx register.

The data is moved from/to this address to/from the memory after the peripheral event, or after the channel is enabled in memory-to-memory mode.

2. Set the memory address in the DMA_CMARx register.

The data is written to/read from the memory after the peripheral event or after the channel is enabled in memory-to-memory mode.

3. Configure the total number of data to transfer in the DMA_CNDTRx register.

After each data transfer, this value is decremented.

4. Configure the parameters listed below in the DMA_CCRx register:

– the channel priority

– the data transfer direction

– the circular mode

– the peripheral and memory incremented mode

– the peripheral and memory data size

– the interrupt enable at half and/or full transfer and/or transfer error

5. Activate the channel by setting the EN bit in the DMA_CCRx register.

A channel, as soon as enabled, may serve any DMA request from the peripheral connected to this channel, or may start a memory-to-memory block transfer.

The two last steps of the channel configuration procedure may be merged into a single access to the DMA_CCRx register, to configure and enable the channel.

Channel state and disabling a channel

A channel x in active state is an enabled channel (read DMA_CCRx.EN = 1). An active channel x is a channel that must have been enabled by the software (DMA_CCRx.EN set to 1) and afterwards with no occurred transfer error (DMA_ISR.TEIFx = 0). In case there is a transfer error, the channel is automatically disabled by hardware (DMA_CCRx.EN = 0).

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Note:

Direct memory access controller (DMA)

The three following use cases may happen:

• Suspend and resume a channel

This corresponds to the two following actions:

– An active channel is disabled by software (writing DMA_CCRx.EN = 0 whereas

DMA_CCRx.EN = 1).

– The software enables the channel again (DMA_CCRx.EN set to 1) without reconfiguring the other channel registers (such as DMA_CNDTRx, DMA_CPARx and DMA_CMARx).

This case is not supported by the DMA hardware, that does not guarantee that the remaining data transfers are performed correctly.

• Stop and abort a channel

If the application does not need any more the channel, this active channel can be disabled by software. The channel is stopped and aborted but the DMA_CNDTRx register content may not correctly reflect the remaining data transfers versus the aborted source and destination buffer/register.

• Abort and restart a channel

This corresponds to the software sequence: disable an active channel, then reconfigure the channel and enable it again.

This is supported by the hardware if the following conditions are met:

– The application guarantees that, when the software is disabling the channel, a

DMA data transfer is not occurring at the same time over its master port. For example, the application can first disable the peripheral in DMA mode, in order to ensure that there is no pending hardware DMA request from this peripheral.

– The software must operate separated write accesses to the same DMA_CCRx register: First disable the channel. Second reconfigure the channel for a next block transfer including the DMA_CCRx if a configuration change is needed. There are read-only DMA_CCRx register fields when DMA_CCRx.EN=1. Finally enable again the channel.

When a channel transfer error occurs, the EN bit of the DMA_CCRx register is cleared by hardware. This EN bit can not be set again by software to re-activate the channel x, until the

TEIFx bit of the DMA_ISR register is set.

Circular mode (in memory-to-peripheral/peripheral-to-memory transfers)

The circular mode is available to handle circular buffers and continuous data flows (such as

ADC scan mode). This feature is enabled using the CIRC bit in the DMA_CCRx register.

The circular mode must not be used in memory-to-memory mode. Before enabling a channel in circular mode (CIRC = 1), the software must clear the MEM2MEM bit of the

DMA_CCRx register. When the circular mode is activated, the amount of data to transfer is automatically reloaded with the initial value programmed during the channel configuration phase, and the DMA requests continue to be served.

In order to stop a circular transfer, the software needs to stop the peripheral from generating

DMA requests (such as quit the ADC scan mode), before disabling the DMA channel.

The software must explicitly program the DMA_CNDTRx value before starting/enabling a transfer, and after having stopped a circular transfer.

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Note:

RM0451

Memory-to-memory mode

The DMA channels may operate without being triggered by a request from a peripheral. This mode is called memory-to-memory mode, and is initiated by software.

If the MEM2MEM bit in the DMA_CCRx register is set, the channel, if enabled, initiates transfers. The transfer stops once the DMA_CNDTRx register reaches zero.

The memory-to-memory mode must not be used in circular mode. Before enabling a channel in memory-to-memory mode (MEM2MEM = 1), the software must clear the CIRC bit of the DMA_CCRx register.

Peripheral-to-peripheral mode

Any DMA channel can operate in peripheral-to-peripheral mode:

• when the hardware request from a peripheral is selected to trigger the DMA channel

This peripheral is the DMA initiator and paces the data transfer from/to this peripheral to/from a register belonging to another memory-mapped peripheral (this one being not configured in DMA mode).

• when no peripheral request is selected and connected to the DMA channel

The software configures a register-to-register transfer by setting the MEM2MEM bit of the DMA_CCRx register.

Programming transfer direction, assigning source/destination

The value of the DIR bit of the DMA_CCRx register sets the direction of the transfer, and consequently, it identifies the source and the destination, regardless the source/destination type (peripheral or memory):

• DIR = 1 defines typically a memory-to-peripheral transfer. More generally, if DIR = 1:

– The source attributes are defined by the DMA_MARx register, the MSIZE[1:0] field and MINC bit of the DMA_CCRx register.

Regardless of their usual naming, these ‘memory’ register, field and bit are used to define the source peripheral in peripheral-to-peripheral mode.

– The destination attributes are defined by the DMA_PARx register, the PSIZE[1:0] field and PINC bit of the DMA_CCRx register.

Regardless of their usual naming, these ‘peripheral’ register, field and bit are used to define the destination memory in memory-to-memory mode.

• DIR = 0 defines typically a peripheral-to-memory transfer. More generally, if DIR = 0:

– The source attributes are defined by the DMA_PARx register, the PSIZE[1:0] field and PINC bit of the DMA_CCRx register.

Regardless of their usual naming, these ‘peripheral’ register, field and bit are used to define the source memory in memory-to-memory mode

– The destination attributes are defined by the DMA_MARx register, the

MSIZE[1:0] field and MINC bit of the DMA_CCRx register.

Regardless of their usual naming, these ‘memory’ register, field and bit are used to define the destination peripheral in peripheral-to-peripheral mode.

When PSIZE[1:0] and MSIZE[1:0] are not equal, the DMA controller performs some data alignments as described in the table below.

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Table 46. Programmable data width and endian behavior (when PINC = MINC = 1)

Source port width

(MSIZE if

DIR = 1, else

PSIZE)

Destinat ion port width

(PSIZE if

DIR = 1, else

MSIZE)

Number of data items to transfer

(NDT)

Source content: address / data

(DMA_CMARx if

DIR = 1, else

DMA_CPARx)

DMA transfers

Destination content: address / data

(DMA_CPARx if

DIR = 1, else

DMA_CMARx)

@0x0 / B0

@0x1 / B1

@0x2 / B2

@0x3 / B3

@0x0 / B0

@0x1 / B1

@0x2 / B2

@0x3 / B3

@0x0 / B0

@0x1 / B1

@0x2 / B2

@0x3 / B3

@0x0 / B1B0

@0x2 / B3B2

@0x4 / B5B4

@0x6 / B7B6

@0x0 / B1B0

@0x2 / B3B2

@0x4 / B5B4

@0x6 / B7B6

@0x0 / B1B0

@0x2 / B3B2

@0x4 / B5B4

@0x6 / B7B6

@0x0 / B3B2B1B0

@0x4 / B7B6B5B4

@0x8 / BBBAB9B8

@0xC / BFBEBDBC

1: read B0[7:0] @0x0 then write B0[7:0] @0x0

2: read B1[7:0] @0x1 then write B1[7:0] @0x1

3: read B2[7:0] @0x2 then write B2[7:0] @0x2

4: read B3[7:0] @0x3 then write B3[7:0] @0x3

1: read B0[7:0] @0x0 then write 00B0[15:0] @0x0

2: read B1[7:0] @0x1 then write 00B1[15:0] @0x2

3: read B2[7:0] @0x2 then write 00B2[15:0] @0x4

4: read B3[7:0] @0x3 then write 00B3[15:0] @0x6

1: read B0[7:0] @0x0 then write 000000B0[31:0] @0x0

2: read B1[7:0] @0x1 then write 000000B1[31:0] @0x4

3: read B2[7:0] @0x2 then write 000000B2[31:0] @0x8

4: read B3[7:0] @0x3 then write 000000B3[31:0] @0xC

1: read B1B0[15:0] @0x0 then write B0[7:0] @0x0

2: read B3B2[15:0] @0x2 then write B2[7:0] @0x1

3: read B5B4[15:0] @0x4 then write B4[7:0] @0x2

4: read B7B6[15:0] @0x6 then write B6[7:0] @0x3

1: read B1B0[15:0] @0x0 then write B1B0[15:0] @0x0

2: read B3B2[15:0] @0x2 then write B3B2[15:0] @0x2

3: read B5B4[15:0] @0x4 then write B5B4[15:0] @0x4

4: read B7B6[15:0] @0x6 then write B7B6[15:0] @0x6

1: read B1B0[15:0] @0x0 then write 0000B1B0[31:0] @0x0

2: read B3B2[15:0] @0x2 then write 0000B3B2[31:0] @0x4

3: read B5B4[15:0] @0x4 then write 0000B5B4[31:0] @0x8

4: read B7B6[15:0] @0x6 then write 0000B7B6[31:0] @0xC

1: read B3B2B1B0[31:0] @0x0 then write B0[7:0] @0x0

2: read B7B6B5B4[31:0] @0x4 then write B4[7:0] @0x1

3: read BBBAB9B8[31:0] @0x8 then write B8[7:0] @0x2

4: read BFBEBDBC[31:0] @0xC then write BC[7:0] @0x3

@0x0 / B0

@0x1 / B1

@0x2 / B2

@0x3 / B3

@0x0 / 00B0

@0x2 / 00B1

@0x4 / 00B2

@0x6 / 00B3

@0x0 / 000000B0

@0x4 / 000000B1

@0x8 / 000000B2

@0xC / 000000B3

@0x0 / B0

@0x1 / B2

@0x2 / B4

@0x3 / B6

@0x0 / B1B0

@0x2 / B3B2

@0x4 / B5B4

@0x6 / B7B6

@0x0 / 0000B1B0

@0x4 / 0000B3B2

@0x8 / 0000B5B4

@0xC / 0000B7B6

@0x0 / B0

@0x1 / B4

@0x2 / B8

@0x3 / BC

@0x0 / B3B2B1B0

@0x4 / B7B6B5B4

@0x8 / BBBAB9B8

@0xC / BFBEBDBC

1: read B3B2B1B0[31:0] @0x0 then write B1B0[15:0] @0x0

2: read B7B6B5B4[31:0] @0x4 then write B5B4[15:0] @0x2

3: read BBBAB9B8[31:0] @0x8 then write B9B8[15:0] @0x4

4: read BFBEBDBC[31:0] @0xC then write BDBC[15:0] @0x6

@0x0 / B1B0

@0x2 / B5B4

@0x4 / B9B8

@0x6 / BDBC

@0x0 / B3B2B1B0

@0x4 / B7B6B5B4

@0x8 / BBBAB9B8

@0xC / BFBEBDBC

1: read B3B2B1B0[31:0] @0x0 then write B3B2B1B0[31:0] @0x0

2: read B7B6B5B4[31:0] @0x4 then write B7B6B5B4[31:0] @0x4

3: read BBBAB9B8[31:0] @0x8 then write BBBAB9B8[31:0] @0x8

4: read BFBEBDBC[31:0] @0xC then write BFBEBDBC[31:0] @0xC

@0x0 / B3B2B1B0

@0x4 / B7B6B5B4

@0x8 / BBBAB9B8

@0xC / BFBEBDBC

Addressing AHB peripherals not supporting byte/half-word write transfers

When the DMA controller initiates an AHB byte or half-word write transfer, the data are duplicated on the unused lanes of the AHB master 32-bit data bus (HWDATA[31:0]).

When the AHB slave peripheral does not support byte or half-word write transfers and does not generate any error, the DMA controller writes the 32 HWDATA bits as shown in the two examples below:

• To write the half-word 0xABCD, the DMA controller sets the HWDATA bus to

0xABCDABCD with a half-word data size (HSIZE = HalfWord in AHB master bus).

• To write the byte 0xAB, the DMA controller sets the HWDATA bus to 0xABABABAB with a byte data size (HSIZE = Byte in the AHB master bus).

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Assuming the AHB/APB bridge is an AHB 32-bit slave peripheral that does not take into account the HSIZE data, any AHB byte or half-word transfer is changed into a 32-bit APB transfer as described below:

• An AHB byte write transfer of 0xB0 to one of the 0x0, 0x1, 0x2 or 0x3 addresses, is converted to an APB word write transfer of 0xB0B0B0B0 to the 0x0 address.

• An AHB half-word write transfer of 0xB1B0 to the 0x0 or 0x2 addresses, is converted to an APB word write transfer of 0xB1B0B1B0 to the 0x0 address.

10.4.6 DMA error management

A DMA transfer error is generated when reading from or writing to a reserved address space. When a DMA transfer error occurs during a DMA read or write access, the faulty channel x is automatically disabled through a hardware clear of its EN bit in the corresponding DMA_CCRx register.

The TEIFx bit of the DMA_ISR register is set. An interrupt is then generated if the TEIE bit of the DMA_CCRx register is set.

The EN bit of the DMA_CCRx register can not be set again by software (channel x reactivated) until the TEIFx bit of the DMA_ISR register is cleared (by setting the CTEIFx bit of the DMA_IFCR register).

When the software is notified with a transfer error over a channel which involves a peripheral, the software has first to stop this peripheral in DMA mode, in order to disable any pending or future DMA request. Then software may normally reconfigure both DMA and the peripheral in DMA mode for a new transfer.

An interrupt can be generated on a half transfer, transfer complete or transfer error for each

DMA channel x. Separate interrupt enable bits are available for flexibility.

Interrupt request

Table 47. DMA interrupt requests

Interrupt event Event flag

Channel x interrupt

Half transfer on channel x

Transfer complete on channel x

Transfer error on channel x

Half transfer or transfer complete or transfer error on channel x

HTIFx

TCIFx

TEIFx

GIFx

Interrupt enable bit

HTIEx

TCIEx

TEIEx

Refer to Section 1.2

for a list of abbreviations used in register descriptions.

The DMA registers have to be accessed by words (32-bit).

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10.6.1 DMA interrupt status register (DMA_ISR)

Address offset: 0x00

Reset value: 0x0000 0000

The content of this register is linked to the DMA channels availability. See

Section 10.3:

DMA implementation for more details.

Every status bit is cleared by hardware when the software sets the corresponding clear bit or the corresponding global clear bit CGIFx, in the DMA_IFCR register.

Res.

28 27 26 25

Res.

TEIF7 HTIF7 TCIF7

12 r

11 r

10 r

9 15 14 13

TEIF4 HTIF4 TCIF4 GIF4 TEIF3 HTIF3 TCIF3 r r r r r r r

GIF7 r

GIF3 r

23 22 21

TEIF6 HTIF6 TCIF6 r

7 r

6 r

TEIF2 HTIF2 TCIF2 r r r

GIF6 r

GIF2 r

19 18 17

TEIF5 HTIF5 TCIF5 r

3 r

2 r

TEIF1 HTIF1 TCIF1 r r r

GIF5 r

GIF1 r

Bits 31:28 Reserved, must be kept at reset value.

Bit 27 TEIF7 : transfer error (TE) flag for channel 7

0: no TE event

1: a TE event occurred

Bit 26 HTIF7 : half transfer (HT) flag for channel 7

0: no HT event

1: a HT event occurred

Bit 25 TCIF7 : transfer complete (TC) flag for channel 7

0: no TC event

1: a TC event occurred

Bit 24 GIF7 : global interrupt flag for channel 7

0: no TE, HT or TC event

1: a TE, HT or TC event occurred

Bit 23 TEIF6 : transfer error (TE) flag for channel 6

0: no TE event

1: a TE event occurred

Bit 22 HTIF6 : half transfer (HT) flag for channel 6

0: no HT event

1: a HT event occurred

Bit 21 TCIF6 : transfer complete (TC) flag for channel 6

0: no TC event

1: a TC event occurred

Bit 20 GIF6 : global interrupt flag for channel 6

0: no TE, HT or TC event

1: a TE, HT or TC event occurred

Bit 19 TEIF5 : transfer error (TE) flag for channel 5

0: no TE event

1: a TE event occurred

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Bit 18 HTIF5 : half transfer (HT) flag for channel 5

0: no HT event

1: a HT event occurred

Bit 17 TCIF5 : transfer complete (TC) flag for channel 5

0: no TC event

1: a TC event occurred

Bit 16 GIF5 : global interrupt flag for channel 5

0: no TE, HT or TC event

1: a TE, HT or TC event occurred

Bit 15 TEIF4 : transfer error (TE) flag for channel 4

0: no TE event

1: a TE event occurred

Bit 14 HTIF4 : half transfer (HT) flag for channel 4

0: no HT event

1: a HT event occurred

Bit 13 TCIF4 : transfer complete (TC) flag for channel 4

0: no TC event

1: a TC event occurred

Bit 12 GIF4 : global interrupt flag for channel 4

0: no TE, HT or TC event

1: a TE, HT or TC event occurred

Bit 11 TEIF3 : transfer error (TE) flag for channel 3

0: no TE event

1: a TE event occurred

Bit 10 HTIF3 : half transfer (HT) flag for channel 3

0: no HT event

1: a HT event occurred

Bit 9 TCIF3 : transfer complete (TC) flag for channel 3

0: no TC event

1: a TC event occurred

Bit 8 GIF3 : global interrupt flag for channel 3

0: no TE, HT or TC event

1: a TE, HT or TC event occurred

Bit 7 TEIF2 : transfer error (TE) flag for channel 2

0: no TE event

1: a TE event occurred

Bit 6 HTIF2 : half transfer (HT) flag for channel 2

0: no HT event

1: a HT event occurred

Bit 5 TCIF2 : transfer complete (TC) flag for channel 2

0: no TC event

1: a TC event occurred

Bit 4 GIF2 : global interrupt flag for channel 2

0: no TE, HT or TC event

1: a TE, HT or TC event occurred

RM0451 Rev 3

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RM0451 Direct memory access controller (DMA)

Bit 3 TEIF1 : transfer error (TE) flag for channel 1

0: no TE event

1: a TE event occurred

Bit 2 HTIF1 : half transfer (HT) flag for channel 1

0: no HT event

1: a HT event occurred

Bit 1 TCIF1 : transfer complete (TC) flag for channel 1

0: no TC event

1: a TC event occurred

Bit 0 GIF1 : global interrupt flag for channel 1

0: no TE, HT or TC event

1: a TE, HT or TC event occurred

10.6.2 DMA interrupt flag clear register (DMA_IFCR)

Address offset: 0x04

Reset value: 0x0000 0000

The content of this register is linked to the DMA channels availability. See

Section 10.3:

DMA implementation for more details.

Setting the global clear bit CGIFx of the channel x in this DMA_IFCR register, causes the

DMA hardware to clear the corresponding GIFx bit and any individual flag among TEIFx,

HTIFx, TCIFx, in the DMA_ISR register.

Setting any individual clear bit among CTEIFx, CHTIFx, CTCIFx in this DMA_IFCR register, causes the DMA hardware to clear the corresponding individual flag and the global flag

GIFx in the DMA_ISR register, provided that none of the two other individual flags is set.

Writing 0 into any flag clear bit has no effect.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res.

15 14 13 12 w

11 w

10 w

9 w

8 w

7 w

6 w

5 w

4 w

3 w

2 w

1 w

0 w w w w w w w w w w

Bits 31:28 Reserved, must be kept at reset value.

Bit 27 CTEIF7 : transfer error flag clear for channel 7

Bit 26 CHTIF7 : half transfer flag clear for channel 7

Bit 25 CTCIF7 : transfer complete flag clear for channel 7

Bit 24 CGIF7 : global interrupt flag clear for channel 7

Bit 23 CTEIF6 : transfer error flag clear for channel 6

Bit 22 CHTIF6 : half transfer flag clear for channel 6 w w w w w w

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Bit 21 CTCIF6 : transfer complete flag clear for channel 6

Bit 20 CGIF6 : global interrupt flag clear for channel 6

Bit 19 CTEIF5 : transfer error flag clear for channel 5

Bit 18 CHTIF5 : half transfer flag clear for channel 5

Bit 17 CTCIF5 : transfer complete flag clear for channel 5

Bit 16 CGIF5 : global interrupt flag clear for channel 5

Bit 15 CTEIF4 : transfer error flag clear for channel 4

Bit 14 CHTIF4 : half transfer flag clear for channel 4

Bit 13 CTCIF4 : transfer complete flag clear for channel 4

Bit 12 CGIF4 : global interrupt flag clear for channel 4

Bit 11 CTEIF3 : transfer error flag clear for channel 3

Bit 10 CHTIF3 : half transfer flag clear for channel 3

Bit 9 CTCIF3 : transfer complete flag clear for channel 3

Bit 8 CGIF3 : global interrupt flag clear for channel 3

Bit 7 CTEIF2 : transfer error flag clear for channel 2

Bit 6 CHTIF2 : half transfer flag clear for channel 2

Bit 5 CTCIF2 : transfer complete flag clear for channel 2

Bit 4 CGIF2 : global interrupt flag clear for channel 2

Bit 3 CTEIF1 : transfer error flag clear for channel 1

Bit 2 CHTIF1 : half transfer flag clear for channel 1

Bit 1 CTCIF1 : transfer complete flag clear for channel 1

Bit 0 CGIF1 : global interrupt flag clear for channel 1

10.6.3 DMA channel x configuration register (DMA_CCRx)

Address offset: 0x08 + 0x14 * (x - 1), (x = 1 to 7)

Reset value: 0x0000 0000

The address offsets of these registers are linked to the DMA channels availability. See

Section 10.3: DMA implementation

for more details.

The register fields/bits MEM2MEM, PL[1:0], MSIZE[1:0], PSIZE[1:0], MINC, PINC, and DIR are read-only when EN = 1.

The states of MEM2MEM and CIRC bits must not be both high at the same time.

Res.

MEM2

MEM rw

13 12 rw

PL[1:0] rw

11 10

MSIZE[1:0] rw rw

9 8

PSIZE[1:0] rw rw

MINC rw

PINC rw

CIRC rw

DIR rw

TEIE rw

HTIE rw

TCIE rw

EN rw

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Bits 31:15 Reserved, must be kept at reset value.

Bit 14 MEM2MEM : memory-to-memory mode

0: disabled

1: enabled

Note: this bit is set and cleared by software.

It must not be written when the channel is enabled (EN = 1).

It is read-only when the channel is enabled (EN = 1).

Bits 13:12 PL[1:0] : priority level

00: low

01: medium

10: high

11: very high

Note: this field is set and cleared by software.

It must not be written when the channel is enabled (EN = 1).

It is read-only when the channel is enabled (EN = 1).

Bits 11:10 MSIZE[1:0] : memory size

Defines the data size of each DMA transfer to the identified memory.

In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0.

In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0.

00: 8 bits

01: 16 bits

10: 32 bits

11: reserved

Note: this field is set and cleared by software.

It must not be written when the channel is enabled (EN = 1).

It is read-only when the channel is enabled (EN = 1).

Bits 9:8 PSIZE[1:0] : peripheral size

Defines the data size of each DMA transfer to the identified peripheral.

In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0.

In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0.

00: 8 bits

01: 16 bits

10: 32 bits

11: reserved

Note: this field is set and cleared by software.

It must not be written when the channel is enabled (EN = 1).

It is read-only when the channel is enabled (EN = 1).

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Bit 7 MINC : memory increment mode

Defines the increment mode for each DMA transfer to the identified memory.

In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0.

In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0.

0: disabled

1: enabled

Note: this bit is set and cleared by software.

It must not be written when the channel is enabled (EN = 1).

It is read-only when the channel is enabled (EN = 1).

Bit 6 PINC : peripheral increment mode

Defines the increment mode for each DMA transfer to the identified peripheral.

n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0.

In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0.

0: disabled

1: enabled

Note: this bit is set and cleared by software.

It must not be written when the channel is enabled (EN = 1).

It is read-only when the channel is enabled (EN = 1).

Bit 5 CIRC : circular mode

0: disabled

1: enabled

Note: this bit is set and cleared by software.

It must not be written when the channel is enabled (EN = 1).

It is not read-only when the channel is enabled (EN = 1).

Bit 4 DIR : data transfer direction

This bit must be set only in memory-to-peripheral and peripheral-to-memory modes.

0: read from peripheral

– Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register.

This is still valid in a memory-to-memory mode.

– Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode.

1: read from memory

– Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode.

– Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register.

This is still valid in a peripheral-to-peripheral mode.

Note: this bit is set and cleared by software.

It must not be written when the channel is enabled (EN = 1).

It is read-only when the channel is enabled (EN = 1).

Bit 3 TEIE : transfer error interrupt enable

0: disabled

1: enabled

Note: this bit is set and cleared by software.

It must not be written when the channel is enabled (EN = 1).

It is not read-only when the channel is enabled (EN = 1).

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Bit 2 HTIE : half transfer interrupt enable

0: disabled

1: enabled

Note: this bit is set and cleared by software.

It must not be written when the channel is enabled (EN = 1).

It is not read-only when the channel is enabled (EN = 1).

Bit 1 TCIE : transfer complete interrupt enable

0: disabled

1: enabled

Note: this bit is set and cleared by software.

It must not be written when the channel is enabled (EN = 1).

It is not read-only when the channel is enabled (EN = 1).

Bit 0 EN : channel enable

When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by setting the CTEIFx bit of the DMA_IFCR register).

0: disabled

1: enabled

Note: this bit is set and cleared by software.

10.6.4 DMA channel x number of data to transfer register (DMA_CNDTRx)

Address offset: 0x0C + 0x14 * (x - 1), (x = 1 to 7)

Reset value: 0x0000 0000

The address offsets of these registers are linked to the DMA channels availability. See

Section 10.3: DMA implementation

for more details.

Res.

15 rw

14 rw

13 rw

12 rw

11 rw

10 rw

9 rw

8 7

NDT[15:0] rw rw

6 rw

5 rw

4 rw

3 rw

2 rw

1 rw

0 rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 NDT[15:0] : number of data to transfer (0 to 2

- 1)

This field is updated by hardware when the channel is enabled:

– It is decremented after each single DMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer.

– It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the DMA_CCRx register).

– It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1).

If this field is zero, no transfer can be served whatever the channel status (enabled or not).

Note: this field is set and cleared by software.

It must not be written when the channel is enabled (EN = 1).

It is read-only when the channel is enabled (EN = 1).

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10.6.5 DMA channel x peripheral address register (DMA_CPARx)

Address offset: 0x10 + 0x14 * (x - 1), (x = 1 to 7)

Reset value: 0x0000 0000

The address offsets of these registers are linked to the DMA channels availability. See

Section 10.3: DMA implementation

for more details.

31 rw

15 rw

30 29 rw

14 rw

28 rw

27 rw

26 rw

25 rw

24 23

PA[31:16] rw

8 rw

7 rw

PA[15:0] rw

22 rw

21 rw

20 rw

19 rw

18 rw

17 rw

16 rw

0 rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 PA[31:0] : peripheral address

It contains the base address of the peripheral data register from/to which the data will be read/written.

When PSIZE[1:0] = 01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address.

When PSIZE = 10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address.

In memory-to-memory mode, this register identifies the memory destination address if

DIR = 1 and the memory source address if DIR = 0.

In peripheral-to-peripheral mode, this register identifies the peripheral destination address

DIR = 1 and the peripheral source address if DIR = 0.

Note: this register is set and cleared by software.

It must not be written when the channel is enabled (EN = 1).

It is not read-only when the channel is enabled (EN = 1).

10.6.6 DMA channel x memory address register (DMA_CMARx)

Address offset: 0x14 + 0x14 * (x - 1), (x = 1 to 7)

Reset value: 0x0000 0000

The address offsets of these registers are linked to the DMA channels availability. See

Section 10.3: DMA implementation

for more details.

31 30 29 28 27 26 25 22 21 20 19 18 17 rw

15 rw rw

14 rw rw

13 rw rw

12 rw rw

11 rw rw

10 rw rw

9 rw

24 23 rw

MA[31:16] rw

8 7

MA[15:0] rw rw rw

6 rw rw

5 rw rw

4 rw rw

3 rw rw

2 rw rw

1 rw

16 rw

0 rw

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RM0451 Direct memory access controller (DMA)

Bits 31:0 MA[31:0] : peripheral address

It contains the base address of the memory from/to which the data will be read/written.

When MSIZE[1:0] = 01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address.

When MSIZE = 10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address.

In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0.

In peripheral-to-peripheral mode, this register identifies the peripheral source address

DIR = 1 and the peripheral destination address if DIR = 0.

Note: this register is set and cleared by software.

It must not be written when the channel is enabled (EN = 1).

It is not read-only when the channel is enabled (EN = 1).

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10.6.7 DMA channel selection register (DMA_CSELR)

Address offset: 0xA8

Reset value: 0x0000 0000

This register is used to manage the mapping of DMA channels as detailed in Section 10.3.2:

DMA request mapping .

Res.

15 rw

Res.

14 13

C4S[3:0] rw rw

Res.

12 rw

27 rw

11 rw

26 25

C7S[3:0] rw

10 rw

C3S[3:0] rw rw

24 rw

8 rw

23 rw

7 rw

22 21

C6S[3:0] rw

6 rw

C2S[3:0] rw rw

Bits 31:28 Reserved, must be kept at reset value.

Bits 27:24 C7S[3:0] : DMA channel 7 selection

Details available in

Section 10.3.2: DMA request mapping

Bits 23:20 C6S[3:0] : DMA channel 6 selection

Details available in

Section 10.3.2: DMA request mapping

Bits 19:16 C5S[3:0] : DMA channel 5 selection

Details available in

Section 10.3.2: DMA request mapping

Bits 15:12 C4S[3:0] : DMA channel 4 selection

Details available in

Section 10.3.2: DMA request mapping

Bits 11:8 C3S[3:0] : DMA channel 3 selection

Details available in

Section 10.3.2: DMA request mapping

Bits 7:4 C2S[3:0] : DMA channel 2 selection

Details available in

Section 10.3.2: DMA request mapping

Bits 3:0 C1S[3:0] : DMA channel 1 selection

Details available in

Section 10.3.2: DMA request mapping

20 rw

4 rw

19 rw

3 rw

18 17

C5S[3:0] rw

2 rw

C1S[3:0] rw rw

16 rw

0 rw

Offset

0x000

0x004

0x008

The table below gives the DMA register map and reset values.

Table 48. DMA register map and reset values

Register

DMA_ISR

Reset value

DMA_IFCR

Reset value

DMA_CCR1

Reset value

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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Offset

0x00C

0x010

0x014

0x018

Table 48. DMA register map and reset values (continued)

Register

DMA_CNDTR1

Reset value

DMA_CPAR1

Reset value

DMA_CMAR1

Reset value

Reserved

NDTR[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PA[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MA[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Reserved.

DMA_CCR2

0x01C

0x020

0x024

0x028

0x02C

Reset value

DMA_CNDTR2

Reset value

DMA_CPAR2

Reset value

DMA_CMAR2

Reset value

Reserved

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NDTR[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PA[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MA[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Reserved.

0x030

DMA_CCR3

0x034

0x038

0x03C

0x040

Reset value

DMA_CNDTR3

Reset value

DMA_CPAR3

Reset value

DMA_CMAR3

Reset value

Reserved

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NDTR[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PA[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MA[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Reserved.

0x044

DMA_CCR4

0x048

0x04C

0x050

0x054

Reset value

DMA_CNDTR4

Reset value

DMA_CPAR4

Reset value

DMA_CMAR4

Reset value

Reserved

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NDTR[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PA[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MA[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Reserved.

0x058

DMA_CCR5

0x05C

0x060

Reset value

DMA_CNDTR5

Reset value

DMA_CPAR5

Reset value

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NDTR[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PA[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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Direct memory access controller (DMA) RM0451

Offset

0x064

0x068

Table 48. DMA register map and reset values (continued)

Register

DMA_CMAR5

Reset value

Reserved

MA[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Reserved.

0x06C

DMA_CCR6

0x070

0x074

0x078

0x07C

Reset value

DMA_CNDTR6

Reset value

DMA_CPAR6

Reset value

DMA_CMAR6

Reset value

Reserved

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NDTR[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PA[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MA[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Reserved.

0x080

DMA_CCR7

0x084

0x088

0x08C

0x090 to

0x0A4

0x0A8

Reset value

DMA_CNDTR7

Reset value

DMA_CPAR7

Reset value

DMA_CMAR7

Reset value

Reserved

DMA_CSELR

Reset value

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NDTR[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PA[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MA[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Reserved.

C7S[3:0] C6S[3:0] C5S[3:0] C4S[3:0] C3S[3:0] C2S[3:0] C1S[3:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Refer to Section 2.2

for the register boundary addresses.

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11

Nested vectored interrupt controller (NVIC)

Nested vectored interrupt controller (NVIC)

• Up to 39 maskable interrupt channels (see

Table 49 ), These do not include the 16

interrupt lines of Cortex

-M0+.

• 4 programmable priority levels (2 bits of interrupt priority are used)

• Low-latency exception and interrupt handling

• Power management control

• Implementation of system control registers

The NVIC and the processor core interface are closely coupled, which enables low-latency interrupt processing and efficient processing of late arriving interrupts.

All interrupts including the core exceptions are managed by the NVIC. For more information on exceptions and NVIC programming, refer to the STM32L0 Series Cortex

-M0+ programming manual (PM0223).

For code example, refer to

A.7.1: NVIC initialization example .

11.2 SysTick calibration value register

The SysTick calibration value is fixed to 4000, which gives a reference time base of 1 ms with the SysTick clock set to 4 MHz (max HCLK/8).

Table 49 is the vector table for STM32L010xx devices.

Position Priority

-3

-2

-1

Table 49. List of vectors

(1)(2)

Type of priority

fixed

Reset

Acronym fixed fixed settable SVC_Handler

NMI_Handler

HardFault_Handler settable PendSV_Handler settable SysTick_Handler

Description Address

Reserved

Reset

Non maskable interrupt. The RCC

Clock Security System (CSS) is linked to the NMI vector.

All class of fault

0x0000_0000

0x0000_0004

0x0000_0008

Reserved

0x0000_000C

0x0000_0010 -

0x0000_002B

System service call via SWI instruction

0x0000_002C

Reserved

0x0000_0030 -

0x0000_0037

Pendable request for system service 0x0000_0038

System tick timer 0x0000_003C

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Table 49. List of vectors (1)(2) (continued)

Position Priority

Type of priority

Acronym Description Address

36 settable settable TIM2 settable settable settable settable settable TIM21 settable settable TIM22 settable I2C1 settable settable SPI1 settable settable settable settable settable settable settable settable DMA1_Channel1

Reserved

DMA1 Channel1 global interrupt settable DMA1_Channel[3:2] DMA1 Channel2 and 3 interrupts settable DMA1_Channel[7:4] DMA1 Channel4 to 7 interrupts settable ADC ADC interrupt through EXTI21 settable LPTIM1 LPTIMER1 interrupt through EXTI29 settable settable

WWDG

RTC

FLASH settable RCC_CRS settable EXTI[1:0] settable EXTI[3:2] settable EXTI[15:4]

USART2

LPUART1

Window Watchdog interrupt

Reserved

RTC global interrupt through

EXTI17/19/20 line and LSE CSS interrupt through EXTI 19 line

Flash memory and data EEPROM global interrupt

RCC global interrupt

EXTI Line0 and 1 interrupts

EXTI Line2 and 3 interrupts

EXTI Line4 to 15 interrupts

0x0000_0040

0x0000_0044

0x0000_0048

0x0000_004C

Reserved

TIMER2 global interrupt

Reserved

Reserved reserved

TIMER21 global interrupt

Reserved

TIMER22 global interrupt

0x0000_0090

0x0000_0094

0x0000_0098

I2C1 global interrupt through EXTI23 0x0000_009C

Reserved 0x0000_00A0

SPI1 global interrupt 0x0000_00A4

Reserved

USART2 global interrupt through

EXTI26

LPUART1 global interrupt through

EXTI28

0x0000_00A8

0x0000_00AC

0x0000_00B0

0x0000_00B4

0x0000_0050

0x0000_0054

0x0000_0058

0x0000_005C

0x0000_0060

0x0000_0064

0x0000_0068

0x0000_006C

0x0000_0070

0x0000_0074

0x0000_0078

0x0000_007C

0x0000_0080

0x0000_0084

0x0000_0088

0x0000_008C

1. The grayed cells correspond to the Cortex ® -M0+ interrupts.

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2. Refer to

Table 1: STM32L010 memory density

, to

Table 2: Overview of features per category and to the device datasheets

for the GPIO ports and peripherals available on your device. The memory area corresponding to unavailable GPIO ports or peripherals are reserved.

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Extended interrupt and event controller (EXTI)

12 Extended interrupt and event controller (EXTI)

RM0451

12.1 Introduction

The extended interrupts and events controller (EXTI) manages the external and internal asynchronous events/interrupts and generates the event request to the CPU/interrupt controller plus a wake-up request to the power controller.

The EXTI allows the management of up to 30 event lines which can wake up the device from Stop mode.

Some of the lines are configurable: in this case the active edge can be chosen independently, and a status flag indicates the source of the interrupt. The configurable lines are used by the I/Os external interrupts, and by few peripherals. Some of the lines are direct: they are used by some peripherals to generate a wakeup from Stop event or interrupt. In this case the status flag is provided by the peripheral.

Each line can be masked independently for interrupt or event generation.

Te EXTI controller also allows to emulate, by programming to a dedicated register, events or interrupts by software multiplexed with the corresponding hardware event line.

12.2 EXTI main features

The EXTI main features are the following:

• Generation of up to 30 event/interrupt requests (configurable and direct lines).

• Independent mask on each event/interrupt line

• Configurable rising or falling edge (configurable lines only)

• Dedicated status bit (configurable lines only)

• Emulation of event/interrupt requests (configurable lines only)

12.3 EXTI functional description

For the configurable interrupt lines, the interrupt line should be configured and enabled in order to generate an interrupt. This is done by programming the two trigger registers with the desired edge detection and by enabling the interrupt request by writing a ‘1’ to the corresponding bit in the interrupt mask register. When the selected edge occurs on the interrupt line, an interrupt request is generated. The pending bit corresponding to the interrupt line is also set. This request is cleared by writing a ‘1’ in the pending register.

For the direct interrupt lines: the interrupt is enabled by default in the interrupt mask register and there is no corresponding pending bit in the pending register.

To generate an event, the event line should be configured and enabled. This is done by programming the two trigger registers with the desired edge detection and by enabling the event request by writing a ‘1’ to the corresponding bit in the event mask register. When the selected edge occurs on the event line, an event pulse is generated. The pending bit corresponding to the event line is not set.

For the configurable lines, an interrupt/event request can also be generated by software by writing a ‘1’ in the software interrupt/event register.

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Note:

Extended interrupt and event controller (EXTI)

The interrupts or events associated to the direct lines are triggered only when the system is in Stop mode. If the system is still running, no interrupt/event is generated by the EXTI.

The block diagram is shown in

Figure 26

Figure 26. Extended interrupts and events controller (EXTI) block diagram

PCLK

APB bus

Peripheral interface

Falling trigger selection register

Rising trigger selection register

Software interrupt event register

Event mask register

Interrupt mask register

Pending request register

Interrupts

Configurable events

Edge detect circuit

Stop mode

Direct events

Rising edge detect.

Events

Wakeup

MSv32798V1

The STM32L010xx microcontrollers are able to handle external or internal events in order to wake up the core (WFE). The wakeup event can be generated by either:

• enabling an interrupt in the peripheral control register but not in the NVIC, and enabling the SEVONPEND bit in the Cortex ® -M0+ system control register (see STM32L0 Series

Cortex ® -M0+ programming manual (PM0223)). When the MCU resumes from WFE, the peripheral interrupt pending bit and the peripheral NVIC IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be cleared.

• or configuring an EXTI line in event mode. When the CPU resumes from WFE, it is not necessary to clear the peripheral interrupt pending bit or the NVIC IRQ channel pending bit as the pending bit corresponding to the event line is not set.

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Extended interrupt and event controller (EXTI) RM0451

Note:

Some peripherals can generate events when the system is in Run mode or in Stop mode, thus allowing to wake up the system from Stop mode.

To accomplish this, the peripheral generates both a synchronized (to the system clock, e.g.

APB clock) and an asynchronous version of the event. This asynchronous event is connected to an EXTI direct line.

Few peripherals with wakeup from Stop capability are connected to an EXTI configurable line. In this case the EXTI configuration is required to allow the wakeup from Stop mode.

To configure a line as an interrupt source, use the following procedure:

Configure the mask bits of the Interrupt lines (EXTI_IMR)

2. Configure the Trigger Selection bits of the Interrupt lines (EXTI_RTSR and

EXTI_FTSR)

3. Configure the enable and mask bits that control the NVIC IRQ channel mapped to the extended interrupt controller (EXTI) so that an interrupt coming from any one of the lines can be correctly acknowledged.

The direct lines do not require any EXTI configuration.

For code example, refer to

A.7.2: Extended interrupt selection code example .

To configure a line as an event source, use the following procedure:

Configure the mask bits of the Event lines (EXTI_EMR)

2. Configure the Trigger Selection bits of the Event lines (EXTI_RTSR and EXTI_FTSR).

12.3.6 Software interrupt/event selection

Any of the configurable lines can be configured as software interrupt/event lines. The procedure below must be followed to generate a software interrupt.

Configure the mask bits of the Interrupt/Event lines (EXTI_IMR, EXTI_EMR)

2. Set the required bit in the software interrupt register (EXTI_SWIER).

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In the STM32L010xx, 30 interrupt/event lines are available.The GPIOs are connected to 16 configurable interrupt/event lines as shown in

Figure 27

Figure 27. Extended interrupt/event GPIO mapping

EXTI0[3:0] bits in SYSCFG_EXTICR1 register

PA0

PB0

PC0

EXTI0

EXTI1[3:0] bits in SYSCFG_EXTICR1 register

PA1

PB1

PC1

EXTI1

EXTI2[3:0] bits in SYSCFG_EXTICR1 register

PA2

PB2

PC2

PD2

EXTI2

EXTI15[3:0] bits in SYSCFG_EXTICR4 register

PA15

PB15

PC15

EXTI15

Note: Refer to the datasheet for the list of available I/O ports.

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Extended interrupt and event controller (EXTI)

The 30 lines are connected as shown in Table 50: EXTI lines connections

EXTI line

0-15

Table 50. EXTI lines connections

Line source

GPIO

Reserved

RTC alarm

Reserved

RTC tamper or timestamp or

CSS_LSE

RTC wakeup timer

Reserved

I2C1 wakeup

Reserved

USART2 wakeup

Reserved

LPUART1 wakeup

LPTIM1 wakeup

Line type configurable configurable configurable configurable direct direct direct direct

RM0451

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Refer to Section 1.2

for a list of abbreviations used in register descriptions.

The peripheral registers have to be accessed by words (32-bit).

12.5.1 EXTI interrupt mask register (EXTI_IMR)

Address offset: 0x00

Reset value: 0x3F84 0000

Res.

IM15 rw

Res.

IM29 rw

IM14 IM13 rw rw

IM28 rw

IM12 rw

Res.

IM11 rw

IM26 rw

IM10 rw

IM25 rw

IM9 rw

IM24 rw

IM8 rw

IM23 rw

IM7 rw

Bits 31:30 Reserved, must be kept at reset value.

Bits 29:28 IMx: Interrupt mask on line x (x = 29 to 28)

0: Interrupt request from Line x is masked

1: Interrupt request from Line x is not masked

Bit 27 Reserved, must be kept at reset value.

Bits 26:19 IMx: Interrupt mask on line x (x = 26 to 19)

0: Interrupt request from Line x is masked

1: Interrupt request from Line x is not masked

Bit 18 Reserved, must be kept at reset value.

Bits 17:0 IMx: Interrupt mask on line x (x = 17 to 0)

0: Interrupt request from Line x is masked

1: Interrupt request from Line x is not masked

IM22 rw

IM6 rw

IM21 rw

IM5 rw

IM20 rw

IM4 rw

IM19 rw

IM3 rw

IM2 rw

Res.

IM17 rw

IM1 rw

IM16 rw

IM0 rw

Address offset: 0x04

Reset value: 0x0000 0000

Res.

30 29 28

Res.

EM29 EM28

14 rw

13 rw

27 25

Res.

EM26 EM25

26 rw

EM15 EM14 EM13 EM12 EM11 EM10 rw

EM9 rw rw rw rw rw rw rw

EM24 rw

EM8 rw

EM23 rw

EM7 rw

22 21 20 19

EM22 EM21 EM20 EM19 rw

6 rw

5 rw

4 rw

EM6 EM5 EM4 EM3 rw rw rw rw

Res.

EM2 rw

EM17 rw

EM1 rw

EM16 rw

EM0 rw

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Extended interrupt and event controller (EXTI) RM0451

Bits 31:30 Reserved, must be kept at reset value.

Bits 29:28 EMx: Event mask on line x (x = 29 to 28)

0: Event request from Line x is masked

1: Event request from Line x is not masked

Bit 27 Reserved, must be kept at reset value.

Bits 26:19 EMx: Event mask on line x (x = 26 to 19)

0: Event request from Line x is masked

1: Event request from Line x is not masked

Bit 18 Reserved, must be kept at reset value.

Bits 17:0 EMx: Event mask on line x (x = 17 to 0)

0: Event request from Line x is masked

1: Event request from Line x is not masked

12.5.3 EXTI rising edge trigger selection register (EXTI_RTSR)

Address offset: 0x08

Reset value: 0x0000 0000

Res.

Note:

Res.

15 14

RT15 RT14 rw rw

13 12

RT13 RT12 rw rw

11 10

RT11 RT10 rw rw

Res.

RT9 rw

Res.

RT8 rw

Res.

RT7 rw

RT22 rw

RT6 rw

21 20

RT21 RT20 rw

5 rw

RT5 rw

RT4 rw

RT19 rw

RT16

RT3 rw

Res.

RT2 rw

RT17 rw

RT1 rw

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:19 RTx: Rising trigger event configuration bit of line x (x = 22 to 19)

0: Rising trigger disabled (for Event and Interrupt) for input line x

1: Rising trigger enabled (for Event and Interrupt) for input line x

Bit 18 Reserved, must be kept at reset value.

Bits 17:0 RTx: Rising trigger event configuration bit of line x (x = 17 to 0)

0: Rising trigger disabled (for Event and Interrupt) for input line x

1: Rising trigger enabled (for Event and Interrupt) for input line x

The configurable wakeup lines are edge triggered, no glitch must be generated on these lines.

If a rising edge on the configurable interrupt line occurs while writing to the EXTI_RTSR register, the pending bit will not be set.

Rising and falling edge triggers can be set for the same interrupt line. In this configuration, both generate a trigger condition.

RT16 rw

RT0 rw

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12.5.4 Falling edge trigger selection register (EXTI_FTSR)

Address offset: 0x0C

Reset value: 0x0000 0000

Res.

FT15 rw

Note:

Res.

FT14 rw

FT13 rw

Res.

FT12 rw

Res.

FT11 rw

FT10 rw

Res.

FT9 rw

Res.

FT8 rw

Res.

FT7 rw

FT22 rw

FT6 rw

FT21 rw

FT5 rw

FT20 rw

FT4 rw

FT19 rw

FT3 rw

Res.

FT2 rw

FT17 rw

FT1 rw

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:19 FTx: Falling trigger event configuration bit of line x (x = 22 to 19)

0: Falling trigger disabled (for Event and Interrupt) for input line x

1: Falling trigger enabled (for Event and Interrupt) for input line x

Bit 18 Reserved, must be kept at reset value.

Bits 17:0 FTx: Falling trigger event configuration bit of line x (x = 17 to 0)

0: Falling trigger disabled (for Event and Interrupt) for input line x

1: Falling trigger enabled (for Event and Interrupt) for input line x

The configurable wakeup lines are edge triggered, no glitch must be generated on these lines.

If a falling edge on the configurable interrupt line occurs while writing to the EXTI_FTSR register, the pending bit will not be set.

Rising and falling edge triggers can be set for the same interrupt line. In this configuration, both generate a trigger condition.

FT16 rw

FT0 rw

Res.

Address offset: 0x10

Reset value: 0x0000 0000

Res.

15 14 13 12 11 10 9

SWI15 SWI14 SWI13 SWI12 SWI11 SWI10 SWI9 rw rw rw rw rw rw rw

Res.

SWI8 rw

23 22 21 20 19 18 17 16

Res.

SWI22 SWI21 SWI20 SWI19 Res.

SWI17 SWI16

7 rw

6 rw

5 rw

4 rw

3 2 rw

1 rw

SWI7 SWI6 SWI5 SWI4 SWI3 SWI2 rw rw rw rw rw rw

SWI1 rw

SWI0 rw

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Bits 31:23 Reserved, must be kept at reset value.

Bits 22:19 SWIx: Software interrupt on line x (x = 22 to 19)

Writing a 1 to this bit when it is at 0 sets the corresponding pending bit in EXTI_PR. If the interrupt is enabled on this line in EXTI_IMR and EXTI_EMR, an interrupt request is generated.

This bit is cleared by clearing the corresponding bit in EXTI_PR (by writing a 1 to this bit).

Bit 18 Reserved, must be kept at reset value.

Bits 17:0 SWIx: Software interrupt on line x (x = 17 to 0)

Writing a 1 to this bit when it is at 0 sets the corresponding pending bit in EXTI_PR. If the interrupt is enabled on this line in EXTI_IMR and EXTI_EMR, an interrupt request is generated.

This bit is cleared by clearing the corresponding bit in EXTI_PR (by writing a 1 to this bit).

12.5.6 EXTI pending register (EXTI_PR)

Address offset: 0x14

Reset value: 0x0000 0000

Res.

23 22 21 20 19

Res.

PIF22 PIF21 PIF20 PIF19

7 rc_w1 rc_w1 rc_w1 rc_w1

6 5 4 3

Res.

17 16

PIF17 PIF16 rc_w1 rc_w1

1 0

PIF15 PIF14 PIF13 PIF12 PIF11 PIF10 PIF9 PIF8 PIF7 PIF6 PIF5 PIF4 PIF3 PIF2 PIF1 PIF0 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:19 PIFx: Pending interrupt flag on line x (x = 22 to 19)

0: No trigger request occurred

1: The selected trigger request occurred

This bit is set when the selected edge event arrives on the interrupt line. This bit is cleared by writing it to 1 or by changing the sensitivity of the edge detector.

Bit 18 Reserved, must be kept at reset value.

Bits 17:0 PIFx: Pending interrupt flag on line x (x = 17 to 0)

0: No trigger request occurred

1: The selected trigger request occurred

This bit is set when the selected edge event arrives on the interrupt line. This bit is cleared by writing it to 1 or by changing the sensitivity of the edge detector.

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12.5.7 EXTI register map

The following table gives the EXTI register map and the reset values.

Table 51. Extended interrupt/event controller register map and reset values

Offset Register

0x00

EXTI_IMR

Reset value

0x04

EXTI_EMR

0x08

0x0C

0x10

0x14

Reset value

EXTI_RTSR

Reset value

EXTI_FTSR

Reset value

EXTI_SWIER

Reset value

EXTI_PR

Reset value

1 1

IM[26:19]

1 1 1 1 0 0 0 0

IM[17:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EM[26:19] EM[17:0]

0 0 0 0 0 0 0 0 0 0 0

RT[22:19]

0 0 0 0

FT[22:19]

0 0 0 0

SWI

[22:19]

0 0 0 0

PIF

[22:19]

0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RT[17:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FT[17:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SWI[17:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PIF[17:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Refer to Section 2.2 on page 39 for the register boundary addresses.

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13 Analog-to-digital converter (ADC)

RM0451

13.1 Introduction

The 12-bit ADC is a successive approximation analog-to-digital converter. It has up to 17 multiplexed channels allowing it to measure signals from 16 external and 1 internal sources.

A/D conversion of the various channels can be performed in single, continuous, scan or discontinuous mode. The result of the ADC is stored in a left-aligned or right-aligned 16-bit data register.

The analog watchdog feature allows the application to detect if the input voltage goes outside the user-defined higher or lower thresholds.

An efficient low-power mode is implemented to allow very low consumption at low frequency.

A built-in hardware oversampler allows analog performances to be improved while offloading the related computational burden from the CPU.

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13.2 ADC main features

• High performance

– 12-bit, 10-bit, 8-bit or 6-bit configurable resolution

– ADC conversion time: 0.87 µs for 12-bit resolution (1.14 MHz), 0.81 µs conversion time for 10-bit resolution, faster conversion times can be obtained by lowering resolution.

– Self-calibration

– Programmable sampling time

– Data alignment with built-in data coherency

– DMA support

• Low-power

– The application can reduce PCLK frequency for low-power operation while still keeping optimum ADC performance. For example, 0.87 µs conversion time is kept, whatever the PCLK frequency

– Wait mode: prevents ADC overrun in applications with low PCLK frequency

– Auto off mode: ADC is automatically powered off except during the active conversion phase. This dramatically reduces the power consumption of the ADC.

• Analog input channels

– 16 external analog inputs

– Three fast channels connected to PA0, PA4 and PA5, and up to 13 standard channels (refer to the device datasheet for details on the corresponding GPIOs)

– 1 channel for internal reference voltage (V

REFINT

)

• Start-of-conversion can be initiated:

– By software

– By hardware triggers with configurable polarity (timer events or GPIO input events)

• Conversion modes

– Can convert a single channel or can scan a sequence of channels.

– Single mode converts selected inputs once per trigger

– Continuous mode converts selected inputs continuously

– Discontinuous mode

• Interrupt generation at the end of sampling, end of conversion, end of sequence conversion, and in case of analog watchdog or overrun events

• Analog watchdog

• Oversampler

– 16-bit data register

– Oversampling ratio adjustable from 2 to 256x

– Programmable data shift up to 8-bits

• ADC input range: V

SSA

≤ V

DDA

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13.3 ADC functional description

Figure 28

shows the ADC block diagram and

Table 52 gives the ADC pin description.

Figure 28. ADC block diagram

ADC_IN[15:0]

TRGO

TRG1

TRG2

TRG3

TRG4

TRG5

TRG6

TRG7

ADC VREF+

1.8 to 3.6V

Analog supply

1.8 to 3.6V

SCANDIR up/down

CH_SEL[18:0]

ADEN/ADDIS

AUTOFF

Auto-off mode

CONT single/cont.

REFINT

IN[x]

Input selection

& scan control

ADCAL selfcalibration

SMP[2:0]

Start & stop sampling time control

WAIT

Auto-delayed conversion

ADSTART

SW trigger

ADSTP stop conversion

Bias & Ref.

SAR ADC

DATA[15:0]

CONVERTED start DATA

Oversampler

OVRMODE

(overrun mode)

ALIGN (left/right)

RES[1:0]

(12, 10, 8, 6 bits)

AREADY

EOSMP

EOSEQ

EOC

OVR

AWD

APB interface

DMAEN

DMACFG

TOVS

AWDxEN

AWDxSGL

AWDCHx[4:0]

LTx[11:0]

HTx[11:0]

OVSS[3:0]

OVSR[2:0]

OVSE HW

EXTEN[1:0]

Trigger enable trigger and edge selection

DISCEN

Discontinuous mode

ADC interrupt

IRQ

CPU

Master

AHB to

APB slave

Master

DMA

DMA request

ADC_AWDx_OUT to analog watchdog

EXTSEL[2:0]

Trigger selection

1. TRGi are mapped at product level. Refer to Table External triggers

in Section 13.3.1: ADC pins and internal signals

MSv48803V4

Name

VDDA

VSSA

ADC_INx

Table 52. ADC input/output pins

Signal type Remarks

Input, analog power supply

Input, analog supply ground

Analog input signals

Analog power supply and positive reference voltage for the ADC

Ground for analog power supply

Up to 16 external analog input channels

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Table 53. ADC internal input/output signals

Internal signal name

Signal type

[x]

TRGx

REFINT

ADC_AWDx_OUT

Analog Input channels

Input

Output

Description

Connected either to internal channels or to ADC_IN i external channels

ADC conversion triggers

Internal voltage reference output voltage

Internal analog watchdog output signal connected to onchip timers (x = Analog watchdog number = 1)

Name

Table 54. External triggers

Source

TRG0

TRG1

TRG2

TRG3

TRG4

TRG5

TRG6

TRG7

Reserved

TIM21_CH2

TIM2_TRGO

TIM2_CH4

TIM22_TRGO

(1)

TIM2_CH3

Reserved

EXTI11

1. TIM21_TRGO is available only in category 1 devices.

EXTSEL[2:0]

100

101

110

111

000

001

010

011

Note:

The ADC has a specific internal voltage regulator which must be enabled and stable before using the ADC.

The ADC voltage regulator stabilization time is entirely managed by the hardware and software does not need to care about it.

After ADC operations are complete, the ADC can be disabled (ADEN = 0). To keep power consumption low, it is important to disable the ADC voltage regulator before entering low-

power mode (LPRun, LPSleep or Stop mode). Refer to Section : ADVREG disable sequence .

When the internal voltage regulator is disabled, the internal analog calibration is kept.

Analog reference for the ADC internal voltage regulator

The internal ADC voltage regulator uses a buffered copy of the internal voltage reference.

This buffer is always enabled when the main voltage regulator is in normal Run mode (MR mode, with the device operating either in Run or Sleep mode). When the main voltage regulator is in low-power mode (with the device operating in LPRun, LPSleep or Stop mode), the voltage reference is disabled and the ADC cannot be used anymore.

The software must follow the procedure described below to manage the ADC in low-power mode:

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Make sure that the ADC is disabled (ADEN = 0).

ADVREGEN 0.

3. Enter low-power mode.

4. Resume from low-power mode.

5. Check that REGLPF = 0.

6. Enable the ADC voltage regulator by using the sequence described in

Section :

ADVREG enable sequence (ADVREGEN = 1 in ADC_CR).

7. Write ADC_CR ADEN = 1 and wait until ADC_CR ADRDY = 1.

8. Write ADRDY = 1 to clear it.

ADVREG enable sequence

There are three ways to enable the voltage regulator:

• by writing ADVREGEN = 1.

• by launching the calibration by writing by ADCAL = 1 (the ADVREGEN bit is automatically set).

• by enabling the ADC by writing ADEN = 1.

ADVREG disable sequence

To disable the ADC voltage regulator, perform the sequence below:

Ensure that the ADC is disabled (ADEN = 0).

13.3.3 Calibration (ADCAL)

The ADC has a calibration feature. During the procedure, the ADC calculates a calibration factor which is internally applied to the ADC until the next ADC power-off. The application must not use the ADC during calibration and must wait until it is complete.

Calibration should be performed before starting A/D conversion. It removes the offset error which may vary from chip to chip due to process variation.

The calibration is initiated by software by setting bit ADCAL = 1. Calibration can only be initiated when the ADC is disabled (when ADEN = 0). ADCAL bit stays at 1 during all the calibration sequence. It is then cleared by hardware as soon the calibration completes. After this, the calibration factor can be read from the ADC_DR register (from bits 6 to 0).

The internal analog calibration is kept if the ADC is disabled (ADEN = 0) or if the ADC voltage reference is disabled (ADVREGEN = 0). When the ADC operating conditions change (V

DDA

changes are the main contributor to ADC offset variations change to a lesser extend), it is recommended to re-run a calibration cycle.

The calibration factor is lost in the following cases:

• The product is in Standby mode (power supply removed from the ADC)

• The ADC peripheral is reset.

The calibration factor is maintained in the following low-power modes: LPRun, LPSleep and

Stop.

It is still possible to save and restore the calibration factor by software to save time when re-starting the ADC (as long as temperature and voltage are stable during the ADC power down).

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RM0451 Analog-to-digital converter (ADC)

The calibration factor can be written if the ADC is enabled but not converting (ADEN = 1 and

ADSTART = 0). Then, at the next start of conversion, the calibration factor is automatically injected into the analog ADC. This loading is transparent and does not add any cycle latency to the start of the conversion.

Software calibration procedure

Ensure that ADEN = 0 and DMAEN = 0.

3. Wait until ADCAL = 0 (or until EOCAL = 1). This can be handled by interrupt if the interrupt is enabled by setting the EOCALIE bit in the ADC_IER register. The ADCAL bit can remain set for some time even after EOCAL has been set. As a result, the software must wait for ADCAL = 0 after EOCAL = 1 to be able to set ADEN = 1 for next

ADC conversions.

4. The calibration factor can be read from bits 6:0 of ADC_DR or ADC_CALFACT registers.

For code example, refer to

A.8.1: Calibration code example

Figure 29. ADC calibration tCAB

ADCAL

ADC State OFF Startup CALIBRATE OFF

ADC_DR[6:0]

ADC_CALFACT[6:0] by S/W by H/W

0x00

CALIBRATION

FACTOR

MS33703V1

If the ADC voltage regulator was not previously set, it is automatically enabled when setting

ADCAL = 1 (bit ADVREGEN is automatically set by hardware). In this case, the ADC calibration time is longer to take into account the stabilization time of the ADC voltage regulator.

At the end of the calibration, the ADC voltage regulator remains enabled.

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Calibration factor forcing software procedure

Ensure that ADEN= 1 and ADSTART = 0 (ADC started with no conversion ongoing)

2. Write ADC_CALFACT with the saved calibration factor

3. The calibration factor is used as soon as a new conversion is launched.

Figure 30. Calibration factor forcing

ADC state

Internal calibration factor[6:0]

Start conversion

(hardware or software)

WRITE ADC_CALFACT

CALFACT[6:0]

Ready (not converting)

Converting channel

Updating calibration

(Single ended)

Ready Converting channel

(Single ended) by S/W by H/W

MS31925V1

At power-up, the ADC is disabled and put in power-down mode (ADEN = 0).

As shown in

Figure 31

, the ADC needs a stabilization time of t

STAB converting accurately.

before it starts

Two control bits are used to enable or disable the ADC:

• Set ADEN = 1 to enable the ADC. The ADRDY flag is set as soon as the ADC is ready for operation.

• Set ADDIS = 1 to disable the ADC and put the ADC in power down mode. The ADEN and ADDIS bits are then automatically cleared by hardware as soon as the ADC is fully disabled.

If the ADC voltage regulator was not previously set, it is automatically enabled when setting

ADEN=1 (bit ADVREGEN is automatically set by hardware). In this case, the ADC stabilization time t

STAB voltage regulator.

is longer to take into account the stabilization time of the ADC

Conversion can then start either by setting ADSTART to 1 (refer to Section 13.4: Conversion on external trigger and trigger polarity (EXTSEL, EXTEN) on page 266 ) or when an external

trigger event occurs if triggers are enabled.

Follow this procedure to enable the ADC:

Clear the ADRDY bit in ADC_ISR register by programming this bit to 1.

2. Set ADEN = 1 in the ADC_CR register.

3. Wait until ADRDY = 1 in the ADC_ISR register (ADRDY is set after the ADC startup time). This can be handled by interrupt if the interrupt is enabled by setting the

ADRDYIE bit in the ADC_IER register.

For code example, refer to

A.8.2: ADC enable sequence code example

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RM0451 Analog-to-digital converter (ADC)

Follow this procedure to disable the ADC:

Check that ADSTART = 0 in the ADC_CR register to ensure that no conversion is ongoing. If required, stop any ongoing conversion by writing 1 to the ADSTP bit in the

ADC_CR register and waiting until this bit is read at 0.

2. Set ADDIS = 1 in the ADC_CR register.

3. If required by the application, wait until ADEN = 0 in the ADC_CR register, indicating that the ADC is fully disabled (ADDIS is automatically reset once ADEN = 0).

4. Clear the ADRDY bit in ADC_ISR register by programming this bit to 1 (optional).

For code example, refer to

A.8.3: ADC disable sequence code example .

Figure 31. Enabling/disabling the ADC

ADEN

ADR DY

ADDIS

ADC stat tSTAB

OFF Startup RDY CONVERTING CH RDY

REQ

-OF

OFF

Note: by S/W by H/W

MS30264V2

In Auto-off mode (AUTOFF = 1) the power-on/off phases are performed automatically, by hardware and the ADRDY flag is not set.

The ADC has a dual clock-domain architecture, so that the ADC can be fed with a clock

(ADC asynchronous clock) independent from the APB clock (PCLK).

Figure 32. ADC clock scheme

RCC

(Reset & Clock Controller)

ADITF

PCLK

APB interface

Bits CKMODE[1:0] of ADC_CFGR2

ADC asynchronous clock

/1 or /2 or /4 Others

Analog ADC_CK Analog

ADC

/1,2,4,6,8,10,12

16,32,64,128,256

Bits PRESC[3:0] of ADC_CCR

Bits CKMODE[1:0] of ADC_CFGR2

MSv31926V2

1. Refer to Section Reset and clock control (RCC ) for how the PCLK clock and ADC asynchronous clock are enabled.

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The input clock of the analog ADC can be selected between two different clock sources (see

Figure 32: ADC clock scheme to see how the PCLK clock and the ADC asynchronous clock

are enabled): a) The ADC clock can be a specific clock source, named “ADC asynchronous clock“ which is independent and asynchronous with the APB clock.

Refer to RCC Section for more information on generating this clock source.

To select this scheme, bits CKMODE[1:0] of the ADC_CFGR2 register must be reset.

b) The ADC clock can be derived from the APB clock of the ADC bus interface, divided by a programmable factor (1, 2 or 4) according to bits CKMODE[1:0].

To select this scheme, bits CKMODE[1:0] of the ADC_CFGR2 register must be different from “00”.

For code example, refer to

A.8.4: ADC clock selection code example .

In option a), the generated ADC clock can eventually be divided by a prescaler (1, 2, 4, 6, 8,

10, 12, 16, 32, 64, 128, 256) when programming the bits PRESC[3:0] in the ADC_CCR register).

Option a) has the advantage of reaching the maximum ADC clock frequency whatever the

APB clock scheme selected.

Option b) has the advantage of bypassing the clock domain resynchronizations. This can be useful when the ADC is triggered by a timer and if the application requires that the ADC is precisely triggered without any uncertainty (otherwise, an uncertainty of the trigger instant is added by the resynchronizations between the two clock domains).

Table 55. Latency between trigger and start of conversion (1)

ADC clock source CKMODE[1:0]

Latency between the trigger event and the start of conversion

HSI16 MHz clock

PCLK divided by 2

PCLK divided by 4

PCLK divided by 1

Latency is not deterministic (jitter)

Latency is deterministic (no jitter) and equal to

4.25 ADC clock cycles

Latency is deterministic (no jitter) and equal to

4.125 ADC clock cycles

Latency is deterministic (no jitter) and equal to

4.5 ADC clock cycles

1. Refer to the device datasheet for the maximum ADC_CLK frequency.

Caution: When selecting CKMODE[1:0] = 11 (PCLK divided by 1), the user must ensure that the

PCLK has a 50% duty cycle. This is done by selecting a system clock with a 50% duty cycle and configuring the APB prescaler in bypass modes in the RCC (refer to there Reset and clock controller section). If an internal source clock is selected, the AHB and APB prescalers do not divide the clock.

Low frequency

When selecting an analog ADC clock frequency lower than 3.5 MHz, it is mandatory to first enable the Low Frequency Mode by setting bit LFMEN = 1 into the ADC_CCR register

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RM0451 Analog-to-digital converter (ADC)

ADC inputs are connected to the external channels as well as internal sources as described in

Figure 33

Figure 33. ADC connectivity

ADC_IN10

ADC_IN11

ADC_IN12

ADC_IN13

ADC_IN14

ADC_IN15

ADC_IN0

ADC_IN1

ADC_IN2

ADC_IN3

ADC_IN4

ADC_IN5

ADC_IN6

ADC_IN7

ADC_IN8

ADC_IN9

STM32L0x0

[8]

[9]

[10]

[11]

[12]

[13]

[14]

Reserved

[15]

[16]

[17]

REFINT

Reserved

[18]

[3]

[4]

[5]

[6]

[7]

ADC

[0]

[1]

[2]

Channel selection

Fast channel

SAR

ADC1

REF+

REF-

MSv68733V1

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Note:

The software must write the ADCAL and ADEN bits in the ADC_CR register and configure the ADC_CFGR1 and ADC_CFGR2 registers only when the ADC is disabled (ADEN must be cleared).

The software must only write to the ADSTART and ADDIS bits in the ADC_CR register only if the ADC is enabled and there is no pending request to disable the ADC (ADEN = 1 and

ADDIS = 0).

For all the other control bits in the ADC_IER, ADC_SMPR, ADC_TR, ADC_CHSELR and

ADC_CCR registers, refer to the description of the corresponding control bit in

Section 13.11: ADC registers .

The software must only write to the ADSTP bit in the ADC_CR register if the ADC is enabled

(and possibly converting) and there is no pending request to disable the ADC (ADSTART =

1 and ADDIS = 0).

There is no hardware protection preventing software from making write operations forbidden by the above rules. If such a forbidden write access occurs, the ADC may enter an undefined state. To recover correct operation in this case, the ADC must be disabled (clear

ADEN = 0 and all the bits in the ADC_CR register).

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There are up to 17 multiplexed channels:

• 16 analog inputs from GPIO pins (ADC_INx)

• 1 internal analog inputs (Internal Reference Voltage)

It is possible to convert a single channel or a sequence of channels.

The sequence of the channels to be converted can be programmed in the ADC_CHSELR channel selection register: each analog input channel has a dedicated selection bit

(CHSELx).

The order in which the channels is scanned can be configured by programming the bit

SCANDIR bit in the ADC_CFGR1 register:

• SCANDIR = 0: forward scan Channel 0 to Channel 17

• SCANDIR = 1: backward scan Channel 17 to Channel 0

V

REFINT

internal channel

The internal voltage reference V

REFINT

is connected to channel ADC V

[17].

Before starting a conversion, the ADC needs to establish a direct connection between the voltage source to be measured and the embedded sampling capacitor of the ADC. This sampling time must be enough for the input voltage source to charge the sample and hold capacitor to the input voltage level.

Having a programmable sampling time allows the conversion speed to be trimmed according to the input resistance of the input voltage source.

Refer to the device datasheet to select the correct sampling time depending on the type of channel you are using (fast or standard).

RM0451 Rev 3

RM0451 Analog-to-digital converter (ADC)

The ADC samples the input voltage for a number of ADC clock cycles that can be modified using the SMP[2:0] bits in the ADC_SMPR register.

This programmable sampling time is common to all channels. If required by the application, the software can change and adapt this sampling time between each conversions.

The total conversion time is calculated as follows: t

CONV

= Sampling time + 12.5 x ADC clock cycles

Example:

With ADC_CLK = 16 MHz and a sampling time of 1.5 ADC clock cycles: t

CONV

= 1.5 + 12.5 = 14 ADC clock cycles = 0.875 µs

The ADC indicates the end of the sampling phase by setting the EOSMP flag.

13.3.10 Single conversion mode (CONT

0)

Note:

In Single conversion mode, the ADC performs a single sequence of conversions, converting all the channels once. This mode is selected when CONT = 0 in the ADC_CFGR1 register.

Conversion is started by either:

• Setting the ADSTART bit in the ADC_CR register

• Hardware trigger event

Inside the sequence, after each conversion is complete:

• The converted data are stored in the 16-bit ADC_DR register

• The EOC (end of conversion) flag is set

• An interrupt is generated if the EOCIE bit is set

After the sequence of conversions is complete:

• The EOS (end of sequence) flag is set

• An interrupt is generated if the EOSIE bit is set

Then the ADC stops until a new external trigger event occurs or the ADSTART bit is set again.

To convert a single channel, program a sequence with a length of 1.

13.3.11 Continuous conversion mode (CONT

1)

In continuous conversion mode, when a software or hardware trigger event occurs, the ADC performs a sequence of conversions, converting all the channels once and then automatically re-starts and continuously performs the same sequence of conversions. This mode is selected when CONT = 1 in the ADC_CFGR1 register. Conversion is started by either:

• Setting the ADSTART bit in the ADC_CR register

• Hardware trigger event

Inside the sequence, after each conversion is complete:

• The converted data are stored in the 16-bit ADC_DR register

• The EOC (end of conversion) flag is set

• An interrupt is generated if the EOCIE bit is set

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Note:

After the sequence of conversions is complete:

• The EOS (end of sequence) flag is set

• An interrupt is generated if the EOSIE bit is set

Then, a new sequence restarts immediately and the ADC continuously repeats the conversion sequence.

To convert a single channel, program a sequence with a length of 1.

It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCEN = 1 and CONT = 1.

13.3.12 Starting conversions (ADSTART)

Note:

Software starts ADC conversions by setting ADSTART = 1.

When ADSTART is set, the conversion:

• Starts immediately if EXTEN = 00 (software trigger)

• At the next active edge of the selected hardware trigger if EXTEN ≠ 00

The ADSTART bit is also used to indicate whether an ADC operation is currently ongoing. It is possible to re-configure the ADC while ADSTART = 0, indicating that the ADC is idle.

The ADSTART bit is cleared by hardware:

• In single mode with software trigger (CONT = 0, EXTEN = 00)

– At any end of conversion sequence (EOS = 1)

• In discontinuous mode with software trigger (CONT = 0, DISCEN = 1, EXTEN = 00)

– At end of conversion (EOC = 1)

• In all cases (CONT = x, EXTEN = XX)

– After execution of the ADSTP procedure invoked by software (see

Section 13.3.14: Stopping an ongoing conversion (ADSTP) on page 266

)

In continuous mode (CONT = 1), the ADSTART bit is not cleared by hardware when the

EOS flag is set because the sequence is automatically relaunched.

When hardware trigger is selected in single mode (CONT = 0 and EXTEN = 01 ), ADSTART is not cleared by hardware when the EOS flag is set (except if DMAEN = 1 and

DMACFG = 0 in which case ADSTART is cleared at end of the DMA transfer). This avoids the need for software having to set the ADSTART bit again and ensures the next trigger event is not missed.

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13.3.13 Timings

The elapsed time between the start of a conversion and the end of conversion is the sum of the configured sampling time plus the successive approximation time depending on data resolution: t

CONV

= t

SMPL

+ t

SAR

= [ 1.5

|min

+ 12.5

|12bit

] x t

ADC_CLK t

CONV

= t

SMPL

+ t

SAR

= 93.8 ns

|min

+ 781.3 ns

|12bit

= 0.875 µs

|min

(for f

ADC_CLK

= 16 MHz)

Figure 34. Analog to digital conversion time

ADC state

Analog channel

Internal S/H

RDY SAMPLING CH(N)

CH(N)

Sample AIN(N+1) t

SMPL

(1) set by SW

ADSTART

EOSMP

EOC

ADC_DR

(1) t

SMPL depends on SMP[2:0]

(2) t

SAR depends on RES[2:0] set by HW

DATA N-1

CONVERTING CH(N)

Hold AIN(N) t

SAR

(2) cleared by SW

Figure 35. ADC conversion timings set by HW

SAMPLING CH(N+1)

CH(N+1)

Sample AIN(N+1)

DATA N cleared by SW

MS30336V1

ADSTART

(1)

ADC state

ADC_DR t

LATENCY

(2)

Ready S0 Conversion 0 S1 Conversion 1

LATENCY

(3)

S2 Conversion 2

LATENCY

(3)

S3 Conversion 3

LATENCY

(3)

Data 0 Data 1 Data 2

MSv33174V1

1. EXTEN = 00 or EXTEN ≠ 00

2. Trigger latency (refer to datasheet for more details)

3. ADC_DR register write latency (refer to datasheet for more details)

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13.3.14 Stopping an ongoing conversion (ADSTP)

The software can decide to stop any ongoing conversions by setting ADSTP = 1 in the

ADC_CR register.

This resets the ADC operation and the ADC is idle, ready for a new operation.

When the ADSTP bit is set by software, any ongoing conversion is aborted and the result is discarded (ADC_DR register is not updated with the current conversion).

The scan sequence is also aborted and reset (meaning that restarting the ADC would restart a new sequence).

Once this procedure is complete, the ADSTP and ADSTART bits are both cleared by hardware and the software must wait until ADSTART=0 before starting new conversions.

Figure 36. Stopping an ongoing conversion

ADC state

ADSTART

ADSTOP

ADC_DR

RDY set by SW

SAMPLING CH(N)

DATA N-1

CONVERTING CH(N) set by SW

RDY cleared by HW cleared by HW

MS30337V1

13.4 Conversion on external trigger and trigger polarity (EXTSEL,

EXTEN)

A conversion or a sequence of conversion can be triggered either by software or by an external event (for example timer capture). If the EXTEN[1:0] control bits are not equal to

“0b00”, then external events are able to trigger a conversion with the selected polarity. The trigger selection is effective once software has set bit ADSTART = 1.

Any hardware triggers which occur while a conversion is ongoing are ignored.

If bit ADSTART = 0, any hardware triggers which occur are ignored.

Table 56 provides the correspondence between the EXTEN[1:0] values and the trigger

polarity.

Table 56. Configuring the trigger polarity

Source

Trigger detection disabled

Detection on rising edge

Detection on falling edge

Detection on both rising and falling edges

EXTEN[1:0]

Note: The polarity of the external trigger can be changed only when the ADC is not converting

(ADSTART = 0).

The EXTSEL[2:0] control bits are used to select which of 8 possible events can trigger conversions.

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Note:

Analog-to-digital converter (ADC)

Refer to Table 54: External triggers in

Section 13.3.1: ADC pins and internal signals

for the list of all the external triggers that can be used for regular conversion.

The software source trigger events can be generated by setting the ADSTART bit in the

ADC_CR register.

The trigger selection can be changed only when the ADC is not converting (ADSTART = 0).

Note:

This mode is enabled by setting the DISCEN bit in the ADC_CFGR1 register.

In this mode (DISCEN = 1), a hardware or software trigger event is required to start each conversion defined in the sequence. On the contrary, if DISCEN = 0, a single hardware or software trigger event successively starts all the conversions defined in the sequence.

Example:

• DISCEN = 1, channels to be converted = 0, 3, 7, 10

– 1st trigger: channel 0 is converted and an EOC event is generated

– 2nd trigger: channel 3 is converted and an EOC event is generated

– 3rd trigger: channel 7 is converted and an EOC event is generated

– 4th trigger: channel 10 is converted and both EOC and EOS events are generated.

– 5th trigger: channel 0 is converted an EOC event is generated

– 6th trigger: channel 3 is converted and an EOC event is generated

– ...

• DISCEN = 0, channels to be converted = 0, 3, 7, 10

– 1st trigger: the complete sequence is converted: channel 0, then 3, 7 and 10. Each conversion generates an EOC event and the last one also generates an EOS event.

– Any subsequent trigger events restarts the complete sequence.

It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCEN = 1 and CONT = 1.

13.4.2 Programmable resolution (RES) - Fast conversion mode

Note:

It is possible to obtain faster conversion times (t

SAR

) by reducing the ADC resolution.

The resolution can be configured to be either 12, 10, 8, or 6 bits by programming the

RES[1:0] bits in the ADC_CFGR1 register. Lower resolution allows faster conversion times for applications where high data precision is not required.

The RES[1:0] bit must only be changed when the ADEN bit is reset.

The result of the conversion is always 12 bits wide and any unused LSB bits are read as zeros.

Lower resolution reduces the conversion time needed for the successive approximation

steps as shown in Table 57

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RES[1:0] bits

Table 57. t

SAR

timings depending on resolution t

SAR

(ADC clock cycles) f t

SAR

(ns) at

ADC

= 16 MHz t

SMPL (min)

(ADC clock cycles) t

CONV

(ADC clock cycles)

(with min. t

SMPL)

12.5

11.5

781 ns

719 ns

1.5

f t

CONV

(ns) at

ADC

= 16 MHz

875 ns

812 ns

11 688

13.4.3 End of conversion, end of sampling phase (EOC, EOSMP flags)

Note:

The ADC indicates each end of conversion (EOC) event.

The ADC sets the EOC flag in the ADC_ISR register as soon as a new conversion data result is available in the ADC_DR register. An interrupt can be generated if the EOCIE bit is set in the ADC_IER register. The EOC flag is cleared by software either by writing 1 to it, or by reading the ADC_DR register.

The ADC also indicates the end of sampling phase by setting the EOSMP flag in the

ADC_ISR register. The EOSMP flag is cleared by software by writing1 to it. An interrupt can be generated if the EOSMPIE bit is set in the ADC_IER register.

The aim of this interrupt is to allow the processing to be synchronized with the conversions.

Typically, an analog multiplexer can be accessed in hidden time during the conversion phase, so that the multiplexer is positioned when the next sampling starts.

As there is only a very short time left between the end of the sampling and the end of the conversion, it is recommenced to use polling or a WFE instruction rather than an interrupt and a WFI instruction.

The ADC notifies the application of each end of sequence (EOS) event.

The ADC sets the EOS flag in the ADC_ISR register as soon as the last data result of a conversion sequence is available in the ADC_DR register. An interrupt can be generated if the EOSIE bit is set in the ADC_IER register. The EOS flag is cleared by software by writing

1 to it.

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13.4.5 Example timing diagrams (single/continuous modes hardware/software triggers)

Figure 37. Single conversions of a sequence, software trigger

ADSTART

(1)

EOC

EOS

SCANDIR

ADC state

(2)

ADC_DR by S/W

RDY by H/W

CH0 CH9 CH10 CH17

D0 D9 D10

RDY

D17

CH17 CH10 CH9 CH0

D17 D10 D9

RDY

MSv30338V3

1. EXTEN = 00, CONT = 0

2. CHSEL = 0x20601, WAIT = 0, AUTOFF = 0

For code example, refer to

A.8.5: Single conversion sequence code example - Software trigger

Figure 38. Continuous conversion of a sequence, software trigger

ADSTART

(1)

EOC

EOS

ADSTP

SCANDIR

ADC state

(2) RDY

ADC_DR

CH0 CH9

CH10 CH17 CH0 CH9 CH10 STP

D9 D10 D17 D0 D9

RDY CH17 CH10

D17 by S/W by H/W

MSv30339V2

1. EXTEN = 00, CONT = 1,

2. CHSEL = 0x20601, WAIT = 0, AUTOFF = 0

For code example, refer to

A.8.6: Continuous conversion sequence code example -

Software trigger .

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Figure 39. Single conversions of a sequence, hardware trigger

RM0451

ADSTART

(1)

EOC

EOS

TRGx

(1)

ADC state

(2)

ADC_DR by S/W triggered

RDY by H/W ignored

CH0 CH1 CH2 CH3 RDY CH0 CH1 CH2 CH3 RDY

D0 D1 D2 D3 D0 D1 D2 D3

MSv30340V2

1. EXTSEL = TRGx (over-frequency), EXTEN = 01 (rising edge), CONT = 0

2. CHSEL = 0xF, SCANDIR = 0, WAIT = 0, AUTOFF = 0

Figure 40. Continuous conversions of a sequence, hardware trigger

ADSTART

(1)

EOC

EOS

ADSTP

TRGx

(1)

ADC state

(2)

ADC_DR

RDY CH0 CH1 CH2 CH3 CH0 CH1 CH2 CH3 CH0 STOP RDY

D0 D1 D2 D3 D0 D1 D2 D3 by S/W triggered by H/W ignored

MSv30341V2

1. EXTSEL = TRGx, EXTEN = 10 (falling edge), CONT = 1

2. CHSEL = 0xF, SCANDIR = 0, WAIT = 0, AUTOFF = 0

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13.5.1 Data register and data alignment (ADC_DR, ALIGN)

At the end of each conversion (when an EOC event occurs), the result of the converted data is stored in the ADC_DR data register which is 16-bit wide.

The format of the ADC_DR depends on the configured data alignment and resolution.

The ALIGN bit in the ADC_CFGR1 register selects the alignment of the data stored after conversion. Data can be right-aligned (ALIGN = 0) or left-aligned (ALIGN = 1) as shown in

Figure 41

Figure 41. Data alignment and resolution (oversampling disabled: OVSE = 0)

ALIGN RES

0 0x0

0x1

0x2

0x3

1 0x0

0x1

0x2

0x3

15 14 13 12 11 10

0x0

0x00

DR[9:0]

DR[7:0]

0x00

DR[11:0]

8 7 6 5 4 3 2 1

DR[11:0]

DR[9:0]

DR[7:0]

DR[5:0]

0x0

0x00

DR[5:0] 0x0

MS30342V1

13.5.2 ADC overrun (OVR, OVRMOD)

The overrun flag (OVR) indicates a data overrun event, when the converted data was not read in time by the CPU or the DMA, before the data from a new conversion is available.

The OVR flag is set in the ADC_ISR register if the EOC flag is still at ‘1’ at the time when a new conversion completes. An interrupt can be generated if the OVRIE bit is set in the

ADC_IER register.

When an overrun condition occurs, the ADC keeps operating and can continue to convert unless the software decides to stop and reset the sequence by setting the ADSTP bit in the

ADC_CR register.

The OVR flag is cleared by software by writing 1 to it.

It is possible to configure if the data is preserved or overwritten when an overrun event occurs by programming the OVRMOD bit in the ADC_CFGR1 register:

• OVRMOD = 0

– An overrun event preserves the data register from being overwritten: the old data is maintained and the new conversion is discarded. If OVR remains at 1, further conversions can be performed but the resulting data is discarded.

• OVRMOD = 1

– The data register is overwritten with the last conversion result and the previous unread data is lost. If OVR remains at 1, further conversions can be performed and the ADC_DR register always contains the data from the latest conversion.

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Figure 42. Example of overrun (OVR)

RM0451

ADSTART

(1)

EOC

EOS

OVR

ADSTP

TRGx

(1)

ADC state

(2)

ADC_DR read access

ADC_DR

(OVRMOD=0)

ADC_DR

(OVRMOD=1)

RDY CH0 CH1 CH2 CH0 CH1 CH2 CH0 STOP

OVERRUN

D0 D1 D2 D0

D0 D1 D2 D0 D1 D2

RDY by S/W triggered by H/W

MSv30343V3

13.5.3 Managing a sequence of data converted without using the DMA

If the conversions are slow enough, the conversion sequence can be handled by software.

In this case the software must use the EOC flag and its associated interrupt to handle each data result. Each time a conversion is complete, the EOC bit is set in the ADC_ISR register and the ADC_DR register can be read. The OVRMOD bit in the ADC_CFGR1 register should be configured to 0 to manage overrun events as an error.

13.5.4 Managing converted data without using the DMA without overrun

It may be useful to let the ADC convert one or more channels without reading the data after each conversion. In this case, the OVRMOD bit must be configured at 1 and the OVR flag should be ignored by the software. When OVRMOD = 1, an overrun event does not prevent the ADC from continuing to convert and the ADC_DR register always contains the latest conversion data.

13.5.5 Managing converted data using the DMA

Since all converted channel values are stored in a single data register, it is efficient to use

DMA when converting more than one channel. This avoids losing the conversion data results stored in the ADC_DR register.

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Note:

Analog-to-digital converter (ADC)

When DMA mode is enabled (DMAEN bit set in the ADC_CFGR1 register), a DMA request is generated after the conversion of each channel. This allows the transfer of the converted data from the ADC_DR register to the destination location selected by the software.

The DMAEN bit in the ADC_CFGR1 register must be set after the ADC calibration phase.

Despite this, if an overrun occurs (OVR = 1) because the DMA could not serve the DMA transfer request in time, the ADC stops generating DMA requests and the data corresponding to the new conversion is not transferred by the DMA. Which means that all the data transferred to the RAM can be considered as valid.

Depending on the configuration of OVRMOD bit, the data is either preserved or overwritten

(refer to

Section 13.5.2: ADC overrun (OVR, OVRMOD) on page 271 ).

The DMA transfer requests are blocked until the software clears the OVR bit.

Two different DMA modes are proposed depending on the application use and are configured with bit DMACFG in the ADC_CFGR1 register:

• DMA one shot mode (DMACFG = 0).

This mode should be selected when the DMA is programmed to transfer a fixed number of data words.

• DMA circular mode (DMACFG = 1)

This mode should be selected when programming the DMA in circular mode.

DMA one shot mode (DMACFG

0)

In this mode, the ADC generates a DMA transfer request each time a new conversion data word is available and stops generating DMA requests once the DMA has reached the last

DMA transfer (when a DMA_EOT interrupt occurs, see Section 10: Direct memory access controller (DMA) on page 216 ) even if a conversion has been started again.

For code example, refer to

A.8.9: DMA one shot mode sequence code example

When the DMA transfer is complete (all the transfers configured in the DMA controller have been done):

• The content of the ADC data register is frozen.

• Any ongoing conversion is aborted and its partial result discarded

• No new DMA request is issued to the DMA controller. This avoids generating an overrun error if there are still conversions which are started.

• The scan sequence is stopped and reset

• The DMA is stopped

DMA circular mode (DMACFG

1)

In this mode, the ADC generates a DMA transfer request each time a new conversion data word is available in the data register, even if the DMA has reached the last DMA transfer.

This allows the DMA to be configured in circular mode to handle a continuous analog input data stream.

For code example, refer to

A.8.10: DMA circular mode sequence code example

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13.6.1 Wait mode conversion

Note:

Wait mode conversion can be used to simplify the software as well as optimizing the performance of applications clocked at low frequency where there might be a risk of ADC overrun occurring.

When the WAIT bit is set in the ADC_CFGR1 register, a new conversion can start only if the previous data has been treated, once the ADC_DR register has been read or if the EOC bit has been cleared.

This is a way to automatically adapt the speed of the ADC to the speed of the system that reads the data.

Any hardware triggers which occur while a conversion is ongoing or during the wait time preceding the read access are ignored.

Figure 43. Wait mode conversion (continuous mode, software trigger)

ADSTART

EOC

EOS

ADSTP

ADC_DR Read access

ADC state

RDY

ADC_DR

CH1 DLY CH2 DLY CH3

D1 D2 by S/W by H/W

DLY

CH1 DLY STOP RDY

MSv30344V2

1. EXTEN = 00, CONT = 1

2. CHSEL = 0x3, SCANDIR = 0, WAIT = 1, AUTOFF = 0

For code example, refer to

A.8.11: Wait mode sequence code example .

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Note:

The ADC has an automatic power management feature which is called auto-off mode, and is enabled by setting AUTOFF = 1 in the ADC_CFGR1 register.

When AUTOFF = 1, the ADC is always powered off when not converting and automatically wakes-up when a conversion is started (by software or hardware trigger). A startup-time is automatically inserted between the trigger event which starts the conversion and the sampling time of the ADC. The ADC is then automatically disabled once the sequence of conversions is complete.

Auto-off mode can cause a dramatic reduction in the power consumption of applications which need relatively few conversions or when conversion requests are timed far enough apart (for example with a low frequency hardware trigger) to justify the extra power and extra time used for switching the ADC on and off.

Auto-off mode can be combined with the wait mode conversion (WAIT = 1) for applications clocked at low frequency. This combination can provide significant power savings if the ADC is automatically powered-off during the wait phase and restarted as soon as the ADC_DR

Refer to the Section Reset and clock control (RCC) for the description of how to manage the dedicated 14 MHz internal oscillator. The ADC interface can automatically switch

ON/OFF the 14 MHz internal oscillator to save power.

Figure 44. Behavior with WAIT = 0, AUTOFF = 1

TRGx

EOC

EOS

ADC_DR Read access

ADC state

RDY Startup CH1 CH2 CH3 CH4

ADC_DR D1 D2 D3

OFF Startup

D4 by S/W triggered by H/W

MSv30345V2

1. EXTSEL = TRGx, EXTEN = 01 (rising edge), CONT = x, ADSTART = 1, CHSEL = 0xF, SCANDIR = 0, WAIT = 1,

AUTOFF = 1

For code example, refer to

A.8.12: Auto off and no wait mode sequence code example .

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Figure 45. Behavior with WAIT = 1, AUTOFF = 1

RM0451

TRGx

EOC

EOS

ADC_DR Read access

ADC state

RDY Startup CH1

ADC_DR

DLY

OFF Startup CH2

DLY

Startup CH3

D1 D2

DLY

OFF

Startup CH1

DLY

CH2

D4 by S/W triggered by H/W

MSv30346V2

1. EXTSEL = TRGx, EXTEN = 01 (rising edge), CONT = x, ADSTART = 1, CHSEL = 0xF, SCANDIR = 0, WAIT = 1,

AUTOFF = 1

For code example, refer to

A.8.13: Auto off and wait mode sequence code example

13.7 Analog window watchdog (AWDEN, AWDSGL, AWDCH,

ADC_TR)

The AWD analog watchdog is enabled by setting the AWDEN bit in the ADC_CFGR1 register. It is used to monitor that either one selected channel or all enabled channels

Table 59: Analog watchdog channel selection )

(see remain within a configured voltage range

(window) as shown in Figure 46 .

The AWD analog watchdog status bit is set if the analog voltage converted by the ADC is below a lower threshold or above a higher threshold. These thresholds are programmed in

HT[11:0] and LT[11:0] bit of ADC_TR register. An interrupt can be enabled by setting the

AWDIE bit in the ADC_IER register.

The AWD flag is cleared by software by programming it to it.

When converting data with a resolution of less than 12-bit (according to bits RES[1:0]), the

LSB of the programmed thresholds must be kept cleared because the internal comparison is always performed on the full 12-bit raw converted data (left aligned).

For code example, refer to

A.8.14: Analog watchdog code example .

Table 58 describes how the comparison is performed for all the possible resolutions.

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Table 58. Analog watchdog comparison

Resolution bits

RES[1:0]

Analog Watchdog comparison between:

Raw converted data, left aligned

(1)

Thresholds

Comments

00: 12-bit DATA[11:0] LT[11:0] and HT[11:0] -

01: 10-bit

10: 8-bit

11: 6-bit

DATA[11:2],00

DATA[11:4],0000

DATA[11:6],000000

LT[11:0] and HT[11:0] The user must configure LT1[1:0] and HT1[1:0] to “00”

LT[11:0] and HT[11:0]

The user must configure LT1[3:0] and HT1[3:0] to

“0000”

LT[11:0] and HT[11:0]

The user must configure LT1[5:0] and HT1[5:0] to

“000000”

1. The watchdog comparison is performed on the raw converted data before any alignment calculation.

Table 59 shows how to configure the AWDSGL and AWDEN bits in the ADC_CFGR1

Figure 46. Analog watchdog guarded area

Analog voltage

Higher threshold HTx

Guarded area

Lower threshold LTx

MS45396V1

Table 59. Analog watchdog channel selection

Channels guarded by the analog watchdog AWDSGL bit

None

All channels

Single

(1)

channel

1. Selected by the AWDCH[4:0] bits x

AWDEN bit

13.7.2 ADC_AWD1_OUT output signal generation

The analog watchdog is associated to an internal hardware signal, ADC_AWD1_OUT that is directly connected to the ETR input (external trigger) of some on-chip timers (refer to the timers section for details on how to select the ADC_AWD1_OUT signal as ETR).

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ADC_AWD1_OUT is activated when the analog watchdog is enabled:

• ADC_AWD1_OUT is set when a guarded conversion is outside the programmed thresholds.

• ADC_AWD1_OUT is reset after the end of the next guarded conversion which is inside the programmed thresholds. It remains at 1 if the next guarded conversions are still outside the programmed thresholds.

• ADC_AWD1_OUT is also reset when disabling the ADC (when setting ADDIS to 1).

Note that stopping conversions (ADSTP set), might clear the ADC_AWD1_OUT state.

• ADC_AWD1_OUT state does not change when the ADC converts the none-guarded channel (see

Figure 47

)

AWD flag is set by hardware and reset by software: AWD flag has no influence on the generation of ADC_AWD1_OUT (as an example, ADC_AWD1_OUT can toggle while AWD flag remains at 1 if the software has not cleared the flag).

The ADC_AWD1_OUT signal is generated by the ADC_CLK domain. This signal can be generated even the APB clock is stopped.

The AWD comparison is performed at the end of each ADC conversion. The

ADC_AWD1_OUT rising edge and falling edge occurs two ADC_CLK clock cycles after the comparison.

As ADC_AWD1_OUT is generated by the ADC_CLK domain and AWD flag is generated by the APB clock domain, the rising edges of these signals are not synchronized.

Figure 47. ADC_AWD1_OUT signal generation

ADC STATE

RDY Conversion1 inside

EOC FLAG

Conversion2 outside

Conversion3 inside

Conversion4 outside

AWD FLAG

Cleared by SW

Conversion5 outside

Conversion6 outside

Conversion7 inside

Cleared by SW

ADC_AWD1_OUT

- Converted channels: 1,2,3,4,5,6,7

- Guarded converted channels: 1,2,3,4,5,6,7

MSv65326V1

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Figure 48. ADC_AWD1_OUT signal generation (AWD flag not cleared by software)

ADC STATE RDY Conversion1 inside

Conversion2 outside

EOC FLAG

Conversion3 inside

Conversion4 outside

Conversion5 outside not cleared by SW

AWD FLAG

Conversion6 outside

Conversion7 inside

ADC_AWD1_OUT

- Converted channels: 1,2,3,4,5,6,7

- Guarded converted channels: 1,2,3,4,5,6,7

MSv65327V1

Figure 49. ADC1_AWD_OUT signal generation (on a single channel)

ADC STATE

Conversion1 outside

Conversion2 Conversion1 inside

Conversion2 Conversion1 Conversion2 outside

EOC FLAG

Conversion1 outside

Conversion2

EOS FLAG

AWD FLAG

ADCy_AWD1_OUT

Cleared by SW

- Converted channels: 1 and 2

- Only channel 1 is guarded

MSv65328V1

13.7.3 Analog watchdog threshold control

LT[11:0] and HT[11:0] can be changed during an analog-to-digital conversion (that is between the start of the conversion and the end of conversion of the ADC internal state). If

LT and HT bits are programmed during the ADC guarded channel conversion, the watchdog function is masked for this conversion. This mask is cleared when starting a new conversion, and the resulting new AWD threshold is applied starting the next ADC conversion result. AWD comparison is performed at each end of conversion. If the current

ADC data are out of the new threshold interval, this does not generated any interrupt or an

ADC_AWD1_OUT signal. The Interrupt and the ADC_AWD1_OUT generation only occurs at the end of the ADC conversion that started after the threshold update. If

ADC_AWD1_OUT is already asserted, programming the new threshold does not deassert the ADC_AWD1_OUT signal.

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Figure 50. Analog watchdog threshold update

RM0451

ADC state

LT, HT

Comparison

Conversion

XXXX

Conversion Conversion

Threshould updated

XXXY

Active Masked

Conversion

XXXZ

Active

MSv65329V1

13.8 Oversampler

The oversampling unit performs data preprocessing to offload the CPU. It can handle multiple conversions and average them into a single data with increased data width, up to

16-bit.

It provides a result with the following form, where N and M can be adjusted:

Result

=

×

n = N 1

 n = 0 n

Note:

It allows the following functions to be performed by hardware: averaging, data rate reduction, SNR improvement, basic filtering.

The oversampling ratio N is defined using the OVFS[2:0] bits in the ADC_CFGR2 register. It can range from 2x to 256x. The division coefficient M consists of a right bit shift up to 8 bits.

It is configured through the OVSS[3:0] bits in the ADC_CFGR2 register.

For code example, refer to

A.8.15: Oversampling code example .

The summation unit can yield a result up to 20 bits (256 x 12-bit), which is first shifted right.

The upper bits of the result are then truncated, keeping only the 16 least significant bits rounded to the nearest value using the least significant bits left apart by the shifting, before being finally transferred into the ADC_DR data register.

If the intermediate result after the shifting exceeds 16 bits, the upper bits of the result are simply truncated.

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Raw 20-bit data

Analog-to-digital converter (ADC)

Figure 51. 20-bit to 16-bit result truncation

19 15 11 7 3 0

Shifting

15 0

Truncation and rounding

MS31928V2

The

Figure 52

gives a numerical example of the processing, from a raw 20-bit accumulated data to the final 16-bit result.

Figure 52. Numerical example with 5-bits shift and rounding

19 15 11 7 3

Raw 20-bit data:

3 B 7 D 7

1 D B F

Final result after 5-bits shift and rounding to nearest

MS31929V1

The

Table 60 below gives the data format for the various N and M combination, for a raw

conversion data equal to 0xFFF.

16x

32x

64x

128x

256x

Table 60. Maximum output results vs N and M. Grayed values indicates truncation

Oversa mpling ratio

Max

Raw data

No-shift

OVSS =

0000

1-bit shift

OVSS =

0001

2-bit shift

OVSS =

0010

3-bit shift

OVSS =

0011

4-bit shift

OVSS =

0100

5-bit shift

OVSS =

0101

6-bit shift

OVSS =

0110

7-bit shift

OVSS =

0111

8-bit shift

OVSS =

1000

0x1FFE 0x1FFE 0x0FFF 0x0800 0x0400 0x0200 0x0100 0x0080 0x0040 0x0020

0x3FFC 0x3FFC 0x1FFE 0x0FFF 0x0800 0x0400 0x0200 0x0100 0x0080 0x0040

0x7FF8 0x7FF8 0x3FFC 0x1FFE 0x0FFF 0x0800 0x0400 0x0200 0x0100 0x0080

0xFFF0 0xFFF0 0x7FF8 0x3FFC 0x1FFE 0x0FFF 0x0800 0x0400 0x0200 0x0100

0x1FFE0 0xFFE0 0xFFF0 0x7FF8 0x3FFC 0x1FFE 0x0FFF 0x0800 0x0400 0x0200

0x3FFC0 0xFFC0 0xFFE0 0xFFF0 0x7FF8 0x3FFC 0x1FFE 0x0FFF 0x0800 0x0400

0x7FF80 0xFF80 0xFFC0 0xFFE0 0xFFF0 0x7FF8 0x3FFC 0x1FFE 0x0FFF 0x0800

0xFFF00 0xFF00 0xFF80 0xFFC0 0xFFE0 0xFFF0 0x7FF8 0x3FFC 0x1FFE 0x0FFF

The conversion timings in oversampled mode do not change compared to standard conversion mode: the sample time is maintained equal during the whole oversampling

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CONV

= N x (t

SMPL

+ t

SAR

). The flags features are raised as following:

• the end of the sampling phase (EOSMP) is set after each sampling phase

• the end of conversion (EOC) occurs once every N conversions, when the oversampled result is available

• the end of sequence (EOCSEQ) occurs once the sequence of oversampled data is completed (i.e. after N x sequence length conversions total)

Note:

In oversampling mode, most of the ADC operating modes are available:

• Single or continuous mode conversions, forward or backward scanned sequences

• ADC conversions start either by software or with triggers

• ADC stop during a conversion (abort)

• Data read via CPU or DMA with overrun detection

• Low-power modes (WAIT, AUTOFF)

• Programmable resolution: in this case, the reduced conversion values (as per RES[1:0] bits in ADC_CFGR1 register) are accumulated, truncated, rounded and shifted in the same way as 12-bit conversions are

The alignment mode is not available when working with oversampled data. The ALIGN bit in

ADC_CFGR1 is ignored and the data are always provided right-aligned.

Note:

The analog watchdog functionality is available (AWDSGL, AWDEN bits), with the following differences:

• the RES[1:0] bits are ignored, comparison is always done on using the full 12-bits values HT[11:0] and LT[11:0]

• the comparison is performed on the most significant 12 bits of the 16 bits oversampled results ADC_DR[15:4]

Care must be taken when using high shifting values. This reduces the comparison range.

For instance, if the oversampled result is shifted by 4 bits thus yielding a 12-bit data rightaligned, the affective analog watchdog comparison can only be performed on 8 bits. The comparison is done between ADC_DR[11:4] and HT[7:0] / LT[[7:0], and HT[11:8] / LT[11:8] must be kept reset.

The averager can also be used for basic filtering purposes. Although not a very efficient filter

(slow roll-off and limited stop band attenuation), it can be used as a notch filter to reject constant parasitic frequencies (typically coming from the mains or from a switched mode power supply). For this purpose, a specific discontinuous mode can be enabled with TOVS bit in ADC_CFGR2, to be able to have an oversampling frequency defined by a user and independent from the conversion time itself.

Figure 53

below shows how conversions are started in response to triggers in discontinuous mode.

If the TOVS bit is set, the content of the DISCEN bit is ignored and considered as 1.

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Figure 53. Triggered oversampling mode (TOVS bit = 1)

Trigger Trigger

CONT = 0

(DISCEN = 1)*

TOVS = 0

Ch(N)

Trigger Trigger Trigger

EOC flag set

Trigger Trigger Trigger Trigger

CONT = 0

(DISCEN = 1)*

TOVS = 1

Ch(N)

EOC flag set

(DISCEN = 1)*: DISCEN bit is forced to 1 by software when TOVS bit is set

MS33700V1

13.9 Internal reference voltage

The internal voltage reference (V REFINT ) provides a stable (bandgap) voltage output for the

ADC. V REFINT is internally connected to the ADC V

[17] input channel. The precise voltage of V REFINT is individually measured for each part by ST during production test and stored in the system memory area. It is accessible in read-only mode.

Figure 54

shows the block diagram of connection between the internal voltage reference and the ADC.

VREFEN bit must be set to enable the conversion of ADC V

[17] (V

REFINT

During the manufacturing process, the calibration data of the internal voltage reference are stored in the system memory area. The user application can then read them and use them to improve the accuracy of the internal reference. Refer to the electrical characteristics section of the device datasheet for additional information.

Main features

• Linearity: ±2 °C max., precision depending on calibration

Figure 54. V

REFINT

channel block diagram

Internal power block

VREFEN control bit

ADC

REFINT

ADC V

[17] converted data

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Note:

RM0451

Calculating the actual V

DDA

voltage using the internal reference voltage

The V

DDA

power supply voltage applied to the device may be subject to variation or not precisely known. The embedded internal voltage reference (V

REFINT

) and its calibration data, acquired by the ADC during the manufacturing process at V

DDA_Charac evaluate the actual V

DDA

voltage level.

, can be used to

The following formula gives the actual V

DDA

voltage supplying the device:

DDA

= V

DDA_Charac

x VREFINT_CAL / VREFINT_DATA

Where:

• V

DDA_Charac

is the value of V

DDA

voltage characterized at V

REFINT manufacturing process. It is specified in the device datasheet.

during the

• VREFINT_CAL is the VREFINT calibration value

• VREFINT_DATA is the actual VREFINT output value converted by ADC

Converting a supply-relative ADC measurement to an absolute voltage value

The ADC is designed to deliver a digital value corresponding to the ratio between the analog power supply and the voltage applied on the converted channel. For most application use cases, it is necessary to convert this ratio into a voltage independent of V

DDA applications where V

DDA the following formula to get this absolute value:

. For

is known and ADC converted values are right-aligned you can use

CHANNELx

DDA

FULL_SCALE

× ADC_DATA x

For applications where V

DDA reference and V

DDA

actual V

DDA

value is not known, you must use the internal voltage

can be replaced by the expression provided in Section : Calculating the

voltage using the internal reference voltage

, resulting in the following formula:

CHANNELx

DDA_Charac

× x

Where:

• V

DDA_Charac

is the value of V

DDA

voltage characterized at V

REFINT manufacturing process. It is specified in the device datasheet.

during the

• VREFINT_CAL is the VREFINT calibration value

• ADC_DATA x

is the value measured by the ADC on channelx (right-aligned)

• VREFINT_DATA is the actual VREFINT output value converted by the ADC

• full_SCALE is the maximum digital value of the ADC output. For example with 12-bit resolution, it is 2 12 - 1 = 4095 or with 8-bit resolution, 2 8 - 1 = 255.

If ADC measurements are done using an output format other than 12 bit right-aligned, all the parameters must first be converted to a compatible format before the calculation is done.

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An interrupt can be generated by any of the following events:

• End Of Calibration (EOCAL flag)

• ADC power-up, when the ADC is ready (ADRDY flag)

• End of any conversion (EOC flag)

• End of a sequence of conversions (EOS flag)

• When an analog watchdog detection occurs (AWD flag)

• When the end of sampling phase occurs (EOSMP flag)

• when a data overrun occurs (OVR flag)

Separate interrupt enable bits are available for flexibility.

Table 61. ADC interrupts

Interrupt event Event flag

End Of Calibration

ADC ready

End of conversion

End of sequence of conversions

Analog watchdog status bit is set

End of sampling phase

Overrun

EOCAL

ADRDY

EOC

EOS

AWD

EOSMP

OVR

Enable control bit

EOCALIE

ADRDYIE

EOCIE

EOSIE

AWDIE

EOSMPIE

OVRIE

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Refer to Section 1.2

for a list of abbreviations used in register descriptions.

13.11.1 ADC interrupt and status register (ADC_ISR)

Address offset: 0x00

Reset value: 0x0000 0000

Res.

12 11 10

Res.

EOCAL Res.

rc_w1

Res.

AWD rc_w1

Res.

4 3 2 1 0

OVR EOS EOC EOSMP ADRDY rc_w1 rc_w1 rc_w1 rc_w1 rc_w1

Bits 31:13 Reserved, must be kept at reset value.

Bit 12 Reserved, must be kept at reset value.

Bit 11 EOCAL : End Of Calibration flag

This bit is set by hardware when calibration is complete. It is cleared by software writing 1 to it.

0: Calibration is not complete

1: Calibration is complete

Bit 10 Reserved, must be kept at reset value.

Bits 9:8 Reserved, must be kept at reset value.

Bit 7 AWD : Analog watchdog flag

This bit is set by hardware when the converted voltage crosses the values programmed in ADC_TR register. It is cleared by software by programming it to 1.

0: No analog watchdog event occurred (or the flag event was already acknowledged and cleared by software)

1: Analog watchdog event occurred

Bits 6:5 Reserved, must be kept at reset value.

Bit 4 OVR : ADC overrun

This bit is set by hardware when an overrun occurs, meaning that a new conversion has complete while the EOC flag was already set. It is cleared by software writing 1 to it.

0: No overrun occurred (or the flag event was already acknowledged and cleared by software)

1: Overrun has occurred

Bit 3 EOS : End of sequence flag

This bit is set by hardware at the end of the conversion of a sequence of channels selected by the

CHSEL bits. It is cleared by software writing 1 to it.

0: Conversion sequence not complete (or the flag event was already acknowledged and cleared by software)

1: Conversion sequence complete

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Bit 2 EOC : End of conversion flag

This bit is set by hardware at the end of each conversion of a channel when a new data result is available in the ADC_DR register. It is cleared by software writing 1 to it or by reading the ADC_DR register.

0: Channel conversion not complete (or the flag event was already acknowledged and cleared by software)

1: Channel conversion complete

Bit 1 EOSMP : End of sampling flag

This bit is set by hardware during the conversion, at the end of the sampling phase.It is cleared by software by programming it to ‘1’.

0: Not at the end of the sampling phase (or the flag event was already acknowledged and cleared by software)

1: End of sampling phase reached

Bit 0 ADRDY : ADC ready

This bit is set by hardware after the ADC has been enabled (ADEN = 1) and when the ADC reaches a state where it is ready to accept conversion requests.

It is cleared by software writing 1 to it.

0: ADC not yet ready to start conversion (or the flag event was already acknowledged and cleared by software)

1: ADC is ready to start conversion

13.11.2 ADC interrupt enable register (ADC_IER)

Address offset: 0x04

Reset value: 0x0000 0000

Res.

EOCAL

IE rw

Res.

8 7 6

Res.

AWDIE Res.

5 4

Res.

OVRIE EOSIE EOCIE rw

3 rw

2 rw

1 0

EOSMP

ADRDY

IE rw rw

Bits 31:13 Reserved, must be kept at reset value.

Bit 12 Reserved, must be kept at reset value.

Bit 11 EOCALIE : End of calibration interrupt enable

This bit is set and cleared by software to enable/disable the end of calibration interrupt.

0: End of calibration interrupt disabled

1: End of calibration interrupt enabled

Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing).

Bit 10 Reserved, must be kept at reset value.

Bits 9:8 Reserved, must be kept at reset value.

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Bit 7 AWDIE : Analog watchdog interrupt enable

This bit is set and cleared by software to enable/disable the analog watchdog interrupt.

0: Analog watchdog interrupt disabled

1: Analog watchdog interrupt enabled

Note: The Software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing).

Bits 6:5 Reserved, must be kept at reset value.

Bit 4 OVRIE : Overrun interrupt enable

This bit is set and cleared by software to enable/disable the overrun interrupt.

0: Overrun interrupt disabled

1: Overrun interrupt enabled. An interrupt is generated when the OVR bit is set.

Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing).

Bit 3 EOSIE : End of conversion sequence interrupt enable

This bit is set and cleared by software to enable/disable the end of sequence of conversions interrupt.

0: EOS interrupt disabled

1: EOS interrupt enabled. An interrupt is generated when the EOS bit is set.

Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing).

Bit 2 EOCIE : End of conversion interrupt enable

This bit is set and cleared by software to enable/disable the end of conversion interrupt.

0: EOC interrupt disabled

1: EOC interrupt enabled. An interrupt is generated when the EOC bit is set.

Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing).

Bit 1 EOSMPIE : End of sampling flag interrupt enable

This bit is set and cleared by software to enable/disable the end of the sampling phase interrupt.

0: EOSMP interrupt disabled.

1: EOSMP interrupt enabled. An interrupt is generated when the EOSMP bit is set.

Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing).

Bit 0 ADRDYIE : ADC ready interrupt enable

This bit is set and cleared by software to enable/disable the ADC Ready interrupt.

0: ADRDY interrupt disabled.

1: ADRDY interrupt enabled. An interrupt is generated when the ADRDY bit is set.

Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing).

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13.11.3 ADC control register (ADC_CR)

Address offset: 0x08

Reset value: 0x0000 0000

31 30

ADCAL Res.

Res.

ADVR

EGEN rw

Res.

5 4 3

Res.

ADSTP Res.

ADSTA

RT rs

ADDIS ADEN rs

0 rs

Bit 31 ADCAL : ADC calibration

This bit is set by software to start the calibration of the ADC.

It is cleared by hardware after calibration is complete.

0: Calibration complete

1: Write 1 to calibrate the ADC. Read at 1 means that a calibration is in progress.

Note: The software is allowed to set ADCAL only when the ADC is disabled (ADCAL = 0,

ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).

The software is allowed to update the calibration factor by writing ADC_CALFACT only when

ADEN = 1 and ADSTART = 0 (ADC enabled and no conversion is ongoing).

Bits 30:29 Reserved, must be kept at reset value.

Bit 28 ADVREGEN : ADC Voltage Regulator Enable

This bit can be set:

– by software, to enable the ADC internal voltage regulator.

– by hardware, when launching the calibration (setting ADCAL = 1) or when enabling the ADC (setting

ADEN = 1)

It is cleared by software to disable the voltage regulator. It can be cleared only if ADEN is cleared.

0: ADC voltage regulator disabled

1: ADC voltage regulator enabled

Note: The software can program this bit field only when the ADC is disabled (ADCAL = 0,

ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).

Bits 27:5 Reserved, must be kept at reset value.

Bit 4 ADSTP : ADC stop conversion command

This bit is set by software to stop and discard an ongoing conversion (ADSTP Command).

It is cleared by hardware when the conversion is effectively discarded and the ADC is ready to accept a new start conversion command.

0: No ADC stop conversion command ongoing

1: Write 1 to stop the ADC. Read 1 means that an ADSTP command is in progress.

Note: Setting ADSTP to ‘1’ is only effective when ADSTART = 1 and ADDIS = 0 (ADC is enabled and may be converting and there is no pending request to disable the ADC)

Bit 3 Reserved, must be kept at reset value.

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Bit 2 ADSTART : ADC start conversion command

This bit is set by software to start ADC conversion. Depending on the EXTEN [1:0] configuration bits, a conversion either starts immediately (software trigger configuration) or once a hardware trigger event occurs (hardware trigger configuration).

It is cleared by hardware:

– In single conversion mode (CONT = 0, DISCEN = 0), when software trigger is selected

(EXTEN = 00): at the assertion of the end of Conversion Sequence (EOS) flag.

– In discontinuous conversion mode(CONT = 0, DISCEN = 1), when the software trigger is selected

(EXTEN = 00): at the assertion of the end of Conversion (EOC) flag.

– In all other cases: after the execution of the ADSTP command, at the same time as the ADSTP bit is cleared by hardware.

0: No ADC conversion is ongoing.

1: Write 1 to start the ADC. Read 1 means that the ADC is operating and may be converting.

Note: The software is allowed to set ADSTART only when ADEN = 1 and ADDIS = 0 (ADC is enabled and there is no pending request to disable the ADC).

Bit 1 ADDIS : ADC disable command

This bit is set by software to disable the ADC (ADDIS command) and put it into power-down state

(OFF state).

It is cleared by hardware once the ADC is effectively disabled (ADEN is also cleared by hardware at this time).

0: No ADDIS command ongoing

1: Write 1 to disable the ADC. Read 1 means that an ADDIS command is in progress.

Note: Setting ADDIS to ‘1’ is only effective when ADEN = 1 and ADSTART = 0 (which ensures that no conversion is ongoing)

Bit 0 ADEN : ADC enable command

This bit is set by software to enable the ADC. The ADC is effectively ready to operate once the

ADRDY flag has been set.

It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS command.

0: ADC is disabled (OFF state)

1: Write 1 to enable the ADC.

Note: The software is allowed to set ADEN only when all bits of ADC_CR registers are 0 (ADCAL = 0,

ADSTP = 0, ADSTART = 0, ADDIS = 0 and ADEN = 0)

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RM0451 Analog-to-digital converter (ADC)

Address offset: 0x0C

Reset value: 0x0000 0000

The software is allowed to program ADC_CFGR1 only when ADEN is cleared in ADC_CR.

Res.

30 rw

29 rw

AWDCH[4:0]

27 rw

AUTOFF WAIT CONT OVRMOD rw rw rw rw rw

26 rw

EXTEN[1:0] rw rw

Res.

24 23 22 21 20 19 18

Res.

AWDEN AWDSGL Res.

Res.

8 rw

7 rw

6 5 4 3 rw

EXTSEL[2:0] rw rw

ALIGN rw

RES[1:0] rw rw

Res.

SCAND

IR rw

DMAC

FG rw

DISCEN rw

DMAEN rw

Bit 31 Reserved, must be kept at reset value.

Bits 30:26 AWDCH[4:0] : Analog watchdog channel selection

These bits are set and cleared by software. They select the input channel to be guarded by the analog watchdog.

00000: ADC analog input Channel 0 monitored by AWD

00001: ADC analog input Channel 1 monitored by AWD

.....

10001: ADC analog input Channel 17 monitored by AWD

Others: Reserved

Note: The channel selected by the AWDCH[4:0] bits must be also set into the CHSELR register.

The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing).The software is allowed to write this bit only when ADEN bit is cleared.

Bits 25:24 Reserved, must be kept at reset value.

Bit 23 AWDEN : Analog watchdog enable

This bit is set and cleared by software.

0: Analog watchdog disabled

1: Analog watchdog enabled

Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing).The software is allowed to write this bit only when ADEN bit is cleared.

Bit 22 AWDSGL : Enable the watchdog on a single channel or on all channels

This bit is set and cleared by software to enable the analog watchdog on the channel identified by the AWDCH[4:0] bits or on all the channels

0: Analog watchdog enabled on all channels

1: Analog watchdog enabled on a single channel

Bits 21:17 Reserved, must be kept at reset value.

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Bit 16 DISCEN : Discontinuous mode

This bit is set and cleared by software to enable/disable discontinuous mode.

0: Discontinuous mode disabled

1: Discontinuous mode enabled

Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCEN = 1 and CONT = 1.

The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing).The software is allowed to write this bit only when ADEN bit is cleared.

Bit 15 AUTOFF : Auto-off mode

This bit is set and cleared by software to enable/disable auto-off mode.

0: Auto-off mode disabled

1: Auto-off mode enabled

Bit 14 WAIT : Wait conversion mode

This bit is set and cleared by software to enable/disable wait conversion mode.

0: Wait conversion mode off

1: Wait conversion mode on

Bit 13 CONT : Single / continuous conversion mode

This bit is set and cleared by software. If it is set, conversion takes place continuously until it is cleared.

0: Single conversion mode

1: Continuous conversion mode

Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCEN = 1 and CONT = 1.

The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing).The software is allowed to write this bit only when ADEN bit is cleared.

Bit 12 OVRMOD : Overrun management mode

This bit is set and cleared by software and configure the way data overruns are managed.

0: ADC_DR register is preserved with the old data when an overrun is detected.

1: ADC_DR register is overwritten with the last conversion result when an overrun is detected.

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Bits 11:10 EXTEN[1:0] : External trigger enable and polarity selection

These bits are set and cleared by software to select the external trigger polarity and enable the trigger.

00: Hardware trigger detection disabled (conversions can be started by software)

01: Hardware trigger detection on the rising edge

10: Hardware trigger detection on the falling edge

11: Hardware trigger detection on both the rising and falling edges

Bit 9 Reserved, must be kept at reset value.

Bits 8:6 EXTSEL[2:0] : External trigger selection

These bits select the external event used to trigger the start of conversion (refer to Table 54:

External triggers

for details):

000: TRG0

001: TRG1

010: TRG2

011: TRG3

100: TRG4

101: TRG5

110: TRG6

111: TRG7

Bit 5 ALIGN : Data alignment

This bit is set and cleared by software to select right or left alignment. Refer to

Figure 41:

Data alignment and resolution (oversampling disabled: OVSE = 0) on page 271

0: Right alignment

1: Left alignment

Bits 4:3 RES[1:0] : Data resolution

These bits are written by software to select the resolution of the conversion.

00: 12 bits

01: 10 bits

10: 8 bits

11: 6 bits

Note: The software is allowed to write these bits only when ADEN is cleared.

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Bit 2 SCANDIR : Scan sequence direction

This bit is set and cleared by software to select the direction in which the channels is scanned in the sequence.

0: Upward scan (from CHSEL0 to CHSEL17)

1: Backward scan (from CHSEL17 to CHSEL0)

Bit 1 DMACFG : Direct memory access configuration

This bit is set and cleared by software to select between two DMA modes of operation and is effective only when DMAEN = 1.

0: DMA one shot mode selected

1: DMA circular mode selected

For more details, refer to

Section 13.5.5: Managing converted data using the DMA on page 272

Bit 0 DMAEN : Direct memory access enable

This bit is set and cleared by software to enable the generation of DMA requests. This allows the DMA controller to be used to manage automatically the converted data. For more details, refer to

Section 13.5.5: Managing converted data using the DMA on page 272 .

0: DMA disabled

1: DMA enabled

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Address offset: 0x10

Reset value: 0x0000 0000

The software is allowed to program ADC_CFGR2 only when ADEN is cleared in ADC_CR.

31 30

CKMODE[1:0] rw

15 rw

Res.

TOVS rw

Res.

7 6

OVSS[3:0] rw rw

Res.

4 rw

OVSR[2:0] rw

2 rw

Res.

1 0

Res.

OVSE rw rw rw

Bits 31:30 CKMODE[1:0]: ADC clock mode

These bits are set and cleared by software to define how the analog ADC is clocked:

00: ADCCLK (Asynchronous clock mode), generated at product level (refer to RCC section)

01: PCLK/2 (Synchronous clock mode)

10: PCLK/4 (Synchronous clock mode)

In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of a conversion.

Note: The software is allowed to write these bits only when the ADC is disabled (ADCAL = 0,

ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).

Bits 29:10 Reserved, must be kept at reset value.

Bit 9 TOVS : Triggered Oversampling

This bit is set and cleared by software.

0: All oversampled conversions for a channel are done consecutively after a trigger

1: Each oversampled conversion for a channel needs a trigger

Bits 8:5 OVSS[3:0] : Oversampling shift

This bit is set and cleared by software.

0000: No shift

0001: Shift 1-bit

0010: Shift 2-bits

0011: Shift 3-bits

0100: Shift 4-bits

0101: Shift 5-bits

0110: Shift 6-bits

0111: Shift 7-bits

1000: Shift 8-bits

Others: Reserved

Note: he software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing).The software is allowed to write this bit only when ADEN bit is cleared.

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Bits 4:2 OVSR[2:0] : Oversampling ratio

This bit filed defines the number of oversampling ratio.

000: 2x

001: 4x

010: 8x

011: 16x

100: 32x

101: 64x

110: 128x

111: 256x

Bit 1 Reserved, must be kept at reset value.

Bit 0 OVSE : Oversampler Enable

This bit is set and cleared by software.

0: Oversampler disabled

1: Oversampler enabled

13.11.6 ADC sampling time register (ADC_SMPR)

Address offset: 0x14

Reset value: 0x0000 0000

Res.

2 rw

SMP[2:0] rw

0 rw

Bits 31:3 Reserved, must be kept at reset value.

Bits 2:0 SMP[2:0]: Sampling time selection

These bits are written by software to select the sampling time that applies to all channels.

000: 1.5 ADC clock cycles

001: 3.5 ADC clock cycles

010: 7.5 ADC clock cycles

011: 12.5 ADC clock cycles

100: 19.5 ADC clock cycles

101: 39.5 ADC clock cycles

110: 79.5 ADC clock cycles

111: 160.5 ADC clock cycles

Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).

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Address offset: 0x20

Reset value: 0x0FFF 0000

Res.

27 rw

26 rw

25 rw

24 rw

23 rw

HT[11:0]

21 rw

6 rw

5 rw

LT[11:0] rw

20 rw

19 rw

18 rw

17 rw

16 rw

0 rw rw rw rw rw rw rw rw rw rw

Bits 31:28 Reserved, must be kept at reset value.

Bits 27:16 HT[11:0] : Analog watchdog higher threshold

These bits are written by software to define the higher threshold for the analog watchdog. Refer to

Section 13.7: Analog window watchdog (AWDEN, AWDSGL, AWDCH, ADC_TR) on page 276

Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).

Bits 15:12 Reserved, must be kept at reset value.

Bits 11:0 LT[11:0] : Analog watchdog lower threshold

These bits are written by software to define the lower threshold for the analog watchdog.

Refer to Section 13.7: Analog window watchdog (AWDEN, AWDSGL, AWDCH, ADC_TR) on page 276 .

Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).

13.11.8 ADC channel selection register (ADC_CHSELR)

Address offset: 0x28

Reset value: 0x0000 0000

Res.

CHSEL

15 rw

CHSEL

14 rw

CHSEL

13 rw

CHSEL

12 rw

CHSEL

11 rw

CHSEL

10 rw

CHSEL

9 rw

CHSEL

8 rw

Res.

Res

CHSEL

7 rw

CHSEL

6 rw

CHSEL

5 rw

CHSEL

4 rw

CHSEL

3 rw

CHSEL

2 rw

CHSEL

17 rw

CHSEL

16 rw

CHSEL

1 rw

CHSEL

0 rw

RM0451 Rev 3 297/784

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Analog-to-digital converter (ADC) RM0451

Bits 31:18 Reserved, must be kept at reset value.

Bits 17:0 CHSELx : Channel-x selection

These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to

Figure 33: ADC connectivity

for ADC inputs connected to external channels and internal sources.

0: Input Channel-x is not selected for conversion

1: Input Channel-x is selected for conversion

Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).

13.11.9 ADC data register (ADC_DR)

Address offset: 0x40

Reset value: 0x0000 0000

Res.

15 14 13 12 11 10 9 8 7

DATA[15:0] r r

6 5 4 3 2 1 0 r r

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 DATA[15:0] : Converted data

These bits are read-only. They contain the conversion result from the last converted channel. The data are left- or right-aligned as shown in

Figure 41: Data alignment and resolution (oversampling disabled:

OVSE = 0) on page 271

Just after a calibration is complete, DATA[6:0] contains the calibration factor.

r r r r r r r r r r r r

Res.

Address offset: 0xB4

Reset value: 0x0000 0000

Res.

1 0 15

Res.

6 rw

5 rw

4 3 2 rw

CALFACT[6:0] rw rw rw rw

298/784 RM0451 Rev 3

RM0451 Analog-to-digital converter (ADC)

Bits 31:7 Reserved, must be kept at reset value.

Bits 6:0 CALFACT[6:0] : Calibration factor

These bits are written by hardware or by software.

– Once a single-ended inputs calibration is complete, they are updated by hardware with the calibration factors.

– Software can write these bits with a new calibration factor. If the new calibration factor is different from the current one stored into the analog ADC, it is then applied once a new single-ended conversion is launched.

– Just after a calibration is complete, DATA[6:0] contains the calibration factor.

Note: Software can write these bits only when ADEN=1 and ADSTART=0 (ADC is enabled and no calibration is ongoing and no conversion is ongoing).

Res.

Address offset: 0x308

Reset value: 0x0000 0000

Res.

26 25 24

Res.

LFMEN Res.

Res.

VREF

EN rw

Res.

21 rw

Res.

20 19

PRESC[3:0] rw

Res.

18 17

Res.

Bits 31:26 Reserved, must be kept at reset value.

Bit 25 LFMEN : Low Frequency Mode enable

This bit is set and cleared by software to enable/disable the Low Frequency Mode.

It is mandatory to enable this mode the user selects an ADC clock frequency lower than 3.5 MHz

0: Low Frequency Mode disabled

1: Low Frequency Mode enabled

Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing.

Bit 24 Reserved, must be kept at reset value.

Bit 23 Reserved, must be kept at reset value.

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Analog-to-digital converter (ADC) RM0451

Bit 22 VREFEN : V

REFINT

enable

This bit is set and cleared by software to enable/disable the V

REFINT

0: V

REFINT

1: V

REFINT

disabled

enabled

Note: Software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).

Bits 21:18 PRESC[3:0]: ADC prescaler

Set and cleared by software to select the frequency of the clock to the ADC.

0000: input ADC clock not divided

0001: input ADC clock divided by 2

0010: input ADC clock divided by 4

0011: input ADC clock divided by 6

0100: input ADC clock divided by 8

0101: input ADC clock divided by 10

0110: input ADC clock divided by 12

0111: input ADC clock divided by 16

1000: input ADC clock divided by 32

1001: input ADC clock divided by 64

1010: input ADC clock divided by 128

1011: input ADC clock divided by 256

Other: Reserved

Note: Software is allowed to write these bits only when the ADC is disabled (ADCAL = 0,

ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).

Bits 17:0 Reserved, must be kept at reset value.

13.12 ADC register map

The following table summarizes the ADC registers.

Table 62. ADC register map and reset values

Offset Register

0x00

0x04

ADC_ISR

Reset value

ADC_IER

Reset value

0x08

ADC_CR

Reset value 0 0

AWDCH[4:0]

0x0C

ADC_CFGR1

Reset value 0 0 0 0 0 0 0

0 0 0 0 0

0 0 0 0 0 0 0

RES

[1:0]

0 0 0

EXTSEL

[2:0]

0 0 0 0 0 0 0 0 0

300/784 RM0451 Rev 3

RM0451

Offset Register

Analog-to-digital converter (ADC)

Table 62. ADC register map and reset values (continued)

0x10

ADC_CFGR2

0x14

0x18

0x1C

0x20

0x24

Reset value

ADC_SMPR

Reset value

Reserved

ADC_TR

Reset value

Reserved

0 0

Reserved

HT[11:0]

1 1 1 1 1 1 1 1 1 1 1 1

Reserved

0 0 0 0 0 0 0 0 0 0

SMP

[2:0]

0 0 0

LT[11:0]

0 0 0 0 0 0 0 0 0 0 0 0

0x28

ADC_CHSELR

Reset value

0x2C

0x30

0x34

0x38

0x3C

0x40

Reserved

...

0xB4

...

ADC_DR

Reset value

Reserved

ADC_CALFACT

Reset value

Reserved

0x308

ADC_CCR

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Reserved

DATA[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Reserved

CALFACT[6:0]

0 0 0 0 0 0 0

Reserved

Reset value 0 0 0 0 0 0

Refer to Section 2.2 on page 39

for the register boundary addresses.

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General-purpose timer (TIM2)

14 General-purpose timer (TIM2)

RM0451

The general-purpose timer consists of a 16-bit auto-reload counter driven by a programmable prescaler.

It may be used for a variety of purposes, including measuring the pulse lengths of input signals ( input capture ) or generating output waveforms ( output compare and PWM ).

Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the RCC clock controller prescalers.

14.2 TIM2 main features

General-purpose TIMx timer features include:

• 16-bit (TIM2) up, down, up/down auto-reload counter.

• 16-bit programmable prescaler used to divide (also “on the fly”) the counter clock frequency by any factor between 1 and 65535.

• Up to 4 independent channels for:

– Input capture

– Output compare

– PWM generation (Edge- and Center-aligned modes)

– One-pulse mode output

• Synchronization circuit to control the timer with external signals and to interconnect several timers.

• Interrupt/DMA generation on the following events:

– Update: counter overflow/underflow, counter initialization (by software or internal/external trigger)

– Trigger event (counter start, stop, initialization or count by internal/external trigger)

– Input capture

– Output compare

• Supports incremental (quadrature) encoder and hall-sensor circuitry for positioning purposes

• Trigger input for external clock or cycle-by-cycle current management

302/784 RM0451 Rev 3

RM0451 General-purpose timer (TIM2)

Figure 55. General-purpose timer block diagram

TIMx_ETR

Internal clock (CK_INT)

TIMxCLK from RCC

ETR

ITR0

ITR1

ITR2

ITR3

Polarity selection & edge detector & prescaler

ETRP

Input filter

ITR

TRC

TI1F_ED

ETRF

Trigger controller

TRGO to other timers to DAC/ADC

TGI

TRGI

Slave controller mode

Reset, enable, up, count

TIMx_CH1

TIMx_CH2

TIMx_CH3

TIMx_CH4

XOR

TI1

TI2

TI3

TI4

TI1FP1

TI2FP2

Encoder interface

Input filter & edge detector

Auto-reload register

CK_PSC

TI1FP1

TI1FP2

IC1

PSC prescaler

Prescaler

Stop, clear or up/down

CK_CNT

CC1I

IC1PS

+/CNT counter

CC1I

Capture/Compare 1 register

OC1REF

TRC

TI2FP1

TI2FP2

TRC

CC2I

IC2

Prescaler

IC2PS

Capture/Compare 2 register

CC2I

OC2REF

CC3I

TI3FP3

TI3FP4

IC3

Prescaler

IC3PS

CC3I

Capture/Compare 3 register

OC3REF

TRC

TI4FP3

TI4FP4

TRC

CC4I

IC4

Prescaler

IC4PS

Capture/Compare 4 register

CC4I

OC4REF

ETRF

Output control

OC1

TIMx_CH1

Output control

OC2

OC3

OC4

TIMx_CH2

TIMx_CH3

TIMx_CH4

Notes:

Reg

Preload registers transferred to active registers on U event according to control bit

Event

Interrupt & DMA output

MS19673V1

RM0451 Rev 3 303/784

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General-purpose timer (TIM2)

14.3 TIM2 functional description

RM0451

The main block of the programmable timer is a 16-bit with its related auto-reload register.

The counter can count up, down or both up and down but also down or both up and down.

The counter clock can be divided by a prescaler.

The counter, the auto-reload register and the prescaler register can be written or read by software. This is true even when the counter is running.

The time-base unit includes:

• Counter Register (TIMx_CNT)

• Prescaler Register (TIMx_PSC):

• Auto-Reload Register (TIMx_ARR)

The auto-reload register is preloaded. Writing to or reading from the auto-reload register accesses the preload register. The content of the preload register are transferred into the shadow register permanently or at each update event (UEV), depending on the auto-reload preload enable bit (ARPE) in TIMx_CR1 register. The update event is sent when the counter reaches the overflow (or underflow when downcounting) and if the UDIS bit equals 0 in the

TIMx_CR1 register. It can also be generated by software. The generation of the update event is described in detail for each configuration.

The counter is clocked by the prescaler output CK_CNT, which is enabled only when the counter enable bit (CEN) in TIMx_CR1 register is set (refer also to the slave mode controller description to get more details on counter enabling).

Note that the actual counter enable signal CNT_EN is set 1 clock cycle after CEN.

Prescaler description

The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It is based on a 16-bit counter controlled through a 16-bit/32-bit register (in the TIMx_PSC register). It can be changed on the fly as this control register is buffered. The new prescaler ratio is taken into account at the next update event.

Figure 56

and

Figure 14.3.2

give some examples of the counter behavior when the

prescaler ratio is changed on the fly:

304/784 RM0451 Rev 3

RM0451 General-purpose timer (TIM2)

Figure 56. Counter timing diagram with prescaler division change from 1 to 2

CK_PSC

CEN

Timerclock = CK_CNT

Counter register

Update event (UEV)

Prescaler control register

F7 F8 F9 FA FB

Write a new value in TIMx_PSC

Prescaler buffer

FC 00 01

02 03

Prescaler counter

0 0 1 0 1 0 1 0 1

MS31076V2

Figure 57. Counter timing diagram with prescaler division change from 1 to 4

CK_PSC

CEN

Timerclock = CK_CNT

Counter register

Update event (UEV)

F7 F8 F9

Prescaler control register

Write a new value in TIMx_PSC

Prescaler buffer

Prescaler counter

FA FB FC 00

0 1 2 3 0 1 2 3

MS31077V2

RM0451 Rev 3 305/784

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General-purpose timer (TIM2) RM0451

Upcounting mode

In upcounting mode, the counter counts from 0 to the auto-reload value (content of the

TIMx_ARR register), then restarts from 0 and generates a counter overflow event.

An Update event can be generated at each counter overflow or by setting the UG bit in the

TIMx_EGR register (by software or by using the slave mode controller).

The UEV event can be disabled by software by setting the UDIS bit in TIMx_CR1 register.

This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until the UDIS bit has been written to 0. However, the counter restarts from 0, as well as the counter of the prescaler (but the prescale rate does not change). In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or DMA request is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event.

When an update event occurs, all the registers are updated and the update flag (UIF bit in

TIMx_SR register) is set (depending on the URS bit):

• The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register)

• The auto-reload shadow register is updated with the preload value (TIMx_ARR)

The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR=0x36.

Figure 58. Counter timing diagram, internal clock divided by 1

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 31 32 33 34 35 36 00 01 02 03 04 05 06 07

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31078V2

306/784 RM0451 Rev 3

RM0451 General-purpose timer (TIM2)

Figure 59. Counter timing diagram, internal clock divided by 2

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

0034 0035 0036 0000 0001 0002 0003

Figure 60. Counter timing diagram, internal clock divided by 4

MS31079V2

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

0035 0036 0000 0001

MS31080V2

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General-purpose timer (TIM2)

Figure 61. Counter timing diagram, internal clock divided by N

RM0451

CK_PSC

Timerclock = CK_CNT

Counter register 1F 20 00

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31081V2

Figure 62. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded)

CK_PSC

CEN

Timerclock = CK_CNT

Counter register

Counter overflow

31 32 33 34 35 36 00 01 02 03 04 05 06 07

Update event (UEV)

Update interrupt flag

(UIF)

Auto-reload preload register

Write a new value in TIMx_ARR

MS31082V2

308/784 RM0451 Rev 3

RM0451 General-purpose timer (TIM2)

Figure 63. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded)

CK_PSC

CEN

Timerclock = CK_CNT

Counter register F0 F1 F2 F3 F4 F5 00 01 02 03 04 05 06 07

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

Auto-reload preload register

F5 36

Auto-reload shadow register

F5 36

Write a new value in TIMx_ARR

MS31083V2

Downcounting mode

In downcounting mode, the counter counts from the auto-reload value (content of the

TIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a counter underflow event.

An Update event can be generate at each counter underflow or by setting the UG bit in the

TIMx_EGR register (by software or by using the slave mode controller)

The UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until UDIS bit has been written to 0.

However, the counter restarts from the current auto-reload value, whereas the counter of the prescaler restarts from 0 (but the prescale rate doesn’t change).

In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the

UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or

DMA request is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event.

When an update event occurs, all the registers are updated and the update flag (UIF bit in

TIMx_SR register) is set (depending on the URS bit):

• The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register).

• The auto-reload active register is updated with the preload value (content of the

TIMx_ARR register). Note that the auto-reload is updated before the counter is reloaded, so that the next period is the expected one.

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General-purpose timer (TIM2) RM0451

The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR=0x36.

Figure 64. Counter timing diagram, internal clock divided by 1

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 05 04 03 02 01 00 36 35 34 33 32 31 30 2F

Counter underflow

(cnt_udf)

Update event (UEV)

Update interrupt flag

(UIF)

MS31184V1

Figure 65. Counter timing diagram, internal clock divided by 2

310/784

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register

Counter underflow

Update event (UEV)

Update interrupt flag

(UIF)

0002 0001 0000 0036 0035 0034 0033

MS31185V1

RM0451 Rev 3

RM0451 General-purpose timer (TIM2)

Figure 66. Counter timing diagram, internal clock divided by 4

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register

Counter underflow

Update event (UEV)

Update interrupt flag

(UIF)

0001 0000 0000 0001

Figure 67. Counter timing diagram, internal clock divided by N

CK_PSC

Timerclock = CK_CNT

Counter register 20 1F 00 36

MS31186V1

Counter underflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31187V1

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General-purpose timer (TIM2) RM0451

Figure 68. Counter timing diagram, Update event when repetition counter is not used

CK_PSC

CEN

Timerclock = CK_CNT

Counter register

Counter underflow

05 04 03 02 01 00 36 35 34 33 32 31 30 2F

Update event (UEV)

Update interrupt flag

(UIF)

Auto-reload preload register

FF 36

Write a new value in TIMx_ARR

MS31188V1

Center-aligned mode (up/down counting)

In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the

TIMx_ARR register) – 1, generates a counter overflow event, then counts from the autoreload value down to 1 and generates a counter underflow event. Then it restarts counting from 0.

Center-aligned mode is active when the CMS bits in TIMx_CR1 register are not equal to

'00'. The Output compare interrupt flag of channels configured in output is set when: the counter counts down (Center aligned mode 1, CMS = "01"), the counter counts up (Center aligned mode 2, CMS = "10") the counter counts up and down (Center aligned mode 3,

CMS = "11").

In this mode, the direction bit (DIR from TIMx_CR1 register) cannot be written. It is updated by hardware and gives the current direction of the counter.

The update event can be generated at each counter overflow and at each counter underflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller) also generates an update event. In this case, the counter restarts counting from

0, as well as the counter of the prescaler.

However, the counter continues counting up and down, based on the current auto-reload value.

In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the

UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or

312/784 RM0451 Rev 3

RM0451 General-purpose timer (TIM2)

DMA request is sent). This is to avoid generating both update and capture interrupt when clearing the counter on the capture event.

When an update event occurs, all the registers are updated and the update flag (UIF bit in

TIMx_SR register) is set (depending on the URS bit):

• The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register).

• The auto-reload active register is updated with the preload value (content of the

TIMx_ARR register). Note that if the update source is a counter overflow, the autoreload is updated before the counter is reloaded, so that the next period is the expected one (the counter is loaded with the new value).

The following figures show some examples of the counter behavior for different clock frequencies.

Figure 69. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6

CK_PSC

CEN

Timerclock = CK_CNT

Counter register

Counter underflow

Counter overflow

04 03 02 01 00 01 02 03 04 05 06 05 04 03

Update event (UEV)

Update interrupt flag

(UIF)

1. Here, center-aligned mode 1 is used (for more details refer to Section 14.4.1: TIMx control register 1

(TIMx_CR1) on page 346 ).

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General-purpose timer (TIM2)

Figure 70. Counter timing diagram, internal clock divided by 2

RM0451

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 0003 0002 0001 0000 0001 0002 0003

Counter underflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31190V1

Figure 71. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 0034 0035

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

Note: Here, center_aligned mode 2 or 3 is updated with an UIF on overflow

1. Center-aligned mode 2 or 3 is used with an UIF on overflow.

0036 0035

MS31191V1

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RM0451 General-purpose timer (TIM2)

Figure 72. Counter timing diagram, internal clock divided by N

CK_PSC

Timerclock = CK_CNT

Counter register 20 1F 01 00

Counter underflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31192V1

Figure 73. Counter timing diagram, Update event with ARPE=1 (counter underflow)

CK_PSC

CEN

Timerclock = CK_CNT

Counter register

06 05 04 03 02 01 00

Counter underflow

Update event (UEV)

Update interrupt flag

(UIF)

Auto-reload preload register

Write a new value in TIMx_ARR

Auto-reload active register

01 02 03 04 05 06 07

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General-purpose timer (TIM2) RM0451

Figure 74. Counter timing diagram, Update event with ARPE=1 (counter overflow)

CK_PSC

CEN

Timer clock = CK_CNT

Counter register F7 F8 F9 FA FB FC 36 35 34 33 32 31 30 2F

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

Auto-reload preload register

Write a new value in TIMx_ARR

Auto-reload active register

MS31194V1

The counter clock can be provided by the following clock sources:

• Internal clock (CK_INT)

• External clock mode1: external input pin (TIx)

• External clock mode2: external trigger input (ETR)

•

Internal trigger inputs (ITRx): using one timer as prescaler for another timer. Refer to :

Using one timer as prescaler for another timer on page 339

for more details.

Internal clock source (CK_INT)

If the slave mode controller is disabled (SMS=000 in the TIMx_SMCR register), then the

CEN, DIR (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed only by software (except UG which remains cleared automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal clock CK_INT.

Figure 75

shows the behavior of the control circuit and the upcounter in normal mode, without prescaler.

316/784 RM0451 Rev 3

RM0451 General-purpose timer (TIM2)

Figure 75. Control circuit in normal mode, internal clock divided by 1

Internal clock

CEN=CNT_EN

CNT_INIT

Counter clock = CK_CNT = CK_PSC

Counter register 31 3 2 33 34 35 36 00 01 02 03 04 05 06 07

MS31085V2

External clock source mode 1

This mode is selected when SMS=111 in the TIMx_SMCR register.

The counter can count at each rising or falling edge on a selected input.

Figure 76. TI2 external clock connection example

TIMx_SMCR

TS[2:0]

TI2

Filter

ICF[3:0]

TIMx_CCMR1

Edge detector

TI2F_Rising

TI2F_Falling

CC2P

TIMx_CCER

ITRx

TI1_ED

TI1FP1

TI2FP2

ETRF

0xx

100

101

110

111 or

TI2F or

TI1F or

TRGI

ETRF

CK_INT

(internal clock)

Encoder mode

External clock mode 1

External clock mode 2

Internal clock mode

CK_PSC

ECE SMS[2:0]

TIMx_SMCR

MS31196V1

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General-purpose timer (TIM2)

Note:

RM0451

For example, to configure the upcounter to count in response to a rising edge on the TI2 input, use the following procedure:

Configure channel 2 to detect rising edges on the TI2 input by writing CC2S= ‘01 in the

TIMx_CCMR1 register.

2. Configure the input filter duration by writing the IC2F[3:0] bits in the TIMx_CCMR1 register (if no filter is needed, keep IC2F=0000).

The capture prescaler is not used for triggering, so it does not need to be configured.

3. Select rising edge polarity by writing CC2P=0 and CC2NP=0 in the TIMx_CCER register.

4. Configure the timer in external clock mode 1 by writing SMS=111 in the TIMx_SMCR register.

5. Select TI2 as the input source by writing TS=110 in the TIMx_SMCR register.

6. Enable the counter by writing CEN=1 in the TIMx_CR1 register.

For code example, refer to

A.9.1: Upcounter on TI2 rising edge code example

When a rising edge occurs on TI2, the counter counts once and the TIF flag is set.

The delay between the rising edge on TI2 and the actual clock of the counter is due to the resynchronization circuit on TI2 input.

Figure 77. Control circuit in external clock mode 1

TI2

CNT_EN

Counter clock = CK_CNT = CK_PSC

Counter register

TIF

34 35 36

Write TIF=0

MS31087V2

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RM0451 General-purpose timer (TIM2)

External clock source mode 2

This mode is selected by writing ECE=1 in the TIMx_SMCR register.

The counter can count at each rising or falling edge on the external trigger input ETR.

Figure 78

gives an overview of the external trigger input block.

Figure 78. External trigger input block

ETR pin

ETR

Divider

/1, /2, /4, /8

ETP

TIMx_SMCR

ETPS[1:0]

TIMx_SMCR

ETRP f

DTS

Filter downcounter

ETF[3:0]

TIMx_SMCR or

TI2F or

TI1F or

Encoder mode

TRGI

ETRF

CK_INT

(internal clock)

External clock mode 1

External clock mode 2

Internal clock mode

CK_PSC

ECE SMS[2:0]

TIMx_SMCR

MS33116V1

For example, to configure the upcounter to count each 2 rising edges on ETR, use the following procedure:

As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register.

2. Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register

3. Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR register

4. Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register.

5. Enable the counter by writing CEN=1 in the TIMx_CR1 register.

For code example, refer to

A.9.2: Up counter on each 2 ETR rising edges code example

The counter counts once each 2 ETR rising edges.

The delay between the rising edge on ETR and the actual clock of the counter is due to the resynchronization circuit on the ETRP signal.

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Figure 79. Control circuit in external clock mode 2 f

CK_INT

CNT_EN

ETR

ETRP

ETRF

Counter clock =

CK_INT =CK_PSC

Counter register 34 35

RM0451

MS33111V2

Each Capture/Compare channel is built around a capture/compare register (including a shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and an output stage (with comparator and output control).

The following figure gives an overview of one Capture/Compare channel.

The input stage samples the corresponding TIx input to generate a filtered signal TIxF.

Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be used as trigger input by the slave mode controller or as the capture command. It is prescaled before the capture register (ICxPS).

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RM0451 General-purpose timer (TIM2)

Figure 80. Capture/compare channel (example: channel 1 input stage)

TI1F_ED

To the slave mode controller

TI1 f

DTS

Filter downcounter

TI1F

ICF[3:0]

TIMx_CCMR1

Edge detector

TI1F_Rising

TI1F_Falling

CC1P/CC1NP

TIMx_CCER

TI2F_Rising

(from channel 2)

TI2F_Falling

(from channel 2)

0 TI1FP1

TI2FP1

IC1 Divider

/1, /2, /4, /8

IC1PS

TRC

(from slave mode controller)

CC1S[1:0] ICPS[1:0]

TIMx_CCMR1

CC1E

TIMx_CCER

MS33115V1

The output stage generates an intermediate waveform which is then used for reference:

OCxRef (active high). The polarity acts at the end of the chain.

Figure 81. Capture/compare channel 1 main circuit

APB Bus

Read CCR1H

Read CCR1L

CC1S[1]

CC1S[0]

IC1PS

CC1E

CC1G

TIMx_EGR

MCU-peripheral interface

8 8

S write CCR1H write_in_progress read_in_progress

Input mode

Capture/compare preload register capture_transfer

Capture/compare shadow register

Capture compare_transfer

Comparator

Output mode

CNT>CCR1

R write CCR1L

CC1S[1]

CC1S[0]

OC1PE

UEV

(from time base unit)

OC1PE

TIMx_CCMR1

Counter

CNT=CCR1

MS33144V1

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Figure 82. Output stage of capture/compare channel (channel 1)

TIMx_SMCR

OCCS

To the master mode controller

OCREF_CLR 0

ETRF 1 ocref_clr_int

CNT > CCR1

CNT = CCR1

Output mode controller

OC1REF

Output enable circuit

OC1

CC1P

TIMx_CCER CC1E TIM1_CCER

OC1M[2:0]

TIMx_CCMR1

MS33146V1

The capture/compare block is made of one preload register and one shadow register. Write and read always access the preload register.

In capture mode, captures are actually done in the shadow register, which is copied into the preload register.

In compare mode, the content of the preload register is copied into the shadow register which is compared to the counter.

In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the value of the counter after a transition detected by the corresponding ICx signal. When a capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or a DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was already high, then the over-capture flag CCxOF (TIMx_SR register) is set. CCxIF can be cleared by software by writing it to 0 or by reading the captured data stored in the

TIMx_CCRx register. CCxOF is cleared when it is written with 0.

The following example shows how to capture the counter value in TIMx_CCR1 when TI1 input rises. To do this, use the following procedure:

Select the active input: TIMx_CCR1 must be linked to the TI1 input, so write the CC1S bits to 01 in the TIMx_CCMR1 register. As soon as CC1S becomes different from 00, the channel is configured in input and the TIMx_CCR1 register becomes read-only.

2. Program the appropriate input filter duration in relation with the signal connected to the timer (when the input is one of the TIx (ICxF bits in the TIMx_CCMRx register). Let’s imagine that, when toggling, the input signal is not stable during at must 5 internal clock cycles. We must program a filter duration longer than these 5 clock cycles. We can validate a transition on TI1 when 8 consecutive samples with the new level have been

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RM0451

Note:

General-purpose timer (TIM2) detected (sampled at f

DTS

TIMx_CCMR1 register.

frequency). Then write IC1F bits to 0011 in the

3. Select the edge of the active transition on the TI1 channel by writing the CC1P and

CC1NP bits to 00 in the TIMx_CCER register (rising edge in this case).

4. Program the input prescaler. In our example, we wish the capture to be performed at each valid transition, so the prescaler is disabled (write IC1PS bits to 00 in the

TIMx_CCMR1 register).

5. Enable capture from the counter into the capture register by setting the CC1E bit in the

TIMx_CCER register.

6. If needed, enable the related interrupt request by setting the CC1IE bit in the

TIMx_DIER register, and/or the DMA request by setting the CC1DE bit in the

TIMx_DIER register.

For code example, refer to

A.9.3: Input capture configuration code example

When an input capture occurs:

• The TIMx_CCR1 register gets the value of the counter on the active transition.

• CC1IF flag is set (interrupt flag). CC1OF is also set if at least two consecutive captures occurred whereas the flag was not cleared.

• An interrupt is generated depending on the CC1IE bit.

• A DMA request is generated depending on the CC1DE bit.

For code example, refer to

A.9.4: Input capture data management code example

In order to handle the overcapture, it is recommended to read the data before the overcapture flag. This is to avoid missing an overcapture which could happen after reading the flag and before reading the data.

IC interrupt and/or DMA requests can be generated by software by setting the corresponding CCxG bit in the TIMx_EGR register.

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14.3.6 PWM input mode

This mode is a particular case of input capture mode. The procedure is the same except:

• Two ICx signals are mapped on the same TIx input.

• These 2 ICx signals are active on edges with opposite polarity.

• One of the two TIxFP signals is selected as trigger input and the slave mode controller is configured in reset mode.

For example, one can measure the period (in TIMx_CCR1 register) and the duty cycle (in

TIMx_CCR2 register) of the PWM applied on TI1 using the following procedure (depending on CK_INT frequency and prescaler value):

Select the active input for TIMx_CCR1: write the CC1S bits to 01 in the TIMx_CCMR1 register (TI1 selected).

2. Select the active polarity for TI1FP1 (used both for capture in TIMx_CCR1 and counter clear): write the CC1P to ‘0’ and the CC1NP bit to ‘0’ (active on rising edge).

3. Select the active input for TIMx_CCR2: write the CC2S bits to 10 in the TIMx_CCMR1 register (TI1 selected).

4. Select the active polarity for TI1FP2 (used for capture in TIMx_CCR2): write the CC2P bit to ‘1’ and the CC2NP bit to ’0’(active on falling edge).

5. Select the valid trigger input: write the TS bits to 101 in the TIMx_SMCR register

(TI1FP1 selected).

6. Configure the slave mode controller in reset mode: write the SMS bits to 100 in the

TIMx_SMCR register.

7. Enable the captures: write the CC1E and CC2E bits to ‘1 in the TIMx_CCER register.

For code example, refer to

A.9.5: PWM input configuration code example

Figure 83. PWM input mode timing

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RM0451 General-purpose timer (TIM2)

14.3.7 Forced output mode

In output mode (CCxS bits = 00 in the TIMx_CCMRx register), each output compare signal

(OCxREF and then OCx) can be forced to active or inactive level directly by software, independently of any comparison between the output compare register and the counter.

To force an output compare signal (OCxREF/OCx) to its active level, one just needs to write

101 in the OCxM bits in the corresponding TIMx_CCMRx register. Thus OCxREF is forced high (OCxREF is always active high) and OCx get opposite value to CCxP polarity bit.

e.g.: CCxP=0 (OCx active high) => OCx is forced to high level.

OCxREF signal can be forced low by writing the OCxM bits to 100 in the TIMx_CCMRx register.

Anyway, the comparison between the TIMx_CCRx shadow register and the counter is still performed and allows the flag to be set. Interrupt and DMA requests can be sent accordingly. This is described in the Output Compare Mode section.

14.3.8 Output compare mode

This function is used to control an output waveform or indicating when a period of time has elapsed.

When a match is found between the capture/compare register and the counter, the output compare function:

• Assigns the corresponding output pin to a programmable value defined by the output compare mode (OCxM bits in the TIMx_CCMRx register) and the output polarity (CCxP bit in the TIMx_CCER register). The output pin can keep its level (OCXM=000), be set active (OCxM=001), be set inactive (OCxM=010) or can toggle (OCxM=011) on match.

• Sets a flag in the interrupt status register (CCxIF bit in the TIMx_SR register).

• Generates an interrupt if the corresponding interrupt mask is set (CCXIE bit in the

TIMx_DIER register).

• Sends a DMA request if the corresponding enable bit is set (CCxDE bit in the

TIMx_DIER register, CCDS bit in the TIMx_CR2 register for the DMA request selection).

The TIMx_CCRx registers can be programmed with or without preload registers using the

OCxPE bit in the TIMx_CCMRx register.

In output compare mode, the update event UEV has no effect on OCxREF and OCx output.

The timing resolution is one count of the counter. Output compare mode can also be used to output a single pulse (in One-pulse mode).

Procedure:

Select the counter clock (internal, external, prescaler).

2. Write the desired data in the TIMx_ARR and TIMx_CCRx registers.

3. Set the CCxIE and/or CCxDE bits if an interrupt and/or a DMA request is to be generated.

4. Select the output mode. For example, one must write OCxM=011, OCxPE=0, CCxP=0 and CCxE=1 to toggle OCx output pin when CNT matches CCRx, CCRx preload is not used, OCx is enabled and active high.

5. Enable the counter by setting the CEN bit in the TIMx_CR1 register.

For code example, refer to

A.9.7: Output compare configuration code example

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The TIMx_CCRx register can be updated at any time by software to control the output waveform, provided that the preload register is not enabled (OCxPE=0, else TIMx_CCRx shadow register is updated only at the next update event UEV). An example is given in

Figure 84

Figure 84. Output compare mode, toggle on OC1.

Write B201h in the CC1R register

TIM1_CNT 0039

TIM1_CCR1

OC1REF= OC1

003A

003B B200

B201

Match detected on CCR1

Interrupt generated if enabled

MS31092V1

Pulse width modulation mode allows to generate a signal with a frequency determined by the value of the TIMx_ARR register and a duty cycle determined by the value of the

TIMx_CCRx register.

The PWM mode can be selected independently on each channel (one PWM per OCx output) by writing 110 (PWM mode 1) or ‘111 (PWM mode 2) in the OCxM bits in the

TIMx_CCMRx register. The corresponding preload register must be enabled by setting the

OCxPE bit in the TIMx_CCMRx register, and eventually the auto-reload preload register (in upcounting or center-aligned modes) by setting the ARPE bit in the TIMx_CR1 register.

As the preload registers are transferred to the shadow registers only when an update event occurs, before starting the counter, all registers must be initialized by setting the UG bit in the TIMx_EGR register.

OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register. It can be programmed as active high or active low. OCx output is enabled by the CCxE bit in the TIMx_CCER register. Refer to the TIMx_CCERx register description for more details.

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In PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine whether TIMx_CCRx ≤ TIMx_CNT or TIMx_CNT ≤ TIMx_CCRx (depending on the direction of the counter). However, to comply with the OCREF_CLR functionality (OCREF can be cleared by an external event through the ETR signal until the next PWM period), the

OCREF signal is asserted only:

• When the result of the comparison changes, or

• When the output compare mode (OCxM bits in TIMx_CCMRx register) switches from the “frozen” configuration (no comparison, OCxM=‘000) to one of the PWM modes

(OCxM=‘110 or ‘111).

This forces the PWM by software while the timer is running.

The timer is able to generate PWM in edge-aligned mode or center-aligned mode depending on the CMS bits in the TIMx_CR1 register.

PWM edge-aligned mode

Upcounting configuration

Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to Section :

Upcounting mode on page 306 .

In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is high as long as TIMx_CNT <TIMx_CCRx else it becomes low. If the compare value in

TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR) then OCxREF is held at ‘1.

If the compare value is 0 then OCxREF is held at ‘0. Figure 85

shows some edge-aligned

PWM waveforms in an example where TIMx_ARR=8.

For code example, refer to

A.9.8: Edge-aligned PWM configuration example

Figure 85. Edge-aligned PWM waveforms (ARR=8)

Counter register

CCRx=4

OCXREF

CCxIF

0 1 2 3 4 5 6 7 8 0 1

CCRx=8

OCXREF

CCxIF

CCRx>8

OCXREF ‘1’

CCxIF

CCRx=0

OCXREF ‘0’

CCxIF

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Downcounting configuration

Downcounting is active when DIR bit in TIMx_CR1 register is high. Refer to Section :

Downcounting mode on page 309

In PWM mode 1, the reference signal OCxREF is low as long as TIMx_CNT>TIMx_CCRx else it becomes high. If the compare value in TIMx_CCRx is greater than the auto-reload value in TIMx_ARR, then OCxREF is held at ‘1. 0% PWM is not possible in this mode.

PWM center-aligned mode

Center-aligned mode is active when the CMS bits in TIMx_CR1 register are different from

‘00 (all the remaining configurations having the same effect on the OCxREF/OCx signals).

The compare flag is set when the counter counts up, when it counts down or both when it counts up and down depending on the CMS bits configuration. The direction bit (DIR) in the

TIMx_CR1 register is updated by hardware and must not be changed by software. Refer to

Section : Center-aligned mode (up/down counting) on page 312

Figure 86

shows some center-aligned PWM waveforms in an example where:

• TIMx_ARR=8,

• PWM mode is the PWM mode 1,

• The flag is set when the counter counts down corresponding to the center-aligned mode 1 selected for CMS=01 in TIMx_CR1 register.

For code example, refer to

A.9.9: Center-aligned PWM configuration example .

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RM0451 General-purpose timer (TIM2)

Figure 86. Center-aligned PWM waveforms (ARR=8)

Counter register 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1

OCxREF

CCRx = 4

CCxIF

CMS=01

CMS=10

CMS=11

CCRx=7

OCxREF

CMS=10 or 11

CCxIF

CCRx=8

OCxREF

‘1’

CCxIF CMS=01

CMS=10

CMS=11

CCRx>8

OCxREF

‘1’

CCxIF

CMS=01

CMS=10

CMS=11

CCRx=0

OCxREF

‘0’

CCxIF CMS=01

CMS=10

CMS=11

AI14681b

Hints on using center-aligned mode:

• When starting in center-aligned mode, the current up-down configuration is used. It means that the counter counts up or down depending on the value written in the DIR bit in the TIMx_CR1 register. Moreover, the DIR and CMS bits must not be changed at the same time by the software.

• Writing to the counter while running in center-aligned mode is not recommended as it can lead to unexpected results. In particular:

– The direction is not updated if a value greater than the auto-reload value is written in the counter (TIMx_CNT>TIMx_ARR). For example, if the counter was counting up, it continues to count up.

– The direction is updated if 0 or the TIMx_ARR value is written in the counter but no

Update Event UEV is generated.

• The safest way to use center-aligned mode is to generate an update by software

(setting the UG bit in the TIMx_EGR register) just before starting the counter and not to write the counter while it is running.

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One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay.

Starting the counter can be controlled through the slave mode controller. Generating the waveform can be done in output compare mode or PWM mode. One-pulse mode is selected by setting the OPM bit in the TIMx_CR1 register. This makes the counter stop automatically at the next update event UEV.

A pulse can be correctly generated only if the compare value is different from the counter initial value. Before starting (when the timer is waiting for the trigger), the configuration must be:

• In upcounting: CNT<CCRx ≤ ARR (in particular, 0<CCRx),

• In downcounting: CNT>CCRx.

Figure 87. Example of one-pulse mode.

TI2

OC1REF

OC1

TIM1_ARR

TIM1_CCR1

0 t

DELAY t

PULSE t

MS31099V1

For example one may want to generate a positive pulse on OC1 with a length of t

PULSE after a delay of t

DELAY

as soon as a positive edge is detected on the TI2 input pin.

and

Let’s use TI2FP2 as trigger 1:

Map TI2FP2 on TI2 by writing CC2S=01 in the TIMx_CCMR1 register.

2. TI2FP2 must detect a rising edge, write CC2P=0 and CC2NP=’0’ in the TIMx_CCER register.

3. Configure TI2FP2 as trigger for the slave mode controller (TRGI) by writing TS=110 in the TIMx_SMCR register.

4. TI2FP2 is used to start the counter by writing SMS to ‘110 in the TIMx_SMCR register

(trigger mode).

For code example, refer to

A.9.16: One-Pulse mode code example .

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The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler).

• The t

DELAY is defined by the value written in the TIMx_CCR1 register.

• The t

PULSE

is defined by the difference between the auto-reload value and the compare value (TIMx_ARR - TIMx_CCR1+1).

• Let’s say one want to build a waveform with a transition from ‘0 to ‘1 when a compare match occurs and a transition from ‘1 to ‘0 when the counter reaches the auto-reload value. To do this PWM mode 2 must be enabled by writing OC1M=111 in the

TIMx_CCMR1 register. Optionally the preload registers can be enabled by writing

OC1PE=1 in the TIMx_CCMR1 register and ARPE in the TIMx_CR1 register. In this case one has to write the compare value in the TIMx_CCR1 register, the auto-reload value in the TIMx_ARR register, generate an update by setting the UG bit and wait for external trigger event on TI2. CC1P is written to ‘0 in this example.

In our example, the DIR and CMS bits in the TIMx_CR1 register should be low.

Since only 1 pulse (Single mode) is needed, a 1 must be written in the OPM bit in the

TIMx_CR1 register to stop the counter at the next update event (when the counter rolls over from the auto-reload value back to 0). When OPM bit in the TIMx_CR1 register is set to '0', so the Repetitive Mode is selected.

Particular case: OCx fast enable:

In One-pulse mode, the edge detection on TIx input set the CEN bit which enables the counter. Then the comparison between the counter and the compare value makes the output toggle. But several clock cycles are needed for these operations and it limits the minimum delay t

DELAY

min we can get.

If one wants to output a waveform with the minimum delay, the OCxFE bit can be set in the

TIMx_CCMRx register. Then OCxRef (and OCx) is forced in response to the stimulus, without taking in account the comparison. Its new level is the same as if a compare match had occurred. OCxFE acts only if the channel is configured in PWM1 or PWM2 mode.

For code example, refer to

A.9.16: One-Pulse mode code example .

The external trigger prescaler should be kept off: bits ETPS[1:0] in the TIMx_SMCR register are cleared to 00.

2. The external clock mode 2 must be disabled: bit ECE in the TIMx_SMCR register is cleared to 0.

3. The external trigger polarity (ETP) and the external trigger filter (ETF) can be configured according to the application’s needs.

For code example, refer to

A.9.10: ETR configuration to clear OCxREF code example

Figure 88

shows the behavior of the OCxREF signal when the ETRF input becomes high, for both values of the OCxCE enable bit. In this example, the timer TIMx is programmed in

PWM mode.

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Figure 88. Clearing TIMx OCxREF

Counter (CNT)

(CCRx)

ETRF

OCxREF

(OCxCE = ‘0’)

OCxREF

(OCxCE = ‘1’)

OCxREF_CLR becomes high

OCxREF_CLR still high

MS33105V1

1. In case of a PWM with a 100% duty cycle (if CCRx>ARR), OCxREF is enabled again at the next counter overflow.

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To select Encoder Interface mode write SMS=‘001 in the TIMx_SMCR register if the counter is counting on TI2 edges only, SMS=010 if it is counting on TI1 edges only and SMS=011 if it is counting on both TI1 and TI2 edges.

Select the TI1 and TI2 polarity by programming the CC1P and CC2P bits in the TIMx_CCER register. CC1NP and CC2NP must be kept cleared. When needed, the input filter can be programmed as well.

The two inputs TI1 and TI2 are used to interface to an incremental encoder. Refer to

Table 63 . The counter is clocked by each valid transition on TI1FP1 or TI2FP2 (TI1 and TI2

after input filter and polarity selection, TI1FP1=TI1 if not filtered and not inverted,

TI2FP2=TI2 if not filtered and not inverted) assuming that it is enabled (CEN bit in

TIMx_CR1 register written to ‘1). The sequence of transitions of the two inputs is evaluated and generates count pulses as well as the direction signal. Depending on the sequence the counter counts up or down, the DIR bit in the TIMx_CR1 register is modified by hardware accordingly. The DIR bit is calculated at each transition on any input (TI1 or TI2), whatever the counter is counting on TI1 only, TI2 only or both TI1 and TI2.

Encoder interface mode acts simply as an external clock with direction selection. This means that the counter just counts continuously between 0 and the auto-reload value in the

TIMx_ARR register (0 to ARR or ARR down to 0 depending on the direction). So the

TIMx_ARR must be configured before starting. In the same way, the capture, compare, prescaler, trigger output features continue to work as normal.

In this mode, the counter is modified automatically following the speed and the direction of the incremental encoder and its content, therefore, always represents the encoder’s

RM0451 Rev 3

RM0451 General-purpose timer (TIM2) position. The count direction correspond to the rotation direction of the connected sensor.

The table summarizes the possible combinations, assuming TI1 and TI2 do not switch at the same time.

Active edge

Counting on

TI1 only

Counting on

TI2 only

Counting on

TI1 and TI2

Table 63. Counting direction versus encoder signals

Level on opposite signal (TI1FP1 for

TI2, TI2FP2 for TI1)

TI1FP1 signal

Rising Falling

TI2FP2 signal

Rising Falling

High

Low

High

Low

High

Low

Down

No Count

Down

No Count

Down

No Count

Down

No Count

Down

An external incremental encoder can be connected directly to the MCU without external interface logic. However, comparators are normally be used to convert the encoder’s differential outputs to digital signals. This greatly increases noise immunity. The third encoder output which indicate the mechanical zero position, may be connected to an external interrupt input and trigger a counter reset.

Figure 89

gives an example of counter operation, showing count signal generation and direction control. It also shows how input jitter is compensated where both edges are selected. This might occur if the sensor is positioned near to one of the switching points. For this example we assume that the configuration is the following:

• CC1S= 01 (TIMx_CCMR1 register, TI1FP1 mapped on TI1)

• CC2S= 01 (TIMx_CCMR2 register, TI2FP2 mapped on TI2)

• CC1P=0, CC1NP = ‘0’ (TIMx_CCER register, TI1FP1 noninverted, TI1FP1=TI1)

• CC2P=0, CC2NP = ‘0’ (TIMx_CCER register, TI2FP2 noninverted, TI2FP2=TI2)

• SMS= 011 (TIMx_SMCR register, both inputs are active on both rising and falling edges)

• CEN= 1 (TIMx_CR1 register, Counter is enabled)

For code example, refer to

A.9.11: Encoder interface code example .

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Figure 89. Example of counter operation in encoder interface mode forward jitter backward jitter forward

TI1

TI2

RM0451

Counter up down up

MS33107V1

Figure 90

gives an example of counter behavior when TI1FP1 polarity is inverted (same configuration as above except CC1P=1).

Figure 90. Example of encoder interface mode with TI1FP1 polarity inverted forward jitter backward jitter forward

TI1

TI2

Counter down up down

MS33108V1

The timer, when configured in Encoder Interface mode provides information on the sensor’s current position. Dynamic information can be obtained (speed, acceleration, deceleration) by measuring the period between two encoder events using a second timer configured in capture mode. The output of the encoder which indicates the mechanical zero can be used for this purpose. Depending on the time between two events, the counter can also be read at regular times. This can be done by latching the counter value into a third input capture register if available (then the capture signal must be periodic and can be generated by another timer). when available, it is also possible to read its value through a DMA request generated by a Real-Time clock.

14.3.13 Timer input XOR function

The TI1S bit in the TIMx_CR2 register, allows the input filter of channel 1 to be connected to the output of a XOR gate, combining the three input pins TIMx_CH1 to TIMx_CH3.

The XOR output can be used with all the timer input functions such as trigger or input capture.

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14.3.14 Timers and external trigger synchronization

The TIMx Timers can be synchronized with an external trigger in several modes: Reset mode, Gated mode and Trigger mode.

Slave mode: Reset mode

The counter and its prescaler can be reinitialized in response to an event on a trigger input.

Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is generated. Then all the preloaded registers (TIMx_ARR, TIMx_CCRx) are updated.

In the following example, the upcounter is cleared in response to a rising edge on TI1 input:

• Configure the channel 1 to detect rising edges on TI1. Configure the input filter duration

(in this example, we do not need any filter, so we keep IC1F=0000). The capture prescaler is not used for triggering, so it does not need to be configured. The CC1S bits select the input capture source only, CC1S = 01 in the TIMx_CCMR1 register. Write

CC1P=0 and CC1NP=0 in TIMx_CCER register to validate the polarity (and detect rising edges only).

• Configure the timer in reset mode by writing SMS=100 in TIMx_SMCR register. Select

TI1 as the input source by writing TS=101 in TIMx_SMCR register.

• Start the counter by writing CEN=1 in the TIMx_CR1 register.

For code example, refer to

A.9.12: Reset mode code example .

The counter starts counting on the internal clock, then behaves normally until TI1 rising edge. When TI1 rises, the counter is cleared and restarts from 0. In the meantime, the trigger flag is set (TIF bit in the TIMx_SR register) and an interrupt request, or a DMA request can be sent if enabled (depending on the TIE and TDE bits in TIMx_DIER register).

The following figure shows this behavior when the auto-reload register TIMx_ARR=0x36.

The delay between the rising edge on TI1 and the actual reset of the counter is due to the resynchronization circuit on TI1 input.

Figure 91. Control circuit in reset mode

TI1

Counter clock = ck_cnt = ck_psc

Counter register

TIF

30 31 32 33 34 35 36 00 01 02 03 00 01 02 03

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Slave mode: Gated mode

The counter can be enabled depending on the level of a selected input.

In the following example, the upcounter counts only when TI1 input is low:

Configure the channel 1 to detect low levels on TI1. Configure the input filter duration

CC1P=1 and CC1NP=0 in TIMx_CCER register to validate the polarity (and detect low level only).

2. Configure the timer in gated mode by writing SMS=101 in TIMx_SMCR register. Select

TI1 as the input source by writing TS=101 in TIMx_SMCR register.

3. Enable the counter by writing CEN=1 in the TIMx_CR1 register (in gated mode, the counter doesn’t start if CEN=0, whatever is the trigger input level).

For code example, refer to

A.9.13: Gated mode code example .

The counter starts counting on the internal clock as long as TI1 is low and stops as soon as

TI1 becomes high. The TIF flag in the TIMx_SR register is set both when the counter starts or stops.

The delay between the rising edge on TI1 and the actual stop of the counter is due to the resynchronization circuit on TI1 input.

Figure 92. Control circuit in gated mode

TI1 cnt_en

Counter clock = ck_cnt = ck_psc

Counter register

TIF

30 31 32 33 34 35 36 37 38

Write TIF=0

MS31402V1

1. The configuration “CCxP=CCxNP=1” (detection of both rising and falling edges) does not have any effect in gated mode because gated mode acts on a level and not on an edge.

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Slave mode: Trigger mode

The counter can start in response to an event on a selected input.

In the following example, the upcounter starts in response to a rising edge on TI2 input:

Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration

(in this example, we do not need any filter, so we keep IC2F=0000). The capture prescaler is not used for triggering, so it does not need to be configured. CC2S bits are selecting the input capture source only, CC2S=01 in TIMx_CCMR1 register. Write

CC2P=1 and CC2NP=0 in TIMx_CCER register to validate the polarity (and detect low level only).

2. Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select

TI2 as the input source by writing TS=110 in TIMx_SMCR register.

For code example, refer to

A.9.14: Trigger mode code example

When a rising edge occurs on TI2, the counter starts counting on the internal clock and the

TIF flag is set.

The delay between the rising edge on TI2 and the actual start of the counter is due to the resynchronization circuit on TI2 input.

Figure 93. Control circuit in trigger mode

TI2 cnt_en

Counter clock = ck_cnt = ck_psc

Counter register

General-purpose timer (TIM2)

35 36 37 38

TIF

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Slave mode: External Clock mode 2 + trigger mode

The external clock mode 2 can be used in addition to another slave mode (except external clock mode 1 and encoder mode). In this case, the ETR signal is used as external clock input, and another input can be selected as trigger input when operating in reset mode, gated mode or trigger mode. It is recommended not to select ETR as TRGI through the TS bits of TIMx_SMCR register.

In the following example, the upcounter is incremented at each rising edge of the ETR signal as soon as a rising edge of TI1 occurs:

Configure the external trigger input circuit by programming the TIMx_SMCR register as follows:

– ETF = 0000: no filter

– ETPS=00: prescaler disabled

– ETP=0: detection of rising edges on ETR and ECE=1 to enable the external clock mode 2.

2. Configure the channel 1 as follows, to detect rising edges on TI:

– IC1F=0000: no filter.

– The capture prescaler is not used for triggering and does not need to be configured.

– CC1S=01in TIMx_CCMR1 register to select only the input capture source

– CC1P=0 and CC1NP=0 in TIMx_CCER register to validate the polarity (and detect rising edge only).

3. Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select

TI1 as the input source by writing TS=101 in TIMx_SMCR register.

For code example, refer to

A.9.15: External clock mode 2 + trigger mode code example .

A rising edge on TI1 enables the counter and sets the TIF flag. The counter then counts on

ETR rising edges.

The delay between the rising edge of the ETR signal and the actual reset of the counter is due to the resynchronization circuit on ETRP input.

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Figure 94. Control circuit in external clock mode 2 + trigger mode

TI1

CEN/CNT_EN

ETR

Counter clock = CK_CNT = CK_PSC

Counter register

TIF

34 35 36

MS33110V1

Note:

The TIMx timers are linked together internally for timer synchronization or chaining. When one Timer is configured in Master Mode, it can reset, start, stop or clock the counter of another Timer configured in Slave Mode.

Figure 95: Master/Slave timer example presents an overview of the trigger selection and the

master mode selection blocks.

The clock of the slave timer must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer.

Using one timer as prescaler for another timer

TIMx

Figure 95. Master/Slave timer example

TIMy

Clock

Prescaler

UEV

Counter

MMS

Master mode control

TRGO1

SMS

ITR1

Slave mode control

CK_PSC

Prescaler

Input trigger selection

Counter

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Note:

RM0451

For example, Timer x can be configured to act as a prescaler for Timer y. Refer to

Figure 95

To do this, follow the sequence below:

Configure Timer x in master mode so that it outputs a periodic trigger signal on each update event UEV. If MMS=010 is written in the TIMx_CR2 register, a rising edge is output on TRGO1 each time an update event is generated.

2. To connect the TRGO1 output of Timer x to Timer y, Timer y must be configured in slave mode using ITR1 as internal trigger. This is selected through the TS bits in the

TIMy_SMCR register (writing TS=000).

3. Then the slave mode controller must be put in external clock mode 1 (write SMS=111 in the TIMy_SMCR register). This causes Timer y to be clocked by the rising edge of the periodic Timer x trigger signal (which correspond to the timer x counter overflow).

4. Finally both timers must be enabled by setting their respective CEN bits (TIMx_CR1 register).

For code example, refer to

A.9.17: Timer prescaling another timer code example

If OCx is selected on Timer x as trigger output (MMS=1xx), its rising edge is used to clock the counter of timer y.

Using one timer to enable another timer

In this example, we control the enable of Timer y with the output compare 1 of Timer x.

Refer to Figure 95 for connections. Timer y counts on the divided internal clock only when

OC1REF of Timer x is high. Both counter clock frequencies are divided by 3 by the prescaler compared to CK_INT (f

CK_CNT

= f

CK_INT

/3).

Configure Timer x master mode to send its Output Compare 1 Reference (OC1REF) signal as trigger output (MMS=100 in the TIMx_CR2 register).

2. Configure the Timer x OC1REF waveform (TIMx_CCMR1 register).

3. Configure Timer y to get the input trigger from Timer x (TS=000 in the TIMy_SMCR register).

4. Configure Timer y in gated mode (SMS=101 in TIMy_SMCR register).

Timer writing ‘1 in the CEN bit (TIMy_CR1 register).

6. Start Timer x by writing ‘1 in the CEN bit (TIMx_CR1 register).

For code example, refer to

A.9.18: Timer enabling another timer code example .

The counter 2 clock is not synchronized with counter 1, this mode only affects the Timer y counter enable signal.

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Figure 96. Gating timer y with OC1REF of timer x

CK_INT

TIMERx-OC1REF

TIMERx-CNT

TIMERy-CNT

TIMERy-TIF

3045

FD FE FF

3046 3047

3048

Write TIF = 0

MS33137V1

In the example in Figure 96 , the Timer y counter and prescaler are not initialized before

being started. So they start counting from their current value. It is possible to start from a given value by resetting both timers before starting Timer x. Then any value can be written in the timer counters. The timers can easily be reset by software using the UG bit in the

TIMx_EGR registers.

In the next example, we synchronize Timer x and Timer y. Timer x is the master and starts from 0. Timer y is the slave and starts from 0xE7. The prescaler ratio is the same for both timers. Timer y stops when Timer x is disabled by writing ‘0 to the CEN bit in the TIMy_CR1 register:

Configure Timer x master mode to send its Output Compare 1 Reference (OC1REF) signal as trigger output (MMS=100 in the TIMx_CR2 register).

2. Configure the Timer x OC1REF waveform (TIMx_CCMR1 register).

3. Configure Timer y to get the input trigger from Timer x (TS=000 in the TIMy_SMCR register).

4. Configure Timer y in gated mode (SMS=101 in TIMy_SMCR register).

5. Reset Timer x by writing ‘1 in UG bit (TIMx_EGR register).

6. Reset Timer y by writing ‘1 in UG bit (TIMy_EGR register).

7. Initialize Timer y to 0xE7 by writing ‘0xE7’ in the timer y counter (TIMy_CNTL).

Timer writing ‘1 in the CEN bit (TIMy_CR1 register).

9. Start Timer x by writing ‘1 in the CEN bit (TIMx_CR1 register).

10. Stop Timer x by writing ‘0 in the CEN bit (TIMx_CR1 register).

For code example, refer to

A.9.19: Master and slave synchronization code example .

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Figure 97. Gating timer y with Enable of timer x

CK_INT

TIMERx-CEN=CNT_EN

TIMERx-CNT_INIT

TIMERx-CNT

75 00 01

TIMERy-CNT

TIMERy-CNT_INIT

TIMERy-write CNT

TIMERy-TIF

AB 00 E7 E8

RM0451

Write TIF = 0

MS33138V1

Using one timer to start another timer

In this example, we set the enable of Timer y with the update event of Timer x. Refer to

Figure 95

for connections. Timer y starts counting from its current value (which can be nonzero) on the divided internal clock as soon as the update event is generated by Timer x.

When Timer y receives the trigger signal its CEN bit is automatically set and the counter counts until we write ‘0 to the CEN bit in the TIM2_CR1 register. Both counter clock frequencies are divided by 3 by the prescaler compared to CK_INT (f

CK_CNT

= f

CK_INT

/3).

Configure Timer x master mode to send its Update Event (UEV) as trigger output

(MMS=010 in the TIMx_CR2 register).

2. Configure the Timer x period (TIMx_ARR registers).

3. Configure Timer y to get the input trigger from Timer x (TS=000 in the TIMy_SMCR register).

4. Configure Timer y in trigger mode (SMS=110 in TIMy_SMCR register).

5. Start Timer x by writing ‘1 in the CEN bit (TIMx_CR1 register).

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Figure 98. Triggering timer y with update of timer x

CK_INT

TIMERx-UEV

TIMERx-CNT

TIMERy-CNT

TIMERy-CEN=CNT_EN

TIMERy-TIF

FD FE

FF 00

Write TIF = 0

MS33139V1

As in the previous example, both counters can be initialized before starting counting.

Figure 99 shows the behavior with the same configuration as in Figure 98 but in trigger

mode instead of gated mode (SMS=110 in the TIMy_SMCR register).

Figure 99. Triggering timer y with Enable of timer x

CK_INT

TIMERx-CEN=CNT_EN

TIMERx-CNT_INIT

TIMERx-CNT

TIMERy-CNT

TIMERy-CNT_INIT

TIMERy write CNT

TIMERy-TIF

CD 00

Write TIF = 0

E9 EA

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Note:

RM0451

Starting 2 timers synchronously in response to an external trigger

In this example, we set the enable of timer x when its TI1 input rises, and the enable of

Timer y with the enable of Timer x. Refer to Figure 95 for connections. To ensure the

counters are aligned, Timer x must be configured in Master/Slave mode (slave with respect to TI1, master with respect to Timer y):

Configure Timer x master mode to send its Enable as trigger output (MMS=001 in the

TIMx_CR2 register).

2. Configure Timer x slave mode to get the input trigger from TI1 (TS=100 in the

TIMx_SMCR register).

3. Configure Timer x in trigger mode (SMS=110 in the TIMx_SMCR register).

4. Configure the Timer x in Master/Slave mode by writing MSM=1 (TIMx_SMCR register).

5. Configure Timer y to get the input trigger from Timer x (TS=000 in the TIMy_SMCR register).

6. Configure Timer y in trigger mode (SMS=110 in the TIMy_SMCR register).

For code example, refer to

A.9.20: Two timers synchronized by an external trigger code example .

When a rising edge occurs on TI1 (Timer x), both counters starts counting synchronously on the internal clock and both TIF flags are set.

In this example both timers are initialized before starting (by setting their respective UG bits). Both counters starts from 0, but an offset can easily be inserted between them by writing any of the counter registers (TIMx_CNT). One can see that the master/slave mode insert a delay between CNT_EN and CK_PSC on timer x.

Figure 100. Triggering timer x and y with timer x TI1 input

CK_INT

TIMERx-TI1

TIMERx-CEN=CNT_EN

TIMERx-CK_PSC

TIMERx-CNT

TIMERx-TIF

TIMERy-CEN=CNT_EN

TIMERy-CK_PSC

TIMERy-CNT

TIMERy-TIF

01 02 03 04 05 06 07 08 09

MS33141V1

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When the microcontroller enters debug mode (Cortex

-M0+ core - halted), the TIMx counter either continues to work normally or stops, depending on DBG_TIMx_STOP configuration

bit in DBG module. For more details, refer to Section 24.9.2: Debug support for timers, watchdog and I

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Refer to Section 1.2 on page 33 for a list of abbreviations used in register descriptions.

The 32-bit peripheral registers have to be written by words (32 bits). All other peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits).

14.4.1 TIMx control register 1 (TIMx_CR1)

Res.

Address offset: 0x00

Reset value: 0x0000

Res.

CKD[1:0]

8 rw rw

ARPE rw

6 5 rw

CMS rw

DIR rw

OPM rw

URS rw

UDIS rw

CEN rw

Bits 15:10 Reserved, must be kept at reset value.

Bits 9:8 CKD : Clock division

This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and sampling clock used by the digital filters (ETR, TIx),

00: t

DTS

= t

CK_INT

01: t

DTS

= 2 × t

CK_INT

10: t

DTS

= 4 × t

CK_INT

11: Reserved

Bit 7 ARPE : Auto-reload preload enable

0: TIMx_ARR register is not buffered

1: TIMx_ARR register is buffered

Bits 6:5 CMS : Center-aligned mode selection

00: Edge-aligned mode. The counter counts up or down depending on the direction bit

(DIR).

01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting down.

10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting up.

11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set both when the counter is counting up or down.

Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1)

Bit 4 DIR : Direction

0: Counter used as upcounter

1: Counter used as downcounter

Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode.

Bit 3 OPM : One-pulse mode

0: Counter is not stopped at update event

1: Counter stops counting at the next update event (clearing the bit CEN)

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Bit 2 URS : Update request source

This bit is set and cleared by software to select the UEV event sources.

0: Any of the following events generate an update interrupt or DMA request if enabled.

These events can be:

– Counter overflow/underflow

– Setting the UG bit

– Update generation through the slave mode controller

1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled.

Bit 1 UDIS : Update disable

This bit is set and cleared by software to enable/disable UEV event generation.

0: UEV enabled. The Update (UEV) event is generated by one of the following events:

– Counter overflow/underflow

– Setting the UG bit

– Update generation through the slave mode controller

Buffered registers are then loaded with their preload values.

1: UEV disabled. The Update event is not generated, shadow registers keep their value

(ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller.

Bit 0 CEN : Counter enable

0: Counter disabled

1: Counter enabled

Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware.

CEN is cleared automatically in one-pulse mode, when an update event occurs.

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14.4.2 TIMx control register 2 (TIMx_CR2)

Res.

Address offset: 0x04

Reset value: 0x0000

Res.

TI1S rw

6 rw

MMS[2:0] rw

4 rw

3 2

CCDS Res.

Res.

Bits 15:8 Reserved, must be kept at reset value.

Bit 7 TI1S : TI1 selection

0: The TIMx_CH1 pin is connected to TI1 input

1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination)

Bits 6:4 MMS : Master mode selection

These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows:

000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset.

001: Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode.

When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register).

010: Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer.

011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred.

(TRGO)

100: Compare - OC1REF signal is used as trigger output (TRGO)

101: Compare - OC2REF signal is used as trigger output (TRGO)

110: Compare - OC3REF signal is used as trigger output (TRGO)

111: Compare - OC4REF signal is used as trigger output (TRGO)

Note: The clock of the slave timer or ADC must be enabled prior to receiving events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer.

Bit 3 CCDS : Capture/compare DMA selection

0: CCx DMA request sent when CCx event occurs

1: CCx DMA requests sent when update event occurs

Bits 2:0 Reserved, must be kept at reset value.

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14.4.3 TIMx slave mode control register (TIMx_SMCR)

ETP rw

Address offset: 0x08

ECE rw

Reset value: 0x0000

13 12

ETPS[1:0]

11 rw rw rw

ETF[3:0]

9 rw rw

8 rw

MSM rw

6 rw

TS[2:0] rw

4 rw

Res.

2 rw

SMS[2:0] rw

0 rw

Bit 15 ETP : External trigger polarity

This bit selects whether ETR or ETR is used for trigger operations

0: ETR is noninverted, active at high level or rising edge

1: ETR is inverted, active at low level or falling edge

Bit 14 ECE : External clock enable

This bit enables External clock mode 2.

0: External clock mode 2 disabled

1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.

1: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=111).

2: It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to

ETRF in this case (TS bits must not be 111).

3: If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF.

Bits 13:12 ETPS : External trigger prescaler

External trigger signal ETRP frequency must be at most 1/4 of CK_INT frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks.

00: Prescaler OFF

01: ETRP frequency divided by 2

10: ETRP frequency divided by 4

11: ETRP frequency divided by 8

Bits 11:8 ETF[3:0] : External trigger filter

This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:

0000: No filter, sampling is done at f

DTS

0001: f

SAMPLING

CK_INT

0010: f

SAMPLING

0011: f

SAMPLING

0100: f

SAMPLING

0101: f

SAMPLING

0110: f

SAMPLING

CK_INT

DTS

, N=2

, N=4

, N=8

/2, N=6

/2, N=8

/4, N=6

/4, N=8 0111: f

SAMPLING

DTS

1000: f

SAMPLING

1001: f

SAMPLING

1010: f

SAMPLING

1011: f

SAMPLING

1100: f

SAMPLING

DTS

/8, N=6

/8, N=8

/16, N=5

/16, N=6

/16, N=8

/32, N=5 1101: f

SAMPLING

1110: f

SAMPLING

1111: f

SAMPLING

DTS

/32, N=6

/32, N=8

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Bit 7 MSM: Master/Slave mode

0: No action

1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

Bits 6:4 TS: Trigger selection

This bit-field selects the trigger input to be used to synchronize the counter.

000: Internal Trigger 0 (ITR0).

001: Internal Trigger 1 (ITR1).

010: Reserved

011: Reserved.

100: TI1 Edge Detector (TI1F_ED)

101: Filtered Timer Input 1 (TI1FP1)

110: Filtered Timer Input 2 (TI2FP2)

111: External Trigger input (ETRF)

See

Table 64: TIM2/TIM3 internal trigger connection on page 350

for more details on ITRx meaning for each Timer.

Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition.

Bit 3 Reserved, must be kept at ‘1’.

Bits 2:0 SMS: Slave mode selection

When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description.

000: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.

001: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.

010: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.

011: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.

100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.

101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.

110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.

111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.

Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=100).

Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal.

The clock of the slave timer must be enabled prior to receiving events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer."

Slave TIM

TIM2

Table 64. TIM2/TIM3 internal trigger connection

ITR0 (TS = 000) ITR1 (TS = 001)

TIM21 TIM22

RM0451 Rev 3

RM0451 General-purpose timer (TIM2)

14.4.4 TIMx DMA/Interrupt enable register (TIMx_DIER)

Address offset: 0x0C

Reset value: 0x0000

Res.

TDE rw

13 12 11 10 9 8

Res.

CC4DE CC3DE CC2DE CC1DE UDE rw rw rw rw rw

Res.

TIE rw

5 4 3 2 1

Res.

CC4IE CC3IE CC2IE CC1IE rw rw rw rw

UIE rw

Bit 15 Reserved, must be kept at reset value.

Bit 14 TDE : Trigger DMA request enable

0: Trigger DMA request disabled.

1: Trigger DMA request enabled.

Bit 13 Reserved, always read as 0

Bit 12 CC4DE : Capture/Compare 4 DMA request enable

0: CC4 DMA request disabled.

1: CC4 DMA request enabled.

Bit 11 CC3DE : Capture/Compare 3 DMA request enable

0: CC3 DMA request disabled.

1: CC3 DMA request enabled.

Bit 10 CC2DE : Capture/Compare 2 DMA request enable

0: CC2 DMA request disabled.

1: CC2 DMA request enabled.

Bit 9 CC1DE : Capture/Compare 1 DMA request enable

0: CC1 DMA request disabled.

1: CC1 DMA request enabled.

Bit 8 UDE : Update DMA request enable

0: Update DMA request disabled.

1: Update DMA request enabled.

Bit 7 Reserved, must be kept at reset value.

Bit 6 TIE : Trigger interrupt enable

0: Trigger interrupt disabled.

1: Trigger interrupt enabled.

Bit 5 Reserved, must be kept at reset value.

Bit 4 CC4IE : Capture/Compare 4 interrupt enable

0: CC4 interrupt disabled.

1: CC4 interrupt enabled.

Bit 3 CC3IE : Capture/Compare 3 interrupt enable

0: CC3 interrupt disabled

1: CC3 interrupt enabled

RM0451 Rev 3 351/784

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General-purpose timer (TIM2)

Bit 2 CC2IE : Capture/Compare 2 interrupt enable

0: CC2 interrupt disabled

1: CC2 interrupt enabled

Bit 1 CC1IE : Capture/Compare 1 interrupt enable

0: CC1 interrupt disabled

1: CC1 interrupt enabled

Bit 0 UIE : Update interrupt enable

0: Update interrupt disabled

1: Update interrupt enabled

RM0451

Res.

Address offset: 0x10

Reset value: 0x0000

13 12 11 10 9 8

Res.

CC4OF CC3OF CC2OF CC1OF Res.

rc_w0 rc_w0 rc_w0 rc_w0

Res.

TIF rc_w0

5 4 3 2 1

Res.

CC4IF CC3IF CC2IF CC1IF

UIF rc_w0 rc_w0 rc_w0 rc_w0 rc_w0

Bits 15:13 Reserved, must be kept at reset value.

Bit 12 CC4OF : Capture/Compare 4 overcapture flag refer to CC1OF description

Bit 11 CC3OF : Capture/Compare 3 overcapture flag refer to CC1OF description

Bit 10 CC2OF : Capture/compare 2 overcapture flag refer to CC1OF description

Bit 9 CC1OF : Capture/Compare 1 overcapture flag

This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to ‘0.

0: No overcapture has been detected

1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set

Bits 8:7 Reserved, must be kept at reset value.

Bit 6 TIF : Trigger interrupt flag

This flag is set by hardware on trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software.

0: No trigger event occurred

1: Trigger interrupt pending

Bit 5 Reserved, must be kept at reset value.

Bit 4 CC4IF : Capture/Compare 4 interrupt flag refer to CC1IF description

Bit 3 CC3IF : Capture/Compare 3 interrupt flag refer to CC1IF description

352/784 RM0451 Rev 3

RM0451 General-purpose timer (TIM2)

Bit 2 CC2IF : Capture/Compare 2 interrupt flag refer to CC1IF description

Bit 1 CC1IF : Capture/compare 1 interrupt flag

If channel CC1 is configured as output:

This flag is set by hardware when the counter matches the compare value, with some exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register description). It is cleared by software.

0: No match

1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register.

When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in upcounting and up/down-counting modes) or underflow

(in downcounting mode)

If channel CC1 is configured as input:

This bit is set by hardware on a capture. It is cleared by software or by reading the

TIMx_CCR1 register.

0: No input capture occurred

1: The counter value has been captured in TIMx_CCR1 register (An edge has been detected on IC1 which matches the selected polarity)

Bit 0 UIF : Update interrupt flag

″ This bit is set by hardware on an update event. It is cleared by software.

0: No update occurred.

1: Update interrupt pending. This bit is set by hardware when the registers are updated:

″

At overflow or underflow and if UDIS=0 in the TIMx_CR1 register.

When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register.

When CNT is reinitialized by a trigger event (refer to the synchro control register description), if URS=0 and UDIS=0 in the TIMx_CR1 register.

RM0451 Rev 3 353/784

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General-purpose timer (TIM2) RM0451

Res.

Address offset: 0x14

Reset value: 0x0000

Res.

TG w

5 4 3 2 1

Res.

CC4G CC3G CC2G CC1G w w w w

UG w

Bits 15:7 Reserved, must be kept at reset value.

Bit 6 TG : Trigger generation

This bit is set by software in order to generate an event, it is automatically cleared by hardware.

0: No action

1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

Bit 5 Reserved, must be kept at reset value.

Bit 4 CC4G : Capture/compare 4 generation refer to CC1G description

Bit 3 CC3G : Capture/compare 3 generation refer to CC1G description

Bit 2 CC2G : Capture/compare 2 generation refer to CC1G description

Bit 1 CC1G : Capture/compare 1 generation

This bit is set by software in order to generate an event, it is automatically cleared by hardware.

0: No action

1: A capture/compare event is generated on channel 1:

If channel CC1 is configured as output:

CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled.

If channel CC1 is configured as input:

The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the

CC1IF flag was already high.

Bit 0 UG : Update generation

This bit can be set by software, it is automatically cleared by hardware.

0: No action

1: Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (TIMx_ARR) if DIR=1 (downcounting).

354/784 RM0451 Rev 3

RM0451 General-purpose timer (TIM2)

14.4.7 TIMx capture/compare mode register 1 (TIMx_CCMR1)

OC2CE rw

Address offset: 0x18

Reset value: 0x0000

The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode. For a given bit,

OCxx describes its function when the channel is configured in output, ICxx describes its function when the channel is configured in input. So one must take care that the same bit can have a different meaning for the input stage and for the output stage.

14 13

OC2M[2:0]

IC2F[3:0] rw rw

12 rw

11 10

OC2PE OC2FE

IC2PSC[1:0] rw rw

CC2S[1:0] rw

8 rw

OC1CE rw

6 5

OC1M[2:0]

IC1F[3:0] rw rw

4 rw

3 2

OC1PE OC1FE

IC1PSC[1:0] rw rw

CC1S[1:0] rw

0 rw

Output compare mode

Bit 15 OC2CE: Output compare 2 clear enable

Bits 14:12 OC2M[2:0] : Output compare 2 mode

Bit 11 OC2PE : Output compare 2 preload enable

Bit 10 OC2FE : Output compare 2 fast enable

Bits 9:8 CC2S[1:0] : Capture/Compare 2 selection

This bit-field defines the direction of the channel (input/output) as well as the used input.

00: CC2 channel is configured as output

01: CC2 channel is configured as input, IC2 is mapped on TI2

10: CC2 channel is configured as input, IC2 is mapped on TI1

11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through the TS bit (TIMx_SMCR register)

Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER).

Bit 7 OC1CE: Output compare 1 clear enable

OC1CE: Output Compare 1 Clear Enable

0: OC1Ref is not affected by the ETRF input

1: OC1Ref is cleared as soon as a High level is detected on ETRF input

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General-purpose timer (TIM2) RM0451

Bits 6:4 OC1M : Output compare 1 mode

These bits define the behavior of the output reference signal OC1REF from which OC1 and

OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits.

000: Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing base).

001: Set channel 1 to active level on match. OC1REF signal is forced high when the counter

TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).

010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).

011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.

100: Force inactive level - OC1REF is forced low.

101: Force active level - OC1REF is forced high.

110: PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1 else inactive. In downcounting, channel 1 is inactive (OC1REF=‘0) as long as

TIMx_CNT>TIMx_CCR1 else active (OC1REF=1).

111: PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1 else active. In downcounting, channel 1 is active as long as TIMx_CNT>TIMx_CCR1 else inactive.

Note: In PWM mode 1 or 2, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode.

Bit 3 OC1PE : Output compare 1 preload enable

0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately.

1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event.

Note: The PWM mode can be used without validating the preload register only in one-pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed.

Bit 2 OC1FE : Output compare 1 fast enable

This bit is used to accelerate the effect of an event on the trigger in input on the CC output.

0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is

ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is

5 clock cycles.

1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently from the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2 mode.

Bits 1:0 CC1S : Capture/Compare 1 selection

This bit-field defines the direction of the channel (input/output) as well as the used input.

00: CC1 channel is configured as output.

01: CC1 channel is configured as input, IC1 is mapped on TI1.

10: CC1 channel is configured as input, IC1 is mapped on TI2.

11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)

Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).

Input capture mode

356/784 RM0451 Rev 3

RM0451 General-purpose timer (TIM2)

Bits 15:12 IC2F : Input capture 2 filter

Bits 11:10 IC2PSC[1:0] : Input capture 2 prescaler

Bits 9:8 CC2S : Capture/compare 2 selection

This bit-field defines the direction of the channel (input/output) as well as the used input.

00: CC2 channel is configured as output.

01: CC2 channel is configured as input, IC2 is mapped on TI2.

10: CC2 channel is configured as input, IC2 is mapped on TI1.

11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)

Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER).

Bits 7:4 IC1F : Input capture 1 filter

This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:

0000: No filter, sampling is done at f

DTS

0001: f

SAMPLING

0010: f

SAMPLING

0011: f

SAMPLING

CK_INT

, N=2

, N=4

, N=8

/2, N=6 0100: f

SAMPLING

0101: f

SAMPLING

0110: f

SAMPLING

DTS

0111: f

SAMPLING

DTS

/2, N=8

/4, N=6

/4, N=8

1000: f

SAMPLING

1001: f

SAMPLING

1010: f

SAMPLING

1011: f

SAMPLING

DTS

/8, N=6

/8, N=8

/16, N=5

/16, N=6

/16, N=8 1100: f

SAMPLING

1101: f

SAMPLING

1110: f

SAMPLING

DTS

1111: f

SAMPLING

DTS

/32, N=5

/32, N=6

/32, N=8

Bits 3:2 IC1PSC : Input capture 1 prescaler

This bit-field defines the ratio of the prescaler acting on CC1 input (IC1).

The prescaler is reset as soon as CC1E=0 (TIMx_CCER register).

00: no prescaler, capture is done each time an edge is detected on the capture input

01: capture is done once every 2 events

10: capture is done once every 4 events

11: capture is done once every 8 events

Bits 1:0 CC1S : Capture/Compare 1 selection

This bit-field defines the direction of the channel (input/output) as well as the used input.

00: CC1 channel is configured as output

01: CC1 channel is configured as input, IC1 is mapped on TI1

10: CC1 channel is configured as input, IC1 is mapped on TI2

11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)

Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).

RM0451 Rev 3 357/784

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General-purpose timer (TIM2) RM0451

14.4.8 TIMx capture/compare mode register 2 (TIMx_CCMR2)

OC4CE rw

Address offset: 0x1C

Reset value: 0x0000

Refer to the above CCMR1 register description.

14 13

OC4M[2:0]

IC4F[3:0] rw rw

12 rw

11 10

OC4PE OC4FE

IC4PSC[1:0] rw rw

9 8

CC4S[1:0] rw rw

OC3CE rw

6 5

OC3M[2:0]

IC3F[3:0] rw rw

4 rw

3 2

OC3PE OC3FE

IC3PSC[1:0] rw rw

Output compare mode

1 0

CC3S[1:0] rw rw

Bit 15 OC4CE: Output compare 4 clear enable

Bits 14:12 OC4M : Output compare 4 mode

Bit 11 OC4PE : Output compare 4 preload enable

Bit 10 OC4FE : Output compare 4 fast enable

Bits 9:8 CC4S : Capture/Compare 4 selection

This bit-field defines the direction of the channel (input/output) as well as the used input.

00: CC4 channel is configured as output

01: CC4 channel is configured as input, IC4 is mapped on TI4

10: CC4 channel is configured as input, IC4 is mapped on TI3

11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)

Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER).

Bit 7 OC3CE: Output compare 3 clear enable

Bits 6:4 OC3M : Output compare 3 mode

Bit 3 OC3PE : Output compare 3 preload enable

Bit 2 OC3FE : Output compare 3 fast enable

Bits 1:0 CC3S : Capture/Compare 3 selection

This bit-field defines the direction of the channel (input/output) as well as the used input.

00: CC3 channel is configured as output

01: CC3 channel is configured as input, IC3 is mapped on TI3

10: CC3 channel is configured as input, IC3 is mapped on TI4

11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)

Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER).

358/784 RM0451 Rev 3

RM0451 General-purpose timer (TIM2)

Input capture mode

Bits 15:12 IC4F : Input capture 4 filter

Bits 11:10 IC4PSC : Input capture 4 prescaler

Bits 9:8 CC4S : Capture/Compare 4 selection

This bit-field defines the direction of the channel (input/output) as well as the used input.

00: CC4 channel is configured as output

01: CC4 channel is configured as input, IC4 is mapped on TI4

10: CC4 channel is configured as input, IC4 is mapped on TI3

11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)

Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER).

Bits 7:4 IC3F : Input capture 3 filter

Bits 3:2 IC3PSC : Input capture 3 prescaler

Bits 1:0 CC3S : Capture/Compare 3 selection

This bit-field defines the direction of the channel (input/output) as well as the used input.

00: CC3 channel is configured as output

01: CC3 channel is configured as input, IC3 is mapped on TI3

10: CC3 channel is configured as input, IC3 is mapped on TI4

11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)

Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER).

14.4.9 TIMx capture/compare enable register (TIMx_CCER)

Address offset: 0x20

15 14

CC4NP Res.

Reset value: 0x0000

13 12 11 10

CC4P CC4E CC3NP Res.

rw rw rw

9 8 7 6

CC3P CC3E CC2NP Res.

rw rw rw

5 4 3 2

CC2P CC2E CC1NP Res.

rw rw rw

1 0

CC1P CC1E rw rw

Bit 15 CC4NP : Capture/Compare 4 output Polarity.

Refer to CC1NP description

Bit 14 Reserved, must be kept at reset value.

Bit 13 CC4P : Capture/Compare 4 output Polarity.

refer to CC1P description

Bit 12 CC4E : Capture/Compare 4 output enable.

refer to CC1E description

Bit 11 CC3NP : Capture/Compare 3 output Polarity.

refer to CC1NP description

Bit 10 Reserved, must be kept at reset value.

Bit 9 CC3P : Capture/Compare 3 output Polarity.

refer to CC1P description

Bit 8 CC3E : Capture/Compare 3 output enable.

refer to CC1E description

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General-purpose timer (TIM2) RM0451

Bit 7 CC2NP : Capture/Compare 2 output Polarity.

refer to CC1NP description

Bit 6 Reserved, must be kept at reset value.

Bit 5 CC2P : Capture/Compare 2 output Polarity.

refer to CC1P description

Bit 4 CC2E : Capture/Compare 2 output enable.

refer to CC1E description

Bit 3 CC1NP : Capture/Compare 1 output Polarity.

CC1 channel configured as output:

CC1NP must be kept cleared in this case.

CC1 channel configured as input:

This bit is used in conjunction with CC1P to define TI1FP1/TI2FP1 polarity. refer to CC1P description.

Bit 2 Reserved, must be kept at reset value.

Bit 1 CC1P : Capture/Compare 1 output Polarity.

CC1 channel configured as output:

0: OC1 active high

1: OC1 active low

CC1 channel configured as input:

CC1NP/CC1P bits select TI1FP1 and TI2FP1 polarity for trigger or capture operations.

00: noninverted/rising edge

Circuit is sensitive to TIxFP1 rising edge (capture, trigger in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger in gated mode, encoder mode).

01: inverted/falling edge

Circuit is sensitive to TIxFP1 falling edge (capture, trigger in reset, external clock or trigger mode), TIxFP1 is inverted (trigger in gated mode, encoder mode).

10: reserved, do not use this configuration.

11: noninverted/both edges

Circuit is sensitive to both TIxFP1 rising and falling edges (capture, trigger in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger in gated mode). This configuration must not be used for encoder mode.

Bit 0 CC1E : Capture/Compare 1 output enable.

CC1 channel configured as output:

0: Off - OC1 is not active

1: On - OC1 signal is output on the corresponding output pin

CC1 channel configured as input:

This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (TIMx_CCR1) or not.

0: Capture disabled

1: Capture enabled

CCxE bit

Table 65. Output control bit for standard OCx channels

OCx output state

Output Disabled (OCx=0, OCx_EN=0)

OCx=OCxREF + Polarity, OCx_EN=1

360/784 RM0451 Rev 3

RM0451

Note:

General-purpose timer (TIM2)

The state of the external I/O pins connected to the standard OCx channels depends on the

OCx channel state and the GPIO registers.

15 rw

Address offset: 0x24

Reset value: 0x0000

13 12 11 10 9 rw rw rw rw rw rw

Bits 15:0 CNT[15:0] : Low counter value

8 7

CNT[15:0] rw rw

6 rw

5 rw

4 rw

3 rw

2 rw

1 rw

0 rw

15 rw

Address offset: 0x28

Reset value: 0x0000

13 12 11 10 9 8 7

PSC[15:0] rw rw

6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 PSC[15:0] : Prescaler value

The counter clock frequency (CK_CNT) is equal to f

CK_PSC

/ (PSC[15:0] + 1).

PSC contains the value to be loaded in the active prescaler register at each update event

(including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in “reset mode”).

14.4.12 TIMx auto-reload register (TIMx_ARR)

15 14

Address offset: 0x2C

Reset value: 0xFFFF FFFF

13 12 11 10 9 rw rw rw rw rw rw rw

8 7

ARR[15:0] rw rw

6 rw

5 4 3 2 1 0 rw rw rw rw rw rw

Bits 15:0 ARR[15:0] : Low Auto-reload value

ARR is the value to be loaded in the actual auto-reload register.

Refer to the Section 14.3.1: Time-base unit on page 304

for more details about ARR update and behavior.

The counter is blocked while the auto-reload value is null.

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General-purpose timer (TIM2) RM0451

15 rw/r

Address offset: 0x34

Reset value: 0x0000

13 12 11 10 9 8 7

CCR1[15:0] rw/r rw/r

6 5 4 3 2 1 0 rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r

Bits 15:0 CCR1[15:0] : Low Capture/Compare 1 value

If channel CC1 is configured as output :

CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value).

It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register

(bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when an update event occurs.

The active capture/compare register contains the value to be compared to the counter

TIMx_CNT and signaled on OC1 output.

If channel CC1is configured as input :

CCR1 is the counter value transferred by the last input capture 1 event (IC1). The

TIMx_CCR1 register is read-only and cannot be programmed.

15 rw/r

Address offset: 0x38

Reset value: 0x0000

13 12 11 10 9 8 7

CCR2[15:0] rw/r rw/r

6 5 4 3 2 1 0 rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r

Bits 15:0 CCR2[15:0] : Low Capture/Compare 2 value

If channel CC2 is configured as output:

CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value).

It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register

(bit OC2PE). Else the preload value is copied in the active capture/compare 2 register when an update event occurs.

The active capture/compare register contains the value to be compared to the counter

TIMx_CNT and signalled on OC2 output.

If channel CC2 is configured as input:

CCR2 is the counter value transferred by the last input capture 2 event (IC2). The

TIMx_CCR2 register is read-only and cannot be programmed.

362/784 RM0451 Rev 3

RM0451 General-purpose timer (TIM2)

15 rw/r

Address offset: 0x3C

Reset value: 0x0000

13 12 11 10 9 8 7

CCR3[15:0] rw/r rw/r

6 5 4 3 2 1 0 rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r

Bits 15:0 CCR3[15:0] : Low Capture/Compare value

If channel CC3 is configured as output:

CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value).

It is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register

(bit OC3PE). Else the preload value is copied in the active capture/compare 3 register when an update event occurs.

The active capture/compare register contains the value to be compared to the counter

TIMx_CNT and signalled on OC3 output.

If channel CC3is configured as input:

CCR3 is the counter value transferred by the last input capture 3 event (IC3). The

TIMx_CCR3 register is read-only and cannot be programmed.

15 rw/r

Address offset: 0x40

Reset value: 0x0000

13 12 11 10 9 8 7

CCR4[15:0] rw/r rw/r

6 5 4 3 2 1 0 rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r

Bits 15:0 CCR4[15:0] : Low Capture/Compare value

If CC4 channel is configured as output (CC4S bits):

CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value).

It is loaded permanently if the preload feature is not selected in the TIMx_CCMR4 register

(bit OC4PE). Else the preload value is copied in the active capture/compare 4 register when an update event occurs.

The active capture/compare register contains the value to be compared to the counter

TIMx_CNT and signalled on OC4 output.

If CC4 channel is configured as input (CC4S bits in TIMx_CCMR4 register):

CCR4 is the counter value transferred by the last input capture 4 event (IC4). The

TIMx_CCR4 register is read-only and cannot be programmed.

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14.4.17 TIMx DMA control register (TIMx_DCR)

Res.

Address offset: 0x48

Reset value: 0x0000

Res.

12 11 10

DBL[4:0] rw rw rw

9 rw

8 rw

Res.

4 3 rw

DBA[4:0] rw

1 rw

0 rw rw

Bits 15:13 Reserved, must be kept at reset value.

Bits 12:8 DBL[4:0] : DMA burst length

This 5-bit vector defines the number of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address).

00000: 1 transfer,

00001: 2 transfers,

00010: 3 transfers,

...

10001: 18 transfers.

Bits 7:5 Reserved, must be kept at reset value.

Bits 4:0 DBA[4:0] : DMA base address

This 5-bit vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register.

Example:

00000: TIMx_CR1,

00001: TIMx_CR2,

00010: TIMx_SMCR,

...

Example: Let us consider the following transfer: DBL = 7 transfers & DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address.

14.4.18 TIMx DMA address for full transfer (TIMx_DMAR)

15 14

Address offset: 0x4C

Reset value: 0x0000

13 12 11 10 9 6 5 rw rw rw rw rw rw rw

8 7

DMAB[15:0] rw rw rw rw

4 rw

3 2 1 0 rw rw rw rw

Bits 15:0 DMAB[15:0] : DMA register for burst accesses

A read or write operation to the DMAR register accesses the register located at the address

(TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the

DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR).

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Note:

General-purpose timer (TIM2)

Example of how to use the DMA burst feature

In this example the timer DMA burst feature is used to update the contents of the CCRx registers (x = 2, 3, 4) with the DMA transferring half words into the CCRx registers.

This is done in the following steps:

Configure the corresponding DMA channel as follows:

– DMA channel peripheral address is the DMAR register address

– DMA channel memory address is the address of the buffer in the RAM containing the data to be transferred by DMA into CCRx registers.

– Number of data to transfer = 3 (See note below).

– Circular mode disabled.

2. Configure the DCR register by configuring the DBA and DBL bit fields as follows:

DBL = 3 transfers, DBA = 0xE.

3. Enable the TIMx update DMA request (set the UDE bit in the DIER register).

5. Enable the DMA channel

For code example, refer to

A.9.21: DMA burst feature code example

This example is for the case where every CCRx register to be updated once. If every CCRx register is to be updated twice for example, the number of data to transfer should be 6. Let's take the example of a buffer in the RAM containing data1, data2, data3, data4, data5 and data6. The data is transferred to the CCRx registers as follows: on the first update DMA request, data1 is transferred to CCR2, data2 is transferred to CCR3, data3 is transferred to

CCR4 and on the second update DMA request, data4 is transferred to CCR2, data5 is transferred to CCR3 and data6 is transferred to CCR4.

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14.4.19 TIM2 option register (TIM2_OR)

Address offset: 0x50

Reset value: 0x0000

Res.

TI4_RMP

3 rw rw

2 rw

ETR_RMP rw

0 rw

Bits 15:5 Reserved, must be kept at reset value.

Bits 4:3 TI4_RMP: Internal trigger (TI4 connected to TIM2_CH4) remap

This bit is set and cleared by software.

01: Reserved

10: Reserved others: TIM2 TI4 input connected to ORed GPIOs. Refer to the Alternate function mapping table in the device datasheets.

Bits 2:0 ETR_RMP : Timer2 ETR remap

This bit is set and cleared by software.

111: Reserved

110: Reserved

101: TIM2 ETR input is connected to LSE

011: TIM2 ETR input is connected to HSI16 when HSI16OUTEN bit is set in

Clock control register (RCC_CR)

(except for category 3 devices) others: TIM2 ETR input is connected to ORed GPIOs. Refer to the Alternate function mapping table in the device datasheets

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RM0451 General-purpose timer (TIM2)

14.5 TIMx register map

TIMx registers are mapped as described in the table below:

Offset Register

Table 66. TIM2 register map and reset values

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0x00

0x04

TIMx_CR1

Reset value

TIMx_CR2

Reset value

CKD [1:0]

0 0 0

CMS[1:0]

0 0

MMS[2:0]

0 0 0

0x08

0x0C

0x10

0x14

0x18

0x1C

0x20

0x24

0x28

TIMx_SMCR

Reset value

TIMx_DIER

Reset value

TIMx_SR

Reset value

TIMx_EGR

Reset value

TIMx_CCMR1

Output

Compare mode

Reset value

TIMx_CCMR1

Input Capture mode

Reset value

TIMx_CCMR2

Output

Compare mode

Reset value

TIMx_CCMR2

Input Capture mode

Reset value

TIMx_CCER

Reset value

TIMx_CNT

Reset value

TIMx_PSC

Reset value

OC2M

[2:0]

0 0

IC2F[3:0]

0 0

OC4M

[2:0]

0 0

IC4F[3:0]

0 0 0

ETF[3:0]

0 0 0

0 0

TS[2:0]

0 0

IC2

PSC

[1:0]

CC2S [1:0]

0 0

CC2S [1:0]

0 0

CC4S [1:0]

IC4

PSC

[1:0]

0 0

CC4S [1:0]

0 0

OC1M

[2:0]

0 0

IC1F[3:0]

OC3M

[2:0]

IC3F[3:0]

0 0 0

0 0

CNT[15:0]

0 0

PSC[15:0]

0 0

SMS[2:0]

0 0 0 0

IC1

PSC

[1:0]

CC1S [1:0]

0 0

CC1S [1:0]

0 0

CC3S [1:0]

IC3

PSC

[1:0]

0 0

CC3S [1:0]

0 0

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Offset

0x2C

0x30

0x34

0x38

0x3C

0x40

0x44

0x48

0x4C

0x50

Table 66. TIM2 register map and reset values (continued)

Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TIMx_ARR

Reset value 0 0 0 0 0 0 0

Res.

ARR[15:0]

0 0 0 0 0 0 0 0

TIMx_CCR1

Reset value

TIMx_CCR2

Reset value

TIMx_CCR3

Reset value

TIMx_CCR4

Reset value

0 0 0 0

CCR1[15:0]

0 0

CCR2[15:0]

0 0

CCR3[15:0]

0 0

CCR4[15:0]

Res.

0 0

0 0 0 0

DBA[4:0]

0 0 0

TIMx_DCR

Reset value

TIMx_DMAR

Reset value

TIM2_OR

0 0 0

DBL[4:0]

0 0

0 0 0

DMAB[15:0]

0 0 0

0 0

Reset value

Refer to Section 2.2 on page 39 for the register boundary addresses.

0 0 0 0

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RM0451 General-purpose timers (TIM21/22)

15.1 Introduction

The TIM21/22 general-purpose timers consist of a 16-bit auto-reload counter driven by a programmable prescaler.

They may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare, PWM).

Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the RCC clock controller prescalers.

15.2 TIM21/22 main features

15.2.1 TIM21/22 main features

The features of the TIM21/22 general-purpose timer include:

• 16-bit up, down, up/down, auto-reload counter

• 16-bit programmable prescaler used to divide the counter clock frequency by any factor between 1 and 65535 (can be changed “on the fly”)

• Up to 2 independent channels for:

– Input capture

– Output compare

– PWM generation (edge- and center-aligned mode)

– One-pulse mode output

• Synchronization circuit to control the timer with external signals and to interconnect several timers together

• Interrupt generation on the following events:

– Update: counter overflow/underflow, counter initialization (by software or internal trigger)

– Trigger event (counter start, stop, initialization or count by internal trigger)

– Input capture

– Output compare

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TIMx_ETR

TIMx_CH1

TIMx_CH2

Figure 101. General-purpose timer block diagram (TIM21/22)

ETR

Internal clock (CK_INT)

Polarity selection & edge

ETRP

Input filter

ITR0

ITR1

ITR

TRC

TI1F_ED

ETRF

Trigger controller

TGI

TRGI

Slave controller mode

Reset, enable, up, count

Encoder interface

TI1FP1

TI2FP2

TRGO

TI1

TI2

Input filter & edge detector

TI2FP1

TI2FP2

TRC

Auto-reload register

Stop, Clear

CK_PSC

TI1FP1

TI1FP2

IC1

PSC prescaler

CK_CNT

CC1I

Prescaler

IC1PS

+/CNT counter

CC1I

Capture/Compare 1 register

OC1REF

TRC

CC2I

IC2

Prescaler

IC2PS

Capture/Compare 2 register

CC2I

OC2REF

Output control

OC1

TIMx_CH1

Output control

OC2

TIMx_CH2

Notes:

Reg

Preload registers transferred to active registers on U event according to control bit

Event

Interrupt

ETRF

MSv33704V2

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15.3 TIM21/22 functional description

General-purpose timers (TIM21/22)

The main block of the timer is a 16-bit counter with its related auto-reload register. The counters counts up, down or both up and down but also down or both up and down. The counter clock can be divided by a prescaler.

The counter, the auto-reload register and the prescaler register can be written or read by software. This is true even when the counter is running.

The timebase unit includes:

• Counter register (TIMx_CNT)

• Prescaler register (TIMx_PSC)

• Auto-reload register (TIMx_ARR)

The auto-reload register is preloaded. Writing to or reading from the auto-reload register accesses the preload register. The content of the preload register are transferred into the shadow register permanently or at each update event (UEV), depending on the auto-reload preload enable bit (ARPE) in TIMx_CR1 register. The update event is sent when the counter reaches the overflow and if the UDIS bit equals 0 in the TIMx_CR1 register. It can also be generated by software. The generation of the update event is described in detailed for each configuration.

Note that the counter starts counting 1 clock cycle after setting the CEN bit in the TIMx_CR1 register.

Prescaler description

The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register).

It can be changed on the fly as this control register is buffered. The new prescaler ratio is taken into account at the next update event.

Figure 103

and Figure 104 give some examples of the counter behavior when the prescaler

ratio is changed on the fly.

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Figure 102. Counter timing diagram with prescaler division change from 1 to 2

CK_PSC

CEN

Timerclock = CK_CNT

Counter register

Update event (UEV)

Prescaler control register

F7 F8 F9 FA FB

Write a new value in TIMx_PSC

Prescaler buffer

Prescaler counter

00 01

02 03

1 0 1 0 1 0 1

MS31076V2

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RM0451 General-purpose timers (TIM21/22)

Figure 103. Counter timing diagram with prescaler division change from 1 to 4

CK_PSC

CEN

Timerclock = CK_CNT

Counter register

Update event (UEV)

F7 F8 F9

Prescaler control register

Write a new value in TIMx_PSC

Prescaler buffer

Prescaler counter

FA FB FC 00

0 1 2 3 0 1 2 3

MS31077V2

Upcounting mode

In upcounting mode, the counter counts from 0 to the auto-reload value (content of the

TIMx_ARR register), then restarts from 0 and generates a counter overflow event.

Setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller on TIM21/22) also generates an update event.

The UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until the UDIS bit has been written to 0.

However, the counter restarts from 0, as well as the counter of the prescaler (but the prescale rate does not change). In addition, if the URS bit (update request selection) in

TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event.

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When an update event occurs, all the registers are updated and the update flag (UIF bit in

TIMx_SR register) is set (depending on the URS bit):

• The auto-reload shadow register is updated with the preload value (TIMx_ARR),

• The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register).

The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR=0x36.

Figure 104. Counter timing diagram, internal clock divided by 1

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 31 32 33 34 35 36 00 01 02 03 04 05 06 07

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31078V2

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RM0451 General-purpose timers (TIM21/22)

Figure 105. Counter timing diagram, internal clock divided by 2

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 0034 0035 0036 0000 0001 0002 0003

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

Figure 106. Counter timing diagram, internal clock divided by 4

MS31079V2

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

0035 0036 0000 0001

MS31080V2

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General-purpose timers (TIM21/22)

Figure 107. Counter timing diagram, internal clock divided by N

RM0451

CK_PSC

Timerclock = CK_CNT

Counter register 1F 20 00

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31081V2

Figure 108. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded)

CK_PSC

CEN

Timerclock = CK_CNT

Counter register

Counter overflow

31 32

Update event (UEV)

Update interrupt flag

(UIF)

Auto-reload preload register

Write a new value in TIMx_ARR

33 34 35 36 00 01 02 03 04 05 06 07

MS31082V2

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RM0451 General-purpose timers (TIM21/22)

Figure 109. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded)