Intel

®

Celeron

®

Processor E3000

Series

Datasheet

August 2010

Document Number: 322567-003

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED,

BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS

PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER,

AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING

LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY

PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

UNLESS OTHERWISE AGREED IN WRITING BY INTEL, THE INTEL PRODUCTS ARE NOT DESIGNED NOR INTENDED FOR ANY

APPLICATION IN WHICH THE FAILURE OF THE INTEL PRODUCT COULD CREATE A SITUATION WHERE PERSONAL INJURY OR DEATH

MAY OCCUR.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The Intel Celeron

®

processor E3000 series may contain design defects or errors known as errata which may cause the product to deviate from published specifications.

Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. See http://www.intel.com/products/processor_number for details. Over time processor numbers will increment based on changes in clock, speed, cache, FSB, or other features, and increments are not intended to represent proportional or quantitative increases in any particular feature. Current roadmap processor number progression is not necessarily representative of future roadmaps. See www.intel.com/products/processor_number for details.

Intel

®

64 requires a computer system with a processor, chipset, BIOS, operating system, device drivers and applications enabled for Intel 64. Processor will not operate (including 32-bit operation) without an Intel 64-enabled BIOS. Performance will vary depending on your hardware and software configurations. See http://developer.intel.com/technology/intel64/ for more information including details on which processors support Intel 64 or consult with your system vendor for more information.

Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system. Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality.

‡ Not all specified units of this processor support Enhanced Intel SpeedStep

®

Technology. See the Processor Spec Finder at http:/

/processorfinder.intel.com or contact your Intel representative for more information.

Not all specified units of this processor support Thermal Monitor 2, Enhanced HALT State and Enhanced Intel SpeedStep

®

Technology. See the Processor Spec Finder at http://processorfinder.intel.com or contact your Intel representative for more information.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Intel, Pentium, Celeron, Intel Core, Intel SpeedStep, and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries.

* Other names and brands may be claimed as the property of others.

Copyright © 2009–2010, Intel Corporation. All rights reserved.

2

Datasheet

Contents

1

2

3

4

5

Introduction .............................................................................................................. 9

1.1

Terminology ....................................................................................................... 9

1.1.1

Processor Terminology Definitions ............................................................ 10

1.2

References ....................................................................................................... 11

Electrical Specifications ........................................................................................... 13

2.1

Power and Ground Lands.................................................................................... 13

2.2

Decoupling Guidelines ........................................................................................ 13

2.2.1

V

CC

2.2.2

V

TT

Decoupling ...................................................................................... 13

Decoupling ...................................................................................... 13

2.2.3

FSB Decoupling...................................................................................... 14

2.3

Voltage Identification ......................................................................................... 14

2.4

Reserved, Unused, and TESTHI Signals ................................................................ 16

2.5

Power Segment Identifier (PSID)......................................................................... 16

2.6

Voltage and Current Specification ........................................................................ 17

2.6.1

Absolute Maximum and Minimum Ratings .................................................. 17

2.6.2

DC Voltage and Current Specification ........................................................ 18

2.6.3

V

CC

Overshoot ....................................................................................... 20

2.6.4

Die Voltage Validation ............................................................................. 21

2.7

Signaling Specifications ...................................................................................... 21

2.7.1

FSB Signal Groups.................................................................................. 22

2.7.2

CMOS and Open Drain Signals ................................................................. 23

2.7.3

Processor DC Specifications ..................................................................... 24

2.7.3.1

Platform Environment Control Interface (PECI) DC Specifications..... 25

2.7.3.2

GTL+ Front Side Bus Specifications ............................................. 26

2.8

Clock Specifications ........................................................................................... 27

2.8.1

Front Side Bus Clock (BCLK[1:0]) and Processor Clocking ............................ 27

2.8.2

FSB Frequency Select Signals (BSEL[2:0])................................................. 28

2.8.3

Phase Lock Loop (PLL) and Filter .............................................................. 29

2.8.4

BCLK[1:0] Specifications ......................................................................... 29

Package Mechanical Specifications .......................................................................... 33

3.1

Package Mechanical Drawing............................................................................... 33

3.2

Processor Component Keep-Out Zones ................................................................. 37

3.3

Package Loading Specifications ........................................................................... 37

3.4

Package Handling Guidelines............................................................................... 37

3.5

Package Insertion Specifications .......................................................................... 38

3.6

Processor Mass Specification ............................................................................... 38

3.7

Processor Materials............................................................................................ 38

3.8

Processor Markings............................................................................................ 38

3.9

Processor Land Coordinates ................................................................................ 39

Land Listing and Signal Descriptions ....................................................................... 41

4.1

Processor Land Assignments ............................................................................... 41

4.2

Alphabetical Signals Reference ............................................................................ 64

Thermal Specifications and Design Considerations .................................................. 75

5.1

Processor Thermal Specifications ......................................................................... 75

5.1.1

Thermal Specifications ............................................................................ 75

5.1.2

Thermal Metrology ................................................................................. 78

5.2

Processor Thermal Features ................................................................................ 78

5.2.1

Thermal Monitor..................................................................................... 78

5.2.2

Thermal Monitor 2 .................................................................................. 79

5.2.3

On-Demand Mode .................................................................................. 80

5.2.4

PROCHOT# Signal .................................................................................. 81

5.2.5

THERMTRIP# Signal ............................................................................... 81

5.3

Platform Environment Control Interface (PECI) ...................................................... 82

Datasheet

3

6

7

8

5.3.1

Introduction ...........................................................................................82

5.3.1.1

T

CONTROL

and TCC activation on PECI-Based Systems .....................82

5.3.2

PECI Specifications .................................................................................83

5.3.2.1

PECI Device Address..................................................................83

5.3.2.2

PECI Command Support .............................................................83

5.3.2.3

PECI Fault Handling Requirements ...............................................83

5.3.2.4

PECI GetTemp0() Error Code Support ..........................................83

Features ..................................................................................................................85

6.1

Power-On Configuration Options ..........................................................................85

6.2

Clock Control and Low Power States .....................................................................85

6.2.1

Normal State .........................................................................................86

6.2.2

HALT and Extended HALT Powerdown States ..............................................86

6.2.2.1

HALT Powerdown State ..............................................................87

6.2.2.2

Extended HALT Powerdown State ................................................87

6.2.3

Stop Grant and Extended Stop Grant States ...............................................87

6.2.3.1

Stop-Grant State.......................................................................87

6.2.3.2

Extended Stop Grant State .........................................................88

6.2.4

Extended HALT Snoop State, HALT Snoop State, Extended

Stop Grant Snoop State, and Stop Grant Snoop State..................................88

6.2.4.1

HALT Snoop State, Stop Grant Snoop State ..................................88

6.2.4.2

Extended HALT Snoop State, Extended Stop Grant Snoop State.......88

6.2.5

Sleep State ............................................................................................89

6.2.6

Deep Sleep State ....................................................................................89

6.2.7

Deeper Sleep State .................................................................................90

6.2.8

Enhanced Intel SpeedStep

®

Technology ....................................................90

6.3

Processor Power Status Indicator (PSI) Signal .......................................................90

Boxed Processor Specifications ................................................................................91

7.1

Introduction ......................................................................................................91

7.2

Mechanical Specifications ....................................................................................92

7.2.1

Boxed Processor Cooling Solution Dimensions.............................................92

7.2.2

Boxed Processor Fan Heatsink Weight .......................................................93

7.2.3

Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly .....93

7.3

Electrical Requirements ......................................................................................93

7.3.1

Fan Heatsink Power Supply ......................................................................93

7.4

Thermal Specifications........................................................................................95

7.4.1

Boxed Processor Cooling Requirements ......................................................95

7.4.2

Variable Speed Fan .................................................................................97

Debug Tools Specifications ......................................................................................99

8.1

Logic Analyzer Interface (LAI) .............................................................................99

8.1.1

Mechanical Considerations .......................................................................99

8.1.2

Electrical Considerations ..........................................................................99

4

Datasheet

Figures

1 Processor V

CC

Static and Transient Tolerance............................................................... 20

2 V

CC

Overshoot Example Waveform ............................................................................. 21

3 Differential Clock Waveform ...................................................................................... 30

4 Measurement Points for Differential Clock Waveforms ................................................... 31

5 Processor Package Assembly Sketch ........................................................................... 33

6 Processor Package Drawing Sheet 1 of 3 ..................................................................... 34

7 Processor Package Drawing Sheet 2 of 3 ..................................................................... 35

8 Processor Package Drawing Sheet 3 of 3 ..................................................................... 36

9 Intel

®

Celeron

®

Processor E3000 Series Top-Side Markings Example .............................. 38

10 Processor Land Coordinates and Quadrants, Top View ................................................... 39

11 land-out Diagram (Top View – Left Side) ..................................................................... 42

12 land-out Diagram (Top View – Right Side) ................................................................... 43

13 Processor Series Thermal Profile ................................................................................ 77

14 Case Temperature (TC) Measurement Location ............................................................ 78

15 Thermal Monitor 2 Frequency and Voltage Ordering ...................................................... 80

16 Conceptual Fan Control Diagram on PECI-Based Platforms ............................................. 82

17 Processor Low Power State Machine ........................................................................... 86

18 Mechanical Representation of the Boxed Processor ....................................................... 91

19 Space Requirements for the Boxed Processor (Side View) .............................................. 92

20 Space Requirements for the Boxed Processor (Top View)............................................... 92

21 Overall View Space Requirements for the Boxed Processor............................................. 93

22 Boxed Processor Fan Heatsink Power Cable Connector Description .................................. 94

23 Baseboard Power Header Placement Relative to Processor Socket ................................... 95

24 Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 1 view) ................... 96

25 Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 2 view) ................... 96

26 Boxed Processor Fan Heatsink Set Points..................................................................... 97

Datasheet

5

Tables

1 References ..............................................................................................................11

2 Voltage Identification Definition ..................................................................................15

3 Absolute Maximum and Minimum Ratings ....................................................................17

4 Voltage and Current Specifications ..............................................................................18

5 Processor V

CC

Static and Transient Tolerance ...............................................................19

6 V

CC

Overshoot Specifications......................................................................................20

7 FSB Signal Groups ....................................................................................................22

8 Signal Characteristics................................................................................................23

9 Signal Reference Voltages .........................................................................................23

10 GTL+ Signal Group DC Specifications ..........................................................................24

11 Open Drain and TAP Output Signal Group DC Specifications ...........................................24

12 CMOS Signal Group DC Specifications..........................................................................25

13 PECI DC Electrical Limits ...........................................................................................26

14 GTL+ Bus Voltage Definitions .....................................................................................27

15 Core Frequency to FSB Multiplier Configuration.............................................................28

16 BSEL[2:0] Frequency Table for BCLK[1:0] ...................................................................29

17 Front Side Bus Differential BCLK Specifications .............................................................29

18 FSB Differential Clock Specifications (800 MHz FSB) ......................................................30

19 Processor Loading Specifications.................................................................................37

20 Package Handling Guidelines ......................................................................................37

21 Processor Materials ...................................................................................................38

22 Alphabetical Land Assignments...................................................................................44

23 Numerical Land Assignment .......................................................................................54

24 Signal Description.....................................................................................................64

25 Processor Thermal Specifications ................................................................................76

26 Processor Thermal Profile ..........................................................................................77

27 GetTemp0() Error Codes ...........................................................................................83

28 Power-On Configuration Option Signals .......................................................................85

29 Fan Heatsink Power and Signal Specifications ...............................................................94

30 Fan Heatsink Power and Signal Specifications ...............................................................98

6

Datasheet

Intel

®

Celeron

®

Processor E3000 Series Features

• Available at 2.70, 2.60 GHz, 2.50 GHz and

2.40 GHz

• Enhanced Intel Speedstep

®

Technology

• Supports Intel

®

64 architecture

• Supports Execute Disable Bit capability

• FSB frequency at 800 MHz

• Binary compatible with applications running on previous members of the Intel microprocessor line

• Advance Dynamic Execution

• Very deep out-of-order execution

• Enhanced branch prediction

• Optimized for 32-bit applications running on advanced 32-bit operating systems

• Intel

®

Advanced Smart Cache

• 1 MB Level 2 cache

• Intel

®

Advanced Digital Media Boost

• Enhanced floating point and multimedia unit for enhanced video, audio, encryption, and

3D performance

• Power Management capabilities

• System Management mode

• Multiple low-power states

• 8-way cache associativity provides improved cache hit rate on load/store operations

• 775-land Package

The Intel

®

Celeron

®

processor E3000 series is based on the Enhanced Intel

®

Core™ microarchitecture. The Enhanced Intel

®

Core™ microarchitecture combines the performance across applications and usages where end-users can truly appreciate and experience the performance. These applications include Internet audio and streaming video, image processing, video content creation, speech, 3D, CAD, games, multimedia, and multitasking user environments.

Intel

®

64 architecture enables the processor to execute operating systems and applications written to take advantage of the Intel 64 architecture. The processor, supporting Enhanced Intel Speedstep

® technology, allows tradeoffs to be made between performance and power consumption.

The Intel Celeron processor E3000 series also includes the Execute Disable Bit capability. This feature, combined with a supported operating system, allows memory to be marked as executable or nonexecutable.

Datasheet

7

Revision History

Revision

Number

001

002

003

Description

• Initial release

• Intel

®

Celeron

®

processor E3400

• Changed the processor numbering from Intel Celeron processor E3x00 series to Intel Celeron processor E3000 series.

• Intel

®

Celeron

®

processor E3500

Revision Date

August 2009

January 2010

August 2010

§ §

8

Datasheet

Introduction

1

Note:

Note:

1.1

Introduction

The Intel

®

Celeron

®

processor E3000 series is based on the Enhanced Intel

®

Core™ microarchitecture. The Intel Enhanced Core™ microarchitecture combines the performance of previous generation Desktop products with the power efficiencies of a low-power microarchitecture to enable smaller, quieter systems. The Intel Celeron processor E3000 series is a 64-bit processor that maintains compatibility with IA-32 software.

In this document, the Intel

®

Celeron

®

processor E3000 series may be referred to as

"the processor."

In this document, unless otherwise specified, the Intel series refers to the Intel

®

®

Celeron

®

processor E3000

Celeron

®

processor E3500, E3400, E3300, and E3200.

The processors use Flip-Chip Land Grid Array (FC-LGA8) package technology, and plugs into a 775-land surface mount, Land Grid Array (LGA) socket, referred to as the

LGA775 socket.

The processors are based on 45 nm process technology. The processors feature the

Intel

®

Advanced Smart Cache, a shared multi-core optimized cache that significantly reduces latency to frequently used data. The processors feature an 800 MHz front side bus (FSB) and 1 MB of L2 cache. The processors support all the existing Streaming

SIMD Extensions 2 (SSE2), Streaming SIMD Extensions 3 (SSE3), and Supplemental

Streaming SIMD Extension 3 (SSSE3). The processors support several Advanced

Technologies: Execute Disable Bit, Intel

SpeedStep

®

Technology.

®

64 architecture, and Enhanced Intel

The processor's front side bus (FSB) use a split-transaction, deferred reply protocol.

The FSB uses Source-Synchronous Transfer of address and data to improve performance by transferring data four times per bus clock (4X data transfer rate).

Along with the 4X data bus, the address bus can deliver addresses two times per bus clock and is referred to as a "double-clocked" or 2X address bus. Working together, the

4X data bus and 2X address bus provide a data bus bandwidth of up to 8.5 GB/s.

Intel has enabled support components for the processor including heatsink, heatsink retention mechanism, and socket. Manufacturability is a high priority; hence, mechanical assembly may be completed from the top of the baseboard and should not require any special tooling.

Terminology

A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in the active state when driven to a low level. For example, when RESET# is low, a reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data), the ‘#’ symbol implies that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and

D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level).

“Front Side Bus” refers to the interface between the processor and system core logic

(a.k.a. the chipset components). The FSB is a multiprocessing interface to processors, memory, and I/O.

Datasheet 9

Introduction

1.1.1

Processor Terminology Definitions

Commonly used terms are explained here for clarification:

• Intel

®

Celeron

®

processor E3000 series—Dual core processor in the FC-LGA8 package with a 1 MB L2 cache.

• Processor—For this document, the term processor is the generic form of the

Intel

®

Celeron

®

processor E3000 series.

• Voltage Regulator Design Guide—For this document “Voltage Regulator Design

Guide” may be used in place of:

— Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design

Guidelines For Desktop LGA775 Socket

• Enhanced Intel

®

Core

™

microarchitecture—A new foundation for Intel

® architecture-based desktop, mobile and mainstream server multi-core processors.

For additional information refer to: http://www.intel.com/technology/architecture/ coremicro/

• Keep-out zone—The area on or near the processor that system design can not use.

• Processor core—Processor die with integrated L2 cache.

• LGA775 socket—The processors mate with the system board through a surface mount, 775-land, LGA socket.

• Integrated heat spreader (IHS) —A component of the processor package used to enhance the thermal performance of the package. Component thermal solutions interface with the processor at the IHS surface.

• Retention mechanism (RM)—Since the LGA775 socket does not include any mechanical features for heatsink attach, a retention mechanism is required.

Component thermal solutions should attach to the processor using a retention mechanism that is independent of the socket.

• FSB (Front Side Bus)—The electrical interface that connects the processor to the chipset. Also referred to as the processor system bus or the system bus. All memory and I/O transactions as well as interrupt messages pass between the processor and chipset over the FSB.

• Storage conditions—Refers to a non-operational state. The processor may be installed in a platform, in a tray, or loose. Processors may be sealed in packaging or exposed to free air. Under these conditions, processor lands should not be connected to any supply voltages, have any I/Os biased, or receive any clocks.

Upon exposure to “free air”(that is, unsealed packaging or a device removed from packaging material) the processor must be handled in accordance with moisture sensitivity labeling (MSL) as indicated on the packaging material.

• Functional operation—Refers to normal operating conditions in which all processor specifications, including DC, AC, system bus, signal quality, mechanical and thermal are satisfied.

• Execute Disable Bit—Execute Disable Bit allows memory to be marked as executable or non-executable, when combined with a supporting operating system.

If code attempts to run in non-executable memory the processor raises an error to the operating system. This feature can prevent some classes of viruses or worms that exploit buffer over run vulnerabilities and can thus help improve the overall security of the system. See the Intel

®

Architecture Software Developer's Manual for more detailed information.

• Intel

®

64 Architecture— An enhancement to Intel's IA-32 architecture, allowing the processor to execute operating systems and applications written to take advantage of the Intel 64 architecture. Further details on Intel 64 architecture and programming model can be found in the Intel Extended Memory 64 Technology

10 Datasheet

Introduction

1.2

Table 1.

Software Developer Guide at http://developer.intel.com/technology/

64bitextensions/.

• Enhanced Intel SpeedStep

®

Technology—Enhanced Intel SpeedStep

Technology allows trade-offs to be made between performance and power consumptions, based on processor utilization. This may lower average power consumption (in conjunction with OS support).

• Intel

®

Virtualization Technology (Intel

®

VT)—A set of hardware enhancements to Intel server and client platforms that can improve virtualization solutions. Intel VT will provide a foundation for widely-deployed virtualization solutions and enables more robust hardware assisted virtualization solutions. More information can be found at: http://www.intel.com/technology/virtualization/

• Platform Environment Control Interface (PECI)—A proprietary one-wire bus interface that provides a communication channel between the processor and chipset components to external monitoring devices.

References

Material and concepts available in the following documents may be beneficial when reading this document.

References

Document

Intel

®

Celeron

®

Processor E3000 Series Specification Update

Intel

®

Core™2 Duo Processor E8000 and E7000 Series, Intel

®

Pentium

®

Dual-Core Processor E6000 and E5000 Series, and

Intel

®

Celeron Processor E3000 Series Thermal and Mechanical

Design Guidelines

Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery

Design Guidelines For Desktop LGA775 Socket

LGA775 Socket Mechanical Design Guide

Location

http://download.intel.com/ design/processor/ specupdt/322568.pdf

www.intel.com/design/ processor/designex/

318734.htm http://www.intel.com/ design/processor/ applnots/313214.htm

http://intel.com/design/

Pentium4/guides/

302666.htm

Intel

®

64 and IA-32 Intel Architecture Software Developer's

Manuals

Volume 1: Basic Architecture

Volume 2A: Instruction Set Reference, A-M

Volume 2B: Instruction Set Reference, N-Z

Volume 3A: System Programming Guide, Part 1

Volume 3B: System Programming Guide, Part 2

§

http://www.intel.com/ products/processor/ manuals/

Datasheet 11

Introduction

12 Datasheet

Electrical Specifications

2

2.1

2.2

2.2.1

2.2.2

Electrical Specifications

This chapter describes the electrical characteristics of the processor interfaces and signals. DC electrical characteristics are provided.

Power and Ground Lands

The processor has VCC (power), VTT, and VSS (ground) inputs for on-chip power distribution. All power lands must be connected to V

CC

, while all VSS lands must be connected to a system ground plane. The processor VCC lands must be supplied the voltage determined by the Voltage IDentification (VID) lands.

The signals denoted as VTT provide termination for the front side bus and power to the

I/O buffers. A separate supply must be implemented for these lands, that meets the

V

TT

specifications outlined in Table 4 .

Decoupling Guidelines

Due to its large number of transistors and high internal clock speeds, the processor is capable of generating large current swings. This may cause voltages on power planes to sag below their minimum specified values if bulk decoupling is not adequate. Larger bulk storage (C

BULK

), such as electrolytic or aluminum-polymer capacitors, supply current during longer lasting changes in current demand by the component, such as coming out of an idle condition. Similarly, they act as a storage well for current when entering an idle condition from a running condition. The motherboard must be designed to ensure that the voltage provided to the processor remains within the specifications listed in Table 4 . Failure to do so can result in timing violations or reduced lifetime of the component.

V

CC

Decoupling

V

CC

regulator solutions need to provide sufficient decoupling capacitance to satisfy the processor voltage specifications. This includes bulk capacitance with low effective series resistance (ESR) to keep the voltage rail within specifications during large swings in load current. In addition, ceramic decoupling capacitors are required to filter high frequency content generated by the front side bus and processor activity. Consult the

Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For

Desktop LGA775 Socket for further information. Contact your Intel field representative for additional information.

V

TT

Decoupling

Decoupling must be provided on the motherboard. Decoupling solutions must be sized to meet the expected load. To ensure compliance with the specifications, various factors associated with the power delivery solution must be considered including regulator type, power plane and trace sizing, and component placement. A conservative decoupling solution would consist of a combination of low ESR bulk capacitors and high frequency ceramic capacitors.

Datasheet 13

Electrical Specifications

2.2.3

2.3

Note:

FSB Decoupling

The processor integrates signal termination on the die. In addition, some of the high frequency capacitance required for the FSB is included on the processor package.

However, additional high frequency capacitance must be added to the motherboard to properly decouple the return currents from the front side bus. Bulk decoupling must also be provided by the motherboard for proper [A]GTL+ bus operation.

Voltage Identification

The Voltage Identification (VID) specification for the processor is defined by the Voltage

Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop

LGA775 Socket. The voltage set by the VID signals is the reference VR output voltage to be delivered to the processor VCC lands (see Chapter 2.6.3

for V

CC

overshoot specifications). Refer to Table 12 for the DC specifications for these signals. Voltages for each processor frequency is provided in Table 4 .

To support the Deeper Sleep State the platform must use a VRD 11.1 compliant solution. The Deeper Sleep State also requires additional platform support.

Individual processor VID values may be calibrated during manufacturing such that two devices at the same core speed may have different default VID settings. This is reflected by the VID Range values provided in Table 4 . Refer to the Intel

®

Celeron

®

Processor E3000 Series Specification Update for further details on specific valid core frequency and VID values of the processor. Note that this differs from the VID employed by the processor during a power management event (Thermal Monitor 2,

Enhanced Intel SpeedStep

®

technology, or Extended HALT State).

The processor uses eight voltage identification signals, VID[7:0], to support automatic selection of power supply voltages. Table 2 specifies the voltage level corresponding to the state of VID[7:0]. A ‘1’ in this table refers to a high voltage level and a ‘0’ refers to a low voltage level. If the processor socket is empty (VID[7:0] = 11111110), or the voltage regulation circuit cannot supply the voltage that is requested, it must disable itself.

The processor provides the ability to operate while transitioning to an adjacent VID and its associated processor core voltage (V

CC

). This will represent a DC shift in the load line. It should be noted that a low-to-high or high-to-low voltage state change may result in as many VID transitions as necessary to reach the target core voltage.

Transitions above the specified VID are not permitted. Table 4 includes VID step sizes and DC shift ranges. Minimum and maximum voltages must be maintained as shown in

Table 5 , and Figure 1 , as measured across the VCC_SENSE and VSS_SENSE lands.

The VRM or VRD used must be capable of regulating its output to the value defined by the new VID. DC specifications for dynamic VID transitions are included in Table 4 and

Table 5 . Refer to the Voltage Regulator Design Guide for further details.

14 Datasheet

Electrical Specifications

Table 2.

Voltage Identification Definition

VID

7

VID

6

VID

5

VID

4

VID

3

VID

2

VID

1

VID

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

1

1

1

1

1

1

0

0

0

0

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

0

0

0

0

1

1

1

1

1

1

0

0

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

0

0

1

1

0

0

1

1

0

0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Voltage

1.4125

1.4

1.3875

1.375

1.3625

1.35

1.3375

1.325

1.3125

1.3

1.2875

1.275

1.2625

1.25

1.2375

1.225

OFF

1.6

1.5875

1.575

1.5625

1.55

1.5375

1.525

1.5125

1.5

1.4875

1.475

1.4625

1.45

1.4375

1.425

1.2125

1.2

1.1875

1.175

1.1625

1.15

1.1375

1.125

1.1125

1.1

1.0875

1.075

1.0625

1.05

VID

7

VID

6

VID

5

VID

4

VID

3

VID

2

VID

1

VID

0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

0

1

1

1

1

1

1

0

0

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

1

1

0

0

0

0

0

0

1

1

1

1

0

0

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

0

0

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Voltage

0.8375

0.825

0.8125

0.8

0.7875

0.775

0.7625

0.75

0.7375

0.725

0.7125

0.7

0.6875

0.675

0.6625

0.65

1.0375

1.025

1.0125

1

0.9875

0.975

0.9625

0.95

0.9375

0.925

0.9125

0.9

0.8875

0.875

0.8625

0.85

0.6375

0.625

0.6125

0.6

0.5875

0.575

0.5625

0.55

0.5375

0.525

0.5125

0.5

OFF

Datasheet 15

Electrical Specifications

2.4

2.5

Reserved, Unused, and TESTHI Signals

All RESERVED lands must remain unconnected. Connection of these lands to V

CC

V

TT, or incompatibility with future processors. See Chapter 4 for a land listing of the

, V

SS

,

or to any other signal (including each other) can result in component malfunction processor and the location of all RESERVED lands.

In a system level design, on-die termination has been included by the processor to allow signals to be terminated within the processor silicon. Most unused GTL+ inputs should be left as no connects as GTL+ termination is provided on the processor silicon.

However, see Table 7 for details on GTL+ signals that do not include on-die termination.

Unused active high inputs, should be connected through a resistor to ground (V

SS

).

Unused outputs can be left unconnected, however this may interfere with some TAP functions, complicate debug probing, and prevent boundary scan testing. A resistor must be used when tying bidirectional signals to power or ground. When tying any signal to power or ground, a resistor will also allow for system testability. Resistor values should be within ± 20% of the impedance of the motherboard trace for front side bus signals. For unused GTL+ input or I/O signals, use pull-up resistors of the same value as the on-die termination resistors (R

TT

). For details see Table 14 .

TAP and CMOS signals do not include on-die termination. Inputs and used outputs must be terminated on the motherboard. Unused outputs may be terminated on the motherboard or left unconnected. Note that leaving unused outputs unterminated may interfere with some TAP functions, complicate debug probing, and prevent boundary scan testing.

All TESTHI[12,10:0] lands should be individually connected to V

TT resistor that matches the nominal trace impedance.

using a pull-up

The TESTHI signals may use individual pull-up resistors or be grouped together as detailed below. A matched resistor must be used for each group:

• TESTHI[1:0]

• TESTHI[7:2]

• TESTHI8/FC42 – cannot be grouped with other TESTHI signals

• TESTHI9/FC43 – cannot be grouped with other TESTHI signals

• TESTHI10 – cannot be grouped with other TESTHI signals

• TESTHI12/FC44 – cannot be grouped with other TESTHI signals

Terminating multiple TESTHI pins together with a single pull-up resistor is not recommended for designs supporting boundary scan for proper Boundary Scan testing of the TESTHI signals. For optimum noise margin, all pull-up resistor values used for

TESTHI[12,10:0] lands should have a resistance value within ± 20% of the impedance of the board transmission line traces. For example, if the nominal trace impedance is

50 , then a value between 40 and 60 should be used.

Power Segment Identifier (PSID)

Power Segment Identifier (PSID) is a mechanism to prevent booting under mismatched power requirement situations. The PSID mechanism enables BIOS to detect if the processor in use requires more power than the platform voltage regulator (VR) is capable of supplying. For example, a 130 W TDP processor installed in a board with a

65 W or 95 W TDP capable VR may draw too much power and cause a potential VR issue.

16 Datasheet

Electrical Specifications

2.6

2.6.1

Table 3.

Voltage and Current Specification

Absolute Maximum and Minimum Ratings

Table 3 specifies absolute maximum and minimum ratings only and lie outside the functional limits of the processor. Within functional operation limits, functionality and long-term reliability can be expected.

At conditions outside functional operation condition limits, but within absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected. If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits, but within the absolute maximum and minimum ratings, the device may be functional, but with its lifetime degraded depending on exposure to conditions exceeding the functional operation condition limits.

At conditions exceeding absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected. Moreover, if a device is subjected to these conditions for any length of time then, when returned to conditions within the functional operating condition limits, it will either not function, or its reliability will be severely degraded.

Although the processor contains protective circuitry to resist damage from static electric discharge, precautions should always be taken to avoid high static voltages or electric fields.

Absolute Maximum and Minimum Ratings

Symbol

V

CC

V

TT

T

CASE

Parameter

Core voltage with respect to

V

SS

FSB termination voltage with respect to V

SS

Processor case temperature

Min

–0.3

–0.3

See Section 5

T

STORAGE

Processor storage temperature

–40

Max

1.45

1.45

See

Section 5

85

Unit Notes

1, 2

V

V

°C

°C

-

-

-

3, 4, 5

NOTES:

1.

For functional operation, all processor electrical, signal quality, mechanical and thermal

2.

specifications must be satisfied.

Excessive overshoot or undershoot on any signal will likely result in permanent damage to

3.

the processor.

Storage temperature is applicable to storage conditions only. In this scenario, the processor must not receive a clock, and no lands can be connected to a voltage bias.

Storage within these limits will not affect the long-term reliability of the device. For

4.

5.

functional operation, refer to the processor case temperature specifications.

This rating applies to the processor and does not include any tray or packaging.

Failure to adhere to this specification can affect the long term reliability of the processor.

Datasheet 17

Electrical Specifications

2.6.2

DC Voltage and Current Specification

Table 4.

Voltage and Current Specifications

Symbol Parameter

VID Range

Core V

V

V

I

V

CC_BOOT

CCPLL

CC

TT

CC

VID

Processor Number

(1 MB Cache):

E3500

E3400

E3300

E3200

V

CC

for

775_VR_CONFIG_06:

2.70 GHz

2.60 GHz

2.50 GHz

2.40 GHz

Default V

CC

voltage for initial power up

PLL V

CC

Processor Number

(1 MB Cache):

E3500

E3400

E3300

E3200

V

CC

for

775_VR_CONFIG_06:

2.70 GHz

2.60 GHz

2.50 GHz

2.40 GHz

FSB termination voltage

(DC + AC specifications) on Intel 3 series

Chipset family boards on Intel 4 series

Chipset family boards

VTT_OUT_LEFT and

VTT_OUT_RIGHT

I

CC

DC Current that may be drawn from

VTT_OUT_LEFT and VTT_OUT_RIGHT per land

I

I

I

TT

CC_VCCPLL

CC_GTLREF

I

CC

for V

TT

supply before V

CC

stable

I

CC

for V

TT

supply after V

CC

stable

I

CC

for PLL land

I

CC

for GTLREF

Min

0.8500

Refer to

—

- 5%

—

1.045

1.14

—

—

—

—

Typ

—

Table 5

1.10

1.50

—

1.1

1.2

—

—

—

—

,

Max

1.3625

Figure 1

—

+ 5%

75

75

75

75

1.155

1.26

580

4.5

4.6

130

200

Unit Notes

V

V

V

V

A

V mA

A mA

µA

1

3, 4, 5

6

7, 8

9

2, 10

NOTES:

1.

Each processor is programmed with a maximum valid voltage identification value (VID) that is set at manufacturing and can not be altered. Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have

2.

different settings within the VID range. Note that this differs from the VID employed by the processor during a power management event (Thermal Monitor 2, Enhanced Intel

SpeedStep

®

technology, or Extended HALT State).

Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical data. These specifications will be updated with characterized data from silicon measurements at a later date.

3.

4.

These voltages are targets only. A variable voltage source should exist on systems in the event that a different voltage is required. See Section 2.3

and Table 2 for more information.

The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE lands at the socket with a 100 MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1 M minimum impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled into the oscilloscope probe.

18 Datasheet

Electrical Specifications

Table 5.

5.

6.

7.

8.

9.

10.

Refer to Table 5 and Figure 1 , for the minimum, typical, and maximum V

CC

allowed for a given current. The processor should not be subjected to any V wherein V

CC

exceeds V

CC_MAX

for a given current.

CC

and I

CC

combination

I

CC_MAX specification is based on V

V

TT

CC_

MAX

loadline. Refer to Figure 1 for details.

must be provided using a separate voltage source and not be connected to V

CC

. This specification is measured at the land.

Baseboard bandwidth is limited to 20 MHz.

This is the maximum total current drawn from the V

TT

plane by only the processor. This specification does not include the current coming from on-board termination (R

TT

), through the signal line. Refer to the Voltage Regulator Design Guide to determine the total

I

TT

drawn by the system. This parameter is based on design characterization and is not tested.

Adherence to the voltage specifications for the processor are required to ensure reliable processor operation.

Processor V

CC

Static and Transient Tolerance

Voltage Deviation from VID Setting (V)

1, 2, 3, 4

I

CC

(A)

Maximum Voltage

1.65 m

Typical Voltage

1.73 m

Minimum Voltage

1.80 m

60

65

70

75

40

45

50

55

20

25

30

35

0

5

10

15

-0.066

-0.074

-0.083

-0.091

-0.099

-0.107

-0.116

-0.124

0.000

-0.008

-0.017

-0.025

-0.033

-0.041

-0.050

-0.058

-0.088

-0.097

-0.105

-0.114

-0.123

-0.131

-0.140

-0.148

-0.019

-0.028

-0.036

-0.045

-0.054

-0.062

-0.071

-0.079

-0.110

-0.119

-0.128

-0.137

-0.146

-0.155

-0.164

-0.173

-0.038

-0.047

-0.056

-0.065

-0.074

-0.083

-0.092

-0.101

NOTES:

1.

The loadline specification includes both static and transient limits except for overshoot allowed as shown in

Section 2.6.3

.

2.

This table is intended to aid in reading discrete points on Figure 1 .

3.

The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE lands. Voltage regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS lands. Refer to the Voltage Regulator Design Guide for socket loadline guidelines and VR implementation details.

4.

Adherence to this loadline specification is required to ensure reliable processor operation.

Datasheet 19

Electrical Specifications

Figure 1.

2.6.3

Table 6.

Processor V

CC

Static and Transient Tolerance

VID - 0.000

0

VID - 0.013

VID - 0.025

VID - 0.038

VID - 0.050

VID - 0.063

VID - 0.075

VID - 0.088

VID - 0.100

VID - 0.113

VID - 0.125

VID - 0.138

VID - 0.150

VID - 0.163

VID - 0.175

VID - 0.188

5 10 15

Vcc Typical

20 25 30

Vcc Minimum

35

Icc [A]

40 45 50

Vcc Maximum

55 60 65 70 75

NOTES:

1.

The loadline specification includes both static and transient limits except for overshoot allowed as shown in

Section 2.6.3

.

2.

This loadline specification shows the deviation from the VID set point.

3.

The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE lands. Voltage regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS lands. Refer to the Voltage Regulator Design Guide for socket loadline guidelines and VR implementation details.

V

CC

Overshoot

The processor can tolerate short transient overshoot events where V

CC

exceeds the VID voltage when transitioning from a high to low current load condition. This overshoot cannot exceed VID + V

OS_MAX

(V

OS_MAX

is the maximum allowable overshoot voltage).

The time duration of the overshoot event must not exceed T

OS_MAX

(T

OS_MAX

is the maximum allowable time duration above VID). These specifications apply to the processor die voltage as measured across the VCC_SENSE and VSS_SENSE lands.

V

CC

Overshoot Specifications

Symbol Parameter Min Max Unit Figure Notes

V

OS_MAX

Magnitude of V

CC

VID

overshoot above

— 50 mV 2

1

T

OS_MAX

Time duration of V

CC

overshoot above

VID

— 25 µs 2

NOTES:

1.

Adherence to these specifications is required to ensure reliable processor operation.

1

20 Datasheet

Electrical Specifications

Figure 2.

V

CC

Overshoot Example Waveform

Example Overshoot Waveform

V

OS

VID + 0.050

VID - 0.000

2.6.4

2.7

0 5

T

OS

10

Time [us]

15

T

OS

: Overshoot time above VID

V

OS

: Overshoot above VID

20 25

NOTES:

1.

2.

V

OS

is measured overshoot voltage.

T

OS

is measured time duration above VID.

Die Voltage Validation

Overshoot events on processor must meet the specifications in Table 6 when measured across the VCC_SENSE and VSS_SENSE lands. Overshoot events that are < 10 ns in duration may be ignored. These measurements of processor die level overshoot must be taken with a bandwidth limited oscilloscope set to a greater than or equal to 100

MHz bandwidth limit.

Signaling Specifications

Most processor Front Side Bus signals use Gunning Transceiver Logic (GTL+) signaling technology. This technology provides improved noise margins and reduced ringing through low voltage swings and controlled edge rates. Platforms implement a termination voltage level for GTL+ signals defined as V

TT

. Because platforms implement separate power planes for each processor (and chipset), separate V

CC

and V

TT supplies are necessary. This configuration allows for improved noise tolerance as processor frequency increases. Speed enhancements to data and address busses have caused signal integrity considerations and platform design methods to become even more critical than with previous processor families.

The GTL+ inputs require a reference voltage (GTLREF) that is used by the receivers to determine if a signal is a logical 0 or a logical 1. GTLREF must be generated on the motherboard (see Table 14 for GTLREF specifications). Termination resistors (R

TT

GTL+ signals are provided on the processor silicon and are terminated to V

) for

TT

. Intel chipsets will also provide on-die termination, thus eliminating the need to terminate the bus on the motherboard for most GTL+ signals.

Datasheet 21

Electrical Specifications

2.7.1

Table 7.

FSB Signal Groups

The front side bus signals have been combined into groups by buffer type. GTL+ input signals have differential input buffers that use GTLREF[1:0] as a reference level. In this document, the term “GTL+ Input” refers to the GTL+ input group as well as the GTL+

I/O group when receiving. Similarly, “GTL+ Output” refers to the GTL+ output group as well as the GTL+ I/O group when driving.

With the implementation of a source synchronous data bus comes the need to specify two sets of timing parameters. One set is for common clock signals that are dependent upon the rising edge of BCLK0 (ADS#, HIT#, HITM#, and so on) and the second set is for the source synchronous signals that are relative to their respective strobe lines

(data and address) as well as the rising edge of BCLK0. Asychronous signals are still present (A20M#, IGNNE#, and so on) and can become active at any time during the clock cycle. Table 7 identifies which signals are common clock, source synchronous, and asynchronous.

FSB Signal Groups

Signals

1

Signal Group

GTL+ Common

Clock Input

GTL+ Common

Clock I/O

Type

Synchronous to

BCLK[1:0]

Synchronous to

BCLK[1:0]

BPRI#, DEFER#, RESET#, RS[2:0]#, TRDY#

ADS#, BNR#, BPM[5:0]#, BR0#

3

, DBSY#, DRDY#,

HIT#, HITM#, LOCK#

GTL+ Source

Synchronous I/O

Synchronous to assoc. strobe

Signals

REQ[4:0]#, A[16:3]#

3

A[35:17]#

3

D[15:0]#, DBI0#

D[31:16]#, DBI1#

D[47:32]#, DBI2#

D[63:48]#, DBI3#

Associated Strobe

ADSTB0#

ADSTB1#

DSTBP0#, DSTBN0#

DSTBP1#, DSTBN1#

DSTBP2#, DSTBN2#

DSTBP3#, DSTBN3#

GTL+ Strobes

Synchronous to

BCLK[1:0]

ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#

CMOS

A20M#, DPRSTP#. DPSLP#, IGNNE#, INIT#, LINT0/

INTR, LINT1/NMI, SMI#

3

, STPCLK#, PWRGOOD, SLP#,

TCK, TDI, TMS, TRST#, BSEL[2:0], VID[7:0], PSI#

FERR#/PBE#, IERR#, THERMTRIP#, TDO Open Drain Output

Open Drain Input/

Output

FSB Clock

PROCHOT#

4

Power/Other

Clock BCLK[1:0], ITP_CLK[1:0]

2

VCC, VTT, VCCA, VCCIOPLL, VCCPLL, VSS, VSSA,

GTLREF[1:0], COMP[8,3:0], RESERVED,

TESTHI[12,10:0], VCC_SENSE,

VCC_MB_REGULATION, VSS_SENSE,

VSS_MB_REGULATION, DBR#

2

, VTT_OUT_LEFT,

VTT_OUT_RIGHT, VTT_SEL, FCx, PECI, MSID[1:0]

NOTES:

1.

Refer to Section 4.2

for signal descriptions.

2.

In processor systems where no debug port is implemented on the system board, these signals are used to support a debug port interposer. In systems with the debug port implemented on the system board, these signals are no connects.

22 Datasheet

Electrical Specifications

.

Table 8.

Table 9.

2.7.2

3.

4.

The value of these signals during the active-to-inactive edge of RESET# defines the processor configuration options. See Section 6.1

for details.

PROCHOT# signal type is open drain output and CMOS input.

Signal Characteristics

Signals with R

TT

A[35:3]#, ADS#, ADSTB[1:0]#, BNR#, BPRI#,

D[63:0]#, DBI[3:0]#, DBSY#, DEFER#,

DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, HIT#,

HITM#, LOCK#, PROCHOT#, REQ[4:0]#,

RS[2:0]#, TRDY#

Signals with No R

TT

A20M#, BCLK[1:0], BPM[5:0]#, BSEL[2:0],

COMP[8,3:0], FERR#/PBE#, IERR#, IGNNE#,

INIT#, ITP_CLK[1:0], LINT0/INTR, LINT1/

NMI, MSID[1:0], PWRGOOD, RESET#, SMI#,

STPCLK#, TDO, TESTHI[12,10:0],

THERMTRIP#, VID[7:0], GTLREF[1:0], TCK,

TDI, TMS, TRST#, VTT_SEL

Open Drain Signals

1

THERMTRIP#, FERR#/PBE#, IERR#, BPM[5:0]#,

BR0#, TDO, FCx

NOTES:

1.

Signals that do not have R

TT

, nor are actively driven to their high-voltage level.

Signal Reference Voltages

GTLREF V

TT

/2

BPM[5:0]#, RESET#, BNR#, HIT#, HITM#, BR0#,

A[35:0]#, ADS#, ADSTB[1:0]#, BPRI#, D[63:0]#,

DBI[3:0]#, DBSY#, DEFER#, DRDY#, DSTBN[3:0]#,

DSTBP[3:0]#, LOCK#, REQ[4:0]#, RS[2:0]#,

TRDY#

A20M#, LINT0/INTR, LINT1/NMI,

IGNNE#, INIT#, PROCHOT#,

PWRGOOD

1

, SMI#, STPCLK#, TCK

1

,

TDI

1

, TMS

1

, TRST#

1

NOTE:

1.

See Table 11 for more information.

CMOS and Open Drain Signals

Legacy input signals such as A20M#, IGNNE#, INIT#, SMI#, and STPCLK# use CMOS input buffers. All of the CMOS and Open Drain signals are required to be asserted/deasserted for at least eight BCLKs for the processor to recognize the proper signal state.

See Section 2.7.3

for the DC specifications. See Section 6.2

for additional timing requirements for entering and leaving the low power states.

Datasheet 23

Electrical Specifications

2.7.3

Table 10.

Table 11.

Processor DC Specifications

The processor DC specifications in this section are defined at the processor core (pads) unless otherwise stated. All specifications apply to all frequencies and cache sizes unless otherwise stated.

GTL+ Signal Group DC Specifications

Symbol Parameter Min Max Unit Notes

1

V

V

V

I

IL

IH

OH

OL

Input Low Voltage

Input High Voltage

Output High Voltage

Output Low Current

-0.10

GTLREF + 0.10

V

TT

– 0.10

N/A

GTLREF – 0.10

V

TT

+ 0.10

V

TT

V

TT_MAX

/

[(R

TT_MIN

) + (2 * R

ON_MIN

)]

V

V

V

A

2, 5

3, 4, 5

4, 5

-

I

I

LI

LO

Input Leakage

Current

Output Leakage

Current

Buffer On Resistance

N/A

N/A

± 100

± 100

µA

µA

6

7

R

ON

7.49

9.16

NOTES:

1.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2.

3.

4.

5.

6.

7.

V

IL

is defined as the voltage range at a receiving agent that will be interpreted as a logical low value.

V

IH

is defined as the voltage range at a receiving agent that will be interpreted as a logical high value.

V

IH

and V

The V

TT

OH

may experience excursions above V

TT

.

referred to in these specifications is the instantaneous V

TT

.

Leakage to V

SS

with land held at V

TT

.

Leakage to V

TT

with land held at 300 mV.

Open Drain and TAP Output Signal Group DC Specifications

Symbol

V

OL

I

OL

I

LO

Parameter

Output Low Voltage

Output Low Current

Output Leakage Current

Min

0

16

N/A

Max

0.20

50

± 200

Unit Notes

1

V mA

µA

-

2

3

NOTES:

1.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2.

3.

Measured at V

TT

* 0.2 V.

For Vin between 0 and V

OH

.

24 Datasheet

Electrical Specifications

Table 12.

2.7.3.1

CMOS Signal Group DC Specifications

Symb ol

V

IL

V

IH

V

OL

V

OH

I

OL

I

OH

I

LI

I

LO

Parameter

Input Low Voltage

Input High Voltage

Output Low Voltage

Output High Voltage

Output Low Current

Output Low Current

Input Leakage Current

Output Leakage Current

Min Max

-0.10

V

TT

* 0.70

-0.10

0.90 * V

TT

V

TT

* 0.30

V

TT

+ 0.10

V

TT

* 0.10

V

TT

+ 0.10

V

TT

* 0.10 / 67 V

TT

* 0.10 / 27

V

TT

* 0.10 / 67 V

TT

* 0.10 / 27

N/A ± 100

N/A ± 100

Unit Notes

1

V

A

A

µA

µA

V

V

V

5.

6.

7.

8.

9.

NOTES:

1.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2.

3.

All outputs are open drain.

V

IL

is defined as the voltage range at a receiving agent that will be interpreted as a logical low value.

4.

V

IH

is defined as the voltage range at a receiving agent that will be interpreted as a logical high value.

V

IH

and V

OH

may experience excursions above V

TT

.

The V

I

OL

TT

referred to in these specifications refers to instantaneous V

TT

.

is measured at 0.10 * V

TT.

I

OH is measured at 0.90 * V

TT.

Leakage to V

SS

with land held at V

TT

.

Leakage to V

TT

with land held at 300 mV.

3, 6

4, 5, 6

6

2, 5, 6

6, 7

6, 7

8

9

Platform Environment Control Interface (PECI) DC Specifications

PECI is an Intel proprietary one-wire interface that provides a communication channel between Intel processors, chipsets, and external thermal monitoring devices. The processor contains Digital Thermal Sensors (DTS) distributed throughout die. These sensors are implemented as analog-to-digital converters calibrated at the factory for reasonable accuracy to provide a digital representation of relative processor temperature. PECI provides an interface to relay the highest DTS temperature within a die to external management devices for thermal/fan speed control. More detailed information may be found in the Platform Environment Control Interface (PECI)

Specification.

Datasheet 25

Electrical Specifications

Table 13.

PECI DC Electrical Limits

Symbol Definition and Conditions Min Max Units Notes

1

V in

V hysteresis

V n

V p

Input Voltage Range

Hysteresis

Negative-edge threshold voltage

Positive-edge threshold voltage

-0.15

0.1 * V

TT

0.275 * V

TT

0.550 * V

TT

V

TT

—

0.500 * V

TT

0.725 * V

TT

V

V

V

V

2

I source

I sink

I leak+

I leak-

High level output source

(V

OH

= 0.75 * V

TT)

Low level output sink

(V

OL

= 0.25 * V

TT

)

High impedance state leakage to V

High impedance leakage to GND

TT

-6.0

0.5

N/A

N/A

N/A

1.0

50

10 mA mA

µA

µA

3

3

C bus

Bus capacitance per node N/A 10 pF 4

V noise

Signal noise immunity above 300

MHz

0.1 * V

TT

— V p-p

NOTES:

1. V

TT

V

TT

supplies the PECI interface. PECI behavior does not affect V

TT

min/max specifications. Refer to Table 4 for

specifications.

2. The leakage specification applies to powered devices on the PECI bus.

3. The input buffers use a Schmitt-triggered input design for improved noise immunity.

4. One node is counted for each client and one node for the system host. Extended trace lengths might appear as additional nodes.

.

2.7.3.2

GTL+ Front Side Bus Specifications

In most cases, termination resistors are not required as these are integrated into the processor silicon. See Table 8 for details on which GTL+ signals do not include on-die termination.

Valid high and low levels are determined by the input buffers by comparing with a reference voltage called GTLREF. Table 14 lists the GTLREF specifications. The GTL+ reference voltage (GTLREF) should be generated on the system board using high precision voltage divider circuits.

26 Datasheet

Electrical Specifications

Table 14.

2.8

2.8.1

GTL+ Bus Voltage Definitions

Symbol

GTLREF_PU

GTLREF_PD

R

TT

COMP[3:0]

COMP8

Parameter

GTLREF pull up on Intel

®

3 Series Chipset family boards

GTLREF pull down on

Intel

®

3 Series Chipset family boards

Termination Resistance

COMP Resistance

COMP Resistance

Min

57.6 * 0.99

100 * 0.99

45

49.40

24.65

Typ

57.6

100

Max

57.6 * 1.01

100 * 1.01

Units Notes

1

2

2

50

49.90

24.90

55

50.40

25.15

3

4

4

NOTES:

1.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2.

GTLREF is to be generated from V

TT

by a voltage divider of 1% resistors. If an Adjustable

GTLREF circuit is used on the board (for Quad-Core processors compatibility) the two

GTLREF lands connected to the Adjustable GTLREF circuit require the following:

GTLREF_PU = 50 , GTLREF_PD = 100

3.

4.

R

TT

is the on-die termination resistance measured at V

TT

/3 of the GTL+ output driver.

COMP resistance must be provided on the system board with 1% resistors. COMP[3:0] and

COMP8 resistors are to V

SS

.

Clock Specifications

Front Side Bus Clock (BCLK[1:0]) and Processor Clocking

BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the processor. As in previous generation processors, the processor’s core frequency is a multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier will be set at its default ratio during manufacturing. The processor supports Half Ratios between 7.5 and 13.5, refer to Table 15 for the processor supported ratios.

The processor uses a differential clocking implementation. For more information on the processor clocking, contact your Intel field representative.

Datasheet 27

Electrical Specifications

Table 15.

2.8.2

Core Frequency to FSB Multiplier Configuration

Multiplication of System

Core Frequency to FSB

Frequency

1/6

1/7

1/7.5

1/8

1/8.5

1/9

1/9.5

1/10

1/10.5

1/11

1/11.5

1/12

1/12.5

1/13

1/13.5

1/14

1/15

Core Frequency

(200 MHz BCLK/

800 MHz FSB)

1.20 GHz

1.40 GHz

1.5 GHz

1.60 GHz

1.70 GHz

1.80 GHz

1.90 GHz

2 GHz

2.1 GHz

2.2 GHz

2.3 GHz

2.4 GHz

2.5 GHz

2.6 GHz

2.7 GHz

2.8 GHz

3 GHz

Notes

1, 2

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

NOTES:

1.

Individual processors operate only at or below the rated frequency.

2.

Listed frequencies are not necessarily committed production frequencies.

FSB Frequency Select Signals (BSEL[2:0])

The BSEL[2:0] signals are used to select the frequency of the processor input clock

(BCLK[1:0]).

Table 16 defines the possible combinations of the signals and the frequency associated with each combination. The required frequency is determined by the processor, chipset, and clock synthesizer. All agents must operate at the same frequency.

The Intel

®

Celeron

®

processor E3000 series operates at a 800 MHz FSB frequency

(selected by a 200 MHz BCLK[1:0] frequency). Individual processors will only operate at their specified FSB frequency.

For more information about these signals, refer to Section 4.2

.

28 Datasheet

Electrical Specifications

Table 16.

2.8.3

2.8.4

BSEL[2:0] Frequency Table for BCLK[1:0]

BSEL2

H

H

H

H

L

L

L

L

BSEL1

L

L

H

H

H

H

L

L

BSEL0

H

L

L

H

H

L

L

H

FSB Frequency

Reserved

Reserved

Reserved

200 MHz

Reserved

Reserved

Reserved

Reserved

Phase Lock Loop (PLL) and Filter

An on-die PLL filter solution will be implemented on the processor. The VCCPLL input is used for the PLL. Refer to Table 4 for DC specifications.

BCLK[1:0] Specifications

Table 17.

Front Side Bus Differential BCLK Specifications

Symbol

V

L

V

H

V

CROSS(abs)

V

CROSS

V

OS

V

US

V

SWING

Parameter

Input Low Voltage

Input High Voltage

Absolute Crossing Point

Range of Crossing Points

Overshoot

Undershoot

Differential Output Swing

Min

-0.30

N/A

0.300

N/A

N/A

-0.300

0.300

Typ

N/A

N/A

N/A

N/A

N/A

N/A

N/A

Max

N/A

1.15

0.550

0.140

1.4

N/A

N/A

Unit Figure Notes

1

V

V

V

V

V

V

V

3

3

3

3

3

3

4

2

-

3

3

4

NOTES:

1.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2.

Crossing voltage is defined as the instantaneous voltage value when the rising edge of

BCLK0 equals the falling edge of BCLK1.

3.

4.

5.

“Steady state” voltage, not including overshoot or undershoot.

Overshoot is defined as the absolute value of the maximum voltage. Undershoot is defined as the absolute value of the minimum voltage.

Measurement taken from differential waveform.

Datasheet 29

Electrical Specifications

Table 18.

FSB Differential Clock Specifications (800 MHz FSB)

T# Parameter

BCLK[1:0] Frequency

T1: BCLK[1:0] Period

T2: BCLK[1:0] Period Stability

T5: BCLK[1:0] Rise and Fall Slew Rate

Min

198.980

4.99950

—

2.5

Nom

—

—

—

—

Max

200.020

5.00050

150

8

Unit Figure Notes

1

MHz -

2

3 ns ps

3

3

4

V/nS 3

5

%

6

T6: Slew Rate Matching N/A N/A 20

NOTES:

1.

2.

3.

4.

5.

6.

Unless otherwise noted, all specifications in this table apply to all processor core frequencies based on a 200 MHz BCLK[1:0].

Duty Cycle (High time/Period) must be between 40 and 60%.

The period specified here is the average period. A given period may vary from this specification as governed by the period stability specification (T2). Min period specification is based on -

300 PPM deviation from a 5 ns period. Max period specification is based on the summation of

+300 PPM deviation from a 5 ns period and a +0.5% maximum variance due to spread spectrum clocking.

In this context, period stability is defined as the worst case timing difference between successive crossover voltages. In other words, the largest absolute difference between adjacent clock periods must be less than the period stability.

Measurement taken from differential waveform.

Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a ±75 mV window centered on the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. Slew rate matching is a single ended measurement.

Figure 3.

Differential Clock Waveform

Threshold

Region

Tph

BCLK1

BCLK0

V

CRO SS (ABS

) V

CRO SS (ABS

)

Tpl

Tp

Tp = T1: BCLK[1:0] period

T2: BCLK[1:0] period stability (not shown)

Tph = T3: BCLK[1:0] pulse high time

Tpl = T4: BCLK[1:0] pulse low time

T5: BCLK[1:0] rise time through the threshold region

T6: BCLK[1:0] fall time through the threshold region

Ringback

Margin

Overshoot

VH

Rising Edge

Ringback

Falling Edge

Ringback

VL

Undershoot

30 Datasheet

Electrical Specifications

Figure 4.

Measurement Points for Differential Clock Waveforms

Slew_rise Slew _fall

+150 mV

0.0V

-150 mV

Diff

V_swing

T5 = BCLK[1:0] rise and fall time through the swing region

+150mV

0.0V

-150mV

§ §

Datasheet 31

Electrical Specifications

32 Datasheet

Package Mechanical Specifications

3 Package Mechanical

Specifications

Figure 5.

The processor is packaged in a Flip-Chip Land Grid Array (FC-LGA8) package that interfaces with the motherboard using an LGA775 socket. The package consists of a processor core mounted on a substrate land-carrier. An integrated heat spreader (IHS) is attached to the package substrate and core and serves as the mating surface for processor component thermal solutions, such as a heatsink. Figure 5 shows a sketch of the processor package components and how they are assembled together. Refer to the

LGA775 Socket Mechanical Design Guide for complete details on the LGA775 socket.

The package components shown in Figure 5 include the following:

• Integrated Heat Spreader (IHS)

• Thermal Interface Material (TIM)

• Processor core (die)

• Package substrate

• Capacitors

Processor Package Assembly Sketch

Substrate

IHS

Core (die) TIM

3.1

Capacitors

LGA775 Socket

System Board

Processor_Pkg_Assembly_775

NOTE:

1.

Socket and motherboard are included for reference and are not part of processor package.

Package Mechanical Drawing

The package mechanical drawings are shown in Figure 6 and Figure 7 . The drawings include dimensions necessary to design a thermal solution for the processor. These dimensions include:

• Package reference with tolerances (total height, length, width, and so on)

• IHS parallelism and tilt

• Land dimensions

• Top-side and back-side component keep-out dimensions

• Reference datums

• All drawing dimensions are in mm [in].

• Guidelines on potential IHS flatness variation with socket load plate actuation and installation of the cooling solution is available in the processor Thermal and

Mechanical Design Guidelines.

Datasheet 33

Figure 6.

Processor Package Drawing Sheet 1 of 3

Package Mechanical Specifications

34 Datasheet

Package Mechanical Specifications

Figure 7.

Processor Package Drawing Sheet 2 of 3

Datasheet 35

Figure 8.

Processor Package Drawing Sheet 3 of 3

Package Mechanical Specifications

36 Datasheet

Package Mechanical Specifications

3.2

3.3

.

Table 19.

Processor Component Keep-Out Zones

The processor may contain components on the substrate that define component keepout zone requirements. A thermal and mechanical solution design must not intrude into the required keep-out zones. Decoupling capacitors are typically mounted to either the topside or land-side of the package substrate. See Figure 6 and Figure 7 for keep-out zones. The location and quantity of package capacitors may change due to manufacturing efficiencies but will remain within the component keep-in.

Package Loading Specifications

Table 19 provides dynamic and static load specifications for the processor package.

These mechanical maximum load limits should not be exceeded during heatsink assembly, shipping conditions, or standard use condition. Also, any mechanical system or component testing should not exceed the maximum limits. The processor package substrate should not be used as a mechanical reference or load-bearing surface for thermal and mechanical solution. The minimum loading specification must be maintained by any thermal and mechanical solutions.

Processor Loading Specifications

Parameter

Static

Dynamic

Minimum

80 N [17 lbf]

-

Maximum

311 N [70 lbf]

756 N [170 lbf]

Notes

1, 2, 3

1, 3, 4

NOTES:

1.

These specifications apply to uniform compressive loading in a direction normal to the processor IHS.

2.

3.

This is the maximum force that can be applied by a heatsink retention clip. The clip must also provide the minimum specified load on the processor package.

These specifications are based on limited testing for design characterization. Loading limits

4.

are for the package only and do not include the limits of the processor socket.

Dynamic loading is defined as an 11 ms duration average load superimposed on the static load requirement.

3.4

Table 20.

Package Handling Guidelines

Table 20 includes a list of guidelines on package handling in terms of recommended maximum loading on the processor IHS relative to a fixed substrate. These package handling loads may be experienced during heatsink removal.

Package Handling Guidelines

Parameter Maximum Recommended Notes

Shear

Tensile

Torque

311 N [70 lbf]

111 N [25 lbf]

3.95 N-m [35 lbf-in]

1, 4

2, 4

3, 4

NOTES:

1.

A shear load is defined as a load applied to the IHS in a direction parallel to the IHS top

2.

surface.

A tensile load is defined as a pulling load applied to the IHS in a direction normal to the

3.

4.

IHS surface.

A torque load is defined as a twisting load applied to the IHS in an axis of rotation normal to the IHS top surface.

These guidelines are based on limited testing for design characterization.

Datasheet 37

Package Mechanical Specifications

3.5

3.6

3.7

Table 21.

3.8

Figure 9.

Package Insertion Specifications

The processor can be inserted into and removed from a LGA775 socket 15 times. The socket should meet the LGA775 requirements detailed in the LGA775 Socket

Mechanical Design Guide.

Processor Mass Specification

The typical mass of the processor is 21.5 g [0.76 oz]. This mass [weight] includes all the components that are included in the package.

Processor Materials

Table 21 lists some of the package components and associated materials.

Processor Materials

Component

Integrated Heat Spreader

(IHS)

Substrate

Substrate Lands

Material

Nickel Plated Copper

Fiber Reinforced Resin

Gold Plated Copper

Processor Markings

Figure 9 shows the topside markings on the processor. This diagrams can be used to aid in the identification of the processor.

Intel

®

Celeron

®

Processor E3000 Series Top-Side Markings Example

Intel® Celeron®

SLGU4 [COO]

2.50GHZ/1M/800/06

[FPO]

e

4

ATPO

S/N

38 Datasheet

Package Mechanical Specifications

3.9

Processor Land Coordinates

Figure 10 shows the top view of the processor land coordinates. The coordinates are referred to throughout the document to identify processor lands.

.

Figure 10.

Processor Land Coordinates and Quadrants, Top View

V

CC

/

V

SS

30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

AE

AD

AC

AB

AA

Y

W

V

U

T

R

P

N

M

L

AN

AM

AL

AK

AJ

AH

AG

AF

F

E

D

C

B

A

K

J

H

G

Socket 775

Quadrants

Top View

30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

V

TT

/ Clocks Data

AE

AD

AC

AB

AA

Y

W

V

U

T

R

P

N

M

L

AN

AM

AL

AK

AJ

AH

AG

AF

K

J

H

G

F

E

D

C

B

A

Address/

Common Clock/

Async

§

Datasheet 39

Package Mechanical Specifications

40 Datasheet

Land Listing and Signal Descriptions

4

4.1

Land Listing and Signal

Descriptions

This chapter provides the processor land assignment and signal descriptions.

Processor Land Assignments

This section contains the land listings for the processor. The land-out footprint is shown in Figure 11 and Figure 12 . These figures represent the land-out arranged by land number and they show the physical location of each signal on the package land array

(top view). Table 22 lists the processor lands ordered alphabetically by land (signal) name. Table 23 lists the processor lands ordered numerically by land number.

Datasheet 41

Land Listing and Signal Descriptions

H

C

B

A

E

D

G

F

Y

R

P

N

M

L

K

J

W

V

U

T

AH

AG

AF

AE

AM

AL

AK

AJ

AD

AC

AB

AA

AN

Figure 11.

land-out Diagram (Top View – Left Side)

30 29 28 27 26 25 24 23 22 21

VCC VCC VSS VSS VCC VCC VSS VSS VCC VCC

VCC

VCC

VSS

VSS

VCC

VCC

VSS

VSS

VCC

VCC

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VCC

VCC

VCC

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VCC

VCC

VSS

VSS

VCC

VCC

VCC

VCC

VCC

VCC

VSS

VSS

VCC

VCC

VSS

VSS

VCC

VCC

VCC

VCC

VCC

VCC

VSS

VSS

VCC

VCC

VSS

VSS

VSS

VSS

VSS

VSS

VCC

VCC

VSS

VSS

VCC

VCC

VSS

VSS

VSS

VSS

VSS

VSS

VCC

VCC

VSS

VSS

VCC

VCC

VSS

VSS

VCC

VCC

VSS

VSS

VCC

VCC

VSS

VSS

VCC

VCC

VSS

VSS

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC VCC VCC

VSS

VCC

VCC

VSS

VCC

VCC

VSS

VCC

VCC

VSS

VCC

VSS

VCC

VCC

VSS

VCC

VCC

VSS

VCC

VCC

VSS

VCC

VSS

VCC

VCC

VSS

VCC

VCC

VSS

VCC

VCC

VSS

VCC

VCC

VSS

VCC

VCC

VSS

VCC

VCC

VSS

VCC

VCC

VSS

VCC

VSS

VCC

VCC

VSS

VCC

VCC

VSS

VCC

VCC

VSS

VCC

VSS

VCC

VCC

VSS

VCC

VCC

VSS

VCC

VCC

VSS

VCC

VSS

VCC

VCC

VSS

VCC

VCC

VSS

VCC

VCC

VSS

VCC

VSS

VCC

VCC

VSS

VCC

VCC

VSS

VCC

VCC

VSS

VCC

VCC VCC VCC VCC

VCC VCC

BSEL1 FC15 VSS VSS VSS VSS VSS VSS VSS

BSEL2 BSEL0 BCLK1 TESTHI4 TESTHI5 TESTHI3 TESTHI6 RESET# D47#

RSVD BCLK0 VTT_SEL TESTHI0 TESTHI2 TESTHI7 RSVD VSS

VTT

FC26

VTT

VSS

VTT

VSS

VTT

VSS

VTT

VSS

VTT

FC10

VSS

RSVD

VCCPLL

D45#

D46#

VTT

VTT

VTT

30

VTT

VTT

VTT

29

VTT

VTT

VTT

28

VTT

VTT

VTT

27

VTT

VTT

VTT

26

VTT

VTT

VTT

25

VSS

VSS

FC23

24

VCCIO

PLL

VSSA

VCCA

23

VSS

D63#

D62#

22

20

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VCC

19

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

18

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

17

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

FC34

16

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

FC31 VCC

VSS

D59#

VSS

21

VSS

VSS

RSVD

20

VSS

D60#

D61#

19

VSS

D57#

VSS

18

VSS FC33

D44# DSTBN2# DSTBP2# D35#

D43# D41# VSS D38#

D42#

VSS

VSS

D48#

D40#

DBI2#

D39#

VSS

D58# DBI3# VSS

D36#

D37#

VSS

D49#

D32#

VSS

D34#

RSVD

D54# DSTBP3# VSS

FC32

VSS D55# D53#

D56# DSTBN3# VSS

17 16 15

D31#

D30#

D33#

VSS

D51#

15

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

42 Datasheet

Land Listing and Signal Descriptions

Figure 12.

land-out Diagram (Top View – Right Side)

14 13 12 11 10 9

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

8

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

SKTOCC#

VCC

VCC

VCC

7 6 5

VID_SEL

ECT

VSS_MB_RE

GULATION

VCC_MB_

REGULATION

VID7

VSS

FC40

VID3

VID6

VID1

VSS

VSS

VSS

VSS

FC8

A35#

VSS

A29#

VSS

A34#

A33#

A31#

VSS

VSS

VSS

VSS

VSS

VSS

RSVD

A22#

VSS

A17#

A27#

VSS

ADSTB1#

A25#

A24#

4

VSS_

SENSE

VSS

VID5

VID4

VSS

A32#

A30#

A28#

RSVD

VSS

RSVD

A26#

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

A19#

A18#

VSS

A10#

VSS

ADSTB0#

A4#

VSS

REQ2#

VSS

REQ3#

REQ4#

VSS

A23#

VSS

A16#

A14#

A12#

A9#

VSS

RSVD

RSVD

A5#

A3#

VSS

REQ1#

TESTHI10

A21#

A20#

VSS

A15#

A13#

A11#

A8#

VSS

RSVD

A7#

A6#

REQ0#

VSS

FC35

3

VCC_

SENSE

2

VSS

VID2 VID0

VRDSEL PROCHOT#

ITP_CLK0

ITP_CLK1

VSS

BPM5#

VSS

FC18

FC36

VSS

FC37

VSS

PSII#

VSS

BPM0#

RSVD

BPM3#

BPM4#

VSS

BPM2#

DBR#

IERR#

FC39

VSS

1

VSS

AN

VSS

FC25

FC24

BPM1#

VSS

TRST#

TDO

TCK

TDI

TMS

VSS

VTT_OUT_

RIGHT

AA

FC0/

BOOTSELECT

Y

AH

AG

AF

AE

AM

AL

AK

AJ

AD

AC

AB

TESTHI1

VSS

FC30

VSS

FERR#/

PBE#

TESTHI12/

FC44

RSVD

FC29

DPRSTP#

VSS

MSID0

MSID1

FC28

COMP1

COMP3

W

V

U

T

R

INIT#

VSS

SMI#

IGNNE#

STPCLK# THERMTRIP#

VSS SLP#

A20M# VSS

FC22

VSS

FC3

GTLREF1

DPSLP#

P

PWRGOOD

N

VSS

LINT1

LINT0

M

L

K

VTT_OUT_

LEFT

J

GTLREF0

H

D29#

D28#

VSS

RSVD

D27# DSTBN1# DBI1#

VSS D24# D23#

D26# DSTBP1# VSS

D25# VSS D15#

D52# VSS

VSS COMP8

D50# COMP0

14 13

D14#

D13#

VSS

12

D11#

VSS

D9#

11

FC38

VSS

D21#

D22#

D16#

D18#

D19#

VSS

BPRI# DEFER#

D17#

VSS

D12#

VSS

RSVD

D20#

VSS FC41

D10# DSTBP0#

D8#

10

VSS

9

DSTBN0# VSS

VSS

DBI0#

8

D6#

D7#

7

RSVD

FC21

RSVD

VSS

D3#

D5#

VSS

6

D1#

VSS

D4#

5

PECI

RS1#

FC20

VSS

TESTHI9/

FC43

TESTHI8/

FC42

VSS

HITM#

HIT#

BR0#

TRDY#

VSS

VSS

D0#

D2#

4

LOCK#

RS0#

RS2#

3

COMP2

FC5

VSS

ADS#

BNR#

DBSY#

VSS

2

FC27

RSVD

DRDY#

VSS

1

G

D

C

F

E

B

A

Datasheet 43

44

Land Listing and Signal Descriptions

Table 22.

Alphabetical Land

Assignments

A31#

A32#

A33#

A34#

A35#

A20M#

A25#

A26#

A27#

A28#

A29#

A30#

ADS#

ADSTB0#

ADSTB1#

BCLK0

BCLK1

A19#

A20#

A21#

A22#

A23#

A24#

A13#

A14#

A15#

A16#

A17#

A18#

A3#

A4#

A5#

A6#

A7#

A8#

A9#

A10#

A11#

A12#

Land Name

Land

#

Signal Buffer

Type

Direction

U6

T4

U5

M4

R4

T5

L5

P6

M5

L4

Source Synch Input/Output

Source Synch Input/Output

Source Synch Input/Output

Source Synch Input/Output

Source Synch Input/Output

Source Synch Input/Output

Source Synch Input/Output

Source Synch Input/Output

Source Synch Input/Output

Source Synch Input/Output

U4

V5

V4

Source Synch Input/Output

Source Synch Input/Output

Source Synch Input/Output

W5 Source Synch Input/Output

AB6 Source Synch Input/Output

W6 Source Synch Input/Output

Y6 Source Synch Input/Output

Y4 Source Synch Input/Output

AA4 Source Synch Input/Output

AD6 Source Synch Input/Output

AA5 Source Synch Input/Output

AB5 Source Synch Input/Output

AC5 Source Synch Input/Output

AB4 Source Synch Input/Output

AF5 Source Synch Input/Output

AF4 Source Synch Input/Output

AG6 Source Synch Input/Output

AG4 Source Synch Input/Output

AG5 Source Synch Input/Output

AH4 Source Synch Input/Output

AH5 Source Synch Input/Output

AJ5 Source Synch Input/Output

AJ6 Source Synch Input/Output

K3 Asynch CMOS Input

D2 Common Clock Input/Output

R6 Source Synch Input/Output

AD5 Source Synch Input/Output

F28

G28

Clock

Clock

Input

Input

Table 22.

Alphabetical Land

Assignments

D11#

D12#

D13#

D14#

D15#

D16#

D5#

D6#

D7#

D8#

D9#

D10#

D17#

D18#

D19#

D20#

D21#

BSEL1

BSEL2

COMP0

COMP1

COMP2

COMP3

COMP8

D0#

D1#

D2#

D3#

D4#

BNR#

BPM0#

BPM1#

BPM2#

BPM3#

BPM4#

BPM5#

BPRI#

BR0#

BSEL0

Land Name

Land

#

Signal Buffer

Type

Direction

C2 Common Clock Input/Output

AJ2 Common Clock Input/Output

AJ1 Common Clock Input/Output

AD2 Common Clock Input/Output

AG2 Common Clock Input/Output

AF2 Common Clock Input/Output

AG3 Common Clock Input/Output

G8 Common Clock Input

F3 Common Clock Input/Output

G29 Asynch CMOS Output

B13

B4

C5

A4

C6

A5

H30 Asynch CMOS

G30 Asynch CMOS

A13 Power/Other

T1

G2

R1

Power/Other

Power/Other

Power/Other

Power/Other

Output

Output

Input

Input

Input

Input

Input

Source Synch Input/Output

Source Synch Input/Output

Source Synch Input/Output

Source Synch Input/Output

Source Synch Input/Output

B6

B7

A7

Source Synch Input/Output

Source Synch Input/Output

Source Synch Input/Output

A10 Source Synch Input/Output

A11 Source Synch Input/Output

B10 Source Synch Input/Output

C11 Source Synch Input/Output

D8 Source Synch Input/Output

B12 Source Synch Input/Output

C12 Source Synch Input/Output

D11 Source Synch Input/Output

G9 Source Synch Input/Output

F8

F9

E9

Source Synch Input/Output

Source Synch Input/Output

Source Synch Input/Output

D7 Source Synch Input/Output

E10 Source Synch Input/Output

Datasheet

Land Listing and Signal Descriptions

Datasheet

Table 22.

Alphabetical Land

Assignments

D40#

D41#

D42#

D43#

D44#

D45#

D34#

D35#

D36#

D37#

D38#

D39#

D28#

D29#

D30#

D31#

D32#

D33#

D22#

D23#

D24#

D25#

D26#

D27#

D52#

D53#

D54#

D55#

D56#

D57#

D46#

D47#

D48#

D49#

D50#

D51#

D58#

D59#

D60#

Land Name

Land

#

Signal Buffer

Type

Direction

D10 Source Synch Input/Output

F11 Source Synch Input/Output

F12 Source Synch Input/Output

D13 Source Synch Input/Output

E13 Source Synch Input/Output

G13 Source Synch Input/Output

F14 Source Synch Input/Output

G14 Source Synch Input/Output

F15 Source Synch Input/Output

G15 Source Synch Input/Output

G16 Source Synch Input/Output

E15 Source Synch Input/Output

E16 Source Synch Input/Output

G18 Source Synch Input/Output

G17 Source Synch Input/Output

F17 Source Synch Input/Output

F18 Source Synch Input/Output

E18 Source Synch Input/Output

E19 Source Synch Input/Output

F20 Source Synch Input/Output

E21 Source Synch Input/Output

F21 Source Synch Input/Output

G21 Source Synch Input/Output

E22 Source Synch Input/Output

D22 Source Synch Input/Output

G22 Source Synch Input/Output

D20 Source Synch Input/Output

D17 Source Synch Input/Output

A14 Source Synch Input/Output

C15 Source Synch Input/Output

C14 Source Synch Input/Output

B15 Source Synch Input/Output

C18 Source Synch Input/Output

B16 Source Synch Input/Output

A17 Source Synch Input/Output

B18 Source Synch Input/Output

C21 Source Synch Input/Output

B21 Source Synch Input/Output

B19 Source Synch Input/Output

Table 22.

Alphabetical Land

Assignments

Land Name

FC21

FC22

FC23

FC24

FC25

FC26

FC5

FC8

FC10

FC15

FC18

FC20

FC27

FC28

FC29

FC30

D61#

D62#

D63#

DBI0#

DBI1#

DBI2#

DBI3#

DBR#

DBSY#

DEFER#

DPRSTP#

DPSLP#

DRDY#

DSTBN0#

DSTBN1#

DSTBN2#

DSTBN3#

DSTBP0#

DSTBP1#

DSTBP2#

DSTBP3#

FC0/

BOOTSELECT

FC3

Land

#

Signal Buffer

Type

Direction

A19 Source Synch Input/Output

A22 Source Synch Input/Output

B22 Source Synch Input/Output

A8 Source Synch Input/Output

G11 Source Synch Input/Output

D19 Source Synch Input/Output

C20 Source Synch Input/Output

AC2 Power/Other Output

B2 Common Clock Input/Output

G7 Common Clock

T2

P1

Asynch CMOS

Asynch CMOS

Input

Input

Input

C1 Common Clock Input/Output

C8 Source Synch Input/Output

G12 Source Synch Input/Output

G20 Source Synch Input/Output

A16 Source Synch Input/Output

B9 Source Synch Input/Output

E12 Source Synch Input/Output

G19 Source Synch Input/Output

C17 Source Synch Input/Output

Y1

J2

F2

AK6

E24

H29

AE3

E5

F6

J3

A24

AK1

AL1

E29

G1

U1

U2

U3

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

45

46

Land Listing and Signal Descriptions

Table 22.

Alphabetical Land

Assignments

Land Name

LINT1

LOCK#

MSID0

MSID1

PECI

PROCHOT#

PSI#

PWRGOOD

REQ0#

REQ1#

REQ2#

REQ3#

REQ4#

RESERVED

RESERVED

RESERVED

RESERVED

FC41

FERR#/PBE#

GTLREF0

GTLREF1

HIT#

HITM#

IERR#

IGNNE#

INIT#

ITP_CLK0

ITP_CLK1

LINT0

FC31

FC32

FC33

FC34

FC35

FC36

FC37

FC38

FC39

FC40

Land

#

Signal Buffer

Type

Direction

J16

H15

H16

J17

Power/Other

Power/Other

Power/Other

Power/Other

H4 Power/Other

AD3 Power/Other

AB3 Power/Other

G10 Power/Other

AA2 Power/Other

AM6 Power/Other

C9

R3

H1

Power/Other

Asynch CMOS

Power/Other

Output

Input

H2 Power/Other Input

D4 Common Clock Input/Output

E4 Common Clock Input/Output

AB2 Asynch CMOS

N2 Asynch CMOS

P3 Asynch CMOS

AK3

AJ3

K1

TAP

TAP

Asynch CMOS

Output

Input

Input

Input

Input

Input

J6

V2

A20

AC4

AE4

J5

M6

K6

Y3

N1

K4

L1 Asynch CMOS Input

C3 Common Clock Input/Output

W1 Power/Other Output

V1 Power/Other Output

G5 Power/Other Input/Output

AL2 Asynch CMOS Input/Output

Asynch CMOS

Power/Other

Source Synch

Output

Input

Source Synch Input/Output

Input/Output

Source Synch Input/Output

Source Synch Input/Output

Source Synch Input/Output

Table 22.

Alphabetical Land

Assignments

Land Name

Land

#

Signal Buffer

Type

Direction

RESERVED

RESERVED

RESERVED

RESERVED

RESET#

RS0#

RS1#

RS2#

SKTOCC#

SLP#

SMI#

STPCLK#

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

AE6

AH2

D1

D14

D16

E23

E6

E7

F23

F29

TCK

TDI

TDO

TESTHI0

TESTHI1

TESTHI10

TESTHI12/

FC44

TESTHI2

TESTHI3

TESTHI4

TESTHI5

TESTHI6 G24

TESTHI7 F24

TESTHI8/FC42 G3

F25

G25

G27

G26

AE1

AD1

AF1

F26

W3

H5

W2

TAP

TAP

TAP

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

TESTHI9/FC43 G4

THERMTRIP#

TMS

M2

AC1

Power/Other

Asynch CMOS

TAP

G6

N4

N5

P5

G23 Common Clock

B3 Common Clock

F5 Common Clock

A3 Common Clock

AE8 Power/Other

L2

P2

M3

Asynch CMOS

Asynch CMOS

Asynch CMOS

Input

Input

Input

Input

Input

Input

Input

Input

Input

Output

Input

Input

Input

Input

Input

Output

Input

Input

Input

Input

Input

Output

Input

Input

Input

Datasheet

Land Listing and Signal Descriptions

Datasheet

Table 22.

Alphabetical Land

Assignments

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

TRDY#

TRST#

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

Land Name

Land

#

Signal Buffer

Type

Direction

E3 Common Clock

AG1 TAP

AA8 Power/Other

AB8 Power/Other

AC23 Power/Other

AC24 Power/Other

AC25 Power/Other

AC26 Power/Other

AC27 Power/Other

AC28 Power/Other

AC29 Power/Other

AC30 Power/Other

AC8 Power/Other

AD23 Power/Other

AD24 Power/Other

AD25 Power/Other

AD26 Power/Other

AD27 Power/Other

AD28 Power/Other

AD29 Power/Other

AD30 Power/Other

AD8 Power/Other

AE11 Power/Other

AE12 Power/Other

AE14 Power/Other

AE15 Power/Other

AE18 Power/Other

AE19 Power/Other

AE21 Power/Other

AE22 Power/Other

AE23 Power/Other

AE9 Power/Other

AF11 Power/Other

AF12 Power/Other

AF14 Power/Other

AF15 Power/Other

AF18 Power/Other

AF19 Power/Other

AF21 Power/Other

Input

Input

Table 22.

Alphabetical Land

Assignments

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

Land Name

Land

#

Signal Buffer

Type

Direction

AH14 Power/Other

AH15 Power/Other

AH18 Power/Other

AH19 Power/Other

AH21 Power/Other

AH22 Power/Other

AH25 Power/Other

AH26 Power/Other

AH27 Power/Other

AH28 Power/Other

AH29 Power/Other

AH30 Power/Other

AH8 Power/Other

AH9 Power/Other

AJ11 Power/Other

AJ12 Power/Other

AJ14 Power/Other

AJ15 Power/Other

AF22 Power/Other

AF8

AF9

Power/Other

Power/Other

AG11 Power/Other

AG12 Power/Other

AG14 Power/Other

AG15 Power/Other

AG18 Power/Other

AG19 Power/Other

AG21 Power/Other

AG22 Power/Other

AG25 Power/Other

AG26 Power/Other

AG27 Power/Other

AG28 Power/Other

AG29 Power/Other

AG30 Power/Other

AG8 Power/Other

AG9 Power/Other

AH11 Power/Other

AH12 Power/Other

47

48

Land Listing and Signal Descriptions

Table 22.

Alphabetical Land

Assignments

Land Name

Land

#

Signal Buffer

Type

Direction

AJ18 Power/Other

AJ19 Power/Other

AJ21 Power/Other

AJ22 Power/Other

AJ25 Power/Other

AJ26 Power/Other

AJ8 Power/Other

AJ9 Power/Other

AK11 Power/Other

AK12 Power/Other

AK14 Power/Other

AK15 Power/Other

AK18 Power/Other

AK19 Power/Other

AK21 Power/Other

AK22 Power/Other

AK25 Power/Other

AK26 Power/Other

AK8 Power/Other

AK9 Power/Other

AL11 Power/Other

AL12 Power/Other

AL14 Power/Other

AL15 Power/Other

AL18 Power/Other

AL19 Power/Other

AL21 Power/Other

AL22 Power/Other

AL25 Power/Other

AL26 Power/Other

AL29 Power/Other

AL30 Power/Other

AL8

AL9

Power/Other

Power/Other

AM11 Power/Other

AM12 Power/Other

AM14 Power/Other

AM15 Power/Other

AM18 Power/Other

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

Table 22.

Alphabetical Land

Assignments

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

Land Name

Land

#

Signal Buffer

Type

Direction

AM19 Power/Other

AM21 Power/Other

AM22 Power/Other

AM25 Power/Other

AM26 Power/Other

AM29 Power/Other

AM30 Power/Other

AM8 Power/Other

AM9 Power/Other

AN11 Power/Other

AN12 Power/Other

AN14 Power/Other

AN15 Power/Other

AN18 Power/Other

AN19 Power/Other

AN21 Power/Other

AN22 Power/Other

AN25 Power/Other

AN26 Power/Other

AN29 Power/Other

AN30 Power/Other

AN8 Power/Other

J23

J24

J25

J26

J27

J15

J18

J19

J20

J21

J22

AN9 Power/Other

J10

J11

Power/Other

Power/Other

J12

J13

J14

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Datasheet

Land Listing and Signal Descriptions

Datasheet

Table 22.

Alphabetical Land

Assignments

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

Land Name

Land

#

Signal Buffer

Type

Direction

J28

J29

J30

Power/Other

Power/Other

Power/Other

J8 Power/Other

J9 Power/Other

K23 Power/Other

K24 Power/Other

K25 Power/Other

K26 Power/Other

K27 Power/Other

K28 Power/Other

K29 Power/Other

K30 Power/Other

K8

L8

Power/Other

Power/Other

M23 Power/Other

M24 Power/Other

M25 Power/Other

M26 Power/Other

M27 Power/Other

M28 Power/Other

M29 Power/Other

M30 Power/Other

M8 Power/Other

N23 Power/Other

N24 Power/Other

N25 Power/Other

N26 Power/Other

N27 Power/Other

N28 Power/Other

N29 Power/Other

N30 Power/Other

N8 Power/Other

P8

R8

T23

Power/Other

Power/Other

Power/Other

T24

T25

T26

Power/Other

Power/Other

Power/Other

Table 22.

Alphabetical Land

Assignments

Land Name

Land

#

Signal Buffer

Type

Direction

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC_MB_

REGULATION

VCC_SENSE

W29 Power/Other

W30 Power/Other

W8 Power/Other

Y23

Y24

Y25

Y26

Y27

Y28

Y29

Y30

Y8

AN5

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

AN3 Power/Other

VCCA

VCCIOPLL

VCCPLL

A23

C23

D23

Power/Other

Power/Other

Power/Other

VID_SELECT AN7 Power/Other

T27

T28

T29

T30

T8

U23

U24

U25

U26

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

U27

U28

U29

U30

U8

V8

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

W23 Power/Other

W24 Power/Other

W25 Power/Other

W26 Power/Other

W27 Power/Other

W28 Power/Other

Output

Output

Output

49

50

Land Listing and Signal Descriptions

Table 22.

Alphabetical Land

Assignments

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VID0

VID1

VID2

VID3

VID4

VID5

VID6

VID7

VRDSEL

VSS

Land Name

Land

#

Signal Buffer

Type

Direction

B8

A12

A15

A18

A2

A21

B11

B14

B17

B20

B24

B5

AM2 Asynch CMOS

AL5 Asynch CMOS

AM3 Asynch CMOS

AL6 Asynch CMOS

AK4 Asynch CMOS

AL4 Asynch CMOS

AM5 Asynch CMOS

AM7 Asynch CMOS

AL3

B1

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

A6 Power/Other

A9 Power/Other

AA23 Power/Other

AA24 Power/Other

AA25 Power/Other

AA26 Power/Other

AA27 Power/Other

AA28 Power/Other

AA29 Power/Other

AA3 Power/Other

AA30 Power/Other

AA6 Power/Other

AA7 Power/Other

AB1 Power/Other

AB23 Power/Other

AB24 Power/Other

AB25 Power/Other

Output

Output

Output

Output

Output

Output

Output

Output

Table 22.

Alphabetical Land

Assignments

Land Name

Land

#

Signal Buffer

Type

Direction

AB26 Power/Other

AB27 Power/Other

AB28 Power/Other

AB29 Power/Other

AB30 Power/Other

AB7

AC3

Power/Other

Power/Other

AC6

AC7

AD4

Power/Other

Power/Other

Power/Other

AD7 Power/Other

AE10 Power/Other

AE13 Power/Other

AE16 Power/Other

AE17 Power/Other

AE2 Power/Other

AE20 Power/Other

AE24 Power/Other

AE25 Power/Other

AE26 Power/Other

AE27 Power/Other

AE28 Power/Other

AE29 Power/Other

AE30 Power/Other

AE5 Power/Other

AE7 Power/Other

AF10 Power/Other

AF13 Power/Other

AF16 Power/Other

AF17 Power/Other

AF20 Power/Other

AF23 Power/Other

AF24 Power/Other

AF25 Power/Other

AF26 Power/Other

AF27 Power/Other

AF28 Power/Other

AF29 Power/Other

AF3 Power/Other

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

Datasheet

Land Listing and Signal Descriptions

Datasheet

Table 22.

Alphabetical Land

Assignments

Land Name

Land

#

Signal Buffer

Type

Direction

AF30 Power/Other

AF6

AF7

Power/Other

Power/Other

AG10 Power/Other

AG13 Power/Other

AG16 Power/Other

AG17 Power/Other

AG20 Power/Other

AG23 Power/Other

AG24 Power/Other

AG7

AH1

Power/Other

Power/Other

AH10 Power/Other

AH13 Power/Other

AH16 Power/Other

AH17 Power/Other

AH20 Power/Other

AH23 Power/Other

AH24 Power/Other

AH3

AH6

Power/Other

Power/Other

AH7 Power/Other

AJ10 Power/Other

AJ13 Power/Other

AJ16 Power/Other

AJ17 Power/Other

AJ20 Power/Other

AJ23 Power/Other

AJ24 Power/Other

AJ27 Power/Other

AJ28 Power/Other

AJ29 Power/Other

AJ30 Power/Other

AJ4 Power/Other

AJ7 Power/Other

AK10 Power/Other

AK13 Power/Other

AK16 Power/Other

AK17 Power/Other

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

Table 22.

Alphabetical Land

Assignments

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

Land Name

Land

#

Signal Buffer

Type

Direction

AM10 Power/Other

AM13 Power/Other

AM16 Power/Other

AM17 Power/Other

AM20 Power/Other

AM23 Power/Other

AM24 Power/Other

AM27 Power/Other

AM28 Power/Other

AM4 Power/Other

AN1 Power/Other

AN10 Power/Other

AN13 Power/Other

AN16 Power/Other

AN17 Power/Other

AN2 Power/Other

AN20 Power/Other

AN23 Power/Other

AK2 Power/Other

AK20 Power/Other

AK23 Power/Other

AK24 Power/Other

AK27 Power/Other

AK28 Power/Other

AK29 Power/Other

AK30 Power/Other

AK5 Power/Other

AK7 Power/Other

AL10 Power/Other

AL13 Power/Other

AL16 Power/Other

AL17 Power/Other

AL20 Power/Other

AL23 Power/Other

AL24 Power/Other

AL27 Power/Other

AL28 Power/Other

AL7 Power/Other

AM1 Power/Other

51

52

Land Listing and Signal Descriptions

Table 22.

Alphabetical Land

Assignments

Land Name

Land

#

Signal Buffer

Type

Direction

E28

E8

F10

F13

F16

F19

E17

E2

E20

E25

E26

E27

F22

F4

F7

H10

H11

D3

D5

D6

D9

E11

E14

C7

D12

D15

D18

D21

D24

AN24 Power/Other

AN27 Power/Other

AN28 Power/Other

C10 Power/Other

C13

C16

C19

C22

C24

C4

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

Table 22.

Alphabetical Land

Assignments

Land Name

Land

#

Signal Buffer

Type

Direction

L26

L27

L28

L29

L3

L30

K2

K5

K7

L23

L24

L25

L6

L7

M1

M7

N3

H9

J4

J7

H6

H7

H8

H24

H25

H26

H27

H28

H3

H18

H19

H20

H21

H22

H23

H12

H13

H14

H17

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

Datasheet

Land Listing and Signal Descriptions

Datasheet

Table 22.

Alphabetical Land

Assignments

Land Name

Land

#

Signal Buffer

Type

Direction

R28

R29

R30

R5

R7

T3

R2

R23

R24

R25

R26

R27

P27

P28

P29

P30

P4

P7

N6

N7

P23

P24

P25

P26

V26

V27

V28

V29

V3

V30

T6

T7

U7

V23

V24

V25

V6

V7

W4

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

Table 22.

Alphabetical Land

Assignments

Land Name

Land

#

Signal Buffer

Type

Direction

VSS

VSS

VSS

W7

Y2

Y5

Y7

Power/Other

Power/Other

Power/Other

Power/Other VSS

VSS_MB_

REGULATION

VSS_SENSE

VSSA

VTT

VTT

VTT

VTT

VTT

VTT

VTT

VTT

VTT

VTT

VTT

VTT

VTT

VTT

VTT

VTT

VTT

VTT

VTT

AN6 Power/Other

AN4 Power/Other

B23 Power/Other

B25 Power/Other

B26 Power/Other

B27 Power/Other

B28 Power/Other

B29 Power/Other

B30 Power/Other

A25 Power/Other

A26 Power/Other

A27 Power/Other

A28 Power/Other

A29 Power/Other

A30 Power/Other

C25 Power/Other

C26 Power/Other

C27 Power/Other

C28 Power/Other

VTT

VTT

VTT

VTT D29

VTT D30

VTT_OUT_LEFT J1

VTT_OUT_RIG

HT

VTT_SEL

AA1

F27

C29 Power/Other

C30 Power/Other

D25 Power/Other

D26

D27

D28

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Output

Output

Output

Output

Output

53

54

Land Listing and Signal Descriptions

Table 23.

Numerical Land

Assignment

A30

B1

B2

B3

B4

B5

A24

A25

A26

A27

A28

A29

B6

B7

B8

B9

B10

A18

A19

A20

A21

A22

A23

A12

A13

A14

A15

A16

A17

A6

A7

A8

A9

A10

A11

A2

A3

A4

A5

VTT

VSS

DBSY#

RS0#

D00#

VSS

FC23

VTT

VTT

VTT

VTT

VTT

D05#

D06#

VSS

DSTBP0#

D10#

VSS

COMP0

D50#

VSS

DSTBN3#

D56#

VSS

D61#

RESERVED

VSS

D62#

VCCA

VSS

RS2#

D02#

D04#

VSS

D07#

DBI0#

VSS

D08#

D09#

Land # Land Name

Signal Buffer

Type

Direction

Power/Other

Common Clock Input

Source Synch Input/Output

Source Synch Input/Output

Power/Other

Source Synch Input/Output

Source Synch Input/Output

Power/Other

Source Synch Input/Output

Source Synch Input/Output

Power/Other

Power/Other Input

Source Synch Input/Output

Power/Other

Source Synch Input/Output

Source Synch Input/Output

Power/Other

Source Synch Input/Output

Power/Other

Source Synch Input/Output

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Common Clock Input/Output

Common Clock

Source Synch

Input

Source Synch Input/Output

Power/Other

Source Synch Input/Output

Source Synch Input/Output

Power/Other

Source Synch Input/Output

Input/Output

Table 23.

Numerical Land

Assignment

Land # Land Name

Signal Buffer

Type

C9

C10

C11

C12

C13

C14

C6

C7

C8

C3

C4

C5

C15

C16

C17

C18

C19

B27

B28

B29

B30

C1

C2

B21

B22

B23

B24

B25

B26

B15

B16

B17

B18

B19

B20

B11

B12

B13

B14

LOCK#

VSS

D01#

D03#

VSS

DSTBN0#

FC41

VSS

D11#

D14#

VSS

D52#

D51#

VSS

DSTBP3#

D54#

VSS

VTT

VTT

VTT

VTT

DRDY#

BNR#

D59#

D63#

VSSA

VSS

VTT

VTT

VSS

D13#

COMP8

VSS

D53#

D55#

VSS

D57#

D60#

VSS

Direction

Power/Other

Source Synch Input/Output

Power/Other

Power/Other

Input

Source Synch Input/Output

Source Synch Input/Output

Power/Other

Source Synch Input/Output

Source Synch Input/Output

Power/Other

Source Synch Input/Output

Source Synch Input/Output

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Common Clock Input/Output

Common Clock Input/Output

Common Clock Input/Output

Power/Other

Source Synch Input/Output

Source Synch Input/Output

Power/Other

Source Synch Input/Output

Power/Other

Power/Other

Source Synch Input/Output

Source Synch Input/Output

Power/Other

Source Synch Input/Output

Source Synch Input/Output

Power/Other

Source Synch Input/Output

Source Synch Input/Output

Power/Other

Datasheet

Land Listing and Signal Descriptions

Datasheet

Table 23.

Numerical Land

Assignment

Land # Land Name

Signal Buffer

Type

Direction

D8

D9

D10

D11

D12

D13

D5

D6

D7

D2

D3

D4

C26

C27

C28

C29

C30

D1

C20

C21

C22

C23

C24

C25

D20

D21

D22

D23

D24

D25

D14

D15

D16

D17

D18

D19

D26

D27

D28

D12#

VSS

D22#

D15#

VSS

D25#

ADS#

VSS

HIT#

VSS

VSS

D20#

DBI3#

D58#

VSS

VCCIOPLL

VSS

VTT

VTT

VTT

VTT

VTT

VTT

RESERVED

RESERVED

VSS

RESERVED

D49#

VSS

DBI2#

D48#

VSS

D46#

VCCPLL

VSS

VTT

VTT

VTT

VTT

Source Synch Input/Output

Source Synch Input/Output

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Common Clock Input/Output

Power/Other

Common Clock Input/Output

Power/Other

Power/Other

Source Synch Input/Output

Source Synch Input/Output

Power/Other

Source Synch Input/Output

Source Synch Input/Output

Power/Other

Source Synch Input/Output

Power/Other

Source Synch Input/Output

Power/Other

Source Synch Input/Output

Source Synch Input/Output

Power/Other

Source Synch Input/Output

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Table 23.

Numerical Land

Assignment

E27

E28

E29

F2

F3

F4

E21

E22

E23

E24

E25

E26

F5

F6

F7

F8

F9

F10

E15

E16

E17

E18

E19

E20

E9

E10

E11

E12

E13

E14

D29

D30

E2

E6

E7

E8

E3

E4

E5

Land # Land Name

Signal Buffer

Type

Direction

Power/Other

Power/Other

Power/Other

Common Clock Input

Common Clock Input/Output

Power/Other

Power/Other

Source Synch Input/Output

Source Synch Input/Output

Power/Other

Source Synch Input/Output

Source Synch Input/Output

Power/Other

Source Synch Input/Output

Source Synch Input/Output

Power/Other

Source Synch Input/Output

Source Synch Input/Output

Power/Other

Source Synch Input/Output

Source Synch Input/Output

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Common Clock Input/Output

Power/Other

Input Common Clock

Power/Other

Power/Other

Source Synch Input/Output

Source Synch Input/Output

Power/Other

D42#

D45#

RESERVED

FC10

VSS

VSS

VSS

VSS

FC26

FC5

BR0#

VSS

RS1#

FC21

VSS

D17#

D18#

VSS

D19#

D21#

VSS

DSTBP1#

D26#

VSS

D33#

D34#

VSS

D39#

D40#

VSS

VTT

VTT

VSS

TRDY#

HITM#

FC20

RESERVED

RESERVED

VSS

55

56

Land Listing and Signal Descriptions

Table 23.

Numerical Land

Assignment

G3

G4

G11

G12

G13

G14

G15

G16

G5

G6

G7

G8

G9

G10

G17

G18

G19

D43#

VSS

RESERVED

TESTHI7

TESTHI2

TESTHI0

VTT_SEL

BCLK0

RESERVED

FC27

COMP2

TESTHI8/

FC42

TESTHI9/

FC43

D23#

D24#

VSS

D28#

D30#

VSS

D37#

D38#

VSS

D41#

PECI

RESERVED

DEFER#

BPRI#

D16#

FC38

DBI1#

DSTBN1#

D27#

D29#

D31#

D32#

D36#

D35#

DSTBP2#

Land # Land Name

Signal Buffer

Type

F27

F28

F29

G1

G2

F21

F22

F23

F24

F25

F26

F15

F16

F17

F18

F19

F20

F11

F12

F13

F14

Source Synch Input/Output

Source Synch Input/Output

Power/Other

Source Synch Input/Output

Source Synch Input/Output

Power/Other

Source Synch Input/Output

Source Synch Input/Output

Power/Other

Source Synch Input/Output

Source Synch Input/Output

Power/Other

Power/Other

Power/Other

Power/Other

Input

Input

Input

Power/Other

Clock

Power/Other

Power/Other

Output

Input

Input

Power/Other

Power/Other

Power/Other

Common Clock

Common Clock

Direction

Input

Input

Input/Output

Input

Input

Source Synch Input/Output

Power/Other

Source Synch Input/Output

Source Synch Input/Output

Source Synch Input/Output

Source Synch Input/Output

Source Synch Input/Output

Source Synch Input/Output

Source Synch Input/Output

Source Synch Input/Output

Source Synch Input/Output

Table 23.

Numerical Land

Assignment

H18

H19

H20

H21

H22

H23

H12

H13

H14

H15

H16

H17

H24

H25

H26

H27

H28

H6

H7

H8

H9

H10

H11

G30

H1

H2

H3

H4

H5

G24

G25

G26

G27

G28

G29

G20

G21

G22

G23

Land # Land Name

Signal Buffer

Type

Direction

Source Synch Input/Output

Source Synch Input/Output

Source Synch Input/Output

Common Clock Input

Power/Other

Power/Other

Power/Other

Power/Other

Clock

Asynch CMOS

Input

Input

Input

Input

Input

Output

Asynch CMOS

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Output

Input

Input

Input

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

FC32

FC33

VSS

VSS

VSS

VSS

VSS

VSS

BSEL2

GTLREF0

GTLREF1

VSS

FC35

TESTHI10

VSS

VSS

VSS

VSS

VSS

VSS

DSTBN2#

D44#

D47#

RESET#

TESTHI6

TESTHI3

TESTHI5

TESTHI4

BCLK1

BSEL0

Datasheet

Land Listing and Signal Descriptions

Datasheet

Table 23.

Numerical Land

Assignment

J19

J20

J21

J22

J23

J24

J13

J14

J15

J16

J17

J18

J10

J11

J12

J7

J8

J9

J2

J3

J4

J5

J6

K4

K5

K6

K1

K2

K3

K7

J25

J26

J27

J28

J29

J30

Land # Land Name

Signal Buffer

Type

H29

H30

Direction

J1

LINT0

VSS

A20M#

REQ0#

VSS

REQ3#

VSS

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

FC31

FC34

VCC

FC15

BSEL1

VTT_OUT_LE

FT

Power/Other

Asynch CMOS

Power/Other

FC3

FC22

VSS

REQ1#

REQ4#

VSS

VCC

VCC

VCC

VCC

VCC

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Output

Output

Source Synch Input/Output

Source Synch Input/Output

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Asynch CMOS

Power/Other

Asynch CMOS

Input

Input

Source Synch Input/Output

Power/Other

Source Synch Input/Output

Power/Other

Table 23.

Numerical Land

Assignment

M2

M8

M23

M24

M25

M26

M27

M28

M3

M4

M5

M6

M7

Land # Land Name

Signal Buffer

Type

L7

L8

L23

L24

L25

L26

L4

L5

L6

L1

L2

L3

L27

L28

L29

L30

M1

K8

K23

K24

K25

K26

K27

K28

K29

K30

VSS

VCC

VSS

VSS

VSS

VSS

LINT1

SLP#

VSS

A06#

A03#

VSS

VSS

VSS

VSS

VSS

VSS

THERMTRIP

#

STPCLK#

A07#

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

A05#

REQ2#

VSS

VCC

VCC

VCC

VCC

VCC

VCC

VCC

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Asynch CMOS

Asynch CMOS

Power/Other

Input

Input

Source Synch Input/Output

Source Synch Input/Output

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Asynch CMOS

Asynch CMOS

Source Synch

Source Synch

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Direction

Output

Input

Input/Output

Input/Output

Source Synch Input/Output

57

58

Land Listing and Signal Descriptions

Table 23.

Numerical Land

Assignment

Land # Land Name

Signal Buffer

Type

P25

P26

P27

P28

P29

P30

P5

P6

P7

P8

P23

P24

R1

R2

R3

R4

R5

N29

N30

P1

P2

P3

P4

N23

N24

N25

N26

N27

N28

N6

N7

N8

N3

N4

N5

M29

M30

N1

N2

Direction

VCC

VCC

DPSLP#

SMI#

INIT#

VSS

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

PWRGOOD

IGNNE#

VSS

RESERVED

RESERVED

VSS

VSS

VCC

Power/Other

Power/Other

Power/Other

Asynch CMOS

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Asynch CMOS

Asynch CMOS

Asynch CMOS

Power/Other

RESERVED

A04#

VSS

VCC

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

Source Synch

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Input/Output

COMP3 Power/Other

VSS Power/Other

FERR#/PBE# Asynch CMOS

A08#

VSS

Input

Output

Source Synch Input/Output

Power/Other

Input

Input

Input

Input

Input

Table 23.

Numerical Land

Assignment

Land # Land Name

Signal Buffer

Type

U5

U6

U7

U2

U3

U4

T26

T27

T28

T29

T30

U1

U8

U23

U24

U25

U26

T6

T7

T8

T23

T24

T25

R30

T1

T2

T3

T4

T5

R24

R25

R26

R27

R28

R29

R6

R7

R8

R23

FC29

FC30

A13#

A12#

A10#

VSS

VCC

VCC

VCC

VCC

VCC

FC28

VCC

VCC

VCC

VCC

VCC

VSS

COMP1

DPRSTP#

VSS

A11#

A09#

VSS

VSS

VCC

VCC

VCC

VCC

ADSTB0#

VSS

VCC

VSS

VSS

VSS

VSS

VSS

VSS

VSS

Direction

Source Synch Input/Output

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Asynch CMOS

Input

Input

Power/Other

Source Synch Input/Output

Source Synch Input/Output

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Source Synch Input/Output

Source Synch Input/Output

Source Synch Input/Output

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Datasheet

Land Listing and Signal Descriptions

Datasheet

Table 23.

Numerical Land

Assignment

Land # Land Name

Signal Buffer

Type

Direction

V6

V7

V8

V3

V4

V5

U27

U28

U29

U30

V1

V2

V23

V24

V25

V26

V27

V28

VSS

VSS

VSS

VSS

VSS

VSS

V29

V30

W1

W2

VSS

VSS

MSID0

TESTHI12/

FC44

TESTHI1 W3

W4

W5

W6

W7

W8

W23

W24

W25

W26

VSS

A16#

A18#

VSS

VCC

VCC

W27

W28

W29

VCC

VCC

VCC

VCC

VCC

VCC

W30

Y1

Y2

VCC

FC0/

BOOTSELECT

VSS

VCC

VCC

VCC

VCC

MSID1

RESERVED

VSS

A15#

A14#

VSS

VSS

VCC

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Source Synch Input/Output

Source Synch Input/Output

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other Output

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Output

Input

Input

Power/Other

Source Synch Input/Output

Source Synch Input/Output

Table 23.

Numerical Land

Assignment

Land # Land Name

Signal Buffer

Type

Y3

Y4

Y5

Y6

Y7

Y8

Y23

Y24

Y25

PSI#

A20#

VSS

A19#

VSS

VCC

VCC

VCC

VCC

AB3

AB4

AB5

AB6

AB7

AB8

AB23

AA27

AA28

AA29

AA30

AB1

AB2

Y26

Y27

Y28

Y29

Y30

AA1

AA7

AA8

AA23

AA24

AA25

AA26

AA2

AA3

AA4

AA5

AA6

VCC

VCC

VCC

VCC

VCC

VTT_OUT_RI

GHT

FC39

VSS

A21#

A23#

VSS

VSS

VCC

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

IERR#

FC37

A26#

A24#

A17#

VSS

VCC

VSS

Direction

Asynch CMOS Output

Source Synch Input/Output

Power/Other

Source Synch Input/Output

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Source Synch

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Asynch CMOS

Power/Other

Source Synch

Power/Other

Power/Other

Power/Other

Output

Input/Output

Source Synch Input/Output

Output

Source Synch Input/Output

Source Synch Input/Output

Input/Output

59

60

Land Listing and Signal Descriptions

Table 23.

Numerical Land

Assignment

Land # Land Name

Signal Buffer

Type

AD6

AD7

AD8

AD23

AD24

AD25

AC30

AD1

AD2

AD3

AD4

AD5

AD26

AD27

AD28

AD29

AD30

AC24

AC25

AC26

AC27

AC28

AC29

AC4

AC5

AC6

AC7

AC8

AC23

AB24

AB25

AB26

AB27

AB28

AB29

AB30

AC1

AC2

AC3

VCC

TDI

BPM2#

FC36

VSS

ADSTB1#

A22#

VSS

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

RESERVED

A25#

VSS

VSS

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VSS

VSS

VSS

VSS

VSS

VSS

VSS

TMS

DBR#

VSS

Direction

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

TAP

Power/Other

Power/Other

Source Synch Input/Output

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Input

Output

Power/Other

TAP Input

Common Clock Input/Output

Power/Other

Power/Other

Source Synch Input/Output

Source Synch Input/Output

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Table 23.

Numerical Land

Assignment

Land # Land Name

Signal Buffer

Type

AE1

AE2

AE3

AE4

AE29

AE30

AF1

AF2

AF3

AF4

AE23

AE24

AE25

AE26

AE27

AE28

AF5

AF6

AF7

AF8

AF9

AE17

AE18

AE19

AE20

AE21

AE22

AE11

AE12

AE13

AE14

AE15

AE16

AE5

AE6

AE7

AE8

AE9

AE10

TAP

Power/Other

Power/Other

Power/Other

VSS

VSS

TDO

BPM4#

VSS

A28#

VCC

VSS

VSS

VSS

VSS

VSS

A27#

VSS

VSS

VCC

VCC

VSS

VCC

VCC

VSS

VCC

VCC

VCC

VCC

VSS

VCC

VCC

VSS

TCK

VSS

FC18

RESERVED

VSS

RESERVED

VSS

SKTOCC#

VCC

VSS

Direction

Input

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

TAP Output

Common Clock Input/Output

Power/Other

Source Synch Input/Output

Source Synch Input/Output

Power/Other

Power/Other

Power/Other

Power/Other

Output

Datasheet

Land Listing and Signal Descriptions

Datasheet

Table 23.

Numerical Land

Assignment

Land # Land Name

Signal Buffer

Type

Direction

AF28

AF29

AF30

AG1

AG2

AG3

AF22

AF23

AF24

AF25

AF26

AF27

AF16

AF17

AF18

AF19

AF20

AF21

AF10

AF11

AF12

AF13

AF14

AF15

AG10

AG11

AG12

AG13

AG14

AG15

AG4

AG5

AG6

AG7

AG8

AG9

AG16

AG17

AG18

VSS

VSS

VSS

TRST#

BPM3#

BPM5#

VCC

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VCC

VCC

VSS

VCC

VSS

VCC

VCC

VSS

VCC

VCC

VSS

VCC

VCC

VSS

VCC

VCC

A30#

A31#

A29#

VSS

VCC

VCC

VSS

VSS

VCC

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

TAP Input

Common Clock Input/Output

Common Clock Input/Output

Source Synch Input/Output

Source Synch Input/Output

Source Synch Input/Output

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Table 23.

Numerical Land

Assignment

Land # Land Name

Signal Buffer

Type

AH16

AH17

AH18

AH19

AH20

AH21

AH10

AH11

AH12

AH13

AH14

AH15

AH22

AH23

AH24

AH25

AH26

AH27

AH4

AH5

AH6

AH7

AH8

AH9

AG28

AG29

AG30

AH1

AH2

AH3

AG19

AG20

AG21

AG22

AG23

AG24

AG25

AG26

AG27

VSS

VSS

VCC

VCC

VSS

VCC

VSS

VCC

VCC

VSS

VCC

VCC

VCC

VSS

VSS

VCC

VCC

VCC

VCC

VCC

VCC

VSS

RESERVED

VSS

A32#

A33#

VSS

VSS

VCC

VCC

VCC

VSS

VCC

VCC

VSS

VSS

VCC

VCC

VCC

Direction

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Source Synch Input/Output

Source Synch Input/Output

Power/Other

Power/Other

Power/Other

Power/Other

61

62

Land Listing and Signal Descriptions

Table 23.

Numerical Land

Assignment

Land # Land Name

Signal Buffer

Type

AJ26

AJ27

AJ28

AJ29

AJ30

AK1

AJ20

AJ21

AJ22

AJ23

AJ24

AJ25

AK2

AK3

AK4

AK5

AK6

AJ14

AJ15

AJ16

AJ17

AJ18

AJ19

AJ8

AJ9

AJ10

AJ11

AJ12

AJ13

AH28

AH29

AH30

AJ1

AJ2

AJ3

AJ4

AJ5

AJ6

AJ7

VCC

VSS

VSS

VSS

VSS

FC24

VSS

VCC

VCC

VSS

VSS

VCC

VSS

ITP_CLK0

VID4

VSS

FC8

VCC

VCC

VSS

VSS

VCC

VCC

VCC

VCC

VSS

VCC

VCC

VSS

VCC

VCC

VCC

BPM1#

BPM0#

ITP_CLK1

VSS

A34#

A35#

VSS

Direction

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

TAP

Asynch CMOS

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Common Clock Input/Output

Common Clock Input/Output

TAP

Power/Other

Input

Source Synch Input/Output

Source Synch Input/Output

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Input

Output

Table 23.

Numerical Land

Assignment

Land # Land Name

Signal Buffer

Type

AL5

AL6

AL7

AL8

AL9

AL10

AK29

AK30

AL1

AL2

AL3

AL4

AL11

AL12

AL13

AL14

AL15

AK23

AK24

AK25

AK26

AK27

AK28

AK17

AK18

AK19

AK20

AK21

AK22

AK7

AK8

AK9

AK10

AK11

AK12

AK13

AK14

AK15

AK16

Direction

VSS

VSS

VCC

VCC

VSS

VSS

VSS

VCC

VCC

VSS

VCC

VCC

VSS

VCC

VCC

VSS

VCC

VCC

VSS

VCC

VCC

VSS

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

VSS

VSS

FC25

Power/Other

Power/Other

Power/Other

PROCHOT# Asynch CMOS Input/Output

VRDSEL

VID5

Power/Other

Asynch CMOS Output

VID1

VID3

VSS

VCC

VCC

VSS

Asynch CMOS

Asynch CMOS

Power/Other

Power/Other

Power/Other

Power/Other

Output

Output

VCC

VCC

VSS

VCC

VCC

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Datasheet

Land Listing and Signal Descriptions

Datasheet

Table 23.

Numerical Land

Assignment

Land # Land Name

Signal Buffer

Type

Direction

AM12

AM13

AM14

AM15

AM16

AM17

AL28

AL29

AL30

AM1

AM10

AM11

AL22

AL23

AL24

AL25

AL26

AL27

AL16

AL17

AL18

AL19

AL20

AL21

AM6

AM7

AM8

AM9

AM20

AM21

AM18

AM19

AM2

AM3

AM4

AM5

AM22

AM23

AM24

VCC

VSS

VCC

VCC

VSS

VSS

VSS

VCC

VCC

VSS

VSS

VCC

VCC

VSS

VSS

VCC

VCC

VSS

VSS

VSS

VCC

VCC

VSS

VCC

FC40

VID7

VCC

VCC

VSS

VCC

VCC

VCC

VID0

VID2

VSS

VID6

VCC

VSS

VSS

Output

Output

Output

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Asynch CMOS

Asynch CMOS

Power/Other

Asynch CMOS

Power/Other

Asynch CMOS

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Output

Table 23.

Numerical Land

Assignment

Land # Land Name

Signal Buffer

Type

AN26

AN27

AN28

AN29

AN30

AN20

AN21

AN22

AN23

AN24

AN25

AN14

AN15

AN16

AN17

AN18

AN19

AN8

AN9

AN10

AN11

AN12

AN13

AM25

AM26

AM27

VCC

VCC

VSS

AM28

AM29

AM30

VSS

VCC

VCC

AN1 VSS

AN2 VSS

AN3 VCC_SENSE

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

AN4 VSS_SENSE

AN5

VCC_MB_

REGULATION

Power/Other

Power/Other

AN6

VSS_MB_

REGULATION

Power/Other

AN7 VID_SELECT Power/Other

VCC

VCC

VSS

VCC

VCC

VSS

VCC

VCC

VSS

VSS

VCC

VCC

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

VCC

VSS

VSS

VCC

VCC

VSS

VCC

VCC

VSS

VSS

VCC

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Power/Other

Direction

Output

Output

Output

Output

Output

63

Land Listing and Signal Descriptions

4.2

Alphabetical Signals Reference

Table 24.

Signal Description (Sheet 1 of 10)

Name

A[35:3]#

A20M#

ADS#

ADSTB[1:0]#

Type

Input/

Output

Input

Input/

Output

Description

A[35:3]# (Address) define a 2

36

-byte physical memory address space. In sub-phase 1 of the address phase, these signals transmit the address of a transaction. In sub-phase 2, these signals transmit transaction type information. These signals must connect the appropriate pins/lands of all agents on the processor FSB.

A[35:3]# are source synchronous signals and are latched into the receiving buffers by ADSTB[1:0]#.

On the active-to-inactive transition of RESET#, the processor samples a subset of the A[35:3]# signals to determine power-on configuration. See Section 6.1

for more details.

If A20M# (Address-20 Mask) is asserted, the processor masks physical address bit 20 (A20#) before looking up a line in any internal cache and before driving a read/write transaction on the bus. Asserting A20M# emulates the 8086 processor's address wrap-around at the 1-MB boundary. Assertion of A20M# is only supported in real mode.

A20M# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/

Output Write bus transaction.

ADS# (Address Strobe) is asserted to indicate the validity of the transaction address on the A[35:3]# and REQ[4:0]# signals. All bus agents observe the ADS# activation to begin protocol checking, address decode, internal snoop, or deferred reply ID match operations associated with the new transaction.

Address strobes are used to latch A[35:3]# and REQ[4:0]# on their rising and falling edges. Strobes are associated with signals as shown below.

Input/

Output

Signals Associated Strobe

REQ[4:0]#, A[16:3]#

A[35:17]#

ADSTB0#

ADSTB1#

BCLK[1:0]

BNR#

Input

Input/

Output

The differential pair BCLK (Bus Clock) determines the FSB frequency. All processor FSB agents must receive these signals to drive their outputs and latch their inputs.

All external timing parameters are specified with respect to the rising edge of BCLK0 crossing V

CROSS

.

BNR# (Block Next Request) is used to assert a bus stall by any bus agent unable to accept new bus transactions. During a bus stall, the current bus owner cannot issue any new transactions.

64 Datasheet

Land Listing and Signal Descriptions

Table 24.

Signal Description (Sheet 2 of 10)

Name

BPM[5:0]#

BPRI#

BR0#

BSEL[2:0]

COMP[3:0],

COMP8

Type

Input/

Output

Input

Input/

Output

Output

Analog

Description

BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals. They are outputs from the processor that indicate the status of breakpoints and programmable counters used for monitoring processor performance. BPM[5:0]# should connect the appropriate pins/lands of all processor FSB agents.

BPM4# provides PRDY# (Probe Ready) functionality for the TAP port. PRDY# is a processor output used by debug tools to determine processor debug readiness.

BPM5# provides PREQ# (Probe Request) functionality for the TAP port. PREQ# is used by debug tools to request debug operation of the processor.

These signals do not have on-die termination. Refer to

Section 2.6.2

for termination requirements.

BPRI# (Bus Priority Request) is used to arbitrate for ownership of the processor FSB. It must connect the appropriate pins/lands of all processor FSB agents. Observing BPRI# active (as asserted by the priority agent) causes all other agents to stop issuing new requests, unless such requests are part of an ongoing locked operation. The priority agent keeps BPRI# asserted until all of its requests are completed, then releases the bus by de-asserting

BPRI#.

BR0# drives the BREQ0# signal in the system and is used by the processor to request the bus. During power-on configuration this signal is sampled to determine the agent ID = 0.

This signal does not have on-die termination and must be terminated.

The BCLK[1:0] frequency select signals BSEL[2:0] are used to select the processor input clock frequency. Table 16 defines the possible combinations of the signals and the frequency associated with each combination. The required frequency is determined by the processor, chipset, and clock synthesizer. All agents must operate at the same frequency. For more information about these signals, including termination recommendations refer to

Section 2.8.2

.

COMP[3:0] and COMP8 must be terminated to V

SS board using precision resistors. on the system

Datasheet 65

Land Listing and Signal Descriptions

Table 24.

Signal Description (Sheet 3 of 10)

Name Type Description

D[63:0]# (Data) are the data signals. These signals provide a 64bit data path between the processor FSB agents, and must connect the appropriate pins/lands on all such agents. The data driver asserts DRDY# to indicate a valid data transfer.

D[63:0]# are quad-pumped signals and will, thus, be driven four times in a common clock period. D[63:0]# are latched off the falling edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group of

16 data signals correspond to a pair of one DSTBP# and one

DSTBN#. The following table shows the grouping of data signals to data strobes and DBI#.

D[63:0]#

DBI[3:0]#

DBR#

DBSY#

Input/

Output

Quad-Pumped Signal Groups

Data Group

D[15:0]#

D[31:16]#

D[47:32]#

D[63:48]#

DSTBN#/DSTBP#

0

1

2

3

DBI#

0

1

2

3

Input/

Output

Furthermore, the DBI# signals determine the polarity of the data signals. Each group of 16 data signals corresponds to one DBI# signal. When the DBI# signal is active, the corresponding data group is inverted and therefore sampled active high.

DBI[3:0]# (Data Bus Inversion) are source synchronous and indicate the polarity of the D[63:0]# signals.The DBI[3:0]# signals are activated when the data on the data bus is inverted. If more than half the data bits, within a 16-bit group, would have been asserted electrically low, the bus agent may invert the data bus signals for that particular sub-phase for that 16-bit group.

DBI[3:0] Assignment To Data Bus

Bus Signal

DBI3#

DBI2#

DBI1#

DBI0#

Data Bus Signals

D[63:48]#

D[47:32]#

D[31:16]#

D[15:0]#

Output

Input/

Output

DBR# (Debug Reset) is used only in processor systems where no debug port is implemented on the system board. DBR# is used by a debug port interposer so that an in-target probe can drive system reset. If a debug port is implemented in the system, DBR# is a no connect in the system. DBR# is not a processor signal.

DBSY# (Data Bus Busy) is asserted by the agent responsible for driving data on the processor FSB to indicate that the data bus is in use. The data bus is released after DBSY# is de-asserted. This signal must connect the appropriate pins/lands on all processor FSB agents.

66 Datasheet

Land Listing and Signal Descriptions

Table 24.

Signal Description (Sheet 4 of 10)

Name

DEFER#

DPRSTP#

DPSLP#

DRDY#

Type

Input

Input

Input

Input/

Output

Description

DEFER# is asserted by an agent to indicate that a transaction cannot be ensured in-order completion. Assertion of DEFER# is normally the responsibility of the addressed memory or input/ output agent. This signal must connect the appropriate pins/lands of all processor FSB agents.

DPRSTP#, when asserted on the platform, causes the processor to transition from the Deep Sleep State to the Deeper Sleep state. To return to the Deep Sleep State, DPRSTP# must be de-asserted. Use of the DPRSTP# pin, and corresponding low power state, requires chipset support and may not be available on all platforms.

NOTE: Some processors may not have the Deeper Sleep State enabled, refer to the Specification Update for specific sku and stepping guidance.

DPSLP#, when asserted on the platform, causes the processor to transition from the Sleep State to the Deep Sleep state. To return to the Sleep State, DPSLP# must be de-asserted. Use of the

DPSLP# pin, and corresponding low power state, requires chipset support and may not be available on all platforms.

NOTE: Some processors may not have the Deep Sleep State enabled, refer to the Specification Update for specific processor and stepping guidance.

DRDY# (Data Ready) is asserted by the data driver on each data transfer, indicating valid data on the data bus. In a multi-common clock data transfer, DRDY# may be de-asserted to insert idle clocks. This signal must connect the appropriate pins/lands of all processor FSB agents.

DSTBN[3:0]# are the data strobes used to latch in D[63:0]#.

DSTBN[3:0]#

DSTBP[3:0]#

Input/

Output

Signals

D[15:0]#, DBI0#

D[31:16]#, DBI1#

D[47:32]#, DBI2#

D[63:48]#, DBI3#

Associated Strobe

DSTBN0#

DSTBN1#

DSTBN2#

DSTBN3#

Input/

Output

DSTBP[3:0]# are the data strobes used to latch in D[63:0]#.

Signals

D[15:0]#, DBI0#

D[31:16]#, DBI1#

D[47:32]#, DBI2#

D[63:48]#, DBI3#

Associated Strobe

DSTBP0#

DSTBP1#

DSTBP2#

DSTBP3#

FC0/BOOTSELECT Other

FCx Other

FC0/BOOTSELECT is not used by the processor. When this land is tied to V

SS

previous processors based on the Intel NetBurst

® microarchitecture should be disabled and prevented from booting.

FC signals are signals that are available for compatibility with other processors.

Datasheet 67

Land Listing and Signal Descriptions

Table 24.

Signal Description (Sheet 5 of 10)

Name

FERR#/PBE#

GTLREF[1:0]

HIT#

HITM#

IERR#

IGNNE#

INIT#

Type Description

Output

Input

Output

Input

Input

FERR#/PBE# (floating point error/pending break event) is a multiplexed signal and its meaning is qualified by STPCLK#. When

STPCLK# is not asserted, FERR#/PBE# indicates a floating-point error and will be asserted when the processor detects an unmasked floating-point error. When STPCLK# is not asserted, FERR#/PBE# is similar to the ERROR# signal on the Intel 387 coprocessor, and is included for compatibility with systems using MS-DOS*-type floating-point error reporting. When STPCLK# is asserted, an assertion of FERR#/PBE# indicates that the processor has a pending break event waiting for service. The assertion of FERR#/

PBE# indicates that the processor should be returned to the Normal state. For additional information on the pending break event functionality, including the identification of support of the feature and enable/disable information, refer to volume 3 of the Intel

Architecture Software Developer's Manual and the Intel Processor

Identification and the CPUID Instruction application note.

GTLREF[1:0] determine the signal reference level for GTL+ input signals. GTLREF is used by the GTL+ receivers to determine if a signal is a logical 0 or logical 1.

Input/

Output

Input/

Output

HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation results. Any FSB agent may assert both HIT# and

HITM# together to indicate that it requires a snoop stall that can be continued by reasserting HIT# and HITM# together.

IERR# (Internal Error) is asserted by a processor as the result of an internal error. Assertion of IERR# is usually accompanied by a

SHUTDOWN transaction on the processor FSB. This transaction may optionally be converted to an external error signal (such as

NMI) by system core logic. The processor will keep IERR# asserted until the assertion of RESET#.

This signal does not have on-die termination. Refer to Section 2.6.2

for termination requirements.

IGNNE# (Ignore Numeric Error) is asserted to the processor to ignore a numeric error and continue to execute noncontrol floatingpoint instructions. If IGNNE# is de-asserted, the processor generates an exception on a noncontrol floating-point instruction if a previous floating-point instruction caused an error. IGNNE# has no effect when the NE bit in control register 0 (CR0) is set.

IGNNE# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/

Output Write bus transaction.

INIT# (Initialization), when asserted, resets integer registers inside the processor without affecting its internal caches or floating-point registers. The processor then begins execution at the power-on

Reset vector configured during power-on configuration. The processor continues to handle snoop requests during INIT# assertion. INIT# is an asynchronous signal and must connect the appropriate pins/lands of all processor FSB agents.

If INIT# is sampled active on the active to inactive transition of

RESET#, then the processor executes its Built-in Self-Test (BIST).

68 Datasheet

Land Listing and Signal Descriptions

Table 24.

Signal Description (Sheet 6 of 10)

Name

ITP_CLK[1:0]

LINT[1:0]

LOCK#

MSID[1:0]

PECI

PROCHOT#

PSI#

Type

Input

Input

Input/

Output

Output

Input/

Output

Input/

Output

Output

Description

ITP_CLK[1:0] are copies of BCLK that are used only in processor systems where no debug port is implemented on the system board.

ITP_CLK[1:0] are used as BCLK[1:0] references for a debug port implemented on an interposer. If a debug port is implemented in the system, ITP_CLK[1:0] are no connects in the system. These are not processor signals.

LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins/lands of all APIC Bus agents. When the APIC is disabled, the

LINT0 signal becomes INTR, a maskable interrupt request signal, and LINT1 becomes NMI, a nonmaskable interrupt. INTR and NMI are backward compatible with the signals of those names on the

Pentium processor. Both signals are asynchronous.

Both of these signals must be software configured using BIOS programming of the APIC register space to be used either as NMI/

INTR or LINT[1:0]. Because the APIC is enabled by default after

Reset, operation of these signals as LINT[1:0] is the default configuration.

LOCK# indicates to the system that a transaction must occur atomically. This signal must connect the appropriate pins/lands of all processor FSB agents. For a locked sequence of transactions,

LOCK# is asserted from the beginning of the first transaction to the end of the last transaction.

When the priority agent asserts BPRI# to arbitrate for ownership of the processor FSB, it will wait until it observes LOCK# de-asserted.

This enables symmetric agents to retain ownership of the processor

FSB throughout the bus locked operation and ensure the atomicity of lock.

On the processor these signals are connected on the package to

V

SS

. As an alternative to MSID, Intel has implemented the Power

Segment Identifier (PSID) to report the maximum Thermal Design

Power of the processor. Refer to Section 2.5

for additional information regarding PSID.

PECI is a proprietary one-wire bus interface. See Chapter 5.3

for details.

As an output, PROCHOT# (Processor Hot) will go active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature.

This indicates that the processor Thermal Control Circuit (TCC) has been activated, if enabled. As an input, assertion of PROCHOT# by the system will activate the TCC, if enabled. The TCC will remain active until the system de-asserts PROCHOT#. See Section 5.2.4

for more details.

Processor Power Status Indicator Signal. This signal may be asserted when the processor is in the Deeper Sleep State. PSI# can be used to improve load efficiency of the voltage regulator, resulting in platform power savings.

Datasheet 69

Land Listing and Signal Descriptions

Table 24.

Signal Description (Sheet 7 of 10)

Name

PWRGOOD

REQ[4:0]#

RESET#

RESERVED

RS[2:0]#

SKTOCC#

Type

Input

Input/

Output

Input

Input

Output

Description

PWRGOOD (Power Good) is a processor input. The processor requires this signal to be a clean indication that the clocks and power supplies are stable and within their specifications. ‘Clean’ implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification. The signal must then transition monotonically to a high state. PWRGOOD can be driven inactive at any time, but clocks and power must again be stable before a subsequent rising edge of PWRGOOD.

The PWRGOOD signal must be supplied to the processor; it is used to protect internal circuits against voltage sequencing issues. It should be driven high throughout boundary scan operation.

REQ[4:0]# (Request Command) must connect the appropriate pins/lands of all processor FSB agents. They are asserted by the current bus owner to define the currently active transaction type.

These signals are source synchronous to ADSTB0#.

Asserting the RESET# signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents. For a power-on Reset, RESET# must stay active for at least one millisecond after V

CC

and BCLK have reached their proper specifications. On observing active RESET#, all FSB agents will deassert their outputs within two clocks. RESET# must not be kept asserted for more than 10 ms while PWRGOOD is asserted.

A number of bus signals are sampled at the active-to-inactive transition of RESET# for power-on configuration. These configuration options are described in the Section 6.1

.

This signal does not have on-die termination and must be terminated on the system board.

All RESERVED lands must remain unconnected. Connection of these lands to V

CC

, V

SS

, V

TT

, or to any other signal (including each other) can result in component malfunction or incompatibility with future processors.

RS[2:0]# (Response Status) are driven by the response agent (the agent responsible for completion of the current transaction), and must connect the appropriate pins/lands of all processor FSB agents.

SKTOCC# (Socket Occupied) will be pulled to ground by the processor. System board designers may use this signal to determine if the processor is present.

70 Datasheet

Land Listing and Signal Descriptions

Table 24.

Signal Description (Sheet 8 of 10)

Name

SLP#

SMI#

STPCLK#

TCK

TDI

TDO

TESTHI[12,10:0]

Type

Input

Input

Input

Input

Input

Output

Input

Description

SLP# (Sleep), when asserted in Extended Stop Grant or Stop Grant state, causes the processor to enter the Sleep state. In the Sleep state, the processor stops providing internal clock signals to all units, leaving only the Phase-Locked Loop (PLL) still operating.

Processors in this state will not recognize snoops or interrupts. The processor will recognize only assertion of the RESET# signal, deassertion of SLP#, and removal of the BCLK input while in Sleep state. If SLP# is de-asserted, the processor exits Sleep state and returns to Extended Stop Grant or Stop Grant state, restarting its internal clock signals to the bus and processor core units. If

DPSLP# is asserted while in the Sleep state, the processor will exit the Sleep state and transition to the Deep Sleep state. Use of the

SLP# pin, and corresponding low power state, requires chipset support and may not be available on all platforms.

NOTE: Some processors may not have the Sleep State enabled, refer to the Specification Update for specific processor and stepping guidance.

SMI# (System Management Interrupt) is asserted asynchronously by system logic. On accepting a System Management Interrupt, the processor saves the current state and enter System Management

Mode (SMM). An SMI Acknowledge transaction is issued, and the processor begins program execution from the SMM handler.

If SMI# is asserted during the de-assertion of RESET#, the processor will tri-state its outputs.

STPCLK# (Stop Clock), when asserted, causes the processor to enter a low power Stop-Grant state. The processor issues a Stop-

Grant Acknowledge transaction, and stops providing internal clock signals to all processor core units except the FSB and APIC units.

The processor continues to snoop bus transactions and service interrupts while in Stop-Grant state. When STPCLK# is deasserted, the processor restarts its internal clock to all units and resumes execution. The assertion of STPCLK# has no effect on the bus clock; STPCLK# is an asynchronous input.

TCK (Test Clock) provides the clock input for the processor Test Bus

(also known as the Test Access Port).

TDI (Test Data In) transfers serial test data into the processor. TDI provides the serial input needed for JTAG specification support.

TDO (Test Data Out) transfers serial test data out of the processor.

TDO provides the serial output needed for JTAG specification support.

The TESTHI[12,10:0] lands must be connected to the processor’s appropriate power source (refer to VTT_OUT_LEFT and

VTT_OUT_RIGHT signal description) through a resistor for proper processor operation. See Section 2.4

for more details.

Datasheet 71

Land Listing and Signal Descriptions

Table 24.

Signal Description (Sheet 9 of 10)

Name

THERMTRIP#

TMS

TRDY#

TRST#

VCC

VCCA

VCCIOPLL

VCCPLL

VCC_SENSE

VCC_MB_

REGULATION

Type Description

Output

Input

Input

In the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached a temperature approximately 20 °C above the maximum T

C

.

Assertion of THERMTRIP# (Thermal Trip) indicates the processor junction temperature has reached a level beyond where permanent silicon damage may occur. Upon assertion of THERMTRIP#, the processor will shut off its internal clocks (thus, halting program execution) in an attempt to reduce the processor junction temperature. To protect the processor, its core voltage (V

CC

) must be removed following the assertion of THERMTRIP#. Driving of the

THERMTRIP# signal is enabled within 10 s of the assertion of

PWRGOOD (provided V

TT

and V

CC de-assertion of PWRGOOD (if V

TT are asserted) and is disabled on

or V

CC are not valid, THERMTRIP# may also be disabled). Once activated, THERMTRIP# remains latched until PWRGOOD, V

TT or V

CC is de-asserted. While the deassertion of the PWRGOOD, V

TT or V

CC signal will de-assert

THERMTRIP#, if the processor’s junction temperature remains at or above the trip level, THERMTRIP# will again be asserted within

10 s of the assertion of PWRGOOD (provided V

TT and V

CC are valid).

TMS (Test Mode Select) is a JTAG specification support signal used by debug tools.

TRDY# (Target Ready) is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer. TRDY# must connect the appropriate pins/lands of all FSB agents.

Input

Input

Input

Input

TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven low during power on Reset.

VCC are the power pins for the processor. The voltage supplied to these pins is determined by the VID[7:0] pins.

VCCA provides isolated power for internal PLLs on previous generation processors. It may be left as a No-Connect on boards supporting the processor.

VCCIOPLL provides isolated power for internal processor FSB PLLs on previous generation processors. It may be left as a No-Connect on boards supporting the processor.

Input VCCPLL provides isolated power for internal processor FSB PLLs.

Output

VCC_SENSE is an isolated low impedance connection to processor core power (V

CC

). It can be used to sense or measure voltage near the silicon with little noise.

Output

This land is provided as a voltage regulator feedback sense point for V

CC

. It is connected internally in the processor package to the sense point land U27 as described in the Voltage Regulator Design

Guide.

72 Datasheet

Land Listing and Signal Descriptions

Table 24.

Signal Description (Sheet 10 of 10)

Name

VID[7:0]

VID_SELECT

VRDSEL

VSS

VSSA

VSS_SENSE

VSS_MB_

REGULATION

VTT

VTT_OUT_LEFT

VTT_OUT_RIGHT

VTT_SEL

Type Description

Output

Output

Input

Input

Input

Output

Output

The VID (Voltage ID) signals are used to support automatic selection of power supply voltages (V

CC

). Refer to the Voltage

Regulator Design Guide for more information. The voltage supply for these signals must be valid before the VR can supply V

CC

to the processor. Conversely, the VR output must be disabled until the voltage supply for the VID signals becomes valid. The VID signals are needed to support the processor voltage specification variations. See Table 2 for definitions of these signals. The VR must supply the voltage that is requested by the signals, or disable itself.

This land is tied high on the processor package and is used by the

VR to choose the proper VID table. Refer to the Voltage Regulator

Design Guide for more information.

This input should be left as a no connect in order for the processor to boot. The processor will not boot on legacy platforms where this land is connected to V

SS

.

VSS are the ground pins for the processor and should be connected to the system ground plane.

VSSA provides isolated ground for internal PLLs on previous generation processors. It may be left as a No-Connect on boards supporting the processor.

VSS_SENSE is an isolated low impedance connection to processor core V

SS

. It can be used to sense or measure ground near the silicon with little noise.

This land is provided as a voltage regulator feedback sense point for V

SS

. It is connected internally in the processor package to the sense point land V27 as described in the Voltage Regulator Design

Guide.

Miscellaneous voltage supply.

Output

Output

The VTT_OUT_LEFT and VTT_OUT_RIGHT signals are included to provide a voltage supply for some signals that require termination to V

TT

on the motherboard.

The VTT_SEL signal is used to select the correct V

TT

voltage level for the processor. This land is connected internally in the package to V

SS

.

73 Datasheet

Land Listing and Signal Descriptions

74 Datasheet

Thermal Specifications and Design Considerations

5

5.1

Note:

5.1.1

Thermal Specifications and

Design Considerations

Processor Thermal Specifications

The processor requires a thermal solution to maintain temperatures within the operating limits as set forth in Section 5.1.1

. Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system. As processor technology changes, thermal management becomes increasingly crucial when building computer systems.

Maintaining the proper thermal environment is key to reliable, long-term system operation.

A complete thermal solution includes both component and system level thermal management features. Component level thermal solutions can include active or passive heatsinks attached to the processor Integrated Heat Spreader (IHS). Typical system level thermal solutions may consist of system fans combined with ducting and venting.

For more information on designing a component level thermal solution, refer to the appropriate Thermal and Mechanical Design Guidelines (see Section 1.2

).

The boxed processor will ship with a component thermal solution. Refer to Chapter 7 for details on the boxed processor.

Thermal Specifications

To allow for the optimal operation and long-term reliability of Intel processor-based systems, the system/processor thermal solution should be designed such that the processor remains within the minimum and maximum case temperature (T

C

) specifications when operating at or below the Thermal Design Power (TDP) value listed per frequency in Table 25 . Thermal solutions not designed to provide this level of thermal capability may affect the long-term reliability of the processor and system. For more details on thermal solution design, refer to the appropriate Thermal and

Mechanical Design Guidelines (see Section 1.2

).

The processor uses a methodology for managing processor temperatures that is intended to support acoustic noise reduction through fan speed control. Selection of the appropriate fan speed is based on the relative temperature data reported by the processor’s Platform Environment Control Interface (PECI) bus as described in

Section 5.3

. If the value reported using PECI is less than T

CONTROL

, then the case temperature is permitted to exceed the Thermal Profile. If the value reported using

PECI is greater than or equal to T

CONTROL

, then the processor case temperature must remain at or below the temperature as specified by the thermal profile. The temperature reported over PECI is always a negative value and represents a delta below the onset of thermal control circuit (TCC) activation, as indicated by PROCHOT#

(see Section 5.2

). Systems that implement fan speed control must be designed to take these conditions in to account. Systems that do not alter the fan speed only need to ensure the case temperature meets the thermal profile specifications.

To determine a processor's case temperature specification based on the thermal profile, it is necessary to accurately measure processor power dissipation. Intel has developed a methodology for accurate power measurement that correlates to Intel test temperature and voltage conditions. Refer to the appropriate Thermal and Mechanical

Design Guidelines (see Section 1.2

) for the details of this methodology.

Datasheet 75

Thermal Specifications and Design Considerations

The case temperature is defined at the geometric top center of the processor. Analysis indicates that real applications are unlikely to cause the processor to consume maximum power dissipation for sustained time periods. Intel recommends that complete thermal solution designs target the Thermal Design Power (TDP) indicated in

Table 25 instead of the maximum processor power consumption. The Thermal Monitor feature is designed to protect the processor in the unlikely event that an application exceeds the TDP recommendation for a sustained periods of time. For more details on the usage of this feature, refer to Section 5.2

. In all cases the Thermal Monitor or

Thermal Monitor 2 feature must be enabled for the processor to remain within specification.

Table 25.

Processor Thermal Specifications

Processor

Number

Core

Frequency

(GHz)

Thermal

Design

Power

(W)

3,4

E3500

E3400

E3300

E3200

2.70

2.60

2.50

2.40

65.0

65.0

65.0

65.0

Extended

HALT

Power

(W)

1

8

8

8

8

Deeper

Sleep

Power

(W)

2

6

6

6

6

775_VR_

CONFIG_06

Guidance

5

Minimum

T

C

(°C)

Maximum

T

C

(°C)

Notes

775_VR_CONFIG

_06

(65 W)

5

5

5

5

See

Table 26 and

Figure 13

NOTES:

1.

Specification is at 36 °C T

C

and minimum voltage loadline. Specification is ensured by design characterization and not 100% tested.

2.

3.

Specification is at 34 °C T

C

and minimum voltage loadline. Specification is ensured by design characterization and not 100% tested.

Thermal Design Power (TDP) should be used for processor thermal solution design targets.

4.

5.

The TDP is not the maximum power that the processor can dissipate.

This table shows the maximum TDP for a given frequency range. Individual processors may have a lower TDP. Therefore, the maximum T

C

will vary depending on the TDP of the individual processor. Refer to thermal profile figure and associated table for the allowed combinations of power and T

C

.

775_VR_CONFIG_06 guidelines provide a design target for meeting future thermal requirements.

76 Datasheet

Thermal Specifications and Design Considerations

Table 26.

14

16

18

8

10

12

20

22

0

2

4

6

Processor Thermal Profile

Power (W)

Maximum Tc

(°C)

44.9

45.8

46.7

47.6

48.5

49.4

50.3

51.2

52.1

53.0

53.9

54.8

Power

38

40

42

32

34

36

44

46

24

26

28

30

Figure 13.

Processor Series Thermal Profile

Maximum Tc

(°C)

55.7

56.6

57.5

58.4

59.3

60.2

61.1

62.0

62.9

63.8

64.7

65.6

Power

62

64

65

56

58

60

48

50

52

54

Maximum Tc

(°C)

66.5

67.4

68.3

69.2

70.1

71.0

71.9

72.8

73.7

74.1

72.0

68.0

64.0

60.0

56.0

52.0

48.0

44.0

0 10 20 y = 0.45x + 44.9

30

Power (W)

40 50 60

Datasheet 77

Thermal Specifications and Design Considerations

5.1.2

Thermal Metrology

The maximum and minimum case temperatures (T

C

) for the processor is specified in

Table 25 . This temperature specification is meant to help ensure proper operation of the processor. Figure 14 illustrates where Intel recommends T

C

thermal measurements should be made. For detailed guidelines on temperature measurement methodology, refer to the appropriate Thermal and Mechanical Design Guidelines (see Section 1.2

).

Figure 14.

Case Temperature (T

C

) Measurement Location

5.2

5.2.1

Processor Thermal Features

Thermal Monitor

The Thermal Monitor feature helps control the processor temperature by activating the thermal control circuit (TCC) when the processor silicon reaches its maximum operating temperature. The TCC reduces processor power consumption by modulating (starting and stopping) the internal processor core clocks. The Thermal Monitor feature must

be enabled for the processor to be operating within specifications. The temperature at which Thermal Monitor activates the thermal control circuit is not user configurable and is not software visible. Bus traffic is snooped in the normal manner, and interrupt requests are latched (and serviced during the time that the clocks are on) while the TCC is active.

When the Thermal Monitor feature is enabled, and a high temperature situation exists

(that is, TCC is active), the clocks will be modulated by alternately turning the clocks off and on at a duty cycle specific to the processor (typically 30–50%). Clocks often will not be off for more than 3.0 microseconds when the TCC is active. Cycle times are processor speed dependent and will decrease as processor core frequencies increase. A small amount of hysteresis has been included to prevent rapid active/inactive transitions of the TCC when the processor temperature is near its maximum operating temperature. Once the temperature has dropped below the maximum operating temperature, and the hysteresis timer has expired, the TCC goes inactive and clock modulation ceases.

With a properly designed and characterized thermal solution, it is anticipated that the

TCC would only be activated for very short periods of time when running the most power intensive applications. The processor performance impact due to these brief

78 Datasheet

Thermal Specifications and Design Considerations

5.2.2

periods of TCC activation is expected to be so minor that it would be immeasurable. An under-designed thermal solution that is not able to prevent excessive activation of the

TCC in the anticipated ambient environment may cause a noticeable performance loss, and in some cases may result in a T

C

that exceeds the specified maximum temperature and may affect the long-term reliability of the processor. In addition, a thermal solution that is significantly under-designed may not be capable of cooling the processor even when the TCC is active continuously. Refer to the appropriate Thermal and Mechanical

Design Guidelines (see Section 1.2

) for information on designing a thermal solution.

The duty cycle for the TCC, when activated by the Thermal Monitor, is factory configured and cannot be modified. The Thermal Monitor does not require any additional hardware, software drivers, or interrupt handling routines.

Thermal Monitor 2

The processor also supports an additional power reduction capability known as Thermal

Monitor 2. This mechanism provides an efficient means for limiting the processor temperature by reducing the power consumption within the processor.

When Thermal Monitor 2 is enabled, and a high temperature situation is detected, the

Thermal Control Circuit (TCC) will be activated. The TCC causes the processor to adjust its operating frequency (using the bus multiplier) and input voltage (using the VID signals). This combination of reduced frequency and VID results in a reduction to the processor power consumption.

A processor enabled for Thermal Monitor 2 includes two operating points, each consisting of a specific operating frequency and voltage. The first operating point represents the normal operating condition for the processor. Under this condition, the core-frequency-to-FSB multiple used by the processor is that contained in the

CLK_GEYSIII_STAT MSR and the VID is that specified in Table 4 . These parameters represent normal system operation.

The second operating point consists of both a lower operating frequency and voltage.

When the TCC is activated, the processor automatically transitions to the new frequency. This transition occurs very rapidly (on the order of 5 s). During the frequency transition, the processor is unable to service any bus requests, and consequently, all bus traffic is blocked. Edge-triggered interrupts will be latched and kept pending until the processor resumes operation at the new frequency.

Once the new operating frequency is engaged, the processor will transition to the new core operating voltage by issuing a new VID code to the voltage regulator. The voltage regulator must support dynamic VID steps to support Thermal Monitor 2. During the voltage change, it will be necessary to transition through multiple VID codes to reach the target operating voltage. Each step will likely be one VID table entry (see Table 4 ).

The processor continues to execute instructions during the voltage transition.

Operation at the lower voltage reduces the power consumption of the processor.

A small amount of hysteresis has been included to prevent rapid active/inactive transitions of the TCC when the processor temperature is near its maximum operating temperature. Once the temperature has dropped below the maximum operating temperature, and the hysteresis timer has expired, the operating frequency and voltage transition back to the normal system operating point. Transition of the VID code will occur first, in order to ensure proper operation once the processor reaches its normal operating frequency. Refer to Figure 15 for an illustration of this ordering.

Datasheet 79

Thermal Specifications and Design Considerations

Figure 15.

Thermal Monitor 2 Frequency and Voltage Ordering

T

TM2

f

MAX

f

TM2

VID

VID

TM2

Temperature

Frequency

VID

5.2.3

PROCHOT#

The PROCHOT# signal is asserted when a high temperature situation is detected, regardless of whether Thermal Monitor or Thermal Monitor 2 is enabled.

It should be noted that the Thermal Monitor 2 TCC cannot be activated using the ondemand mode. The Thermal Monitor TCC, however, can be activated through the use of the on-demand mode.

On-Demand Mode

The processor provides an auxiliary mechanism that allows system software to force the processor to reduce its power consumption. This mechanism is referred to as “On-

Demand” mode and is distinct from the Thermal Monitor feature. On-Demand mode is intended as a means to reduce system level power consumption. Systems using the processor must not rely on software usage of this mechanism to limit the processor temperature.

If bit 4 of the ACPI P_CNT Control Register (located in the processor

IA32_THERM_CONTROL MSR) is written to a '1', the processor will immediately reduce its power consumption using modulation (starting and stopping) of the internal core clock, independent of the processor temperature. When using On-Demand mode, the duty cycle of the clock modulation is programmable using bits 3:1 of the same ACPI

P_CNT Control Register. In On-Demand mode, the duty cycle can be programmed from

12.5% on/87.5% off, to 87.5% on/12.5% off in 12.5% increments. On-Demand mode may be used in conjunction with the Thermal Monitor. If the system tries to enable On-

Demand mode at the same time the TCC is engaged, the factory configured duty cycle of the TCC will override the duty cycle selected by the On-Demand mode.

80 Datasheet

Thermal Specifications and Design Considerations

5.2.4

Note:

5.2.5

PROCHOT# Signal

An external signal, PROCHOT# (processor hot), is asserted when the processor core temperature has reached its maximum operating temperature. If the Thermal Monitor is enabled (note that the Thermal Monitor must be enabled for the processor to be operating within specification), the TCC will be active when PROCHOT# is asserted. The processor can be configured to generate an interrupt upon the assertion or deassertion of PROCHOT#.

PROCHOT# is a bi-directional signal. As an output, PROCHOT# (Processor Hot) will go active when the processor temperature monitoring sensor detects that one or both cores has reached its maximum safe operating temperature. This indicates that the processor Thermal Control Circuit (TCC) has been activated, if enabled. As an input, assertion of PROCHOT# by the system will activate the TCC, if enabled, for both cores.

The TCC will remain active until the system de-asserts PROCHOT#.

PROCHOT# will not be asserted (as an output) or observed (as an input) when the processor is in the Stop Grant, Sleep, Deep Sleep, and Deeper Sleep low-power states, hence the thermal solution must be designed to ensure the processor remains within specification. If the processor enters one of the above low-power states with

PROCHOT# already asserted, PROCHOT# will remain asserted until the processor exits the low-power state and the processor DTS temperature drops below the thermal trip point.

PROCHOT# allows for some protection of various components from over-temperature situations. The PROCHOT# signal is bi-directional in that it can either signal when the processor (either core) has reached its maximum operating temperature or be driven from an external source to activate the TCC. The ability to activate the TCC using

PROCHOT# can provide a means for thermal protection of system components.

Bi-directional PROCHOT# can allow VR thermal designs to target maximum sustained current instead of maximum current. Systems should still provide proper cooling for the

VR, and rely on bi-directional PROCHOT# only as a backup in case of system cooling failure. The system thermal design should allow the power delivery circuitry to operate within its temperature specification even while the processor is operating at its Thermal

Design Power. With a properly designed and characterized thermal solution, it is anticipated that bi-directional PROCHOT# would only be asserted for very short periods of time when running the most power intensive applications. An under-designed thermal solution that is not able to prevent excessive assertion of PROCHOT# in the anticipated ambient environment may cause a noticeable performance loss. Refer to the Voltage Regulator Design Guide for details on implementing the bi-directional

PROCHOT# feature.

THERMTRIP# Signal

Regardless of whether or not Thermal Monitor or Thermal Monitor 2 is enabled, in the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached an elevated temperature (refer to the THERMTRIP# definition in

Table 24 ). At this point, the FSB signal THERMTRIP# will go active and stay active as described in Table 24 . THERMTRIP# activation is independent of processor activity and does not generate any bus cycles. If THERMTRIP# is asserted, processor core voltage

(V

CC

) must be removed within the timeframe defined in Table 10 .

Datasheet 81

Thermal Specifications and Design Considerations

5.3

Platform Environment Control Interface (PECI)

5.3.1

Introduction

PECI offers an interface for thermal monitoring of Intel processor and chipset components. It uses a single wire, thus alleviating routing congestion issues. PECI uses

CRC checking on the host side to ensure reliable transfers between the host and client devices. Also, data transfer speeds across the PECI interface are negotiable within a wide range (2 Kbps to 2 Mbps). The PECI interface on the processor is disabled by default and must be enabled through BIOS. More information can be found in the

Platform Environment Control Interface (PECI) Specification.

5.3.1.1

T

CONTROL

and TCC activation on PECI-Based Systems

Fan speed control solutions based on PECI use a T

CONTROL

IA32_TEMPERATURE_TARGET MSR. The T

CONTROL

value stored in the processor

MSR uses the same offset temperature format as PECI though it contains no sign bit. Thermal management devices should infer the T

CONTROL

value as negative. Thermal management algorithms should use the relative temperature value delivered over PECI in conjunction with the

T

CONTROL

MSR value to control or optimize fan speeds. Figure 16 shows a conceptual fan control diagram using PECI temperatures.

The relative temperature value reported over PECI represents the delta below the onset of thermal control circuit (TCC) activation as indicated by PROCHOT# assertions. As the temperature approaches TCC activation, the PECI value approaches zero. TCC activates at a PECI count of zero.

Figure 16.

Conceptual Fan Control Diagram on PECI-Based Platforms

82 Datasheet

Thermal Specifications and Design Considerations

5.3.2

5.3.2.1

5.3.2.2

5.3.2.3

5.3.2.4

Table 27.

PECI Specifications

PECI Device Address

The PECI register resides at address 30h.

PECI Command Support

PECI command support is covered in detail in the Platform Environment Control

Interface Specification. Refer to this document for details on supported PECI command function and codes.

PECI Fault Handling Requirements

PECI is largely a fault tolerant interface, including noise immunity and error checking improvements over other comparable industry standard interfaces. The PECI client is as reliable as the device that it is embedded in, and thus given operating conditions that fall under the specification, the PECI will always respond to requests and the protocol itself can be relied upon to detect any transmission failures. There are, however, certain scenarios where the PECI is know to be unresponsive.

Prior to a power-on RESET# and during RESET# assertion, PECI is not assured to provide reliable thermal data. System designs should implement a default power-on condition that ensures proper processor operation during the time frame when reliable data is not available using PECI.

To protect platforms from potential operational or safety issues due to an abnormal condition on PECI, the Host controller should take action to protect the system from possible damage. It is recommended that the PECI host controller take appropriate action to protect the client processor device if valid temperature readings have not been obtained in response to three consecutive GetTemp()s or for a one second time interval. The host controller may also implement an alert to software in the event of a critical or continuous fault condition.

PECI GetTemp0() Error Code Support

The error codes supported for the processor GetTemp() command are listed in

Table 27 :

GetTemp0() Error Codes

Error Code

8000h

8002h

Description

General sensor error

Sensor is operational, but has detected a temperature below its operational range (underflow)

§ §

Datasheet 83

Thermal Specifications and Design Considerations

84 Datasheet

Features

6 Features

6.1

Table 28.

Power-On Configuration Options

Several configuration options can be configured by hardware. The processor samples the hardware configuration at reset, on the active-to-inactive transition of RESET#. For specifications on these options, refer to Table 28 .

The sampled information configures the processor for subsequent operation. These configuration options cannot be changed except by another reset. All resets reconfigure the processor; for configuration purposes, the processor does not distinguish between a "warm" reset and a "power-on" reset.

Power-On Configuration Option Signals

Configuration Option

Output tristate

Execute BIST

Disable dynamic bus parking

Symmetric agent arbitration ID

RESERVED

Signal 1,2

SMI#

A3#

A25#

BR0#

A[24:4]#, A[35:26]#

NOTE:

1.

2.

3.

Asserting this signal during RESET# will select the corresponding option.

Address signals not identified in this table as configuration options should not be asserted during RESET#.

Disabling of any of the cores within the processors must be handled by configuring the

EXT_CONFIG Model Specific Register (MSR). This MSR will allow for the disabling of a single core per die within the processor package.

6.2

Clock Control and Low Power States

The processor allows the use of AutoHALT and Stop-Grant states to reduce power consumption by stopping the clock to internal sections of the processor, depending on each particular state. See Figure 17 for a visual representation of the processor low power states.

Datasheet 85

Features

Figure 17.

Processor Low Power State Machine

Normal State

- Normal Execution

HALT or MWAIT Instruction and

HALT Bus Cycle Generated

INIT#, INTR, NMI, SMI#, RESET#,

FSB interrupts

Extended HALT or HALT

State

- BCLK running

- Snoops and interrupts

allowed

6.2.1

6.2.2

STPCLK#

Asserted

STPCLK#

De-asserted

Snoop

Event

Occurs

Snoop

Event

Serviced

STPCLK#

Asserted

STPCLK#

De-asserted

Stop Grant State

- BCLK running

- Snoops and interrupts

allowed

Snoop Event Occurs

Snoop Event Serviced

Extended HALT Snoop or

HALT Snoop State

- BCLK running

- Service Snoops to caches

Extended Stop Grant or

Stop Grant Snoop State

- BCLK running

- Service Snoops to caches

SLP#

Asserted

SLP#

De-asserted

DPSLP#

Asserted

Sleep State

- BCLK running

- No Snoops or

interrupts allowed

- PECI unavailable in

this state

DPSLP#

De-asserted

Deep Sleep State

- BCLK can be stopped

- No Snoops or

interrupts allowed

- PECI unavailable in

this state

DPRSTP#

Asserted

DPRSTP#

De-asserted

Deeper Sleep State

- BCLK can be stopped

- No Snoops or

interrupts allowed

- PECI unavailable in

this state

Normal State

This is the normal operating state for the processor.

HALT and Extended HALT Powerdown States

The processor supports the HALT or Extended HALT powerdown state. The Extended

HALT powerdown state must be configured and enabled using the BIOS for the processor to remain within specification.

The Extended HALT state is a lower power state as compared to the Stop Grant State.

If Extended HALT is not enabled, the default powerdown state entered will be HALT.

Refer to the sections below for details about the HALT and Extended HALT states.

86 Datasheet

Features

6.2.2.1

6.2.2.2

6.2.3

6.2.3.1

HALT Powerdown State

HALT is a low power state entered when all the processor cores have executed the HALT or MWAIT instructions. When one of the processor cores executes the HALT instruction, that processor core is halted, however, the other processor continues normal operation.

The halted core will transition to the Normal state upon the occurrence of SMI#, INIT#, or LINT[1:0] (NMI, INTR). RESET# will cause the processor to immediately initialize itself.

The return from a System Management Interrupt (SMI) handler can be to either

Normal Mode or the HALT powerdown state. See the Intel Architecture Software

Developer's Manual, Volume 3B: System Programming Guide, Part 2 for more information.

The system can generate a STPCLK# while the processor is in the HALT powerdown state. When the system de-asserts the STPCLK# interrupt, the processor will return execution to the HALT state.

While in HALT powerdown state, the processor will process bus snoops.

Extended HALT Powerdown State

Extended HALT is a low power state entered when all processor cores have executed the HALT or MWAIT instructions and Extended HALT has been enabled using the BIOS.

When one of the processor cores executes the HALT instruction, that logical processor is halted; however, the other processor continues normal operation. The Extended

HALT powerdown state must be enabled using the BIOS for the processor to remain within its specification.

The processor will automatically transition to a lower frequency and voltage operating point before entering the Extended HALT state. Note that the processor FSB frequency is not altered; only the internal core frequency is changed. When entering the low power state, the processor will first switch to the lower bus ratio and then transition to the lower VID.

While in Extended HALT state, the processor will process bus snoops.

The processor exits the Extended HALT state when a break event occurs. When the processor exits the Extended HALT state, it will resume operation at the lower frequency, transition the VID to the original value, and then change the bus ratio back to the original value.

Stop Grant and Extended Stop Grant States

The processor supports the Stop Grant and Extended Stop Grant states. The Extended

Stop Grant state is a feature that must be configured and enabled using the BIOS.

Refer to the sections below for details about the Stop Grant and Extended Stop Grant states.

Stop-Grant State

When the STPCLK# signal is asserted, the Stop Grant state of the processor is entered

20 bus clocks after the response phase of the processor-issued Stop Grant

Acknowledge special bus cycle.

Since the GTL+ signals receive power from the FSB, these signals should not be driven

(allowing the level to return to V

TT

) for minimum power drawn by the termination resistors in this state. In addition, all other input signals on the FSB should be driven to the inactive state.

Datasheet 87

Features

6.2.3.2

6.2.4

6.2.4.1

6.2.4.2

RESET# will cause the processor to immediately initialize itself, but the processor will stay in Stop-Grant state. A transition back to the Normal state will occur with the deassertion of the STPCLK# signal.

A transition to the Grant Snoop state will occur when the processor detects a snoop on the FSB (see Section 6.2.4

).

While in the Stop-Grant State, SMI#, INIT# and LINT[1:0] will be latched by the processor, and only serviced when the processor returns to the Normal State. Only one occurrence of each event will be recognized upon return to the Normal state.

While in Stop-Grant state, the processor will process a FSB snoop.

Extended Stop Grant State

Extended Stop Grant is a low power state entered when the STPCLK# signal is asserted and Extended Stop Grant has been enabled using the BIOS.

The processor will automatically transition to a lower frequency and voltage operating point before entering the Extended Stop Grant state. When entering the low power state, the processor will first switch to the lower bus ratio and then transition to the lower VID.

The processor exits the Extended Stop Grant state when a break event occurs. When the processor exits the Extended Stop Grant state, it will resume operation at the lower frequency, transition the VID to the original value, and then change the bus ratio back to the original value.

Extended HALT Snoop State, HALT Snoop State, Extended

Stop Grant Snoop State, and Stop Grant Snoop State

The Extended HALT Snoop State is used in conjunction with the Extended HALT state. If

Extended HALT state is not enabled in the BIOS, the default Snoop State entered will be the HALT Snoop State. Refer to the sections below for details on HALT Snoop State,

Stop Grant Snoop State, Extended HALT Snoop State, Extended Stop Grant Snoop

State.

HALT Snoop State, Stop Grant Snoop State

The processor will respond to snoop transactions on the FSB while in Stop-Grant state or in HALT powerdown state. During a snoop transaction, the processor enters the HALT

Snoop State:Stop Grant Snoop state. The processor will stay in this state until the snoop on the FSB has been serviced (whether by the processor or another agent on the

FSB). After the snoop is serviced, the processor will return to the Stop Grant state or

HALT powerdown state, as appropriate.

Extended HALT Snoop State, Extended Stop Grant Snoop State

The processor will remain in the lower bus ratio and VID operating point of the

Extended HALT state or Extended Stop Grant state.

While in the Extended HALT Snoop State or Extended Stop Grant Snoop State, snoops are handled the same way as in the HALT Snoop State or Stop Grant Snoop State. After the snoop is serviced the processor will return to the Extended HALT state or Extended

Stop Grant state.

88 Datasheet

Features

6.2.5

6.2.6

Sleep State

The Sleep state is a low power state in which the processor maintains its context, maintains the phase-locked loop (PLL), and stops all internal clocks. The Sleep state is entered through assertion of the SLP# signal while in the Extended Stop Grant or Stop

Grant state. The SLP# pin should only be asserted when the processor is in the

Extended Stop Grant or Stop Grant state. SLP# assertions while the processor is not in these states is out of specification and may result in unapproved operation.

In the Sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals. No transitions or assertions of signals (with the exception of

SLP#, DPSLP# or RESET#) are allowed on the FSB while the processor is in Sleep state. Snoop events that occur while in Sleep state or during a transition into or out of

Sleep state will cause unpredictable behavior. Any transition on an input signal before the processor has returned to the Stop-Grant state will result in unpredictable behavior.If RESET# is driven active while the processor is in the Sleep state, and held active as specified in the RESET# pin specification, then the processor will reset itself, ignoring the transition through the Stop-Grant state.

If RESET# is driven active while the processor is in the Sleep state, the SLP# and

STPCLK# signals should be de-asserted immediately after RESET# is asserted to ensure the processor correctly executes the Reset sequence.

While in the Sleep state, the processor is capable of entering an even lower power state, the Deep Sleep state, by asserting the DPSLP# pin (See Section 7.2.6). While the processor is in the Sleep state, the SLP# pin must be de-asserted if another asynchronous FSB event needs to occur. PECI is not available and will not respond while in the Sleep State. Refer to the appropriate Thermal and Mechanical Design

Guidelines (see Section 1.2

) for guidance on how to ensure PECI thermal data is available when the Sleep State is enabled.

Deep Sleep State

The Deep Sleep state is entered through assertion of the DPSLP# pin while in the Sleep state. BCLK may be stopped during the Deep Sleep state for additional platform level power savings. BCLK stop/restart timings on appropriate chipset-based platforms with the CK505 clock chip are as follows:

• Deep Sleep entry: the system clock chip may stop/tristate BCLK within two BCLKs of DPSLP# assertion. It is permissible to leave BCLK running during Deep Sleep.

• Deep Sleep exit: the system clock chip must drive BCLK to differential DC levels within 2-3 ns of DPSLP# de-assertion and start toggling BCLK within 10 BCLK periods.

To re-enter the Sleep state, the DPSLP# pin must be de-asserted. BCLK can be restarted after DPSLP# de-assertion as described above. A period of 15 microseconds

(to allow for PLL stabilization) must occur before the processor can be considered to be in the Sleep state. Once in the Sleep state, the SLP# pin must be de-asserted to reenter the Stop-Grant state.

While in the Deep Sleep state the processor is incapable of responding to snoop transactions or latching interrupt signals. No transitions of signals are allowed on the

FSB while the processor is in the Deep Sleep state. When the processor is in the Deep

Sleep state it will not respond to interrupts or snoop transactions. Any transition on an input signal before the processor has returned to the Stop-Grant state will result in unpredictable behavior. PECI is not available and will not respond while in the Deep

Sleep State. Refer to the appropriate Thermal and Mechanical Design Guidelines (see

Section 1.2

) for guidance on how to ensure PECI thermal data is available when the

Deep Sleep State is enabled.

Datasheet 89

Features

6.2.7

6.2.8

6.3

Deeper Sleep State

The Deeper Sleep state is similar to the Deep Sleep state but the core voltage is reduced to a lower level. The Deeper Sleep state is entered through assertion of the

DPRSTP# pin while in the Deep Sleep state. Exit from Deeper Sleep is initiated by

DPRSTP# de-assertion. PECI is not available and will not respond while in the Deeper

Sleep State. Refer to the appropriate Thermal and Mechanical Design Guidelines (see

Section 1.2

) for guidance on how to ensure PECI thermal data is available when the

Deeper Sleep State is enabled.

In response to entering Deeper Sleep, the processor drives the VID code corresponding to the Deeper Sleep core voltage on the VID pins. Unlike typical Dynamic VID changes

(where the steps are single VID steps) the processor will perform a VID jump on the order of 100 mV. To support the Deeper Sleep State the platform must use a VRD 11.1 compliant solution.

Enhanced Intel SpeedStep

®

Technology

The processor supports Enhanced Intel SpeedStep Technology. This technology enables the processor to switch between frequency and voltage points that may result in platform power savings. To support this technology, the system must support dynamic

VID transitions. Switching between voltage/frequency states is software controlled.

Enhanced Intel SpeedStep Technology is a technology that creates processor performance states (P states). P states are power consumption and capability states within the Normal state as shown in Figure 17 . Enhanced Intel SpeedStep Technology enables real-time dynamic switching between frequency and voltage points. It alters the performance of the processor by changing the bus to core frequency ratio and voltage. This allows the processor to run at different core frequencies and voltages to best serve the performance and power requirements of the processor and system. Note that the front side bus is not altered; only the internal core frequency is changed. To run at reduced power consumption, the voltage is altered in step with the bus ratio.

The following are key features of Enhanced Intel SpeedStep Technology:

• Voltage/Frequency selection is software controlled by writing to processor MSR's

(Model Specific Registers), thus eliminating chipset dependency.

— If the target frequency is higher than the current frequency, Vcc is incriminated in steps (+12.5 mV) by placing a new value on the VID signals after which the processor shifts to the new frequency. Note that the top frequency for the processor can not be exceeded.

— If the target frequency is lower than the current frequency, the processor shifts to the new frequency and Vcc is then decremented in steps (-12.5 mV) by changing the target VID through the VID signals.

Processor Power Status Indicator (PSI) Signal

The processor incorporates the PSI# signal that is asserted when the processor is in a reduced power consumption state. PSI# can be used to improve efficiency of the voltage regulator, resulting in platform power savings.

PSI# may be asserted only when the processor is in the Deeper Sleep state.

§

90 Datasheet

Boxed Processor Specifications

7 Boxed Processor Specifications

7.1

Introduction

Note:

The processor will also be offered as an Intel boxed processor. Intel boxed processors are intended for system integrators who build systems from baseboards and standard components. The boxed processor will be supplied with a cooling solution. This chapter documents baseboard and system requirements for the cooling solution that will be supplied with the boxed processor. This chapter is particularly important for OEMs that manufacture baseboards for system integrators.

Unless otherwise noted, all figures in this chapter are dimensioned in millimeters and inches [in brackets]. Figure 18 shows a mechanical representation of a boxed processor.

Note:

Drawings in this section reflect only the specifications on the Intel boxed processor product. These dimensions should not be used as a generic keep-out zone for all cooling solutions. It is the system designers’ responsibility to consider their proprietary cooling solution when designing to the required keep-out zone on their system platforms and chassis. Refer to the appropriate Thermal and Mechanical Design

Guidelines (see Section 1.2

) for further guidance. Contact your local Intel Sales

Representative for this document.

Figure 18.

Mechanical Representation of the Boxed Processor

Datasheet

NOTE: The airflow of the fan heatsink is into the center and out of the sides of the fan heatsink.

91

Boxed Processor Specifications

7.2

Mechanical Specifications

7.2.1

Boxed Processor Cooling Solution Dimensions

This section documents the mechanical specifications of the boxed processor. The boxed processor will be shipped with an unattached fan heatsink. Figure 18 shows a mechanical representation of the boxed processor.

Clearance is required around the fan heatsink to ensure unimpeded airflow for proper cooling. The physical space requirements and dimensions for the boxed processor with assembled fan heatsink are shown in Figure 19 (Side View), and Figure 20 (Top View).

The airspace requirements for the boxed processor fan heatsink must also be incorporated into new baseboard and system designs. Airspace requirements are shown in Figure 24 and Figure 25 . Note that some figures have centerlines shown

(marked with alphabetic designations) to clarify relative dimensioning.

Figure 19.

Space Requirements for the Boxed Processor (Side View)

95.0

[3.74]

81.3

[3.2]

10.0

[0.39]

25.0

[0.98]

Figure 20.

Space Requirements for the Boxed Processor (Top View)

95.0

[3.74]

B d P Sid Vi

95.0

[3.74]

92

NOTES:

1.

Diagram does not show the attached hardware for the clip design and is provided only as a mechanical representation.

Datasheet

Boxed Processor Specifications

Figure 21.

Overall View Space Requirements for the Boxed Processor

7.2.2

7.2.3

7.3

7.3.1

Boxed Processor Fan Heatsink Weight

The boxed processor fan heatsink will not weigh more than 450 grams. See Chapter 5 and the appropriate Thermal and Mechanical Design Guidelines (see Section 1.2

) for details on the processor weight and heatsink requirements.

Boxed Processor Retention Mechanism and Heatsink

Attach Clip Assembly

The boxed processor thermal solution requires a heatsink attach clip assembly, to secure the processor and fan heatsink in the baseboard socket. The boxed processor will ship with the heatsink attach clip assembly.

Electrical Requirements

Fan Heatsink Power Supply

The boxed processor's fan heatsink requires a +12 V power supply. A fan power cable will be shipped with the boxed processor to draw power from a power header on the baseboard. The power cable connector and pinout are shown in Figure 22 . Baseboards must provide a matched power header to support the boxed processor. Table 29 contains specifications for the input and output signals at the fan heatsink connector.

The fan heatsink outputs a SENSE signal that is an open- collector output that pulses at a rate of 2 pulses per fan revolution. A baseboard pull-up resistor provides V

OH

to match the system board-mounted fan speed monitor requirements, if applicable. Use of the SENSE signal is optional. If the SENSE signal is not used, pin 3 of the connector should be tied to GND.

The fan heatsink receives a PWM signal from the motherboard from the 4th pin of the connector labeled as CONTROL.

Datasheet 93

Boxed Processor Specifications

The boxed processor's fanheat sink requires a constant +12 V supplied to pin 2 and does not support variable voltage control or 3-pin PWM control.

The power header on the baseboard must be positioned to allow the fan heatsink power cable to reach it. The power header identification and location should be documented in the platform documentation, or on the system board itself. Figure 23 shows the location of the fan power connector relative to the processor socket. The baseboard power header should be positioned within 110 mm [4.33 inches] from the center of the processor socket.

Figure 22.

Boxed Processor Fan Heatsink Power Cable Connector Description

1

2

3

4

Pin Signal

GND

+12 V

SENSE

CONTROL

Straight square pin, 4-pin terminal housing with polarizing ribs and friction locking ramp.

0.100" pitch, 0.025" square pin width.

Match with straight pin, friction lock header on mainboard.

1 2 3 4

Table 29.

Fan Heatsink Power and Signal Specifications

Description

+12 V: 12 volt fan power supply

IC:

• Maximum fan steady-state current draw

• Average fan steady-state current draw

• Maximum fan start-up current draw

• Fan start-up current draw maximum duration

Min

11.4

—

—

—

—

Typ

12

1.2

0.5

2.2

1.0

SENSE: SENSE frequency — 2

CONTROL 21 25

NOTES:

1. Baseboard should pull this pin up to 5 V with a resistor.

2. Open drain type, pulse width modulated.

3. Fan will have pull-up resistor for this signal to maximum of 5.25 V.

Max

12.6

—

—

—

—

—

28

Unit

V

Notes

-

A

A

A

Second pulses per fan revolution kHz

-

1

2, 3

94 Datasheet

Boxed Processor Specifications

Figure 23.

Baseboard Power Header Placement Relative to Processor Socket

R110

[4.33]

B

C

7.4

7.4.1

Thermal Specifications

This section describes the cooling requirements of the fan heatsink solution used by the boxed processor.

Boxed Processor Cooling Requirements

The boxed processor may be directly cooled with a fan heatsink. However, meeting the processor's temperature specification is also a function of the thermal design of the entire system, and ultimately the responsibility of the system integrator. The processor temperature specification is provided in Chapter 5 . The boxed processor fan heatsink is able to keep the processor temperature within the specifications (see Table 25 ) in chassis that provide good thermal management. For the boxed processor fan heatsink to operate properly, it is critical that the airflow provided to the fan heatsink is unimpeded. Airflow of the fan heatsink is into the center and out of the sides of the fan heatsink. Airspace is required around the fan to ensure that the airflow through the fan heatsink is not blocked. Blocking the airflow to the fan heatsink reduces the cooling efficiency and decreases fan life. Figure 24 and Figure 25 illustrate an acceptable airspace clearance for the fan heatsink. The air temperature entering the fan should be kept below 38 ºC. Again, meeting the processor's temperature specification is the responsibility of the system integrator.

Datasheet 95

Boxed Processor Specifications

Figure 24.

Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 1 view)

Figure 25.

Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 2 view)

96 Datasheet

Boxed Processor Specifications

7.4.2

Variable Speed Fan

If the boxed processor fan heatsink 4-pin connector is connected to a 3-pin motherboard header it will operate as follows:

The boxed processor fan will operate at different speeds over a short range of internal chassis temperatures. This allows the processor fan to operate at a lower speed and noise level, while internal chassis temperatures are low. If internal chassis temperature increases beyond a lower set point, the fan speed will rise linearly with the internal temperature until the higher set point is reached. At that point, the fan speed is at its maximum. As fan speed increases, so does fan noise levels. Systems should be designed to provide adequate air around the boxed processor fan heatsink that remains cooler then lower set point. These set points, represented in Figure 26 and Table 30 , can vary by a few degrees from fan heatsink to fan heatsink. The internal chassis temperature should be kept below 38 ºC.

Meeting the processor's temperature specification (see Chapter 5 ) is the responsibility of the system integrator.

The motherboard must supply a constant +12 V to the processor's power header to ensure proper operation of the variable speed fan for the boxed processor. Refer to

Table 29 for the specific requirements.

Figure 26.

Boxed Processor Fan Heatsink Set Points

Higher Set Point

Highest Noise Level

Increasing Fan

Speed & Noise

Lower Set Point

Lowest Noise Level

X

Y

Internal Chassis Temperature (Degrees C)

Z

Datasheet 97

Boxed Processor Specifications

Table 30.

Fan Heatsink Power and Signal Specifications

Boxed Processor

Fan Heatsink Set

Point (°C)

Boxed Processor Fan Speed

X 30

Y = 35

When the internal chassis temperature is below or equal to this set point, the fan operates at its lowest speed.

Recommended maximum internal chassis temperature for nominal operating environment.

When the internal chassis temperature is at this point, the fan operates between its lowest and highest speeds.

Recommended maximum internal chassis temperature for worst-case operating environment.

Z 38

When the internal chassis temperature is above or equal to this set point, the fan operates at its highest speed.

NOTES:

1. Set point variance is approximately ± 1 C from fan heatsink to fan heatsink.

Notes

1

-

-

If the boxed processor fan heatsink 4-pin connector is connected to a 4-pin motherboard header and the motherboard is designed with a fan speed controller with

PWM output (CONTROL see Table 29 ) and remote thermal diode measurement capability the boxed processor will operate as follows:

As processor power has increased the required thermal solutions have generated increasingly more noise. Intel has added an option to the boxed processor that allows system integrators to have a quieter system in the most common usage.

The 4th wire PWM solution provides better control over chassis acoustics. This is achieved by more accurate measurement of processor die temperature through the processor's Digital Thermal Sensors (DTS) and PECI. Fan RPM is modulated through the use of an ASIC located on the motherboard that sends out a PWM control signal to the

4th pin of the connector labeled as CONTROL. The fan speed is based on actual processor temperature instead of internal ambient chassis temperatures.

If the new 4-pin active fan heat sink solution is connected to an older 3-pin baseboard processor fan header, it will default back to a thermistor controlled mode, allowing compatibility with existing 3-pin baseboard designs. Under thermistor controlled mode, the fan RPM is automatically varied based on the Tinlet temperature measured by a thermistor located at the fan inlet.

For more details on specific motherboard requirements for 4-wire based fan speed control, refer to the appropriate Thermal and Mechanical Design Guidelines (see

Section 1.2

).

§

98 Datasheet

Debug Tools Specifications

8

8.1

8.1.1

8.1.2

Debug Tools Specifications

Logic Analyzer Interface (LAI)

Intel is working with two logic analyzer vendors to provide logic analyzer interfaces

(LAIs) for use in debugging Intel Celeron

®

processor E3000 series systems. Tektronix and Agilent should be contacted to get specific information about their logic analyzer interfaces. The following information is general in nature. Specific information must be obtained from the logic analyzer vendor.

Due to the complexity of Intel Celeron

®

processor E3000 series systems, the LAI is critical in providing the ability to probe and capture FSB signals. There are two sets of considerations to keep in mind when designing an Intel Celeron

®

processor E3000 series system that can make use of an LAI: mechanical and electrical.

Mechanical Considerations

The LAI is installed between the processor socket and the processor. The LAI lands plug into the processor socket, while the processor lands plug into a socket on the LAI.

Cabling that is part of the LAI egresses the system to allow an electrical connection between the processor and a logic analyzer. The maximum volume occupied by the LAI, known as the keepout volume, as well as the cable egress restrictions, should be obtained from the logic analyzer vendor. System designers must make sure that the keepout volume remains unobstructed inside the system. Note that it is possible that the keepout volume reserved for the LAI may differ from the space normally occupied by the processor heatsink. If this is the case, the logic analyzer vendor will provide a cooling solution as part of the LAI.

Electrical Considerations

The LAI will also affect the electrical performance of the FSB; therefore, it is critical to obtain electrical load models from each of the logic analyzers to be able to run system level simulations to prove that their tool will work in the system. Contact the logic analyzer vendor for electrical specifications and load models for the LAI solution it provides.

§

Datasheet 99

Debug Tools Specifications

100 Datasheet