Die Voltage Validation. Intel E3300

Electrical Specifications

Figure 2.

V

CC

Overshoot Example Waveform

Example Overshoot Waveform

V

OS

VID + 0.050

VID - 0.000

2.6.4

2.7

0 5

T

OS

10

Time [us]

15

T

OS

: Overshoot time above VID

V

OS

: Overshoot above VID

20 25

NOTES:

1.

2.

V

OS

is measured overshoot voltage.

T

OS

is measured time duration above VID.

Die Voltage Validation

Overshoot events on processor must meet the specifications in Table 6 when measured across the VCC_SENSE and VSS_SENSE lands. Overshoot events that are < 10 ns in duration may be ignored. These measurements of processor die level overshoot must be taken with a bandwidth limited oscilloscope set to a greater than or equal to 100

MHz bandwidth limit.

Signaling Specifications

Most processor Front Side Bus signals use Gunning Transceiver Logic (GTL+) signaling technology. This technology provides improved noise margins and reduced ringing through low voltage swings and controlled edge rates. Platforms implement a termination voltage level for GTL+ signals defined as V

TT

. Because platforms implement separate power planes for each processor (and chipset), separate V

CC

and V

TT supplies are necessary. This configuration allows for improved noise tolerance as processor frequency increases. Speed enhancements to data and address busses have caused signal integrity considerations and platform design methods to become even more critical than with previous processor families.

The GTL+ inputs require a reference voltage (GTLREF) that is used by the receivers to determine if a signal is a logical 0 or a logical 1. GTLREF must be generated on the motherboard (see Table 14 for GTLREF specifications). Termination resistors (R

TT

GTL+ signals are provided on the processor silicon and are terminated to V

) for

TT

. Intel chipsets will also provide on-die termination, thus eliminating the need to terminate the bus on the motherboard for most GTL+ signals.

Datasheet 21