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AT91SAM9263-EK Evaluation Board
....................................................................................................................
User Guide
6325D–ATARM–26-Aug-09
Table of Contents
Section 1
Section 2
Section 3
Section 4
Section 5
AT91SAM9263-EK Evaluation Board User Guide i
6325D–ATARM–26-Aug-09
Table of Contents (Continued)
Section 6
Section 7
Section 8
ii
6325D–ATARM–26-Aug-09
AT91SAM9263-EK Evaluation Board User Guide
Section 1
Overview
1.1
Scope
The AT91SAM9263-EK evaluation kit enables the evaluation of and code development for applications running on an AT91SAM9263.
This guide focuses on the AT91SAM9263-EK board as an evaluation platform.
1.2
Deliverables
The AT91SAM9263-EK package contains the following items:
an AT91SAM9263-EK board
one A/B-type USB cable
one serial RS232 cable
one RJ45 crossed Ethernet cable
one CD-ROM that allows the user to begin evaluating the AT91 ARM
®
Thumb
®
32-bit microcontroller quickly.
1.3
AT91SAM9263-EK Evaluation Board
The board is equipped with an AT91SAM9263 (324-ball LFBGA package) together with the following:
64 Mbytes of SDRAM memory
4 Mbytes of PSRAM memory on EBI1
256 Mbytes of NANDFlash memory
One NOR Flash memory (footprint only)
One 1.8” Hard disk connectors
One TWI serial memory
One USB device port interface
Two USB Host port interfaces
One RS232 serial communication port
One DBGU serial communication port
One serial CAN 2.0B communication port
One JTAG/ICE debug interface
One Ethernet 100-base TX with three status LEDs
One AC97 Audio DAC
AT91SAM9263-EK Evaluation Board User Guide 1-1
6325D–ATARM–26-Aug-09
Overview
One 3.5" 1/4 VGA TFT LCD Module with TouchScreen and backlight
One ISI connector (camera interface)
One Power LED and two general-purpose LEDs
Two user input push buttons
One Wakeup input push button
One reset push button
One DataFlash
®
/SD/SDIO/MMC card slot
One SD/SDIO/MMC card slot
One Lithium Coin Cell Battery Retainer for 12 mm cell size
1-2
6325D–ATARM–26-Aug-09
AT91SAM9263-EK Evaluation Board User Guide
Section 2
Setting Up the AT91SAM9263-EK Board
2.1
Electrostatic Warning
The AT91SAM9263-EK evaluation board is shipped in protective anti-static packaging. The board must not be subjected to high electrostatic potentials. A grounding strap or similar protective device should be worn when handling the board. Avoid touching the component pins or any other metallic element.
2.2
Requirements
In order to set up the AT91SAM9263-EK evaluation board, the following items are needed:
the AT91SAM9263-EK evaluation board itself.
AC/DC power adapter (12V at 1A), 2.1 mm by 5.5 mm
2.3
Layout
.
AT91SAM9263-EK Evaluation Board User Guide 2-1
6325D–ATARM–26-Aug-09
Setting Up the AT91SAM9263-EK Board
Figure 2-1. AT91SAM9263-EK Layout - Top View
2-2
6325D–ATARM–26-Aug-09
AT91SAM9263-EK Evaluation Board User Guide
Figure 2-2. AT91SAM9263-EK Layout - Bottom View
Setting Up the AT91SAM9263-EK Board
AT91SAM9263-EK Evaluation Board User Guide 2-3
6325D–ATARM–26-Aug-09
Setting Up the AT91SAM9263-EK Board
2.4
Powering Up the Board
The AT91SAM9263-EK requires 12V DC. DC power is supplied to the board via the 2.1 mm by 5.5 mm socket J1. Coaxial plug center positive standard.
2.5
Backup Power Supply
The user has the possibility to plug a battery (3V Lithium Battery CR1225 or equivalent) in order to permanently power the backup part of the device.
2.6
Getting Started
The AT91SAM9263-EK evaluation board is delivered with a CD-ROM that allows the user to begin evaluation of the AT91 ARM Thumb 32-bit microcontroller quickly. Please refer to the AT91 web site, http://www.atmel.com/products/AT91/ , for the most up-to-date information on getting started with the
AT91SAM9263-EK.
2-4
6325D–ATARM–26-Aug-09
AT91SAM9263-EK Evaluation Board User Guide
Setting Up the AT91SAM9263-EK Board
2.7
AT91SAM9263-EK Block Diagram
Figure 2-3. AT91SAM9263-EK Block Diagram
EBI0 SDRAM NANFLASH NORFLASH 1.8" HDD EBI1 PSRAM
RAS CAS SDA10 SDW BA0 BA1 NANDCS RDYBSY
PD2 PD3 PE16 PE17
MMC SD/SDIO
DATAFLASH
CARD READER CARD READER
MMC SD/SDIO L SERIA
EEPROM
PE18 PE19
PE17 PE18 PE19 PE22 PE23
(INTRQ) (IORDY
PD1 PD2 PD3 PD5 PD6 PD7 PD10 PD11 PD13 PD14 PD15 PD17 PD18 PD19 PD21 PD22 PD23 PD25 PD26 PD27 PD29 PD30 PD31
PC5 PC6 PC13 PC14 PC21 PC22
PB6 PB7 PB13 PB14 PB15 PB17 PB18 PB19 PB21 PB22 PB23 PB25 PB26 PB27 PB29 PB30 PB31
PA17 PA18 PA19 PA21 PA22 PA23 PA25 PA26 PA30 PA31
PC4 PC5 AC97CK AC97TX
12VDC ACE
USER'S
INTERF
OUT IN MIC RS232
DDM DDP
PA24 PA23 PA21 PA20 PA19 PA18 CANRX CANTX
USB CAN
EMDC EMDI
10/100 FAST ETHERNET
LCDCC PA30
TERFACE LCD IN TERFACE CAMERA IN
PA17 PA16
AT91SAM9263-EK Evaluation Board User Guide 2-5
6325D–ATARM–26-Aug-09
Section 3
Board Description
3.1
AT91SAM9263 Microcontroller
Incorporates the ARM926EJ-S ™ ARM ® Thumb ® Processor
– DSP Instruction Extensions, Jazelle ® Technology for Java ® Acceleration
– 16 Kbyte Data Cache, 16 Kbyte Instruction Cache, Write Buffer
– 200 MIPS at 180 MHz
– Memory Management Unit
– EmbeddedICE ™ , Debug Communication Channel Support
– Mid-level Implementation Embedded Trace Macrocell ™
Bus Matrix
– Nine 32-bit-layer Matrix, Allowing a Total of 28.8 Gbps of On-chip Bus Bandwidth
– Boot Mode Select Option, Remap Command
Embedded Memories
– One 128 Kbyte Internal ROM, Single-cycle Access at Maximum Bus Matrix Speed
– One 80 Kbyte Internal SRAM, Single-cycle Access at Maximum Processor Bus Matrix Speed
– One 16 Kbyte Internal SRAM, Single-cycle Access at Maximum Bus Matrix Speed
Dual External Bus Interface (EBI0 and EBI1)
– EBI0 Supports SDRAM, Static Memory, ECC-enabled NAND Flash and CompactFlash ®
– EBI1 Supports SDRAM, Static Memory and ECC-enabled NAND Flash
DMA Controller (DMAC)
– Acts as one Bus Matrix Master
– Embeds 2 Unidirectional Channels with Programmable Priority, Address Generation, Channel
Buffering and Control
Twenty Peripheral DMA Controller Channels (PDC)
LCD Controller
– Supports Passive or Active Displays
– Up to 24 bits per Pixel in TFT Mode, Up to 16 bits per Pixel in STN Color Mode
– Up to 16M Colors in TFT Mode, Resolution Up to 2048x2048, Supports Virtual Screen Buffers
2D Graphics Accelerator
– Line Draw, Block Transfer, Polygon Fill, Clipping, Commands Queuing
Image Sensor Interface
– ITU-R BT. 601/656 External Interface, Programmable Frame Capture Rate
– 12-bit Data Interface for Support of High Sensibility Sensors
– SAV and EAV Synchronization, Preview Path with Scaler, YCbCr Format
AT91SAM9263-EK Evaluation Board User Guide 3-1
6325D–ATARM–26-Aug-09
Board Description
USB 2.0 Full Speed (12 Mbits per second) Host Double Port
– Dual On-chip Transceivers
– Integrated FIFOs and Dedicated DMA Channels
USB 2.0 Full Speed (12 Mbits per second) Device Port
– On-chip Transceiver, 2,432-byte Configurable Integrated DPRAM
Ethernet MAC 10/100 Base-T
– Media Independent Interface or Reduced Media Independent Interface
– 28-byte FIFOs and Dedicated DMA Channels for Receive and Transmit
Fully-featured System Controller, including
– Reset Controller, Shutdown Controller
– Twenty 32-bit Battery Backup Registers for a Total of 80 Bytes
– Clock Generator and Power Management Controller
– Advanced Interrupt Controller and Debug Unit
– Periodic Interval Timer, Watchdog Timer and Double Real-time Timer
Reset Controller (RSTC)
– Based on Two Power-on Reset Cells, Reset Source Identification and Reset Output Control
Shutdown Controller (SHDWC)
– Programmable Shutdown Pin Control and Wake-up Circuitry
Clock Generator (CKGR)
– 32768Hz Low-power Oscillator on Battery Backup Power Supply, Providing a Permanent Slow
Clock
– 3 to 20 MHz On-chip Oscillator and Two Up to 240 MHz PLLs
Power Management Controller (PMC)
– Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities
– Four Programmable External Clock Signals
Advanced Interrupt Controller (AIC)
– Individually Maskable, Eight-level Priority, Vectored Interrupt Sources
– Two External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected
Debug Unit (DBGU)
– 2-wire UART and Support for Debug Communication Channel, Programmable ICE Access
Prevention
Periodic Interval Timer (PIT)
– 20-bit Interval Timer plus 12-bit Interval Counter
Watchdog Timer (WDT)
– Key-protected, Programmable Only Once, Windowed 16-bit Counter Running at Slow Clock
Two Real-time Timers (RTT)
– 32-bit Free-running Backup Counter Running at Slow Clock with 16-bit Prescaler
Five 32-bit Parallel Input/Output Controllers (PIOA, PIOB, PIOC, PIOD and PIOE)
– 160 Programmable I/O Lines Multiplexed with Up to Two Peripheral I/Os
– Input Change Interrupt Capability on Each I/O Line
– Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output
One Part 2.0A and Part 2.0B-compliant CAN Controller
3-2
6325D–ATARM–26-Aug-09
AT91SAM9263-EK Evaluation Board User Guide
Board Description
– 16 Fully-programmable Message Object Mailboxes, 16-bit Time Stamp Counter
Two Multimedia Card Interfaces (MCI)
– SDCard/SDIO and MultiMediaCard Compliant
– Automatic Protocol Control and Fast Automatic Data Transfers with PDC
– Two SDCard Slots Support on each Controller
Two Synchronous Serial Controllers (SSC)
– Independent Clock and Frame Sync Signals for Each Receiver and Transmitter
– I²S Analog Interface Support, Time Division Multiplex Support
– High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer
One AC97 Controller (AC97C)
– 6-channel Single AC97 Analog Front End Interface, Slot Assigner
Three Universal Synchronous/Asynchronous Receiver Transmitters (USART)
– Individual Baud Rate Generator, IrDA
®
Infrared Modulation/Demodulation, Manchester
Encoding/Decoding
– Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support
Two Master/Slave Serial Peripheral Interfaces (SPI)
– 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects
– Synchronous Communications at Up to 90Mbits/sec
One Three-channel 16-bit Timer/Counters (TC)
– Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel
– Double PWM Generation, Capture/Waveform Mode, Up/Down Capability
One Four-channel 16-bit PWM Controller (PWMC)
One Two-wire Interface (TWI)
– Master Mode Support, All Two-wire Atmel
®
EEPROMs Supported
IEEE
®
1149.1 JTAG Boundary Scan on All Digital Pins
Required Power Supplies
– 1.08V to 1.32V for VDDCORE and VDDBU
– 3.0V to 3.6V for VDDOSC, VDDPLL and VDDIOP0 (Peripheral I/Os)
– 1.65V to 3.6V for VDDIOP1 (Peripheral I/Os)
– Programmable 1.65V to 1.95V or 3.0V to 3.6V for VDDIOM0/VDDIOM1 (Memory I/Os)
Available in a 324-ball BGA Green Package
AT91SAM9263-EK Evaluation Board User Guide 3-3
6325D–ATARM–26-Aug-09
Board Description
3.2
AT91SAM9263 Block Diagram
Figure 3-1. AT91SAM9263 Block Diagram
HDMB
HDPB
HDMA
HDPA
EMDIO
EMDC
EF100
ETX0-ETX3
ERX0-ERX3
ERXER-ERXDV
ECRS-ECOL
ETXEN-ETXER
LCDCC
LCDDEN
LCDDOTCK
LCDHSYNC
LCDVSYNC
TSYNC
TCLK
TPS0-TPS2
BMS
TPK0-TPK15
LCDD0-LCDD23
ETXCK-ERXCK-EREFCK
RTCK
JTAGSEL
TCK
TMS
TDO
TDI
NTRST
3-4
6325D–ATARM–26-Aug-09
TIOB0-TIOB2
TIOA0-TIOA2
TCLK0-TCLK2
NPCS1
NPCS2
NPCS0
NPCS3
MOSI
SPCK
MISO
CANTX
CANRX
PWM0-PWM3
CK
TWD
TWCK
CDA
CDB DA0-DA3
CTS0-CTS2
RTS0-RTS2
SCK0-SCK2
RDX0-RDX2
DB0-DB3
TXD0-TXD2
ISI_VSYNC
ISI_HSYNC
ISI_PCK
ISI_MCK
ISI_D0-ISI_D11
DDM
DDP
TD0-TD1
TF0-TF1
TK0-TK1
RD0-RD1
RK0-RK1
RF0-RF1
AC97RX
AC97FS
AC97CK
AC97TX
DMARQ0_DMARQ3
AT91SAM9263-EK Evaluation Board User Guide
Board Description
3.3
Memory
16 Kbytes of Internal data cache
16 Kbytes of Internal instruction cache
128 Kbytes of Internal ROM
80 Kbytes of Internal single-cycle access high-speed SRAM
16 Kbytes of Internal single-cycle access high-speed SRAM
8 Mbytes of Atmel NOR Flash (not populated)
64 Mbytes of SDRAM memory
4 Mbytes of PSRAM (EBI1)
256 Mbytes of NANDFlash memory
Atmel TWI serial EEPROM
3.4
Clock Circuitry
16.36766 MHz standard crystal for the embedded oscillator
32.768 kHz standard crystal for the slow clock oscillator
3.5
Reset Circuitry
Internal reset controller with bi-directional reset pin
External reset pushbutton
3.6
Shutdown Controller
Programmable shutdown and Wake-Up
Wake-up push button
3.7
Power Supply Circuitry
For dynamic power consumption, the AT91SAM9263 consumes a maximum of 50 mA on VDDCORE at maximum speed in typical conditions (1.2V, 25°C), processor running full-performance algorithm.
On-board 1.2V high efficiency step-down Charge Pump regulator with shutdown control
On-board 3.3V switching regulator with shutdown control
On-board 5V switching regulator with shutdown control
3.8
Remote Communication
One RS232 serial communication port
One serial CAN 2.0B communication port via 3-position printed circuit terminal block
One USB V2.0 Full-speed Compliant, 12 Mbits per second (UDP)
Two USB Host ports V2.0 Full-speed Compliant, 12 Mbits per second (UHP)
One RMII Ethernet 100-base TX with three status LEDs
AT91SAM9263-EK Evaluation Board User Guide 3-5
6325D–ATARM–26-Aug-09
Board Description
3.9
Audio Stereo Interface
One AC'97 2.3 compliant Codec (20-bit PCM DAC)
One 32-ohm Stereo Headset line-out
One stereo line input
One stereo electret microphone input
One mono 8-ohm amplified speaker
3.10
User Interface
Two user input pushbuttons
Two user green LEDs
One yellow power LED (can be also software controlled)
One 3.5" ¼ VGA display LCD with Touch Panel and white LED backlight
One ISI connector (camera interface)
3.11
Debug Interface
20-pin JTAG/ICE interface connector
One Serial interface (DBGU COM Port) via RS-232 DB9 male socket
3.12
Expansion Slot
One DataFlash/SD/SDIO/MMC card slot
One SD/SDIO/MMC card slot
All unused I/Os of the AT91SAM9263 are routed to peripheral extension connectors (J24 and J25).
This allows the developer to add external hardware components or boards.
3-6
6325D–ATARM–26-Aug-09
AT91SAM9263-EK Evaluation Board User Guide
Board Description
MCI0_DB2
MCI0_DB3
MCI1_CDB
MCI1_DB0
MCI1_DB1
MCI1_DB2
MCI1_DB3
TXD0
RXD0
RTS0
CTS0
SCK0
DMARQ0
MCI0_DA1
MCI0_DA2
MCI0_DA3
MCI1_CK
MCI1_CDA
MCI1_DA0
MCI1_DA1
MCI1_DA2
MCI1_DA3
MCI0_CK
CANTX
CANRX
TCLK2
MCI0_CDB
MCI0_DB0
MCI0_DB1
PA2
PA19
PA20
PA21
PA22
PA23
PA24
PA25
PA26
PA27
PA28
PA29
PA30
PA31
PA11
PA12
PA13
PA14
PA15
PA16
PA17
PA18
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
3.13
PIO Usage
Table 3-1. PIO Controller A
I/O Line Peripheral A Peripheral B
PA0
PA1
MCI0_DA0
MCI0_CDA
SPI0_MISO
PCK0
IRQ0
IRQ1
EBI1_D16
EBI1_D17
EBI1_D18
EBI1_D19
EBI1_D20
EBI1_D21
EBI1_D22
EBI1_D23
EBI1_D24
EBI1_D25
EBI1_D26
EBI1_D27
EBI1_D28
EBI1_D29
EBI1_D30
EBI_D31
SPI0_MOSI
SPI0_SPCK
SPI0_NPCS1
SPI0_NPCS2
SPI0_NPCS0
PCK2
Peripheral Usage
SD/MMC/DATAFLASH SOCKET (J9) & TOUCH screen
CONTROLLER
SD/MMC/DATAFLASH SOCKET (J9) & TOUCH screen
CONTROLLER
SD/MMC/DATAFLASH SOCKET (J9) & TOUCH screen
CONTROLLER
SD/MMC/DATAFLASH SOCKET (J9)
SD/MMC/DATAFLASH SOCKET (J9)
SD/MMC/DATAFLASH SOCKET (J9)
SD/MMC SOCKET (J10)
SD/MMC SOCKET (J10)
SD/MMC SOCKET (J10)
SD/MMC SOCKET (J10)
SD/MMC SOCKET (J10)
SD/MMC SOCKET (J10)
SD/MMC/DATAFLASH SOCKET (J9)
CAN BUS INTERFACE (J17)
CAN BUS INTERFACE (J17)
TOUCH SCREEN CONTROLLER (MN19)
IMAGE SENSORS CONNECTORS (J23)
IMAGE SENSORS CONNECTORS (J23)
CAN INTERFACE (RXEN)
CAN INTERFACE (RS)
USB HOST B POWER MONITOR (MN17)
USB HOST B POWER CONTROL (MN17)
NANDFLASH (MN12B)
USB HOST B POWER MONITOR (MN17)
USB HOST B POWER CONTROL (MN17)
USB DEVICE INTERFACE
RS232 COM PORT (J15)
RS232 COM PORT (J15)
RS232 COM PORT (J15)
RS232 COM PORT (J15)
LCD PANEL (Power Control In)
TOUCH SCREEN CONTROLLER (MN19)
MCI0_DA0 or SPI0_MISO
MCI0_CDA or SPI0_MOSI
SPI0_SPCK
MCI1_CK
MCI1_CDA
MCI1_DA0
MCI1_DA1
MCI1_DA2
MCI1_DA3
MCI0_CK
CANTX
CANRX
IRQ1
PA16 as CTRL1
PA17 as CTRL2
PA18 as RXEN
PA19 as RS
PA20 as FLGB
PA21 as ENB
PA22 as RDY/BSY
PA23 as FLGA
PA24 as ENA
PA25 as USB_CNX
TXD0
RXD0
RTS0
CTS0
PA30 as PCI
PA31 as BUSY
Powered by
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOM1
VDDIOM1
VDDIOM1
VDDIOM1
VDDIOM1
VDDIOM1
VDDIOM1
VDDIOM1
VDDIOM1
VDDIOM1
VDDIOM1
VDDIOM1
VDDIOM1
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOM1
VDDIOM1
VDDIOM1
AT91SAM9263-EK Evaluation Board User Guide 3-7
6325D–ATARM–26-Aug-09
Board Description
PB23
PB24
PB25
PB26
PB27
PB28
PB29
PB30
PB31
PB15
PB16
PB17
PB18
PB19
PB20
PB21
PB22
PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14
I/O Line
PB0
PB1
PB2
PB3
PB4
PB5
PB6
Table 3-2. PIO Controller B
Peripheral A
AC97FS
AC97CK
AC97TX
AC97RX
TWD
TWCK
TF1
TK1
TD1
RD1
RK1
RF1
SPI1_MISO
SPI1_MOSI
SPI1_SPCK
SPI1_NPCS0
SPI1_NPCS1
SPI1_NPCS2
SPI1_NPCS3
Peripheral B
TF0
TK0
TD0
RD0
RK0
RF0
DMARQ1
PWM0
PWM1
LCDCC
PCK1
SPI0_NPCS3
PCK1
TIOA2
TIOB2
DMARQ3
PWM2
TCLK0
PWM3
Peripheral Usage
AC97 CODEC (MN12)
AC97 CODEC (MN12)
AC97 CODEC (MN12)
AC97 CODEC (MN12)
TWI EEPROM (MN11)
TWI EEPROM (MN11)
POWER LED CONTROL (DS3)
USER'S LED1 CONTROL (DS1)
LCD PANEL (backlight control)
AC97 CODEC (MN12) Optional clock source
TOUCH SCREEN CONTROLLER (MN19)
AC97FS
AC97CK
AC97TX
AC97RX
TWD / SDA
TWCK / SCL
PB7 or PWM0
PB8 or PWM1
LCDCC
PCK1
SPI0_NPCS3
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
Powered by
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
3-8
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AT91SAM9263-EK Evaluation Board User Guide
Board Description
Table 3-3. PIO Controller C
Peripheral B
PC23
PC24
PC25
PC26
PC27
PC28
PC29
PC30
PC31
PC15
PC16
PC17
PC18
PC19
PC20
PC21
PC22
PC7
PC8
PC9
PC10
PC11
PC12
PC13
PC14
I/O Line
PC0
PC1
PC2
PC3
PC4
PC5
PC6
LCDD19
LCDD20
LCDD21
LCDD22
LCDD23
PWM0
PCK0
DRXD
DTXD
LCDD11
LCDD12
LCDD13
LCDD14
LCDD15
LCDD16
LCDD17
LCDD18
Peripheral A
LCDVSYNC
LCDHSYNC
LCDDOTCK
LCDDEN
LCDD0
LCDD1
LCDD2
LCDD3
LCDD4
LCDD5
LCDD6
LCDD7
LCDD8
LCDD9
LCDD10
LCDD23
ETX2
ETX3
ERX2
ERX3
ETXER
ERXDV
ECOL
ERXCK
TCLK1
PWM2
LCDD12
LCDD13
LCDD14
LCDD15
LCDD19
LCDD20
LCDD21
LCDD22
PWM1
LCDD3
LCDD4
LCDD5
LCDD6
LCDD7
LCDD10
LCDD11
Peripheral Usage
LCD PANEL
LCD PANEL
LCD PANEL
USER'S PUSH BUTTON (BP2)
USER'S PUSH BUTTON (BP1)
LCD PANEL
LCD PANEL
LCD PANEL
LCD PANEL
LCD PANEL
LCD PANEL
LCD PANEL
LCD PANEL
LCD PANEL
LCD PANEL
LCD PANEL
LCD PANEL
LCD PANEL
LCDHSYNC
LCDDOTCK
LCDDEN
PC4 as RIGHT CLICK
PC5 as LEFT CLICK
LCDD2
LCDD3
LCDD4
LCDD5
LCDD6
LCDD7
LCDD13
LCDD10
LCDD11
LCDD12
LCDD21
LCDD14
LCDD15
LCD PANEL
LCD PANEL
LCD PANEL
ETHERNET RMII (MN18)
LCD PANEL
LCD PANEL
USER'S LED2 CONTROL (DS2)
SERIAL DEBUG PORT (J14)
SERIAL DEBUG PORT (J14)
LCDD18
LCDD19
LCDD20
ERXDV
LCDD22
LCDD23
PC29 or PWM2
DRXD
DTXD
RED
RED
RED
RED
RED
RED
GREEN
GREEN
GREEN
GREEN
BLUE
GREEN
GREEN
BLUE
BLUE
BLUE
BLUE
BLUE
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
Powered by
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
AT91SAM9263-EK Evaluation Board User Guide 3-9
6325D–ATARM–26-Aug-09
Board Description
PD23
PD24
PD25
PD26
PD27
PD28
PD29
PD30
PD31
PD15
PD16
PD17
PD18
PD19
PD20
PD21
PD22
PD7
PD8
PD9
PD10
PD11
PD12
PD13
PD14
I/O Line
PD0
PD1
PD2
PD3
PD4
PD5
PD6
Table 3-4. PIO Controller D
Peripheral A
TXD1
RXD1
TXD2
RXD2
FIQ
EBI0_NWAIT
EBI0_NCS4/CFCS0
EBI0_NCS5/CFCS1
EBI0_CFCE1
EBI0_CFCE2
EBI0_NCS2
EBI0_A23
EBI0_A24
EBI0_A25_CFRNW
EBI0_NCS3/NANDCS
EBI0_D16
EBI0_D17
EBI0_D18
EBI0_D19
EBI0_D20
EBI0_D21
EBI0_D22
EBI0_D23
EBI0_D24
EBI0_D25
EBI0_D26
EBI0_D27
EBI0_D28
EBI0_D29
EBI0_D30
EBI0_D31
TPK7
TPK8
TPK9
TPK10
TPK11
TPK12
TPK13
TPK14
TPK15
TPS2
TPK0
TPK1
TPK2
TPK3
TPK4
TPK5
TPK6
Peripheral B
SPI0_NPCS2
SPI0_NPCS3
SPI1_NPCS2
SPI1_NPCS3
DMARQ2
RTS2
CTS2
RTS1
CTS1
SCK2
SCK1
TSYNC
TCLK
TPS0
TPS1
Peripheral Usage
HDD CONNECTORS (J8)
HDD CONNECTORS (J8)
HDD CONNECTORS (J8)
HDD CONNECTORS (J8)
NANDFLASH (MN12B)
EBI0 SDRAM DATA BUS
EBI0 SDRAM DATA BUS
EBI0 SDRAM DATA BUS
EBI0 SDRAM DATA BUS
EBI0 SDRAM DATA BUS
EBI0 SDRAM DATA BUS
EBI0 SDRAM DATA BUS
EBI0 SDRAM DATA BUS
EBI0 SDRAM DATA BUS
EBI0 SDRAM DATA BUS
EBI0 SDRAM DATA BUS
EBI0 SDRAM DATA BUS
EBI0 SDRAM DATA BUS
EBI0 SDRAM DATA BUS
EBI0 SDRAM DATA BUS
EBI0 SDRAM DATA BUS
PD2 as IRQ
PD3 as IOREADY
EBI0_CFCE1
EBI0_CFCE2
EBI0_NCS3/NANDCS
D16
D17
D18
D19
D20
D21
D22
D27
D28
D29
D30
D31
D23
D24
D25
D26
VDDIOM0
VDDIOM0
VDDIOM0
VDDIOM0
VDDIOM0
VDDIOM0
VDDIOM0
VDDIOM0
VDDIOM0
VDDIOM0
VDDIOM0
VDDIOM0
VDDIOM0
VDDIOM0
VDDIOM0
VDDIOM0
VDDIOM0
Powered by
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOM0
VDDIOM0
VDDIOM0
VDDIOM0
VDDIOM0
VDDIOM0
VDDIOM0
VDDIOM0
VDDIOM0
VDDIOM0
3-10
6325D–ATARM–26-Aug-09
AT91SAM9263-EK Evaluation Board User Guide
Board Description
PE20
PE21
PE22
PE23
PE24
PE25
PE26
PE27
PE28
PE29
PE30
PE31
PE7
PE8
PE9
PE10
PE11
PE12
PE13
PE14
I/O Line
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE15
PE16
PE17
PE18
PE19
Table 3-5. PIO Controller E
Peripheral A
ISI_D0
ISI_D1
ISI_D2
ISI_D3
ISI_D4
ISI_D5
ISI_D6
ISI_D7
ISI_PCK
ISI_HSYNC
ISI_VSYNC
ISI_MCK
Peripheral B
TIOA1
TIOB1
PWM3
PCK3
ISI_D8
ISI_D9
ISI_D10
ISI_D11
TIOA0
TIOB0
ETXCK
ECRS
ETX0
ETX1
ERX0
ERX1
ERXER
ETXEN
EMDC
EMDIO
EF100
EBI1_NWAIT
EBI1_NANDWE
EBI1_NCS2/NANDCS
EB1_NANDOE
EBI1_NWR3/NBS3
EBI1_NCS1/SDCS
EBI1_SDCKE
EBI1_RAS
EBI1_CAS
EBI1_SDWE
EBI1_SDA10
Peripheral Usage
IMAGE SENSORS CONNECTORS (J23)
IMAGE SENSORS CONNECTORS (J23)
IMAGE SENSORS CONNECTORS (J23)
IMAGE SENSORS CONNECTORS (J23)
IMAGE SENSORS CONNECTORS (J23)
IMAGE SENSORS CONNECTORS (J23)
IMAGE SENSORS CONNECTORS (J23)
IMAGE SENSORS CONNECTORS (J23)
IMAGE SENSORS CONNECTORS (J23)
IMAGE SENSORS CONNECTORS (J23)
IMAGE SENSORS CONNECTORS (J23)
IMAGE SENSORS CONNECTORS (J23)
IMAGE SENSORS CONNECTORS (J23)
IMAGE SENSORS CONNECTORS (J23)
IMAGE SENSORS CONNECTORS (J23)
IMAGE SENSORS CONNECTORS (J23)
SD/MMC/DATAFLASH SOCKET (J9)
SD/MMC/DATAFLASH SOCKET (J9)
SD/MMC SOCKET (J10)
SD/MMC SOCKET (J10)
SD/MMC/DATAFLASH SOCKET (J9)
ETHERNET RMII (MN18)
ISI_D0
ISI_D1
ISI_D2
ISI_D3
ISI_D4
ISI_D5
ISI_D6
ISI_D7
ISI_PCK
ISI_HSYNC
ISI_VSYNC
ISI_MCK
ISI_D8
ISI_D9
ISI_D10
ISI_D11
PE16 as CD (Card Detect)
PE17 as WP (Write Protect)
PE18 as CD (Card Detect)
PE19 as WP (Write Protect)
PE20 as CKSEL (Clock
Select)
ETXCK
Powered by
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOM1
ETHERNET RMII (MN18)
ETHERNET RMII (MN18)
ETHERNET RMII (MN18)
ETHERNET RMII (MN18)
ETHERNET RMII (MN18)
ETHERNET RMII (MN18)
ETHERNET RMII (MN18)
ETHERNET RMII (MN18)
ETX0
ETX1
ERX0
ERX1
ERXER
ETXEN
EMDC
EMDIO
PE31 as IRQ
VDDIOM1
VDDIOM1
VDDIOM1
VDDIOM1
VDDIOM1
VDDIOM1
VDDIOM1
VDDIOM1
VDDIOM1
VDDIOM1
VDDIOM1
AT91SAM9263-EK Evaluation Board User Guide 3-11
6325D–ATARM–26-Aug-09
Section 4
Configuration
4.1
Configuration Jumpers and Straps
Table 4-1. Configuration Jumpers and Straps
Designation
J2
J4-1
J4-2
J5-1
J5-2
J5-3
J5-4
J5.5
Default Setting
Closed
Closed
Closed
Closed
Closed
Closed
Closed
Closed
Feature
Forces power on. To use the software shutdown control, J2 must be opened and the battery backup inserted in its socket.
VDDBU jumper
J5-6
Enables Boot on the internal ROM
Enables Boot on the NCS0
S3
R17
R18
R13
R15
J16
J21
S1
S2
Opened
Closed
Closed
Closed
Opened
Opened
Opened
IN
IN
IN
IN
Enables 120 ohms CAN bus resistance termination
Enables Ethernet Auto MDIX control
Selects ICE mode. See
Disables NAND FLASH write protect
Disables 5V power supply on J24, J25 expansion connectors
Enables the ICE NTRST input
Enables the ICE NRST input
Enables the use of the Y1 crystal. If an external clock has to be used,
R13 and R15 must be unsoldered and R16/J16 fitted.
R30
R45
R46
R75
R79
R84
IN
IN
IN
IN
IN
IN
Enables the use of the MN7 SDRAM device. Needs to be removed when ETM is used.
Enables the use of the SERIAL EEPROM SCL (PB5)
Enables the use of the SERIAL EEPROM SDA (PB4)
Enables the use of the DBGU TXD signal (PC31)
Enables the use of the DBGU RXD signal (PC30)
Enables the use of the USB CNX detection (PA25)
AT91SAM9263-EK Evaluation Board User Guide 4-1
6325D–ATARM–26-Aug-09
Configuration
Table 4-1. Configuration Jumpers and Straps
Designation
R76
R78
Default Setting
IN
IN
Feature
Enables the use of the RS232 COM PORT TXD signal (PA26)
Enables the use of the RS232 COM PORT RTS signal (PA28)
R126
R127
R128
TP67
TP68
TP69
TP70
TP71
TP72
TP73
TP74
R80
R82
R87
R89
R91
R93
R112
N.A
N.A
N.A
N.A
N.A
N.A
N.A
N.A
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
Enables the use of the RS232 COM PORT RXD signal (PA27)
Enables the use of the RS232 COM PORT CTS signal (PA29)
Enables the use of the CAN BUS driver RS control signal (PA26)
Enables the use of the CAN BUS driver CANTXRT RTS signal (PA28)
Enables the use of the RS232 COM PORT RXD signal (PA27)
Enables the use of the RS232 COM PORT CTS signal (PA29)
Enables the use of interrupt ETHERNET PHY (PE31)
Enables the use of TOUCH SCREEN CONTROLLER
(PB11_SPI0_NPCS3)
Enables the use of TOUCH SCREEN CONTROLLER BUSY signal
(PA31)
Enables the use of TOUCH SCREEN CONTROLLER PENIRQ
(PA15_IRQ1)
GND Test point
GND Test point
GND Test point
GND Test point
0 to 3.3V analog user's input
0 to 3.3V analog user's input
AGND of TP71
AGND of TP72
Note: 1. These jumpers are provided for power consumption measurement use. By default, they are closed. To use this feature, the user has to open the strap and insert an ammeter.
2. AT91SAM9263 ETM signals [TPK0 - TPK15] are multiplexed with EBI0 signals [EBI0_D16 - EBI0_D31].
AT91SAM9263-EK EBI0 signals [EBI0_D16 - EBI0_D31] are connected to an SDRAM device
(part MN7).
Having this SDRAM device enabled adds capacitance to the data line [EBI0_D16 - EBI0_D31], which leads to ETM data corruption.
You need to remove the resistor R30 to release the EBI0_NCS1_SDCS signal and put the SDRAM
I/Os [EBI0_D16 - EBI0_D31] in High-Z. Having these signals in High-Z removes the added capacitance; the ETM signals are no longer corrupted.
4-2
6325D–ATARM–26-Aug-09
AT91SAM9263-EK Evaluation Board User Guide
5.1
Schematics
This section contains the following schematics:
Power Supply
AT91SAM9263
EBI0 Memory
EBI1 Memory
Serial Memory
Audio AC97
Serial Interfaces
Ethernet
LCD and ISI
Expansion
Section 5
Schematics
AT91SAM9263-EK Evaluation Board User Guide 5-1
6325D–ATARM–26-Aug-09
D
C
B
A
8
8
7
POWER SUPPLY
VDDBU
POWERLED
SHDN
USERLED1
USERLED2
RIGHTCLIC
LEFTCLIC
01 - POWER SUPPLY
AC97
SYNC
BITCLK
SDATA_OUT
AUDIO
SDATA_IN
EXT_CLK
RST#
06 - AUDIO
SERIAL INTERFACES
DBGU
COM0
DTXD
DRXD
TXD
RXD
RTS
CTS
DEVICE
USBCNX
DDM
DDP
HOST A
HOST B
HDMA
HDPA
ENA
FLGA
HDMB
HDPB
ENB
FLGB
07 - COMMUNICATION
CANRS
CANRXEN
CANRX
CANTX
RMII ETHERNET
TX_CLK
TXD1
TXD0
TX_EN
RXD1
RXD0
RX_DV
RX_ER
MDC
MDIO
MDINTR
NRST
08 - ETHERNET
LCD & CAMERA INTERFACE
R[0..5]
G[0..5]
B[0..5]
3.5" QVGA
HSYNC
DCLK
DTMG
VCTRL
PCI
TOUCH SCREEN
CONTROLLER
MOSI
MISO
SPCK
NPCS
IRQ
BUSY
RFTS
ISI_D[0..11]
ISI_MCK
ISI_VSYNC
ISI_HSYNC
ISI_PCK
ISI
VDDISI
SDA
SCL
CTRL2
CTRL1
09 - LCD & CAMERA INTERFACE
PWM0
PWM1
PWM2
PC4
PC5
AC97FS
AC97CK
AC97TX
AC97RX
PCK1
NRST
DTXD
DRXD
TXD0
RXD0
RTS0
CTS0
PA25
PA24
PA23
PA21
PA20
PA19
PA18
CANRX
CANTX
ETXCK
ETX1
ETX0
ETXEN
ERX1
ERX0
ERXDV
ERXER
EMDC
EMDIO
PE31
NRST
LCDD[2..7]
LCDD[10..15]
LCDD[18..23]
LCDHSYNC
LCDDOTCK
LCDDEN
LCDCC
PA30
SPI0_MOSI
SPI0_MISO
SPI0_SPCK
SPI0_NPCS3
IRQ1
PA31
ISI_D[0..11]
ISI_MCK
ISI_VSYNC
ISI_HSYNC
ISI_PCK
VDDISI
TWD
TWCK
PA17
PA16
7
6
DDM
DDP
HDMA
HDPA
HDMB
HDPB
EXPANSION CONNECTORS
PA[0..31]
PB[0..31]
PC[0..31]
PD[0..31]
PE[0..31]
RFTS
CLK16M
SIGI
SIGQ
10 - EXPANSION CONNECTORS
PA[0..31]
PB[0..31]
PC[0..31]
PD[0..31]
PE[0..31]
PPS
CK16M
SIGI
SIGQ
02 - MICROCONTROLLER
PIO USAGE
PA[0..31]
SPI0_MISO
SPI0_MOSI
PA0
PA1
6
VDDISI
5
AT91SAM9263_BGA324
VDDBU
SHDN
VDDISI
PA[0..31]
PB[0..31]
PC[0..31]
PD[0..31]
PE[0..31]
PA[0..31]
PB[0..31]
PC[0..31]
PD[0..31]
PE[0..31]
4
EBI0_D[0..31]
EBI0_A[0..22]
EBI0_RAS
EBI0_CAS
EBI0_SDA10
EBI0_SDWE
EBI0_NCS1/SDCS
EBI0_SDCK
EBI0_SDCKE
EBI0_D[0..31]
EBI0_A[0..22]
EBI0_NANDOE
EBI0_NANDWE
EBI0_NCS0
EBI0_NWE/NWR0/CFWE
EBI0_NRD/CFOE
NRST
NRST
EBI0_NBS1/NW1/CFIOR
EBI0_NBS3/NW3/CFIOW
EBI0_NBS1
EBI0_NBS3
EBI1_D[0..15]
EBI1_A[0..21]
EBI1_NCS0
EBI1_NWE/NWR0/CFWE
EBI1_NRD/CFOE
EBI1_NBS1/NW1/CFIOR
EBI1_SDCK
EBI1_D[0..15]
EBI1_A[0..21]
3
PA0 MCI0_DA0
PA1 MCI0_CDA
PA2 SPI0_SPCK
PA3 MCI0_DA1
PA4 MCI0_DA2
PA5 MCI0_DA3
PA6 MCI1_CK
PA7 MCI1_CDA
PA8 MCI1_DA0
PA9 MCI1_DA1
PA10 MCI1_DA2
PA11 MCI1_DA3
PA12 MCI0_CK
PA13 CANTX
PA14 CANRX
PA15 IRQ1
PA16
PA17
PA18
PA19
PA20
PA21
PA22
PA23
PA24
(CTRL1)
(CTRL2)
(CANRXEN)
(CANRS)
(FLGB)
(ENB)
(RDYBSY)
(FLGA)
(ENA)
PA25 (USBCNX)
PA26 TXD0
PA27 RXD0
PA28 RTS0
PA29 CTS0
PA30
PA31
(PCI)
(BUSY)
PB[0..31] PC[0..31]
PB15
PB16
PB17
PB18
PB19
PB20
PB21
PB22
PB23
PB24
PB25
PB26
PB27
PB28
PB29
PB30
PB31
PB0 AC97FS
PB1 AC97CK
PB2 AC97TX
PB3 AC97RX
PB4 TWD
PB5 TWCK
PB6
PB7 PWM0
PB8 PWM1
PB9 LCDCC
PB10 PCK1
PB11 SPI0_NPCS3
PB12
PB13
PB14
PC0
PC1 LCDHSYNC
PC2 LCDDOTCK
PC3 LCDDEN
PC4
PC5
(RIGHTCLIC)
(LEFTCLIC)
PC6 LCDD2
PC7 LCDD3
PC8 LCDD4
PC9 LCDD5
PC10 LCDD6
PC11 LCDD7
PC12 LCDD13
PC13
PC14 LCDD10
PC15 LCDD11
PC16 LCDD12
PC17 LCDD21
PC18 LCDD14
PC19 LCDD15
PC20
PC21
PC22 LCDD18
PC23 LCDD19
PC24 LCDD20
PC25 ERXDV
PC26 LCDD22
PC27 LCDD23
PC28
PC29 PWM2
PC30 DRXD
PC31 DTXD
PD[0..31]
PD15
PD16
PD17
PD18
PD19
PD20
PD21
PD22
PD23
PD24
PD25
PD26
PD27
PD28
PD29
PD30
PD31
PD0
PD1
PD2
PD3
PD4
PD5
PD6
(INTRQ)
(IORDY)
PD7
PD8 EBI0_CFCE1
PD9 EBI0_CFCE2
PD10
PD11
PD12
PD13
PD14
(NANDCS)
PE[0..31]
PE0 ISI_D0
PE1 ISI_D1
PE2 ISI_D2
PE3 ISI_D3
PE4 ISI_D4
PE5 ISI_D5
PE6 ISI_D6
PE7 ISI_D7
PE8 ISI_PCK
PE9 ISI_HSYNC
PE10 ISI_VSYNC
PE11 ISI_MCK
PE12 ISI_D8
PE13 ISI_D9
PE14 ISI_D10
PE15 ISI_D11
PE16
PE17
PE18
PE19
PE20
(MCI0_CD)
(MCI0_WP)
(MCI1_CD)
(MCI1_WP)
(CKSEL)
PE21 ETXCK
PE22
PE23 ETX0
PE24 ETX1
PE25 ERX0
PE26 ERX1
PE27 ERXER
PE28 ETXEN
PE29 EMDC
PE30 EMDIO
PE31 (MDINTR)
5 4 3
2
EBI0_A0
EBI0_NBS1
EBI0_A1
EBI0_NBS3
EBI0_A16
EBI0_A17
EBI0_A22
EBI0_A21
PD15
PA22
EBI0 MEMORY
D[0..31]
A[0..22]
RAS
CAS
SDA10
SDWE
SDCS
SDCK
SDCKE
NBS0
NBS1
NBS2
NBS3
BA0
BA1
CLE
ALE
NANDOE
NANDWE
NANDCS
RDYBSY
NCS
NWE
NRD
NRST
RESET-
EBI0_CFCE1
EBI0_CFCE2
PD2
PD3
INTRQ
IORDY
03 - EBI0 MEMORY
EBI1_A[1..21]
EBI1 MEMORY
D[0..15]
A[1..21]
NCS
NWR
NOE
EBI1_A0
CS0-
CS1-
DIOR-
DIOW-
LB
UB
04 - EBI1 MEMORY
PE16
PE17
MCI & TWI
MCI0_CD
MCI0_WP
MCI0_DA0
MCI0_DA1
MCI0_DA2
MCI0_DA3
MCI0_CDA
MCI0_CK
SPI0_SPCK
PE20
PE18
PE19
MCI0_DA0
MCI0_DA1
MCI0_DA2
MCI0_DA3
MCI0_CDA
MCI0_CK
SPI0_SPCK
CKSEL
CARD
READER
MCI1_DA0
MCI1_DA1
MCI1_DA2
MCI1_DA3
MCI1_CDA
MCI1_CK
MCI1_CD
MCI1_WP
MCI1_DA0
MCI1_DA1
MCI1_DA2
MCI1_DA3
MCI1_CDA
CARD
READER
MCI1_CK
TWCK
TWD
SCL
SDA
05 - MCI & TWI
1
DIAGRAM
2
A
REV
INIT EDIT
MODIF.
SCALE 1/1
JPG
DES.
10/10/06
DATE VER.
REV.
A
1
DATE
SHEET
1
11
A
D
C
B
8 7 6 5
D
1
2
CR2
STPS2L30A
C2
2.2µF
Q1
1
BSH103
2
3
4
11
3
7
10
15
VIN
VIN
SHDN
NC
NC
NC
C
VDDBU
SHDN
C14
15PF
Q3
BSH103
1
3
2
C8
2.2µF
Q2
1
BSH103
2
3
4
11
3
7
10
15
VIN
VIN
SHDN
NC
NC
NC
FORCE
POWER
ON
B
A
C1
180NF
CR1
BAT20J
5V
SW
SW
FB
6
5
12
L1
2.2µH
CR3
STPS2L30A
C4
2.2NF
C3
10µF
C7
180NF
CR4
BAT20J
3V3
SW
SW
FB
6
5
12
L2
2.2µH
CR5
STPS2L30A
C9
10µF
C12
2.2µF
C13
2.2NF
C5
1µF
C6
1µF
8
5
C1M
VIN
6 3 4
C1P C2M C2P
VOUT
7
C10
22µF
R1
100K
1V2
C11
10PF
1
EN GND
9
FB
10
PG
2
R2
200K
R5
120R
3V3
R8
470K
POWER LED
DS3
YELLOW
3
Q4
IRLML2402
2
1
R9 0R
POWERLED
USER INTERFACE
3V3
RIGHT CLICK
LEFT CLICK
BP1
USERLED2
USERLED1
RIGHTCLIC
LEFTCLIC
8 7 6 5 4
4 3 2 1
3
ADHESIVE FEET GND TEST POINT
POWER SUPPLY
2
A
REV
INIT EDIT
MODIF.
SCALE 1/1
JPG
DES.
10/10/06
DATE VER.
REV.
A
1
DATE
SHEET
2
11
A
B
D
C
D
C
A
PA[0..31]
PC[0..31]
B
PE[0..31]
NRST
8
3V3
PE12
PE13
PE14
PE15
PE16
PE17
PE18
PE19
PE20
PE21
PE22
PE23
PE24
PE25
PE26
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PE8
PE9
PE10
PE11
PE27
PE28
PE29
PE30
PE31
8
A13
D11
A12
F11
B11
C11
A11
E10
D14
B13
F12
A14
D12
B12
E11
C12
C14
B14
D15
E13
A15
F13
C13
E12
E16
D17
D16
C15
E14
B16
D13
B15
PC12
PC13
PC14
PC15
PC16
PC17
PC18
PC19
PC20
PC21
PC22
PC23
PC24
PC25
PC26
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
PC27
PC28
PC29
PC30
PC31
PA16
PA17
PA18
PA19
PA20
PA21
PA22
PA23
PA24
PA25
PA26
PA27
PA28
PA29
PA30
PA31
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
U5
V4
R5
T6
U4
R4
T5
V3
U2
T4
V2
U3
P3
U1
R3
T3
M18
L15
L17
L18
L16
L13
K14
K15
N16
N15
P15
P14
M15
M17
M14
M16
R19
1K
V14
T14
R14
U14
P16
T15
R16
T16
N6
N5
M1
N3
P6
V13
U13
T13
M7
L3
L1
M4
M6
M5
M2
M3
L2
L5
K1
L4
K3
K4
L6
L7
PA0/MCI0_DA0/SPI0_MISO
PA1/MCI0_CDA/SPI0_MOSI
PA2/SPI0_SPCK
PA3/MCI0_DA1/SPI0_NPCS1
PA4/MCI0_DA2/SPI0_NPCS2
PA5/MCI0_DA3/SPI0_NPCS0
PA6/MCI1_CK/PCK2
PA7/MCI1_CDA
PA8/MCI1_DA0
PA9/MCI1_DA1
PA10/MCI1_DA2
PA11/MCI1_DA3
PA12/MCI0_CK
PA13/CANTX/PCK0
PA14/CANRX/IRQ0
PA15/TCLK2/IRQ1
PA16/MCI0_CDB/EBI1_D16
PA17/MCI0_DB0/EBI1_D17
PA18/MCI0_DB1/EBI1_D18
PA19/MCI0_DB2/EBI1_D19
PA20/MCI0_DB3/EBI1_D20
PA21/MCI1_CDB/EBI1_D21
PA22/MCI1_DB0/EBI1_D22
PA23/MCI1_DB1/EBI1_D23
PA24/MCI1_DB2/EBI1_D24
PA25/MCI1_DB3/EBI1_D25
PA26/TXD0/EBI1_D26
PA27/RXD0/EBI1_D27
PA28/RTS0/EBI1_D28
PA29/CTS0/EBI1_D29
PA30/SCK0/EBI1_D30
PA31/DMARQ0/EBI1_D31
PC0/LCDVSYNC
PC1/LCDHSYNC
PC2/LCDDOTCK
PC3/LCDDEN/PWM1
PC4/LCDD0/LCDD3
PC5/LCDD1/LCDD4
PC6/LCDD2/LCDD5
PC7/LCDD3/LCDD6
PC8/LCDD4/LCDD7
PC9/LCDD5/LCDD10
PC10/LCDD6/LCDD11
PC11/LCDD7/LCDD12
PC12/LCDD8/LCDD13
PC13/LCDD9/LCDD14
PC14/LCDD10/LCDD15
PC15/LCDD11/LCDD19
PC16/LCDD12/LCDD20
PC17/LCDD13/LCDD21
PC18/LCDD14/LCDD22
PC19/LCDD15/LCDD23
PC20/LCDD16/E_TX2
PC21/LCDD17/E_TX3
PC22/LCDD18/E_RX2
PC23/LCDD19/E_RX3
PC24/LCDD20/E_TXER
PC25/LCDD21/E_RXDV
PC26/LCDD22/E_COL
PC27/LCDD23/E_RXCK
PC28/PWM0/TCLK1
PC29/PCK0/PWM2
PC30/DRXD
PC31/DTXD
7
PE0/ISI_D0/DRFIN0
PE1/ISI_D1/DRFIN1
PE2/ISI_D2/DRFIN2
PE3/ISI_D3/DRFIN3
PE4/ISI_D4/DRFIN4
PE5/ISI_D5/DRFIN5
PE6/ISI_D6/DRFIN6
PE7/ISI_D7/DRFIN7
PE8/ISI_PCK/TIOA1
PE9/ISI_HSYNC/TIOB1
PE10/ISI_VSYNC/PWM3
PE11/ISI_MCK/PCK3
PE12/KBDR0/ISI_D8
PE13/KBDR1/ISI_D9
PE14/KBDR2/ISI_D10
PE15/KBDR3/ISI_D11
PE16/KBDPWR
PE17/KBDC0
PE18/KBDC1/TIOA0
PE19/KBDC2/TIOB0
PE20/KBDC3/EBI1_NWAIT
PE21/E_TXCK/EBI1_NANDWE
PE22/E_CRS/EBI1_NCS2/NANDCS
PE23/E_TX0/EBI1_NANDOE
PE24/E_TX1/EBI1_NWR3/NBS3/CFIOW
PE25/E_RX0/EBI1_NCS1/SDCS
PE26/E_RX1
PE27/E_RXER/EBI1_SDCKE
PE28/E_TXEN/EBI1_RAS
PE29/E_MDC/EBI1_CAS
PE30/E_MDIO/EBI1_SDWE
PE31/E_F100/EBI1_SDA10
PB0/AC97FS/TF0
PB1/AC97CK/TK0
PB2/AC97TX/TD0
BMS_PB3/AC97RX/RD0
PB4/TWD/RK0
PB5/TWCK/RF0
PB6/TF1/DMARQ1
PB7/TK1/PWM0
PB8/TD1/PWM1
PB9/RD1/LCDCC
PB10/RK1/PCK1
PB11/RF1/SPI0_NPCS3
PB12/SPI1_MISO
PB13/SPI1_MOSI
PB14/SPI1_SPCK
PB15/SPI1_NPCS0
PB16/SPI1_NPCS1/PCK1
PB17/SPI1_NPCS2/TIOA2
PB18/SPI1_NPCS3/TIOB2
PB19/LVRST
PB20/CKSYNC
PB21/PCTL0
PB22/CKDAT
PB23/GPSSYNC
PB24/OTG_SE0_VM/DMARQ3
PB25/OTG_DAT_VP
PB26/OTGTP_OE
PB27/OTGRCV/PWM2
PB28/OTGSUSPEND/TCLK0
PB29/OTGINT/PWM3
PB30/OTGTWD
PB31/OTGTWCK
PD0/TXD1/SPI0_NPCS2
PD1/RXD1/SPI0_NPCS3
PD2/TXD2/SPI1_NPCS2
PD3/RXD2/SPI1_NPCS3
PD4/FIQ/DMARQ2
PD5/EBI0_NWAIT/RTS2
PD6/EBI0_NCS4/CFCS0/CTS2
PD7/EBI0_NCS5/CFCS1/RTS1
PD8/EBI0_CFCE1/CTS1
PD9/EBI0_CFCE2/SCK2
PD10/SCK1
PD11/EBI0_NCS2/TSYNC
PD12/EBI0_A23/TCLK
PD13/EBI0_A24/TPS0
PD14/EBI0_A25_CFRNW/TPS1
PD15/EBI0_NCS3/NANDCS/TPS2
PD16/EBI0_D16/TPK0
PD17/EBI0_D17/TPK1
PD18/EBI0_D18/TPK2
PD19/EBI0_D19/TPK3
PD20/EBI0_D20/TPK4
PD21/EBI0_D21/TPK5
PD22/EBI0_D22/TPK6
PD23/EBI0_D23/TPK7
PD24/EBI0_D24/TPK8
PD25/EBI0_D25/TPK9
PD26/EBI0_D26/TPK10
PD27/EBI0_D27/TPK11
PD28/EBI0_D28/TPK12
PD29/EBI0_D29/TPK13
PD30/EBI0_D30/TPK14
PD31/EBI0_D31/TPK15
H16
F15
F14
F17
G16
F16
E15
E17
B17
H13
G18
H12
G14
G13
G17
G15
J18
J13
J14
J12
H18
H15
H17
H14
K17
K16
K18
K13
L14
J15
J16
J17
PB16
PB17
PB18
PB19
PB20
PB21
PB22
PB23
PB24
PB25
PB26
PB27
PB28
PB29
PB30
PB31
PB8
PB9
PB10
PB11
PB12
PB13
PB14
PB15
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
TPK4
TPK5
TPK6
TPK7
TPK8
TPK9
TPK10
TPK11
TPK12
TPK13
TPK14
TPK15
TSYNC
TCLK
TPS0
TPS1
TPS2
TPK0
TPK1
TPK2
TPK3
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PD10
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
K2
K7
J1
K6
H1
K8
J2
K5
J8
J7
J3
J6
H7
G1
J5
J4
G2
H2
H6
H3
G6
H4
G7
H5
B10
D10
C10
F10
A10
G5
G3
F1
6
PB3
R134
4.7K
BOOT MODE SELECT
Closed
PB[0..31]
11
Opened =
=
PD[0..31]
8
7
6
5
PD11
PD12
PD13
PD14
PD15
PD16
PD17
PD18
PD19
PD20
PD21
PD22
PD23
PD24
PD25
PD26
PD27
PD28
PD29
PD30
PD31
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
12
Internal ROM BOOT
NCS0
RR3
0R
R139
RR4
0R
RR5
0R
0R
0R
R135 4.7K
RR6
RR7
0R
5
EBI0_D[0..31]
PD16 EBI0_D16
PD17 EBI0_D17
PD18 EBI0_D18
PD19 EBI0_D19
PD20 EBI0_D20
PD21 EBI0_D21
PD22 EBI0_D22
PD23 EBI0_D23
PD24 EBI0_D24
PD25 EBI0_D25
PD26 EBI0_D26
PD27 EBI0_D27
PD28 EBI0_D28
PD29 EBI0_D29
PD30 EBI0_D30
PD31 EBI0_D31
EBI0_A[0..22]
EBI0_RAS
EBI0_CAS
EBI0_SDWE
EBI0_SDA10
EBI0_SDCKE
EBI0_SDCK
EBI0_NCS0
EBI0_NCS1/SDCS
EBI0_NRD/CFOE
EBI0_NWE/NWR0/CFWE
EBI0_NBS1/NW1/CFIOR
EBI0_NBS3/NW3/CFIOW
EBI0_A0
EBI0_A1
EBI0_A2
EBI0_A3
EBI0_A4
EBI0_A5
EBI0_A6
EBI0_A7
EBI0_A8
EBI0_A9
EBI0_A10
EBI0_A11
EBI0_A12
EBI0_A13
EBI0_A14
EBI0_A15
EBI0_A16
EBI0_A17
EBI0_A18
EBI0_A19
EBI0_A20
EBI0_A21
EBI0_A22
EBI0_D0
EBI0_D1
EBI0_D2
EBI0_D3
EBI0_D4
EBI0_D5
EBI0_D6
EBI0_D7
EBI0_D8
EBI0_D9
EBI0_D10
EBI0_D11
EBI0_D12
EBI0_D13
EBI0_D14
EBI0_D15
F5
F2
G4
E1
E4
F3
D1
F4
C2
D4
A1
D2
B1
E3
C1
E2
F8
C7
E7
B7
C8
D8
A7
A6
B9
A8
F9
B8
E9
A9
D9
C9
F7
D6
D7
A5
D5
C6
B6
B4
B3
C4
E8
A2
C5
EBI0_NANDOE
EBI0_NANDWE
F6
A4
E6
A3
E5
B5
B2
C3
RESERVED FOR FUTURE USE
PPS
SIGI
SIGQ
CK16M
HDPB
HDMB
HDPA
HDMA
DDP
DDM
A18
B18
G9
V16
V17
C18
D18
E18
F18
ICE INTERFACE
3V3
2
4
6
8
10
12
14
16
18
20
3V3
9
11
13
15
5
7
1
3
17
19
6 7 8
3V3
RR1
100K
NOT POPULATED
R17
R18
0R
0R
2
4
1
3
5
C22 4.7NF
C24 470 pF
C25 10NF
C26 1NF
R14
NOT POPULATED
C28
22PF
C31
22PF
R16
NOT POPULATED
C33
15PF
C36
15PF
3V3
R11 1,96K 1%
R12
R13
R15
Y2
1.5K
0R
0R
32.768 kHz
NTRST
TDI
TMS
TCK
RTCK
TDO
NRST
P18
U18
R18
T18
R1
P1
U16
P17
N17
R17
U15
N18
P5
V15
VDDBU
R20
100K
SHDN
NRST
7 6
WAKE UP
5
PPS
RFIN1
RFIN2
HDPB
HDMB
HDPA
HDMA
DDP
DDM
EBI0_D0
EBI0_D1
EBI0_D2
EBI0_D3
EBI0_D4
EBI0_D5
EBI0_D6
EBI0_D7
EBI0_D8
EBI0_D9
EBI0_D10
EBI0_D11
EBI0_D12
EBI0_D13
EBI0_D14
EBI0_D15
EBI0_NBS0/A0
EBI0_NBS2/NWR2/A1
EBI0_A2
EBI0_A3
EBI0_A4
EBI0_A5
EBI0_A6
EBI0_A7
EBI0_A8
EBI0_A9
EBI0_A10
EBI0_A11
EBI0_A12
EBI0_A13
EBI0_A14
EBI0_A15
EBI0_BA0/A16
EBI0_BA1/A17
EBI0_A18
EBI0_A19
EBI0_A20
EBI0_A21
EBI0_A22
EBI0_RAS
EBI0_CAS
EBI0_SDWE
EBI0_SDA10
EBI0_SDCKE
EBI0_SDCK
EBI0_NCS0
EBI0_NCS1/SDCS
EBI0_NRD/CFOE
EBI0_NWE/NWR0/CFWE
EBI0_NBS1/NWR1/CFIOR
EBI0_NBS3/NWR3/CFIOW
EBI0_NANDOE
EBI0_NANDWE
PLLRCB
PLLRCA
XOUT
XIN
XOUT32
XIN32
NTRST
TDI
TMS
TCK
RTCK
TDO
JTAGSEL
NRST
4
4
R21
10K
3
EBI1_NBS0/A0
EBI1_NWR2/A1
EBI1_A2
EBI1_A3
EBI1_A4
EBI1_A5
EBI1_A6
EBI1_A7
EBI1_A8
EBI1_A9
EBI1_A10
EBI1_A11
EBI1_A12
EBI1_A13
EBI1_A14
EBI1_A15
EBI1_BA0/A16
EBI1_BA1/A17
EBI1_A18
EBI1_A19
EBI1_A20
EBI1_A21
EBI1_A22
EBI1_D0
EBI1_D1
EBI1_D2
EBI1_D3
EBI1_D4
EBI1_D5
EBI1_D6
EBI1_D7
EBI1_D8
EBI1_D9
EBI1_D10
EBI1_D11
EBI1_D12
EBI1_D13
EBI1_D14
EBI1_D15
T8
R8
R7
V8
P7
V7
U8
N8
P8
U7
N7
T7
U6
V5
R6
V6
U9
R9
T9
P9
V9
M9
N9
R11
N12
P13
V12
R12
U12
T12
R13
T10
R10
N10
U11
P12
V11
N11
T11
EBI1_D0
EBI1_D1
EBI1_D2
EBI1_D3
EBI1_D4
EBI1_D5
EBI1_D6
EBI1_D7
EBI1_D8
EBI1_D9
EBI1_D10
EBI1_D11
EBI1_D12
EBI1_D13
EBI1_D14
EBI1_D15
EBI1_A0
EBI1_A1
EBI1_A2
EBI1_A3
EBI1_A4
EBI1_A5
EBI1_A6
EBI1_A7
EBI1_A8
EBI1_A9
EBI1_A10
EBI1_A11
EBI1_A12
EBI1_A13
EBI1_A14
EBI1_A15
EBI1_A16
EBI1_A17
EBI1_A18
EBI1_A19
EBI1_A20
EBI1_A21
NOT USED
2
EBI1_D[0..15]
EBI1_A[0..21]
3V3
R136
10K
TPS0
TPS1
TPS2
TSYNC
TPK0
TPK1
TPK2
TPK3
TPK4
TPK5
TPK6
TPK7
TCLK
R137
0R
C160
100NF
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
1
EBI1_SDCK
EBI1_NCS0
EBI1_NRD/CFOE
EBI1_NWE/NWR0/CFWE
EBI1_NBS1/NWR1/CFIOR
R15
P10
U10
P11
V10
VDDBU
GNDBU
M8
L12
VDDCORE
VDDCORE
VDDCORE
V1
H10
A16
VDDPLLB
VDDPLLA
VDDOSC
GNDPLLB
GNDPLLA
V18
U17
T1
T17
N14
VDDIOP0
VDDIOP0
VDDIOP0
L11
C17
A17
VDDIOP1
L8
VDDIOM0
VDDIOM0
VDDIOM0
VDDIOM0
L10
K12
K10
H8
VDDIOM1
VDDIOM1
VDDIOM1
VDDIOM1
T2
M13
M10
L9
EBI1_SDCK
EBI1_NCS0
EBI1_NRD/CFOE
EBI1_NWE/NWR0/CFWE
EBI1_NBS1/NW1/CFIOR
1 2
VDDBU
MN5
R1100D121C
C16
100NF
3
C15 100NF
3
C17 100NF
C18 100NF
C19 100NF
1
C20 100NF
C21 100NF
C23 100NF
4
2
1V2
3V3
3V3
CR6
MMBD1704A
3
C27 100NF
C29 100NF
C30 100NF
5
C32 100NF
7
C34 100NF
C35 100NF
C37 100NF
C38 100NF
9
C39 100NF
C40 100NF
C41 100NF
C42 100NF
4
6
8
10
3V3
3V3
3V3
3V3
VDDISI
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
TPK8
TPK9
TPK10
TPK11
TPK12
TPK13
TPK14
TPK15
NTRST
TDI
TMS
TCK
RTCK
TDO
NRST
R138
10K
D
C
B
A
3
AT91SAM9263
2
A
REV
INIT EDIT
MODIF.
SCALE 1/1
JPG
DES.
10/10/06
DATE VER.
REV.
A
1
DATE
SHEET
3
11
D
B
CLE
ALE
NANDOE
NANDWE
NANDCS
RDYBSY
A
A[0..22]
D[0..31]
8
C
SDCS
8
7 6
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A13
SDA10
BA0
BA1
A14
3V3
SDCKE
SDCK
NBS0
NBS1
CAS
RAS
R25
470K
SDWE
SDA10
BA0
BA1
SDCKE
SDCK
CAS
RAS
SDWE
A12
N.C
CKE
CLK
DQML
DQMH
CAS
RAS
A4
A5
A6
A7
A0
A1
A2
A3
A8
A9
A10
A11
BA0
BA1
20
21
36
40
29
30
31
32
23
24
25
26
33
34
22
35
37
38
15
39
17
18
16
19
WE
CS
28
41
54
6
12
46
52
1
14
27
3
9
43
49
48
50
51
53
42
44
45
47
8
10
11
13
5
7
2
4
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
256 Mbits
D4
D5
D6
D7
D8
D9
D0
D1
D2
D3
D10
D11
D12
D13
D14
D15
3V3
C43 100NF
C45 100NF
C47 100NF
C49 100NF
C51 100NF
C53 100NF
C55 100NF
5
SDRAM
4 3 2
NORFLASH
1
3V3
R27
470K
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A13
A14
NBS2
NBS3
SDA10
BA0
BA1
SDCKE
SDCK
CAS
RAS
SDWE
A12
N.C
CKE
CLK
DQML
DQMH
CAS
RAS
A4
A5
A6
A7
A0
A1
A2
A3
A8
A9
A10
A11
BA0
BA1
20
21
36
40
29
30
31
32
23
24
25
26
33
34
22
35
37
38
15
39
17
18
16
19
WE
CS
28
41
54
6
12
46
52
1
14
27
3
9
43
49
48
50
51
53
42
44
45
47
8
10
11
13
5
7
2
4
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
256 Mbits
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
3V3
C44 100NF
C46 100NF
C48 100NF
C50 100NF
C52 100NF
C54 100NF
C56 100NF
P15
R23
NOT POPULATED
P9
A20
A22
NRST
NWE
NRD
NCS
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A1
A2
A3
A4
A5
A6
A7
A8
A21
3V3
P15
P9
2
1
4
3
6
5
8
7
48
17
16
15
10
9
21
20
19
18
25
24
23
22
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A4
A5
A6
A7
A0
A1
A2
A3
12
11
14
13
26
28
RESET
WE
N.C
VPP
CE
OE
39
41
43
45
30
32
34
36
38
40
42
44
29
31
33
35
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/00
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D0
D1
D2
D3
D4
D5
VCCQ
47
3V3
C57 100NF
VCC
GND
GND
37
46
27
C58 100NF
NOT POPULATED
R29 470K
3V3
D
C
3V3
3V3
NANDFLASH
DUAL FOOTPRINT
CLE
ALE nRE nWE nCE
RnB
WP
16
17
8
18
9
7
19
CLE
ALE
RE
WE
CE
R/B
WP
10
11
14
15
3
4
5
6
1
2
20
21
22
23
24
34
35
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
NOT POPULATED
!"#$!%&$'"(#)
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
40
42
44
46
26
28
30
32
41
43
45
47
27
29
31
33
N.C
PRE
N.C
39
38
36
VCC
VCC
VSS
VSS
VSS
37
12
48
25
13
D9
D10
D11
D12
D13
D14
D15
D5
D6
D7
D8
D0
D1
D2
D3
D4
3V3
C60
100NF
C59
100NF
CLE
ALE nRE nWE nCE
RnB
WP
16
17
8
18
9
7
19
CLE
ALE
RE
WE
CE
R/B
WP
10
11
14
15
3
4
5
6
1
2
20
21
22
23
24
25
26
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
!"#$!%&$'"(#)
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
41
42
43
44
29
30
31
32
N.C
N.C
N.C
N.C
N.C
N.C
PRE
N.C
N.C
N.C
N.C
N.C
48
47
46
45
40
39
38
35
34
33
28
27
VCC
VCC
37
12
VSS
VSS
36
13
D0
D1
D2
D3
D4
D5
D6
D7
3V3
RESET-
3V3
DIOW-
DIOR-
IORDY
INTRQ
CS0-
D3
D2
D1
D0
D7
D6
D5
D4
A1
A0
3V3
IDE CONNECTOR
LT1
29
31
33
35
21
23
25
27
37
39
41
43
13
15
17
19
9
11
5
7
A
C
E
1
3
LT2
14
16
18
20
6
8
10
12
F
2
4
B
D
30
32
34
36
22
24
26
28
38
40
42
44
D8
D9
D10
D11
D12
D13
D14
D15
R39 10K 3V3
A2
C61
100NF
3V3
C62
10µF
CS1-
B
7 6 5 4 3
EBI0 MEMORY
2
A
REV
INIT EDIT
MODIF.
SCALE 1/1
JPG
DES.
10/10/06
DATE VER.
REV.
A
DATE
SHEET
4
11
1
A
B
C
D
8 7 6 5 4 3 2 1
D
D[0..15]
A[1..21]
NCS
NWR
NOE
LB
UB
3V3
A16
A17
A18
A19
A20
A21
A9
A10
A11
A12
A13
A14
A15
A1
A2
A3
A4
A5
A6
A7
A8
R40 10K
G3
G4
F3
F4
H2
H3
H4
H5
B4
C3
C4
D4
A3
A4
A5
B3
E4
D3
H1
G2
H6
E3
A8
A9
A10
A11
A12
A13
A14
A15
A4
A5
A6
A7
A0
A1
A2
A3
A16
A17
A18
A19
A20
NC
A6
B5
G5
A2
E2
E1
W
G
A1
B2
LB
UB
PSRAM
E2
F2
F1
G1
B1
C1
C2
D2
E5
F5
F6
G6
B6
C5
C6
D5
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D0
D1
D2
D3
D4
D5
VCC
VCC
E1
D6
VSS
VSS
D1
E6
3V3
C63 100NF
C64 100NF
C
B
A
8 7 6 5 4 3
EBI1 MEMORY
2
A
REV
INIT EDIT
MODIF.
SCALE 1/1
JPG
DES.
10/10/06
DATE VER.
REV.
A
DATE
SHEET
5
11
1
A
B
A
D
C
8 7
8 7 6
6 5 4
CKSEL
MCI0_CK
SPI0_SPCK
1
2
3
IN1
GND
IN0
IN2
VCC
Y
6
5
4
3V3
C65
100NF
MCI0_CD
MCI0_WP
MCI0_DA1
MCI0_DA0
MCI0_CDA
MCI0_DA3
MCI0_DA2
SD CARD / MMC CARD
DATAFLASH CARD INTERFACE
3V3
C66 100NF
2
1
4
3
9
6
5
8
7
12
11
10
MCI1_CD
MCI1_WP
MCI1_DA1
MCI1_DA0
MCI1_CK
MCI1_CDA
MCI1_DA3
MCI1_DA2
3V3
C67 100NF
2
1
4
3
9
6
5
8
7
SD CARD / MMC CARD INTERFACE
SCL
SDA
3V3
R43
10K
R44
10K
3V3
C68
100NF
6
5
8
SCL
SDA
VCC
A0
A1
NC
1
2
3
4
GND
7
WP
SERIAL EEPROM
12
11
10
3
5 4
2 1
3
SERIAL MEMORY
2
A
REV
INIT EDIT
MODIF.
SCALE 1/1
JPG
DES.
10/10/06
DATE VER.
REV.
A
DATE
SHEET
6
11
1
A
D
C
B
D
C
B
A
8
8
7 6
EXT_CLK
SDATA_OUT
BITCLK
SDATA_IN
SYNC
RST#
CLOCK SELECTION - PIN STRAPING TABLE
RA
OUT
OUT
IN
IN
RB
OUT
IN
OUT
IN
CODEC ID
PRIMARY
SECONDARY
PRIMARY
PRIMARY
CLK FREQ
24.576 MHz
12.288 MHz
48.000 MHz
14.318 MHz
Local XTAL
Ext. BITCLK
Ext. BITCLK (Into XTAL-IN)
Ext. BITCLK (Into XTAL-IN)
RA
RB
(see table)
R49 1K
R50 1K
R51 NOT POPULATED
C77 22PF
C81
100NF 3V3
AVDD_AC97
C79
10µF
10V
C82
100NF
C80 22PF
7
8
9
10
11
12
5
6
1
2
3
4
DVDD1
XTL_IN
XTL_OUT
DVSS1
SDATA_OUT
BIT_CLK
DVSS2
SDATA_IN
DVDD2
SYNC
RESET
NC
5 4 3
L3 742792093
L4 742792093
C71
470 pF
C73
100NF
C74
100NF
C75
10µF
10V
AGND_AC97 C76 1µF
LINE_OUT_R
LINE_OUT_L
AVDD4
AVSS4
AFILT4
AFILT3
AFILT2
AFILT1
VREFOUT
VREF
AVSS1
AVDD1
28
27
26
25
32
31
30
29
36
35
34
33
AVDD_AC97
VREFOUT
C84 100NF
C85 270 pF
C86 270 pF
C87 270 pF
C88 270 pF
C89 100NF
C90 100NF
C91 1µF
AGND_AC97
R47
1K
R48
1K
R52 22K
AGND_AC97
4
3
AVDD_AC97
R53 22K
C78 10µF
6 C83 100NF
5
C92
100NF
2
1
7
AGND_AC97
8
2
3.5 PHONEJACK STEREO
3
J11
5
2
C72
470 pF
1 4
HEADPHONE
LINE-OUT
1
1
2
3
A
B
GND
VCC
C
5
4
3V3
Need only to isolate PB3/BMS during the reset sequence
R56 2,2K
R58 2,2K
AGND_AC97
C93 1µF
C94 1µF
R60
4.7K
R57 4.7K
L5 742792093
R59 4.7K
R61
4.7K
L6 742792093
C95
470 pF
3.5 PHONEJACK STEREO
3 J12 5
2
C96
470 pF
1 4
LINE-IN
C101
10µF
10V
5V AVDD_AC97
L8 4.7µH 220mA
C102
100NF
R66 0R
C103
47 uF
6V3
AGND_AC97
C97 100NF
OPTIONAL VOICE
FILTER COMPONENTS
R62 100R
C98 100NF
C99
10NF
R63 100R
C100
10NF
AGND_AC97
R64
3,9K
OPTIONAL MIC BIASING FROM VREFOUT
R68
NOT POPULATED
VREFOUT
R65
3,9K
AGND_AC97
R69 470R
AVDD_AC97
R71 470R
L7 742792093
L9 742792093
C104
470 pF
3.5 PHONEJACK STEREO
3
J13
5
2
C105
470 pF
1
C106
470 pF
R67
0R
AGND_AC97
4
MONO / STEREO
MICROPHONE INPUT
7 6 5
R70
NOT POPULATED
TO BIAS FROM VREFOUT
CHANGE R64 and R65 to 3k 5%
DO NOT INSTALL R71, R69, C107, C108
C107
10µF
10V
VREFOUT MUST BE PROGRAMMED TO 3.7V
USING VREFH BIT (REG 76h)
AGND_AC97
C108
10µF
10V
4 3 2
A
REV
INIT EDIT
MODIF.
SCALE 1/1
JPG
DES.
10/10/06
DATE VER.
REV.
A
1
DATE
SHEET
7
11
D
C
B
A
8 7
D
SERIAL DEBUG PORT
1
6
2
7
3
8
4
9
5
C110
100NF
C117
100NF
3V3
C109
100NF
16
15
2
0R R81
6
14
7
13
8
6
1
C111
100NF
3
4
C115
100NF
5
11
10
12
9
0R R77
3V3
R72
100K
DTXD
DRXD
5
C
C120
100NF
1
4
6 5
2
3
15K R83
*
R85
22K
3V3
NOT POPULATED
R88
1,5K
C119
33PF
USB DEVICE INTERFACE
USBCNX
DDM
DDP
C121
15PF
C122
15PF
B
A
C126
33 uF C125
100NF
5V
8
7
USB HOST INTERFACE
OUTA
IN
ENA
FLGA
1
2
6
5
GNG
OUTB
FLGB
ENB
3
4
C127
33 uF
C128
100NF
B1
B2
B3
B4
4 3 2 1
A1
A2
A3
A4
C129
100NF
NOT POPULATED
C130
47pF
C131
47pF R98
15K
R99
15K
NOT POPULATED
C132
47pF C133
47pF
R102
15K
R103
15K
ENA
FLGA
FLGB
ENB
HDMA
HDPA
HDMB
HDPB
8 7 6 5
4
TXD
RTS
RXD
CTS
3
3V3
R73
100K
R74
100K
C112
100NF
C116
100NF
1
3
4
5
11
10
12
9
2
6
14
7
13
8
16
15
2
3V3
C113
100NF
C114
100NF
C118
100NF
1
RS232 COM PORT
1
6
2
7
3
8
4
9
5
D
CANRS
CANTX
CANRXEN
CANRX
3V3
R86
10K
R95
10K
5
4
2
8
MN16
Rs
1
7
6
C123
100NF
3
3V3
C124
10µF
10V
R90
120R
CAN BUS
1
2
3
C
B
4 3 2
A
REV
INIT EDIT
MODIF.
SCALE 1/1
JPG
DES.
10/10/06
DATE VER.
REV.
A
1
DATE
SHEET
8
11
A
D
C
B
A
8
8
7 6 5 4 3 2 1
3V3
TX_CLK
TXD1
TXD0
TX_EN
RXD1
RXD0
RX_DV
RX_ER
MDC
MDIO
MDINTR
NRST
1
2
3V3
4
3
C134
100NF
3V3
R118 0R
39
3V3
C143
100NF
C144
100NF
C145
100NF
41
30
23
15
33
44
10
40
36
35
24
25
32
34
37
16
38
42
17
18
19
20
21
22
26
27
28
29
REF_CLK/XT2
TXD3
TXD2
TXD1
TXD0
TX_EN
TX_CLK/ISOLATE
RXD3/PHYAD3
RXD2/PHYAD2
RXD1/PHYAD1
RXD0/PHYAD0
RX_CLK/10BTSER
RX_DV/TESTMODE
TX_ER/TXD4
RX_ER/RXD4/RPTR
COL/RMII
CRS/PHYAD4
MDC
MDIO
MDINTR
DISMDIX
DVDD
DVDD
DVDD
DGND
DGND
DGND
PWRDWN
RESET
XT1
TX+
TX-
RX+
RX-
AVDDR
AVDDR
AVDDT
AGND
AGND
AGND
BGRESG
43
7
8
3
4
BGRES
LEDMODE
LED0/OP0
LED1/OP1
LED2/OP2
CABLESTS/LINKSTS
N.C
48
31
11
12
13
14
45
1
2
9
5
6
46
AVDDT
47
C136
100NF
C138
100NF
C141
100NF
GND_ETH
L10 742792093
C139
10µF
AVDDT
C140
10µF
R107
49R9
1%
R109
49R9
1%
C135
100NF
GND_ETH
R108
49R9
1%
AVDDT
R111
49R9
1%
C137
100NF
C142
100NF
GND_ETH
7
8
3
5
6
4
2
1
J20
TD+
3V3
2 3 4
GND_ETH
RJ45 ETHERNET CONNECTOR
3V3
FULL DUPLEX
SPEED 100
LINK&ACT
R120 0R
3V3
C146
10µF
R121 0R
GND_ETH
7 6 5 4 3
ETHERNET
2
A
REV
INIT EDIT
MODIF.
SCALE 1/1
JPG
DES.
10/10/06
DATE VER.
REV.
A
1
DATE
SHEET
9
11
A
D
C
B
B
A
8 7
D
C
ISI_D[0..11]
VDDISI
CTRL1
SCL
IMAGE SENSOR CONNECTOR
3V3
C149
100NF
C150
100NF
C147
10V
10µF
ISI_D1
ISI_D3
ISI_D5
ISI_D7
ISI_D9
ISI_D11
17
19
21
23
25
27
29
9
11
13
15
5
7
1
3
18
20
22
24
26
28
30
10
12
14
16
6
8
2
4
ISI_D0
ISI_D2
ISI_D4
ISI_D6
ISI_D8
ISI_D10
CTRL2
SDA
ISI_MCK
ISI_VSYNC
ISI_HSYNC
ISI_PCK
6
8 7 6
5
5
4 3 2 1
Z17 TX09D71VM1CCA
1/4 VGA TFT LCD DISPLAY
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
40
39
38
37
36
35
34
33
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
C151
100NF
X_RIGHT
Y_LOW
X_LEFT
Y_UP
B0
B1
B2
B3
B4
B5
G0
G1
G2
G3
G4
G5
R0
R1
R2
R3
R4
R5
LCDD18
LCDD19
LCDD20
LCDD21
LCDD22
LCDD23
LCDD10
LCDD11
LCDD12
LCDD13
LCDD14
LCDD15
LCDD2
LCDD3
LCDD4
LCDD5
LCDD6
LCDD7
C148
100NF
R122 10K
LCDCC
R123
10K
VCTRL
PCI
B[0..5]
G[0..5]
LCDDEN
LCDHSYNC
LCDDDOTCK
R[0..5]
DTMG
HSYNC
DCLK
3V3
C152
10µF
10V
3V3
TOUCH SCREEN CONTROLLER
X_LEFT
Y_UP
X_RIGHT
Y_LOW
RFTS
4
5
2
3
XP
YP
XM
YM
7
8
IN3
IN4
DCLK
DIN
DOUT
CS
16
14
12
15
BUSY
PENIRQ
13
11
VREF
VCC
VCC
9
1
10
C154
100NF
GND
6
R124
100K
R125 47R
AGND C156
100NF
TWO USER'S ANALOG INPUTS
Full-Scale Input Span 0 to VREF
L11 4.7µH 220mA
3V3
C153
10µF
R133 0R
SPCK
MOSI
MISO
NPCS
BUSY
IRQ
4 3 2
A
REV
INIT EDIT
MODIF.
SCALE 1/1
JPG
DES.
10/10/06
DATE VER.
REV.
A
DATE
SHEET
10
11
1
A
D
C
B
B
A
D
C
8
8 7
7 6 5 4 3
PA[0..31]
PB[0..31]
MCI1_CDA
MCI1_DA1
MCI1_DA3
TWCK/RF0
SPI1_MOSI
SPI1_NPCS0
SPI1_NPCS2/TIOA2
OTG_DAT_VP
OTGRCV/PWM2
OTGINT/PWM3
OTGTWCK
PA7
PA9
PA11
PB5
PB13
PB15
PB17
PB19
PB21
PB23
PB25
PB27
PB29
PB31
3V3
25
27
29
31
17
19
21
23
33
35
37
39
9
11
13
15
5
7
1
3
5V
26
28
30
32
18
20
22
24
34
36
38
40
10
12
14
16
6
8
2
4 PA6
PA8
PA10
PB4
PB6
PB12
PB14
PB16
PB18
PB20
PB22
PB24
PB26
PB28
PB30
MCI1_CK/PCK2
MCI1_DA0
MCI1_DA2
TWD/RK0
TF1/DMARQ1
SPI1_MISO
SPI1_SPCK
SPI1_NPCS1/PCK1
SPI1_NPCS3/TIOB2
OTG_SE0_VM/DMARQ3
OTGTP_OE
OTGSUSPEND/TCLK0
OTGTWD
3V3
PC[0..31]
PD[0..31]
PE[0..31]
RXD1/SPI0_NPCS3
RXD2/SPI1_NPCS3
EBI0_NWAIT/RTS2
EBI0_NCS5/CFCS1/RTS1
EBI0_CFCE2/SCK2
EBI0_NCS2/TSYNC
EBI0_A24/TPS0
KBDC0
KBDC2/TIOB0
PD1
PD3
PD5
PD7
PD9
PD11
PD13
PE17
PE19
PC13
3V3
25
27
29
31
17
19
21
23
33
35
37
39
9
11
13
15
5
7
1
3
26
28
30
32
18
20
22
24
34
36
38
40
10
12
14
16
6
8
2
4
3V3
PD0
PD2
PD4
PD6
PD8
PD10
PD12
PD14
PE16
PE18
PE22
TXD1/SPI0_NPCS2
TXD2/SPI1_NPCS2
FIQ/DMARQ2
EBI0_NCS4/CFCS0/CTS2
EBI0_CFCE1/CTS1
SCK1
EBI0_A23/TCLK
EBI0_A25_CFRNW/TPS1
KBDPWR
KBDC1/TIOA0
ECRS/EBI1_NCS2/NANDCS
PC0
PC28 PWM0/TCLK1
2
RESERVED - NOT POPULATED
C157
100NF L12 4.7µH 220mA
3V3
C158
10µF
SIGI
SIGQ
18
20
22
24
26
28
10
12
14
16
6
8
2
4
17
19
21
23
25
27
9
11
13
15
5
7
1
3
PB12
PB13
PD4
PB18
PB14
5V
C159
100NF
CLK16M
RFTS
18
20
22
24
26
28
10
12
14
16
6
8
2
4
17
19
21
23
25
27
9
11
13
15
5
7
1
3
6 5 4 3
1
EXPANSION
2
A
REV
INIT EDIT
MODIF.
SCALE 1/1
JPG
DES.
10/10/06
DATE VER.
REV.
A
1
DATE
SHEET
11
11
A
D
C
B
Section 6
Warning
6.1
BMS Signal Sampling
The following behavior and its consequences are related to an AT91SAM9263 device issue described in the Errata section of the AT91SAM9263 datasheet (“BMS: BMS does not have correct state”). The text below is a reminder of this issue and a Workaround proposal at the board level.
Description
The BMS signal, which is multiplexed with the PB3/AC97RX PIO needs to be sampled at a High Level for the AT91SAM9263 microcontroller to boot out of the internal ROM.
At power up, the on-board AC97 device negates its “SDATA_IN” output pin and due to this fact, the
BMS_PB3/AC97RX pin needs to be isolated during the reset phase.
The MN20 gate, controlled by the NRST signal, achieves this, but with the default ERSTL value in the reset controller (refer to the RSTC section in the AT91SAM9263 datasheet for more details), when the
VDDBU power supply is applied for more than 1.2 seconds before the VDDCORE power supply, the
AT91SAM9263 microcontroller samples the BMS signal one Slow Clock (SLCK) cycle after the NRST signal rising (See
As a result, the BMS signal is sampled at a Low Level and the AT91SAM9263 boots out of the external
EBI device connected to NCS0.
AT91SAM9263-EK Evaluation Board User Guide 6-1
6325D–ATARM–26-Aug-09
Warning
Figure 6-1. BMS Signal Sampling
SLCK
MCK
Backup Supply
(VDDBU)
POR output backup_nreset processor_nreset
NRST
(nrst_out)
Startup Time
Processor Startup
= 3 cycles
Any
Freq.
EXTERNAL RESET LENGTH
= 2 cycles
BMS_PB3/AC97RX
BMS signal sampling
Workaround:
A t th e fir s t V D D B U p o w e r up o r i f t h i s p o w e r s u p p l y h a s be e n s h u t d o w n ( J 4 - 1 op e n e d
(VDDBU/VDDBACKUP Jumper) or the CR1225 battery cell (J3) removed or changed), the following power-up sequence has to be applied in order to boot out of the internal ROM:
1.
Close J2 to force power on
2.
Open J5 (Boot Mode Select Jumper)
3.
Power on the board
4.
Remove and replace J4-1 (VDDBU/VDDBACKUP Jumper)
6-2
6325D–ATARM–26-Aug-09
AT91SAM9263-EK Evaluation Board User Guide
Section 7
Errata
7.1
JTAGSEL S1 Footprint Selector
The S1 footprint must never be shorted to select a JTAG mode, else the chip can be damaged.
By default, the JTAGSEL input pin integrates a pull-down resistor (ICE mode). To select the JTAG mode, connect the JTAGSEL input pin to VDDBU power.
7.2
PIO Usage
PC20 and PC21 are not routed on the PCB. As a result, these signals are inaccessible.
7.3
TWI Line Pull-Ups for Fast Mode Operation
In order to use the TWI in Fast Mode (up to 400 Kbits/s), the default 10 K Ω resistors R43 and R44 should be replaced by smaller values (e.g., 2.2 K
Ω).
Note that there is no need to change the pull-up resistors if the TWI is used in Standard Mode (up to
100 Kbits/s).
AT91SAM9263-EK Evaluation Board User Guide 7-1
6325D–ATARM–26-Aug-09
Section 8
Revision History
8.1
Revision History
Table 8-1.
Document
6279A
6279B
6279C
6279D
Comments
First issue.
Added errata Section 7.3, ” TWI line pullups for Fast
Updated
,
.
Deleted some Peripheral A labels from
“PIO Controller B,” on page 3-8
and some Peripheral B labels from
Table 3-5, “PIO Controller E,” on page 3-
New schematic Sheet 3/11 on AT91SAM9263-EK.
Added
Change Request
Ref.
4087
4506
4404
4371
Issue not applicable: GPS signals shall only be removed from Rev B and later versions.
4674
In
, 7/11 edited
n Section 5.1, ” Schematics” , Rev B changed into
Rev A in 3/11
5083
5625
Row R30 and note (2) added to Table 4-1 on page 4-1
6056
AT91SAM9263-EK Evaluation Board User Guide 8-1
6325D–ATARM–26-Aug-09
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