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Section 6
Warning
6.1
BMS Signal Sampling
The following behavior and its consequences are related to an AT91SAM9263 device issue described in the Errata section of the AT91SAM9263 datasheet (“BMS: BMS does not have correct state”). The text below is a reminder of this issue and a Workaround proposal at the board level.
Description
The BMS signal, which is multiplexed with the PB3/AC97RX PIO needs to be sampled at a High Level for the AT91SAM9263 microcontroller to boot out of the internal ROM.
At power up, the on-board AC97 device negates its “SDATA_IN” output pin and due to this fact, the
BMS_PB3/AC97RX pin needs to be isolated during the reset phase.
The MN20 gate, controlled by the NRST signal, achieves this, but with the default ERSTL value in the reset controller (refer to the RSTC section in the AT91SAM9263 datasheet for more details), when the
VDDBU power supply is applied for more than 1.2 seconds before the VDDCORE power supply, the
AT91SAM9263 microcontroller samples the BMS signal one Slow Clock (SLCK) cycle after the NRST signal rising (See
As a result, the BMS signal is sampled at a Low Level and the AT91SAM9263 boots out of the external
EBI device connected to NCS0.
AT91SAM9263-EK Evaluation Board User Guide 6-1
6325D–ATARM–26-Aug-09
Warning
Figure 6-1. BMS Signal Sampling
SLCK
MCK
Backup Supply
(VDDBU)
POR output backup_nreset processor_nreset
NRST
(nrst_out)
Startup Time
Processor Startup
= 3 cycles
Any
Freq.
EXTERNAL RESET LENGTH
= 2 cycles
BMS_PB3/AC97RX
BMS signal sampling
Workaround:
A t th e fir s t V D D B U p o w e r up o r i f t h i s p o w e r s u p p l y h a s be e n s h u t d o w n ( J 4 - 1 op e n e d
(VDDBU/VDDBACKUP Jumper) or the CR1225 battery cell (J3) removed or changed), the following power-up sequence has to be applied in order to boot out of the internal ROM:
1.
Close J2 to force power on
2.
Open J5 (Boot Mode Select Jumper)
3.
Power on the board
4.
Remove and replace J4-1 (VDDBU/VDDBACKUP Jumper)
6-2
6325D–ATARM–26-Aug-09
AT91SAM9263-EK Evaluation Board User Guide
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Table of contents
- 5 Overview
- 5 1.1 Scope
- 5 1.2 Deliverables
- 5 1.3 AT91SAM9263-EK Evaluation Board
- 7 Setting Up the AT91SAM9263-EK Board
- 7 2.1 Electrostatic Warning
- 7 2.2 Requirements
- 7 2.3 Layout
- 10 2.4 Powering Up the Board
- 10 2.5 Backup Power Supply
- 10 2.6 Getting Started
- 11 2.7 AT91SAM9263-EK Block Diagram
- 12 Board Description
- 12 3.1 AT91SAM9263 Microcontroller
- 15 3.2 AT91SAM9263 Block Diagram
- 16 3.3 Memory
- 16 3.4 Clock Circuitry
- 16 3.5 Reset Circuitry
- 16 3.6 Shutdown Controller
- 16 3.7 Power Supply Circuitry
- 16 3.8 Remote Communication
- 17 3.9 Audio Stereo Interface
- 17 3.10 User Interface
- 17 3.11 Debug Interface
- 17 3.12 Expansion Slot
- 18 3.13 PIO Usage
- 23 Configuration
- 23 4.1 Configuration Jumpers and Straps
- 25 Schematics
- 25 5.1 Schematics
- 37 Warning
- 37 6.1 BMS Signal Sampling
- 39 Errata
- 39 7.1 JTAGSEL S1 Footprint Selector
- 39 7.2 PIO Usage
- 39 7.3 TWI Line Pull-Ups for Fast Mode Operation
- 40 Revision History
- 40 8.1 Revision History