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Intel ®
X6800
Δ
Core™2 Duo
Desktop Processor E6000
E4000
Core™2 Extreme Processor
Δ
and Intel
Series
®
Δ
and
Datasheet
—on 65 nm Process in the 775-land LGA Package and supporting Intel
®
64
Architecture and supporting Intel
®
Virtualization Technology ±
March 2008
Document Number: 313278-008
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR
OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS
OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING
TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,
MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. INTEL PRODUCTS ARE NOT
INTENDED FOR USE IN MEDICAL, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
Δ Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. See http://www.intel.com/products/processor_number for details. Over time processor numbers will increment based on changes in clock, speed, cache, FSB, or other features, and increments are not intended to represent proportional or quantitative increases in any particular feature. Current roadmap processor number progression is not necessarily representative of future roadmaps. See www.intel.com/products/ processor_number for details.
Intel ® 64 requires a computer system with a processor, chipset, BIOS, operating system, device drivers, and applications enabled for Intel 64. Processor will not operate (including 32-bit operation) without an Intel 64-enabled BIOS. Performance will vary depending on your hardware and software configurations. See http://www.intel.com/technology/intel64/index.htm for more information including details on which processors support Intel 64, or consult with your system vendor for more information.
No computer system can provide absolute security under all conditions. Intel ® development by Intel and requires for operation a computer system with Intel
Trusted Execution Technology (Intel ® TXT) is a security technology under
® Virtualization Technology, a Intel Trusted Execution Technology-enabled
Intel processor, chipset, BIOS, Authenticated Code Modules, and an Intel or other Intel and specific software for some uses.
Trusted Execution Technology compatible measured virtual machine monitor. In addition, Intel Trusted Execution Technology requires the system to contain a TPMv1.2 as defined by the Trusted Computing Group
±Intel ® Virtualization Technology requires a computer system with an enabled Intel ® processor, BIOS, virtual machine monitor (VMM) and, for some uses, certain platform software enabled for it. Functionality, performance or other benefits will vary depending on hardware and software configurations and may require a BIOS update. Software applications may not be compatible with all operating systems. Please check with your application vendor.
Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system. Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality.
The Intel ® Core™2 Duo desktop processor E6000 and E4000 series and Intel ® Core™2 Extreme processor X6800 may contain design defects or errors known as errata which may cause the product to deviate from published specifications.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Intel, Pentium, Intel Core, Core Inside, Intel Inside, Intel Leap ahead, Intel SpeedStep, and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2006–2008 Intel Corporation.
2 Datasheet
Contents
Introduction ............................................................................................................ 11
Terminology ..................................................................................................... 12
Processor Terminology ............................................................................ 12
Electrical Specifications ........................................................................................... 15
Power and Ground Lands.................................................................................... 15
Voltage Identification ......................................................................................... 16
Reserved, Unused, and TESTHI Signals ................................................................ 18
Absolute Maximum and Minimum Ratings .................................................. 19
DC Voltage and Current Specification ........................................................ 20
CC
Overshoot ....................................................................................... 24
FSB Signal Groups.................................................................................. 25
CMOS and Open Drain Signals ................................................................. 27
Processor DC Specifications ..................................................................... 27
GTL+ Front Side Bus Specifications ............................................. 28
Front Side Bus Clock (BCLK[1:0]) and Processor Clocking ............................ 29
FSB Frequency Select Signals (BSEL[2:0])................................................. 29
Phase Lock Loop (PLL) and Filter .............................................................. 30
BCLK[1:0] Specifications (CK505 based Platforms) ..................................... 30
BCLK[1:0] Specifications (CK410 based Platforms) ..................................... 32
Processor Component Keep-Out Zones...................................................... 39
Package Loading Specifications ................................................................ 39
Package Handling Guidelines.................................................................... 39
Package Insertion Specifications............................................................... 40
Processor Mass Specification.................................................................... 40
Processor Land Coordinates ..................................................................... 43
Alphabetical Signals Reference ............................................................................ 68
On-Demand Mode .................................................................................. 86
Datasheet 3
PROCHOT# Signal ..................................................................................87
THERMTRIP# Signal ................................................................................87
Thermal Diode...................................................................................................88
Key Difference with Legacy Diode-Based Thermal
Management ............................................................................90
PECI Device Address..................................................................92
PECI Command Support .............................................................92
PECI Fault Handling Requirements ...............................................92
PECI GetTemp0() Error Code Support ..........................................92
Features ..................................................................................................................93
Power-On Configuration Options ..........................................................................93
Clock Control and Low Power States.....................................................................93
Normal State .........................................................................................94
HALT and Extended HALT Powerdown States ..............................................94
HALT Powerdown State ..............................................................94
Extended HALT Powerdown State ................................................95
Stop Grant and Extended Stop Grant States ...............................................95
Stop Grant State .......................................................................95
Extended Stop Grant State .........................................................96
Extended HALT State, HALT Snoop State, Extended Stop Grant Snoop
State, and Stop Grant Snoop State ...........................................................96
HALT Snoop State, Stop Grant Snoop State ..................................96
Extended HALT Snoop State, Extended Stop Grant Snoop
State .......................................................................................96
SpeedStep
®
Technology .............................................................96
Boxed Processor Cooling Solution Dimensions........................................... 100
Boxed Processor Fan Heatsink Weight ..................................................... 101
Boxed Processor Retention Mechanism and Heatsink Attach Clip
Fan Heatsink Power Supply .................................................................... 101
Boxed Processor Cooling Requirements.................................................... 103
Fan Speed Control Operation (Intel ®
Core2 Extreme Processor
X6800 Only) ........................................................................................ 105
Fan Speed Control Operation (Intel ®
Core2 Duo Desktop Processor
E6000 and E4000 Series Only) ............................................................... 105
Balanced Technology Extended (BTX) Boxed Processor Specifications ................... 107
Balanced Technology Extended (BTX) Type I and Type II Boxed Processor
Cooling Solution Dimensions .................................................................. 108
Boxed Processor Thermal Module Assembly Weight ................................... 110
Boxed Processor Support and Retention Module (SRM) .............................. 111
Thermal Module Assembly Power Supply.................................................. 112
Boxed Processor Cooling Requirements.................................................... 114
Mechanical Considerations ..................................................................... 117
4 Datasheet
Figures
CC
Static and Transient Tolerance ............................................................................. 23
CC
Overshoot Example Waveform ............................................................................. 24
11 Processor Top-Side Markings Example for the Intel
® Core™2 Duo Desktop
Processor E6000 Series with 4 MB L2 Cache with 1333 MHz FSB..................................... 40
12 Processor Top-Side Markings Example for the Intel
®
Core™2 Duo Desktop
Processors E6000 Series with 4 MB L2 Cache with 1066 MHz FSB ................................... 41
13 Processor Top-Side Markings Example for the Intel
® Core™2 Duo Desktop
Processors E6000 Series with 2 MB L2 Cache ............................................................... 41
14 Processor Top-Side Markings Example for the Intel
15 Processor Top-Side Markings for the Intel ®
®
Core™2 Duo Desktop
Processors E4000 Series with 2 MB L2 Cache ............................................................... 42
Core™2 Extreme Processor X6800 ................. 42
36 Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 1 view) ................. 104
37 Boxed Processor Fan Heatsink Airspace Keepout Requirements (Side 2 View)................. 104
41 Requirements for the Balanced Technology Extended (BTX) Type I Keep-out
42 Requirements for the Balanced Technology Extended (BTX) Type II Keep-out
45 Balanced Technology Extended (BTX) Mainboard Power Header Placement
Datasheet 5
Tables
Voltage Identification Definition..................................................................................17
Absolute Maximum and Minimum Ratings ....................................................................20
CC
CC
Static and Transient Tolerance .............................................................................22
Overshoot Specifications......................................................................................24
Signal Characteristics................................................................................................26
40 TMA Set Points for 3-wire operation of BTX Type I and Type II Boxed
6 Datasheet
Revision History
Revision
Number
-001
-002
-003
-004
-005
-006
-007
-008
Description Date
• Initial release
• Corrected L1 Cache information
• Added Intel ® Core™2 Duo Desktop Processor E4300 information
• Updated Table 5, DC Voltage and Current Specification
• Added Section 2.3, PECI DC Specifications
• Updated Section 5.3, Platform Environment Control Interface (PECI)
• Updated Section 7.1.2, Boxed Processor Fan Heatsink Weight
• Updated Table 37, Fan Heatsink Power and Signal Specifications
• Added Section 7.3.2, Fan Speed Control Operation Intel
Processor E6000 and E4000 series Only)
® Core2 Extreme Processor
X6800 Only) and Section 7.3.3, Fan Speed Control Operation (Intel ® Core2 Duo Desktop
• Added Intel ® Core™2 Duo Desktop Processor E6420, E6320, and E4400 information
• Added Intel ® information.
Core™2 Duo Desktop Processor E6850, E6750, E6550, E6540, and E4500
• Added specifications for 1333 MHz FSB.
• Added support for Extended Stop Grant State, Extended Stop Grant Snoop States.
• Added new thermal profile table and figure.
• Added Intel ® Core™2 Duo Desktop Processor E4400 with CPUID = 065Dh.
• Added Intel ® Core™2 Duo Desktop Processor E4600
• Added Intel ® Core™2 Duo Desktop Processor E4700
July 2006
September 2006
January 2007
April 2007
July 2007
August 2007
October 2007
March 2008
Datasheet 7
8 Datasheet
Intel ® Core™2 Extreme Processor
X6800 and Intel ® Core™2 Duo
Desktop Processor E6000 and
E4000 Series Features
• Available at 2.93 GHz (Intel Core™2 Extreme processor X6800 only)
• Available at 3.00 GHz, 2.66 GHz, 2.40 GHz,
2.33 GHz, 2.13 GHz, and 1.86 GHz (Intel Core™2
Duo desktop processor E6850, E6750, E6700,
E6600, E6540, E6540, E6420, E6400, E6320, and
E6300 only)
• Available at 2.40 GHz, 2.20 GHz, 2.00 GHz, and
1.80 GHz and (Intel Core™2 Duo desktop processor
E4700, E4600, E4500, E4400, and E4300 only)
• Enhanced Intel SpeedStep
• Supports Intel
® Technology
® 64 architecture
• Supports Intel ® Virtualization Technology (Intel
Core™2 Extreme processor X6800 and Intel
Core™2 Duo desktop processor E6000 series only)
• Supports Execute Disable Bit capability
• Supports Intel ®
(Intel ®
Trusted Execution Technology
TXT) (Intel Core2 Duo desktop processors
E6850, E6750, and E6550 only)
• FSB frequency at 1333 MHz (Intel Core2 Duo desktop processors E6850, E6750, E6550, and
E6540 only)
• FSB frequency at 1066 MHz (Intel Core™2 Extreme processor X6800 and Intel Core™2 Duo desktop processor E6700, E6600, E6420, E6400, E6320, and E6300 only)
• FSB frequency at 800 MHz (Intel Core™2 Duo desktop processor E4000 series only)
• Binary compatible with applications running on previous members of the Intel microprocessor line
• Advance Dynamic Execution
• Very deep out-of-order execution
• Enhanced branch prediction
• Optimized for 32-bit applications running on advanced 32-bit operating systems
• Two 32-KB Level 1 data caches
• 4 MB Intel ® Advanced Smart Cache (Intel Core™2
Extreme processor X6800 and Intel Core™2 Duo desktop processor E6850, E6750, E6700, E6540,
E6540, E6600, E6420, and E6320, only)
• 2 MB Intel
®
Advanced Smart Cache (Intel Core™2
Duo desktop processor E6400, E6300, E4700,
E4600, E4500, E4400, and E4300 only)
• Intel ® Advanced Digital Media Boost
• Enhanced floating point and multimedia unit for enhanced video, audio, encryption, and 3D performance
• Power Management capabilities
• System Management mode
• Multiple low-power states
• 8-way cache associativity provides improved cache hit rate on load/store operations
• 775-land Package
The Intel Core™2 Extreme processor X6800 and Intel ® Core™2 Duo desktop processor E6000, E4000 series deliver Intel's advanced, powerful processors for desktop PCs. The processor is designed to deliver performance across applications and usages where end-users can truly appreciate and experience the performance. These applications include Internet audio and streaming video, image processing, video content creation, speech, 3D, CAD, games, multimedia, and multitasking user environments.
Intel ® 64 architecture enables the processor to execute operating systems and applications written to take advantage of the Intel 64 architecture. The processor supporting Enhanced Intel SpeedStep technology allows tradeoffs to be made between performance and power consumption.
®
The Intel Core™2 Extreme processor X6800 and Intel ® Core™2 Duo desktop processor E6000, E4000 series also include the Execute Disable Bit capability. This feature, combined with a supported operating system, allows memory to be marked as executable or non-executable.
The Intel Core™2 Extreme processor X6800 and Intel support Intel ®
® Core™2 Duo desktop processor E6000 series
Virtualization Technology. Virtualization Technology provides silicon-based functionality that works together with compatible Virtual Machine Monitor (VMM) software to improve on softwareonly solutions.
The Intel Core™2 Duo desktop processors E6850, E6750, and E6550 support Intel ®
Execution Technology (Intel ® technology.
TXT). Intel ® Trusted Execution Technology (Intel ®
Trusted
TXT) is a security
§ §
Datasheet 9
10 Datasheet
Introduction
1
Note:
Note:
Introduction
The Intel
®
Core™2 Extreme processor X6800 and Intel
®
Core™2 Duo desktop processor E6000 and E4000 series combine the performance of the previous generation of desktop products with the power efficiencies of a low-power microarchitecture to enable smaller, quieter systems. These processors are 64-bit processors that maintain compatibility with IA-32 software.
The Intel ® Core™2 Extreme processor X6800 and Intel ® Core™2 Duo desktop processor E6000 and E4000 series use Flip-Chip Land Grid Array (FC-LGA6) package technology, and plugs into a 775-land surface mount, Land Grid Array (LGA) socket, referred to as the LGA775 socket.
In this document, unless otherwise specified, the Intel processor E6000 series refers to Intel
®
Core™2 Duo desktop
Core™2 Duo desktop processors E6850, E6750,
E6550, E6540, E6700, E6600, E6420, E6400, E6320, and E6300. The Intel
®
Duo desktop processor E4000 series refers to Intel
®
E4700, E4600, E4500, E4400, and E4300.
®
Core™2
Core™2 Duo desktop processor
In this document, unless otherwise specified, the Intel ®
X6800 and Intel ® to as “processor.”
Core™2 Extreme processor
Core™2 Duo desktop processor E6000 and E4000 series are referred
The processors support several Advanced Technologies including the Execute Disable
Bit, Intel
®
64 architecture, and Enhanced Intel SpeedStep
Core™2 Duo desktop processor E6000 series and Intel Core™2 Extreme processor
X6800 support Intel
®
®
Technology. The Intel
Virtualization Technology (Intel VT). In addition, the Intel
Core™2 Duo desktop processors E6850, E6750, and E6550 support Intel
Execution Technology (Intel
®
TXT).
®
Trusted
The processor's front side bus (FSB) uses a split-transaction, deferred reply protocol like the Intel ® Pentium ® 4 processor. The FSB uses Source-Synchronous Transfer (SST) of address and data to improve performance by transferring data four times per bus clock (4X data transfer rate, as in AGP 4X). Along with the 4X data bus, the address bus can deliver addresses two times per bus clock and is referred to as a "doubleclocked" or 2X address bus. Working together, the 4X data bus and 2X address bus provide a data bus bandwidth of up to 10.7 GB/s.
Intel has enabled support components for the processor including heatsink, heatsink retention mechanism, and socket. Manufacturability is a high priority; hence, mechanical assembly may be completed from the top of the baseboard and should not require any special tooling.
The processor includes an address bus power-down capability which removes power from the address and data signals when the FSB is not in use. This feature is always enabled on the processor.
Datasheet 11
Introduction
1.1
1.1.1
Terminology
A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in the active state when driven to a low level. For example, when RESET# is low, a reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data), the ‘#’ symbol implies that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and
D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level).
The phrase “Front Side Bus” refers to the interface between the processor and system core logic (a.k.a. the chipset components). The FSB is a multiprocessing interface to processors, memory, and I/O.
Processor Terminology
Commonly used terms are explained here for clarification:
• Intel
®
Core™2 Extreme processor X6800 — Dual core processor in the FC-
LGA6 package with a 4 MB L2 cache.
• Intel ® Core™2 Duo desktop processor E6850, E6750, E6550, E6540,
E6700, E6600, E6420, and E6320, — Dual core processor in the FC-LGA6 package with a 4 MB L2 cache.
• Intel
®
Core™2 Duo desktop processor E6400, E6300, E4700, E4600,
E4500, E4400, and E4300— Dual core processor in the FC-LGA6 package with a
2 MB L2 cache.
• Processor — For this document, the term processor is the generic form of the
Intel ® Core™2 Duo desktop processor E6000 and E4000 series and the Intel ®
Core™2 Extreme processor X6800. The processor is a single package that contains one or more execution units.
• Keep-out zone — The area on or near the processor that system design can not use.
• Processor core — Processor core die with integrated L2 cache.
• LGA775 socket — The processors mate with the system board through a surface mount, 775-land, LGA socket.
• Integrated heat spreader (IHS) —A component of the processor package used to enhance the thermal performance of the package. Component thermal solutions interface with the processor at the IHS surface.
• Retention mechanism (RM) — Since the LGA775 socket does not include any mechanical features for heatsink attach, a retention mechanism is required.
Component thermal solutions should attach to the processor via a retention mechanism that is independent of the socket.
• FSB (Front Side Bus) — The electrical interface that connects the processor to the chipset. Also referred to as the processor system bus or the system bus. All memory and I/O transactions as well as interrupt messages pass between the processor and chipset over the FSB.
• Storage conditions — Refers to a non-operational state. The processor may be installed in a platform, in a tray, or loose. Processors may be sealed in packaging or exposed to free air. Under these conditions, processor lands should not be connected to any supply voltages, have any I/Os biased, or receive any clocks.
Upon exposure to “free air”(i.e., unsealed packaging or a device removed from packaging material) the processor must be handled in accordance with moisture sensitivity labeling (MSL) as indicated on the packaging material.
12 Datasheet
Introduction
• Functional operation — Refers to normal operating conditions in which all processor specifications, including DC, AC, system bus, signal quality, mechanical and thermal are satisfied.
• Execute Disable Bit — Allows memory to be marked as executable or nonexecutable, when combined with a supporting operating system. If code attempts to run in non-executable memory the processor raises an error to the operating system. This feature can prevent some classes of viruses or worms that exploit buffer over run vulnerabilities and can thus help improve the overall security of the system. See the Intel information.
®
Architecture Software Developer's Manual for more detailed
• Intel ® 64 Architecture — An enhancement to Intel's IA-32 architecture, allowing the processor to execute operating systems and applications written to take advantage of Intel 64 architecture. Further details on Intel 64 architecture and programming model can be found in the Intel ® Extended Memory 64 Technology
Software Developer Guide at http://www.intel.com/technology/intel64/index.htm.
• Enhanced Intel SpeedStep
®
Technology — Enhanced Intel Speedstep
® technology allows trade-offs to be made between performance and power consumptions, based on processor utilization. This may lower average power consumption (in conjunction with OS support).
• Intel ® Virtualization Technology (Intel VT) — Intel Virtualization Technology provides silicon-based functionality that works together with compatible Virtual
Machine Monitor (VMM) software to improve upon software-only solutions. Because this virtualization hardware provides a new architecture upon which the operating system can run directly, it removes the need for binary translation. Thus, it helps eliminate associated performance overhead and vastly simplifies the design of the
VMM, in turn allowing VMMs to be written to common standards and to be more robust. See the Intel ® Virtualization Technology Specification for the IA-32 Intel ®
Architecture for more details.
• Intel
®
Trusted Execution Technology (Intel
Technology (Intel
®
®
TXT)— Intel
®
Trusted Execution
TXT) is a security technology under development by Intel and requires for operation a computer system with Intel
®
Virtualization Technology, a
Intel Trusted Execution Technology-enabled Intel processor, chipset, BIOS,
Authenticated Code Modules, and an Intel or other Intel Trusted Execution
Technology compatible measured virtual machine monitor. In addition, Intel Trusted
Execution Technology requires the system to contain a TPMv1.2 as defined by the
Trusted Computing Group and specific software for some uses.
Datasheet 13
Introduction
1.2
Table 1.
References
Material and concepts available in the following documents may be beneficial when reading this document.
Reference Documents
Intel
Intel
Processor Thermal and Mechanical Design Guidelines
Intel ® Pentium
Edition, Intel ®
® D Processor, Intel
Pentium ®
® Pentium
4 Processor, Intel
® Processor Extreme
® Core™2 Duo Extreme
Processor X6800 Thermal and Mechanical Design Guidelines
Balanced Technology Extended (BTX) System Design Guide
Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design
Guidelines For Desktop LGA775 Socket
LGA775 Socket Mechanical Design Guide
Intel
®
®
®
Core™2 Extreme Processor X6800 and Intel
Desktop Processor E6000 and E4000 Series Specification Update
Core™2 Duo Processor and Intel
Virtualization Technology Specification for the IA-32 Intel ®
Architecture
Document
® Pentium ®
® Core™2 Duo
Dual Core
Intel ® Trusted Exectuion Technology (Intel ® the IA-32 Intel ® Architecture
TXT) Specification for
Intel ® 64 and IA-32 Intel Architecture Software Developer's Manuals
Volume 1: Basic Architecture
Volume 2A: Instruction Set Reference, A-M
Volume 2B: Instruction Set Reference, N-Z
Volume 3A: System Programming Guide
Volume 3B: System Programming Guide
Location www.intel.com/design/ processor/specupdt/
313279.htm
http://www.intel.com/ design/processor/ designex/317804.htm
http://www.intel.com/ design/pentiumXE/ designex/306830.htm www.formfactors.org
http://www.intel.com/ design/processor/ applnots/313214.htm
http://intel.com/design/
Pentium4/guides/
302666.htm
http://www.intel.com/ technology/computing/ vptech/index.htm
http://www.intel.com/ technology/security/ http://www.intel.com/ products/processor/ manuals/
§ §
14 Datasheet
Electrical Specifications
2
2.1
2.2
2.2.1
2.2.2
Electrical Specifications
This chapter describes the electrical characteristics of the processor interfaces and signals. DC electrical characteristics are provided.
Power and Ground Lands
The processor has VCC (power), VTT and VSS (ground) inputs for on-chip power distribution. All power lands must be connected to V
CC
, while all V connected to a system ground plane. The processor V
CC
SS
lands must be
lands must be supplied the voltage determined by the Voltage IDentification (VID) lands.
The signals denoted as V
V
TT
TT
provide termination for the front side bus and power to the
I/O buffers. A separate supply must be implemented for these lands, that meets the
specifications outlined in Table 5 .
Decoupling Guidelines
Due to its large number of transistors and high internal clock speeds, the processor is capable of generating large current swings. This may cause voltages on power planes to sag below their minimum specified values if bulk decoupling is not adequate. Larger bulk storage (C
BULK
), such as electrolytic or aluminum-polymer capacitors, supply current during longer lasting changes in current demand by the component, such as coming out of an idle condition. Similarly, they act as a storage well for current when entering an idle condition from a running condition. The motherboard must be designed to ensure that the voltage provided to the processor remains within the specifications
listed in Table 5 . Failure to do so can result in timing violations or reduced lifetime of
the component.
V
CC
Decoupling
V
CC
regulator solutions need to provide sufficient decoupling capacitance to satisfy the processor voltage specifications. This includes bulk capacitance with low effective series resistance (ESR) to keep the voltage rail within specifications during large swings in load current. In addition, ceramic decoupling capacitors are required to filter high frequency content generated by the front side bus and processor activity. Consult the
Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For
Desktop LGA775 Socket.
V
TT
Decoupling
Decoupling must be provided on the motherboard. Decoupling solutions must be sized to meet the expected load. To insure compliance with the specifications, various factors associated with the power delivery solution must be considered including regulator type, power plane and trace sizing, and component placement. A conservative decoupling solution would consist of a combination of low ESR bulk capacitors and high frequency ceramic capacitors.
Datasheet 15
Electrical Specifications
2.2.3
2.3
FSB Decoupling
The processor integrates signal termination on the die. In addition, some of the high frequency capacitance required for the FSB is included on the processor package.
However, additional high frequency capacitance must be added to the motherboard to properly decouple the return currents from the front side bus. Bulk decoupling must also be provided by the motherboard for proper [A]GTL+ bus operation.
Voltage Identification
The Voltage Identification (VID) specification for the processor is defined by the Voltage
Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop
LGA775 Socket. The voltage set by the VID signals is the reference VR output voltage to be delivered to the processor V
CC
CC
overshoot
specifications). Refer to Table 13
for the DC specifications for these signals. Voltages for each processor frequency is provided in
Individual processor VID values may be calibrated during manufacturing such that two devices at the same core speed may have different default VID settings. This is
reflected by the VID Range values provided in Table 5
Desktop Processor E6000 and E4000 Series and Intel
®
®
Core™2 Duo
Core™2 Extreme Processor
X6800 Specification Update for further details on specific valid core frequency and VID values of the processor. Note this differs from the VID employed by the processor during a power management event (Thermal Monitor 2, Enhanced Intel SpeedStep
Technology, or Extended HALT State).
®
The processor uses six voltage identification signals, VID[6:1], to support automatic selection of power supply voltages.
specifies the voltage level corresponding to the state of VID[6:1]. A ‘1’ in this table refers to a high voltage level and a ‘0’ refers to a low voltage level. If the processor socket is empty (VID[6:1] = 111111), or the voltage regulation circuit cannot supply the voltage that is requested, it must disable itself. The Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design
Guidelines For Desktop LGA775 Socket defines VID [7:0], VID7 and VID0 are not used on the processor; VID0 and VID7 are strapped to V
SS
on the processor package. VID0 and VID7 must be connected to the VR controller for compatibility with future processors.
The processor provides the ability to operate while transitioning to an adjacent VID and its associated processor core voltage (V
CC
). This will represent a DC shift in the load line. It should be noted that a low-to-high or high-to-low voltage state change may result in as many VID transitions as necessary to reach the target core voltage.
Transitions above the specified VID are not permitted.
Table 5 includes VID step sizes
and DC shift ranges. Minimum and maximum voltages must be maintained as shown in
Figure 1 as measured across the VCC_SENSE and VSS_SENSE lands.
The VRM or VRD used must be capable of regulating its output to the value defined by
the new VID. DC specifications for dynamic VID transitions are included in Table 5 and
Table 6 . Refer to the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery
Design Guidelines For Desktop LGA775 Socket for further details.
16 Datasheet
Electrical Specifications
Table 2.
Voltage Identification Definition
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
VID6 VID5 VID4 VID3 VID2 VID1 VID (V)
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1.1500
1.1625
1.1750
1.1875
1.2000
1.2125
1.2250
1.0500
1.0625
1.0750
1.0875
1.1000
1.1125
1.1250
1.1375
0.9500
0.9625
0.9750
0.9875
1.0000
1.0125
1.0250
1.0375
0.8500
0.8625
0.8750
0.8875
0.9000
0.9125
0.9250
0.9375
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
0
1
1
1
1
1
1
0
1
0
0
0
0
0
0
1
0
1
1
1
1
1
1
VID6 VID5 VID4 VID3 VID2 VID1 VID (V)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1.5375
1.5500
1.5625
1.5750
1.5875
1.6000
OFF
1.4375
1.4500
1.4625
1.4750
1.4875
1.5000
1.5125
1.5250
1.3375
1.3500
1.3625
1.3750
1.3875
1.4000
1.4125
1.4250
1.2375
1.2500
1.2625
1.2750
1.2875
1.3000
1.3125
1.3250
Datasheet 17
Electrical Specifications
2.4
Table 3.
2.5
Market Segment Identification (MSID)
The MSID[1:0] signals may be used as outputs to determine the Market Segment of
the processor. Table 3 provides details regarding the state of MSID[1:0]. A circuit can
be used to prevent 130 W TDP processors from booting on boards optimized for 65 W
TDP.
Market Segment Selection Truth Table for MSID[1:0]
1 , 2 , 3 , 4
MSID1 MSID0
0
0
1
1
0
1
0
1
Description
Intel ®
Intel ®
Core™2 Duo desktop processor E6000 and E4000 series and the
Core™2 Extreme processor X6800
Reserved
Reserved
Reserved
2.
3.
4.
NOTES:
1.
The MSID[1:0] signals are provided to indicate the Market Segment for the processor and may be used for future processor compatibility or for keying. Circuitry on the motherboard may use these signals to identify the processor installed.
These signals are not connected to the processor die.
A logic 0 is achieved by pulling the signal to ground on the package.
A logic 1 is achieved by leaving the signal as a no connect on the package.
Reserved, Unused, and TESTHI Signals
All RESERVED lands must remain unconnected. Connection of these lands to V
V
TT processor and the location of all RESERVED lands.
CC
, V
SS
,
, or to any other signal (including each other) can result in component malfunction or incompatibility with future processors. See
Chapter 4 for a land listing of the
In a system level design, on-die termination has been included by the processor to allow signals to be terminated within the processor silicon. Most unused GTL+ inputs should be left as no connects as GTL+ termination is provided on the processor silicon.
for details on GTL+ signals that do not include on-die termination.
Unused active high inputs, should be connected through a resistor to ground (V
SS
).
Unused outputs can be left unconnected, however this may interfere with some TAP functions, complicate debug probing, and prevent boundary scan testing. A resistor must be used when tying bidirectional signals to power or ground. When tying any signal to power or ground, a resistor will also allow for system testability. Resistor values should be within ± 20% of the impedance of the motherboard trace for front side bus signals. For unused GTL+ input or I/O signals, use pull-up resistors of the same value as the on-die termination resistors (R
TT
). For details, see
TAP and CMOS signals do not include on-die termination. Inputs and used outputs must be terminated on the motherboard. Unused outputs may be terminated on the motherboard or left unconnected. Note that leaving unused outputs unterminated may interfere with some TAP functions, complicate debug probing, and prevent boundary scan testing.
All TESTHI[13:0] lands should be individually connected to V
TT that matches the nominal trace impedance.
via a pull-up resistor
18 Datasheet
Electrical Specifications
2.6
2.6.1
The TESTHI signals may use individual pull-up resistors or be grouped together as detailed below. A matched resistor must be used for each group:
• TESTHI[1:0]
• TESTHI[7:2]
• TESTHI8/FC42 – cannot be grouped with other TESTHI signals
• TESTHI9/FC43 – cannot be grouped with other TESTHI signals
• TESTHI10 – cannot be grouped with other TESTHI signals
• TESTHI11 – cannot be grouped with other TESTHI signals
• TESTHI12/FC44 – cannot be grouped with other TESTHI signals
• TESTHI13 – cannot be grouped with other TESTHI signals
However, utilization of boundary scan test will not be functional if these lands are connected together. For optimum noise margin, all pull-up resistor values used for
TESTHI[13:0] lands should have a resistance value within ± 20% of the impedance of the board transmission line traces. For example, if the nominal trace impedance is 50 Ω, then a value between 40 Ω and 60 Ω should be used.
Voltage and Current Specification
Absolute Maximum and Minimum Ratings
Table 4 specifies absolute maximum and minimum ratings only and lie outside the
functional limits of the processor. Within functional operation limits, functionality and long-term reliability can be expected.
At conditions outside functional operation condition limits, but within absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected. If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits, but within the absolute maximum and minimum ratings, the device may be functional, but with its lifetime degraded depending on exposure to conditions exceeding the functional operation condition limits.
At conditions exceeding absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected. Moreover, if a device is subjected to these conditions for any length of time then, when returned to conditions within the functional operating condition limits, it will either not function, or its reliability will be severely degraded.
Although the processor contains protective circuitry to resist damage from static electric discharge, precautions should always be taken to avoid high static voltages or electric fields.
Datasheet 19
Electrical Specifications
Table 4.
Absolute Maximum and Minimum Ratings
Symbol Parameter Min Max Unit Notes 1, 2
V
V
CC
TT
Core voltage with respect to V
SS
FSB termination voltage with respect to V
SS
–0.3
–0.3
1.55
1.55
V
V
-
-
T
C
T
STORAGE
Processor case temperature
Processor storage temperature
See
–40
See
85
°C
°C
-
3, 4, 5
NOTES:
1. For functional operation, all processor electrical, signal quality, mechanical and thermal specifications must be satisfied.
2. Excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor.
3. Storage temperature is applicable to storage conditions only. In this scenario, the processor must not receive a clock, and no lands can be connected to a voltage bias. Storage within these limits will not affect the long-term reliability of the device. For functional operation, refer to the processor case temperature specifications.
4. This rating applies to the processor and does not include any tray or packaging.
5. Failure to adhere to this specification can affect the long term reliability of the processor.
DC Voltage and Current Specification 2.6.2
Table 5.
Symbol
VID Range
V
CC
V
CC_BOOT
Voltage and Current Specifications
Parameter
VID
Processor Number
(4 MB L2 Cache)
E6850
E6750
E6700
E6600
E6550
E6540
E6420
E6320
V
CC
for
775_VR_CONFIG_06
3.00 GHz
2.66 GHz
2.66 GHz
2.40 GHz
2.33 GHz
2.33 GHz
2.13 GHz
1.86 GHz
Processor Number
(4 MB L2 Cache)
X6800
Processor Number
(2 MB L2 Cache)
E6400
E6300
E4700
E4600,
E4500
E4400
E4300
V
CC
for
775_VR_CONFIG_05B
2.93 GHz
V
CC
for
775_VR_CONFIG_06
2.13 GHz
1.86 GHz
2.60 GHz
2.40 GHz
2.20 GHz
2.00 GHz
1.80 GHz
Default V
CC
voltage for initial power up
Min
0.8500
Typ
—
Max
1.5
and
— 1.10
—
Unit Notes 1, 2
V 3
V
V
4, 5, 6
20 Datasheet
Electrical Specifications
Table 5.
Voltage and Current Specifications
Symbol Parameter Min Typ Max Unit Notes 1, 2
V
I
V
CCPLL
CC
TT
VTT_OUT_LEFT and
VTT_OUT_RIGHT I
CC
PLL V
CC
Processor Number
E6850
E6750
E6700
E6600
E6550
E6540
E6400/E6420
E6300/E6320
E4700
E4600
E4500
E4400
E4300
Processor Number
X6800
I
CC
for
775_VR_CONFIG_06
3.00 GHz
2.66 GHz
2.66 GHz
2.40 GHz
2.33 GHz
2.33 GHz
2.13 GHz
1.86 GHz
2.60 GHz
2.40 GHz
2.20 GHz
2.00 GHz
1.80 GHz
I
CC
for
775_VR_CONFIG_05B
2.93 GHz
FSB termination voltage
(DC + AC specifications)
DC Current that may be drawn from
VTT_OUT_LEFT and VTT_OUT_RIGHT per pin
I
CC
for V
I
CC
for V
TT
supply before V
CC
stable
TT
supply after V
CC
stable
I
CC
for PLL land
I
CC
for GTLREF
- 5%
—
—
1.14
—
1.50
—
—
1.20
—
+ 5%
75
75
75
75
75
75
75
75
75
75
75
75
75
90
1.26
580
A
V mA
7
8
9
I
TT
I
CC_VCCPLL
I
CC_GTLREF
—
—
—
—
—
—
4.5
4.6
130
200
A mA
μA
10
NOTES:
1. Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical data.
These specifications will be updated with characterized data from silicon measurements at a later date.
2. Adherence to the voltage specifications for the processor are required to ensure reliable processor operation.
3. Each processor is programmed with a maximum valid voltage identification value (VID), which is set at manufacturing and can not be altered. Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range. Note this differs from the VID employed by the processor during a power management event (Thermal Monitor 2, Enhanced Intel
SpeedStep ® Technology, or Extended HALT State).
4. These voltages are targets only. A variable voltage source should exist on systems in the event that a different voltage is required. See
and
5. The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE lands at the socket with a 100 MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1 MΩ minimum impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled into the oscilloscope probe.
and
for the minimum, typical, and maximum V processor should not be subjected to any V
CC
and I
CC
CC
allowed for a given current. The
combination wherein V
CC
exceeds V
CC_MAX
for a given current.
7. I
CC_MAX
specification is based on the V
CC_MAX
loadline. Refer to Figure 1 for details.
. This specification is measured 8. V
TT
must be provided via a separate voltage source and not be connected to V
CC at the land.
9. Baseboard bandwidth is limited to 20 MHz.
10.This is maximum total current drawn from V
TT
plane by only the processor. This specification does not include the current coming from RTT (through the signal line). Refer to the Voltage Regulator-Down (VRD) 11.0
Processor Power Delivery Design Guidelines For Desktop LGA775 Socket to determine the total I system. This parameter is based on design characterization and is not tested.
TT
drawn by the
Datasheet 21
Electrical Specifications
Table 6.
V
CC
Static and Transient Tolerance
Voltage Deviation from VID Setting (V) 1, 2, 3, 4
I
CC
(A)
Maximum Voltage
1.30 mΩ
Typical Voltage
1.425 mΩ
Minimum Voltage
1.55 mΩ
60
65
70
75
40
45
50
55
20
25
30
35
0
5
10
15
0.000
-0.007
-0.013
-0.020
-0.026
-0.033
-0.039
-0.046
-0.052
-0.059
-0.065
-0.072
-0.078
-0.085
-0.091
-0.098
-0.019
-0.026
-0.033
-0.040
-0.048
-0.055
-0.062
-0.069
-0.076
-0.083
-0.090
-0.097
-0.105
-0.112
-0.119
-0.126
-0.038
-0.046
-0.054
-0.061
-0.069
-0.077
-0.085
-0.092
-0.100
-0.108
-0.116
-0.123
-0.131
-0.139
-0.147
-0.154
NOTES:
1. The loadline specification includes both static and transient limits except for overshoot allowed
.
2. This table is intended to aid in reading discrete points on Figure 1 .
3. The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE lands. Voltage regulation feedback for voltage regulator circuits must be taken from processor
VCC and VSS lands. Refer to the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery
Design Guidelines For Desktop LGA775 Socket for socket loadline guidelines and VR implementation details.
4. Adherence to this loadline specification is required to ensure reliable processor operation.
22 Datasheet
Electrical Specifications
Figure 1.
V
CC
Static and Transient Tolerance
VID - 0.000
0
VID - 0.013
VID - 0.025
VID - 0.038
VID - 0.050
VID - 0.063
VID - 0.075
VID - 0.088
VID - 0.100
VID - 0.113
VID - 0.125
VID - 0.138
VID - 0.150
VID - 0.163
10
Vcc Typical
20 30
Vcc Minimum
Icc [A]
40 50
Vcc Maximum
60 70
NOTES:
1.
The loadline specification includes both static and transient limits except for overshoot allowed as shown in
.
2.
3.
This loadline specification shows the deviation from the VID set point.
The loadlines specify voltage limits at the die measured at the VCC_SENSE and
VSS_SENSE lands. Voltage regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS lands. Refer to the Voltage Regulator-Down (VRD) 11.0
Processor Power Delivery Design Guidelines For Desktop LGA775 Socket for socket loadline guidelines and VR implementation details.
Datasheet 23
Electrical Specifications
2.6.3
Table 7.
Figure 2.
V
CC
Overshoot
The processor can tolerate short transient overshoot events where V
CC
exceeds the VID voltage when transitioning from a high to low current load condition. This overshoot cannot exceed VID + V
OS_MAX
(V
OS_MAX
is the maximum allowable overshoot voltage).
The time duration of the overshoot event must not exceed T
OS_MAX
(T
OS_MAX
is the maximum allowable time duration above VID). These specifications apply to the processor die voltage as measured across the VCC_SENSE and VSS_SENSE lands.
V
CC
Overshoot Specifications
Symbol Parameter Min Max Unit Figure Notes
V
OS_MAX
T
OS_MAX
Magnitude of V
CC
overshoot above VID
Time duration of V
CC
overshoot above VID
—
—
50
25 mV
μs
1
NOTES:
1.
Adherence to these specifications is required to ensure reliable processor operation.
V
CC
Overshoot Example Waveform
Example Overshoot Waveform
V
OS
VID + 0.050
VID - 0.000
2.6.4
0 5
T
OS
10
Time [us]
15
T
OS
: Overshoot time above VID
V
OS
: Overshoot above VID
20 25
NOTES:
1.
2.
V
T
OS
is measured overshoot voltage.
OS
is measured time duration above VID.
Die Voltage Validation
Overshoot events on processor must meet the specifications in
across the VCC_SENSE and VSS_SENSE lands. Overshoot events that are < 10 ns in duration may be ignored. These measurements of processor die level overshoot must be taken with a bandwidth limited oscilloscope set to a greater than or equal to
100 MHz bandwidth limit.
24 Datasheet
Electrical Specifications
2.7
2.7.1
Table 8.
Signaling Specifications
Most processor Front Side Bus signals use Gunning Transceiver Logic (GTL+) signaling technology. This technology provides improved noise margins and reduced ringing through low voltage swings and controlled edge rates.
Platforms implement a termination voltage level for GTL+ signals defined as V
TT
. Because platforms implement separate power planes for each processor (and chipset), separate V
CC
and V
TT supplies are necessary. This configuration allows for improved noise tolerance as processor frequency increases. Speed enhancements to data and address busses have caused signal integrity considerations and platform design methods to become even more critical than with previous processor families.
The GTL+ inputs require a reference voltage (GTLREF) which is used by the receivers to determine if a signal is a logical 0 or a logical 1. GTLREF must be generated on the
motherboard (see Table 14 for GTLREF specifications). Termination resistors (R
GTL+ signals are provided on the processor silicon and are terminated to V
TT
TT
) for
. Intel chipsets will also provide on-die termination, thus eliminating the need to terminate the bus on the motherboard for most GTL+ signals.
FSB Signal Groups
The front side bus signals have been combined into groups by buffer type. GTL+ input signals have differential input buffers, which use GTLREF[1:0] as a reference level. In this document, the term “GTL+ Input” refers to the GTL+ input group as well as the
GTL+ I/O group when receiving. Similarly, “GTL+ Output” refers to the GTL+ output group as well as the GTL+ I/O group when driving.
With the implementation of a source synchronous data bus comes the need to specify two sets of timing parameters. One set is for common clock signals which are dependent upon the rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the source synchronous signals which are relative to their respective strobe lines (data and address) as well as the rising edge of BCLK0. Asychronous signals are still present (A20M#, IGNNE#, etc.) and can become active at any time during the
clock cycle. Table 8 identifies which signals are common clock, source synchronous,
and asynchronous.
FSB Signal Groups (Sheet 1 of 2)
Signals 1 Signal Group
GTL+ Common
Clock Input
GTL+ Common
Clock I/O
Type
Synchronous to
BCLK[1:0]
Synchronous to
BCLK[1:0]
BPRI#, DEFER#, RESET#, RS[2:0]#, TRDY#
ADS#, BNR#, BPM[5:0]#, BR0#, DBSY#, DRDY#,
HIT#, HITM#, LOCK#
GTL+ Source
Synchronous I/O
GTL+ Strobes
Synchronous to assoc. strobe
Signals
REQ[4:0]#, A[16:3]#
3
A[35:17]# 3
D[15:0]#, DBI0#
D[31:16]#, DBI1#
D[47:32]#, DBI2#
D[63:48]#, DBI3#
Associated Strobe
ADSTB0#
ADSTB1#
DSTBP0#, DSTBN0#
DSTBP1#, DSTBN1#
DSTBP2#, DSTBN2#
DSTBP3#, DSTBN3#
Synchronous to
BCLK[1:0]
ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#
Datasheet 25
Electrical Specifications
.
Table 8.
Table 9.
FSB Signal Groups (Sheet 2 of 2)
Signal Group
CMOS
Type Signals 1
A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI,
SMI#, STPCLK#, PWRGOOD, TCK, TDI, TMS, TRST#,
BSEL[2:0], VID[6:1]
FERR#/PBE#, IERR#, THERMTRIP#, TDO Open Drain Output
Open Drain Input/
Output
FSB Clock
PROCHOT# 4
Power/Other
Clock BCLK[1:0], ITP_CLK[1:0] 2
VCC, VTT, VCCA, VCCIOPLL, VCCPLL, VSS, VSSA,
GTLREF[1:0], COMP[8,3:0], RESERVED, TESTHI[13:0],
VCC_SENSE, VCC_MB_REGULATION, VSS_SENSE,
VSS_MB_REGULATION, DBR# 2 , VTT_OUT_LEFT,
VTT_OUT_RIGHT, VTT_SEL, FCx, PECI, MSID[1:0]
NOTES:
1.
2.
Refer to
In processor systems where no debug port is implemented on the system board, these signals are used to support a debug port interposer. In systems with the debug port implemented on the system board, these signals are no connects.
3.
4.
The value of these signals during the active-to-inactive edge of RESET# defines the
processor configuration options. See Section 6.1
for details.
PROCHOT# signal type is open drain output and CMOS input.
Signal Characteristics
Signals with R
A[35:3]#, ADS#, ADSTB[1:0]#, BNR#, BPRI#,
D[63:0]#, DBI[3:0]#, DBSY#, DEFER#,
DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, HIT#,
HITM#, LOCK#, PROCHOT#, REQ[4:0]#,
RS[2:0]#, TRDY#
TT
Signals with No R
TT
A20M#, BCLK[1:0], BSEL[2:0],
COMP[8,3:0], IGNNE#, INIT#, ITP_CLK[1:0],
LINT0/INTR, LINT1/NMI, PWRGOOD,
RESET#, SMI#, STPCLK#, TESTHI[13:0],
VID[6:1], GTLREF[1:0], TCK, TDI, TMS,
TRST#, VTT_SEL, MSID[1:0]
Open Drain Signals
1
THERMTRIP#, FERR#/PBE#, IERR#, BPM[5:0]#,
BR0#, TDO, FCx
NOTES:
1. Signals that do not have R
TT
, nor are actively driven to their high-voltage level.
.
Table 10.
Signal Reference Voltages
GTLREF V
TT
/2
BPM[5:0]#, RESET#, BNR#, HIT#, HITM#, BR0#,
A[35:0]#, ADS#, ADSTB[1:0]#, BPRI#, D[63:0]#,
DBI[3:0]#, DBSY#, DEFER#, DRDY#, DSTBN[3:0]#,
DSTBP[3:0]#, LOCK#, REQ[4:0]#, RS[2:0]#,
TRDY#
A20M#, LINT0/INTR, LINT1/NMI,
IGNNE#, INIT#, PROCHOT#,
PWRGOOD
1
,
NOTES:
1. These signals also have hysteresis added to the reference voltage. See
for more information.
26 Datasheet
Electrical Specifications
2.7.2
2.7.3
Table 11.
.
Table 12.
CMOS and Open Drain Signals
Legacy input signals such as A20M#, IGNNE#, INIT#, SMI#, and STPCLK# use CMOS input buffers. All of the CMOS and Open Drain signals are required to be asserted/deasserted for at least four BCLKs in order for the processor to recognize the proper
signal state. See Section 2.7.3
for the DC. See
requirements for entering and leaving the low power states.
Processor DC Specifications
The processor DC specifications in this section are defined at the processor core (pads) unless otherwise stated. All specifications apply to all frequencies and cache sizes unless otherwise stated.
GTL+ Signal Group DC Specifications
Symbol Parameter Min Max Unit Notes 1
V
IL
V
V
I
IH
OH
OL
Input Low Voltage
Input High Voltage
Output High Voltage
Output Low Current
V
-0.10
GTLREF + 0.10
TT
– 0.10
N/A
GTLREF – 0.10
V
TT
+ 0.10
V
TT
[(R
V
TT_MIN
TT_MAX
)+(2*R
/
ON_MIN
)]
± 100
V
V
V
A
2, 3
-
I
I
LI
LO
Input Leakage Current
Output Leakage
Current
Buffer On Resistance
N/A
N/A ± 100
µA
µA
6
7
R
ON
10 13 Ω
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. V
IL
is defined as the voltage range at a receiving agent that will be interpreted as a logical low value.
3. The V
4. V
IH
TT
referred to in these specifications is the instantaneous V
TT
may experience excursions above V
6. Leakage to V
7. Leakage to V
SS
TT
with land held at V
TT
.
with land held at 300 mV.
TT
.
is defined as the voltage range at a receiving agent that will be interpreted as a logical high value.
5. V
IH
and V
OH
.
Open Drain and TAP Output Signal Group DC Specifications
Symbol Parameter Min Max Unit Notes 1
V
OL
V
OH
I
OL
I
LO
Output Low Voltage
Output High Voltage
Output Low Current
Output Leakage Current
V
TT
0
– 0.05 V
TT
16
N/A
0.20
+ 0.05
50
± 200
V
V mA
µA
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. V
OH
is determined by the value of the external pull-up resister to V
3. Measured at V
TT
* 0.2.
4. For Vin between 0 and V
OH
.
TT
.
-
2
3
4
Datasheet 27
Electrical Specifications
.
Table 13.
2.7.3.1
Table 14.
CMOS Signal Group DC Specifications
Symbol Parameter Min Max Unit Notes 1
I
OL
I
OH
I
LI
I
LO
V
IL
V
IH
V
OL
V
OH
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Current
Output High Current
Input Leakage Current
Output Leakage Current
-0.10
0.90 * V
TT
1.70
1.70
N/A
N/A
V
TT
* 0.30
V
TT
* 0.70
V
TT
+ 0.10
-0.10
V
TT
* 0.10
V
TT
+ 0.10
4.70
4.70
± 100
± 100
V
V
V
V mA mA
µA
µA
2, 3
, 4, 5
8
9
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. V
IL
is defined as the voltage range at a receiving agent that will be interpreted as a logical low value.
3. The V
TT
4. V
IH value.
referred to in these specifications refers to instantaneous V
TT
.
is defined as the voltage range at a receiving agent that will be interpreted as a logical high
IH
and V 5. V
6. All outputs are open drain.
7. I
OH
may experience excursions above V
OL is measured at 0.10 * V
8. Leakage to V
9. Leakage to V
SS
with land held at V
TT
with land held at 300 mV.
TT
.
TT.
I
OH is measured at 0.90 * V
TT
.
TT.
GTL+ Front Side Bus Specifications
In most cases, termination resistors are not required as these are integrated into the
processor silicon. See Table 9
for details on which GTL+ signals do not include on-die termination.
Valid high and low levels are determined by the input buffers by comparing with a reference voltage called GTLREF.
Table 14 lists the GTLREF specifications. The GTL+
reference voltage (GTLREF) should be generated on the system board using high precision voltage divider circuits.
GTL+ Bus Voltage Definitions
Symbol
GTLREF_PU
Parameter
GTLREF pull up resistor
GTLREF_PD GTLREF pull down resistor
R
TT
Termination Resistance
COMP[3:0] COMP Resistance
COMP8 COMP Resistance
Min
124 * 0.99
210 * 0.99
45
49.40
24.65
Typ
124
210
50
49.90
24.90
Max
124 * 1.01
210 * 1.01
55
50.40
25.15
Units Notes 1
Ω 2
Ω
Ω 3
4 Ω
Ω
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. GTLREF is to be generated from V
TT
GTLEREF land).
3. R
by a voltage divider of 1% resistors (one divider for each
TT
is the on-die termination resistance measured at V
TT
/3 of the GTL+ output driver.
4. COMP resistance must be provided on the system board with 1% resistors. See the applicable platform design guide for implementation details. COMP[3:0] and COMP8 resistors are tied to
V
SS
.
28 Datasheet
Electrical Specifications
2.7.4
2.7.5
Table 15.
2.7.6
Clock Specifications
Front Side Bus Clock (BCLK[1:0]) and Processor Clocking
BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the processor. As in previous generation processors, the processor’s core frequency is a multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier will be set at its
default ratio during manufacturing. Refer to Table 15
for the processor supported ratios.
The processor uses a differential clocking implementation. For more information on the processor clocking, contact your Intel Field representative. Platforms using a CK505
Clock Synthesizer/Driver should comply with the specifications in Section 2.7.8
.
Platforms using a CK410 Clock Synthesizer/Driver should comply with the specifications
Core Frequency to FSB Multiplier Configuration
Multiplication of
System Core
Frequency to FSB
Frequency
Core Frequency
(200 MHz BCLK/
800 MHz FSB)
Core Frequency
(266 MHz BCLK/
1066 MHz FSB)
Core Frequency
(333 MHz BCLK/
1333 MHz FSB)
1/6
1/7
1/8
1/9
1/10
1/11
1/12
1.20 GHz
1.40 GHz
1.60 GHz
1.80 GHz
2 GHz
2.2 GHz
2.4 GHz
1.60 GHz
1.87 GHz
2.13 GHz
2.40 GHz
2.66 GHz
2.93 GHz
3.20 GHz
NOTES:
1. Individual processors operate only at or below the rated frequency.
2. Listed frequencies are not necessarily committed production frequencies.
2.00 GHz
2.33 GHz
2.66 GHz
3.00 GHz
3.33 GHz
3.66 GHz
4.00 GHz
Notes 1, 2
-
-
-
-
-
-
FSB Frequency Select Signals (BSEL[2:0])
The BSEL[2:0] signals are used to select the frequency of the processor input clock
defines the possible combinations of the signals and the frequency associated with each combination. The required frequency is determined by the processor, chipset, and clock synthesizer. All agents must operate at the same frequency.
The Intel Core2 Duo desktop processors E6850, E6750, E6550, and E6540 operate at
1333 MHz (selected by the 333 MHz BCLK[2:0] frequency). The Intel Core2 Duo desktop processors E6700, E6600, E6420, E6400, E6320, and E6300 operate at
1066 MHz (selected by the 266 MHz BCLK[2:0] frequency). The Intel Core2 Extreme processor X6800 operates at a 1066 MHz FSB frequency (selected by a 266 MHz
BCLK[1:0] frequency). The Intel Core2 Duo desktop processors E4700, E4600, E4500,
E4400 and E4300 operate at a 800 MHz FSB frequency (selected by a 200 MHz
BCLK[1:0] frequency).
Datasheet 29
Electrical Specifications
Table 16.
2.7.7
2.7.8
BSEL[2:0] Frequency Table for BCLK[1:0]
BSEL2
H
H
H
H
L
L
L
L
BSEL1
L
L
H
H
H
H
L
L
BSEL0
H
L
L
H
H
L
L
H
FSB Frequency
266 MHz
RESERVED
RESERVED
200 MHz
RESERVED
RESERVED
RESERVED
333 MHz
Phase Lock Loop (PLL) and Filter
An on-die PLL filter solution will be implemented on the processor. The VCCPLL input is used for the PLL. Refer to
for DC specifications.
BCLK[1:0] Specifications (CK505 based Platforms)
Table 17.
Front Side Bus Differential BCLK Specifications
Symbol
V
L
V
H
V
CROSS(abs)
ΔV
CROSS
V
OS
V
US
V
SWING
I
LI
Cpad
Parameter
Input Low Voltage
Input High Voltage
Absolute Crossing Point
Range of Crossing Points
Overshoot
Undershoot
Differential Output Swing
Input Leakage Current
Pad Capacitance
Min
-0.30
N/A
0.300
N/A
N/A
Typ
N/A
N/A
N/A
N/A
N/A
-0.300 N/A
0.300
-5
.95
N/A
N/A
1.2
Max
N/A
1.15
0.550
0.140
1.4
N/A
N/A
5
1.45
Unit Figure Notes 1
V
V
V
μA pF
V
V
V
V
,
,
2
3, 4, 5
6
7
8
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. "Steady state" voltage, not including overshoot or undershoot.
3. Crossing voltage is defined as the instantaneous voltage value when the rising edge of BCLK0 equals the falling edge of BCLK1.
4. V
Havg
is the statistical average of the V
H
measured by the oscilloscope.
5. The crossing point must meet the absolute and relative crossing point specifications simultaneously.
6. Overshoot is defined as the absolute value of the maximum voltage. Undershoot is defined as the absolute value of the minimum voltage.
7. Measurement taken from differential waveform.
8. Cpad includes die capacitance only. No package parasitics are included.
30 Datasheet
Electrical Specifications
Figure 3.
Differential Clock Waveform
CLK 0
V
CROSS
Median + 75 mV
V
CROSS median
V
CROSS
Median - 75 mV
CLK 1
V
CROSS
Max
550 mV
V
CROSS
Min
300 mV
High Time
Period
Low Time
V
CROSS median
Figure 4.
Differential Clock Crosspoint Specification
500
450
400
350
300
250
650
600
550
550 + 0.5 (VHavg - 700)
300 mV
550 mV
300 + 0.5 (VHavg - 700)
200
660 670 680 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 850
VHavg (mV)
Figure 5.
Differential Measurements
Slew_rise
+150 mV
0.0V
-150 mV
V_swing
Slew _fall
+150mV
0.0V
- 150mV
Diff
Datasheet 31
Electrical Specifications
2.7.9
BCLK[1:0] Specifications (CK410 based Platforms)
Table 18.
Front Side Bus Differential BCLK Specifications
Symbol Parameter Min Typ Max Unit Figure Notes 1
V
V
V
V
L
H
CROSS(abs)
CROSS(rel)
ΔV
CROSS
V
OS
V
US
V
RBM
V
TM
Input Low Voltage
Input High Voltage
Absolute Crossing
Point
Relative Crossing
Point
Range of Crossing
Points
Overshoot
Undershoot
Ringback Margin
Threshold Region
0.5(V
V
-0.150
0.660
0.250
0.250 +
Havg
– 0.700)
N/A
N/A
0.200
CROSS
– 0.100
0.000
0.700
N/A
N/A
N/A
N/A
-0.300 N/A
N/A
N/A
0.5(V
V
N/A
0.850
0.550
0.550 +
Havg
V
– 0.700)
0.140
H
+ 0.3
N/A
N/A
CROSS
+ 0.100
V
V
V
V
V
V
V
V
V
-
-
2, 3
4,
-
6
7
8
9
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. Crossing voltage is defined as the instantaneous voltage value when the rising edge of BCLK0 equals the falling edge of BCLK1.
3. The crossing point must meet the absolute and relative crossing point specifications simultaneously.
4. V
Havg
is the statistical average of the V
5. V
Havg
H
measured by the oscilloscope.
can be measured directly using “Vtop” on Agilent* oscilloscopes and “High” on Tektronix* oscilloscopes.
6. Overshoot is defined as the absolute value of the maximum voltage.
7. Undershoot is defined as the absolute value of the minimum voltage.
8. Ringback Margin is defined as the absolute voltage difference between the maximum Rising Edge Ringback and the maximum Falling Edge Ringback.
9. Threshold Region is defined as a region entered around the crossing point voltage in which the differential receiver switches. It includes input threshold hysteresis.
Figure 6.
Differential Clock Crosspoint Specification
650
600
550
500
450
550 + 0.5 (VHavg - 700)
550 mV
400
350
300
250
250 mV
250 + 0.5 (VHavg - 700)
200
660 670 680 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 850
VHavg (mV)
32 Datasheet
Electrical Specifications
2.8
Table 19.
PECI DC Specifications
PECI is an Intel proprietary one-wire interface that provides a communication channel between Intel processors (may also include chipset components in the future) and external thermal monitoring devices. The processor contains Digital Thermal Sensors
(DTS) distributed throughout die. These sensors are implemented as analog-to-digital converters calibrated at the factory for reasonable accuracy to provide a digital representation of relative processor temperature. PECI provides an interface to relay the highest DTS temperature within a die to external management devices for thermal/ fan speed control. More detailed information is available in the Platform Environment
Control Interface (PECI) Specification.
PECI DC Electrical Limits
Symbol Definition and Conditions Min Max Units Notes 1
V in
Input Voltage Range
-0.15
V
TT
V
V hysteresis
Hysteresis
Negative-edge threshold voltage
0.1 * V
TT
— V
2
V n
0.275 * V
TT
0.500 * V
TT
V
V p
Positive-edge threshold voltage
0.550 * V
TT
0.725 * V
TT
V
I
I source
I sink leak+
High level output source
(V
OH
= 0.75 * V
TT)
Low level output sink
(V
OL
= 0.25 * V
TT
)
High impedance state leakage to V
TT
High impedance leakage to GND
-6.0
0.5
N/A
N/A
1.0
50 mA mA
µA
3
I leak-
N/A 10 µA
3
C bus
Bus capacitance per node
N/A 10 pF
4
V noise
Signal noise immunity above 300 MHz
0.1 * V
TT
— V p-p
NOTES:
1.
V
TT
supplies the PECI interface. PECI behavior does not affect V
TT
min/max specifications. Refer
2.
3.
to
TT
specifications.
The input buffers use a Schmitt-triggered input design for improved noise immunity.
The leakage specification applies to powered devices on the PECI bus.
4. One node is counted for each client and one node for the system host. Extended trace lengths might appear as additional nodes.
§ §
Datasheet 33
Electrical Specifications
34 Datasheet
Package Mechanical Specifications
3 Package Mechanical
Specifications
Figure 7.
The processor is packaged in a Flip-Chip Land Grid Array (FC-LGA6) package that interfaces with the motherboard via an LGA775 socket. The package consists of a processor core mounted on a substrate land-carrier. An integrated heat spreader (IHS) is attached to the package substrate and core and serves as the mating surface for
processor component thermal solutions, such as a heatsink. Figure 7
shows a sketch of the processor package components and how they are assembled together. Refer to the
LGA775 Socket Mechanical Design Guide for complete details on the LGA775 socket.
The package components shown in Figure 7 include the following:
• Integrated Heat Spreader (IHS)
• Thermal Interface Material (TIM)
• Processor core (die)
• Package substrate
• Capacitors
Processor Package Assembly Sketch
TIM
Substrate
IHS
Core (die)
Capacitors
LGA775 Socket
System Board
3.1
NOTE:
1.
Socket and System Board are included for reference and are not part of processor package.
Package Mechanical Drawing
The package mechanical drawings are shown in
and
. The drawings include dimensions necessary to design a thermal solution for the processor. These dimensions include:
• Package reference with tolerances (total height, length, width, etc.)
• IHS parallelism and tilt
• Land dimensions
• Top-side and back-side component keep-out dimensions
• Reference datums
• All drawing dimensions are in mm [in].
• Guidelines on potential IHS flatness variation with socket load plate actuation and installation of the cooling solution is available in the processor Thermal and
Mechanical Design Guidelines.
Datasheet 35
Figure 8.
Processor Package Drawing Sheet 1 of 3
Package Mechanical Specifications
36 Datasheet
Package Mechanical Specifications
Figure 9.
Processor Package Drawing Sheet 2 of 3
Datasheet 37
Figure 10.
Processor Package Drawing Sheet 3 of 3
Package Mechanical Specifications
38 Datasheet
Package Mechanical Specifications
3.1.1
3.1.2
.
Table 20.
3.1.3
Table 21.
Processor Component Keep-Out Zones
The processor may contain components on the substrate that define component keepout zone requirements. A thermal and mechanical solution design must not intrude into the required keep-out zones. Decoupling capacitors are typically mounted to either the topside or land-side of the package substrate. See
and
for keep-out zones. The location and quantity of package capacitors may change due to manufacturing efficiencies but will remain within the component keep-in.
Package Loading Specifications
provides dynamic and static load specifications for the processor package.
These mechanical maximum load limits should not be exceeded during heatsink assembly, shipping conditions, or standard use condition. Also, any mechanical system or component testing should not exceed the maximum limits. The processor package substrate should not be used as a mechanical reference or load-bearing surface for thermal and mechanical solution. The minimum loading specification must be maintained by any thermal and mechanical solutions.
Processor Loading Specifications
Parameter Minimum Maximum Notes
1, 2, 3 Static
Dynamic
80 N [17 lbf]
—
311 N [70 lbf]
756 N [170 lbf]
, 4
NOTES:
1.
These specifications apply to uniform compressive loading in a direction normal to the processor IHS.
2.
3.
4.
This is the maximum force that can be applied by a heatsink retention clip. The clip must also provide the minimum specified load on the processor package.
These specifications are based on limited testing for design characterization. Loading limits are for the package only and do not include the limits of the processor socket.
Dynamic loading is defined as an 11 ms duration average load superimposed on the static load requirement.
Package Handling Guidelines
includes a list of guidelines on package handling in terms of recommended maximum loading on the processor IHS relative to a fixed substrate. These package handling loads may be experienced during heatsink removal.
Package Handling Guidelines
Parameter
Shear
Tensile
Torque
Maximum Recommended
311 N [70 lbf]
111 N [25 lbf]
3.95 N-m [35 lbf-in]
Notes
1, 2
1.
2.
3.
NOTES:
A shear load is defined as a load applied to the IHS in a direction parallel to the IHS top surface.
4.
These guidelines are based on limited testing for design characterization.
A tensile load is defined as a pulling load applied to the IHS in a direction normal to the IHS surface.
A torque load is defined as a twisting load applied to the IHS in an axis of rotation normal to the
IHS top surface.
Datasheet 39
Package Mechanical Specifications
3.1.4
3.1.5
Package Insertion Specifications
The processor can be inserted into and removed from a LGA775 socket 15 times. The socket should meet the LGA775 requirements detailed in the LGA775 Socket
Mechanical Design Guide.
Processor Mass Specification
The typical mass of the processor is 21.5 g [0.76 oz]. This mass [weight] includes all the components that are included in the package.
3.1.6
Table 22.
Processor Materials
lists some of the package components and associated materials.
Processor Materials
Component
Integrated Heat Spreader (IHS)
Substrate
Substrate Lands
Material
Nickel Plated Copper
Fiber Reinforced Resin
Gold Plated Copper
3.1.7
Processor Markings
Figure 15 show the topside markings on the processor. The diagrams
are to aid in the identification of the processor.
Figure 11.
Processor Top-Side Markings Example for the Intel
®
Core™2 Duo Desktop
Processor E6000 Series with 4 MB L2 Cache with 1333 MHz FSB
INTEL® CORE™2 DUO
SLxxx [COO]
3.00GHZ/4M/1333/06
[FPO] e 4
ATPO
S/N
40 Datasheet
Package Mechanical Specifications
Figure 12.
Processor Top-Side Markings Example for the Intel ® Core™2 Duo Desktop
Processors E6000 Series with 4 MB L2 Cache with 1066 MHz FSB
INTEL® CORE™2 DUO
6700 SLxxx [COO]
2.66GHZ/4M/1066/06
[FPO]
e 4
ATPO
S/N
Figure 13.
Processor Top-Side Markings Example for the Intel
®
Processors E6000 Series with 2 MB L2 Cache
Core™2 Duo Desktop
INTEL® CORE™2 DUO
6400 SLxxx [COO]
2.13GHZ/2M/1066/06
[FPO]
e 4
ATPO
S/N
Datasheet 41
Package Mechanical Specifications
Figure 14.
Processor Top-Side Markings Example for the Intel ®
Processors E4000 Series with 2 MB L2 Cache
Core™2 Duo Desktop
INTEL® CORE™2 DUO
SLxxx [COO]
2.20GHZ/2M/800/06
[FPO] e 4
ATPO
S/N
E
E
Figure 15.
Processor Top-Side Markings for the Intel
®
Core™2 Extreme Processor X6800
INTEL® CORE™2 EXTREME
6800 SLxxx [COO]
2.93GHZ/4M/1066/05B
[FPO]
e 4
ATPO
S/N
42 Datasheet
Package Mechanical Specifications
3.1.8
Processor Land Coordinates
Figure 16 shows the top view of the processor land coordinates. The coordinates are
referred to throughout the document to identify processor lands.
.
Figure 16.
Processor Land Coordinates and Quadrants (Top View)
V
CC
/
V
SS
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
AA
Y
W
V
U
T
R
AD
AC
AB
P
N
M
L
K
J
H
G
F
E
B
A
D
C
AN
AM
AL
AK
AJ
AH
AG
AF
AE
Preliminary
Socket 775
Quadrants
Top View
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
V
TT
/ Clocks Data
§ §
J
H
G
F
E
B
A
D
C
P
N
M
L
K
AH
AG
AF
AE
AD
AC
AB
AN
AM
AL
AK
AJ
AA
Y
W
V
Common Clock/
U
Address/
T
R
Async
Datasheet 43
Package Mechanical Specifications
44 Datasheet
Land Listing and Signal Descriptions
4
4.1
Land Listing and Signal
Descriptions
This chapter provides the processor land assignment and signal descriptions.
Processor Land Assignments
This section contains the land listings for the processor. The land-out footprint is shown
. These figures represent the land-out arranged by land number and they show the physical location of each signal on the package land array
(top view).
Table 23 provides a listing of all processor lands ordered alphabetically by
land (signal) name.
Table 24 provides a listing of all processor lands ordered by land
number.
Datasheet 45
Land Listing and Signal Descriptions
C
B
A
E
D
G
F
VSS
VSS
VCC
VCC
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VCC
Y
U
T
W
V
R
P
N
M
L
K
J
Figure 17.
land-out Diagram (Top View – Left Side)
30 29 28 27 26 25 24 23 22
AN
21
VCC VCC VSS VSS VCC VCC VSS VSS VCC VCC
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
AJ
AH
AG
AF
AM
AL
AK
AE
AD
AC
AB
AA
VSS
VSS
VSS
VCC
VSS
VSS
VSS
VSS
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VCC VCC VCC
H
BSEL1
BSEL2
VTT
VTT
VTT
VTT
30
20
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
19
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
18
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
17
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
FC34
16
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
FC31
15
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
FC15
BSEL0
RSVD
FC26
VTT
VTT
VTT
VTT
29
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS FC33 FC32
BCLK1
BCLK0
VSS
VTT
VTT
VTT
VTT
28
TESTHI4 TESTHI5 TESTHI3 TESTHI6 RESET#
VTT_SEL TESTHI0 TESTHI2 TESTHI7
VSS VSS VSS FC10
VTT VTT VTT VSS
RSVD
RSVD
VTT
VTT
VTT
VTT
VTT
VTT
VSS
VSS
VCCPLL
VCCIO
PLL
VSSA
VTT
27
VTT
26
VTT
25
FC23
24
VCCA
23
D47#
VSS
D45#
D46#
VSS
D63#
D62#
22
D59#
VSS
21
D44#
D43#
D42#
VSS
DSTBN2# DSTBP2#
D41#
VSS
D48#
VSS
D40#
DBI2#
D58# DBI3# VSS
D35#
D38#
D39#
VSS
D54#
VSS
RSVD
20
D60#
D61#
19
D57#
VSS
18
D36#
D37#
VSS
D49#
DSTBP3#
VSS
D56#
17
D32#
VSS
D34#
RSVD
VSS
D55#
DSTBN3#
16
D53#
VSS
15
D31#
D30#
D33#
VSS
D51#
46 Datasheet
Land Listing and Signal Descriptions
Figure 18.
land-out Diagram (Top View – Right Side)
14 13 12 11 10 9
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
8
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
SKTOCC#
VCC
VCC
VCC
7
VID_SELE
CT
VID7
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
6
VSS_MB_
REGULATION
FC40
VID3
FC8
A35#
VSS
A29#
VSS
RSVD
A22#
VSS
A17#
5
VCC_MB_
REGULATION
VID6
VID1
VSS
A34#
A33#
A31#
A27#
VSS
ADSTB1#
A25#
A24#
VCC VSS VSS A23#
VCC VCC VCC VCC VCC VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
A19#
A18#
VSS
A10#
VSS
ADSTB0#
A4#
VSS
REQ2#
VSS
REQ3#
REQ4#
VSS
A16#
A14#
A12#
A9#
VSS
RSVD
RSVD
A5#
A3#
VSS
REQ1#
VSS
D29#
D28#
VSS
RSVD
D52#
VSS
D27#
VSS
D26#
D25#
VSS
VSS VSS VSS
DSTBN1# DBI1# FC38
D24#
DSTBP1#
VSS
D23#
VSS
D15#
VSS
D21#
D22#
D14# D11# VSS
VSS
D16#
D18#
D19#
VSS
FC38
VSS VSS
BPRI#
D17#
VSS
D12#
DSTBN0#
DEFER#
VSS
RSVD
D20#
VSS
VSS
RSVD
FC21
RSVD
VSS
D3#
TESTHI10
PECI
RS1#
FC20
VSS
D1#
A20#
VSS
A15#
A13#
A11#
A8#
VSS
RSVD
A7#
A6#
REQ0#
VSS
4
VSS_
SENSE
VSS
VID5
VID4
VSS
A32#
A30#
A28#
RSVD
VSS
RSVD
A26#
A21#
3
VCC_
SENSE
VID2
2
VSS
1
VSS
VRDSEL
ITP_CLK0
ITP_CLK1
VSS
BPM5#
VSS
FC18
FC36
VSS
FC37
VSS
VID0
PROCHOT#
VSS
BPM0#
RSVD
BPM3#
BPM4#
VSS
BPM2#
DBR#
IERR#
FC39
VSS
THERMDA
THERMDC
BPM1#
VSS
TRST#
TDO
TCK
TDI
TMS
VSS
VTT_OUT_
RIGHT
FC0 FC17
TESTHI1
VSS
TESTHI12/
FC44
RSVD
MSID0
VSS
FC30
VSS
FERR#/
PBE#
INIT#
VSS
FC29
FC4
VSS
SMI#
IGNNE#
STPCLK# THERMTRIP#
VSS TESTHI13
A20M# VSS
FC22 FC3
MSID1
FC28
COMP1
COMP3
TESTHI11
PWRGOOD
VSS
LINT1
LINT0
VTT_OUT_
LEFT
GTLREF0 FC35 VSS
TESTHI9/
FC43
VSS
HITM#
HIT#
TESTHI8/
FC42
BR0#
TRDY#
VSS
VSS LOCK#
GTLREF1
COMP2
FC5
VSS
ADS#
BNR#
FC27
RSVD
DRDY#
VSS
D50#
14
COMP8
COMP0
13
D13#
VSS
12
VSS
D9#
11
D10#
D8#
10
DSTBP0#
VSS
9
VSS
DBI0#
8
D6#
D7#
7
D5#
VSS
6
VSS
D4#
5
D0#
D2#
4
RS0#
RS2#
3
DBSY#
VSS
2
VSS
1
G
F
E
D
C
W
V
U
T
R
P
N
M
L
K
J
H
AN
AD
AC
AB
AH
AG
AF
AE
AM
AL
AK
AJ
AA
Y
B
A
Datasheet 47
48
Land Listing and Signal Descriptions
A26#
A27#
A28#
A29#
A30#
A31#
A32#
A33#
A19#
A20#
A20M#
A21#
A22#
A23#
A24#
A25#
A34#
A35#
ADS#
ADSTB0#
ADSTB1#
BCLK0
BCLK1
A11#
A12#
A13#
A14#
A15#
A16#
A17#
A18#
A3#
A4#
A5#
A6#
A7#
A8#
A9#
A10#
Table 23.
Land Name
Alphabetical Land
Assignments
Land
#
Signal Buffer
Type
Direction
M4
R4
T5
U6
L5
P6
M5
L4
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
T4
U5
U4
V5
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
V4
W5
Source Synch Input/Output
Source Synch Input/Output
AB6 Source Synch Input/Output
W6 Source Synch Input/Output
Y6
Y4
Source Synch Input/Output
Source Synch Input/Output
K3 Asynch CMOS Input
AA4 Source Synch Input/Output
AD6 Source Synch Input/Output
AA5 Source Synch Input/Output
AB5 Source Synch Input/Output
AC5 Source Synch Input/Output
AB4 Source Synch Input/Output
AF5 Source Synch Input/Output
AF4 Source Synch Input/Output
AG6 Source Synch Input/Output
AG4 Source Synch Input/Output
AG5 Source Synch Input/Output
AH4 Source Synch Input/Output
AH5 Source Synch Input/Output
AJ5 Source Synch Input/Output
AJ6 Source Synch Input/Output
D2 Common Clock Input/Output
R6 Source Synch Input/Output
AD5 Source Synch Input/Output
F28 Clock Input
G28 Clock Input
D7#
D8#
D9#
D10#
D11#
D12#
D13#
D14#
COMP8
D0#
D1#
D2#
D3#
D4#
D5#
D6#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
BR0#
BSEL0
BSEL1
BSEL2
COMP0
COMP1
COMP2
COMP3
BNR#
BPM0#
BPM1#
BPM2#
BPM3#
BPM4#
BPM5#
BPRI#
Table 23.
Land Name
Alphabetical Land
Assignments
Land
#
Signal Buffer
Type
Direction
C2 Common Clock Input/Output
AJ2 Common Clock Input/Output
AJ1 Common Clock Input/Output
AD2 Common Clock Input/Output
AG2 Common Clock Input/Output
AF2 Common Clock Input/Output
AG3 Common Clock Input/Output
G8 Common Clock Input
A13
T1
G2
R1
F3 Common Clock Input/Output
G29 Power/Other Output
H30
G30
Power/Other
Power/Other
Output
Output
Power/Other
Power/Other
Power/Other
Power/Other
Input
Input
Input
Input
C6
A5
B6
B7
B13
B4
C5
A4
Power/Other Input
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
A7 Source Synch Input/Output
A10 Source Synch Input/Output
A11 Source Synch Input/Output
B10 Source Synch Input/Output
C11 Source Synch Input/Output
D8 Source Synch Input/Output
B12 Source Synch Input/Output
C12 Source Synch Input/Output
D11 Source Synch Input/Output
G9 Source Synch Input/Output
F8
F9
Source Synch Input/Output
Source Synch Input/Output
E9
D7
Source Synch Input/Output
Source Synch Input/Output
E10 Source Synch Input/Output
Datasheet
Land Listing and Signal Descriptions
Datasheet
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
Table 23.
Land Name
Alphabetical Land
Assignments
Land
#
Signal Buffer
Type
Direction
D10 Source Synch Input/Output
F11 Source Synch Input/Output
F12 Source Synch Input/Output
D13 Source Synch Input/Output
E13 Source Synch Input/Output
G13 Source Synch Input/Output
F14 Source Synch Input/Output
G14 Source Synch Input/Output
F15 Source Synch Input/Output
G15 Source Synch Input/Output
G16 Source Synch Input/Output
E15 Source Synch Input/Output
E16 Source Synch Input/Output
G18 Source Synch Input/Output
G17 Source Synch Input/Output
F17 Source Synch Input/Output
F18 Source Synch Input/Output
E18 Source Synch Input/Output
E19 Source Synch Input/Output
F20 Source Synch Input/Output
E21 Source Synch Input/Output
F21 Source Synch Input/Output
G21 Source Synch Input/Output
E22 Source Synch Input/Output
D22 Source Synch Input/Output
G22 Source Synch Input/Output
D20 Source Synch Input/Output
D17 Source Synch Input/Output
A14 Source Synch Input/Output
C15 Source Synch Input/Output
C14 Source Synch Input/Output
B15 Source Synch Input/Output
C18 Source Synch Input/Output
B16 Source Synch Input/Output
A17 Source Synch Input/Output
B18 Source Synch Input/Output
C21 Source Synch Input/Output
B21 Source Synch Input/Output
B19 Source Synch Input/Output
FC10
FC15
FC17
FC18
FC20
FC21
FC22
FC23
DSTBP1#
DSTBP2#
DSTBP3#
FC0
FC3
FC4
FC5
FC8
FC26
FC27
FC28
FC29
FC30
FC31
FC32
DBSY#
DEFER#
DRDY#
DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
D61#
D62#
D63#
DBI0#
DBI1#
DBI2#
DBI3#
DBR#
Table 23.
Land Name
Alphabetical Land
Assignments
Land
#
Signal Buffer
Type
Direction
E29
G1
U1
U2
U3
J16
H15
A19 Source Synch Input/Output
A22 Source Synch Input/Output
B22 Source Synch Input/Output
A8 Source Synch Input/Output
G11 Source Synch Input/Output
D19 Source Synch Input/Output
C20 Source Synch Input/Output
AC2 Power/Other Output
B2 Common Clock Input/Output
G7 Common Clock Input
C1 Common Clock Input/Output
C8 Source Synch Input/Output
G12 Source Synch Input/Output
G20 Source Synch Input/Output
A16 Source Synch Input/Output
B9 Source Synch Input/Output
E5
F6
J3
A24
E24
H29
Y3
AE3
J2
T2
F2
AK6
E12 Source Synch Input/Output
G19 Source Synch Input/Output
C17 Source Synch Input/Output
Y1 Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
49
50
Land Listing and Signal Descriptions
Table 23.
Land Name
INIT#
ITP_CLK0
ITP_CLK1
LINT0
LINT1
LOCK#
MSID0
MSID1
PECI
PROCHOT#
PWRGOOD
REQ0#
REQ1#
REQ2#
REQ3#
REQ4#
FC40
FERR#/PBE#
GTLREF0
GTLREF1
HIT#
HITM#
IERR#
IGNNE#
FC33
FC34
FC35
FC36
FC37
FC38
FC38
FC39
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Alphabetical Land
Assignments
Table 23.
Alphabetical Land
Assignments
Land
#
Signal Buffer
Type
Direction Land Name
H16
J17
H4
AD3
Power/Other
Power/Other
Power/Other
Power/Other
RESERVED
RESERVED
RESERVED
RESERVED
AB3
G10
C9
AA2
AM6
R3
H1
H2
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Asynch CMOS
Power/Other
Power/Other
Output
Input
Input
D4 Common Clock Input/Output
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESET#
E4 Common Clock Input/Output
AB2
N2
P3
AK3
AJ3
K1
L1
C3 Common Clock Input/Output
W1
V1
G5
Asynch CMOS
Asynch CMOS
Asynch CMOS
TAP
TAP
Asynch CMOS
Asynch CMOS
Power/Other
Power/Other
Output
Input
Input
Input
Input
Input
Input
Output
Output
Power/Other Input/Output
RS0#
RS1#
RS2#
SKTOCC#
SMI#
STPCLK#
TCK
TDI
TDO
TESTHI0
TESTHI1
TESTHI10
TESTHI11
AL2
N1
K4
J5
M6
K6
J6
A20
AC4
AE4
Asynch CMOS Input/Output TESTHI12/
FC44
Power/Other Input
Source Synch Input/Output
TESTHI13
Source Synch Input/Output
TESTHI2
Source Synch Input/Output
TESTHI3
Source Synch Input/Output
TESTHI4
Source Synch Input/Output
TESTHI5
TESTHI6
TESTHI7
TESTHI8/FC42
AE6
AH2
D1
D14
TESTHI9/FC43
THERMDA
THERMDC
THERMTRIP#
TMS
Land
#
Signal Buffer
Type
AF1
F26
W3
H5
P1
P2
M3
AE1
AD1
F23
F29
G6
N4
D16
E23
E6
E7
N5
P5
V2
G23 Common Clock
B3 Common Clock
F5 Common Clock
A3 Common Clock
AE8 Power/Other
Asynch CMOS
Asynch CMOS
TAP
TAP
TAP
Power/Other
Power/Other
Power/Other
Power/Other
W2
L2
F25
G25
G27
G26
G24
F24
G3
G4
AL1
AK1
M2
AC1
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Asynch CMOS
TAP
Direction
Input
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
Input
Input
Input
Output
Input
Input
Input
Input
Datasheet
Land Listing and Signal Descriptions
Datasheet
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
TRDY#
TRST#
VCC
VCC
VCC
VCC
VCC
VCC
Table 23.
Land Name
Alphabetical Land
Assignments
Land
#
Signal Buffer
Type
E3 Common Clock
AG1 TAP
AA8
AB8
Power/Other
Power/Other
AC23 Power/Other
AC24 Power/Other
AC25 Power/Other
AC26 Power/Other
AC27 Power/Other
AC28 Power/Other
AC29 Power/Other
AC30 Power/Other
AC8 Power/Other
AD23 Power/Other
AD24 Power/Other
AD25 Power/Other
AD26 Power/Other
AD27 Power/Other
AD28 Power/Other
AD29 Power/Other
AD30 Power/Other
AD8 Power/Other
AE11 Power/Other
AE12 Power/Other
AE14 Power/Other
AE15 Power/Other
AE18 Power/Other
AE19 Power/Other
AE21 Power/Other
AE22 Power/Other
AE23 Power/Other
AE9 Power/Other
AF11 Power/Other
AF12 Power/Other
AF14 Power/Other
AF15 Power/Other
AF18 Power/Other
AF19 Power/Other
AF21 Power/Other
Direction
Input
Input
Table 23.
Land Name
Alphabetical Land
Assignments
Land
#
Signal Buffer
Type
AF22 Power/Other
AF8 Power/Other
AF9 Power/Other
AG11 Power/Other
AG12 Power/Other
AG14 Power/Other
AG15 Power/Other
AG18 Power/Other
AG19 Power/Other
AG21 Power/Other
AG22 Power/Other
AG25 Power/Other
AG26 Power/Other
AG27 Power/Other
AG28 Power/Other
AG29 Power/Other
AG30 Power/Other
AG8 Power/Other
AG9 Power/Other
AH11 Power/Other
AH12 Power/Other
AH14 Power/Other
AH15 Power/Other
AH18 Power/Other
AH19 Power/Other
AH21 Power/Other
AH22 Power/Other
AH25 Power/Other
AH26 Power/Other
AH27 Power/Other
AH28 Power/Other
AH29 Power/Other
AH30 Power/Other
AH8 Power/Other
AH9
AJ11
Power/Other
Power/Other
AJ12
AJ14
AJ15
Power/Other
Power/Other
Power/Other
Direction
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
51
52
Land Listing and Signal Descriptions
Table 23.
Land Name
Alphabetical Land
Assignments
Land
#
Signal Buffer
Type
AJ18 Power/Other
AJ19 Power/Other
AJ21 Power/Other
AJ22 Power/Other
AJ25 Power/Other
AJ26 Power/Other
AJ8
AJ9
Power/Other
Power/Other
AK11 Power/Other
AK12 Power/Other
AK14 Power/Other
AK15 Power/Other
AK18 Power/Other
AK19 Power/Other
AK21 Power/Other
AK22 Power/Other
AK25 Power/Other
AK26 Power/Other
AK8
AK9
Power/Other
Power/Other
AL11 Power/Other
AL12 Power/Other
AL14 Power/Other
AL15 Power/Other
AL18 Power/Other
AL19 Power/Other
AL21 Power/Other
AL22 Power/Other
AL25 Power/Other
AL26 Power/Other
AL29 Power/Other
AL30 Power/Other
AL8
AL9
Power/Other
Power/Other
AM11 Power/Other
AM12 Power/Other
AM14 Power/Other
AM15 Power/Other
AM18 Power/Other
Direction
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
Table 23.
Land Name
Alphabetical Land
Assignments
Land
#
Signal Buffer
Type
J21
J22
J23
J24
J25
J26
J27
AM19 Power/Other
AM21 Power/Other
AM22 Power/Other
AM25 Power/Other
AM26 Power/Other
AM29 Power/Other
AM30 Power/Other
AM8 Power/Other
AM9 Power/Other
AN11 Power/Other
AN12 Power/Other
AN14 Power/Other
AN15 Power/Other
AN18 Power/Other
AN19 Power/Other
AN21 Power/Other
J15
J18
J19
J20
J11
J12
J13
J14
AN22 Power/Other
AN25 Power/Other
AN26 Power/Other
AN29 Power/Other
AN30 Power/Other
AN8 Power/Other
AN9
J10
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Direction
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
Datasheet
Land Listing and Signal Descriptions
Datasheet
Table 23.
Land Name
Alphabetical Land
Assignments
Land
#
Signal Buffer
Type
N27
N28
N29
N30
N23
N24
N25
N26
M28
M29
M30
M8
M24
M25
M26
M27
N8
P8
R8
T23
T24
T25
T26
K30
K8
L8
M23
K26
K27
K28
K29
J9
K23
K24
K25
J28
J29
J30
J8
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Direction
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
Table 23.
Land Name
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC_MB_
REGULATION
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC_SENSE
VCCA
VCCIOPLL
VCCPLL
VID_SELECT
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
Alphabetical Land
Assignments
AN5
AN3
A23
C23
D23
AN7
Land
#
Signal Buffer
Type
Y27
Y28
Y29
Y30
Y8
Y23
Y24
Y25
Y26
W24
W25
W26
W27
W28
W29
W30
W8
U26
U27
U28
U29
U30
U8
V8
W23
T8
U23
U24
U25
T27
T28
T29
T30
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Direction
Power/Other
Power/Other
Power/Other
Output
Output
Power/Other
Power/Other
Power/Other Output
53
54
Land Listing and Signal Descriptions
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VRDSEL
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VID7
Table 23.
Land Name
Alphabetical Land
Assignments
Land
#
Signal Buffer
Type
A2
A21
A6
A9
AL3
A12
A15
A18
AM2
AL5
AM3
AL6
AK4
AL4
AM5
AM7
AA23 Power/Other
AA24 Power/Other
AA25 Power/Other
AA26 Power/Other
AA27 Power/Other
AA28 Power/Other
AA29 Power/Other
AA3 Power/Other
AA30 Power/Other
AA6 Power/Other
AA7
AB1
Power/Other
Power/Other
AB23 Power/Other
AB24 Power/Other
AB25 Power/Other
AB26 Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AB27 Power/Other
AB28 Power/Other
AB29 Power/Other
AB30 Power/Other
AB7
AC3
AC6
Power/Other
Power/Other
Power/Other
Direction
Output
Output
Output
Output
Output
Output
Output
Output
Table 23.
Land Name
Alphabetical Land
Assignments
Land
#
Signal Buffer
Type
AC7
AD4
Power/Other
Power/Other
AD7 Power/Other
AE10 Power/Other
AE13 Power/Other
AE16 Power/Other
AE17 Power/Other
AE2 Power/Other
AE20 Power/Other
AE24 Power/Other
AE25 Power/Other
AE26 Power/Other
AE27 Power/Other
AE28 Power/Other
AE29 Power/Other
AE30 Power/Other
AE5
AE7
Power/Other
Power/Other
AF10 Power/Other
AF13 Power/Other
AF16 Power/Other
AF17 Power/Other
AF20 Power/Other
AF23 Power/Other
AF24 Power/Other
AF25 Power/Other
AF26 Power/Other
AF27 Power/Other
AF28 Power/Other
AF29 Power/Other
AF3 Power/Other
AF30 Power/Other
AF6
AF7
Power/Other
Power/Other
AG10 Power/Other
AG13 Power/Other
AG16 Power/Other
AG17 Power/Other
AG20 Power/Other
Direction
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Datasheet
Land Listing and Signal Descriptions
Datasheet
Table 23.
Land Name
Alphabetical Land
Assignments
Land
#
Signal Buffer
Type
AG23 Power/Other
AG24 Power/Other
AG7
AH1
Power/Other
Power/Other
AH10 Power/Other
AH13 Power/Other
AH16 Power/Other
AH17 Power/Other
AH20 Power/Other
AH23 Power/Other
AH24 Power/Other
AH3 Power/Other
AH6
AH7
Power/Other
Power/Other
AJ10 Power/Other
AJ13 Power/Other
AJ16 Power/Other
AJ17 Power/Other
AJ20 Power/Other
AJ23 Power/Other
AJ24 Power/Other
AJ27 Power/Other
AJ28 Power/Other
AJ29 Power/Other
AJ30 Power/Other
AJ4 Power/Other
AJ7 Power/Other
AK10 Power/Other
AK13 Power/Other
AK16 Power/Other
AK17 Power/Other
AK2 Power/Other
AK20 Power/Other
AK23 Power/Other
AK24 Power/Other
AK27 Power/Other
AK28 Power/Other
AK29 Power/Other
AK30 Power/Other
Direction
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Table 23.
Land Name
Alphabetical Land
Assignments
Land
#
Signal Buffer
Type
AK5
AK7
Power/Other
Power/Other
AL10 Power/Other
AL13 Power/Other
AL16 Power/Other
AL17 Power/Other
AL20 Power/Other
AL23 Power/Other
AL24 Power/Other
AL27 Power/Other
AL28 Power/Other
AL7 Power/Other
AM1 Power/Other
AM10 Power/Other
AM13 Power/Other
AM16 Power/Other
AM17 Power/Other
AM20 Power/Other
AM23 Power/Other
AM24 Power/Other
AM27 Power/Other
AM28 Power/Other
AM4
AN1
Power/Other
Power/Other
AN10 Power/Other
AN13 Power/Other
AN16 Power/Other
AN17 Power/Other
AN2 Power/Other
AN20 Power/Other
AN23 Power/Other
AN24 Power/Other
AN27 Power/Other
AN28 Power/Other
B1
B11
Power/Other
Power/Other
B14
B17
B20
Power/Other
Power/Other
Power/Other
Direction
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
55
56
Land Listing and Signal Descriptions
Table 23.
Land Name
Alphabetical Land
Assignments
Land
#
Signal Buffer
Type
E28
E8
F10
F13
E20
E25
E26
E27
E11
E14
E17
E2
D3
D5
D6
D9
F16
F19
F22
F4
F7
H10
H11
D15
D18
D21
D24
C24
C4
C7
D12
C13
C16
C19
C22
B24
B5
B8
C10
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Direction
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Table 23.
Land Name
Alphabetical Land
Assignments
Land
#
Signal Buffer
Type
L26
L27
L28
L29
K7
L23
L24
L25
J4
J7
K2
K5
H6
H7
H8
H9
M1
M7
N3
L3
L30
L6
L7
H26
H27
H28
H3
H22
H23
H24
H25
H18
H19
H20
H21
H12
H13
H14
H17
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Direction
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Datasheet
Land Listing and Signal Descriptions
Datasheet
Table 23.
Land Name
Alphabetical Land
Assignments
Land
#
Signal Buffer
Type
V24
V25
V26
V27
T6
T7
U7
V23
R30
R5
R7
T3
R26
R27
R28
R29
V28
V29
V3
V30
V6
V7
W4
R2
R23
R24
R25
P29
P30
P4
P7
P25
P26
P27
P28
N6
N7
P23
P24
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Direction
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Table 23.
Alphabetical Land
Assignments
D25
D26
D27
D28
C27
C28
C29
C30
D29
D30
J1
B29
B30
C25
C26
B25
B26
B27
B28
A27
A28
A29
A30
AN4
B23
A25
A26
Land Name
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT_OUT_LEFT
VTT_OUT_RIG
HT
VTT_SEL
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VSS
VSS
VSS
VSS
VSS_MB_
REGULATION
VSS_SENSE
VSSA
VTT
VTT
Land
#
Signal Buffer
Type
W7
Y2
Y5
Y7
Power/Other
Power/Other
Power/Other
Power/Other
AN6
AA1
F27
Direction
Power/Other Output
Power/Other
Power/Other
Output
Output
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Output
Output
57
58
Land Listing and Signal Descriptions
VTT
VTT
VTT
VTT
VTT
VSS
DBSY#
RS0#
VSS
D61#
RESERVED
VSS
D62#
VCCA
FC23
VTT
D08#
D09#
VSS
COMP0
D50#
VSS
DSTBN3#
D56#
VSS
RS2#
D02#
D04#
VSS
D07#
DBI0#
VSS
D00#
VSS
D05#
D06#
VSS
DSTBP0#
D10#
Land
#
A30
B1
B2
B3
A26
A27
A28
A29
A22
A23
A24
A25
A18
A19
A20
A21
B4
B5
B6
B7
B8
B9
B10
A14
A15
A16
A17
A10
A11
A12
A13
A6
A7
A8
A9
A2
A3
A4
A5
Table 24.
Numerical Land
Assignment
Land Name
Signal Buffer
Type
Direction
Power/Other
Common Clock Input
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Power/Other Input
Source Synch Input/Output
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Source Synch Input/Output
Power/Other
Source Synch Input/Output
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Common Clock Input/Output
Common Clock Input
Source Synch Input/Output
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Table 24.
Numerical Land
Assignment
Land Name
Signal Buffer
Type
Direction
Power/Other
Source Synch Input/Output
Power/Other Input
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Common Clock Input/Output
Common Clock Input/Output
Common Clock Input/Output
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Source Synch Input/Output
Power/Other
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Power/Other
D01#
D03#
VSS
DSTBN0#
FC38
VSS
D11#
D14#
VTT
VTT
VTT
VTT
DRDY#
BNR#
LOCK#
VSS
D60#
VSS
D59#
D63#
VSSA
VSS
VTT
VTT
VSS
D13#
COMP8
VSS
D53#
D55#
VSS
D57#
VSS
D52#
D51#
VSS
DSTBP3#
D54#
VSS
Land
#
C9
C10
C11
C12
C5
C6
C7
C8
C1
C2
C3
C4
B27
B28
B29
B30
C13
C14
C15
C16
C17
C18
C19
B23
B24
B25
B26
B19
B20
B21
B22
B15
B16
B17
B18
B11
B12
B13
B14
Datasheet
Land Listing and Signal Descriptions
Datasheet
RESERVED
VSS
RESERVED
D49#
VSS
DBI2#
D48#
VSS
VSS
D20#
D12#
VSS
D22#
D15#
VSS
D25#
DBI3#
D58#
VSS
VCCIOPLL
VSS
VTT
VTT
VTT
VTT
VTT
VTT
RESERVED
ADS#
VSS
HIT#
VSS
D46#
VCCPLL
VSS
VTT
VTT
VTT
VTT
Land
#
D18
D19
D20
D21
D14
D15
D16
D17
D10
D11
D12
D13
D6
D7
D8
D9
D22
D23
D24
D25
D26
D27
D28
D2
D3
D4
D5
C28
C29
C30
D1
C24
C25
C26
C27
C20
C21
C22
C23
Table 24.
Numerical Land
Assignment
Land Name
Signal Buffer
Type
Direction
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Common Clock Input/Output
Power/Other
Common Clock Input/Output
Power/Other
Power/Other
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Source Synch Input/Output
Power/Other
Source Synch Input/Output
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Source Synch Input/Output
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Land
#
E28
E29
F2
F3
E24
E25
E26
E27
E20
E21
E22
E23
E16
E17
E18
E19
F8
F9
F10
F4
F5
F6
F7
E12
E13
E14
E15
E8
E9
E10
E11
E4
E5
E6
E7
D29
D30
E2
E3
FC10
VSS
VSS
VSS
VSS
FC26
FC5
BR0#
D34#
VSS
D39#
D40#
VSS
D42#
D45#
RESERVED
VTT
VTT
VSS
TRDY#
HITM#
FC20
RESERVED
RESERVED
VSS
D19#
D21#
VSS
DSTBP1#
D26#
VSS
D33#
VSS
RS1#
FC21
VSS
D17#
D18#
VSS
Table 24.
Numerical Land
Assignment
Land Name
Signal Buffer
Type
Direction
Power/Other
Power/Other
Power/Other
Common Clock Input
Common Clock Input/Output
Power/Other
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Common Clock Input/Output
Power/Other
Common Clock Input
Power/Other
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Power/Other
59
60
Land Listing and Signal Descriptions
Table 24.
Numerical Land
Assignment
Land
#
G10
G11
G12
G13
G6
G7
G8
G9
G2
G3
G4
G5
F27
F28
F29
G1
G14
G15
G16
G17
G18
G19
G20
F23
F24
F25
F26
F19
F20
F21
F22
F15
F16
F17
F18
F11
F12
F13
F14
Land Name
VTT_SEL
BCLK0
RESERVED
FC27
COMP2
TESTHI8/FC42
TESTHI9/FC43
PECI
RESERVED
DEFER#
BPRI#
D16#
FC38
DBI1#
DSTBN1#
D27#
VSS
D41#
D43#
VSS
RESERVED
TESTHI7
TESTHI2
TESTHI0
D23#
D24#
VSS
D28#
D30#
VSS
D37#
D38#
D29#
D31#
D32#
D36#
D35#
DSTBP2#
DSTBN2#
Signal Buffer
Type
Direction
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Clock
Power/Other
Power/Other
Power/Other
Power/Other
Input
Input
Input
Output
Input
Input
Input
Input
Power/Other Input/Output
Common Clock
Common Clock
Input
Input
Source Synch Input/Output
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Table 24.
Numerical Land
Assignment
Land Name
Signal Buffer
Type
Direction
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Common Clock
Power/Other
Input
Input
Power/Other
Power/Other
Power/Other
Clock
Input
Input
Input
Input
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Output
Output
Input
Input
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Input
FC32
FC33
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
FC15
D44#
D47#
RESET#
TESTHI6
TESTHI3
TESTHI5
TESTHI4
BCLK1
BSEL0
BSEL2
GTLREF0
GTLREF1
VSS
FC35
TESTHI10
VSS
Land
#
H19
H20
H21
H22
H15
H16
H17
H18
H11
H12
H13
H14
H7
H8
H9
H10
H23
H24
H25
H26
H27
H28
H29
H3
H4
H5
H6
G29
G30
H1
H2
G25
G26
G27
G28
G21
G22
G23
G24
Datasheet
Land Listing and Signal Descriptions
Datasheet
Table 24.
Numerical Land
Assignment
Land
#
J28
J29
J30
K1
J24
J25
J26
J27
J20
J21
J22
J23
J16
J17
J18
J19
K6
K7
K8
K2
K3
K4
K5
J12
J13
J14
J15
J8
J9
J10
J11
J4
J5
J6
J7
H30
J1
J2
J3
Land Name
Signal Buffer
Type
Direction
VCC
VCC
VCC
VCC
VCC
VCC
VCC
LINT0
FC31
FC34
VCC
VCC
VCC
VCC
VCC
VCC
BSEL1 Power/Other
VTT_OUT_LEFT Power/Other
FC3
FC22
Power/Other
Power/Other
VSS
REQ1#
REQ4#
VSS
Power/Other
Output
Output
Source Synch Input/Output
Source Synch Input/Output
Power/Other
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VSS
A20M#
REQ0#
VSS
REQ3#
VSS
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Asynch CMOS
Power/Other
Asynch CMOS
Input
Input
Source Synch Input/Output
Power/Other
Source Synch Input/Output
Power/Other
Power/Other
Table 24.
Land
#
M5
M6
M7
M8
M1
M2
M3
M4
L27
L28
L29
L30
L23
L24
L25
L26
M23
M24
M25
M26
M27
M28
M29
L5
L6
L7
L8
L1
L2
L3
L4
K27
K28
K29
K30
K23
K24
K25
K26
Land Name
VSS
THERMTRIP#
STPCLK#
A07#
A05#
REQ2#
VSS
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
LINT1
TESTHI13
VSS
A06#
A03#
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
Numerical Land
Assignment
Signal Buffer
Type
Direction
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Asynch CMOS
Power/Other
Input
Input
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Asynch CMOS Output
Asynch CMOS Input
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
61
62
Land Listing and Signal Descriptions
Table 24.
Land
#
P26
P27
P28
P29
P8
P23
P24
P25
P4
P5
P6
P7
N30
P1
P2
P3
P30
R1
R2
R3
R4
R5
R6
N26
N27
N28
N29
N8
N23
N24
N25
N4
N5
N6
N7
M30
N1
N2
N3
Land Name
VSS
VSS
VSS
VSS
VCC
VSS
VSS
VSS
VCC
TESTHI11
SMI#
INIT#
VSS
RESERVED
A04#
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
PWRGOOD
IGNNE#
VSS
RESERVED
RESERVED
VSS
VSS
VSS
COMP3
VSS
FERR#/PBE#
A08#
VSS
ADSTB0#
Numerical Land
Assignment
Signal Buffer
Type
Direction
Power/Other
Power/Other
Asynch CMOS
Power/Other
Input
Input
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Asynch CMOS
Asynch CMOS
Power/Other
Source Synch Input/Output
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other Input
Power/Other
Asynch CMOS Output
Source Synch Input/Output
Power/Other
Source Synch Input/Output
Input
Input
Input
Table 24.
Numerical Land
Assignment
Land Name
Signal Buffer
Type
Direction
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Input
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VCC
VCC
FC28
FC29
FC30
A13#
A12#
A10#
VCC
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
COMP1
FC4
VSS
A11#
A09#
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VSS
VSS
Land
#
U3
U4
U5
U6
T29
T30
U1
U2
T25
T26
T27
T28
T7
T8
T23
T24
U7
U8
U23
U24
U25
U26
U27
T3
T4
T5
T6
R29
R30
T1
T2
R25
R26
R27
R28
R7
R8
R23
R24
Datasheet
Land Listing and Signal Descriptions
Datasheet
Table 24.
Numerical Land
Assignment
Land
#
Land Name
Signal Buffer
Type
Direction
W29
W30
Y1
Y2
Y3
Y4
W7
W8
W23
W24
W25
W26
W27
W28
W3
W4
W5
W6
U28
U29
U30
V1
VCC
VCC
VCC
MSID1
Power/Other
Power/Other
Power/Other
Power/Other Output
V2
V3
V4
V5
V6
V7
V8
V23
V24
V25
V26
V27
V28
V29
V30
W1
RESERVED
VSS
A15#
A14#
VSS
VSS
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
MSID0
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
W2 TESTHI12/FC44 Power/Other
Output
Input
TESTHI1
VSS
A16#
A18#
Power/Other
Power/Other
Input
Source Synch Input/Output
Source Synch Input/Output
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
FC0
VSS
FC17
A20#
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Source Synch Input/Output
Table 24.
Numerical Land
Assignment
Land
#
Land Name
Signal Buffer
Type
Direction
VSS
IERR#
FC37
A26#
A24#
A17#
VSS
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AB5
AB6
AB7
AB8
AB1
AB2
AB3
AB4
AA23
AA24
AA25
AA26
AA27
AA28
AA29
AA30
AB23
AB24
AB25
Y23
Y24
Y25
Y26
Y5
Y6
Y7
Y8
VSS
A19#
VSS
VCC
VCC
VCC
VCC
VCC
Power/Other
Source Synch Input/Output
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AA5
AA6
AA7
AA8
Y27
Y28
Y29
Y30
VCC
VCC
VCC
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Output AA1 VTT_OUT_RIGHT Power/Other
AA2 FC39 Power/Other
AA3
AA4
VSS
A21#
Power/Other
Source Synch Input/Output
A23#
VSS
VSS
VCC
Source Synch Input/Output
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Asynch CMOS Output
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
63
64
Land Listing and Signal Descriptions
Land
#
AD4
AD5
AD6
AD7
AD8
AD23
AD24
AD25
AC26
AC27
AC28
AC29
AC30
AD1
AD2
AD3
AD26
AD27
AD28
AD29
AD30
AE1
AE2
AC4
AC5
AC6
AC7
AC8
AC23
AC24
AC25
AB26
AB27
AB28
AB29
AB30
AC1
AC2
AC3
Table 24.
Numerical Land
Assignment
Land Name
VSS
ADSTB1#
A22#
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
TDI
BPM2#
FC36
VCC
VCC
VCC
VCC
VCC
TCK
VSS
RESERVED
A25#
VSS
VSS
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
TMS
DBR#
VSS
Signal Buffer
Type
Direction
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
TAP
Power/Other
Power/Other
Input
Output
Source Synch Input/Output
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
TAP Input
Common Clock Input/Output
Power/Other
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
TAP
Power/Other
Input
VSS
VSS
VSS
VSS
TDO
BPM4#
VSS
A28#
VCC
VSS
VSS
VSS
VCC
VSS
VCC
VCC
VCC
VSS
VSS
VCC
VCC
VCC
VSS
VCC
FC18
RESERVED
VSS
RESERVED
VSS
SKTOCC#
VCC
VSS
A27#
VSS
VSS
VCC
VCC
VSS
VCC
Land
#
AE27
AE28
AE29
AE30
AF1
AF2
AF3
AF4
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AE26
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
AE3
AE4
AE5
AE6
AE7
AE8
AE9
AE10
Table 24.
Numerical Land
Assignment
Land Name
Signal Buffer
Type
Direction
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Output
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
TAP Output
Common Clock Input/Output
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Datasheet
Land Listing and Signal Descriptions
Datasheet
Table 24.
Numerical Land
Assignment
Land Name
Signal Buffer
Type
Direction
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
TAP Input
Common Clock Input/Output
Common Clock Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
A29#
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VSS
VSS
VSS
TRST#
BPM3#
BPM5#
A30#
A31#
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VSS
VSS
VSS
VCC
VCC
VCC
VSS
VCC
VCC
Land
#
AG6
AG7
AG8
AG9
AG10
AG11
AG12
AG13
AF28
AF29
AF30
AG1
AG2
AG3
AG4
AG5
AG14
AG15
AG16
AG17
AG18
AG19
AG20
AF20
AF21
AF22
AF23
AF24
AF25
AF26
AF27
AF12
AF13
AF14
AF15
AF16
AF17
AF18
AF19
VCC
VSS
VCC
VCC
VCC
VSS
VSS
VCC
VCC
VCC
VSS
VCC
VSS
VCC
VCC
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
RESERVED
VSS
A32#
A33#
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
Land
#
AH15
AH16
AH17
AH18
AH19
AH20
AH21
AH22
AH7
AH8
AH9
AH10
AH11
AH12
AH13
AH14
AH23
AH24
AH25
AH26
AH27
AH28
AH29
AG29
AG30
AH1
AH2
AH3
AH4
AH5
AH6
AG21
AG22
AG23
AG24
AG25
AG26
AG27
AG28
Table 24.
Numerical Land
Assignment
Land Name
Signal Buffer
Type
Direction
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
65
66
Land Listing and Signal Descriptions
Table 24.
Numerical Land
Assignment
Land Name
Signal Buffer
Type
Direction
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Common Clock Input/Output
Common Clock Input/Output
TAP Input
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
TAP
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Input
Output
VSS
VCC
VCC
VSS
VSS
VSS
VSS
THERMDC
VSS
VCC
VCC
VSS
VSS
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VCC
VSS
VCC
VCC
BPM1#
BPM0#
ITP_CLK1
VSS
A34#
A35#
VSS
VSS
ITP_CLK0
VID4
VSS
FC8
VSS
VCC
Land
#
AJ24
AJ25
AJ26
AJ27
AJ28
AJ29
AJ30
AK1
AJ16
AJ17
AJ18
AJ19
AJ20
AJ21
AJ22
AJ23
AK2
AK3
AK4
AK5
AK6
AK7
AK8
AJ8
AJ9
AJ10
AJ11
AJ12
AJ13
AJ14
AJ15
AH30
AJ1
AJ2
AJ3
AJ4
AJ5
AJ6
AJ7
Table 24.
Numerical Land
Assignment
Land Name
Signal Buffer
Type
Direction
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Asynch CMOS Input/Output
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Output
Output
Output
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VCC
VCC
VSS
VSS
VSS
VSS
THERMDA
PROCHOT#
VRDSEL
VID5
VID1
VID3
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VCC
VSS
VCC
VCC
Land
#
AL3
AL4
AL5
AL6
AL7
AL8
AL9
AL10
AK25
AK26
AK27
AK28
AK29
AK30
AL1
AL2
AL11
AL12
AL13
AL14
AL15
AL16
AL17
AK17
AK18
AK19
AK20
AK21
AK22
AK23
AK24
AK9
AK10
AK11
AK12
AK13
AK14
AK15
AK16
Datasheet
Land Listing and Signal Descriptions
Datasheet
Table 24.
Numerical Land
Assignment
Land Name
Signal Buffer
Type
Direction
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Output
Output
Output
Output
VSS
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VSS
VID6
FC40
VID7
VCC
VCC
VSS
VCC
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VID0
VID2
VCC
VSS
VSS
VCC
VCC
VCC
VSS
VCC
Land
#
AM12
AM13
AM14
AM15
AM16
AM17
AM18
AM19
AM4
AM5
AM6
AM7
AM8
AM9
AM10
AM11
AM20
AM21
AM22
AM23
AM24
AM25
AM26
AL26
AL27
AL28
AL29
AL30
AM1
AM2
AM3
AL18
AL19
AL20
AL21
AL22
AL23
AL24
AL25
Table 24.
Numerical Land
Assignment
Land
#
AM27
AM28
AM29
AM30
AN1
AN2
AN3
AN4
AN5
Land Name
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VSS
VSS
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC_SENSE
VSS_SENSE
VCC_MB_
REGULATION
VSS_MB_
REGULATION
VID_SELECT
VCC
VCC
VSS
VCC
VCC
VSS
VCC
AN6
AN15
AN16
AN17
AN18
AN19
AN20
AN21
AN22
AN7
AN8
AN9
AN10
AN11
AN12
AN13
AN14
AN23
AN24
AN25
AN26
AN27
AN28
AN29
AN30
Signal Buffer
Type
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Direction
Output
Output
Power/Other Output
Power/Other Output
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Output
67
Land Listing and Signal Descriptions
4.2
Alphabetical Signals Reference
Table 25.
Signal Description (Sheet 1 of 9)
Name
A[35:3]#
A20M#
ADS#
Type
Input/
Output
Input
Input/
Output
Description
A[35:3]# (Address) define a 2 36 -byte physical memory address space. In sub-phase 1 of the address phase, these signals transmit the address of a transaction. In sub-phase 2, these signals transmit transaction type information. These signals must connect the appropriate pins/lands of all agents on the processor FSB. A[35:3]# are source synchronous signals and are latched into the receiving buffers by ADSTB[1:0]#.
On the active-to-inactive transition of RESET#, the processor samples a subset of the A[35:3]# signals to determine power-on configuration. See
for more details.
If A20M# (Address-20 Mask) is asserted, the processor masks physical address bit 20 (A20#) before looking up a line in any internal cache and before driving a read/write transaction on the bus. Asserting A20M# emulates the 8086 processor's address wraparound at the 1-MB boundary. Assertion of A20M# is only supported in real mode.
A20M# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/
Output Write bus transaction.
ADS# (Address Strobe) is asserted to indicate the validity of the transaction address on the A[35:3]# and REQ[4:0]# signals. All bus agents observe the ADS# activation to begin protocol checking, address decode, internal snoop, or deferred reply ID match operations associated with the new transaction.
Address strobes are used to latch A[35:3]# and REQ[4:0]# on their rising and falling edges. Strobes are associated with signals as shown below.
ADSTB[1:0]#
Input/
Output
Signals
REQ[4:0]#, A[16:3]#
A[35:17]#
Associated Strobe
ADSTB0#
ADSTB1#
BCLK[1:0]
BNR#
Input
Input/
Output
The differential pair BCLK (Bus Clock) determines the FSB frequency. All processor FSB agents must receive these signals to drive their outputs and latch their inputs.
All external timing parameters are specified with respect to the rising edge of BCLK0 crossing V
CROSS
.
BNR# (Block Next Request) is used to assert a bus stall by any bus agent unable to accept new bus transactions. During a bus stall, the current bus owner cannot issue any new transactions.
68 Datasheet
Land Listing and Signal Descriptions
Table 25.
Signal Description (Sheet 1 of 9)
BR0#
Name
BPM[5:0]#
BPRI#
BSEL[2:0]
COMP8
COMP[3:0]
Type
Input/
Output
Input
Input/
Output
Output
Analog
Description
BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals. They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance. BPM[5:0]# should connect the appropriate pins/lands of all processor FSB agents.
BPM4# provides PRDY# (Probe Ready) functionality for the TAP port. PRDY# is a processor output used by debug tools to determine processor debug readiness.
BPM5# provides PREQ# (Probe Request) functionality for the TAP port. PREQ# is used by debug tools to request debug operation of the processor.
These signals do not have on-die termination.
BPRI# (Bus Priority Request) is used to arbitrate for ownership of the processor FSB. It must connect the appropriate pins/lands of all processor FSB agents. Observing BPRI# active (as asserted by the priority agent) causes all other agents to stop issuing new requests, unless such requests are part of an ongoing locked operation. The priority agent keeps BPRI# asserted until all of its requests are completed, then releases the bus by de-asserting BPRI#.
BR0# drives the BREQ0# signal in the system and is used by the processor to request the bus. During power-on configuration this signal is sampled to determine the agent ID = 0.
This signal does not have on-die termination and must be terminated.
The BCLK[1:0] frequency select signals BSEL[2:0] are used to
select the processor input clock frequency. Table 16 defines the
possible combinations of the signals and the frequency associated with each combination. The required frequency is determined by the processor, chipset and clock synthesizer. All agents must operate at the same frequency. For more information about these signals, including termination recommendations refer to
COMP[3:0] and COMP8 must be terminated to V
SS board using precision resistors. on the system
Datasheet 69
Land Listing and Signal Descriptions
Table 25.
Signal Description (Sheet 1 of 9)
Name Type Description
D[63:0]# (Data) are the data signals. These signals provide a 64bit data path between the processor FSB agents, and must connect the appropriate pins/lands on all such agents. The data driver asserts DRDY# to indicate a valid data transfer.
D[63:0]# are quad-pumped signals and will, thus, be driven four times in a common clock period. D[63:0]# are latched off the falling edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data signals correspond to a pair of one DSTBP# and one DSTBN#.
The following table shows the grouping of data signals to data strobes and DBI#.
D[63:0]#
Input/
Output
Quad-Pumped Signal Groups
Data Group
D[15:0]#
D[31:16]#
D[47:32]#
D[63:48]#
DSTBN#/
DSTBP#
0
1
2
3
DBI#
0
1
2
3
DBI[3:0]#
DBR#
DBSY#
Input/
Output
Furthermore, the DBI# signals determine the polarity of the data signals. Each group of 16 data signals corresponds to one DBI# signal. When the DBI# signal is active, the corresponding data group is inverted and therefore sampled active high.
DBI[3:0]# (Data Bus Inversion) are source synchronous and indicate the polarity of the D[63:0]# signals.The DBI[3:0]# signals are activated when the data on the data bus is inverted. If more than half the data bits, within a 16-bit group, would have been asserted electrically low, the bus agent may invert the data bus signals for that particular sub-phase for that 16-bit group.
DBI[3:0] Assignment To Data Bus
Bus Signal
DBI3#
DBI2#
DBI1#
DBI0#
Data Bus
Signals
D[63:48]#
D[47:32]#
D[31:16]#
D[15:0]#
Output
Input/
Output
DBR# (Debug Reset) is used only in processor systems where no debug port is implemented on the system board. DBR# is used by a debug port interposer so that an in-target probe can drive system reset. If a debug port is implemented in the system, DBR# is a no connect in the system. DBR# is not a processor signal.
DBSY# (Data Bus Busy) is asserted by the agent responsible for driving data on the processor FSB to indicate that the data bus is in use. The data bus is released after DBSY# is de-asserted. This signal must connect the appropriate pins/lands on all processor FSB agents.
70 Datasheet
Land Listing and Signal Descriptions
Table 25.
Signal Description (Sheet 1 of 9)
Name
DEFER#
DRDY#
Type
Input
Input/
Output
Description
DEFER# is asserted by an agent to indicate that a transaction cannot be ensured in-order completion. Assertion of DEFER# is normally the responsibility of the addressed memory or input/ output agent. This signal must connect the appropriate pins/lands of all processor FSB agents.
DRDY# (Data Ready) is asserted by the data driver on each data transfer, indicating valid data on the data bus. In a multi-common clock data transfer, DRDY# may be de-asserted to insert idle clocks.
This signal must connect the appropriate pins/lands of all processor
FSB agents.
DSTBN[3:0]# are the data strobes used to latch in D[63:0]#.
DSTBN[3:0]#
Input/
Output
Signals
D[15:0]#, DBI0#
D[31:16]#, DBI1#
D[47:32]#, DBI2#
D[63:48]#, DBI3#
Associated Strobe
DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP[3:0]#
FCx
FERR#/PBE#
GTLREF[1:0]
Input/
Output
DSTBP[3:0]# are the data strobes used to latch in D[63:0]#.
Signals
D[15:0]#, DBI0#
D[31:16]#, DBI1#
D[47:32]#, DBI2#
D[63:48]#, DBI3#
Associated Strobe
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#
Other
Output
Input
FC signals are signals that are available for compatibility with other processors.
FERR#/PBE# (floating point error/pending break event) is a multiplexed signal and its meaning is qualified by STPCLK#. When
STPCLK# is not asserted, FERR#/PBE# indicates a floating-point error and will be asserted when the processor detects an unmasked floating-point error. When STPCLK# is not asserted, FERR#/PBE# is similar to the ERROR# signal on the Intel 387 coprocessor, and is included for compatibility with systems using MS-DOS*-type floating-point error reporting. When STPCLK# is asserted, an assertion of FERR#/PBE# indicates that the processor has a pending break event waiting for service. The assertion of FERR#/
PBE# indicates that the processor should be returned to the Normal state. For additional information on the pending break event functionality, including the identification of support of the feature and enable/disable information, refer to volume 3 of the Intel
Architecture Software Developer's Manual and the Intel Processor
Identification and the CPUID Instruction application note.
GTLREF[1:0] determine the signal reference level for GTL+ input signals. GTLREF is used by the GTL+ receivers to determine if a signal is a logical 0 or logical 1.
Datasheet 71
Land Listing and Signal Descriptions
Table 25.
Signal Description (Sheet 1 of 9)
HIT#
Name
HITM#
Type
Input/
Output
Input/
Output
Description
HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation results. Any FSB agent may assert both HIT# and
HITM# together to indicate that it requires a snoop stall, which can be continued by reasserting HIT# and HITM# together.
IERR#
IGNNE#
INIT#
ITP_CLK[1:0]
LINT[1:0]
Output
Input
Input
Input
Input
IERR# (Internal Error) is asserted by a processor as the result of an internal error. Assertion of IERR# is usually accompanied by a
SHUTDOWN transaction on the processor FSB. This transaction may optionally be converted to an external error signal (e.g., NMI) by system core logic. The processor will keep IERR# asserted until the assertion of RESET#.
This signal does not have on-die termination. Refer to
for termination requirements.
IGNNE# (Ignore Numeric Error) is asserted to the processor to ignore a numeric error and continue to execute noncontrol floatingpoint instructions. If IGNNE# is de-asserted, the processor generates an exception on a noncontrol floating-point instruction if a previous floating-point instruction caused an error. IGNNE# has no effect when the NE bit in control register 0 (CR0) is set.
IGNNE# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/
Output Write bus transaction.
INIT# (Initialization), when asserted, resets integer registers inside the processor without affecting its internal caches or floating-point registers. The processor then begins execution at the power-on
Reset vector configured during power-on configuration. The processor continues to handle snoop requests during INIT# assertion. INIT# is an asynchronous signal and must connect the appropriate pins/lands of all processor FSB agents.
ITP_CLK[1:0] are copies of BCLK that are used only in processor systems where no debug port is implemented on the system board.
ITP_CLK[1:0] are used as BCLK[1:0] references for a debug port implemented on an interposer. If a debug port is implemented in the system, ITP_CLK[1:0] are no connects in the system. These are not processor signals.
LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins/lands of all APIC Bus agents. When the APIC is disabled, the
LINT0 signal becomes INTR, a maskable interrupt request signal, and LINT1 becomes NMI, a nonmaskable interrupt. INTR and NMI are backward compatible with the signals of those names on the
Pentium processor. Both signals are asynchronous.
Both of these signals must be software configured via BIOS programming of the APIC register space to be used either as NMI/
INTR or LINT[1:0]. Because the APIC is enabled by default after
Reset, operation of these signals as LINT[1:0] is the default configuration.
72 Datasheet
Land Listing and Signal Descriptions
Table 25.
Signal Description (Sheet 1 of 9)
LOCK#
MSID[1:0]
PECI
Name
PROCHOT#
PWRGOOD
REQ[4:0]#
RESET#
Type
Input/
Output
Output
Input/
Output
Input/
Output
Input
Input/
Output
Input
Description
LOCK# indicates to the system that a transaction must occur atomically. This signal must connect the appropriate pins/lands of all processor FSB agents. For a locked sequence of transactions,
LOCK# is asserted from the beginning of the first transaction to the end of the last transaction.
When the priority agent asserts BPRI# to arbitrate for ownership of the processor FSB, it will wait until it observes LOCK# de-asserted.
This enables symmetric agents to retain ownership of the processor
FSB throughout the bus locked operation and ensure the atomicity of lock.
These signals indicate the Market Segment for the processor. Refer to
Table 3 for additional information.
PECI is a proprietary one-wire bus interface. See Section 5.4
for details.
As an output, PROCHOT# (Processor Hot) will go active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature. This indicates that the processor Thermal Control Circuit (TCC) has been activated, if enabled. As an input, assertion of PROCHOT# by the system will activate the TCC, if enabled. The TCC will remain active
until the system de-asserts PROCHOT#. See Section 5.2.4
details.
PWRGOOD (Power Good) is a processor input. The processor requires this signal to be a clean indication that the clocks and power supplies are stable and within their specifications. ‘Clean’ implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification. The signal must then transition monotonically to a high state. PWRGOOD can be driven inactive at any time, but clocks and power must again be stable before a subsequent rising edge of PWRGOOD.
The PWRGOOD signal must be supplied to the processor; it is used to protect internal circuits against voltage sequencing issues. It should be driven high throughout boundary scan operation.
REQ[4:0]# (Request Command) must connect the appropriate pins/ lands of all processor FSB agents. They are asserted by the current bus owner to define the currently active transaction type. These signals are source synchronous to ADSTB0#.
Asserting the RESET# signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents. For a power-on Reset, RESET# must stay active for at least one millisecond after V
CC
and BCLK have reached their proper specifications. On observing active RESET#, all FSB agents will deassert their outputs within two clocks. RESET# must not be kept asserted for more than 10 ms while PWRGOOD is asserted.
A number of bus signals are sampled at the active-to-inactive transition of RESET# for power-on configuration. These
configuration options are described in the Section 6.1
.
This signal does not have on-die termination and must be terminated on the system board.
Datasheet 73
Land Listing and Signal Descriptions
Table 25.
Signal Description (Sheet 1 of 9)
SMI#
TCK
TDI
TDO
Name
RESERVED
RS[2:0]#
SKTOCC#
STPCLK#
TESTHI[13:0]
THERMDA
THERMDC
Type Description
Input
Output
Input
Input
All RESERVED lands must remain unconnected. Connection of these lands to V
CC processors.
, V
SS
, V
TT
, or to any other signal (including each other) can result in component malfunction or incompatibility with future
RS[2:0]# (Response Status) are driven by the response agent (the agent responsible for completion of the current transaction), and must connect the appropriate pins/lands of all processor FSB agents.
SKTOCC# (Socket Occupied) will be pulled to ground by the processor. System board designers may use this signal to determine if the processor is present.
SMI# (System Management Interrupt) is asserted asynchronously by system logic. On accepting a System Management Interrupt, the processor saves the current state and enter System Management
Mode (SMM). An SMI Acknowledge transaction is issued, and the processor begins program execution from the SMM handler.
If SMI# is asserted during the de-assertion of RESET#, the processor will tri-state its outputs.
STPCLK# (Stop Clock), when asserted, causes the processor to enter a low power Stop-Grant state. The processor issues a Stop-
Grant Acknowledge transaction, and stops providing internal clock signals to all processor core units except the FSB and APIC units.
The processor continues to snoop bus transactions and service interrupts while in Stop-Grant state. When STPCLK# is de-asserted, the processor restarts its internal clock to all units and resumes execution. The assertion of STPCLK# has no effect on the bus clock;
STPCLK# is an asynchronous input.
Input
Input
Output
Input
TCK (Test Clock) provides the clock input for the processor Test Bus
(also known as the Test Access Port).
TDI (Test Data In) transfers serial test data into the processor. TDI provides the serial input needed for JTAG specification support.
TDO (Test Data Out) transfers serial test data out of the processor.
TDO provides the serial output needed for JTAG specification support.
TESTHI[13:0] must be connected to the processor’s appropriate power source (refer to VTT_OUT_LEFT and VTT_OUT_RIGHT signal description) through a resistor for proper processor operation. See
for more details.
Other
Thermal Diode Anode. See Section 5.3
.
Other
Thermal Diode Cathode. See Section 5.3
.
74 Datasheet
Land Listing and Signal Descriptions
Table 25.
Signal Description (Sheet 1 of 9)
Name
THERMTRIP#
TMS
TRDY#
TRST#
VCC
VCCPLL
VCC_SENSE
VCC_MB_
REGULATION
VID[7:0]
VID_SELECT
Type Description
Output
Input
Input
Output
Output
In the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached a temperature approximately 20 °C above the maximum T
C
.
Assertion of THERMTRIP# (Thermal Trip) indicates the processor junction temperature has reached a level beyond where permanent silicon damage may occur. Upon assertion of THERMTRIP#, the processor will shut off its internal clocks (thus, halting program execution) in an attempt to reduce the processor junction temperature. To protect the processor, its core voltage (V be removed following the assertion of THERMTRIP#. Driving of the
THERMTRIP# signal is enabled within 10 μs of the assertion of
PWRGOOD (provided V
TT
and V assertion of PWRGOOD (if V
TT
CC
CC
) must
are valid) and is disabled on de-
or V
CC
are not valid, THERMTRIP# may also be disabled). Once activated, THERMTRIP# remains latched until PWRGOOD, V
TT
, or V assertion of the PWRGOOD, V
TT
CC
is de-asserted. While the de-
, or V
CC
will de-assert THERMTRIP#, if the processor’s junction temperature remains at or above the trip level, THERMTRIP# will again be asserted within 10 μs of the assertion of PWRGOOD (provided V
TT
and V
CC
are valid).
TMS (Test Mode Select) is a JTAG specification support signal used by debug tools.
TRDY# (Target Ready) is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer. TRDY# must connect the appropriate pins/lands of all FSB agents.
Input
Input
TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven low during power on Reset.
VCC are the power pins for the processor. The voltage supplied to these pins is determined by the VID[7:0] pins.
Input VCCPLL provides isolated power for internal processor FSB PLLs.
Output
Output
VCC_SENSE is an isolated low impedance connection to processor core power (V
CC
). It can be used to sense or measure voltage near the silicon with little noise.
This land is provided as a voltage regulator feedback sense point for
V
CC
. It is connected internally in the processor package to the sense point land U27 as described in the Voltage Regulator-Down (VRD)
11.0 Processor Power Delivery Design Guidelines For Desktop
LGA775 Socket.
VID[7:0] (Voltage ID) signals are used to support automatic selection of power supply voltages (V
CC
). Refer to the Voltage
Regulator-Down (VRD) 11.0 Processor Power Delivery Design
Guidelines For Desktop LGA775 Socket for more information. The voltage supply for these signals must be valid before the VR can supply V
CC
to the processor. Conversely, the VR output must be disabled until the voltage supply for the VID signals becomes valid.
The VID signals are needed to support the processor voltage
specification variations. See Table 2
for definitions of these signals.
The VR must supply the voltage that is requested by the signals, or disable itself.
This land is tied high on the processor package and is used by the
VR to choose the proper VID table. Refer to the Voltage Regulator-
Down (VRD) 11.0 Processor Power Delivery Design Guidelines For
Desktop LGA775 Socket for more information.
Datasheet 75
Land Listing and Signal Descriptions
Table 25.
Signal Description (Sheet 1 of 9)
Name
VRDSEL
VSS
VSSA
VSS_SENSE
VSS_MB_
REGULATION
VTT
VTT_OUT_LEFT
VTT_OUT_RIGHT
VTT_SEL
Type Description
Input
Input
This input should be left as a no connect in order for the processor to boot. The processor will not boot on legacy platforms where this land is connected to V
SS
.
VSS are the ground pins for the processor and should be connected to the system ground plane.
Input VSSA is the isolated ground for internal PLLs.
Output
VSS_SENSE is an isolated low impedance connection to processor core V
SS
. It can be used to sense or measure ground near the silicon with little noise.
Output
This land is provided as a voltage regulator feedback sense point for
V
SS
. It is connected internally in the processor package to the sense point land V27 as described in the Voltage Regulator-Down (VRD)
11.0 Processor Power Delivery Design Guidelines For Desktop
LGA775 Socket.
Input Miscellaneous voltage supply.
Output
Output
The VTT_OUT_LEFT and VTT_OUT_RIGHT signals are included to provide a voltage supply for some signals that require termination to V
TT
on the motherboard.
The VTT_SEL signal is used to select the correct V
V
TT
.
TT
voltage level for the processor. This land is connected internally in the package to
§ §
76 Datasheet
Thermal Specifications and Design Considerations
5
5.1
Note:
5.1.1
Datasheet
Thermal Specifications and
Design Considerations
Processor Thermal Specifications
The processor requires a thermal solution to maintain temperatures within the
operating limits as described in Section 5.1.1
. Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system. As processor technology changes, thermal management becomes increasingly crucial when building computer systems.
Maintaining the proper thermal environment is key to reliable, long-term system operation.
A complete thermal solution includes both component and system level thermal management features. Component level thermal solutions can include active or passive heatsinks attached to the processor Integrated Heat Spreader (IHS). Typical system level thermal solutions may consist of system fans combined with ducting and venting.
For more information on designing a component level thermal solution, refer to the
appropriate Thermal and Mechanical Design Guidelines (see Section 1.2
The boxed processor will ship with a component thermal solution. Refer to Chapter 7
for details on the boxed processor.
Thermal Specifications
To allow for the optimal operation and long-term reliability of Intel processor-based systems, the system/processor thermal solution should be designed such that the processor remains within the minimum and maximum case temperature (T
C
) specifications when operating at or below the Thermal Design Power (TDP) value listed
. Thermal solutions not designed to provide this level of thermal capability may affect the long-term reliability of the processor and system. For more details on thermal solution design, refer to the appropriate Thermal and
Mechanical Design Guidelines (see Section 1.2
The processor uses a methodology for managing processor temperatures which is intended to support acoustic noise reduction through fan speed control. Selection of the appropriate fan speed is based on the relative temperature data reported by the processor’s Platform Environment Control Interface (PECI) bus as described in
. The temperature reported over PECI is always a negative value and represents a delta below the onset of thermal control circuit (TCC) activation, as
indicated by PROCHOT# (see Section 5.2
). Systems that implement fan speed control must be designed to take these conditions in to account. Systems that do not alter the fan speed only need to ensure the case temperature meets the thermal profile specifications.
To determine a processor's case temperature specification based on the thermal profile, it is necessary to accurately measure processor power dissipation. Intel has developed a methodology for accurate power measurement that correlates to Intel test temperature and voltage conditions. Refer to the appropriate Thermal and Mechanical
Design Guidelines (see Section 1.2
) and the Processor Power Characterization
Methodology for the details of this methodology.
The case temperature is defined at the geometric top center of the processor. Analysis indicates that real applications are unlikely to cause the processor to consume maximum power dissipation for sustained time periods. Intel recommends that
77
Thermal Specifications and Design Considerations complete thermal solution designs target the Thermal Design Power (TDP) indicated in
instead of the maximum processor power consumption. The Thermal Monitor feature is designed to protect the processor in the unlikely event that an application exceeds the TDP recommendation for a sustained periods of time. For more details on
the usage of this feature, refer to Section 5.2
. In all cases the Thermal Monitor and
Thermal Monitor 2 feature must be enabled for the processor to remain within specification.
Table 26.
Processor Thermal Specifications
Processor
Number
Core
Frequency
(GHz)
Thermal
Design
Power (W) 1,2
Extended
HALT
Power (W) 3
775_VR_
CONFIG_05B/
06 Guidance 4
Minimum
T
C
(°C)
Maximum T
(°C)
C Notes
E4700
E4600
E4500
E4400
E6400
E6400
E6300
E6300
E4400
E4300
E6850
E6750
E6550
E6540
E6700
E6600
E6420
E6320
2.40
2.40
2.20
2.00
2.13
2.13
1.86
1.86
2.00
1.80
3.00
2.66
2.33
2.33
2.66
2.40
2.13
1.86
65.0
65.0
65.0
65.0
65.0
65.0
65.0
65.0
65.0
65.0
65.0
65.0
65.0
65.0
65.0
65.0
65.0
65.0
12.0
22.0
12.0
22.0
8.0
8.0
8.0
8.0
12.0
12.0
8.0
8.0
8.0
8.0
22.0/12.0
22.0/12.0
12.0
12.0
775_VR_CONFIG
_06
775_VR_CONFIG
_06
775_VR_CONFIG
_06
775_VR_CONFIG
_06
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
Thermal
Profile 1
Thermal
Profile 2
)
Thermal
Profile 3
Thermal
Profile 4
)
)
)
5,6
5 , 6
5 , 6
5 , 6
7,8
7 , 8
7 , 8
7 , 8
5 , 6
5 ,9
5 , 9
5 , 9
7 , 10
7 , 8
7 , 10
7 , 8
7 , 10
7 , 10
X6800 2.93
75.0
22.0
775_VR_CONFIG
_05B
5
Thermal
Profile 5
)
7 , 8
NOTES:
1. Thermal Design Power (TDP) should be used for processor thermal solution design targets. The TDP is not the maximum power that the processor can dissipate.
2.
This table shows the maximum TDP for a given frequency range. Individual processors may have a lower TDP.
Therefore, the maximum T
C
will vary depending on the TDP of the individual processor. Refer to thermal profile figure and associated table for the allowed combinations of power and T .
3. Refer to the “Component Identification Information” section of the Intel ® Core™2 Extreme and Intel ® Core™2 Duo Desktop
Processor Specification Update for processor specific Idle power.
4. 775_VR_CONFIG_06/775_VR_CONFIG_05B guidelines provide a design target for meeting future thermal requirements.
5. Specification is at 35 °C T
C
and typical voltage loadline.
6. These processors have CPUID = 06FBh.
7. Specification is at 50 °C T
C
and typical voltage loadline.
8. These processors have CPUID = 06F6h.
9. These processors have CPUID = 06FDh.
10.These processors have CPUID = 06F2h.
78 Datasheet
Thermal Specifications and Design Considerations
Table 27.
Thermal Profile 1
Power
(W)
6
8
10
12
0
2
4
14
16
18
20
22
Maximum
Tc (°C)
44.7
45.5
46.4
47.2
48.1
48.9
49.7
50.6
51.4
52.3
53.1
53.9
Power
(W)
30
32
34
36
24
26
28
38
40
42
44
46
Maximum
Tc (°C)
54.8
55.6
56.5
57.3
58.1
59.0
59.8
60.7
61.5
62.3
63.2
64.0
Power
(W)
54
56
58
60
48
50
52
62
64
65
Maximum
Tc (°C)
64.9
65.7
66.5
67.4
68.2
69.1
69.9
70.7
71.6
72.0
NOTE: For the Intel ® Core™2 Duo Desktop processor E6x50 series with 4 MB L2 Cache and
CPUID = 06FBh, and Intel and CPUID = 06FBh.
® Core™2 Duo Desktop processor E6540 with 4 MB L2 Cache
Figure 19.
Thermal Profile 1
Datasheet
NOTE: For the Intel ® Core™2 Duo Desktop processor E6x50 series with 4 MB L2 Cache and
CPUID = 06FBh, and Intel ® Core™2 Duo Desktop processorr E6540 with 4 MB L2 Cache and CPUID = 06FBh.
79
Thermal Specifications and Design Considerations
Table 28.
Thermal Profile 2
Power
(W)
8
10
12
14
4
6
0
2
16
18
20
22
Maximum
Tc (°C)
43.2
43.7
44.2
44.8
45.3
45.8
46.3
46.8
47.4
47.9
48.4
48.9
Power
(W)
32
34
36
38
24
26
28
30
40
42
44
46
Maximum
Tc (°C)
49.4
50.0
50.5
51.0
51.5
52.0
52.6
53.1
53.6
54.1
54.6
55.2
Power
(W)
56
58
60
62
48
50
52
54
64
65
Maximum
Tc (°C)
55.7
56.2
56.7
57.2
57.8
58.3
58.8
59.3
59.8
60.1
NOTE: For the Intel ® Core™2 Duo Desktop processor E6000 series with 4 MB L2 Cache and
CPUID = 06F6h.
Figure 20.
Thermal Profile 2
65.0
80
60.0
55.0
50.0
45.0
y = 0.26x + 43.2
40.0
0 10 20 30
Power (W)
40 50 60
NOTE: For the Intel
®
Core™2 Duo Desktop processor E6000 series with 4 MB L2 Cache and
CPUID = 06F6h.
Datasheet
Thermal Specifications and Design Considerations
Table 29.
Thermal Profile 3
Power
(W)
8
10
12
14
4
6
0
2
16
18
20
22
Maximum
Tc (°C)
45.3
46.2
47.0
47.9
48.7
49.6
50.5
51.3
52.2
53.0
53.9
54.8
Power
(W)
32
34
36
38
24
26
28
30
40
42
44
46
Maximum
Tc (°C)
55.6
56.5
57.3
58.2
59.1
59.9
60.8
61.6
62.5
63.4
64.2
65.1
Power
(W)
56
58
60
62
48
50
52
54
64
65
Maximum
Tc (°C)
65.9
66.8
67.7
68.5
69.4
70.2
71.1
72.0
72.8
73.3
NOTE: For the Intel
®
Core™2 Duo Desktop processor E4000 series with 2 MB L2 Cache and
CPUID = 06FDh, and for the Intel
Cache and CPUID = 06FBh.
® Core™2 Duo Desktop processor E4700 with 2 MB L2
Figure 21.
Thermal Profile 3
Datasheet
NOTE: For the Intel ® Core™2 Duo Desktop processor E4000 series with 2 MB L2 Cache and
CPUID = 06FDh, and for the Intel
Cache and CPUID = 06FBh.
® Core™2 Duo Desktop processor E4700 with 2 MB L2
81
Thermal Specifications and Design Considerations
Table 30.
Thermal Profile 4
Power
(W)
6
8
10
12
0
2
4
14
16
18
20
22
Maximum
Tc (°C)
43.2
43.8
44.3
44.9
45.4
46.0
46.6
47.1
47.7
48.2
48.8
49.4
Power
(W)
30
32
34
36
24
26
28
38
40
42
44
46
Maximum
Tc (°C)
49.9
50.5
51.0
51.6
52.2
52.7
53.3
53.8
54.4
55.0
55.5
56.1
Power
(W)
54
56
58
60
48
50
52
62
64
65
Maximum
Tc (°C)
56.6
57.2
57.8
58.3
58.9
59.4
60.0
60.6
61.1
61.4
NOTE: For the Intel ® Core™2 Duo Desktop processor E6000 and E4000 series with 2 MB L2
Cache and CPUID = 06F2h, and for the Intel ® Core™2 Duo Desktop processor E6000 series with 2 MB L2 Cache and CPUID = 06F6h.
Figure 22.
Thermal Profile 4
65.0
60.0
55.0
50.0
y = 0.28x + 43.2
45.0
40.0
0 10 20 30
Power (W)
40 50 60
NOTE: For the Intel ® Core™2 Duo Desktop processor E6000 and E4000 series with 2 MB L2
Cache and CPUID = 06F2h, and for the Intel ® Core™2 Duo Desktop processor E6000 series with 2 MB L2 Cache and CPUID = 06F6h.
82 Datasheet
Thermal Specifications and Design Considerations
Table 31.
Thermal Profile 5
Power
(W)
8
10
12
14
4
6
0
2
16
18
20
22
24
Maximum
Tc (°C)
43.2
43.7
44.1
44.6
45.0
45.5
46.0
46.4
46.9
47.3
47.8
48.3
48.7
Power
(W)
34
36
38
40
26
28
30
32
42
44
46
48
50
Maximum
Tc (°C)
49.2
49.6
50.1
50.6
51.0
51.5
51.9
52.4
52.9
53.3
53.8
54.2
54.7
NOTE: For the Intel ® Core™2 Extreme processor X6800.
Figure 23.
Thermal Profile 5
65.0
Power
(W)
60
62
64
66
52
54
56
58
68
70
72
74
75
Maximum
Tc (°C)
55.2
55.6
56.1
56.5
57.0
57.5
57.9
58.2
58.8
59.3
59.8
60.2
60.4
60.0
55.0
50.0
y = 0.23x + 43.2
45.0
40.0
0 10 20 30 40
Po w er (W )
NOTE: For the Intel ® Core™2 Extreme processor X6800.
50 60 70
Datasheet 83
Thermal Specifications and Design Considerations
5.1.2
Thermal Metrology
The maximum and minimum case temperatures (T
C
) for the processor is specified in
. This temperature specification is meant to help ensure proper operation of
the processor. Figure 24 illustrates where Intel recommends T
C
thermal measurements should be made. For detailed guidelines on temperature measurement methodology, refer to the appropriate Thermal and Mechanical Design Guidelines (see
Figure 24.
Case Temperature (T
C
) Measurement Location
Measure T at this point
(geometric center of the package)
5.2
5.2.1
Processor Thermal Features
Thermal Monitor
The Thermal Monitor feature helps control the processor temperature by activating the thermal control circuit (TCC) when the processor silicon reaches its maximum operating temperature. The TCC reduces processor power consumption by modulating (starting and stopping) the internal processor core clocks. The Thermal Monitor feature must
be enabled for the processor to be operating within specifications. The temperature at which Thermal Monitor activates the thermal control circuit is not user configurable and is not software visible. Bus traffic is snooped in the normal manner, and interrupt requests are latched (and serviced during the time that the clocks are on) while the TCC is active.
When the Thermal Monitor feature is enabled, and a high temperature situation exists
(i.e., TCC is active), the clocks will be modulated by alternately turning the clocks off and on at a duty cycle specific to the processor (typically 30–50%). Clocks often will not be off for more than 3.0 microseconds when the TCC is active. Cycle times are processor speed dependent and will decrease as processor core frequencies increase. A small amount of hysteresis has been included to prevent rapid active/inactive transitions of the TCC when the processor temperature is near its maximum operating temperature. Once the temperature has dropped below the maximum operating temperature, and the hysteresis timer has expired, the TCC goes inactive and clock modulation ceases.
With a properly designed and characterized thermal solution, it is anticipated that the
TCC would only be activated for very short periods of time when running the most power intensive applications. The processor performance impact due to these brief periods of TCC activation is expected to be so minor that it would be immeasurable. An under-designed thermal solution that is not able to prevent excessive activation of the
TCC in the anticipated ambient environment may cause a noticeable performance loss,
84 Datasheet
Thermal Specifications and Design Considerations
5.2.2
and in some cases may result in a T
C
that exceeds the specified maximum temperature and may affect the long-term reliability of the processor. In addition, a thermal solution that is significantly under-designed may not be capable of cooling the processor even when the TCC is active continuously. Refer to the appropriate Thermal and Mechanical
Design Guidelines (see Section 1.2
) for information on designing a thermal solution.
The duty cycle for the TCC, when activated by the Thermal Monitor, is factory configured and cannot be modified. The Thermal Monitor does not require any additional hardware, software drivers, or interrupt handling routines.
Thermal Monitor 2
The processor also supports an additional power reduction capability known as Thermal
Monitor 2. This mechanism provides an efficient means for limiting the processor temperature by reducing the power consumption within the processor.
When Thermal Monitor 2 is enabled, and a high temperature situation is detected, the
Thermal Control Circuit (TCC) will be activated. The TCC causes the processor to adjust its operating frequency (via the bus multiplier) and input voltage (via the VID signals).
This combination of reduced frequency and VID results in a reduction to the processor power consumption.
A processor enabled for Thermal Monitor 2 includes two operating points, each consisting of a specific operating frequency and voltage. The first operating point represents the normal operating condition for the processor. Under this condition, the core-frequency-to-FSB multiple used by the processor is that contained in the appropriate MSR and the VID is that specified in
. These parameters represent normal system operation.
The second operating point consists of both a lower operating frequency and voltage.
When the TCC is activated, the processor automatically transitions to the new frequency. This transition occurs very rapidly (on the order of 5 μs). During the frequency transition, the processor is unable to service any bus requests, and consequently, all bus traffic is blocked. Edge-triggered interrupts will be latched and kept pending until the processor resumes operation at the new frequency.
Once the new operating frequency is engaged, the processor will transition to the new core operating voltage by issuing a new VID code to the voltage regulator. The voltage regulator must support dynamic VID steps to support Thermal Monitor 2. During the voltage change, it will be necessary to transition through multiple VID codes to reach
the target operating voltage. Each step will likely be one VID table entry (see Table 5
).
The processor continues to execute instructions during the voltage transition.
Operation at the lower voltage reduces the power consumption of the processor.
A small amount of hysteresis has been included to prevent rapid active/inactive transitions of the TCC when the processor temperature is near its maximum operating temperature. Once the temperature has dropped below the maximum operating temperature, and the hysteresis timer has expired, the operating frequency and voltage transition back to the normal system operating point. Transition of the VID code will occur first, to insure proper operation once the processor reaches its normal
operating frequency. Refer to Figure 25 for an illustration of this ordering.
Datasheet 85
Thermal Specifications and Design Considerations
Figure 25.
Thermal Monitor 2 Frequency and Voltage Ordering
T
TM2
f
MAX
f
TM2
VID
VID
TM2
Temperature
Frequency
VID
5.2.3
PROCHOT#
The PROCHOT# signal is asserted when a high temperature situation is detected, regardless of whether Thermal Monitor or Thermal Monitor 2 is enabled.
It should be noted that the Thermal Monitor 2 TCC cannot be activated via the on demand mode. The Thermal Monitor TCC, however, can be activated through the use of the on demand mode.
On-Demand Mode
The processor provides an auxiliary mechanism that allows system software to force the processor to reduce its power consumption. This mechanism is referred to as “On-
Demand” mode and is distinct from the Thermal Monitor feature. On-Demand mode is intended as a means to reduce system level power consumption. Systems using the processor must not rely on software usage of this mechanism to limit the processor temperature.
The processor provides an auxiliary mechanism that allows system software to force the processor to reduce its power consumption. This mechanism is referred to as “On-
Demand” mode and is distinct from the Thermal Monitor and Thermal Monitor 2 features. On-Demand mode is intended as a means to reduce system level power consumption. Systems must not rely on software usage of this mechanism to limit the processor temperature. If bit 4 of the IA32_CLOCK_MODULATION MSR is set to a 1, the processor will immediately reduce its power consumption via modulation (starting and stopping) of the internal core clock, independent of the processor temperature. When using On-Demand mode, the duty cycle of the clock modulation is programmable via bits 3:1 of the same IA32_CLOCK_MODULATION MSR. In On-Demand mode, the duty cycle can be programmed from 12.5% on/ 87.5% off to 87.5% on/ 12.5% off in 12.5% increments. On-Demand mode may be used in conjunction with the Thermal Monitor; however, if the system tries to enable On-Demand mode at the same time the TCC is engaged, the factory configured duty cycle of the TCC will override the duty cycle selected by the On-Demand mode.
86 Datasheet
Thermal Specifications and Design Considerations
5.2.4
5.2.5
PROCHOT# Signal
An external signal, PROCHOT# (processor hot), is asserted when the processor core temperature has reached its maximum operating temperature. If the Thermal Monitor is enabled (note that the Thermal Monitor must be enabled for the processor to be operating within specification), the TCC will be active when PROCHOT# is asserted. The processor can be configured to generate an interrupt upon the assertion or deassertion of PROCHOT#.
As an output, PROCHOT# (Processor Hot) will go active when the processor temperature monitoring sensor detects that one or both cores has reached its maximum safe operating temperature. This indicates that the processor Thermal
Control Circuit (TCC) has been activated, if enabled. As an input, assertion of
PROCHOT# by the system will activate the TCC, if enabled, for both cores. The TCC will remain active until the system de-asserts PROCHOT#.
PROCHOT# allows for some protection of various components from over-temperature situations. The PROCHOT# signal is bi-directional in that it can either signal when the processor (either core) has reached its maximum operating temperature or be driven from an external source to activate the TCC. The ability to activate the TCC via
PROCHOT# can provide a means for thermal protection of system components.
PROCHOT# can allow VR thermal designs to target maximum sustained current instead of maximum current. Systems should still provide proper cooling for the VR, and rely on PROCHOT# only as a backup in case of system cooling failure. The system thermal design should allow the power delivery circuitry to operate within its temperature specification even while the processor is operating at its Thermal Design Power. With a properly designed and characterized thermal solution, it is anticipated that PROCHOT# would only be asserted for very short periods of time when running the most power intensive applications. An under-designed thermal solution that is not able to prevent excessive assertion of PROCHOT# in the anticipated ambient environment may cause a noticeable performance loss. Refer to the Voltage Regulator-Down (VRD) 11.0
Processor Power Delivery Design Guidelines For Desktop LGA775 Socket for details on implementing the bi-directional PROCHOT# feature.
THERMTRIP# Signal
Regardless of whether or not Thermal Monitor or Thermal Monitor 2 is enabled, in the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached an elevated temperature (refer to the THERMTRIP# definition in
). At this point, the FSB signal THERMTRIP# will go active and stay active as described in
Table 25 . THERMTRIP# activation is independent of processor activity and
does not generate any bus cycles.
Datasheet 87
Thermal Specifications and Design Considerations
5.3
Table 32.
Thermal Diode
The processor incorporates an on-die PNP transistor where the base emitter junction is used as a thermal "diode", with its collector shorted to ground. A thermal sensor located on the system board may monitor the die temperature of the processor for thermal management and fan speed control.
, and
the "diode" parameter and interface specifications. Two different sets of "diode"
parameters are listed in Table 32
and
Table 33 . The Diode Model parameters (
apply to traditional thermal sensors that use the Diode Equation to determine the
processor temperature. Transistor Model parameters ( Table 33 ) have been added to
support thermal sensors that use the transistor equation method. The Transistor Model may provide more accurate temperature measurements when the diode ideality factor is closer to the maximum or minimum limits. This thermal "diode" is separate from the
Thermal Monitor's thermal sensor and cannot be used to predict the behavior of the
Thermal Monitor.
T
CONTROL
is a temperature specification based on a temperature reading from the thermal diode. The value for T configured for each processor. When T
will be calibrated in manufacturing and
DIODE
is above T
CONTROL
, then T
C below T temperature can be maintained at T diode.
C_MAX
as defined by the thermal profile in Table 28
; otherwise, the processor
CONTROL
must be at or
(or lower) as measured by the thermal
Thermal “Diode” Parameters using Diode Model
Symbol
I
FW n
R
T
Parameter
Forward Bias Current
Diode Ideality Factor
Series Resistance
Min
5
1.000
2.79
Typ
—
1.009
4.52
Max
200
1.050
6.24
Unit
µA
-
Ω
Notes
1
2, 3, 4
2, 3, 5
NOTES:
1.
Intel does not support or recommend operation of the thermal diode under reverse bias.
2.
3.
4.
Characterized across a temperature range of 50 – 80 °C.
Not 100% tested. Specified by design characterization.
The ideality factor, n, represents the deviation from ideal diode behavior as exemplified by the diode equation:
5.
where I k = Boltzmann Constant, and T = absolute temperature (Kelvin).
The series resistance, R
T junction temperature. R
T
I
FW
= I
S
* (e qV
D
/nkT –1)
= saturation current, q = electronic charge, V
D
= voltage across the diode,
, is provided to allow for a more accurate measurement of the
, as defined, includes the lands of the processor but does not include any socket resistance or board trace resistance between the socket and the external remote diode thermal sensor. R
T
can be used by remote diode thermal sensors with automatic series resistance cancellation to calibrate out this error term. Another application is that a temperature offset can be manually calculated and programmed into an offset register in the remote diode thermal sensors as exemplified by the equation: where T error
T error
= [R
T
* (N–1) * I
FWmin
] / [nk/q * ln N]
= sensor temperature error, N = sensor current ratio, k = Boltzmann
Constant, q = electronic charge.
88 Datasheet
Thermal Specifications and Design Considerations
Table 33.
Table 34.
Thermal “Diode” Parameters using Transistor Model
Symbol
I
FW
I
E n
Q
Beta
R
T
Parameter
Forward Bias Current
Emitter Current
Transistor Ideality
Series Resistance
Min
5
5
0.997
0.391
2.79
Typ
—
—
1.001
—
4.52
Max
200
200
1.005
0.760
6.24
Unit
µA
µA
-
Ω
Notes
1, 2
3, 4, 5
3, 4
3, 6
2.
3.
4.
5.
NOTES:
1.
Intel does not support or recommend operation of the thermal diode under reverse bias.
Same as I
FW
Characterized across a temperature range of 50–80 °C.
Not 100% tested. Specified by design characterization.
The ideality factor, nQ, represents the deviation from ideal transistor model behavior as exemplified by the equation for the collector current:
6.
Where I
S temperature (Kelvin).
The series resistance, R
T,
I
C
= I
S
* (e qV
BE
/n
Q kT –1)
= saturation current, q = electronic charge, V
BE
provided in the Diode Model Table ( Table 32 ) can be used for
more accurate readings as needed.
= voltage across the transistor base emitter junction (same nodes as VD), k = Boltzmann Constant, and T = absolute
The processor does not support the diode correction offset that exists on other Intel processors
Thermal Diode Interface
Signal Name
THERMDA
THERMDC
Land Number
AL1
AK1
Signal
Description diode anode diode cathode
Datasheet 89
Thermal Specifications and Design Considerations
5.4
Platform Environment Control Interface (PECI)
5.4.1
Introduction
PECI offers an interface for thermal monitoring of Intel processor and chipset components. It uses a single wire, thus alleviating routing congestion issues.
shows an example of the PECI topology in a system. PECI uses CRC checking on the host side to ensure reliable transfers between the host and client devices. Also, data transfer speeds across the PECI interface are negotiable within a wide range (2 Kbps to
2 Mbps). The PECI interface on the processor is disabled by default and must be enabled through BIOS.
Figure 26.
Processor PECI Topology
PECI Host
Controller
Land G5
Domain 0
5.4.1.1
Key Difference with Legacy Diode-Based Thermal Management
Fan speed control solutions based on PECI uses a T
CONTROL processor IA32_TEMPERATURE_TARGET MSR. The T
value stored in the
CONTROL
MSR uses the same offset temperature format as PECI though it contains no sign bit. Thermal management devices should infer the T should use the relative temperature value delivered over PECI in conjunction with the
T
CONTROL
CONTROL
value as negative. Thermal management algorithms
MSR value to control or optimize fan speeds.
fan control diagram using PECI temperatures.
The relative temperature value reported over PECI represents the delta below the onset of thermal control circuit (TCC) activation as indicated by PROCHOT# assertions. As the temperature approaches TCC activation, the PECI value approaches zero. TCC activates at a PECI count of zero.
90 Datasheet
Thermal Specifications and Design Considerations
.
Figure 27.
Conceptual Fan Control on PECI-Based Platforms
Fan Speed
(RPM)
T
CONTROL
Setting
Max
PECI = -10
TCC Activation
Temperature
PECI = 0
Min
PECI = -20
Temperature
Note: Not intended to depict actual implementation
.
Figure 28.
Conceptual Fan Control on Thermal Diode-Based Platforms
Fan Speed
(RPM)
T
CONTROL
Setting
TCC Activation
Temperature
Max
T
DIODE
= 80 °C
T
DIODE
= 90 °C
Min
T
DIODE
= 70 °C
Temperature
Datasheet 91
Thermal Specifications and Design Considerations
5.4.2
5.4.2.1
5.4.2.2
5.4.2.3
5.4.2.4
Table 35.
PECI Specifications
PECI Device Address
The PECI device address for the socket is 30h. For more information on PECI domains, refer to the Platform Environment Control Interface Specification.
PECI Command Support
PECI command support is covered in detail in the Platform Environment Control
Interface Specification. Refer to this document for details on supported PECI command function and codes.
PECI Fault Handling Requirements
PECI is largely a fault tolerant interface, including noise immunity and error checking improvements over other comparable industry standard interfaces. The PECI client is as reliable as the device that it is embedded in, and thus given operating conditions that fall under the specification, the PECI will always respond to requests and the protocol itself can be relied upon to detect any transmission failures. There are, however, certain scenarios where the PECI is know to be unresponsive.
Prior to a power on RESET# and during RESET# assertion, PECI is not ensured to provide reliable thermal data. System designs should implement a default power-on condition that ensures proper processor operation during the time frame when reliable data is not available via PECI.
To protect platforms from potential operational or safety issues due to an abnormal condition on PECI, the Host controller should take action to protect the system from possible damaging states. It is recommended that the PECI host controller take appropriate action to protect the client processor device if valid temperature readings have not been obtained in response to three consecutive gettemp()s or for a one second time interval. The host controller may also implement an alert to software in the event of a critical or continuous fault condition.
PECI GetTemp0() Error Code Support
The error codes supported for the processor GetTemp() command are listed in
.
GetTemp0() Error Codes
Error Code
8000h
8002h
Description
General sensor error
Sensor is operational, but has detected a temperature below its operational range (underflow).
§ §
92 Datasheet
Features
6 Features
6.1
Table 36.
6.2
Power-On Configuration Options
Several configuration options can be configured by hardware. The processor samples the hardware configuration at reset, on the active-to-inactive transition of RESET#. For
specifications on these options, refer to Table 36
.
The sampled information configures the processor for subsequent operation. These configuration options cannot be changed except by another reset. All resets reconfigure the processor; for reset purposes, the processor does not distinguish between a
"warm" reset and a "power-on" reset.
Power-On Configuration Option Signals
Configuration Option
Output tristate
Execute BIST
Disable dynamic bus parking
Symmetric agent arbitration ID
RESERVED
Signal 1
,
2
,
3
SMI#
A3#
A25#
BR0#
A[8:5]#, A[24:11]#, A[35:26]#
NOTES:
1. Asserting this signal during RESET# will select the corresponding option.
2.
3.
Address signals not identified in this table as configuration options should not be asserted during RESET#.
Disabling of any of the cores within the processor must be handled by configuring the EXT_CONFIG Model Specific Register (MSR). This MSR will allow for the disabling of a single core.
Clock Control and Low Power States
The processor allows the use of AutoHALT and Stop Grant states to reduce power consumption by stopping the clock to internal sections of the processor, depending on each particular state. See
Figure 29 for a visual representation of the processor low
power states.
Datasheet 93
Features
Figure 29.
Processor Low Power State Machine
Normal State
- Normal Execution
HALT or MWAIT Instruction and
HALT Bus Cycle Generated
INIT#, INTR, NMI, SMI#, RESET#,
FSB interrupts
Extended HALT or HALT
State
- BCLK running
- Snoops and interrupts
allowed
6.2.1
6.2.2
6.2.2.1
STPCLK#
Asserted
STPCLK#
De-asserted
Snoop
Event
Occurs
Snoop
Event
Serviced
STPCLK#
Asserted
STPCLK#
De-asserted
Extended Stop Grant
State or Stop Grant State
- BCLK running
- Snoops and interrupts
allowed
Snoop Event Occurs
Snoop Event Serviced
Extended HALT Snoop or
HALT Snoop State
- BCLK running
- Service Snoops to caches
Extended Stop Grant
Snoop or Stop Grant
Snoop State
- BCLK running
- Service Snoops to caches
Normal State
This is the normal operating state for the processor.
HALT and Extended HALT Powerdown States
The processor supports the HALT or Extended HALT powerdown state. The Extended
HALT Powerdown must be enabled via the BIOS for the processor to remain within its specification.
The Extended HALT state is a lower power state as compared to the Stop Grant State.
If Extended HALT is not enabled, the default Powerdown state entered will be HALT.
Refer to the following sections for details about the HALT and Extended HALT states.
HALT Powerdown State
HALT is a low power state entered when all the processor cores have executed the HALT or MWAIT instructions. When one of the processor cores executes the HALT instruction, that processor core is halted; however, the other processor continues normal operation.
The processor transitions to the Normal state upon the occurrence of SMI#, INIT#, or
LINT[1:0] (NMI, INTR). RESET# causes the processor to immediately initialize itself.
The return from a System Management Interrupt (SMI) handler can be to either
Normal Mode or the HALT Power Down state. See the Intel Architecture Software
Developer's Manual, Volume III: System Programmer's Guide for more information.
94 Datasheet
Features
6.2.2.2
6.2.3
6.2.3.1
The system can generate a STPCLK# while the processor is in the HALT powerdown state. When the system de-asserts the STPCLK# interrupt, the processor will return execution to the HALT state.
While in HALT Power powerdown, the processor processes bus snoops.
Extended HALT Powerdown State
Extended HALT is a low power state entered when all processor cores have executed the HALT or MWAIT instructions and Extended HALT has been enabled via the BIOS.
When one of the processor cores executes the HALT instruction, that logical processor is halted; however, the other processor continues normal operation. The Extended
HALT Powerdown state must be enabled via the BIOS for the processor to remain within its specification.
The processor automatically transitions to a lower frequency and voltage operating point before entering the Extended HALT state. Note that the processor FSB frequency is not altered; only the internal core frequency is changed. When entering the low power state, the processor first switches to the lower bus ratio and then transitions to the lower VID.
While in Extended HALT state, the processor processes bus snoops.
The processor exits the Extended HALT state when a break event occurs. When the processor exits the Extended HALT state, it will resume operation at the lower frequency, transitions the VID to the original value and then changes the bus ratio back to the original value.
Stop Grant and Extended Stop Grant States
The processor supports the Stop Grant and Extended Stop Grant states. The Extended
Stop Grant state is a feature that must be configured and enabled via the BIOS. Refer to the following sections for details about the Stop Grant and Extended Stop Grant states.
Stop Grant State
When the STPCLK# signal is asserted, the Stop Grant state of the processor is entered
20 bus clocks after the response phase of the processor-issued Stop Grant
Acknowledge special bus cycle.
Since the GTL+ signals receive power from the FSB, these signals should not be driven
(allowing the level to return to V
TT
) for minimum power drawn by the termination resistors in this state. In addition, all other input signals on the FSB should be driven to the inactive state.
RESET# causes the processor to immediately initialize itself, but the processor will stay in Stop Grant state. A transition back to the Normal state occurs with the de-assertion of the STPCLK# signal.
A transition to the Grant Snoop state occurs when the processor detects a snoop on the
While in the Stop Grant State, SMI#, INIT#, and LINT[1:0] is latched by the processor, and only serviced when the processor returns to the Normal State. Only one occurrence of each event will be recognized upon return to the Normal state.
While in Stop Grant state, the processor processes a FSB snoop.
Datasheet 95
Features
6.2.3.2
6.2.4
6.2.4.1
6.2.4.2
6.3
Note:
Extended Stop Grant State
Extended Stop Grant is a low power state entered when the STPCLK# signal is asserted and Extended Stop Grant has been enabled via the BIOS.
The processor will automatically transition to a lower frequency and voltage operating point before entering the Extended Stop Grant state. When entering the low power state, the processor will first switch to the lower bus ratio and then transition to the lower VID.
The processor exits the Extended Stop Grant state when a break event occurs. When the processor exits the Extended Stop Grant state, it will resume operation at the lower frequency, transition the VID to the original value, and then change the bus ratio back to the original value.
Extended HALT State, HALT Snoop State, Extended Stop
Grant Snoop State, and Stop Grant Snoop State
The Extended HALT Snoop State is used in conjunction with the new Extended HALT state. If Extended HALT state is not enabled in the BIOS, the default Snoop State entered will be the HALT Snoop State. Refer to the following sections for details on
HALT Snoop State, Stop Grant Snoop State and Extended HALT Snoop State, and
Extended Stop Grant Snoop State.
HALT Snoop State, Stop Grant Snoop State
The processor will respond to snoop transactions on the FSB while in Stop Grant state or in HALT Power Down state. During a snoop transaction, the processor enters the
HALT Snoop State:Stop Grant Snoop state. The processor will stay in this state until the snoop on the FSB has been serviced (whether by the processor or another agent on the
FSB). After the snoop is serviced, the processor returns to the Stop Grant state or HALT
Power Down state, as appropriate.
Extended HALT Snoop State, Extended Stop Grant Snoop State
The processor will remain in the lower bus ratio and VID operating point of the
Extended HALT state or Extended Stop Grant state. While in the Extended HALT Snoop
State or Extended Stop Grant Snoop State, snoops are handled the same way as in the
HALT Snoop State or Stop Grant Snoop State. After the snoop is serviced, the processor will return to the Extended HALT state or Extended Stop Grant state.
Enhanced Intel
®
SpeedStep
®
Technology
The processor supports Enhanced Intel SpeedStep
®
Technology. This technology enables the processor to switch between multiple frequency and voltage points, which results in platform power savings. Enhanced Intel SpeedStep support for dynamic VID transitions in the platform. Switching between voltage/ frequency states is software controlled.
Technology requires
Not all processors are capable of supporting Enhanced Intel SpeedStep ® Technology.
More details on which processor frequencies support this feature is provided in the
Intel ® Core™2 Duo Desktop Processor E6000 and E4000 Series and Intel
Extreme Processor X6800 Specification Update.
® Core™2
Enhanced Intel SpeedStep
®
Technology creates processor performance states (Pstates) or voltage/frequency operating points. P-states are lower power capability
states within the Normal state as shown in Figure 29
. Enhanced Intel SpeedStep
®
Technology enables real-time dynamic switching between frequency and voltage
96 Datasheet
Features points. It alters the performance of the processor by changing the bus to core frequency ratio and voltage. This allows the processor to run at different core frequencies and voltages to best serve the performance and power requirements of the processor and system. The processor has hardware logic that coordinates the requested voltage (VID) between the processor cores. The highest voltage that is requested for either of the processor cores is selected for that processor package. Note that the front side bus is not altered; only the internal core frequency is changed. To run at reduced power consumption, the voltage is altered in step with the bus ratio.
The following are key features of Enhanced Intel SpeedStep
®
Technology:
• Multiple voltage/frequency operating points provide optimal performance at reduced power consumption.
• Voltage/frequency selection is software controlled by writing to processor MSRs
(Model Specific Registers), thus eliminating chipset dependency.
— If the target frequency is higher than the current frequency, V
CC
is incremented in steps (+12.5 mV) by placing a new value on the VID signals and the processor shifts to the new frequency. Note that the top frequency for the processor can not be exceeded.
— If the target frequency is lower than the current frequency, the processor shifts to the new frequency and V
CC
is then decremented in steps (-12.5 mV) by changing the target VID through the VID signals.
§ §
Datasheet 97
Features
98 Datasheet
Boxed Processor Specifications
7 Boxed Processor Specifications
Note:
The processor is also offered as an Intel boxed processor. Intel boxed processors are intended for system integrators who build systems from baseboards and standard components. The boxed processor will be supplied with a cooling solution. This chapter documents baseboard and system requirements for the cooling solution that will be supplied with the boxed processor. This chapter is particularly important for OEMs that
manufacture baseboards for system integrators. Figure 30
shows a mechanical representation of a boxed processor.
Unless otherwise noted, all figures in this chapter are dimensioned in millimeters and inches [in brackets].
Note: Drawings in this section reflect only the specifications on the Intel boxed processor product. These dimensions should not be used as a generic keep-out zone for all cooling solutions. It is the system designers’ responsibility to consider their proprietary cooling solution when designing to the required keep-out zone on their system platforms and chassis. Refer to the appropriate Thermal and Mechanical Design
) for further guidance.
Figure 30.
Mechanical Representation of the Boxed Processor
Datasheet
NOTE: The airflow of the fan heatsink is into the center and out of the sides of the fan heatsink.
99
Boxed Processor Specifications
7.1
Mechanical Specifications
7.1.1
Boxed Processor Cooling Solution Dimensions
This section documents the mechanical specifications of the boxed processor. The boxed processor will be shipped with an unattached fan heatsink.
mechanical representation of the boxed processor.
Clearance is required around the fan heatsink to ensure unimpeded airflow for proper cooling. The physical space requirements and dimensions for the boxed processor with
assembled fan heatsink are shown in Figure 31 (Side View), and Figure 32
(Top View).
The airspace requirements for the boxed processor fan heatsink must also be incorporated into new baseboard and system designs. Airspace requirements are shown in
. Note that some figures have centerlines shown
(marked with alphabetic designations) to clarify relative dimensioning.
Figure 31.
Space Requirements for the Boxed Processor (Side View)
95.0
[3.74]
81.3
[3.2]
10.0
[0.39]
25.0
[0.98]
Figure 32.
Space Requirements for the Boxed Processor (Top View)
100
NOTES:
1.
Diagram does not show the attached hardware for the clip design and is provided only as a mechanical representation.
Datasheet
Boxed Processor Specifications
Figure 33.
Space Requirements for the Boxed Processor (Overall View)
7.1.2
7.1.3
7.2
7.2.1
Boxed Proc OverallView
Boxed Processor Fan Heatsink Weight
The boxed processor fan heatsink will not weigh more than 550 grams. See Chapter 5
and the appropriate Thermal and Mechanical Design Guidelines (see Section 1.2
) for details on the processor weight and heatsink requirements.
Boxed Processor Retention Mechanism and Heatsink
Attach Clip Assembly
The boxed processor thermal solution requires a heatsink attach clip assembly, to secure the processor and fan heatsink in the baseboard socket. The boxed processor will ship with the heatsink attach clip assembly.
Electrical Requirements
Fan Heatsink Power Supply
The boxed processor's fan heatsink requires a +12 V power supply. A fan power cable will be shipped with the boxed processor to draw power from a power header on the
baseboard. The power cable connector and pinout are shown in Figure 34
. Baseboards
must provide a matched power header to support the boxed processor. Table 37
contains specifications for the input and output signals at the fan heatsink connector.
The fan heatsink outputs a SENSE signal that is an open- collector output that pulses at a rate of 2 pulses per fan revolution. A baseboard pull-up resistor provides V
OH
to match the system board-mounted fan speed monitor requirements, if applicable. Use of the SENSE signal is optional. If the SENSE signal is not used, pin 3 of the connector should be tied to GND.
The fan heatsink receives a PWM signal from the motherboard from the 4th pin of the connector labeled as CONTROL.
Datasheet 101
Boxed Processor Specifications
The boxed processor's fanheat sink requires a constant +12 V supplied to pin 2 and does not support variable voltage control or 3-pin PWM control.
The power header on the baseboard must be positioned to allow the fan heatsink power cable to reach it. The power header identification and location should be documented in the platform documentation, or on the system board itself.
location of the fan power connector relative to the processor socket. The baseboard power header should be positioned within 110 mm [4.33 inches] from the center of the processor socket.
Figure 34.
Boxed Processor Fan Heatsink Power Cable Connector Description
1
2
3
4
Pin Signal
GND
+12 V
SENSE
CONTROL
Straight square pin, 4-pin terminal housing with polarizing ribs and friction locking ramp.
0.100" pitch, 0.025" square pin width.
Match with straight pin, friction lock header on mainboard.
1 2 3 4
B d P P C bl
Table 37.
Fan Heatsink Power and Signal Specifications
Description
+12 V: 12 volt fan power supply
IC:
- Maximum fan steady-state current draw
- Average fan steady-state current draw
- Max fan start-up current draw
- Fan start-up current draw maximum duration
Min
11.4
—
—
—
—
Typ
12
1.2
0.5
2.2
1.0
Max
12.6
SENSE: SENSE frequency — 2 —
CONTROL 21 25 28
1.
2.
NOTES:
Baseboard should pull this pin up to 5 V with a resistor.
Open drain type, pulse width modulated.
3. Fan will have pull-up resistor for this signal to maximum of 5.25 V.
—
—
—
—
Unit
V
Notes
-
A
A
A
Second pulses per fan revolution
Hz
-
1
2, 3
102 Datasheet
Boxed Processor Specifications
Figure 35.
Baseboard Power Header Placement Relative to Processor Socket
R110
[4.33]
B
C
7.3
7.3.1
Boxed Proc PwrHeaderPlacement
Thermal Specifications
This section describes the cooling requirements of the fan heatsink solution used by the boxed processor.
Boxed Processor Cooling Requirements
The boxed processor may be directly cooled with a fan heatsink. However, meeting the processor's temperature specification is also a function of the thermal design of the entire system, and ultimately the responsibility of the system integrator. The processor temperature specification is listed in
Chapter 5 . The boxed processor fan heatsink is
able to keep the processor temperature within the specifications (see
chassis that provide good thermal management. For the boxed processor fan heatsink to operate properly, it is critical that the airflow provided to the fan heatsink is unimpeded. Airflow of the fan heatsink is into the center and out of the sides of the fan heatsink. Airspace is required around the fan to ensure that the airflow through the fan heatsink is not blocked. Blocking the airflow to the fan heatsink reduces the cooling efficiency and decreases fan life.
illustrate an acceptable airspace clearance for the fan heatsink. The air temperature entering the fan should be kept below 38 ºC. Again, meeting the processor's temperature specification is the responsibility of the system integrator.
Datasheet 103
Boxed Processor Specifications
Figure 36.
Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 1 view)
Figure 37.
Boxed Processor Fan Heatsink Airspace Keepout Requirements (Side 2 View)
104 Datasheet
Boxed Processor Specifications
7.3.2
7.3.3
Fan Speed Control Operation (Intel
®
Processor X6800 Only)
Core2 Extreme
The boxed processor fan heatsink is designed to operate continuously at full speed to allow maximum user control over fan speed. The fan speed can be controlled by hardware and software from the motherboard. This is accomplished by varying the duty
cycle of the Control signal on the 4th pin (see Table 38 ). The motherboard must have a
4-pin fan header and must be designed with a fan speed controller with PWM output and Digital Thermometer measurement capabilities. For more information on specific motherboard requirements for 4-wire based fan speed control, refer to the Intel ®
Pentium ® D Processor, Intel ® Pentium ® Processor Extreme Edition, Intel ® Pentium
Processor, Intel ® Core™2 Duo Extreme Processor X6800 Thermal and Mechanical
Design Guidelines.
® 4
The Internal chassis temperature should be kept below 39 ºC. Meeting the processor's
temperature specification (see Chapter 5
) is the responsibility of the system integrator.
The motherboard must supply a constant +12 V to the processor's power header to
ensure proper operation of the fan for the boxed processor. See Table 38
for specific requirements.
Fan Speed Control Operation (Intel
®
Core2 Duo Desktop
Processor E6000 and E4000 Series Only)
If the boxed processor fan heatsink 4-pin connector is connected to a 3-pin motherboard header, it will operate as follows:
The boxed processor fan will operate at different speeds over a short range of internal chassis temperatures. This allows the processor fan to operate at a lower speed and noise level, while internal chassis temperatures are low. If internal chassis temperature increases beyond a lower set point, the fan speed will rise linearly with the internal temperature until the higher set point is reached. At that point, the fan speed is at its maximum. As fan speed increases, so does fan noise levels. Systems should be designed to provide adequate air around the boxed processor fan heatsink that remains cooler than lower set point. These set points, represented in
Table 38 , can vary by a few degrees from fan heatsink
to fan heatsink. The internal chassis temperature should be kept below 38 ºC.
Meeting the processor's temperature specification (see
) is the responsibility of the system integrator.
The motherboard must supply a constant +12 V to the processor's power header to ensure proper operation of the variable speed fan for the boxed processor. Refer to
for the specific requirements.
Figure 38.
Boxed Processor Fan Heatsink Set Points
Higher Set Point
Highest Noise Level
Increasing Fan
Speed & Noise
Lower Set Point
Lowest Noise Level
X Y
Internal Chassis Temperature (Degrees C)
Z
Datasheet 105
Boxed Processor Specifications
Table 38.
Fan Heatsink Power and Signal Specifications
Boxed Processor Fan
Heatsink Set Point (°C)
Boxed Processor Fan Speed
X ≤ 30
Y = 35
Z ≥ 38
When the internal chassis temperature is below or equal to this set point, the fan operates at its lowest speed.
Recommended maximum internal chassis temperature for nominal operating environment.
When the internal chassis temperature is at this point, the fan operates between its lowest and highest speeds.
Recommended maximum internal chassis temperature for worst-case operating environment.
When the internal chassis temperature is above or equal to this set point, the fan operates at its highest speed.
Notes
1
-
-
NOTES:
1.
Set point variance is approximately ± 1 °C from fan heatsink to fan heatsink.
If the boxed processor fan heatsink 4-pin connector is connected to a 4-pin motherboard header and the motherboard is designed with a fan speed controller with
PWM output (CONTROL see
Table 37 ) and remote thermal diode measurement
capability the boxed processor will operate as follows:
As processor power has increased the required thermal solutions have generated increasingly more noise. Intel has added an option to the boxed processor that allows system integrators to have a quieter system in the most common usage.
The 4th wire PWM solution provides better control over chassis acoustics. This is achieved by more accurate measurement of processor die temperature through the processor's temperature diode (T-diode). Fan RPM is modulated through the use of an
ASIC located on the motherboard that sends out a PWM control signal to the 4th pin of the connector labeled as CONTROL. The fan speed is based on actual processor temperature instead of internal ambient chassis temperatures.
If the new 4-pin active fan heat sink solution is connected to an older 3-pin baseboard processor fan header it will default back to a thermistor controlled mode, allowing compatibility with existing 3-pin baseboard designs. Under thermistor controlled mode, the fan RPM is automatically varied based on the Tinlet temperature measured by a thermistor located at the fan inlet.
For more details on specific motherboard requirements for 4-wire based fan speed control, refer to the appropriate Thermal and Mechanical Design Guidelines (see
).
§ §
106 Datasheet
Balanced Technology Extended (BTX) Boxed Processor Specifications
8 Balanced Technology Extended
(BTX) Boxed Processor
Specifications
Note:
The processor is offered as an Intel boxed processor. Intel boxed processors are intended for system integrators who build systems from largely standard components.
The boxed processor will be supplied with a cooling solution known as the Thermal
Module Assembly (TMA). Each processor will be supplied with one of the two available types of TMAs – Type I or Type II. This chapter documents motherboard and system requirements for both the TMAs that will be supplied with the boxed processor in the
775-land LGA package. This chapter is particularly important for OEMs that manufacture motherboards for system integrators.
representation of a boxed processor in the 775-land LGA package with a Type I TMA.
illustrates a mechanical representation of a boxed processor in the 775-land
LGA package with Type II TMA.
Unless otherwise noted, all figures in this chapter are dimensioned in millimeters and inches [in brackets].
Note: Drawings in this section reflect only the specifications on the Intel boxed processor product. These dimensions should not be used as a generic keep-out zone for all cooling solutions. It is the system designers’ responsibility to consider their proprietary cooling solution when designing to the required keep-out zone on their system platforms and chassis. Refer to the appropriate Thermal and Mechanical Design
) for further guidance.
Figure 39.
Mechanical Representation of the Boxed Processor with a Type I TMA
Datasheet
NOTE: The duct, clip, heatsink and fan can differ from this drawing representation but the basic shape and size will remain the same.
107
Balanced Technology Extended (BTX) Boxed Processor Specifications
Figure 40.
Mechanical Representation of the Boxed Processor with a Type II TMA
8.1
8.1.1
NOTE: The duct, clip, heatsink and fan can differ from this drawing representation but the basic shape and size will remain the same.
Mechanical Specifications
Balanced Technology Extended (BTX) Type I and Type II
Boxed Processor Cooling Solution Dimensions
This section documents the mechanical specifications of the boxed processor TMA. The
boxed processor will be shipped with an unattached TMA. Figure 41
shows a mechanical representation of the boxed processor in the 775-land LGA package for
Type I TMA. Figure 42 shows a mechanical representation of the boxed processor in the
775-land LGA package for Type II TMA. The physical space requirements and dimensions for the boxed processor with assembled fan thermal module are shown.
108 Datasheet
Balanced Technology Extended (BTX) Boxed Processor Specifications
Figure 41.
Requirements for the Balanced Technology Extended (BTX) Type I Keep-out
Volumes
Datasheet
NOTE: Diagram does not show the attached hardware for the clip design and is provided only as a mechanical representation.
109
Balanced Technology Extended (BTX) Boxed Processor Specifications
Figure 42.
Requirements for the Balanced Technology Extended (BTX) Type II Keep-out
Volume
8.1.2
NOTE: Diagram does not show the attached hardware for the clip design and is provided only as a mechanical representation.
Boxed Processor Thermal Module Assembly Weight
The boxed processor thermal module assembly for Type I BTX will not weigh more than
1200 grams. The boxed processor thermal module assembly for Type II BTX will not
weigh more than 1200 grams. See Chapter 3 and the appropriate Thermal and
Mechanical Design Guidelines (see
) for details on the processor weight and thermal module assembly requirements.
110 Datasheet
Balanced Technology Extended (BTX) Boxed Processor Specifications
8.1.3
Boxed Processor Support and Retention Module (SRM)
The boxed processor TMA requires an SRM assembly provided by the chassis manufacturer. The SRM provides the attach points for the TMA and provides structural support for the board by distributing the shock and vibration loads to the chassis base pan. The boxed processor TMA will ship with the heatsink attach clip assembly, duct and screws for attachment. The SRM must be supplied by the chassis hardware vendor.
See the Support and Retention Module(SRM) External Design Requirements Document,
Balanced Technology Extended (BTX) System Design Guide, and the appropriate
Thermal and Mechanical Design Guidelines (see
information regarding the support and retention module and chassis interface and
illustrates the assembly stack including the SRM.
Figure 43.
Assembly Stack Including the Support and Retention Module
T he rm a l M od u le A ssem bly
• H ea tsin k & Fan
• C lip
• S tructural D uct
M othe rboard
S R M
C ha ssis P an
Datasheet 111
Balanced Technology Extended (BTX) Boxed Processor Specifications
8.2
Electrical Requirements
8.2.1
Thermal Module Assembly Power Supply
The boxed processor's Thermal Module Assembly (TMA) requires a +12 V power supply.
The TMA will include power cable to power the integrated fan and will plug into the 4wire fan header on the baseboard. The power cable connector and pinout are shown in
Figure 44 . Baseboards must provide a compatible power header to support the boxed
processor.
contains specifications for the input and output signals at the TMA.
The TMA outputs a SENSE signal, which is an open-collector output that pulses at a rate of 2 pulses per fan revolution. A baseboard pull-up resistor provides V
OH
to match the system board-mounted fan speed monitor requirements, if applicable. Use of the
SENSE signal is optional. If the SENSE signal is not used, pin 3 of the connector should be tied to GND.
The TMA receives a Pulse Width Modulation (PWM) signal from the motherboard from the 4 th
pin of the connector labeled as CONTROL.
Note: The boxed processor’s TMA requires a constant +12 V supplied to pin 2 and does not support variable voltage control or 3-pin PWM control.
The power header on the baseboard must be positioned to allow the TMA power cable to reach it. The power header identification and location should be documented in the platform documentation, or on the system board itself.
shows the location of the fan power connector relative to the processor socket. The baseboard power header should be positioned within 4.33 inches from the center of the processor socket.
Figure 44.
Boxed Processor TMA Power Cable Connector Description
1
2
3
4
Pin Signal
GND
+12 V
SENSE
CONTROL
Straight square pin, 4-pin terminal housing with polarizing ribs and friction locking ramp.
0.100" pitch, 0.025" square pin width.
Match with straight pin, friction lock header on mainboard.
1 2 3 4
B d P P C bl
112 Datasheet
Balanced Technology Extended (BTX) Boxed Processor Specifications
Table 39.
TMA Power and Signal Specifications
Description
+12V: 12 volt fan power supply
IC:
- Peak Fan current draw
- Fan start-up current draw
- Fan start-up current draw maximum duration
Min
10.2
—
—
—
Typ
12
1.0
—
—
Max
13.8
1.5
2.0
1.0
SENSE: SENSE frequency — 2 —
CONTROL 21 25
1.
2.
NOTES:
Baseboard should pull this pin up to 5V with a resistor.
Open Drain Type, Pulse Width Modulated.
3. Fan will have a pull-up resistor for this signal to maximum 5.25 V.
28
Unit
V
A
A
Second pulses per fan revolution kHz
Notes
1
2, 3
Figure 45.
Balanced Technology Extended (BTX) Mainboard Power Header Placement
(hatched area)
Datasheet 113
Balanced Technology Extended (BTX) Boxed Processor Specifications
8.3
8.3.1
8.3.2
Note:
Thermal Specifications
This section describes the cooling requirements of the thermal module assembly solution used by the boxed processor.
Boxed Processor Cooling Requirements
The boxed processor may be directly cooled with a TMA. However, meeting the processor's temperature specification is also a function of the thermal design of the entire system, and ultimately the responsibility of the system integrator. The processor case temperature specification is listed in
Chapter 5 . The boxed processor TMA is able
to keep the processor temperature within the specifications (see Table 26 ) for chassis
that provide good thermal management. For the boxed processor TMA to operate properly, it is critical that the airflow provided to the TMA is unimpeded. Airflow of the
TMA is into the duct and out of the rear of the duct in a linear flow. Blocking the airflow to the TMA inlet reduces the cooling efficiency and decreases fan life. Filters will reduce or impede airflow which will result in a reduced performance of the TMA. The air temperature entering the fan should be kept below 35.5 °C. Meeting the processor's temperature specification is the responsibility of the system integrator.
In addition, Type I TMA must be used with Type I chassis only and Type II TMA with
Type II chassis only. Type I TMA will not fit in a Type II chassis due to the height difference. In the event a Type II TMA is installed in a Type I chassis, the gasket on the chassis will not seal against the Type II TMA and poor acoustic performance will occur as a result.
Variable Speed Fan
The boxed processor fan operates at different speeds over a short range of temperatures based on a thermistor located in the fan hub area. This allows the boxed processor fan to operate at a lower speed and noise level while thermistor temperatures are low. If the thermistor senses a temperatures increase beyond a lower set point, the fan speed will rise linearly with the temperature until the higher set point is reached. At that point, the fan speed is at its maximum. As fan speed increases, so do fan noise levels. These set points are represented in
The internal chassis temperature should be kept below 35.5 ºC. Meeting the processor’s
temperature specification (see Chapter 5
) is the responsibility of the system integrator.
The motherboard must supply a constant +12 V to the processor’s power header to ensure proper operation of the variable speed fan for the boxed processor (refer to
) for the specific requirements).
114 Datasheet
Balanced Technology Extended (BTX) Boxed Processor Specifications
Figure 46.
Boxed Processor TMA Set Points
Higher Set Point
Highest Noise Level
Increasing Fan
Speed & Noise
Lower Set Point
Lowest Noise Level
X Y
Internal Chassis Temperature (Degrees C)
Z
Table 40.
TMA Set Points for 3-wire operation of BTX Type I and Type II Boxed
Processors
Boxed Processor
TMA Set Point
(ºC)
Boxed Processor Fan Speed
X ≤ 23
Y = 29
Z ≥ 35.5
When the internal chassis temperature is below or equal to this set point, the fan operates at its lowest speed. Recommended maximum internal chassis temperature for nominal operating environment.
When the internal chassis temperature is at this point, the fan operates between its lowest and highest speeds.
Recommended maximum internal chassis temperature for worst-case operating environment.
When the internal chassis temperature is above or equal to this set point, the fan operates at its highest speed.
Notes
1
1
NOTES:
1.
Set point variance is approximately ±1°C from Thermal Module Assembly to Thermal
Module Assembly.
If the boxed processor TMA 4-pin connector is connected to a 4-pin motherboard header and the motherboard is designed with a fan speed controller with PWM output
(see CONTROL in Table 39 ) and remote thermal diode measurement capability, the
boxed processor will operate as described in the following paragraphs.
As processor power has increased, the required thermal solutions have generated increasingly more noise. Intel has added an option to the boxed processor that allows system integrators to have a quieter system in the most common usage.
The 4-wire PWM controlled fan in the TMA solution provides better control over chassis acoustics. It allows better granularity of fan speed and lowers overall fan speed than a voltage-controlled fan. Fan RPM is modulated through the use of an ASIC located on
Datasheet 115
Balanced Technology Extended (BTX) Boxed Processor Specifications the motherboard that sends out a PWM control signal to the 4 labeled as CONTROL. The fan speed is based on a combination of actual processor temperature and thermistor temperature. th pin of the connector
If the 4-wire PWM controlled fan in the TMA solution is connected to a 3-pin baseboard processor fan header it will default back to a thermistor controlled mode, allowing compatibility with existing 3-pin baseboard designs. Under thermistor controlled mode, the fan RPM is automatically varied based on the T inlet
temperature measured by a thermistor located at the fan inlet.
For more details on specific motherboard requirements for 4-wire based fan speed control, refer to the appropriate Thermal and Mechanical Design Guidelines (see
).
§ §
116 Datasheet
Debug Tools Specifications
9
9.1
9.1.1
9.1.2
Debug Tools Specifications
Logic Analyzer Interface (LAI)
Intel is working with two logic analyzer vendors to provide logic analyzer interfaces
(LAIs) for use in debugging systems. Tektronix and Agilent should be contacted to get specific information about their logic analyzer interfaces. The following information is general in nature. Specific information must be obtained from the logic analyzer vendor.
Due to the complexity of systems, the LAI is critical in providing the ability to probe and capture FSB signals. There are two sets of considerations to keep in mind when designing a system that can make use of an LAI: mechanical and electrical.
Mechanical Considerations
The LAI is installed between the processor socket and the processor. The LAI lands plug into the processor socket, while the processor lands plug into a socket on the LAI.
Cabling that is part of the LAI egresses the system to allow an electrical connection between the processor and a logic analyzer. The maximum volume occupied by the LAI, known as the keepout volume, as well as the cable egress restrictions, should be obtained from the logic analyzer vendor. System designers must make sure that the keepout volume remains unobstructed inside the system. Note that it is possible that the keepout volume reserved for the LAI may differ from the space normally occupied by the processor’s heatsink. If this is the case, the logic analyzer vendor will provide a cooling solution as part of the LAI.
Electrical Considerations
The LAI will also affect the electrical performance of the FSB; therefore, it is critical to obtain electrical load models from each of the logic analyzers to be able to run system level simulations to prove that their tool will work in the system. Contact the logic analyzer vendor for electrical specifications and load models for the LAI solution it provides.
§ §
Datasheet 117
Debug Tools Specifications
118 Datasheet
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