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a
FEATURES
140 MSPS Maximum Conversion Rate
300 MHz Analog Bandwidth
0.5 V to 1.0 V Analog Input Range
500 ps p-p PLL Clock Jitter at 110 MSPS
3.3 V Power Supply
Full Sync Processing
Sync Detect for ”Hot Plugging”
Midscale Clamping
Power-Down Mode
Low Power: 500 mW Typical
4:2:2 Output Format Mode
APPLICATIONS
RGB Graphics Processing
LCD Monitors and Projectors
Plasma Display Panels
Scan Converters
Microdisplays
Digital TV
110 MSPS/140 MSPS Analog Interface for
Flat Panel Displays
AD9883A
FUNCTIONAL BLOCK DIAGRAM
R
AIN
G
AIN
B
AIN
HSYNC
COAST
CLAMP
FILT
SCL
SDA
A
0
CLAMP
CLAMP
CLAMP
SYNC
PROCESSING
AND CLOCK
GENERATION
SERIAL REGISTER
AND
POWER MANAGEMENT
A/D
A/D
A/D
8
8
8
REF
AD9883A
R
OUTA
G
OUTA
B
OUTA
MIDSCV
DTACK
HSOUT
VSOUT
SOGOUT
REF
BYPASS
GENERAL DESCRIPTION
The AD9883A is a complete 8-bit, 140 MSPS monolithic analog interface optimized for capturing RGB graphics signals from personal computers and workstations. Its 140 MSPS encode rate capability and full power analog bandwidth of 300 MHz supports resolutions up to SXGA (1280
× 1024 at 75 Hz).
The AD9883A includes a 140 MHz triple ADC with internal
1.25 V reference, a PLL, and programmable gain, offset, and clamp control. The user provides only a 3.3 V power supply, analog input, and HSYNC and COAST signals. Three-state
CMOS outputs may be powered from 2.5 V to 3.3 V.
The AD9883A’s on-chip PLL generates a pixel clock from
HSYNC and COAST inputs. Pixel clock output frequencies range from 12 MHz to 140 MHz. PLL clock jitter is 500 ps p-p typical at 140 MSPS. When the COAST signal is presented, the PLL maintains its output frequency in the absence of
HSYNC. A sampling phase adjustment is provided. Data,
HSYNC and Clock output phase relationships are maintained.
The AD9883A also offers full sync processing for composite sync and sync-on-green applications.
A clamp signal is generated internally or may be provided by the user through the CLAMP input pin. This interface is fully programmable via a 2-wire serial interface.
Fabricated in an advanced CMOS process, the AD9883A is provided in a space-saving 80-lead LQFP surface mount plastic package and is specified over the 0
°C to 70°C temperature range.
REV. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703 www.analog.com
© Analog Devices, Inc., 2001
AD9883A–SPECIFICATIONS
Analog Interface
(V
D
= 3.3 V, V
DD
= 3.3 V, ADC Clock = Maximum Conversion Rate unless otherwise noted.)
Parameter
RESOLUTION
DC ACCURACY
Differential Nonlinearity
Test
Temp Level
Integral Nonlinearity
25 °C I
Full VI
25 °C I
Full VI
Full VI No Missing Codes
ANALOG INPUT
Input Voltage Range
Minimum
Maximum
Gain Tempco
Input Bias Current
Input Offset Voltage
Input Full-Scale Matching
Offset Adjustment Range
REFERENCE OUTPUT
Output Voltage
Temperature Coefficient
Full VI
Full VI
25
°C
V
25 °C IV
Full IV
Full
Full
Full
VI
VI
VI
Full VI
Full V
SWITCHING PERFORMANCE
Maximum Conversion Rate
Minimum Conversion Rate
Data to Clock Skew t
BUFF t
STAH t
DHO t
DAL t
DAH t
DSU t
STASU t
STOSU
HSYNC Input Frequency
Maximum PLL Clock Rate
Minimum PLL Clock Rate
PLL Jitter
Full VI
Full IV
Full IV
Full VI
Full VI
Full VI
Full VI
Full VI
Full VI
Full VI
Full VI
Full IV
Full VI
Full IV
25
°C
IV
Full IV
Full IV Sampling Phase Tempco
DIGITAL INPUTS
Input Voltage, High (V
IH
)
Input Voltage, Low (V
IL
)
Input Voltage, High (V
IH
)
Input Voltage, Low (V
IL
)
Input Capacitance
Full VI
Full VI
Full V
Full V
25
°C
V
Min
1.0
46
1.20
110
–0.5
4.7
4.0
0
4.7
4.0
250
4.7
4.0
15
110
2.5
AD9883AKST-110
Typ
8
±0.5
Max
+1.25/–1.0
±0.5
Guaranteed
+1.35/–1.0
±1.85
±2.0
100
7
1.5
49
1.25
±50
400
15
3
0.5
1
1
50
6.0
52
1.32
10
+2.0
110
12
700
1000
0.8
–1.0
1
+1.0
1
AD9883AKST-140
Min Typ Max
8
1.0
46
1.20
1.25
±50
–0.5
4.7
4.0
0
4.7
4.0
250
4.7
4.0
15
140
2.5
Unit
Bits
±0.5
+1.35/–1.0
LSB
±0.5
+1.45/–1.0
LSB
±2.0
LSB
±2.3
LSB
Guaranteed
100
7
1.5
49
140
400
15
3
0.5
1
1
70
8.0
52
1.32
10
+2.0
110
12
700 1
1000 1
0.8
–1.0
+1.0
V
V
µA
µA pF
MSPS
MSPS
µs
µs
µs
µs
µs ns
µs
µs
µs kHz
MHz
MHz ps p-p ps p-p ps/
°C
V p-p
V p-p ppm/
°C
µA
µA mV
% FS
% FS
V ppm/
°C
–2– REV. 0
Parameter
Test
Temp Level Min
AD9883AKST-110
Typ Max
DIGITAL OUTPUTS
Output Voltage, High (V
OH
)
Output Voltage, Low (V
OL
)
Duty Cycle DATACK
Output Coding
Full VI
Full VI
Full IV
POWER SUPPLY
I
V
D
Supply Voltage
V
DD
Supply Voltage
P
VD
IP
Supply Voltage
I
D
Supply Current (V
D
)
DD
Supply Current (V
DD
)
2
VD
Supply Current (P
Total Power Dissipation
VD
)
Full
Full
IV
IV
Full IV
25 °C V
25
°C
V
25
°C
V
Full VI
Power-Down Supply Current Full VI
Power-Down Dissipation Full VI
DYNAMIC PERFORMANCE
Analog Bandwidth, Full Power 25
°C
V
Transient Response 25 °C V
Overvoltage Recovery Time 25
°C
V
Signal-to-Noise Ratio (SNR) 25 °C V
(Without Harmonics) Full V f
IN
= 40.7 MHz
Crosstalk Full V
THERMAL CHARACTERISTICS
θ
JC
Junction-to-Case
Thermal Resistance
θ
JA
Junction-to-Ambient
Thermal Resistance
V
V
V
D
45
3.0
2.2
3.0
NOTES
1
VCO Range = 10, Charge Pump Current = 110, PLL Divider = 1693.
2
DATACK Load = 15 pF, Data Load = 5 pF.
Specifications subject to change without notice.
– 0.1
50
Binary
3.3
3.3
3.3
132
19
8
525
5
16.5
300
2
1.5
44
43
55
16
35
0.1
55
3.6
3.6
3.6
650
10
33
Min
AD9883AKST-140
Typ Max
V
D
– 0.1
45 50
Binary
0.1
55
3.15
2.2
3.0
3.6
3.6
3.6
300
2
1.5
43
42
55
3.3
3.3
3.3
180
26
11
650
5
16.5
800
10
33
16
35
AD9883A
Unit
V
V
%
MHz ns ns dB dB dBc
V
V
V mA mA mA mW mA mW
°C/W
°C/W
REV. 0 –3–
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Table of contents
- 2 Specifications
- 5 Pinout
- 24 Package Drawings
- 4 Ordering Guide
- 1 Features
- 1 Applications
- 1 Product Description
- 4 Absolute Maximum Ratings
- 1 Functional Block Diagram
- 6 Pin Function Description
- 4 EXPLANATION OF TEST LEVELS
- 6 OUTPUTS
- 6 DATA OUTPUTS
- 6 DATA CLOCK OUTPUT
- 6 INPUTS
- 7 POWER SUPPLY
- 7 DESIGN GUIDE
- 15 TWO-WIRE SERIAL CONTROL REGISTER DETAIL
- 15 CHIP IDENTIFICATION
- 15 PLL DIVIDER CONTROL
- 16 MODE CONTROL 1
- 16 INPUT GAIN
- 20 WIRE SERIAL CONTROL PORT
- 22 PCB LAYOUT RECOMMENDATIONS
- 8 Diagrams
- 8 Analog Input Interface Circuit
- 9 Typical Clamp Configuration
- 10 PLL Loop Filter Detail
- 11 Output Timing
- 12 4:2:2 Mode (For YUV Only)
- 20 Serial Port Read/Write Timing
- 21 Sync Processing Block Diagram