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Chapter 2 4S648/4S648N BIOS Setup
2.5 Advanced Chipset Features
This section allows you to configure the system based features of the installed chipset. This chipset manages bus speeds and access to system memory resources, such as
DRAM and external cache. It also coordinates communications of the PCI bus. It must be stated that these items should never be altered. The default settings are set up to provide the best operating conditions for your system. The time you might need to make any changes would be if you discover that data is lost while using your system.
Phoenix - AwardBIOS CMOS Setup Utility
Advanced Chipset Features
Item Help
DRAM Clock/Timing Control
DRAM Timing Control x DRAM CAS Latency x RAS Active Time x RAS Precharge Time x RAS to CAS Delay (tRCD)
DRAM Addr/Cmd Rate
AGP & P2P Bridge Control
AGP Aperture Size
Graphic Window WR Combin
Prefetch Caching
System BIOS Cacheable
Video RAM Cacheable
Memory Hole at 15M-16M
Press Enter
By SPD
2.5T
6T
3T
3T
Press Enter
64MB
Disabled
Disabled
Enabled
Enabled
Disabled
←→↑↓ : Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values F6:Fail-Safe Defaults F7:Optimized Defaults
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Chapter 2 4S648/4S648N BIOS Setup
DRAM Clock/Timing Control: Press <Enter> to reveal the following submenu.
DRAM iming Control
Use this item to select the DRAM Clock/Timing mode.
The Choices:
By SPD: DRAM Timing is by Serial Presence Detect (SPD) which is located on the memory module itself.
Manual: DRAM Timing is set manually with the options following this item below.
X DRAM CAS Latency
This item is to set CAS (Column Access Stroke) Latency time.
The Choices: Auto; 1.5; 2; 2.5;
X RAS Active ,Time
This item is to set Active to Precharge Delay cycle.
The Choices: Auto; 7; 6; 5
X DRAM RAS# to CAS# Delay (tRCD)
This item is to set the DRAM RAS (Row Access Stroke) to CAS
(Column Access Stroke) Delay cycle.
The Choices: Auto; 3; 2
X DRAM RAS# Precharge
This item is to set the DRAM RAS Precharge cycle.
The Choices: Auto; 3; 2
DRAM Addr/Cmd Rate
This item is to set the DRAM Addr/Command rate.
The Choices: Auto; 1T; 2T
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Chapter 2 4S648/4S648N BIOS Setup
AGP & P2P BBridge Control: Press <Enter> to reveal the following submenu.
AGP Aperture Size
Select the size of the Accelerated Graphic Port(AGP) aperture .
The aperture is a portion of the PCI memory address range dedicated for graphics memory address space. Host cycle that hit the aperture range are forwarded to the AGP without any translation.
The Choices: 128MB(default); 64MB,;32MB; 16MB; 8MB;
4MB; 256MB
Graphic Window WR Combin
Use this item to enable/disable the Graphic Window Write
Combin function.
The choices: Enabled; Disabled
Prefetch Caching
This item is to enable/disable the Prefetch Caching function.
The Choices: Enabled , Disabled.
System BIOS Cacheable
This item is to enable/disable the System BIOS Cacheable function.
Video RAM Cacheable
Enabled: Enable Video RAM Cacheable.
Disabled :Disable Video RAM Cacheable.
Memory Hole At 15-16M
In order to improve performace, certain space in memory can be reserved for ISA cards. This memory must be mapped into the memory's space below 16MB.
The Choices: Disabled; Enabled.
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