InsydeH2O BIOS Beep Codes. Acer 8431

InsydeH2O BIOS Beep Codes

Beeps

32h

33h

36h

38h

3Ah

3Ch

3Dh

42h

29h

2Ah

2Ch

2Eh

22h

24h

26h

28h

2Fh

30h

18h

1Ah

1Ch

20h

13h

14h

16h

17h

0Fh

10h

11h

12h

0Ah

0Bh

0Ch

0Eh

Code

02h

03h

04h

06h

08h

09h

1-2-2-3

1-3-1-1

1-3-1-3

1-3-4-1

1-3-4-3

1-4-1-1

POST Routine Description

Verify Real Mode

Disable Non-Maskable Interrupt (NMI)

Get CPU type

Initialize system hardware

Initialize chipset with initial POST values

Set IN POST flag

Initialize CPU registers

Enable CPU cache

Initialize caches to initial POST values

Initialize I/O component

Initialize the local bus IDE

Initialize Power Management

Load alternate registers with initial POST values

Restore CPU control word during warm boot

Initialize PCI Bus Mastering devices

Initialize keyboard controller

BIOS ROM checksum

Initialize cache before memory autosize

8254 timer initialization

8237 DMA controller initialization

Reset Programmable Interrupt Controller

Test DRAM refresh

Test 8742 Keyboard Controller

Set ES segment register to 4 GB

Enable A20 line

Autosize DRAM

Initialize POST Memory Manager

Clear 215 KB base RAM

RAM failure on address line xxxx

RAM failure on data bits xxxx of low byte of memory bus

Enable cache before system BIOS shadow

RAM failure on data bits xxxx of high byte of memory bus

Test CPU bus-clock frequency

Initialize InsydeH2O Dispatch Manager

Warm start shut down

Shadow system BIOS ROM

Autosize cache

Advanced configuration of chipset registers

Load alternate registers with CMOS values

Initialize interrupt vectors

Chapter 4

59

60

68h

69h

6Ah

6Bh

6Ch

6Eh

70h

72h

62h

64h

66h

67h

5Ah

5Bh

5Ch

60h

52h

54h

58h

59h

4Ch

4Eh

50h

51h

Code

45h

46h

48h

49h

4Ah

4Bh

81h

82h

83h

84h

76h

7Ch

7Eh

80h

85h

86h

87h

88h

89h

Beeps

2-1-2-3

2-2-3-1

POST Routine Description

POST device initialization

Check ROM copyright notice

Check video configuration against CMOS

Initialize PCI bus and devices

Initialize all video adapters in system

QuietBoot start (optional)

Shadow video BIOS ROM

Display BIOS copyright notice

Display CPU type and speed

Initialize EISA board

Test keyboard

Set key click if enabled

Test for unexpected interrupts

Initialize POST display service

Display prompt “Press F2 to enter SETUP”

Disable CPU cache

Test RAM between 512 and 640 KB

Test extended memory

Test extended memory address lines

Jump to User Patch1

Configure advanced cache registers

Initialize Multi Processor APIC

Enable external and CPU caches

Setup System Management Mode (SMM) area

Display external L2 cache size

Load custom defaults (optional)

Display shadow-area message

Display possible high address for UMB recovery

Display error messages

Check for configuration errors

Check for keyboard errors

Set up hardware interrupt vectors

Initialize coprocessor if present

Disable onboard Super I/O ports and IRQs

Late POST device initialization

Detect and install external RS232 ports

Configure non-MCD IDE controllers

Detect and install external parallel ports

Initialize PC-compatible PnP ISA devices

Re-initialize onboard I/O ports

Configure Motherboard Configurable Devices (optional)

Initialize BIOS Area

Enable Non-Maskable Interrupts (NMIs)

Chapter 4

Chapter 4

BEh

BFh

C0h

C1h

C2h

C3h

C4h

B4h

B5h

B6h

B9h

BAh

BBh

BCh

BDh

A2h

A4h

A8h

AAh

ACh

AEh

B0h

B2h

99h

9Ah

9Ch

9Dh

9Eh

9Fh

A0h

92h

93h

95h

96h

97h

98h

Code

8Ah

8Bh

8Ch

8Fh

90h

91h

Beeps

1-2

1

POST Routine Description

Initialize Extended BIOS Data Area

Test and initialize PS/2 mouse

Initialize floppy controller

Determine number of ATA drives (optional)

Initialize hard-disk controllers

Initialize local-bus hard-disk controllers

Jump to UserPatch2

Build MPTABLE for multi-processor boards

Install CD ROM for boot

Clear huge ES segment register

Fixup Multi Processor table

Search for option ROMs. One long, two short beeps on checksum failure.

Check for SMART drive (optional)

Shadow option ROMs

Set up Power Management

Initialize security engine (optional)

Enable hardware interrupts

Determine number of ATA and SCSI drives

Set time of day

Check key lock

Initialize Typematic rate

Erase F2 prompt

Scan for F2 key stroke

Enter SETUP

Clear Boot flag

Check for errors

POST done- prepare to boot operating system

One short beep before boot

Terminate QuietBoot (optional)

Check password (optional)

Prepare Boot

Initialize DMI parameters

Initialize PnP Option ROMs

Clear parity checkers

Display MultiBoot menu

Clear screen (optional)

Check virus and backup reminders

Try to boot with INT 19

Initialize POST Error Manager (PEM)

Initialize error logging

Initialize error display function

Initialize system error handler

61

62

F4h

F5h

F6h

F7h

F0h

F1h

F2h

F3h

E8h

E9h

EAh

EBh

ECh

EDh

EEh

EFh

E4h

E5h

E6h

E7h

E0h

E1h

E2h

E3h

Code

C5h

C6h

C7h

C8h

C9h

D2h

Beeps

1

POST Routine Description

PnPnd dual CMOS (optional)

Initialize notebook docking (optional)

Initialize notebook docking late

Force check (optional)

Extended checksum (optional)

Unknown interrupt

Initialize the chipset

Initialize the bridge

Initialize the CPU

Initialize the system timer

Initialize system I/O

Check force recovery boot

Checksum BIOS ROM

Go to BIOS

Set Huge Segment

Initialize Multi Processor

Initialize OEM special code

Initialize PIC and DMA

Initialize Memory type

Initialize Memory size

Shadow Boot Block

System memory test

Initialize interrupt vectors

Initialize Run Time Clock

Initialize video

Initialize System Management Mode

Output one beep before boot

Boot to Mini DOS

Clear Huge Segment

Boot to Full DOS

Chapter 4