- No category
advertisement
Document type:
User's Manual (MUT)
Title:
Mod. V1720 8 Channel 12bit - 250MS/s Digitizer
2.4. External connectors
2.4.1. ANALOG INPUT connectors
Revision date:
22/04/2013
Revision:
22
Fig. 2.2: MCX connector
Single ended version (see options in § 1.1):
Function:
Analog input, single ended, input dynamics: 2Vpp Zin=50
Mechanical specifications:
MCX connector (CS 85MCX-50-0-16 SUHNER)
Fig. 2.3: AMP Differential connector
Differential version (see options in § 1.1):
Function:
Analog input, differential, input dynamics: 2.25Vpp Zin=100
or 10Vpp Zin=1K
Mechanical specifications:
AMP 3-102203-4 AMP MODUII
2.4.2. CONTROL connectors
Function:
TRG OUT: Local trigger output (NIM/TTL, on Rt = 50
Ω)
TRG IN: External trigger input (NIM/TTL, Zin= 50
Ω)
SYNC/SAMPLE/START: Sample front panel input (NIM/TTL, Zin=50
Ω)
MON/
Σ: DAC output 1Vpp on Rt=50Ω
Mechanical specifications:
00-type LEMO connectors
NPO:
00103/05:V1720x.MUTx/22
Filename:
V1720_REV22
Number of pages: Page:
61 13
advertisement
* Your assessment is very important for improving the workof artificial intelligence, which forms the content of this project
Related manuals
advertisement
Table of contents
- 7 GENERAL DESCRIPTION
- 11 TECHNICAL SPECIFICATIONS
- 11 Supported VME Crates
- 11 Stand Alone operation
- 13 ANALOG INPUT connectors
- 13 CONTROL connectors
- 14 ADC REFERENCE CLOCK connectors
- 14 Digital I/O connectors
- 15 Optical LINK connector
- 16 Displays
- 20 FUNCTIONAL DESCRIPTION
- 20 Single ended input
- 20 Differential input
- 22 Direct Drive Mode
- 22 PLL Mode
- 22 Trigger Clock
- 22 Output Clock
- 22 AD9510 programming
- 23 Configuration file
- 23 Multiboard synchronization
- 24 Acquisition run/stop
- 24 Acquisition Triggering: Samples and Events
- 26 Custom size events
- 26 Event structure
- 26 Header
- 26 Samples
- 27 Event format examples
- 30 Acquisition Synchronization
- 31 Zero Suppression Algorithm
- 31 Full Suppression based on the amplitude of the signal
- 32 Zero Length Encoding ZLE
- 33 Zero Suppression Examples
- 37 External trigger
- 37 Software trigger
- 38 Local channel auto-trigger
- 39 Trigger coincidence level
- 41 Trigger distribution
- 44 Mode 0: REGISTER
- 44 Mode 1: TRIGGER
- 44 Mode 2: nBUSY/nVETO
- 44 nBusy signal
- 44 nVETO signal
- 44 nTrigger signal
- 45 nRun signal
- 45 Mode 3: OLD STYLE
- 45 nClear_TTT signal
- 45 Busy signal
- 45 DataReady signal
- 45 Trigger signal
- 45 Run signal
- 46 Trigger Majority Mode (Monitor Mode = 0)
- 47 Test Mode (Monitor Mode = 1)
- 47 Buffer Occupancy Mode (Monitor Mode = 3)
- 47 Voltage Level Mode (Monitor Mode = 4)
- 48 Global Reset
- 48 Memory Reset
- 48 Timer Reset
- 49 Addressing capabilities
- 49 Base address
- 49 CR/CSR address
- 50 Address relocation
- 51 Sequential readout
- 51 SINGLE D
- 52 BLOCK TRANSFER D32/D64, 2eVME
- 53 CHAINED BLOCK TRANSFER D32/D
- 53 Random readout (to be implemented)
- 55 SOFTWARE TOOLS
- 58 INSTALLATION
- 60 V1720 Upgrade files description
- 61 TECHNICAL SUPPORT