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Document type:
User's Manual (MUT)
3.3.3.3.
Title:
Mod. V1720 8 Channel 12bit - 250MS/s Digitizer
Event format examples
Revision date:
22/04/2013
Revision:
22
The event format is shown in the following figure (case of 8 channels enabled, with Zero
Length Encoding disabled and enabled respectively; see § 3.3.3.1 and § 3.4.1.2):
An event is structured as follows:
identifier (Trigger Time Tag, Event Counter)
samples caught in the acquisition windows
The event can be stored in the board memories (and can be readout via VME) in two ways: data format is 32 bit long word, and each long_word may contain 2 samples
(Standard mode) or “two and a half” (Pack2.5 mode), depending on Channel
Configuration register setting.
The event formats are described in Fig. 3.5, Fig. 3.6, Fig. 3.7 and Fig. 3.8:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 0 1 0 EVENT SIZE reserved
0 0
0 0
0 0
0 0
SAMPLE [1] – CH[0]
SAMPLE [3] – CH[0]
EVENT COUNTER
TRIGGER TIME TAG
0 0
0 0
0 0
0 0
SAMPLE [0] – CH[0]
SAMPLE [2] – CH[0]
0 0
0 0
0 0
0 0
0 0
0 0
SAMPLE [N-1] – CH[0]
SAMPLE [1] – CH[1]
SAMPLE [3] – CH[1]
0 0 0 0 SAMPLE [N-1] – CH[1]
0 0
0 0
0 0
0 0
0 0
0 0
SAMPLE [N-2 ] – CH [0]
SAMPLE [0] – CH[1]
SAMPLE [2] – CH[1]
0 0 0 0 SAMPLE [N-2 ] – CH [1]
0 0
0 0
0 0
0 0
SAMPLE [1] – CH[7]
SAMPLE [3] – CH[7]
0 0
0 0
0 0
0 0
SAMPLE [0] – CH[7]
SAMPLE [2] – CH[7]
0 0 0 0
SAMPLE [N-1] – CH[7]
0 0 0 0
SAMPLE [N-2 ] – CH [7]
Fig. 3.5: Event Organization (standard mode), normal format
NPO:
00103/05:V1720x.MUTx/22
Filename:
V1720_REV22
Number of pages: Page:
61 27
Document type:
User's Manual (MUT)
Title:
Mod. V1720 8 Channel 12bit - 250MS/s Digitizer
Revision date:
22/04/2013
Revision:
22
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 0 1 0
0 0
0 0 reserved
S [2] – CH[0] L
S [4] – CH[0] H
EVENT SIZE
CHANNEL MASK
EVENT COUNTER
TRIGGER TIME TAG
S [1] – CH[0] H
S [4] – CH[0] L
S [1] – CH[0] L
S [3] – CH[0] H
S [0] – CH[0] H
S [3] – CH[0] L
S [0] – CH[0] L
S [2] – CH[0] H
0 0
0 0
0 0
S[ N ] – CH[0] H
S [2] – CH[1] L
S [4] – CH[1] H
S[ N ] – CH[0] L
S [1] – CH[1] H
S [4] – CH[1] L
S[ N-1 ] – CH[0] H
S [1] – CH[1] L
S [3] – CH[1] H
S[ N-1
] – CH[0]
L
S [0] – CH[1] H
S [3] – CH[1] L
S[ N-2
] – CH[0]
H
S [0] – CH[1] L
S [2] – CH[1] H
0 0
S[
N
] – CH[1] H
S[
N
] – CH[1] L S[
N-1
] – CH[1] H
S[
N-1
] – CH[1]
L
S[
N-2
] – CH[1]
H
0 0
0 0
S [2] – CH[7] L
S [4] – CH[7] H
S [1] – CH[7] H
S [4] – CH[7] L
S [1] – CH[7] L
S [3] – CH[7] H
S [0] – CH[7] H
S [3] – CH[7] L
S [0] – CH[7] L
S [2] – CH[7] H
0 0
S[ N ] – CH[7] H
S[ N ] – CH[7] L S[ N-1 ] – CH[7] H S[
N-1
] – CH[7]
L
S[
N-2
] – CH[7]
H
Fig. 3.6:Event Organization (Pack2.5 mode), normal format
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 0 1 0
BOARD-ID reserved
Res.
0 0 0 0 SAMPLE
1
[1] – CH[0]
PATTERN
EVENT SIZE
EVENT COUNTER
TRIGGER TIME TAG
SIZE
CONTROL WORD
0 0 0 0 SAMPLE
CHANNEL MASK
[0] – CH[0]
0 0
0 0
SAMPLE [N-1] – CH[0]
0 0
0 0
SAMPLE [1] – CH[1]
0 0
0 0 SAMPLE [N-1] – CH[1]
CONTROL WORD
0 0
SIZE
CONTROL WORD
0 0
0 0
SAMPLE [N-2] – CH [0]
SAMPLE [0] – CH[1]
CONTROL WORD
0 0 0 0
SAMPLE [N-2] – CH [1]
0 0
0 0 SAMPLE [1] – CH[7]
SIZE
CONTROL WORD
0 0
0 0 SAMPLE [0] – CH[7]
0 0 0 0
SAMPLE [N-1] – CH[7]
CONTROL WORD
0 0 0 0 SAMPLE [N-2] – CH [7]
Fig. 3.7: Event Organization (standard mode), Zero Length Encoding
NPO:
00103/05:V1720x.MUTx/22
Filename:
V1720_REV22
Number of pages: Page:
61 28
Document type:
User's Manual (MUT)
Title:
Mod. V1720 8 Channel 12bit - 250MS/s Digitizer
Revision date:
22/04/2013
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5
Revision:
22
4 3 2 1 0
1 0 1
BOARD ID
0
RESERVED
RES.
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
S(2) - CH(0) L
S(4) - CH(0) H
S(N-2) - CH(0) L
S(N) - CH(0) H
S(2) - CH(1) L
S(4) - CH(1) H
S(N-2) - CH(1) L
S(N) - CH(1) H
S(1) - CH(0) H
S(4) - CH(0) L
S(N-3) - CH(0) H
S(N) - CH(0) L
S(1) - CH(1) H
S(4) - CH(1) L
S(N-3) - CH(1) H
S(N) - CH(1) L
EVENT SIZE
PATTERN
EVENT COUNTER
TRIGGER TIME TAG
SIZE
CONTROL WORD
S(1) - CH(0) L
S(3) - CH(0) H
…..
CONTROL WORD
S(N-3) - CH(0) L
S(N-1) - CH(0) H
SIZE
CONTROL WORD
S(1) - CH(1) L
S(3) - CH(1) H
…..
CONTROL WORD
S(N-3) - CH(1) L
S(N-1) - CH(1) H
…..
S(0) - CH(0) H
S(3) - CH(0) L
S(N-4) - CH(0) H
S(N-1) - CH(0) L
S(0) - CH(1) H
S(3) - CH(1) L
S(N-4) - CH(1) H
S(N-1) - CH(1) L
CHANNEL MASK
S(0) - CH(0) L
S(2) - CH(0) H
S(N-4) - CH(0) L
S(N-2) - CH(0) H
S(0) - CH(1) L
S(2) - CH(1) H
S(N-4) - CH(1) L
S(N-2) - CH(1) H
0
0
0
0
0
0
0
0
S(2) - CH(7) L
S(4) - CH(7) H
S(N-2) - CH(7) L
S(N) - CH(7) H
S(1) - CH(7) H
S(4) - CH(7) L
S(N-3) - CH(7) H
S(N) - CH(7) L
SIZE
CONTROL WORD
S(1) - CH(7) L
S(3) - CH(7) H
…..
CONTROL WORD
S(N-3) - CH(7) L
S(N-1) - CH(7) H
S(0) - CH(7) H
S(3) - CH(7) L
S(N-4) - CH(7) H
S(N-1) - CH(7) L
Fig. 3.8: Event Organization (Pack2.5 mode), Zero Length Encoding
S(0) - CH(7) L
S(2) - CH(7) H
S(N-4) - CH(7) L
S(N-2) - CH(7) H
NPO:
00103/05:V1720x.MUTx/22
Filename:
V1720_REV22
Number of pages: Page:
61 29
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Table of contents
- 7 GENERAL DESCRIPTION
- 11 TECHNICAL SPECIFICATIONS
- 11 Supported VME Crates
- 11 Stand Alone operation
- 13 ANALOG INPUT connectors
- 13 CONTROL connectors
- 14 ADC REFERENCE CLOCK connectors
- 14 Digital I/O connectors
- 15 Optical LINK connector
- 16 Displays
- 20 FUNCTIONAL DESCRIPTION
- 20 Single ended input
- 20 Differential input
- 22 Direct Drive Mode
- 22 PLL Mode
- 22 Trigger Clock
- 22 Output Clock
- 22 AD9510 programming
- 23 Configuration file
- 23 Multiboard synchronization
- 24 Acquisition run/stop
- 24 Acquisition Triggering: Samples and Events
- 26 Custom size events
- 26 Event structure
- 26 Header
- 26 Samples
- 27 Event format examples
- 30 Acquisition Synchronization
- 31 Zero Suppression Algorithm
- 31 Full Suppression based on the amplitude of the signal
- 32 Zero Length Encoding ZLE
- 33 Zero Suppression Examples
- 37 External trigger
- 37 Software trigger
- 38 Local channel auto-trigger
- 39 Trigger coincidence level
- 41 Trigger distribution
- 44 Mode 0: REGISTER
- 44 Mode 1: TRIGGER
- 44 Mode 2: nBUSY/nVETO
- 44 nBusy signal
- 44 nVETO signal
- 44 nTrigger signal
- 45 nRun signal
- 45 Mode 3: OLD STYLE
- 45 nClear_TTT signal
- 45 Busy signal
- 45 DataReady signal
- 45 Trigger signal
- 45 Run signal
- 46 Trigger Majority Mode (Monitor Mode = 0)
- 47 Test Mode (Monitor Mode = 1)
- 47 Buffer Occupancy Mode (Monitor Mode = 3)
- 47 Voltage Level Mode (Monitor Mode = 4)
- 48 Global Reset
- 48 Memory Reset
- 48 Timer Reset
- 49 Addressing capabilities
- 49 Base address
- 49 CR/CSR address
- 50 Address relocation
- 51 Sequential readout
- 51 SINGLE D
- 52 BLOCK TRANSFER D32/D64, 2eVME
- 53 CHAINED BLOCK TRANSFER D32/D
- 53 Random readout (to be implemented)
- 55 SOFTWARE TOOLS
- 58 INSTALLATION
- 60 V1720 Upgrade files description
- 61 TECHNICAL SUPPORT