Directly Addressable Console Hardware. DEC AlphaServer 8400, AlphaServer 8200

TLEPMERR register, 7-59

TLEP_VMG register, 7-62

TLESR0-3 registers, 7-26

TLFADR0-1 registers, 7-24

TLILID0-3 registers, 7-30

TLINTRMASK register, 7-63

TLINTRSUM register, 7-65

TLIOINTR4-8 registers, 7-36

TLIPINTR register, 7-35

TLMBPR register, 7-32

TLMBPR register map, 6-15

TLMCR register, 7-43

TLMMR0-7 registers, 7-21

TLMODCONFIG register, 7-52

TLRDRD register, 2-33, 7-41

TLRDRE register, 7-42

TLRMDQRX register, 7-39

TLRMDQR8 register, 7-40

TLSB address transmit check errors, 6-70

TLSB arbitration, 2-2, 6-30

TLSB architecture, 1-2

TLSB Bad bit, 7-77

TLSB bank available flags, 5-4

TLSB bank match logic, 5-3

TLSB bus monitor, 5-2

TLSB command decode, 5-2

TLSB command encoding, 5-3

TLSB Conwin bit, 7-77

TLSB CSR address mapping, 2-29

TLSB CSR control, memory, 5-14

TLSB CSR space, 3-8

TLSB CSR space map, 3-8

TLSB errors, 2-33

TLSB error handling, 2-2

TLSB input latches, 5-2

TLSB interface, CPU, 1-4

TLSB interface, I/O port, 6-23

TLSB mailboxes, 2-30

TLSB memory control, 5-1

TLSB Node ID bits, 7-77

TLSB operation, 2-5

TLSB overview, 2-1

TLSB principles for interrupts, 8-3

TLSB quadword transmit on hose, 6-20

TLSB register list, 7-4

TLSB Run bit, 7-80

TLSB signals, 2-3

TLSB status, additional, 6-74

TLSB transactions, 2-2

TLSB Window Overflow bit, 7-118

TLSB wrapping, 3-7

TLSB_ADR<2:0>, 6-17

TLSB_ADR<31:5>, 6-17, 6-19

TLSB_ADR<33:32>, 6-17, 6-19, 6-21

TLSB_ADR<35:34>, 6-17, 6-19, 6-21

TLSB_ADR<38:36>, 6-17, 6-19, 6-21

Index-12

TLSB_ADR<39>, 6-17, 6-19, 6-21

TLSB_ADR<4:0>, 6-19

TLSB_ADR<4:3>, 6-17

TLSB_BAD, 7-77

TLSB_BANK_NUM<3:0>, 6-17, 6-19

TLSB_BANK_NUM<<3:0>, 6-21

TLSB_CONWIN, 7-77

TLSB_DATA_ERR, 6-67

TLSB_DATA_ERROR Disable bit, 7-99

TLSB_DATA_VALID, 2-22

TLSB_DIRTY, 2-23

TLSB_FAULT, 6-68

TLSB_LOCKOUT, 2-24

TLSB_RESET, 2-24

TLSB_RUN, 7-80

TLSB_SECURE, 7-80

TLSB_SHARED, 2-22

TLSB_STATCHK, 2-23

TLSB_WND_OFLO, 7-118

TLVID register, 7-19

TLWSDQR4-8 registers, 7-38

Toggle mode, 6-32

Transactions extended NVRAM, 6-13

I/O port, 6-3, 6-23, 6-28

Transactions, address bus, 2-12

Transactions, dense address space, 6-20

Transactions, DMA, 6-24

Transactions, DMA interlock read, 6-10

Transactions, DMA masked write, 6-26

Transactions, DMA read, 6-10, 6-24

Transactions, DMA unmasked write, 6-26

Transactions, DMA write, 6-11

Transactions, extended NVRAM write, 6-30

Transactions, integrated I/O section, 6-83

Transactions, interrupt, 6-26

Transactions, I/O window space read, 6-29

Transactions, I/O window space write, 6-29

Transactions, mailbox, 6-28

Transactions, memory, 4-16

Transactions, module, 2-12

Transaction types

I/O port, 6-5

I/O port supported, 6-24

Translation buffer, 3-2

Transmitter During Error bit, 7-28

Transmit check errors, 2-41, 3-17, 6-74

Transmit Check Error bit, 7-27

Transmit Data bit, 7-84

Transmit Serial Data bit, 7-86, 7-141

Turbo Vortex errors, 6-75, 6-76

U

UACKE, 7-8

UDE, 7-10