STMicroelectronics ST8034HC Datasheet

ST8034HN, ST8034HC
24-pin smartcard interfaces
Datasheet - production data
 Automatic activation and deactivation
sequences initiated by the microcontroller
 Emergency deactivation sequences initiated
by a card supply short-circuit, card take-off,
falling VDD, VDDP, or VDD(INTF) or by the
interface device overheating
 Voltage supply supervisors
– with a fixed threshold (VDD, VDDP)
– with an external resistor divider to set the
VDD(INTF) threshold (PORADJ pin)
 Multipurpose card status signal OFF
 Non-inverted card reset pin RST driven by the
RSTIN input
QFN24 4 x 4 x 0.8 mm
 Thermal and short-circuit protection of all card
contacts
 Card presence detection contacts debounced
 Enhanced card side ESD protection of 8 kV
Features
 Space saving QFN24 4 x 4 x 0.8 mm package
 Complete smartcard interface
 ISO 7816, NDS and EMV 4.3 payment systems
compatible
 Three protected half-duplex bidirectional
buffered I/O lines to the smartcard
 Temperature range -25 to +85 °C
Applications
Smartcard readers for
 5 V, 3 V or 1.8 V supply voltage for the
smartcard (VCC), pin-selectable. Ensures
controlled VCC rise and fall times and provides
smart overload detection with glitch immunity.
 Set-top boxes
 Very low power consumption in deep shutdown
mode
 Banking
 Pay-TV
 Identification
 Tachographs
 Chip select function allows the device interface
to be isolated from the microcontroller signals allows parallel combination of the card
interface devices (ST8034HC)
 Card clock generation by integrated crystal
oscillator or from external clock source
 Card clock frequency up to 20 MHz,
programmable by CLKDIV1 and CLKDIV2 pins
(ST8034HN) or by CLKDIV pin (ST8034HC),
with synchronous frequency changes
October 2013
This is information on a product in full production.
DocID024511 Rev 2
1/31
www.st.com
1
Contents
ST8034HN, ST8034HC
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Electrical characteristics over recommended operating conditions . . . . . . . . . . . 11
6
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.1
Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.2
Voltage supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.3
Clock circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.4
Input and output circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.5
Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.6
Deep shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.7
Activation sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.8
Deactivation sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.9
VCC generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.10
Fault detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.11
VCC_SEL pin-programmed card supply voltage (VCC) . . . . . . . . . . . . . . 27
6.12
Chip select (ST8034HC only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8
Tape and reel information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2/31
DocID024511 Rev 2
ST8034HN, ST8034HC
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description ST8034HN and ST8034HC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Absolute maximum ratings, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Supply voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Card interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Microcontroller interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Clock circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Protection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Clock frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
VCC selection by VCC_SEL1, VCC_SEL2 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
QFN24 4 x 4 x 0.8 mm, 0.5 mm pitch package mechanical data, . . . . . . . . . . . . . . . . . . . 29
Tape and reel specification for QFN24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
DocID024511 Rev 2
3/31
List of figures
ST8034HN, ST8034HC
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
4/31
Block diagram ST8034HN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Block diagram ST8034HC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin connections ST8034HN (top-through view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin connections ST8034HC (top-through view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Definition of duty cycle and input and output rise/fall times . . . . . . . . . . . . . . . . . . . . . . . . 18
Voltage supervisor, configured with adjustable VDD(INTF) threshold. . . . . . . . . . . . . . . . . . 19
Voltage supervisor waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
External clock usage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Shutdown and deep shutdown mode activation and deactivation . . . . . . . . . . . . . . . . . . . 23
Activation sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Deactivation sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Deactivation sequence after card removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Debounce at OFF, CMDVCC, PRES and VCC pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
QFN24 4 x 4 x 0.8 mm, 0.5 mm pitch package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
QFN24 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Carrier tape for QFN24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
DocID024511 Rev 2
ST8034HN, ST8034HC
1
Description
Description
The ST8034HN and ST8034HC devices are complete low-cost analog interfaces for
asynchronous and synchronous smartcards operating at a supply voltage of 5 V, 3 V or
1.8 V. The ST8034HN and ST8034HC devices can be placed between the card and the
microcontroller to provide all supply, protection, detection and control functions, with just
a few external components.
Table 1. Device summary
VCC
Chip CLKDIV
NDS
selection
select inputs compliant
pins
Order code
PORADJ
ST8034HNQR


ST8034HCQR



Package
Shipment
Package
topmark
2

QFN24
4 x 4 x 0.85 mm,
0.5 mm pitch
Tape and
reel
8034HN
1

QFN24
4 x 4 x 0.85 mm,
0.5 mm pitch
Tape and
reel
8034HC
DocID024511 Rev 2
5/31
Block diagrams
2
ST8034HN, ST8034HC
Block diagrams
Figure 1. Block diagram ST8034HN
Q)
9''
9'',17)
5
567,1
&0'9&&
2))
&/.',9
&/.',9
9&&B6(/
9&&B6(/
,28&
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9''3
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5()(5(1&(
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Q)
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6(16(
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26&,//$725
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/'2
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5(6(7
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*(1(5$725
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Q)
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&/.
(1
Q)
/(9(/
6+,)7(5
&5<67$/
26&,//$725
7+(50$/
3527(&7,21
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,2
75$16&(,9(5
,2
,2
75$16&(,9(5
$8;
,2
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&
&
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&
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;7$/ ;7$/
9'',17)
$09
1. Optional external resistor divider. If not used, connect the PORADJ pin to VDD(INTF) for a direct VDD(INTF) voltage
monitoring.
6/31
DocID024511 Rev 2
ST8034HN, ST8034HC
Block diagrams
Figure 2. Block diagram ST8034HC
Q)
9''
9'',17)
35(6
567,1
&0'9&&
2))
&/.',9
9&&B6(/
9&&B6(/
,28&
$8;8&
$8;8&
,17(51$/
5()(5(1&(
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9''3
*1'
6833/<
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Q)
&+,3
6(/(&7
92/7$*(
6(16(
,17(51$/
26&,//$725
&/.83
$/$50
(1
39&&
6(48(1&(5
(1
&/2&.
&,5&8,7
9&&
5(6(7
*(1(5$725
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&/2&.
*(1(5$725
&/.
/(9(/
6+,)7(5
&/.
&5<67$/
26&,//$725
(1
7+(50$/
3527(&7,21
67+&
Q)
Q)
(1
9&&
/'2
,2
75$16&(,9(5
,2
,2
75$16&(,9(5
$8;
,2
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&$5'
&211(&725
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;7$/ ;7$/
9'',17)
$09
1. Optional external resistor divider. If not used, connect the PORADJ pin to VDD(INTF) for a direct VDD(INTF) voltage
monitoring.
DocID024511 Rev 2
7/31
Pin description
3
ST8034HN, ST8034HC
Pin description
Figure 3. Pin connections ST8034HN (top-through view)
$8;8& $8;8&
;7$/
,28&
;7$/
2))
9'',17)
325$'-
9&&B6(/
9''
567,1
9''3
9&&B6(/
9&&
&0'9&&
567
&/.',9
&/.
67+1
&/.',9
,2 $8; *1'
$8;
35(6
4)1[[PPPPSLWFK7KHUPDOSDGQRWFRQQHFWHG
$09
Figure 4. Pin connections ST8034HC (top-through view)
$8;8& $8;8&
;7$/
,28&
;7$/
2))
9'',17)
325$'-
9&&B6(/
9''
567,1
9''3
9&&B6(/
9&&
&0'9&&
567
&6
&/.
67+&
&/.',9
,2 $8; *1'
$8;
35(6
4)1[[PPPPSLWFK7KHUPDOSDGQRWFRQQHFWHG
$09
8/31
DocID024511 Rev 2
ST8034HN, ST8034HC
Pin description
Table 2. Pin description ST8034HN and ST8034HC
Pin
number
Symbol
Ref. supply
1
VDD(INTF)
VDD(INTF)
Microcontroller interface supply voltage
2
VCC_SEL2
VDD(INTF)
VCC selection control signal 5 V or 3 V (see Table 13 on page 27)
3
RSTIN
VDD(INTF)
Card reset input from microcontroller; active high
4
VCC_SEL1
VDD(INTF)
VCC selection control signal 1.8 V, overrides VCC_SEL2 (see Table 13 on
page 27)
5
CMDVCC
VDD(INTF)
Activation sequence start, input (from microcontroller, active low)
CLKDIV1
VDD(INTF)
CLK frequency division control input (together with CLKDIV2), see Table 12
on page 21 (ST8034HN)
CS
VDD(INTF)
Chip select input. High = device active, low = all microcontroller interface
pins in high impedance (ST8034HC)
CLKDIV2
VDD(INTF)
CLK frequency division control (together with CLKDIV1), see Table 12 on
page 21 (ST8034HN)
CLKDIV
VDD(INTF)
CLK frequency division control, see Table 12 on page 21 (ST8034HC)
8
PRES
VDD(INTF)
Card presence input (active low: PRES low = card is present). Debounced.
9
I/O
VCC
Card input/output data line (C7); internal 9 k pull-up resistor to VCC
10
AUX1
VCC
Auxiliary card input/output data line (C4); internal 9 k pull-up resistor to
VCC
11
AUX2
VCC
Auxiliary card input/output data line (C8); internal 9 k pull-up resistor to
VCC
12
GND
13
CLK
VCC
Clock to card (C3)
14
RST
VCC
Card reset, output (C2)
15
VCC
Supply voltage for the card, output (C1)
16
VDDP
LDO supply voltage input (for VCC generation)
17
VDD
Control logic supply voltage input
18
PORADJ
VDD(INTF)
Power-on reset threshold adjustment input (with an optional external
resistor divider)
19
OFF
VDD(INTF)
Interrupt to microcontroller (active low output); internal 20 k pull-up
resistor to VDD(INTF)
20
I/OUC
VDD(INTF)
Microcontroller data I/O line (with internal 10 k pull-up resistor connected
to VDD(INTF))
21
AUXUC1
VDD(INTF)
Auxiliary microcontroller input/output data line; internal 10 k pull-up
resistor to VDD(INTF)
22
AUXUC2
VDD(INTF)
Auxiliary microcontroller input/output data line; internal 10 k pull-up
resistor to VDD(INTF)
23
XTAL1
VDD
Crystal or external clock input
24
XTAL2
VDD
Crystal connection (leave this pin open if external clock is used)
6
7
Function
Ground
DocID024511 Rev 2
9/31
Maximum ratings
4
ST8034HN, ST8034HC
Maximum ratings
Table 3. Absolute maximum ratings(1), (2)
Symbol
Parameter
Min.
Max. Unit
VDD
Supply voltage, logic
-0.3
6
V
VDDP
Supply voltage, power
-0.3
6
V
Supply voltage, interface
-0.3
6
V
Input voltage on XTAL1, XTAL2, RSTIN, I/OUC, AUX1UC,
AUX2UC, CLKDIV1, CLKDIV2, CS, VCC_SEL1, VCC_SEL2,
PORADJ, CMDVCC, OFF, PRES, I/O, AUX1, and AUX2 pins
-0.3
6
V
Human body model (HBM) on card lines - I/O, RST, VCC, CLK,
and PRES pins
-8
8
kV
Human body model (HBM), all other pins
-2
2
kV
Machine model (MM), all pins
-200
200
V
VESD (FCDM) Field charged device model (FCDM), all pins
-500
500
V
Total power dissipation (TA = -25 to +85 °C)
0.25
W
Maximum operating junction temperature
125
°C
150
°C
VDD(INTF)
VIN
VESD (HBM)
VESD (MM)
PTOT
TJ(MAX)
TSTG
Storage temperature range
-55
1. Absolute maximum ratings are those values beyond which damage to the device may occur. Functional
operation under these conditions is not implied.
2. All card contacts are protected against short-circuit to any other card contact.
Table 4. Thermal data
Symbol
RTHJA
Parameter
Thermal resistance junction-ambient temperature
(multilayer test board - JEDEC standard)
Test
conditions
Typ.
Unit
QFN24
47
°C/W
Min.
Max.
Unit
-25
85
°C
Table 5. Recommended operating conditions
Symbol
TA
10/31
Parameter
Test conditions
Ambient temperature range
DocID024511 Rev 2
ST8034HN, ST8034HC
5
Electrical characteristics
Electrical characteristics
Electrical characteristics over recommended operating conditions
Table 6. Supply voltages
Symbol
Test conditions(1)
Parameter
Min.
Typ.
Max.
Unit
2.7
3.3
3.6(2)
V
4.85
5
5.5
3
3.3
5.5
1.6
3.3
VDD
+0.3(3)
Device supply voltages
VDD
Supply voltage, logic
VDDP
Supply voltage, power
VDD(INTF)
IDD
IDDP
IDD(INTF)
VCC = 5 V
VCC = 3 V or 1.8 V
Supply voltage,
microcontroller interface
Supply current, logic
Supply current, power
Supply current, interface
V
V
Shutdown mode
35
Deep shutdown mode
12
Active mode
2
mA
Shutdown mode, fXTAL stopped
5
A
A
Active mode, fCLK = fXTAL/2, no ICC load
1.5
Active mode, fCLK = fXTAL/2, ICC = 65 mA
70
Shutdown mode
6
A
Active mode
2
mA
mA
Card supply voltage
VCC
ICC
CVCC
SR
Card supply voltage
(output)(4)
Card supply current (refer
also to Table 10: Protection
characteristics on page 17)
Active mode, VCC = 5 V, ICC < 65 mA
4.75
5.0
5.25
With current pulses of 40 nAs at
ICC < 200 mA, t < 400 ns(5)
4.65
5.0
5.25
Active mode, VCC = 3 V, ICC < 65 mA
2.85
3.05
3.15
With current pulses of 40 nAs at
ICC < 200 mA, t < 400 ns(5)
2.76
Active mode, VCC = 1.8 V, ICC < 65 mA
1.71
With current pulses of 15 nAs at
ICC < 200 mA, t < 400 ns(5)
1.66
1.83
VCC shorted to GND
1.89
65
90
120
150
160
320
530
VCC = 5 V
0.055 0.180
0.300
VCC = 3 V
0.040 0.180
0.300
VCC = 1.8 V
0.025 0.180
0.300
DocID024511 Rev 2
V
1.94
VCC = 5 V, 3 V or 1.8 V
VCC decoupling capacitor (4) VCC to GND
VCC slew rate (rising or
falling)(4)
3.20
mA
nF
V/s
11/31
Electrical characteristics
ST8034HN, ST8034HC
Table 6. Supply voltages (continued)
Symbol
Test conditions(1)
Parameter
VCC(SHDN)
VCC output voltage in
shutdown mode
ICC(SHDN)
VCC output current in
shutdown mode
Min.
Typ.
Max.
No load
-0.1
0.1
ICC = 1 mA
-0.1
0.3
VCC connected to GND
-1
Unit
V
mA
Device supply voltages monitoring
VTH
VHYS
Falling supply voltage
threshold
Hysteresis on supply
voltage threshold
VDD pin
2.3
2.4
2.5
VDDP pin (VCC = 5 V)
3.0
4.1
4.4
VDDP pin (VCC = 3 V or 1.8 V)
2.3
2.4
2.5
PORADJ pin
1.20
1.24
1.29
VDD pin
50
100
150
VDDP pin (VCC = 5 V)
100
200
350
VDDP pin (VCC = 3 V or 1.8 V)
50
100
150
PORADJ pin
10
20
30
II(PORADJ) Input current, PORADJ pin
tW
-1
Power-on or undervoltage
reset pulse width (minimum)
5.1
8
V
mV
1
A
10.2
ms
1. TA = 25 °C, VDD = 3.3 V, VDDP = 5 V, VDD(INTF) = 3.3 V, fXTAL = 10 MHz, unless otherwise noted.
2. The device can operate at VDD supply voltage up to 5.5 V, however the specified parameters (mainly related to current
consumption) are guaranteed in the basic VDD range 2.7 to 3.6 V.
3. The device can operate at VDD(INTF) supply voltage up to 5.5 V, however the specified parameters (mainly related to current
consumption and input currents) are guaranteed in the basic VDD(INTF) range 1.6 to 3.6 V.
4. Two low ESR (< 350 m) ceramic capacitors for VCC decoupling recommended: 100 nF ± 20% (up to 330 nF ± 20%) close
to the ST8034 and 100 nF ± 20% (up to 330 nF ± 20%) close to the card.
5. These current pulses are filtered by the decoupling capacitors on the VCC pin, therefore for the LDO just the mean value
matters.
12/31
DocID024511 Rev 2
ST8034HN, ST8034HC
Electrical characteristics
Table 7. Card interface
Symbol
Test conditions(1)
Parameter
Min.
Typ.
Max.
Unit
200
ns
400
ns
Data lines to the card (I/O, AUX1, AUX2 pins)(2)
tD
tW(PU)
Delay time
Falling edge on pin I/O to falling
edge on I/OUC or vice versa
Pull-up pulse width
100
fIO
Input/output frequency
1
MHz
CI
Input capacitance
10
pF
VO
Output voltage in
shutdown mode
IO
Output current in
shutdown mode
VOL
VOH
Output voltage low
Output voltage high
No load
0
0.1
V
IO = 1 mA
0
0.3
V
-1
mA
I/O connected to GND
IOL = 1 mA
0
0.3
VCC - 0.4
VCC
No load
0.9 VCC
VCC + 0.1
IOH < -40 A, 5 V or 3 V
0.75 VCC
VCC + 0.1
IOH < -20 A, 1.8 V
0.75 VCC
VCC + 0.1
0
0.4
-0.3
0.8
VCC = 5 V
0.6 VCC
VCC + 0.3
VCC = 3 V or 1.8 V
0.7 VCC
VCC + 0.3
IOL  15 mA (current limit)
IOH  -15 mA (current limit)
VIL
Input voltage low
VIH
Input voltage high
V
V
V
Hysteresis
I/O pin
IIL
Input current low
I/O pin, VIL = 0 V
750
A
IIH
Input current high
I/O pin, VIH = VCC
10
A
tR(I)
Input rise time
VIL max. to VIH min.
0.15
s
tR(O)
Output rise time
CL  80 pF, 10% to 90%, 0 V to VCC
0.1
s
tF(I)
Input fall time
VIL max. to VIH min.
0.15
s
tF(O)
Output fall time
CL  80 pF, 10% to 90%, 0 V to VCC
0.1
s
RPU
Pull-up resistance to VCC
7
9
11
k
IPU
Pull-up current (one-shot
VOH = 0.9 VCC
circuit active)
-8
-6
-4
mA
VHYS
50
V
mV
Reset output to the card (RST pin)
No load
0
0.1
IO = 1 mA
0
0.3
VO
Output voltage in
shutdown mode
IO
Output current in
shutdown mode
RST connected to GND
-1
mA
tD
Delay time
Between RSTIN and RST; RST
enabled
2
s
DocID024511 Rev 2
V
13/31
Electrical characteristics
ST8034HN, ST8034HC
Table 7. Card interface (continued)
Symbol
VOL
VOH
Test conditions(1)
Parameter
Output voltage low
Output voltage high
Min.
Typ.
Max.
IOL = 200 A, VCC = 5 V
0
0.3
IOL = 200 A, VCC = 3 V or 1.8 V
0
0.2
IOL = 20 mA (current limit)
VCC - 0.4
VCC
IOH = -200 A
0.9 VCC
VCC
0
0.4
IOH = -20 mA (current limit)
tR
Rise time
CL = 100 pF
0.1
tF
Fall time
CL = 100 pF
0.1
Unit
V
V
s
Clock output to the card (CLK pin)
VO
Output voltage in
shutdown mode
IO
Output current in
shutdown mode
VOL
Output voltage low
VOH
Output voltage high
tR
tF
Rise time(3)
Fall
time(3)
No load
0
0.1
IO = 1 mA
0
0.3
CLK connected to GND
-1
IOL = 200 A
0
0.3
IOL = 70 mA (current limit)
VCC - 0.4
VCC
IOH = -200 A
0.9 VCC
VCC
0
0.4
IOH = -70 mA (current limit)
V
mA
V
V
CL = 30 pF
16
ns
CL = 30 pF
16
ns
fCLK
Frequency on pin CLK
Operational
0
20
MHz
DC
Duty cycle(3)
CL = 30 pF
45
55
%
SR
Slew rate (rise and fall,
CL = 30 pF)
VCC = 5 V
0.2
VCC = 3 V or 1.8 V
0.12
V/ns
Card detection input (PRES pin)(4)
VIL
Input voltage low
-0.3
0.3
VDD(INTF)
V
VIH
Input voltage high
0.7
VDD(INTF)
VDD(INTF)
+ 0.3
V
VHYS
0.14
VDD(INTF)
Hysteresis
V
IIL
Input current low
0 < VIL < VDD(INTF)
5
A
IIH
Input current high
0 < VIH < VDD(INTF)
5
A
1. TA = 25 °C, VDD = 3.3 V, VDDP = 5 V, VDD(INTF) = 3.3 V, fXTAL = 10 MHz, unless otherwise noted.
2. With an internal 9 k pull-up resistor to VCC.
3. For rise and fall times and duty cycle definitions, see Figure 5 on page 18.
4. PRES is active low, with an internal current source of 1.25 A (pull-up) to VDD(INTF).
14/31
DocID024511 Rev 2
ST8034HN, ST8034HC
Electrical characteristics
Table 8. Microcontroller interface
Symbol
Parameter
Test conditions(1)
Min.
Typ.
Max.
Unit
200
ns
400
ns
Data lines to the microcontroller (I/OUC, AUX1UC, AUX2UC pins)(2)
tD
tW(PU)
Delay time
Falling edge on pin I/O to
falling edge on I/OUC or vice
versa
Pull-up pulse width
100
fIO
Input/output frequency
1
MHz
CI
Input capacitance
10
pF
VOL
Output voltage low
0
0.3
V
No load
0.9
VDD(INTF)
VDD(INTF)
+ 0.1
IOH  -40 A;
VDD(INTF) > 2 V
0.75
VDD(INTF)
VDD(INTF)
+ 0.1
IOH  -20 A;
VDD(INTF) < 2 V
0.75
VDD(INTF)
VDD(INTF)
+ 0.1
VOH
Output voltage high
IOL = 1 mA
V
VIL
Input voltage low
-0.3
0.3
VDD(INTF)
V
VIH
Input voltage high
0.7
VDD(INTF)
VDD(INTF)
+ 0.3
V
VHYS
0.14
VDD(INTF)
Hysteresis
I/OUC pin
V
IIL
Input current low
VIL = 0 V
500
A
IIH
Input current high
VIH = VDD(INTF)
10
A
12
k
RPU
Pull-up resistance to
VDD(INTF)
8
IPU
Pull-up current (one-shot
VOH = 0.9 VDD(INTF)
circuit active)
-1
tR(I)
Input rise time
VIL max. to VIH min.
0.15
s
tR(O)
Output rise time
CL  30 pF, 10% to 90%, 0 V
to VDD(INTF)
0.1
s
tF(I)
Input fall time
VIL max. to VIH min.
0.15
s
tF(O)
Output fall time
CL  30 pF, 10% to 90%, 0 V
to VDD(INTF)
0.1
s
10
mA
Device control inputs (CLKDIV1, CLKDIV2, RSTIN, VCC_SEL1, VCC_SEL2, CS pins)(3)
VIL
Input voltage low
-0.3
0.3
VDD(INTF)
V
VIH
Input voltage high
VDD(INTF)
VDD(INTF)
+ 0.3
V
VHYS
0.14
VDD(INTF)
Hysteresis
DocID024511 Rev 2
V
15/31
Electrical characteristics
ST8034HN, ST8034HC
Table 8. Microcontroller interface (continued)
Symbol
Parameter
Test conditions(1)
Min.
Typ.
Max.
Unit
IIL
Input current low
1
A
IIH
Input current high
1
A
(4)
Control input CMDVCC
VIL
Input voltage low
-0.3
0.3
VDD(INTF)
V
VIH
Input voltage high
0.7
VDD(INTF)
VDD(INTF)
+ 0.3
V
VHYS
0.14
VDD(INTF)
Hysteresis
V
IIL
Input current low
VIL = 0 V
1
A
IIH
Input current high
VIH = VDD(INTF)
1
A
100
Hz
0.3
V
fCMDVCC
Frequency at CMDVCC
pin
OFF output(5)
VOL
Output voltage low
IOL = 2 mA
VOH
Output voltage high
IOH = -15 A
RPU
Pull-up resistance to
VDD(INTF)
0
0.75
VDD(INTF)
16
V
20
24
k
1. TA = 25 °C, VDD = 3.3 V, VDDP = 5 V, VDD(INTF) = 3.3 V, fXTAL = 10 MHz, unless otherwise noted.
2. With an internal 10 k pull-up resistor to VDD(INTF).
3. For clock frequency division control (CLKDIV), see Table 12 on page 21.
4. CMDVCC is active low.
5. OFF is an NMOS open drain, with an internal 20 k pull-up resistor to VDD(INTF). The pull-up is connected only when used
(i.e. when OFF = high), otherwise disconnected.
16/31
DocID024511 Rev 2
ST8034HN, ST8034HC
Electrical characteristics
Table 9. Clock circuits
Symbol
Test conditions(1)
Parameter
Min.
Typ.
Max.
Unit
100
150
200
kHz
2
2.7
3.2
MHz
15
pF
2
26
MHz
0.032
26
MHz
Internal oscillator
fOSC(INT)LOW
fOSC(INT)
Shutdown mode
Internal oscillator frequency
Active state
Crystal oscillator (XTAL1 and XTAL2 pins)
CEXT
External capacitances
XTAL1 and XTAL2 to GND
(according to the crystal or
resonator specification)
fXTAL
External crystal frequency
Card clock reference,
crystal oscillator
fEXT
External clock frequency
External clock on XTAL1
tR(fEXT)
External clock frequency rise time External clock on XTAL1
10
ns
tF(fEXT)
External clock frequency fall time External clock on XTAL1
10
ns
VIL
Input voltage low
VIH
Input voltage high
Crystal oscillator
-0.3
0.3 VDD
External clock on XTAL1
-0.3
0.3
VDD(INTF)
0.7 VDD
VDD + 0.3
0.7
VDD(INTF)
+ 0.3
V
Max.
Unit
Crystal oscillator
External clock on XTAL1
VDD(INTF)
V
1. TA = 25 °C, VDD = 3.3 V, VDDP = 5 V, VDD(INTF) = 3.3 V, fXTAL = 10 MHz, unless otherwise noted.
Table 10. Protection characteristics
Symbol
IOLIM
Test conditions(1)
Parameter
Output current limit
(2)
ISD(VCC)
Limit and shutdown card supply
current
TSD
Shutdown junction temperature
Min.
Typ.
I/O pin
-15
15
CLK pin
-70
70
RST pin
-20
20
VCC pin
90
120
150
150
mA
mA
°C
1. TA = 25 °C, VDD = 3.3 V, VDDP = 5 V, VDD(INTF) = 3.3 V, fXTAL = 10 MHz, unless otherwise noted.
2. All card contacts are protected against short-circuit to any other card contact.
DocID024511 Rev 2
17/31
Electrical characteristics
ST8034HN, ST8034HC
Table 11. Timing characteristics
Symbol
tACT
tDEACT
tD(START),
tD(END)
Test conditions(1)
Parameter
Activation time
See Figure 10 on
page 24
2090
Deactivation time
See Figure 11 on
page 25
35
tD(START) = t3,
see Figure 10 on
Delay time, CLK sent to card using an page 24
external clock
=t ,
t
D(END)
5
see Figure 10 on
page 24
tDEB
Min.
Debounce time
PRES pin
Typ.
90
2090
Max.
Unit
4160
µs
250
µs
4112
µs
2120
3.2
4160
4.5
6.4
ms
1. TA = 25 °C, VDD = 3.3 V, VDDP = 5 V, VDD(INTF) = 3.3 V, fXTAL = 10 MHz, unless otherwise noted.
Figure 5. Definition of duty cycle and input and output rise/fall times
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Duty cycle (DC) = t1 / (t1 + t2).
18/31
DocID024511 Rev 2
ST8034HN, ST8034HC
6
Functional description
Functional description
Throughout this document it is assumed that the reader is familiar with ISO7816
terminology.
6.1
Power supplies
All interface signals to the host microcontroller are referenced to VDD(INTF). All card contacts
remain inactive during power-up or power-down. After powering up the device, OFF output
remains low until CMDVCC input is set high and PRES input is low. During power-down,
OFF output goes low when VDDP falls below the VDDP falling threshold voltage. The internal
oscillator clock frequency fOSC(INT) is used only during the activation sequence. When the
card is not activated (CMDVCC input is high), the internal oscillator is in low frequency
mode to reduce power consumption.
Power-on sequence: supply voltages may be applied to the ST8034 in any sequence.
6.2
Voltage supervisor
Figure 6. Voltage supervisor, configured with adjustable VDD(INTF) threshold
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DocID024511 Rev 2
19/31
Functional description
ST8034HN, ST8034HC
The voltage supervisor monitors the VDDP, VDD, and VDD(INTF) voltages and provides both
power-on reset (POR) and supply dropout detection during a card session. The supervisor
threshold voltages for VDDP and VDD are set internally, and VDD(INTF) is set externally by an
external resistor divider on the PORADJ pin, which provides additional voltage monitoring
flexibility (this pin can be used for monitoring any external voltage, with adjustable
threshold):
Undervoltage (UVLO) threshold adjustment on the PORADJ input with the resistor divider:
VDD(INTF) UVLO threshold (falling) = (R1+R2)/R2 x VTH(PORADJ)
VDD(INTF) UVLO threshold (rising) = (R1+R2)/R2 x (VTH(PORADJ) + VHYST(PORADJ))
If the external resistor divider is not used, connect the PORADJ pin to VDD(INTF), then
VDD(INTF) UVLO threshold = VTH(PORADJ).
As long as VDDP, VDD or VDD(INTF) is less than the corresponding VTH + VHYS, the device
remains inactive irrespective of the command line levels. After VDDP, VDD, and VDD(INTF)
has reached a level higher than the corresponding VTH + VHYS, the device still remains
inactive for the duration of tW, a defined reset pulse of approximately 8 ms (tW = 1024 x
1/fOSC(INT)LOW) when the output of the supervisor keeps the control logic in reset state. This
is used to maintain the device in shutdown mode during the supply voltage power-on, see
Figure 7. A deactivation sequence is performed when either VDD, VDDP or VDD(INTF) falls
below the corresponding VTH.
Figure 7. Voltage supervisor waveforms
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6.3
Clock circuits
The clock signal for the card (CLK output) is either provided by an external clock signal
connected to the XTAL1 pin or generated by a crystal connected between the XTAL1 and
XTAL2 pins. The ST8034 automatically detects if an external clock is connected to XTAL1,
which eliminates the need for a separate clock source selection pin. Automatic clock source
detection is performed on each activation command (falling edge of CMDVCC). The
presence of an external clock on the XTAL1 pin is checked during a time window defined by
the internal oscillator. If the external clock is detected, the crystal oscillator is stopped. If the
clock is not detected, the crystal oscillator is started. When the external clock is used, the
clock signal must be present on the XTAL1 pin before the CMDVCC falling edge. If the
external clock is used, connect it to XTAL1 input and leave the XTAL2 pin floating. The
XTAL1 pin can not be left floating, either a crystal or an external clock source needs to be
connected, or the XTAL1 pin needs to be grounded.
20/31
DocID024511 Rev 2
ST8034HN, ST8034HC
Functional description
Figure 8. External clock usage
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The clock frequency is selected by the CLKDIV1 and CLKDIV2 pins and is fXTAL, fXTAL/2,
fXTAL/4 or fXTAL/8 in the case of the ST8034HN or either fXTAL or fXTAL/2 in the case of the
ST8034HC, selected by the CLKDIV pin, see Table 12.
The frequency change is synchronous, meaning that after transition on the CLKDIV input,
the present clock period is completed and after that the new whole clock period starts,
therefore no clock period is shortened during the frequency switchover.
If an external crystal is used, the duty cycle on the CLK pin should be between 45% and
55%. If an external clock is connected to the XTAL1 pin, its duty cycle must be between 48%
and 52% so that the CLK output duty cycle is between 45% and 55%.
Table 12. Clock frequency selection
ST8034HN
CLKDIV1 pin level
CLKDIV2 pin level
CLK frequency
Low
Low
fXTAL/8
Low
High
fXTAL/4
High
High
fXTAL/2
High
Low
fXTAL
ST8034HC
6.4
CLKDIV pin level
CLK frequency
High
fXTAL/2
Low
fXTAL
Input and output circuits
When the I/O and I/OUC pins are pulled high by a 9 k resistor between I/O and VCC and/or
10 k resistor between I/OUC and VDD(INTF), both lines enter the idle state. The I/O pin is
referenced to VCC and the I/OUC pin to VDD(INTF), which allows operation at VCC level
different from VDD(INTF) level.
DocID024511 Rev 2
21/31
Functional description
ST8034HN, ST8034HC
The first side on which a falling edge occurs becomes the master. An anti-latch circuit
disables falling edge detection on the other side, making it the slave. After a time delay tD,
the logic 0 present on the master side is sent to the slave side. When the master side
returns logic 1, the slave side sends logic 1 during time delay (tW(PU)). After this sequence,
both master and slave sides return to their idle states.
The active pull-up feature (one-shot circuit) ensures fast low to high transitions, making the
ST8034 outputs capable of delivering more than 1 mA, up to an output voltage of 0.9 VCC, at
a load of 80 pF. At the end of the active pull-up pulse, the output voltage is dependent on the
internal pull-up resistor value and load current. The current sent to and received from the
card's I/O lines is limited to 15 mA at a maximum frequency of 1 MHz.
6.5
Shutdown mode
After a power-on reset, if CMDVCC is high, the ST8034 enters shutdown mode, ensuring
only the minimum number of circuits are active while the ST8034 waits for the
microcontroller to start a session.
22/31

All card contacts are inactive. The impedance between the contacts and GND is
approximately 200 

I/OUC, AUX1UC, AUX2UC pins are in high impedance with the 10 k pull-up resistor
connected to VDD(INTF)

The voltage generators are stopped

The voltage supervisor is active

The internal oscillator runs at its lowest frequency (fOSC(INT)LOW).
DocID024511 Rev 2
ST8034HN, ST8034HC
6.6
Functional description
Deep shutdown mode
When the smartcard reader is inactive, the ST8034HN and ST8034HC enter a deep
shutdown mode if the CMDVCC pin is forced high and the VCC_SEL1 and VCC_SEL2 pins
are low. In deep shutdown mode, all circuits are disabled and the OFF pin follows the status
of the PRES pin. Changing the status of either CMDVCC, VCC_SEL1 or VCC_SEL2 exits
the deep shutdown mode, see Figure 9.
Figure 9. Shutdown and deep shutdown mode activation and deactivation
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6.7
Activation sequence
The following device activation sequence is applied when using an external clock, also see
Figure 10:
1.
CMDVCC is pulled low (t0).
2.
The internal oscillator is triggered (t0).
3.
The internal oscillator changes to high frequency (t1).
4.
VCC rises from 0 V to 1.8 V or to 3 V or to 5 V on a controlled slope (t2).
5.
I/O, AUX1, AUX2 are driven high (t3).
6.
The clock on the CLK output is applied to the C3 contact (t4).
7.
RST is enabled (t5).
DocID024511 Rev 2
23/31
Functional description
ST8034HN, ST8034HC
Time delays

t1 = t0 + 384 × 1/fOSC(INT)LOW

t2 = t1

t3 (tD(START)) = t1 + 17T/2

t4 = driven by host microcontroller; > t3 and < t5

t5 (tD(END)) = t1 + 23T/2.
T = 64 x 1/fOSC(INT).
Figure 10. Activation sequence
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6.8
Deactivation sequence
When a session ends, the microcontroller sets CMDVCC high. The ST8034 device then
executes an automatic deactivation sequence by counting the sequencer back to the
inactive state (see Figure 11):
24/31
1.
RST goes low (t11).
2.
The clock is stopped, CLK is low (t12).
3.
I/O, AUX1, AUX2 are pulled low (t13).
4.
VCC falls to 0 V (t14). The deactivation sequence is completed when VCC reaches its
inactive state.
5.
VCC < 0.4 V (tDEACT).
6.
All card contacts become low impedance to GND. The I/OUC, AUX1UC and AUX2UC
pins remain pulled up to VDD(INTF) by the internal 10 k pull-up resistor.
7.
The internal oscillator returns to its low frequency mode.
DocID024511 Rev 2
ST8034HN, ST8034HC
Functional description
Time delays

t11 = t10 + 3T / 64

t12 = t11 + T / 2

t13 = t11 + T

t14 = t11 + 3T / 2

tDEACT = t11 + 3T / 2 + VCC fall time.
T = 64 x 1/fOSC(INT).
Figure 11. Deactivation sequence
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6.9
VCC generator
The LDO on the VCC output is capable of supplying up to 65 mA continuously at any
selected VCC value (5 V, 3 V or 1.8 V). This output is overcurrent protected by the current
limiter with a limit threshold value of 120 mA typ., with a glitch immunity allowing overcurrent
pulses up to 200 mA with duration up to several microseconds not causing a deactivation
(the average current value must stay below the specified current limit, see Table 6 on
page 11 and Table 10 on page 17).
A 100 nF capacitor (min.) with ESR < 350 m should be tied to GND near the VCC pin and
another low ESR 100 nF capacitor (min.) should be tied to GND also on the card side, near
the card reader contact C1.
DocID024511 Rev 2
25/31
Functional description
6.10
ST8034HN, ST8034HC
Fault detection
The fault conditions monitored by the device are:

Short-circuit or overcurrent on the VCC pin

Card removal during transaction

VDD falling

VDDP falling

VDD(INTF) falling

Overheating.
There are two different fault detection situations:

Outside card session (CMDVCC pin is high): the OFF pin is low if the card is not in the
reader and high if the card is in the reader. Any voltage drop on VDD, VDDP or VDD(INTF)
is detected by the voltage supervisor. This generates an internal power-on reset pulse
but does not act upon the OFF pin signal. The card is not powered-up and short-circuits
or overheating are not detected.

In card session (CMDVCC pin is low): when the OFF pin goes low, the fault detection
circuit triggers the automatic emergency deactivation sequence (see Figure 12).
On card insertion or removal, bouncing can occur on the card presence switch (i.e. on the
PRES signal). Therefore a debouncing feature is integrated into the ST8034 (4.5 ms
typically, tDEB = 640 × 1/fOSC(INT)LOW). See Figure 13.
On card insertion, the OFF pin goes high after the debounce time has elapsed. When the
card is extracted, the automatic card deactivation sequence is performed on the first high to
low transition on the PRES pin. After this, the OFF pin goes low.
Figure 12. Deactivation sequence after card removal
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DocID024511 Rev 2
ST8034HN, ST8034HC
Functional description
Figure 13. Debounce at OFF, CMDVCC, PRES and VCC pins
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1. Deactivation caused by card withdrawal.
2. Deactivation caused by short-circuit on card side.
6.11
VCC_SEL pin-programmed card supply voltage (VCC)
The card supply voltage (VCC) is selected by the VCC_SEL1 and VCC_SEL2 inputs, see
Table 13.
Table 13. VCC selection by VCC_SEL1, VCC_SEL2 pins
VCC_SEL1 pin level
VCC_SEL2 pin level
VCC
Low
x(1)
1.8 V
High
High
5V
High
Low
3V
1. x = “don't care”. However keep in mind that combination VCC_SEL1 = VCC_SEL2 = GND and CMDVCC =
high initiates deep shutdown mode.
6.12
Chip select (ST8034HC only)
The chip select (CS) input pin of the ST8034HC replaces the CLKDIV1 pin and is active
high, meaning normal operation of the device when CS is in logic high state. When the CS
pin goes low, the status of the ST8034HC device is frozen (i.e. status of control inputs
RSTIN, CMDVCC, CLKDIV, VCC_SEL1 and VCC_SEL2 is latched) and the I/OUC,
AUX1UC, and AUX2UC pins on the microcontroller interface go into high impedance mode
(with pull-up resistors to VDD(INTF)), not transferring any data to or from the card. The OFF
output pin also goes into high impedance mode. This allows the microcontroller to share
interface pins among multiple smartcard interfaces connected in parallel. Status and all the
ST8034HC device functions (including the card) are maintained for immediate use when the
CS goes high again. For this reason clock input is not affected by the chip select, the clock
is provided to the ST8034HC device and to the card even when the CS is low.
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Package information
7
ST8034HN, ST8034HC
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
Figure 14. QFN24 4 x 4 x 0.8 mm, 0.5 mm pitch package outline
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28/31
DocID024511 Rev 2
ST8034HN, ST8034HC
Package information
Table 14. QFN24 4 x 4 x 0.8 mm, 0.5 mm pitch package mechanical data(1), (2)
Dimensions (mm)
Symbol
Note
Min.
Typ.
Max.
A
0.80
0.90
1.00
A1
0.00
0.02
0.05
b
0.18
0.25
0.30
D
3.90
4.00
4.10
E
3.90
4.00
4.10
e
(3)
0.5 ref.
D2
1.95
2.10
2.20
E2
1.95
2.10
2.20
K
0.20
-
-
L
0.30
0.40
0.50
aaa
0.05
0.05
bbb
0.10
0.10
ccc
0.10
0.10
ddd
0.05
0.05
eee
0.08
0.08
1. Dimensioning and tolerancing conform to ASME Y14.5-2009.
2. The location of the terminal #1 identifier is within the hatched area.
3. Dimension b applies to metallized terminal. If the terminal has a radius on its end, dimension b should not
be measured in that radius area.
Figure 15. QFN24 recommended footprint
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Tape and reel information
8
ST8034HN, ST8034HC
Tape and reel information
Figure 16. Carrier tape for QFN24
“
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$
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%R
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1. 10 sprocket hole pitch cumulative tolerance  0.2.
2. Camber in compliance with EIA 481.
3. Pocket position relative to sprocket hole measured as true position of pocket, not pocket hole.
Table 15. Tape and reel specification for QFN24
Carrier tape
Quantity
per reel
3000
9
Cover tape
Lockreel 7 / 13"
Part no.
(vendor)
Description
Part no.
(vendor)
Description
Part no.
(vendor)
Description
434146 (Cpak)
Carrier tape
12 mm width,
8 mm pitch
437150 (Cpak)
Cover tape
9.2 mm width
434543 (peak)
13" lockreel
Revision history
Table 16. Document revision history
Date
Revision
22-Apr-2013
1
Initial release.
22-Oct-2013
2
Updated title on page 1 (removed ST8034HN and ST8034HC).
Updated Table 1 on page 5 (removed note 1).
Minor modifications throughout document.
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Changes
DocID024511 Rev 2
ST8034HN, ST8034HC
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