54VCXH162374
Rad hard low voltage CMOS 16-bit d-type flip-flop (3-state) with 3.6 V tolerant inputs and outputs
Features
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1.65 to 3.6 V inputs and outputs
High speed:
– t
PD
= 3.4 ns (Max.) at V
CC
= 3.0 to 3.6 V
– t
PD
= 4.8 ns (Max.) at V
CC
= 2.3 to 2.7 V
Symmetrical impedance outputs:
– |I
OH
| = I
OL
= 12 mA (Min.) at V
CC
= 3.0 V
– |I
OH
| = I
OL
= 8 mA (Min.) at V
CC
= 2.3 V
Power down protection on inputs and outputs
26
Ω serie resistors in outputs
Operating voltage range:
– V
CC
(Opr) = 1.65 V to 3.6 V
Pin and function compatible with 54 series
H162374
Bus hold provided on both sides
Cold spare function
Latch-up performance exceeds
300 mA (JESD 17)
ESD performance:
– HBM > 2000 V
(MIL STD 883 method 3015); MM > 200 V
300 KRad Mil1019.6 condition A, (RHA QML qualification extension undergone)
No SEL, no SEU and no SET under 110
Mev/cm2/mg LET heavy ions irradiation
QML qualified product
Device fully compliant with
DSCC SMD 5962-05212
100 mV typical input hysteresis
Flat-48
The upper metallic lid is not electrically connected to any pins, nor to the IC die inside the package.
Description
The 54VCXH162374 is a low voltage CMOS 16 bit d-type flip-flop with 3 state outputs non inverting fabricated with sub-micron silicon gate and five-layer metal wiring C²MOS technology. It is ideal for low power and very high speed 1.65 to
3.6 V applications; it can be interfaced to 3.6 V signal environment for both inputs and outputs.
These 16 bit d-type flip-flops are controlled by two clock inputs (nCK) and two output enable inputs
(nOE). On the positive transition of the (nCK), the nQ outputs will be set to the logic state that were setup at the nD inputs. While the (nOE) input is low, the 8 outputs (nQ) will be in a normal state
(HIGH or LOW logic level) and while high level the outputs will be in a high impedance state. Any output control does not affect the internal operation of flip flops; that is, the old data can be retained or the new data can be entered even while the outputs are OFF.
August 2011 Doc ID 10654 Rev 7 1/18
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Contents
Contents
3
54VCXH162374
Logic symbols and I/O equivalent circuit . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3
Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2/18 Doc ID 10654 Rev 7
54VCXH162374
1
Logic symbols and I/O equivalent circuit
Logic symbols and I/O equivalent circuit
Figure 1.
IEC logic symbols
Figure 2.
Input and output equivalent circuit
Doc ID 10654 Rev 7 3/18
Logic symbols and I/O equivalent circuit
Figure 3.
Logic diagram
54VCXH162374
Note: This logic diagram has not to be used to estimate propagation delays
4/18 Doc ID 10654 Rev 7
54VCXH162374
Figure 4.
Pin connection (top through view)
Pin settings
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6/18
Pin settings 54VCXH162374
Table 1.
Pin description
Pin n°
1
2, 3, 5, 6, 8, 9, 11, 12
13, 14, 16, 17, 19, 20, 22, 23
24
25
36, 35, 33, 32, 30, 29, 27, 26
47, 46, 44, 43, 41, 40, 38, 37
48
4, 10, 15, 21, 28, 34, 39, 45
7, 18, 31, 42
Symbol
1OE
1Q0 to 1Q7
2Q0 to 2Q7
2OE
2CK
2D0 to 2D7
1D0 to 1D7
1CK
GND
V
CC
Name and function
3 state output enable input
(Active LOW)
3-state outputs
3-state outputs
3 state output enable input
(Active LOW)
Clock input
Data inputs
Data inputs
Clock input
Ground (0 V)
Positive supply voltage
Note:
Table 2.
Truth table
Inputs
OE LE D
H
L
L
X X
X
L
L H
1.
Q outputs are latched at the time when the LE input is taken low logic level.
X = Do not care; Z = High impedance
Output
Q
Z
No change
(1)
L
H
Doc ID 10654 Rev 7
54VCXH162374 Maximum rating
3.1
Stressing the device above the rating listed in the “absolute maximum ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Table 3.
Symbol
Absolute maximum ratings
Parameter
V
CC
V
I
V
O
V
O
I
IK
I
OK
I
O
I
CC or
I
GND
P
D
T stg
T
L
Supply voltage
DC input voltage
DC output voltage (OFF state)
DC output voltage (high or low state)
DC input diode current
DC output diode current
DC output current
DC V
CC
(2)
(1)
or ground current per supply pin
Power dissipation
Storage temperature
Lead temperature (10 sec)
1.
I
O
absolute maximum rating must be observed
2.
V
O
< GND, V
O
> V
CC
Value
-0.5 to +4.6
-0.5 to +4.6
-0.5 to +4.6
-0.5 to V
CC
+ 0.5
- 50
- 50
± 50
± 100
400
-65 to +150
260 mA mW
°C
°C
Unit
V
V
V
V mA mA mA
Recommended operating conditions
Table 4.
Symbol
V
CC
V
I
V
O
V
O
I
OH
, I
OL
I
OH
, I
OL
T op dt/dv
Recommended operating conditions
Parameter
Supply voltage
Input voltage
Output voltage (OFF state)
Output voltage (high or low state)
High or low level output current (V
CC
= 3.0 to 3.6 V)
High or low level output current (V
CC
= 2.3 to 2.7 V)
Operating temperature
Input rise and fall time
(1)
1.
V
IN
from 0.8 V to 2 V at V
CC
= 3.0 V
Value
1.8 to 3.6
-0.3 to 3.6
0 to 3.6
0 to V
CC
± 12
± 8
-55 to 125
0 to 10
Unit
mA mA
°C ns/V
V
V
V
V
Doc ID 10654 Rev 7 7/18
8/18
Electrical characteristics 54VCXH162374
2.7 V < V
CC
< 3.6 V unless otherwise specified
Table 5.
DC specifications
Test condition Value
Symbol Parameter -55 to 125°C
V
CC
(V)
Min.
V
IH
V
IL
High level input voltage
Low level input voltage
2.7 to 3.6
V
V
I
I(HOLD)
I
I
I
ΔI
I
OH
OL
I off
OZ
CC
CC
High level output voltage
Low level output voltage
Input leakage current
Input hold current
2.7 to 3.6
2.7
3.0
2.7 to 3.6
2.7
3.0
2.7 to 3.6
3.0
3.6
I
O
=-100
μA
I
O
=-6 mA
I
O
=-8 mA
I
O
=-12 mA
I
O
=100
μA
I
O
=6 mA
I
O
=8 mA
I
O
=12 mA
V
I
= 0 to 3.6 V
V
I
= 0.8 V
V
I
= 2 V
V
I
= 0 to 3.6 V
Power off leakage current
0 V
I
or V
O
= 0 to 3.6 V
I
High impedance output leakage current
Quiescent supply current
CC
incr. per Input
2.7 to 3.6
2.7 to 3.6
2.7 to 3.6
V
I
= V
IH
or V
IL
V
O
= 0 to 3.6 V
V
I
= V
CC
or GND
V
I
or V
O
= V
CC
to 3.6 V
V
IH
= V
CC
- 0.6 V
2.0
V
CC
-0.2
2.2
2.4
2.2
75
-75
Max.
0.8
± 500
10
± 10
20
± 20
750
0.2
0.4
0.55
0.8
± 5
Unit
V
V
V
μA
μA
μA
μA
μA
μA
Doc ID 10654 Rev 7
54VCXH162374 Electrical characteristics
2.3 V < V
CC
< 2.7 V unless otherwise specified
Table 6.
DC specifications
Test condition
Symbol Parameter
V
CC
(V)
V
IH
V
IL
High level input voltage
Low level input voltage
2.3 to 2.7
V
OH
V
OL
I
I
I
I(HOLD)
High level output voltage
Low level output voltage
Input leakage current
Input hold current
2.3 to 2.7
2.3
2.3 to 2.7
2.3
2.3 to 2.7
2.3
I
O
=-100
μA
I
O
=-4 mA
I
O
=-6 mA
I
O
=-8 mA
I
O
=100
μA
I
O
=6 mA
I
O
=8 mA
V
I
= V
CC
or GND
V
I
= 0.7 V
V
I
= 1.7 V
I off
Power Off leakage current
0 V
I
or V
O
= 0 to 3.6 V
I
OZ
I
CC
High impedance output leakage current
Quixent
2.3 to 2.7
2.3 to 2.7
V
I
= V
IH
or V
IL
V
O
= 0 to 3.6 V
V
I
= V
CC
or GND
V
I
or V
O
=
V
CC
to 3.6 V
T
A
= 25 °C, Input t r
= t f
= 2.0 ns, C
L
= 30 pF, R
L
= 500
Ω
Table 7.
Dynamic switching characteristics
Test condition
Value
-55 to 125°C
Min.
1.6
Max.
0.7
V
CC
-0.2
2.0
1.8
1.7
0.2
0.4
0.6
± 5
45
-45
10
± 10
20
± 20
Unit
V
V
V
μA
μA
μA
μA
μA
Value
Symbol Parameter
V
CC
(V)
T
A
= 25 °C Unit
Min.
Typ.
Max.
V
V
V
OLV
OHV
OHV
Dynamic valley low voltage quiet output
(1)
Dynamic valley high voltage quiet output
Dynamic valley high voltage quiet output
(2)
(2) (3)
(2) (3)
2.5
3.3
2.5
3.3
2.5
3.3
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
= 0 V
= V
CC
= 0 V
= V
= 0 V
= V
CC
CC
-
-
-
-
-
0.25
0.35
-0.25
-0.35
2.05
2.65
1.
Number of outputs defined as “n”. Measured with “n-1” outputs switching from HIGH to LOW or LOW to
HIGH. The remaining output is measured in the LOW state.
2.
Parameters guaranteed by design.
3.
Number of outputs defined as “n”. Measured with “n-1” outputs switching from HIGH to LOW or LOW to
HIGH. The remaining output is measured in the HIGH state.
-
-
-
-
-
-
V
V
V
Doc ID 10654 Rev 7 9/18
Electrical characteristics 54VCXH162374
C
L
= 30 pF, R
L
= 500
Ω, Input t r
= t f
= 2.0 ns
Table 8.
AC electrical characteristics
Test condition Value
Symbol Parameter -55 to 125 °C Unit
V
CC
(V)
Min.
Max.
t
PLH
t
PHL t
PLH
t
PHL t
PZL
t
PZH t
PLZ
t
PHZ t s t h t w
Propagation delay time Dn to Qn
Propagation delay time LE to Qn
Output enable time
Output disable time
Setup tIme, HIGH or
LOW level Dn to LE
Hold time High or
LOW level Dn to LE
LE pulse width, HIGH
2.3 to 2.7
3.0 to 3.6
2.3 to 2.7
3.0 to 3.6
2.3 to 2.7
3.0 to 3.6
2.3 to 2.7
3.0 to 3.6
2.3 to 2.7
3.0 to 3.6
2.3 to 2.7
3.0 to 3.6
2.3 to 2.7
3.0 to 3.6
2.3 to 2.7
3.0 to 3.6
1.0
1.5
1.5
1.5
1.5
190
235
1.0
0.8
1.0
0.8
1.0
0.8
1.0
5.5
4.5
6.2
4.5
5.1
4.6
ns ns ns ns ns ns ns t
OSLH
t
OSHL
Output to output skew time
(1) (2)
0.5
0.5
ns
1.
Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switching in the same direction, either HIGH or LOW (t
OSLH
= | t
PLHm
- t
PLHn
|, t
OSHL
= | t
PHLm
- t
PHLn
|)
2.
Parameter guaranteed by design
Table 9.
Capacitive characteristics
Test condition Value
Symbol Parameter
V
CC
(V)
T
A
= 25 °C
Min.
Typ.
Max.
Unit
C
C
C
IN
OUT
PD
Input capacitance
Output capacitance
Power dissipation capacitance
(1)
2.5 or 3.3
V
IN
= 0 or V
CC
2.5 or 3.3
V
IN
= 0 or V
CC
2.5 or 3.3
f
IN
= 10MHz
V
IN
= 0 or V
CC
-
-
6
7
20 -
-
-
1.
C
PD
is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
/16 (per circuit) pF pF pF
10/18 Doc ID 10654 Rev 7
54VCXH162374
Figure 5.
Test circuit
Test circuit
Table 10.
Test circuit
Test
t
PLH
, t
PHL t
PZL
, t
PLZ
(V
CC
= 3.0 to 3.6 V) t
PZL
, t
PLZ
(V
CC
= 2.3 to 2.7 V) t
PZH
, t
PHZ
C
L
= 30 pF or equivalent (includes jig and probe capacitance)
R
L
= R
1
= 500
Ω
or equivalent
R
T
= Z
OUT
of pulse generator (typically 50
Ω
)
Switch
Open
6 V
2 V
CC
GND
Doc ID 10654 Rev 7 11/18
Waveforms
6 Waveforms
54VCXH162374
Table 11.
Waveform symbol value
V
CC
Symbol
V
IH
V
M
V
X
V
Y
3.0 to 3.6 V
2.7 V
1.5 V
V
OL
+0.3 V
V
OH
-0.3 V
2.3 to 2.7 V
V
CC
V
CC
/2
V
OL
+0.15 V
V
OH
-0.15 V
Figure 6.
Waveform - nCK TO Qn propagation delays, nCK maximum frequency, Dn
TO nCK setup and hold times (f = 1 MHz; 50% duty cycle)
12/18 Doc ID 10654 Rev 7
54VCXH162374 Waveforms
Figure 7.
Waveform - output enable and disable time (f = 1 MHz; 50% duty cycle)
Figure 8.
Waveform - nCK minimum pulse width (f = 1 MHz; 50% duty cycle)
Doc ID 10654 Rev 7 13/18
Package mechanical data
7 Package mechanical data
54VCXH162374
54VCXH162374 products are supplied into ceramic body / metal lid hermetic Flat 48-pin space package.
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
® specifications, grade definitions and product status are available at:
www.st.com
.
ECOPACK
®
is an ST trademark.
Table 12.
Flat-48 (MIL-STD-1835) mechanical data mm
Dim.
Min.
Typ.
Max.
Min.
inch
Typ.
Max.
e 0.635 f 0.20
0.025
0.008
14/18 Doc ID 10654 Rev 7
54VCXH162374
Figure 9.
Package dimension
Package mechanical data
Note:
7330585B
The upper metallic lid is not electrically connected to any pins, nor to the IC die inside the package. Connecting unused pins or metal lid to ground or to the power supply will not affect the electrical characteristics.
Doc ID 10654 Rev 7 15/18
Order codes 54VCXH162374
Table 13.
Ordering information
Package
Min op. voltage
Lead finish
Radiation level
Flight models
Engineering model Packing
QML-V
48-pin flat 1.8 V Gold plated 300 krad RHFXH162374K03V RHRXH162374K1 Conductive strip pack
16/18 Doc ID 10654 Rev 7
54VCXH162374 Revision history
Table 14.
Document revision history
Date Revision
09-Jul-2004
17-May-2005
19-Jun-2006
25-Jul-2007
17-Sep-2008
23-Sep-2009
02-Aug-2011
4
5
6
1
2
3
7
Changes
First release.
SMD qualified.
300 Krad bullet updated, new template, mechanical data updated
Typo in
Table 12 on page 14
.
Updated cover page
Updated
Table 13 on page 16
Added
Note: on page 15
and in the "Pin connections" diagram on the coverpage
Doc ID 10654 Rev 7 17/18
54VCXH162374
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18/18 Doc ID 10654 Rev 7
